| /aosp_15_r20/external/armnn/samples/SpeechRecognition/src/ |
| H A D | Decoder.cpp | 8 namespace asr namespace
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| H A D | SpeechRecognitionPipeline.cpp | 9 namespace asr namespace
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| /aosp_15_r20/external/armnn/samples/SpeechRecognition/include/ |
| H A D | Decoder.hpp | 14 namespace asr namespace
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| H A D | SpeechRecognitionPipeline.hpp | 13 namespace asr namespace
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| /aosp_15_r20/external/skia/tools/gpu/ |
| H A D | TestContext.cpp | 32 auto asr = SkScopeExit(this->onPlatformGetAutoContextRestore()); in makeCurrentAndAutoRestore() local
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| /aosp_15_r20/external/vixl/test/aarch64/ |
| H A D | test-api-movprfx-aarch64.cc | 118 __ asr(z2.VnS(), p2.Merging(), z2.VnS(), z2.VnS()); in TEST() local
121 __ asr(z10.VnH(), p2.Merging(), z10.VnH(), z10.VnD()); in TEST() local
124 __ asr(z17.VnD(), p5.Merging(), z17.VnD(), z17.VnD()); in TEST() local
689 __ asr(z26.VnB(), p5.Merging(), z26.VnB(), 3); in TEST() local
692 __ asr(z25.VnH(), p7.Merging(), z25.VnH(), z14.VnH()); in TEST() local
695 __ asr(z12.VnH(), p7.Merging(), z12.VnH(), z23.VnD()); in TEST() local
698 __ asr(z3.VnD(), p4.Merging(), z3.VnD(), z15.VnD()); in TEST() local
1356 __ asr(z24.VnD(), p5.Merging(), z24.VnD(), 3); in TEST() local
1359 __ asr(z1.VnH(), p3.Merging(), z1.VnH(), z4.VnH()); in TEST() local
1362 __ asr(z0.VnB(), p7.Merging(), z0.VnB(), z28.VnD()); in TEST() local
[all …]
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| H A D | test-trace-aarch64.cc | 69 __ asr(w11, w12, 0); in GenerateTestSequenceBase() local
70 __ asr(x13, x14, 1); in GenerateTestSequenceBase() local
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| /aosp_15_r20/external/coreboot/src/include/device/dram/ |
| H A D | ddr3.h | 90 unsigned int asr:1; member
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| /aosp_15_r20/external/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 29 asr, enumerator
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 29 asr, enumerator
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 29 asr, enumerator
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| /aosp_15_r20/hardware/google/gfxstream/third-party/astc-encoder/Source/ |
| D | astcenc_vecmathlib_none_4.h | 567 template <int s> ASTCENC_SIMD_INLINE vint4 asr(vint4 a) in asr() function
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| D | astcenc_vecmathlib_neon_4.h | 526 template <int s> ASTCENC_SIMD_INLINE vint4 asr(vint4 a) in asr() function
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| D | astcenc_vecmathlib_sse_4.h | 548 template <int s> ASTCENC_SIMD_INLINE vint4 asr(vint4 a) in asr() function
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| D | astcenc_vecmathlib_avx2_8.h | 479 template <int s> ASTCENC_SIMD_INLINE vint8 asr(vint8 a) in asr() function
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| /aosp_15_r20/external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 788 void asr(const Register& rd, const Register& rn, unsigned shift) { in asr() function
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| H A D | assembler-sve-aarch64.cc | 178 void Assembler::asr(const ZRegister& zd, in asr() function in vixl::aarch64::Assembler
195 void Assembler::asr(const ZRegister& zd, in asr() function in vixl::aarch64::Assembler
389 void Assembler::asr(const ZRegister& zd, const ZRegister& zn, int shift) { in asr() function in vixl::aarch64::Assembler
397 void Assembler::asr(const ZRegister& zd, in asr() function in vixl::aarch64::Assembler
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| /aosp_15_r20/prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| D | inst.go | 411 asr const
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| /aosp_15_r20/hardware/google/gfxstream/third-party/astc-encoder/Source/UnitTest/ |
| D | test_simd.cpp | 1564 TEST(vint4, asr) in TEST() argument
3173 TEST(vint8, asr) in TEST() argument
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| /aosp_15_r20/external/vixl/benchmarks/aarch32/ |
| H A D | asm-disasm-speed-test.cc | 4796 __ asr(lr, lr, 3U); in Generate_36() local
5296 __ asr(ip, lr, 3U); in Generate_40() local
5391 __ asr(r8, r8, 1U); in Generate_41() local
5509 __ asr(r8, r8, 1U); in Generate_42() local
5555 __ asr(fp, r1, 3U); in Generate_42() local
5561 __ asr(fp, ip, 1U); in Generate_42() local
5876 __ asr(sl, r9, 3U); in Generate_45() local
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| /aosp_15_r20/external/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 2015 void asr(Register rd, Register rm, const Operand& operand) { in asr() function
2018 void asr(Condition cond, Register rd, Register rm, const Operand& operand) { in asr() function
2021 void asr(EncodingSize size, in asr() function
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| H A D | assembler-aarch32.cc | 2873 void Assembler::asr(Condition cond, in asr() function in vixl::aarch32::Assembler
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| H A D | disasm-aarch32.cc | 1245 void Disassembler::asr(Condition cond, in asr() function in vixl::aarch32::Disassembler
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| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceAssemblerARM32.cpp | 1729 void AssemblerARM32::asr(const Operand *OpRd, const Operand *OpRm, in asr() function in Ice::ARM32::AssemblerARM32
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| /aosp_15_r20/art/compiler/optimizing/ |
| H A D | code_generator_arm_vixl.cc | 5598 __ asr(pl, o_l, high, temp); in HandleShift() local
|