1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17 #include <linux/kvm_host.h>
18
19 #include <asm/cpufeature.h>
20 #include <asm/debugreg.h>
21 #include <asm/hardirq.h>
22 #include <asm/intel-family.h>
23 #include <asm/intel_pt.h>
24 #include <asm/apic.h>
25 #include <asm/cpu_device_id.h>
26
27 #include "../perf_event.h"
28
29 /*
30 * Intel PerfMon, used on Core and later.
31 */
32 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
33 {
34 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
35 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
36 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
37 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
38 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
39 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
40 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
41 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
42 };
43
44 static struct event_constraint intel_core_event_constraints[] __read_mostly =
45 {
46 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
47 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
48 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
49 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
50 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
51 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
52 EVENT_CONSTRAINT_END
53 };
54
55 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
56 {
57 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
58 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
59 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
60 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
61 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
62 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
63 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
64 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
65 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
66 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
67 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
68 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
69 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
70 EVENT_CONSTRAINT_END
71 };
72
73 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
74 {
75 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
76 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
77 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
78 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
79 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
80 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
81 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
82 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
83 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
84 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
85 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
86 EVENT_CONSTRAINT_END
87 };
88
89 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
90 {
91 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
92 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
93 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
94 EVENT_EXTRA_END
95 };
96
97 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
98 {
99 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
101 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
102 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
103 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
104 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
105 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
106 EVENT_CONSTRAINT_END
107 };
108
109 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
110 {
111 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
112 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
113 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
115 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
118 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
119 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
120 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
121 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
122 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
123
124 /*
125 * When HT is off these events can only run on the bottom 4 counters
126 * When HT is on, they are impacted by the HT bug and require EXCL access
127 */
128 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
130 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
131 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
132
133 EVENT_CONSTRAINT_END
134 };
135
136 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
137 {
138 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
139 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
140 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
141 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
142 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
143 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
144 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
146 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
149 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
150 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
151
152 /*
153 * When HT is off these events can only run on the bottom 4 counters
154 * When HT is on, they are impacted by the HT bug and require EXCL access
155 */
156 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
158 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
159 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
160
161 EVENT_CONSTRAINT_END
162 };
163
164 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
165 {
166 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
167 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
168 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
169 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
170 EVENT_EXTRA_END
171 };
172
173 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
174 {
175 EVENT_CONSTRAINT_END
176 };
177
178 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
179 {
180 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
181 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
182 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
183 EVENT_CONSTRAINT_END
184 };
185
186 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
187 {
188 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
189 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
190 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
191 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
192 FIXED_EVENT_CONSTRAINT(0x0500, 4),
193 FIXED_EVENT_CONSTRAINT(0x0600, 5),
194 FIXED_EVENT_CONSTRAINT(0x0700, 6),
195 FIXED_EVENT_CONSTRAINT(0x0800, 7),
196 FIXED_EVENT_CONSTRAINT(0x0900, 8),
197 FIXED_EVENT_CONSTRAINT(0x0a00, 9),
198 FIXED_EVENT_CONSTRAINT(0x0b00, 10),
199 FIXED_EVENT_CONSTRAINT(0x0c00, 11),
200 FIXED_EVENT_CONSTRAINT(0x0d00, 12),
201 FIXED_EVENT_CONSTRAINT(0x0e00, 13),
202 FIXED_EVENT_CONSTRAINT(0x0f00, 14),
203 FIXED_EVENT_CONSTRAINT(0x1000, 15),
204 EVENT_CONSTRAINT_END
205 };
206
207 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
208 {
209 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
210 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
211 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
212 EVENT_CONSTRAINT_END
213 };
214
215 static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
216 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
217 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
218 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
219 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
220 EVENT_CONSTRAINT_END
221 };
222
223 static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
224 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
225 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
226 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
227 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
228 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
229 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
230 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
231 EVENT_CONSTRAINT_END
232 };
233
234 static struct event_constraint intel_skl_event_constraints[] = {
235 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
236 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
237 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
238 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
239
240 /*
241 * when HT is off, these can only run on the bottom 4 counters
242 */
243 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
244 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
245 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
246 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
247 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
248
249 EVENT_CONSTRAINT_END
250 };
251
252 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
253 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
254 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
255 EVENT_EXTRA_END
256 };
257
258 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
259 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
260 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
261 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
262 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
263 EVENT_EXTRA_END
264 };
265
266 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
267 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
268 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
269 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
270 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
271 EVENT_EXTRA_END
272 };
273
274 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
275 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
276 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
277 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
278 /*
279 * Note the low 8 bits eventsel code is not a continuous field, containing
280 * some #GPing bits. These are masked out.
281 */
282 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
283 EVENT_EXTRA_END
284 };
285
286 static struct event_constraint intel_icl_event_constraints[] = {
287 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
288 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
289 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
290 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
291 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
292 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
293 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
297 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
298 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
299 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
300 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
301 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
302 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
303 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
304 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
305 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
306 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
307 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
308 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
309 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
310 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
311 EVENT_CONSTRAINT_END
312 };
313
314 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
315 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
316 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
317 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
318 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
319 EVENT_EXTRA_END
320 };
321
322 static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
323 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
324 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
325 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
326 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
327 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
328 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
329 EVENT_EXTRA_END
330 };
331
332 static struct event_constraint intel_glc_event_constraints[] = {
333 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
334 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
335 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
336 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
337 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
338 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
339 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
340 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
341 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
342 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
343 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
344 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
345 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
346 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
347
348 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
349 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
350 /*
351 * Generally event codes < 0x90 are restricted to counters 0-3.
352 * The 0x2E and 0x3C are exception, which has no restriction.
353 */
354 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
355
356 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
357 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
358 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
359 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
360 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
361 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
362 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
363 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
364 /*
365 * Generally event codes >= 0x90 are likely to have no restrictions.
366 * The exception are defined as above.
367 */
368 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
369
370 EVENT_CONSTRAINT_END
371 };
372
373 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
374 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
375 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
376 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
377 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
378 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
379 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
380 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
381 EVENT_EXTRA_END
382 };
383
384 static struct event_constraint intel_lnc_event_constraints[] = {
385 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
386 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
387 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
388 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
389 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
390 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
391 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
392 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
393 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
394 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
395 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
396 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
397 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
398 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
399
400 INTEL_EVENT_CONSTRAINT(0x20, 0xf),
401
402 INTEL_UEVENT_CONSTRAINT(0x012a, 0xf),
403 INTEL_UEVENT_CONSTRAINT(0x012b, 0xf),
404 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
405 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
406
407 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff),
408 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff),
409
410 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
411 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
412 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
413 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
414 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1),
415 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
416 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
417 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
418
419 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
420
421 INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf),
422
423 EVENT_CONSTRAINT_END
424 };
425
426 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
427 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0),
428 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1),
429 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
430 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
431 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
432 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
433 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
434 EVENT_EXTRA_END
435 };
436
437 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
438 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
439 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
440
441 static struct attribute *nhm_mem_events_attrs[] = {
442 EVENT_PTR(mem_ld_nhm),
443 NULL,
444 };
445
446 /*
447 * topdown events for Intel Core CPUs.
448 *
449 * The events are all in slots, which is a free slot in a 4 wide
450 * pipeline. Some events are already reported in slots, for cycle
451 * events we multiply by the pipeline width (4).
452 *
453 * With Hyper Threading on, topdown metrics are either summed or averaged
454 * between the threads of a core: (count_t0 + count_t1).
455 *
456 * For the average case the metric is always scaled to pipeline width,
457 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
458 */
459
460 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
461 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
462 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
463 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
464 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
465 "event=0xe,umask=0x1"); /* uops_issued.any */
466 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
467 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
468 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
469 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
470 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
471 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
472 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
473 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
474 "4", "2");
475
476 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
477 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
478 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
479 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
480 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
481 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
482 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
483 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
484 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
485
486 static struct attribute *snb_events_attrs[] = {
487 EVENT_PTR(td_slots_issued),
488 EVENT_PTR(td_slots_retired),
489 EVENT_PTR(td_fetch_bubbles),
490 EVENT_PTR(td_total_slots),
491 EVENT_PTR(td_total_slots_scale),
492 EVENT_PTR(td_recovery_bubbles),
493 EVENT_PTR(td_recovery_bubbles_scale),
494 NULL,
495 };
496
497 static struct attribute *snb_mem_events_attrs[] = {
498 EVENT_PTR(mem_ld_snb),
499 EVENT_PTR(mem_st_snb),
500 NULL,
501 };
502
503 static struct event_constraint intel_hsw_event_constraints[] = {
504 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
505 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
506 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
507 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
508 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
509 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
510 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
511 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
512 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
513 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
514 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
515 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
516
517 /*
518 * When HT is off these events can only run on the bottom 4 counters
519 * When HT is on, they are impacted by the HT bug and require EXCL access
520 */
521 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
522 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
523 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
524 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
525
526 EVENT_CONSTRAINT_END
527 };
528
529 static struct event_constraint intel_bdw_event_constraints[] = {
530 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
531 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
532 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
533 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
534 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
535 /*
536 * when HT is off, these can only run on the bottom 4 counters
537 */
538 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
539 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
540 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
541 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
542 EVENT_CONSTRAINT_END
543 };
544
intel_pmu_event_map(int hw_event)545 static u64 intel_pmu_event_map(int hw_event)
546 {
547 return intel_perfmon_event_map[hw_event];
548 }
549
550 static __initconst const u64 glc_hw_cache_event_ids
551 [PERF_COUNT_HW_CACHE_MAX]
552 [PERF_COUNT_HW_CACHE_OP_MAX]
553 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
554 {
555 [ C(L1D ) ] = {
556 [ C(OP_READ) ] = {
557 [ C(RESULT_ACCESS) ] = 0x81d0,
558 [ C(RESULT_MISS) ] = 0xe124,
559 },
560 [ C(OP_WRITE) ] = {
561 [ C(RESULT_ACCESS) ] = 0x82d0,
562 },
563 },
564 [ C(L1I ) ] = {
565 [ C(OP_READ) ] = {
566 [ C(RESULT_MISS) ] = 0xe424,
567 },
568 [ C(OP_WRITE) ] = {
569 [ C(RESULT_ACCESS) ] = -1,
570 [ C(RESULT_MISS) ] = -1,
571 },
572 },
573 [ C(LL ) ] = {
574 [ C(OP_READ) ] = {
575 [ C(RESULT_ACCESS) ] = 0x12a,
576 [ C(RESULT_MISS) ] = 0x12a,
577 },
578 [ C(OP_WRITE) ] = {
579 [ C(RESULT_ACCESS) ] = 0x12a,
580 [ C(RESULT_MISS) ] = 0x12a,
581 },
582 },
583 [ C(DTLB) ] = {
584 [ C(OP_READ) ] = {
585 [ C(RESULT_ACCESS) ] = 0x81d0,
586 [ C(RESULT_MISS) ] = 0xe12,
587 },
588 [ C(OP_WRITE) ] = {
589 [ C(RESULT_ACCESS) ] = 0x82d0,
590 [ C(RESULT_MISS) ] = 0xe13,
591 },
592 },
593 [ C(ITLB) ] = {
594 [ C(OP_READ) ] = {
595 [ C(RESULT_ACCESS) ] = -1,
596 [ C(RESULT_MISS) ] = 0xe11,
597 },
598 [ C(OP_WRITE) ] = {
599 [ C(RESULT_ACCESS) ] = -1,
600 [ C(RESULT_MISS) ] = -1,
601 },
602 [ C(OP_PREFETCH) ] = {
603 [ C(RESULT_ACCESS) ] = -1,
604 [ C(RESULT_MISS) ] = -1,
605 },
606 },
607 [ C(BPU ) ] = {
608 [ C(OP_READ) ] = {
609 [ C(RESULT_ACCESS) ] = 0x4c4,
610 [ C(RESULT_MISS) ] = 0x4c5,
611 },
612 [ C(OP_WRITE) ] = {
613 [ C(RESULT_ACCESS) ] = -1,
614 [ C(RESULT_MISS) ] = -1,
615 },
616 [ C(OP_PREFETCH) ] = {
617 [ C(RESULT_ACCESS) ] = -1,
618 [ C(RESULT_MISS) ] = -1,
619 },
620 },
621 [ C(NODE) ] = {
622 [ C(OP_READ) ] = {
623 [ C(RESULT_ACCESS) ] = 0x12a,
624 [ C(RESULT_MISS) ] = 0x12a,
625 },
626 },
627 };
628
629 static __initconst const u64 glc_hw_cache_extra_regs
630 [PERF_COUNT_HW_CACHE_MAX]
631 [PERF_COUNT_HW_CACHE_OP_MAX]
632 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
633 {
634 [ C(LL ) ] = {
635 [ C(OP_READ) ] = {
636 [ C(RESULT_ACCESS) ] = 0x10001,
637 [ C(RESULT_MISS) ] = 0x3fbfc00001,
638 },
639 [ C(OP_WRITE) ] = {
640 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
641 [ C(RESULT_MISS) ] = 0x3f3fc00002,
642 },
643 },
644 [ C(NODE) ] = {
645 [ C(OP_READ) ] = {
646 [ C(RESULT_ACCESS) ] = 0x10c000001,
647 [ C(RESULT_MISS) ] = 0x3fb3000001,
648 },
649 },
650 };
651
652 /*
653 * Notes on the events:
654 * - data reads do not include code reads (comparable to earlier tables)
655 * - data counts include speculative execution (except L1 write, dtlb, bpu)
656 * - remote node access includes remote memory, remote cache, remote mmio.
657 * - prefetches are not included in the counts.
658 * - icache miss does not include decoded icache
659 */
660
661 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
662 #define SKL_DEMAND_RFO BIT_ULL(1)
663 #define SKL_ANY_RESPONSE BIT_ULL(16)
664 #define SKL_SUPPLIER_NONE BIT_ULL(17)
665 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
666 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
667 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
668 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
669 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
670 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
671 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
672 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
673 #define SKL_SPL_HIT BIT_ULL(30)
674 #define SKL_SNOOP_NONE BIT_ULL(31)
675 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
676 #define SKL_SNOOP_MISS BIT_ULL(33)
677 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
678 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
679 #define SKL_SNOOP_HITM BIT_ULL(36)
680 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
681 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
682 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
683 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
684 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
685 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
686 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
687 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
688 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
689 SKL_SNOOP_HITM|SKL_SPL_HIT)
690 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
691 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
692 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
693 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
694 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
695
696 static __initconst const u64 skl_hw_cache_event_ids
697 [PERF_COUNT_HW_CACHE_MAX]
698 [PERF_COUNT_HW_CACHE_OP_MAX]
699 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
700 {
701 [ C(L1D ) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
704 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
705 },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
708 [ C(RESULT_MISS) ] = 0x0,
709 },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = 0x0,
712 [ C(RESULT_MISS) ] = 0x0,
713 },
714 },
715 [ C(L1I ) ] = {
716 [ C(OP_READ) ] = {
717 [ C(RESULT_ACCESS) ] = 0x0,
718 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
719 },
720 [ C(OP_WRITE) ] = {
721 [ C(RESULT_ACCESS) ] = -1,
722 [ C(RESULT_MISS) ] = -1,
723 },
724 [ C(OP_PREFETCH) ] = {
725 [ C(RESULT_ACCESS) ] = 0x0,
726 [ C(RESULT_MISS) ] = 0x0,
727 },
728 },
729 [ C(LL ) ] = {
730 [ C(OP_READ) ] = {
731 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
732 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
733 },
734 [ C(OP_WRITE) ] = {
735 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
736 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
737 },
738 [ C(OP_PREFETCH) ] = {
739 [ C(RESULT_ACCESS) ] = 0x0,
740 [ C(RESULT_MISS) ] = 0x0,
741 },
742 },
743 [ C(DTLB) ] = {
744 [ C(OP_READ) ] = {
745 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
746 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
747 },
748 [ C(OP_WRITE) ] = {
749 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
750 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
751 },
752 [ C(OP_PREFETCH) ] = {
753 [ C(RESULT_ACCESS) ] = 0x0,
754 [ C(RESULT_MISS) ] = 0x0,
755 },
756 },
757 [ C(ITLB) ] = {
758 [ C(OP_READ) ] = {
759 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
760 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
761 },
762 [ C(OP_WRITE) ] = {
763 [ C(RESULT_ACCESS) ] = -1,
764 [ C(RESULT_MISS) ] = -1,
765 },
766 [ C(OP_PREFETCH) ] = {
767 [ C(RESULT_ACCESS) ] = -1,
768 [ C(RESULT_MISS) ] = -1,
769 },
770 },
771 [ C(BPU ) ] = {
772 [ C(OP_READ) ] = {
773 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
774 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
775 },
776 [ C(OP_WRITE) ] = {
777 [ C(RESULT_ACCESS) ] = -1,
778 [ C(RESULT_MISS) ] = -1,
779 },
780 [ C(OP_PREFETCH) ] = {
781 [ C(RESULT_ACCESS) ] = -1,
782 [ C(RESULT_MISS) ] = -1,
783 },
784 },
785 [ C(NODE) ] = {
786 [ C(OP_READ) ] = {
787 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
788 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
789 },
790 [ C(OP_WRITE) ] = {
791 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
792 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
793 },
794 [ C(OP_PREFETCH) ] = {
795 [ C(RESULT_ACCESS) ] = 0x0,
796 [ C(RESULT_MISS) ] = 0x0,
797 },
798 },
799 };
800
801 static __initconst const u64 skl_hw_cache_extra_regs
802 [PERF_COUNT_HW_CACHE_MAX]
803 [PERF_COUNT_HW_CACHE_OP_MAX]
804 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
805 {
806 [ C(LL ) ] = {
807 [ C(OP_READ) ] = {
808 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
809 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
810 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
811 SKL_L3_MISS|SKL_ANY_SNOOP|
812 SKL_SUPPLIER_NONE,
813 },
814 [ C(OP_WRITE) ] = {
815 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
816 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
817 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
818 SKL_L3_MISS|SKL_ANY_SNOOP|
819 SKL_SUPPLIER_NONE,
820 },
821 [ C(OP_PREFETCH) ] = {
822 [ C(RESULT_ACCESS) ] = 0x0,
823 [ C(RESULT_MISS) ] = 0x0,
824 },
825 },
826 [ C(NODE) ] = {
827 [ C(OP_READ) ] = {
828 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
829 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
830 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
831 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
832 },
833 [ C(OP_WRITE) ] = {
834 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
835 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
836 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
837 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
838 },
839 [ C(OP_PREFETCH) ] = {
840 [ C(RESULT_ACCESS) ] = 0x0,
841 [ C(RESULT_MISS) ] = 0x0,
842 },
843 },
844 };
845
846 #define SNB_DMND_DATA_RD (1ULL << 0)
847 #define SNB_DMND_RFO (1ULL << 1)
848 #define SNB_DMND_IFETCH (1ULL << 2)
849 #define SNB_DMND_WB (1ULL << 3)
850 #define SNB_PF_DATA_RD (1ULL << 4)
851 #define SNB_PF_RFO (1ULL << 5)
852 #define SNB_PF_IFETCH (1ULL << 6)
853 #define SNB_LLC_DATA_RD (1ULL << 7)
854 #define SNB_LLC_RFO (1ULL << 8)
855 #define SNB_LLC_IFETCH (1ULL << 9)
856 #define SNB_BUS_LOCKS (1ULL << 10)
857 #define SNB_STRM_ST (1ULL << 11)
858 #define SNB_OTHER (1ULL << 15)
859 #define SNB_RESP_ANY (1ULL << 16)
860 #define SNB_NO_SUPP (1ULL << 17)
861 #define SNB_LLC_HITM (1ULL << 18)
862 #define SNB_LLC_HITE (1ULL << 19)
863 #define SNB_LLC_HITS (1ULL << 20)
864 #define SNB_LLC_HITF (1ULL << 21)
865 #define SNB_LOCAL (1ULL << 22)
866 #define SNB_REMOTE (0xffULL << 23)
867 #define SNB_SNP_NONE (1ULL << 31)
868 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
869 #define SNB_SNP_MISS (1ULL << 33)
870 #define SNB_NO_FWD (1ULL << 34)
871 #define SNB_SNP_FWD (1ULL << 35)
872 #define SNB_HITM (1ULL << 36)
873 #define SNB_NON_DRAM (1ULL << 37)
874
875 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
876 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
877 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
878
879 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
880 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
881 SNB_HITM)
882
883 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
884 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
885
886 #define SNB_L3_ACCESS SNB_RESP_ANY
887 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
888
889 static __initconst const u64 snb_hw_cache_extra_regs
890 [PERF_COUNT_HW_CACHE_MAX]
891 [PERF_COUNT_HW_CACHE_OP_MAX]
892 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
893 {
894 [ C(LL ) ] = {
895 [ C(OP_READ) ] = {
896 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
897 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
898 },
899 [ C(OP_WRITE) ] = {
900 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
901 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
902 },
903 [ C(OP_PREFETCH) ] = {
904 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
905 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
906 },
907 },
908 [ C(NODE) ] = {
909 [ C(OP_READ) ] = {
910 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
911 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
912 },
913 [ C(OP_WRITE) ] = {
914 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
915 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
916 },
917 [ C(OP_PREFETCH) ] = {
918 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
919 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
920 },
921 },
922 };
923
924 static __initconst const u64 snb_hw_cache_event_ids
925 [PERF_COUNT_HW_CACHE_MAX]
926 [PERF_COUNT_HW_CACHE_OP_MAX]
927 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
928 {
929 [ C(L1D) ] = {
930 [ C(OP_READ) ] = {
931 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
932 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
933 },
934 [ C(OP_WRITE) ] = {
935 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
936 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
937 },
938 [ C(OP_PREFETCH) ] = {
939 [ C(RESULT_ACCESS) ] = 0x0,
940 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
941 },
942 },
943 [ C(L1I ) ] = {
944 [ C(OP_READ) ] = {
945 [ C(RESULT_ACCESS) ] = 0x0,
946 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
947 },
948 [ C(OP_WRITE) ] = {
949 [ C(RESULT_ACCESS) ] = -1,
950 [ C(RESULT_MISS) ] = -1,
951 },
952 [ C(OP_PREFETCH) ] = {
953 [ C(RESULT_ACCESS) ] = 0x0,
954 [ C(RESULT_MISS) ] = 0x0,
955 },
956 },
957 [ C(LL ) ] = {
958 [ C(OP_READ) ] = {
959 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
960 [ C(RESULT_ACCESS) ] = 0x01b7,
961 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
962 [ C(RESULT_MISS) ] = 0x01b7,
963 },
964 [ C(OP_WRITE) ] = {
965 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
966 [ C(RESULT_ACCESS) ] = 0x01b7,
967 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
968 [ C(RESULT_MISS) ] = 0x01b7,
969 },
970 [ C(OP_PREFETCH) ] = {
971 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
972 [ C(RESULT_ACCESS) ] = 0x01b7,
973 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
974 [ C(RESULT_MISS) ] = 0x01b7,
975 },
976 },
977 [ C(DTLB) ] = {
978 [ C(OP_READ) ] = {
979 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
980 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
981 },
982 [ C(OP_WRITE) ] = {
983 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
984 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
985 },
986 [ C(OP_PREFETCH) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0,
988 [ C(RESULT_MISS) ] = 0x0,
989 },
990 },
991 [ C(ITLB) ] = {
992 [ C(OP_READ) ] = {
993 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
994 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
995 },
996 [ C(OP_WRITE) ] = {
997 [ C(RESULT_ACCESS) ] = -1,
998 [ C(RESULT_MISS) ] = -1,
999 },
1000 [ C(OP_PREFETCH) ] = {
1001 [ C(RESULT_ACCESS) ] = -1,
1002 [ C(RESULT_MISS) ] = -1,
1003 },
1004 },
1005 [ C(BPU ) ] = {
1006 [ C(OP_READ) ] = {
1007 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1008 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1009 },
1010 [ C(OP_WRITE) ] = {
1011 [ C(RESULT_ACCESS) ] = -1,
1012 [ C(RESULT_MISS) ] = -1,
1013 },
1014 [ C(OP_PREFETCH) ] = {
1015 [ C(RESULT_ACCESS) ] = -1,
1016 [ C(RESULT_MISS) ] = -1,
1017 },
1018 },
1019 [ C(NODE) ] = {
1020 [ C(OP_READ) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x01b7,
1022 [ C(RESULT_MISS) ] = 0x01b7,
1023 },
1024 [ C(OP_WRITE) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x01b7,
1026 [ C(RESULT_MISS) ] = 0x01b7,
1027 },
1028 [ C(OP_PREFETCH) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01b7,
1030 [ C(RESULT_MISS) ] = 0x01b7,
1031 },
1032 },
1033
1034 };
1035
1036 /*
1037 * Notes on the events:
1038 * - data reads do not include code reads (comparable to earlier tables)
1039 * - data counts include speculative execution (except L1 write, dtlb, bpu)
1040 * - remote node access includes remote memory, remote cache, remote mmio.
1041 * - prefetches are not included in the counts because they are not
1042 * reliably counted.
1043 */
1044
1045 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
1046 #define HSW_DEMAND_RFO BIT_ULL(1)
1047 #define HSW_ANY_RESPONSE BIT_ULL(16)
1048 #define HSW_SUPPLIER_NONE BIT_ULL(17)
1049 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
1050 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
1051 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
1052 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
1053 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
1054 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1055 HSW_L3_MISS_REMOTE_HOP2P)
1056 #define HSW_SNOOP_NONE BIT_ULL(31)
1057 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
1058 #define HSW_SNOOP_MISS BIT_ULL(33)
1059 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
1060 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1061 #define HSW_SNOOP_HITM BIT_ULL(36)
1062 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
1063 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
1064 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
1065 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
1066 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
1067 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
1068 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
1069 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
1070 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
1071 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
1072 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
1073
1074 #define BDW_L3_MISS_LOCAL BIT(26)
1075 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
1076 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1077 HSW_L3_MISS_REMOTE_HOP2P)
1078
1079
1080 static __initconst const u64 hsw_hw_cache_event_ids
1081 [PERF_COUNT_HW_CACHE_MAX]
1082 [PERF_COUNT_HW_CACHE_OP_MAX]
1083 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1084 {
1085 [ C(L1D ) ] = {
1086 [ C(OP_READ) ] = {
1087 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1088 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1089 },
1090 [ C(OP_WRITE) ] = {
1091 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1092 [ C(RESULT_MISS) ] = 0x0,
1093 },
1094 [ C(OP_PREFETCH) ] = {
1095 [ C(RESULT_ACCESS) ] = 0x0,
1096 [ C(RESULT_MISS) ] = 0x0,
1097 },
1098 },
1099 [ C(L1I ) ] = {
1100 [ C(OP_READ) ] = {
1101 [ C(RESULT_ACCESS) ] = 0x0,
1102 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1103 },
1104 [ C(OP_WRITE) ] = {
1105 [ C(RESULT_ACCESS) ] = -1,
1106 [ C(RESULT_MISS) ] = -1,
1107 },
1108 [ C(OP_PREFETCH) ] = {
1109 [ C(RESULT_ACCESS) ] = 0x0,
1110 [ C(RESULT_MISS) ] = 0x0,
1111 },
1112 },
1113 [ C(LL ) ] = {
1114 [ C(OP_READ) ] = {
1115 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1116 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1117 },
1118 [ C(OP_WRITE) ] = {
1119 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1120 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1121 },
1122 [ C(OP_PREFETCH) ] = {
1123 [ C(RESULT_ACCESS) ] = 0x0,
1124 [ C(RESULT_MISS) ] = 0x0,
1125 },
1126 },
1127 [ C(DTLB) ] = {
1128 [ C(OP_READ) ] = {
1129 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1130 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1131 },
1132 [ C(OP_WRITE) ] = {
1133 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1134 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1135 },
1136 [ C(OP_PREFETCH) ] = {
1137 [ C(RESULT_ACCESS) ] = 0x0,
1138 [ C(RESULT_MISS) ] = 0x0,
1139 },
1140 },
1141 [ C(ITLB) ] = {
1142 [ C(OP_READ) ] = {
1143 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1144 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1145 },
1146 [ C(OP_WRITE) ] = {
1147 [ C(RESULT_ACCESS) ] = -1,
1148 [ C(RESULT_MISS) ] = -1,
1149 },
1150 [ C(OP_PREFETCH) ] = {
1151 [ C(RESULT_ACCESS) ] = -1,
1152 [ C(RESULT_MISS) ] = -1,
1153 },
1154 },
1155 [ C(BPU ) ] = {
1156 [ C(OP_READ) ] = {
1157 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1158 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1159 },
1160 [ C(OP_WRITE) ] = {
1161 [ C(RESULT_ACCESS) ] = -1,
1162 [ C(RESULT_MISS) ] = -1,
1163 },
1164 [ C(OP_PREFETCH) ] = {
1165 [ C(RESULT_ACCESS) ] = -1,
1166 [ C(RESULT_MISS) ] = -1,
1167 },
1168 },
1169 [ C(NODE) ] = {
1170 [ C(OP_READ) ] = {
1171 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1172 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1173 },
1174 [ C(OP_WRITE) ] = {
1175 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1176 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1177 },
1178 [ C(OP_PREFETCH) ] = {
1179 [ C(RESULT_ACCESS) ] = 0x0,
1180 [ C(RESULT_MISS) ] = 0x0,
1181 },
1182 },
1183 };
1184
1185 static __initconst const u64 hsw_hw_cache_extra_regs
1186 [PERF_COUNT_HW_CACHE_MAX]
1187 [PERF_COUNT_HW_CACHE_OP_MAX]
1188 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1189 {
1190 [ C(LL ) ] = {
1191 [ C(OP_READ) ] = {
1192 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1193 HSW_LLC_ACCESS,
1194 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1195 HSW_L3_MISS|HSW_ANY_SNOOP,
1196 },
1197 [ C(OP_WRITE) ] = {
1198 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1199 HSW_LLC_ACCESS,
1200 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1201 HSW_L3_MISS|HSW_ANY_SNOOP,
1202 },
1203 [ C(OP_PREFETCH) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x0,
1205 [ C(RESULT_MISS) ] = 0x0,
1206 },
1207 },
1208 [ C(NODE) ] = {
1209 [ C(OP_READ) ] = {
1210 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1211 HSW_L3_MISS_LOCAL_DRAM|
1212 HSW_SNOOP_DRAM,
1213 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1214 HSW_L3_MISS_REMOTE|
1215 HSW_SNOOP_DRAM,
1216 },
1217 [ C(OP_WRITE) ] = {
1218 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1219 HSW_L3_MISS_LOCAL_DRAM|
1220 HSW_SNOOP_DRAM,
1221 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1222 HSW_L3_MISS_REMOTE|
1223 HSW_SNOOP_DRAM,
1224 },
1225 [ C(OP_PREFETCH) ] = {
1226 [ C(RESULT_ACCESS) ] = 0x0,
1227 [ C(RESULT_MISS) ] = 0x0,
1228 },
1229 },
1230 };
1231
1232 static __initconst const u64 westmere_hw_cache_event_ids
1233 [PERF_COUNT_HW_CACHE_MAX]
1234 [PERF_COUNT_HW_CACHE_OP_MAX]
1235 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1236 {
1237 [ C(L1D) ] = {
1238 [ C(OP_READ) ] = {
1239 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1240 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1241 },
1242 [ C(OP_WRITE) ] = {
1243 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1244 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1245 },
1246 [ C(OP_PREFETCH) ] = {
1247 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1248 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1249 },
1250 },
1251 [ C(L1I ) ] = {
1252 [ C(OP_READ) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1254 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1255 },
1256 [ C(OP_WRITE) ] = {
1257 [ C(RESULT_ACCESS) ] = -1,
1258 [ C(RESULT_MISS) ] = -1,
1259 },
1260 [ C(OP_PREFETCH) ] = {
1261 [ C(RESULT_ACCESS) ] = 0x0,
1262 [ C(RESULT_MISS) ] = 0x0,
1263 },
1264 },
1265 [ C(LL ) ] = {
1266 [ C(OP_READ) ] = {
1267 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1268 [ C(RESULT_ACCESS) ] = 0x01b7,
1269 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1270 [ C(RESULT_MISS) ] = 0x01b7,
1271 },
1272 /*
1273 * Use RFO, not WRITEBACK, because a write miss would typically occur
1274 * on RFO.
1275 */
1276 [ C(OP_WRITE) ] = {
1277 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1278 [ C(RESULT_ACCESS) ] = 0x01b7,
1279 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1280 [ C(RESULT_MISS) ] = 0x01b7,
1281 },
1282 [ C(OP_PREFETCH) ] = {
1283 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1284 [ C(RESULT_ACCESS) ] = 0x01b7,
1285 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1286 [ C(RESULT_MISS) ] = 0x01b7,
1287 },
1288 },
1289 [ C(DTLB) ] = {
1290 [ C(OP_READ) ] = {
1291 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1292 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1293 },
1294 [ C(OP_WRITE) ] = {
1295 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1296 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1297 },
1298 [ C(OP_PREFETCH) ] = {
1299 [ C(RESULT_ACCESS) ] = 0x0,
1300 [ C(RESULT_MISS) ] = 0x0,
1301 },
1302 },
1303 [ C(ITLB) ] = {
1304 [ C(OP_READ) ] = {
1305 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1306 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1307 },
1308 [ C(OP_WRITE) ] = {
1309 [ C(RESULT_ACCESS) ] = -1,
1310 [ C(RESULT_MISS) ] = -1,
1311 },
1312 [ C(OP_PREFETCH) ] = {
1313 [ C(RESULT_ACCESS) ] = -1,
1314 [ C(RESULT_MISS) ] = -1,
1315 },
1316 },
1317 [ C(BPU ) ] = {
1318 [ C(OP_READ) ] = {
1319 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1320 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1321 },
1322 [ C(OP_WRITE) ] = {
1323 [ C(RESULT_ACCESS) ] = -1,
1324 [ C(RESULT_MISS) ] = -1,
1325 },
1326 [ C(OP_PREFETCH) ] = {
1327 [ C(RESULT_ACCESS) ] = -1,
1328 [ C(RESULT_MISS) ] = -1,
1329 },
1330 },
1331 [ C(NODE) ] = {
1332 [ C(OP_READ) ] = {
1333 [ C(RESULT_ACCESS) ] = 0x01b7,
1334 [ C(RESULT_MISS) ] = 0x01b7,
1335 },
1336 [ C(OP_WRITE) ] = {
1337 [ C(RESULT_ACCESS) ] = 0x01b7,
1338 [ C(RESULT_MISS) ] = 0x01b7,
1339 },
1340 [ C(OP_PREFETCH) ] = {
1341 [ C(RESULT_ACCESS) ] = 0x01b7,
1342 [ C(RESULT_MISS) ] = 0x01b7,
1343 },
1344 },
1345 };
1346
1347 /*
1348 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1349 * See IA32 SDM Vol 3B 30.6.1.3
1350 */
1351
1352 #define NHM_DMND_DATA_RD (1 << 0)
1353 #define NHM_DMND_RFO (1 << 1)
1354 #define NHM_DMND_IFETCH (1 << 2)
1355 #define NHM_DMND_WB (1 << 3)
1356 #define NHM_PF_DATA_RD (1 << 4)
1357 #define NHM_PF_DATA_RFO (1 << 5)
1358 #define NHM_PF_IFETCH (1 << 6)
1359 #define NHM_OFFCORE_OTHER (1 << 7)
1360 #define NHM_UNCORE_HIT (1 << 8)
1361 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1362 #define NHM_OTHER_CORE_HITM (1 << 10)
1363 /* reserved */
1364 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1365 #define NHM_REMOTE_DRAM (1 << 13)
1366 #define NHM_LOCAL_DRAM (1 << 14)
1367 #define NHM_NON_DRAM (1 << 15)
1368
1369 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1370 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1371
1372 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1373 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1374 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1375
1376 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1377 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1378 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1379
1380 static __initconst const u64 nehalem_hw_cache_extra_regs
1381 [PERF_COUNT_HW_CACHE_MAX]
1382 [PERF_COUNT_HW_CACHE_OP_MAX]
1383 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1384 {
1385 [ C(LL ) ] = {
1386 [ C(OP_READ) ] = {
1387 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1388 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1389 },
1390 [ C(OP_WRITE) ] = {
1391 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1392 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1393 },
1394 [ C(OP_PREFETCH) ] = {
1395 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1396 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1397 },
1398 },
1399 [ C(NODE) ] = {
1400 [ C(OP_READ) ] = {
1401 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1402 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1403 },
1404 [ C(OP_WRITE) ] = {
1405 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1406 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1407 },
1408 [ C(OP_PREFETCH) ] = {
1409 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1410 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1411 },
1412 },
1413 };
1414
1415 static __initconst const u64 nehalem_hw_cache_event_ids
1416 [PERF_COUNT_HW_CACHE_MAX]
1417 [PERF_COUNT_HW_CACHE_OP_MAX]
1418 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1419 {
1420 [ C(L1D) ] = {
1421 [ C(OP_READ) ] = {
1422 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1423 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1424 },
1425 [ C(OP_WRITE) ] = {
1426 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1427 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1428 },
1429 [ C(OP_PREFETCH) ] = {
1430 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1431 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1432 },
1433 },
1434 [ C(L1I ) ] = {
1435 [ C(OP_READ) ] = {
1436 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1437 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1438 },
1439 [ C(OP_WRITE) ] = {
1440 [ C(RESULT_ACCESS) ] = -1,
1441 [ C(RESULT_MISS) ] = -1,
1442 },
1443 [ C(OP_PREFETCH) ] = {
1444 [ C(RESULT_ACCESS) ] = 0x0,
1445 [ C(RESULT_MISS) ] = 0x0,
1446 },
1447 },
1448 [ C(LL ) ] = {
1449 [ C(OP_READ) ] = {
1450 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1451 [ C(RESULT_ACCESS) ] = 0x01b7,
1452 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1453 [ C(RESULT_MISS) ] = 0x01b7,
1454 },
1455 /*
1456 * Use RFO, not WRITEBACK, because a write miss would typically occur
1457 * on RFO.
1458 */
1459 [ C(OP_WRITE) ] = {
1460 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1461 [ C(RESULT_ACCESS) ] = 0x01b7,
1462 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1463 [ C(RESULT_MISS) ] = 0x01b7,
1464 },
1465 [ C(OP_PREFETCH) ] = {
1466 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1467 [ C(RESULT_ACCESS) ] = 0x01b7,
1468 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1469 [ C(RESULT_MISS) ] = 0x01b7,
1470 },
1471 },
1472 [ C(DTLB) ] = {
1473 [ C(OP_READ) ] = {
1474 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1475 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1476 },
1477 [ C(OP_WRITE) ] = {
1478 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1479 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1480 },
1481 [ C(OP_PREFETCH) ] = {
1482 [ C(RESULT_ACCESS) ] = 0x0,
1483 [ C(RESULT_MISS) ] = 0x0,
1484 },
1485 },
1486 [ C(ITLB) ] = {
1487 [ C(OP_READ) ] = {
1488 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1489 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1490 },
1491 [ C(OP_WRITE) ] = {
1492 [ C(RESULT_ACCESS) ] = -1,
1493 [ C(RESULT_MISS) ] = -1,
1494 },
1495 [ C(OP_PREFETCH) ] = {
1496 [ C(RESULT_ACCESS) ] = -1,
1497 [ C(RESULT_MISS) ] = -1,
1498 },
1499 },
1500 [ C(BPU ) ] = {
1501 [ C(OP_READ) ] = {
1502 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1503 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1504 },
1505 [ C(OP_WRITE) ] = {
1506 [ C(RESULT_ACCESS) ] = -1,
1507 [ C(RESULT_MISS) ] = -1,
1508 },
1509 [ C(OP_PREFETCH) ] = {
1510 [ C(RESULT_ACCESS) ] = -1,
1511 [ C(RESULT_MISS) ] = -1,
1512 },
1513 },
1514 [ C(NODE) ] = {
1515 [ C(OP_READ) ] = {
1516 [ C(RESULT_ACCESS) ] = 0x01b7,
1517 [ C(RESULT_MISS) ] = 0x01b7,
1518 },
1519 [ C(OP_WRITE) ] = {
1520 [ C(RESULT_ACCESS) ] = 0x01b7,
1521 [ C(RESULT_MISS) ] = 0x01b7,
1522 },
1523 [ C(OP_PREFETCH) ] = {
1524 [ C(RESULT_ACCESS) ] = 0x01b7,
1525 [ C(RESULT_MISS) ] = 0x01b7,
1526 },
1527 },
1528 };
1529
1530 static __initconst const u64 core2_hw_cache_event_ids
1531 [PERF_COUNT_HW_CACHE_MAX]
1532 [PERF_COUNT_HW_CACHE_OP_MAX]
1533 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1534 {
1535 [ C(L1D) ] = {
1536 [ C(OP_READ) ] = {
1537 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1538 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1539 },
1540 [ C(OP_WRITE) ] = {
1541 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1542 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1543 },
1544 [ C(OP_PREFETCH) ] = {
1545 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1546 [ C(RESULT_MISS) ] = 0,
1547 },
1548 },
1549 [ C(L1I ) ] = {
1550 [ C(OP_READ) ] = {
1551 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1552 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1553 },
1554 [ C(OP_WRITE) ] = {
1555 [ C(RESULT_ACCESS) ] = -1,
1556 [ C(RESULT_MISS) ] = -1,
1557 },
1558 [ C(OP_PREFETCH) ] = {
1559 [ C(RESULT_ACCESS) ] = 0,
1560 [ C(RESULT_MISS) ] = 0,
1561 },
1562 },
1563 [ C(LL ) ] = {
1564 [ C(OP_READ) ] = {
1565 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1566 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1567 },
1568 [ C(OP_WRITE) ] = {
1569 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1570 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1571 },
1572 [ C(OP_PREFETCH) ] = {
1573 [ C(RESULT_ACCESS) ] = 0,
1574 [ C(RESULT_MISS) ] = 0,
1575 },
1576 },
1577 [ C(DTLB) ] = {
1578 [ C(OP_READ) ] = {
1579 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1580 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1581 },
1582 [ C(OP_WRITE) ] = {
1583 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1584 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1585 },
1586 [ C(OP_PREFETCH) ] = {
1587 [ C(RESULT_ACCESS) ] = 0,
1588 [ C(RESULT_MISS) ] = 0,
1589 },
1590 },
1591 [ C(ITLB) ] = {
1592 [ C(OP_READ) ] = {
1593 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1594 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1595 },
1596 [ C(OP_WRITE) ] = {
1597 [ C(RESULT_ACCESS) ] = -1,
1598 [ C(RESULT_MISS) ] = -1,
1599 },
1600 [ C(OP_PREFETCH) ] = {
1601 [ C(RESULT_ACCESS) ] = -1,
1602 [ C(RESULT_MISS) ] = -1,
1603 },
1604 },
1605 [ C(BPU ) ] = {
1606 [ C(OP_READ) ] = {
1607 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1608 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1609 },
1610 [ C(OP_WRITE) ] = {
1611 [ C(RESULT_ACCESS) ] = -1,
1612 [ C(RESULT_MISS) ] = -1,
1613 },
1614 [ C(OP_PREFETCH) ] = {
1615 [ C(RESULT_ACCESS) ] = -1,
1616 [ C(RESULT_MISS) ] = -1,
1617 },
1618 },
1619 };
1620
1621 static __initconst const u64 atom_hw_cache_event_ids
1622 [PERF_COUNT_HW_CACHE_MAX]
1623 [PERF_COUNT_HW_CACHE_OP_MAX]
1624 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1625 {
1626 [ C(L1D) ] = {
1627 [ C(OP_READ) ] = {
1628 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1629 [ C(RESULT_MISS) ] = 0,
1630 },
1631 [ C(OP_WRITE) ] = {
1632 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1633 [ C(RESULT_MISS) ] = 0,
1634 },
1635 [ C(OP_PREFETCH) ] = {
1636 [ C(RESULT_ACCESS) ] = 0x0,
1637 [ C(RESULT_MISS) ] = 0,
1638 },
1639 },
1640 [ C(L1I ) ] = {
1641 [ C(OP_READ) ] = {
1642 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1643 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1644 },
1645 [ C(OP_WRITE) ] = {
1646 [ C(RESULT_ACCESS) ] = -1,
1647 [ C(RESULT_MISS) ] = -1,
1648 },
1649 [ C(OP_PREFETCH) ] = {
1650 [ C(RESULT_ACCESS) ] = 0,
1651 [ C(RESULT_MISS) ] = 0,
1652 },
1653 },
1654 [ C(LL ) ] = {
1655 [ C(OP_READ) ] = {
1656 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1657 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1658 },
1659 [ C(OP_WRITE) ] = {
1660 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1661 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1662 },
1663 [ C(OP_PREFETCH) ] = {
1664 [ C(RESULT_ACCESS) ] = 0,
1665 [ C(RESULT_MISS) ] = 0,
1666 },
1667 },
1668 [ C(DTLB) ] = {
1669 [ C(OP_READ) ] = {
1670 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1671 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1672 },
1673 [ C(OP_WRITE) ] = {
1674 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1675 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1676 },
1677 [ C(OP_PREFETCH) ] = {
1678 [ C(RESULT_ACCESS) ] = 0,
1679 [ C(RESULT_MISS) ] = 0,
1680 },
1681 },
1682 [ C(ITLB) ] = {
1683 [ C(OP_READ) ] = {
1684 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1685 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1686 },
1687 [ C(OP_WRITE) ] = {
1688 [ C(RESULT_ACCESS) ] = -1,
1689 [ C(RESULT_MISS) ] = -1,
1690 },
1691 [ C(OP_PREFETCH) ] = {
1692 [ C(RESULT_ACCESS) ] = -1,
1693 [ C(RESULT_MISS) ] = -1,
1694 },
1695 },
1696 [ C(BPU ) ] = {
1697 [ C(OP_READ) ] = {
1698 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1699 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1700 },
1701 [ C(OP_WRITE) ] = {
1702 [ C(RESULT_ACCESS) ] = -1,
1703 [ C(RESULT_MISS) ] = -1,
1704 },
1705 [ C(OP_PREFETCH) ] = {
1706 [ C(RESULT_ACCESS) ] = -1,
1707 [ C(RESULT_MISS) ] = -1,
1708 },
1709 },
1710 };
1711
1712 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1713 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1714 /* no_alloc_cycles.not_delivered */
1715 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1716 "event=0xca,umask=0x50");
1717 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1718 /* uops_retired.all */
1719 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1720 "event=0xc2,umask=0x10");
1721 /* uops_retired.all */
1722 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1723 "event=0xc2,umask=0x10");
1724
1725 static struct attribute *slm_events_attrs[] = {
1726 EVENT_PTR(td_total_slots_slm),
1727 EVENT_PTR(td_total_slots_scale_slm),
1728 EVENT_PTR(td_fetch_bubbles_slm),
1729 EVENT_PTR(td_fetch_bubbles_scale_slm),
1730 EVENT_PTR(td_slots_issued_slm),
1731 EVENT_PTR(td_slots_retired_slm),
1732 NULL
1733 };
1734
1735 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1736 {
1737 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1738 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1739 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1740 EVENT_EXTRA_END
1741 };
1742
1743 #define SLM_DMND_READ SNB_DMND_DATA_RD
1744 #define SLM_DMND_WRITE SNB_DMND_RFO
1745 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1746
1747 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1748 #define SLM_LLC_ACCESS SNB_RESP_ANY
1749 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1750
1751 static __initconst const u64 slm_hw_cache_extra_regs
1752 [PERF_COUNT_HW_CACHE_MAX]
1753 [PERF_COUNT_HW_CACHE_OP_MAX]
1754 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1755 {
1756 [ C(LL ) ] = {
1757 [ C(OP_READ) ] = {
1758 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1759 [ C(RESULT_MISS) ] = 0,
1760 },
1761 [ C(OP_WRITE) ] = {
1762 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1763 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1764 },
1765 [ C(OP_PREFETCH) ] = {
1766 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1767 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1768 },
1769 },
1770 };
1771
1772 static __initconst const u64 slm_hw_cache_event_ids
1773 [PERF_COUNT_HW_CACHE_MAX]
1774 [PERF_COUNT_HW_CACHE_OP_MAX]
1775 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1776 {
1777 [ C(L1D) ] = {
1778 [ C(OP_READ) ] = {
1779 [ C(RESULT_ACCESS) ] = 0,
1780 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1781 },
1782 [ C(OP_WRITE) ] = {
1783 [ C(RESULT_ACCESS) ] = 0,
1784 [ C(RESULT_MISS) ] = 0,
1785 },
1786 [ C(OP_PREFETCH) ] = {
1787 [ C(RESULT_ACCESS) ] = 0,
1788 [ C(RESULT_MISS) ] = 0,
1789 },
1790 },
1791 [ C(L1I ) ] = {
1792 [ C(OP_READ) ] = {
1793 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1794 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1795 },
1796 [ C(OP_WRITE) ] = {
1797 [ C(RESULT_ACCESS) ] = -1,
1798 [ C(RESULT_MISS) ] = -1,
1799 },
1800 [ C(OP_PREFETCH) ] = {
1801 [ C(RESULT_ACCESS) ] = 0,
1802 [ C(RESULT_MISS) ] = 0,
1803 },
1804 },
1805 [ C(LL ) ] = {
1806 [ C(OP_READ) ] = {
1807 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1808 [ C(RESULT_ACCESS) ] = 0x01b7,
1809 [ C(RESULT_MISS) ] = 0,
1810 },
1811 [ C(OP_WRITE) ] = {
1812 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1813 [ C(RESULT_ACCESS) ] = 0x01b7,
1814 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1815 [ C(RESULT_MISS) ] = 0x01b7,
1816 },
1817 [ C(OP_PREFETCH) ] = {
1818 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1819 [ C(RESULT_ACCESS) ] = 0x01b7,
1820 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1821 [ C(RESULT_MISS) ] = 0x01b7,
1822 },
1823 },
1824 [ C(DTLB) ] = {
1825 [ C(OP_READ) ] = {
1826 [ C(RESULT_ACCESS) ] = 0,
1827 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1828 },
1829 [ C(OP_WRITE) ] = {
1830 [ C(RESULT_ACCESS) ] = 0,
1831 [ C(RESULT_MISS) ] = 0,
1832 },
1833 [ C(OP_PREFETCH) ] = {
1834 [ C(RESULT_ACCESS) ] = 0,
1835 [ C(RESULT_MISS) ] = 0,
1836 },
1837 },
1838 [ C(ITLB) ] = {
1839 [ C(OP_READ) ] = {
1840 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1841 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1842 },
1843 [ C(OP_WRITE) ] = {
1844 [ C(RESULT_ACCESS) ] = -1,
1845 [ C(RESULT_MISS) ] = -1,
1846 },
1847 [ C(OP_PREFETCH) ] = {
1848 [ C(RESULT_ACCESS) ] = -1,
1849 [ C(RESULT_MISS) ] = -1,
1850 },
1851 },
1852 [ C(BPU ) ] = {
1853 [ C(OP_READ) ] = {
1854 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1855 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1856 },
1857 [ C(OP_WRITE) ] = {
1858 [ C(RESULT_ACCESS) ] = -1,
1859 [ C(RESULT_MISS) ] = -1,
1860 },
1861 [ C(OP_PREFETCH) ] = {
1862 [ C(RESULT_ACCESS) ] = -1,
1863 [ C(RESULT_MISS) ] = -1,
1864 },
1865 },
1866 };
1867
1868 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1869 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1870 /* UOPS_NOT_DELIVERED.ANY */
1871 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1872 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1873 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1874 /* UOPS_RETIRED.ANY */
1875 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1876 /* UOPS_ISSUED.ANY */
1877 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1878
1879 static struct attribute *glm_events_attrs[] = {
1880 EVENT_PTR(td_total_slots_glm),
1881 EVENT_PTR(td_total_slots_scale_glm),
1882 EVENT_PTR(td_fetch_bubbles_glm),
1883 EVENT_PTR(td_recovery_bubbles_glm),
1884 EVENT_PTR(td_slots_issued_glm),
1885 EVENT_PTR(td_slots_retired_glm),
1886 NULL
1887 };
1888
1889 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1890 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1891 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1892 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1893 EVENT_EXTRA_END
1894 };
1895
1896 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1897 #define GLM_DEMAND_RFO BIT_ULL(1)
1898 #define GLM_ANY_RESPONSE BIT_ULL(16)
1899 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1900 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1901 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1902 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1903 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1904 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1905 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1906
1907 static __initconst const u64 glm_hw_cache_event_ids
1908 [PERF_COUNT_HW_CACHE_MAX]
1909 [PERF_COUNT_HW_CACHE_OP_MAX]
1910 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1911 [C(L1D)] = {
1912 [C(OP_READ)] = {
1913 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1914 [C(RESULT_MISS)] = 0x0,
1915 },
1916 [C(OP_WRITE)] = {
1917 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1918 [C(RESULT_MISS)] = 0x0,
1919 },
1920 [C(OP_PREFETCH)] = {
1921 [C(RESULT_ACCESS)] = 0x0,
1922 [C(RESULT_MISS)] = 0x0,
1923 },
1924 },
1925 [C(L1I)] = {
1926 [C(OP_READ)] = {
1927 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1928 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1929 },
1930 [C(OP_WRITE)] = {
1931 [C(RESULT_ACCESS)] = -1,
1932 [C(RESULT_MISS)] = -1,
1933 },
1934 [C(OP_PREFETCH)] = {
1935 [C(RESULT_ACCESS)] = 0x0,
1936 [C(RESULT_MISS)] = 0x0,
1937 },
1938 },
1939 [C(LL)] = {
1940 [C(OP_READ)] = {
1941 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1942 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1943 },
1944 [C(OP_WRITE)] = {
1945 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1946 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1947 },
1948 [C(OP_PREFETCH)] = {
1949 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1950 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1951 },
1952 },
1953 [C(DTLB)] = {
1954 [C(OP_READ)] = {
1955 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1956 [C(RESULT_MISS)] = 0x0,
1957 },
1958 [C(OP_WRITE)] = {
1959 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1960 [C(RESULT_MISS)] = 0x0,
1961 },
1962 [C(OP_PREFETCH)] = {
1963 [C(RESULT_ACCESS)] = 0x0,
1964 [C(RESULT_MISS)] = 0x0,
1965 },
1966 },
1967 [C(ITLB)] = {
1968 [C(OP_READ)] = {
1969 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1970 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1971 },
1972 [C(OP_WRITE)] = {
1973 [C(RESULT_ACCESS)] = -1,
1974 [C(RESULT_MISS)] = -1,
1975 },
1976 [C(OP_PREFETCH)] = {
1977 [C(RESULT_ACCESS)] = -1,
1978 [C(RESULT_MISS)] = -1,
1979 },
1980 },
1981 [C(BPU)] = {
1982 [C(OP_READ)] = {
1983 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1984 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1985 },
1986 [C(OP_WRITE)] = {
1987 [C(RESULT_ACCESS)] = -1,
1988 [C(RESULT_MISS)] = -1,
1989 },
1990 [C(OP_PREFETCH)] = {
1991 [C(RESULT_ACCESS)] = -1,
1992 [C(RESULT_MISS)] = -1,
1993 },
1994 },
1995 };
1996
1997 static __initconst const u64 glm_hw_cache_extra_regs
1998 [PERF_COUNT_HW_CACHE_MAX]
1999 [PERF_COUNT_HW_CACHE_OP_MAX]
2000 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2001 [C(LL)] = {
2002 [C(OP_READ)] = {
2003 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2004 GLM_LLC_ACCESS,
2005 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2006 GLM_LLC_MISS,
2007 },
2008 [C(OP_WRITE)] = {
2009 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2010 GLM_LLC_ACCESS,
2011 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2012 GLM_LLC_MISS,
2013 },
2014 [C(OP_PREFETCH)] = {
2015 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
2016 GLM_LLC_ACCESS,
2017 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
2018 GLM_LLC_MISS,
2019 },
2020 },
2021 };
2022
2023 static __initconst const u64 glp_hw_cache_event_ids
2024 [PERF_COUNT_HW_CACHE_MAX]
2025 [PERF_COUNT_HW_CACHE_OP_MAX]
2026 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2027 [C(L1D)] = {
2028 [C(OP_READ)] = {
2029 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2030 [C(RESULT_MISS)] = 0x0,
2031 },
2032 [C(OP_WRITE)] = {
2033 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2034 [C(RESULT_MISS)] = 0x0,
2035 },
2036 [C(OP_PREFETCH)] = {
2037 [C(RESULT_ACCESS)] = 0x0,
2038 [C(RESULT_MISS)] = 0x0,
2039 },
2040 },
2041 [C(L1I)] = {
2042 [C(OP_READ)] = {
2043 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2044 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2045 },
2046 [C(OP_WRITE)] = {
2047 [C(RESULT_ACCESS)] = -1,
2048 [C(RESULT_MISS)] = -1,
2049 },
2050 [C(OP_PREFETCH)] = {
2051 [C(RESULT_ACCESS)] = 0x0,
2052 [C(RESULT_MISS)] = 0x0,
2053 },
2054 },
2055 [C(LL)] = {
2056 [C(OP_READ)] = {
2057 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2058 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2059 },
2060 [C(OP_WRITE)] = {
2061 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2062 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2063 },
2064 [C(OP_PREFETCH)] = {
2065 [C(RESULT_ACCESS)] = 0x0,
2066 [C(RESULT_MISS)] = 0x0,
2067 },
2068 },
2069 [C(DTLB)] = {
2070 [C(OP_READ)] = {
2071 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2072 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2073 },
2074 [C(OP_WRITE)] = {
2075 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2076 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2077 },
2078 [C(OP_PREFETCH)] = {
2079 [C(RESULT_ACCESS)] = 0x0,
2080 [C(RESULT_MISS)] = 0x0,
2081 },
2082 },
2083 [C(ITLB)] = {
2084 [C(OP_READ)] = {
2085 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2086 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2087 },
2088 [C(OP_WRITE)] = {
2089 [C(RESULT_ACCESS)] = -1,
2090 [C(RESULT_MISS)] = -1,
2091 },
2092 [C(OP_PREFETCH)] = {
2093 [C(RESULT_ACCESS)] = -1,
2094 [C(RESULT_MISS)] = -1,
2095 },
2096 },
2097 [C(BPU)] = {
2098 [C(OP_READ)] = {
2099 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2100 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2101 },
2102 [C(OP_WRITE)] = {
2103 [C(RESULT_ACCESS)] = -1,
2104 [C(RESULT_MISS)] = -1,
2105 },
2106 [C(OP_PREFETCH)] = {
2107 [C(RESULT_ACCESS)] = -1,
2108 [C(RESULT_MISS)] = -1,
2109 },
2110 },
2111 };
2112
2113 static __initconst const u64 glp_hw_cache_extra_regs
2114 [PERF_COUNT_HW_CACHE_MAX]
2115 [PERF_COUNT_HW_CACHE_OP_MAX]
2116 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2117 [C(LL)] = {
2118 [C(OP_READ)] = {
2119 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2120 GLM_LLC_ACCESS,
2121 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2122 GLM_LLC_MISS,
2123 },
2124 [C(OP_WRITE)] = {
2125 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2126 GLM_LLC_ACCESS,
2127 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2128 GLM_LLC_MISS,
2129 },
2130 [C(OP_PREFETCH)] = {
2131 [C(RESULT_ACCESS)] = 0x0,
2132 [C(RESULT_MISS)] = 0x0,
2133 },
2134 },
2135 };
2136
2137 #define TNT_LOCAL_DRAM BIT_ULL(26)
2138 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2139 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2140 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2141 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2142 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2143 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2144
2145 static __initconst const u64 tnt_hw_cache_extra_regs
2146 [PERF_COUNT_HW_CACHE_MAX]
2147 [PERF_COUNT_HW_CACHE_OP_MAX]
2148 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2149 [C(LL)] = {
2150 [C(OP_READ)] = {
2151 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2152 TNT_LLC_ACCESS,
2153 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2154 TNT_LLC_MISS,
2155 },
2156 [C(OP_WRITE)] = {
2157 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2158 TNT_LLC_ACCESS,
2159 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2160 TNT_LLC_MISS,
2161 },
2162 [C(OP_PREFETCH)] = {
2163 [C(RESULT_ACCESS)] = 0x0,
2164 [C(RESULT_MISS)] = 0x0,
2165 },
2166 },
2167 };
2168
2169 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2170 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2171 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2172 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2173
2174 static struct attribute *tnt_events_attrs[] = {
2175 EVENT_PTR(td_fe_bound_tnt),
2176 EVENT_PTR(td_retiring_tnt),
2177 EVENT_PTR(td_bad_spec_tnt),
2178 EVENT_PTR(td_be_bound_tnt),
2179 NULL,
2180 };
2181
2182 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2183 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2184 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2185 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2186 EVENT_EXTRA_END
2187 };
2188
2189 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2190 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2191
2192 static struct attribute *grt_mem_attrs[] = {
2193 EVENT_PTR(mem_ld_grt),
2194 EVENT_PTR(mem_st_grt),
2195 NULL
2196 };
2197
2198 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2199 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2200 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2201 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
2202 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2203 EVENT_EXTRA_END
2204 };
2205
2206 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0");
2207 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0");
2208
2209 static struct attribute *cmt_events_attrs[] = {
2210 EVENT_PTR(td_fe_bound_tnt),
2211 EVENT_PTR(td_retiring_cmt),
2212 EVENT_PTR(td_bad_spec_cmt),
2213 EVENT_PTR(td_be_bound_tnt),
2214 NULL
2215 };
2216
2217 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
2218 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2219 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
2220 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1),
2221 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2222 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2223 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2224 EVENT_EXTRA_END
2225 };
2226
2227 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2228 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2229 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
2230 #define KNL_MCDRAM_FAR BIT_ULL(22)
2231 #define KNL_DDR_LOCAL BIT_ULL(23)
2232 #define KNL_DDR_FAR BIT_ULL(24)
2233 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2234 KNL_DDR_LOCAL | KNL_DDR_FAR)
2235 #define KNL_L2_READ SLM_DMND_READ
2236 #define KNL_L2_WRITE SLM_DMND_WRITE
2237 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2238 #define KNL_L2_ACCESS SLM_LLC_ACCESS
2239 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2240 KNL_DRAM_ANY | SNB_SNP_ANY | \
2241 SNB_NON_DRAM)
2242
2243 static __initconst const u64 knl_hw_cache_extra_regs
2244 [PERF_COUNT_HW_CACHE_MAX]
2245 [PERF_COUNT_HW_CACHE_OP_MAX]
2246 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2247 [C(LL)] = {
2248 [C(OP_READ)] = {
2249 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2250 [C(RESULT_MISS)] = 0,
2251 },
2252 [C(OP_WRITE)] = {
2253 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2254 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2255 },
2256 [C(OP_PREFETCH)] = {
2257 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2258 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2259 },
2260 },
2261 };
2262
2263 /*
2264 * Used from PMIs where the LBRs are already disabled.
2265 *
2266 * This function could be called consecutively. It is required to remain in
2267 * disabled state if called consecutively.
2268 *
2269 * During consecutive calls, the same disable value will be written to related
2270 * registers, so the PMU state remains unchanged.
2271 *
2272 * intel_bts events don't coexist with intel PMU's BTS events because of
2273 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2274 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2275 *
2276 * Avoid PEBS_ENABLE MSR access in PMIs.
2277 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2278 * It doesn't matter if the PEBS is enabled or not.
2279 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2280 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2281 * However, there are some cases which may change PEBS status, e.g. PMI
2282 * throttle. The PEBS_ENABLE should be updated where the status changes.
2283 */
__intel_pmu_disable_all(bool bts)2284 static __always_inline void __intel_pmu_disable_all(bool bts)
2285 {
2286 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2287
2288 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2289
2290 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2291 intel_pmu_disable_bts();
2292 }
2293
intel_pmu_disable_all(void)2294 static __always_inline void intel_pmu_disable_all(void)
2295 {
2296 __intel_pmu_disable_all(true);
2297 intel_pmu_pebs_disable_all();
2298 intel_pmu_lbr_disable_all();
2299 }
2300
__intel_pmu_enable_all(int added,bool pmi)2301 static void __intel_pmu_enable_all(int added, bool pmi)
2302 {
2303 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2304 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2305
2306 intel_pmu_lbr_enable_all(pmi);
2307
2308 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) {
2309 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val);
2310 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val;
2311 }
2312
2313 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2314 intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2315
2316 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2317 struct perf_event *event =
2318 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2319
2320 if (WARN_ON_ONCE(!event))
2321 return;
2322
2323 intel_pmu_enable_bts(event->hw.config);
2324 }
2325 }
2326
intel_pmu_enable_all(int added)2327 static void intel_pmu_enable_all(int added)
2328 {
2329 intel_pmu_pebs_enable_all();
2330 __intel_pmu_enable_all(added, false);
2331 }
2332
2333 static noinline int
__intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt,unsigned long flags)2334 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2335 unsigned int cnt, unsigned long flags)
2336 {
2337 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2338
2339 intel_pmu_lbr_read();
2340 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2341
2342 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2343 intel_pmu_enable_all(0);
2344 local_irq_restore(flags);
2345 return cnt;
2346 }
2347
2348 static int
intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2349 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2350 {
2351 unsigned long flags;
2352
2353 /* must not have branches... */
2354 local_irq_save(flags);
2355 __intel_pmu_disable_all(false); /* we don't care about BTS */
2356 __intel_pmu_lbr_disable();
2357 /* ... until here */
2358 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2359 }
2360
2361 static int
intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2362 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2363 {
2364 unsigned long flags;
2365
2366 /* must not have branches... */
2367 local_irq_save(flags);
2368 __intel_pmu_disable_all(false); /* we don't care about BTS */
2369 __intel_pmu_arch_lbr_disable();
2370 /* ... until here */
2371 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2372 }
2373
2374 /*
2375 * Workaround for:
2376 * Intel Errata AAK100 (model 26)
2377 * Intel Errata AAP53 (model 30)
2378 * Intel Errata BD53 (model 44)
2379 *
2380 * The official story:
2381 * These chips need to be 'reset' when adding counters by programming the
2382 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2383 * in sequence on the same PMC or on different PMCs.
2384 *
2385 * In practice it appears some of these events do in fact count, and
2386 * we need to program all 4 events.
2387 */
intel_pmu_nhm_workaround(void)2388 static void intel_pmu_nhm_workaround(void)
2389 {
2390 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2391 static const unsigned long nhm_magic[4] = {
2392 0x4300B5,
2393 0x4300D2,
2394 0x4300B1,
2395 0x4300B1
2396 };
2397 struct perf_event *event;
2398 int i;
2399
2400 /*
2401 * The Errata requires below steps:
2402 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2403 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2404 * the corresponding PMCx;
2405 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2406 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2407 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2408 */
2409
2410 /*
2411 * The real steps we choose are a little different from above.
2412 * A) To reduce MSR operations, we don't run step 1) as they
2413 * are already cleared before this function is called;
2414 * B) Call x86_perf_event_update to save PMCx before configuring
2415 * PERFEVTSELx with magic number;
2416 * C) With step 5), we do clear only when the PERFEVTSELx is
2417 * not used currently.
2418 * D) Call x86_perf_event_set_period to restore PMCx;
2419 */
2420
2421 /* We always operate 4 pairs of PERF Counters */
2422 for (i = 0; i < 4; i++) {
2423 event = cpuc->events[i];
2424 if (event)
2425 static_call(x86_pmu_update)(event);
2426 }
2427
2428 for (i = 0; i < 4; i++) {
2429 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2430 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2431 }
2432
2433 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2434 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2435
2436 for (i = 0; i < 4; i++) {
2437 event = cpuc->events[i];
2438
2439 if (event) {
2440 static_call(x86_pmu_set_period)(event);
2441 __x86_pmu_enable_event(&event->hw,
2442 ARCH_PERFMON_EVENTSEL_ENABLE);
2443 } else
2444 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2445 }
2446 }
2447
intel_pmu_nhm_enable_all(int added)2448 static void intel_pmu_nhm_enable_all(int added)
2449 {
2450 if (added)
2451 intel_pmu_nhm_workaround();
2452 intel_pmu_enable_all(added);
2453 }
2454
intel_set_tfa(struct cpu_hw_events * cpuc,bool on)2455 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2456 {
2457 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2458
2459 if (cpuc->tfa_shadow != val) {
2460 cpuc->tfa_shadow = val;
2461 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2462 }
2463 }
2464
intel_tfa_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)2465 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2466 {
2467 /*
2468 * We're going to use PMC3, make sure TFA is set before we touch it.
2469 */
2470 if (cntr == 3)
2471 intel_set_tfa(cpuc, true);
2472 }
2473
intel_tfa_pmu_enable_all(int added)2474 static void intel_tfa_pmu_enable_all(int added)
2475 {
2476 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2477
2478 /*
2479 * If we find PMC3 is no longer used when we enable the PMU, we can
2480 * clear TFA.
2481 */
2482 if (!test_bit(3, cpuc->active_mask))
2483 intel_set_tfa(cpuc, false);
2484
2485 intel_pmu_enable_all(added);
2486 }
2487
intel_pmu_get_status(void)2488 static inline u64 intel_pmu_get_status(void)
2489 {
2490 u64 status;
2491
2492 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2493
2494 return status;
2495 }
2496
intel_pmu_ack_status(u64 ack)2497 static inline void intel_pmu_ack_status(u64 ack)
2498 {
2499 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2500 }
2501
event_is_checkpointed(struct perf_event * event)2502 static inline bool event_is_checkpointed(struct perf_event *event)
2503 {
2504 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2505 }
2506
intel_set_masks(struct perf_event * event,int idx)2507 static inline void intel_set_masks(struct perf_event *event, int idx)
2508 {
2509 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2510
2511 if (event->attr.exclude_host)
2512 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2513 if (event->attr.exclude_guest)
2514 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2515 if (event_is_checkpointed(event))
2516 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2517 }
2518
intel_clear_masks(struct perf_event * event,int idx)2519 static inline void intel_clear_masks(struct perf_event *event, int idx)
2520 {
2521 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2522
2523 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2524 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2525 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2526 }
2527
intel_pmu_disable_fixed(struct perf_event * event)2528 static void intel_pmu_disable_fixed(struct perf_event *event)
2529 {
2530 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2531 struct hw_perf_event *hwc = &event->hw;
2532 int idx = hwc->idx;
2533 u64 mask;
2534
2535 if (is_topdown_idx(idx)) {
2536 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2537
2538 /*
2539 * When there are other active TopDown events,
2540 * don't disable the fixed counter 3.
2541 */
2542 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2543 return;
2544 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2545 }
2546
2547 intel_clear_masks(event, idx);
2548
2549 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);
2550 cpuc->fixed_ctrl_val &= ~mask;
2551 }
2552
intel_pmu_disable_event(struct perf_event * event)2553 static void intel_pmu_disable_event(struct perf_event *event)
2554 {
2555 struct hw_perf_event *hwc = &event->hw;
2556 int idx = hwc->idx;
2557
2558 switch (idx) {
2559 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2560 intel_clear_masks(event, idx);
2561 x86_pmu_disable_event(event);
2562 break;
2563 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2564 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2565 intel_pmu_disable_fixed(event);
2566 break;
2567 case INTEL_PMC_IDX_FIXED_BTS:
2568 intel_pmu_disable_bts();
2569 intel_pmu_drain_bts_buffer();
2570 return;
2571 case INTEL_PMC_IDX_FIXED_VLBR:
2572 intel_clear_masks(event, idx);
2573 break;
2574 default:
2575 intel_clear_masks(event, idx);
2576 pr_warn("Failed to disable the event with invalid index %d\n",
2577 idx);
2578 return;
2579 }
2580
2581 /*
2582 * Needs to be called after x86_pmu_disable_event,
2583 * so we don't trigger the event without PEBS bit set.
2584 */
2585 if (unlikely(event->attr.precise_ip))
2586 intel_pmu_pebs_disable(event);
2587 }
2588
intel_pmu_assign_event(struct perf_event * event,int idx)2589 static void intel_pmu_assign_event(struct perf_event *event, int idx)
2590 {
2591 if (is_pebs_pt(event))
2592 perf_report_aux_output_id(event, idx);
2593 }
2594
intel_pmu_needs_branch_stack(struct perf_event * event)2595 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event)
2596 {
2597 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK;
2598 }
2599
intel_pmu_del_event(struct perf_event * event)2600 static void intel_pmu_del_event(struct perf_event *event)
2601 {
2602 if (intel_pmu_needs_branch_stack(event))
2603 intel_pmu_lbr_del(event);
2604 if (event->attr.precise_ip)
2605 intel_pmu_pebs_del(event);
2606 }
2607
icl_set_topdown_event_period(struct perf_event * event)2608 static int icl_set_topdown_event_period(struct perf_event *event)
2609 {
2610 struct hw_perf_event *hwc = &event->hw;
2611 s64 left = local64_read(&hwc->period_left);
2612
2613 /*
2614 * The values in PERF_METRICS MSR are derived from fixed counter 3.
2615 * Software should start both registers, PERF_METRICS and fixed
2616 * counter 3, from zero.
2617 * Clear PERF_METRICS and Fixed counter 3 in initialization.
2618 * After that, both MSRs will be cleared for each read.
2619 * Don't need to clear them again.
2620 */
2621 if (left == x86_pmu.max_period) {
2622 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2623 wrmsrl(MSR_PERF_METRICS, 0);
2624 hwc->saved_slots = 0;
2625 hwc->saved_metric = 0;
2626 }
2627
2628 if ((hwc->saved_slots) && is_slots_event(event)) {
2629 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2630 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2631 }
2632
2633 perf_event_update_userpage(event);
2634
2635 return 0;
2636 }
2637
2638 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);
2639
icl_get_metrics_event_value(u64 metric,u64 slots,int idx)2640 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2641 {
2642 u32 val;
2643
2644 /*
2645 * The metric is reported as an 8bit integer fraction
2646 * summing up to 0xff.
2647 * slots-in-metric = (Metric / 0xff) * slots
2648 */
2649 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2650 return mul_u64_u32_div(slots, val, 0xff);
2651 }
2652
icl_get_topdown_value(struct perf_event * event,u64 slots,u64 metrics)2653 static u64 icl_get_topdown_value(struct perf_event *event,
2654 u64 slots, u64 metrics)
2655 {
2656 int idx = event->hw.idx;
2657 u64 delta;
2658
2659 if (is_metric_idx(idx))
2660 delta = icl_get_metrics_event_value(metrics, slots, idx);
2661 else
2662 delta = slots;
2663
2664 return delta;
2665 }
2666
__icl_update_topdown_event(struct perf_event * event,u64 slots,u64 metrics,u64 last_slots,u64 last_metrics)2667 static void __icl_update_topdown_event(struct perf_event *event,
2668 u64 slots, u64 metrics,
2669 u64 last_slots, u64 last_metrics)
2670 {
2671 u64 delta, last = 0;
2672
2673 delta = icl_get_topdown_value(event, slots, metrics);
2674 if (last_slots)
2675 last = icl_get_topdown_value(event, last_slots, last_metrics);
2676
2677 /*
2678 * The 8bit integer fraction of metric may be not accurate,
2679 * especially when the changes is very small.
2680 * For example, if only a few bad_spec happens, the fraction
2681 * may be reduced from 1 to 0. If so, the bad_spec event value
2682 * will be 0 which is definitely less than the last value.
2683 * Avoid update event->count for this case.
2684 */
2685 if (delta > last) {
2686 delta -= last;
2687 local64_add(delta, &event->count);
2688 }
2689 }
2690
update_saved_topdown_regs(struct perf_event * event,u64 slots,u64 metrics,int metric_end)2691 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2692 u64 metrics, int metric_end)
2693 {
2694 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2695 struct perf_event *other;
2696 int idx;
2697
2698 event->hw.saved_slots = slots;
2699 event->hw.saved_metric = metrics;
2700
2701 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2702 if (!is_topdown_idx(idx))
2703 continue;
2704 other = cpuc->events[idx];
2705 other->hw.saved_slots = slots;
2706 other->hw.saved_metric = metrics;
2707 }
2708 }
2709
2710 /*
2711 * Update all active Topdown events.
2712 *
2713 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2714 * modify by a NMI. PMU has to be disabled before calling this function.
2715 */
2716
intel_update_topdown_event(struct perf_event * event,int metric_end)2717 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end)
2718 {
2719 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2720 struct perf_event *other;
2721 u64 slots, metrics;
2722 bool reset = true;
2723 int idx;
2724
2725 /* read Fixed counter 3 */
2726 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2727 if (!slots)
2728 return 0;
2729
2730 /* read PERF_METRICS */
2731 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2732
2733 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2734 if (!is_topdown_idx(idx))
2735 continue;
2736 other = cpuc->events[idx];
2737 __icl_update_topdown_event(other, slots, metrics,
2738 event ? event->hw.saved_slots : 0,
2739 event ? event->hw.saved_metric : 0);
2740 }
2741
2742 /*
2743 * Check and update this event, which may have been cleared
2744 * in active_mask e.g. x86_pmu_stop()
2745 */
2746 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2747 __icl_update_topdown_event(event, slots, metrics,
2748 event->hw.saved_slots,
2749 event->hw.saved_metric);
2750
2751 /*
2752 * In x86_pmu_stop(), the event is cleared in active_mask first,
2753 * then drain the delta, which indicates context switch for
2754 * counting.
2755 * Save metric and slots for context switch.
2756 * Don't need to reset the PERF_METRICS and Fixed counter 3.
2757 * Because the values will be restored in next schedule in.
2758 */
2759 update_saved_topdown_regs(event, slots, metrics, metric_end);
2760 reset = false;
2761 }
2762
2763 if (reset) {
2764 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2765 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2766 wrmsrl(MSR_PERF_METRICS, 0);
2767 if (event)
2768 update_saved_topdown_regs(event, 0, 0, metric_end);
2769 }
2770
2771 return slots;
2772 }
2773
icl_update_topdown_event(struct perf_event * event)2774 static u64 icl_update_topdown_event(struct perf_event *event)
2775 {
2776 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2777 x86_pmu.num_topdown_events - 1);
2778 }
2779
2780 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, x86_perf_event_update);
2781
intel_pmu_read_event(struct perf_event * event)2782 static void intel_pmu_read_event(struct perf_event *event)
2783 {
2784 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN)) {
2785 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2786 bool pmu_enabled = cpuc->enabled;
2787
2788 /* Only need to call update_topdown_event() once for group read. */
2789 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ))
2790 return;
2791
2792 cpuc->enabled = 0;
2793 if (pmu_enabled)
2794 intel_pmu_disable_all();
2795
2796 if (is_topdown_event(event))
2797 static_call(intel_pmu_update_topdown_event)(event);
2798 else
2799 intel_pmu_drain_pebs_buffer();
2800
2801 cpuc->enabled = pmu_enabled;
2802 if (pmu_enabled)
2803 intel_pmu_enable_all(0);
2804
2805 return;
2806 }
2807
2808 x86_perf_event_update(event);
2809 }
2810
intel_pmu_enable_fixed(struct perf_event * event)2811 static void intel_pmu_enable_fixed(struct perf_event *event)
2812 {
2813 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2814 struct hw_perf_event *hwc = &event->hw;
2815 u64 mask, bits = 0;
2816 int idx = hwc->idx;
2817
2818 if (is_topdown_idx(idx)) {
2819 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2820 /*
2821 * When there are other active TopDown events,
2822 * don't enable the fixed counter 3 again.
2823 */
2824 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2825 return;
2826
2827 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2828
2829 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR)
2830 bits |= INTEL_FIXED_3_METRICS_CLEAR;
2831 }
2832
2833 intel_set_masks(event, idx);
2834
2835 /*
2836 * Enable IRQ generation (0x8), if not PEBS,
2837 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2838 * if requested:
2839 */
2840 if (!event->attr.precise_ip)
2841 bits |= INTEL_FIXED_0_ENABLE_PMI;
2842 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2843 bits |= INTEL_FIXED_0_USER;
2844 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2845 bits |= INTEL_FIXED_0_KERNEL;
2846
2847 /*
2848 * ANY bit is supported in v3 and up
2849 */
2850 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2851 bits |= INTEL_FIXED_0_ANYTHREAD;
2852
2853 idx -= INTEL_PMC_IDX_FIXED;
2854 bits = intel_fixed_bits_by_idx(idx, bits);
2855 mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);
2856
2857 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2858 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2859 mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2860 }
2861
2862 cpuc->fixed_ctrl_val &= ~mask;
2863 cpuc->fixed_ctrl_val |= bits;
2864 }
2865
intel_pmu_enable_event(struct perf_event * event)2866 static void intel_pmu_enable_event(struct perf_event *event)
2867 {
2868 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE;
2869 struct hw_perf_event *hwc = &event->hw;
2870 int idx = hwc->idx;
2871
2872 if (unlikely(event->attr.precise_ip))
2873 intel_pmu_pebs_enable(event);
2874
2875 switch (idx) {
2876 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2877 if (branch_sample_counters(event))
2878 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR;
2879 intel_set_masks(event, idx);
2880 __x86_pmu_enable_event(hwc, enable_mask);
2881 break;
2882 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2883 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2884 intel_pmu_enable_fixed(event);
2885 break;
2886 case INTEL_PMC_IDX_FIXED_BTS:
2887 if (!__this_cpu_read(cpu_hw_events.enabled))
2888 return;
2889 intel_pmu_enable_bts(hwc->config);
2890 break;
2891 case INTEL_PMC_IDX_FIXED_VLBR:
2892 intel_set_masks(event, idx);
2893 break;
2894 default:
2895 pr_warn("Failed to enable the event with invalid index %d\n",
2896 idx);
2897 }
2898 }
2899
intel_pmu_add_event(struct perf_event * event)2900 static void intel_pmu_add_event(struct perf_event *event)
2901 {
2902 if (event->attr.precise_ip)
2903 intel_pmu_pebs_add(event);
2904 if (intel_pmu_needs_branch_stack(event))
2905 intel_pmu_lbr_add(event);
2906 }
2907
2908 /*
2909 * Save and restart an expired event. Called by NMI contexts,
2910 * so it has to be careful about preempting normal event ops:
2911 */
intel_pmu_save_and_restart(struct perf_event * event)2912 int intel_pmu_save_and_restart(struct perf_event *event)
2913 {
2914 static_call(x86_pmu_update)(event);
2915 /*
2916 * For a checkpointed counter always reset back to 0. This
2917 * avoids a situation where the counter overflows, aborts the
2918 * transaction and is then set back to shortly before the
2919 * overflow, and overflows and aborts again.
2920 */
2921 if (unlikely(event_is_checkpointed(event))) {
2922 /* No race with NMIs because the counter should not be armed */
2923 wrmsrl(event->hw.event_base, 0);
2924 local64_set(&event->hw.prev_count, 0);
2925 }
2926 return static_call(x86_pmu_set_period)(event);
2927 }
2928
intel_pmu_set_period(struct perf_event * event)2929 static int intel_pmu_set_period(struct perf_event *event)
2930 {
2931 if (unlikely(is_topdown_count(event)))
2932 return static_call(intel_pmu_set_topdown_event_period)(event);
2933
2934 return x86_perf_event_set_period(event);
2935 }
2936
intel_pmu_update(struct perf_event * event)2937 static u64 intel_pmu_update(struct perf_event *event)
2938 {
2939 if (unlikely(is_topdown_count(event)))
2940 return static_call(intel_pmu_update_topdown_event)(event);
2941
2942 return x86_perf_event_update(event);
2943 }
2944
intel_pmu_reset(void)2945 static void intel_pmu_reset(void)
2946 {
2947 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2948 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2949 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);
2950 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);
2951 unsigned long flags;
2952 int idx;
2953
2954 if (!*(u64 *)cntr_mask)
2955 return;
2956
2957 local_irq_save(flags);
2958
2959 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2960
2961 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) {
2962 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2963 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2964 }
2965 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) {
2966 if (fixed_counter_disabled(idx, cpuc->pmu))
2967 continue;
2968 wrmsrl_safe(x86_pmu_fixed_ctr_addr(idx), 0ull);
2969 }
2970
2971 if (ds)
2972 ds->bts_index = ds->bts_buffer_base;
2973
2974 /* Ack all overflows and disable fixed counters */
2975 if (x86_pmu.version >= 2) {
2976 intel_pmu_ack_status(intel_pmu_get_status());
2977 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2978 }
2979
2980 /* Reset LBRs and LBR freezing */
2981 if (x86_pmu.lbr_nr) {
2982 update_debugctlmsr(get_debugctlmsr() &
2983 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2984 }
2985
2986 local_irq_restore(flags);
2987 }
2988
2989 /*
2990 * We may be running with guest PEBS events created by KVM, and the
2991 * PEBS records are logged into the guest's DS and invisible to host.
2992 *
2993 * In the case of guest PEBS overflow, we only trigger a fake event
2994 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
2995 * The guest will then vm-entry and check the guest DS area to read
2996 * the guest PEBS records.
2997 *
2998 * The contents and other behavior of the guest event do not matter.
2999 */
x86_pmu_handle_guest_pebs(struct pt_regs * regs,struct perf_sample_data * data)3000 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
3001 struct perf_sample_data *data)
3002 {
3003 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3004 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
3005 struct perf_event *event = NULL;
3006 int bit;
3007
3008 if (!unlikely(perf_guest_state()))
3009 return;
3010
3011 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
3012 !guest_pebs_idxs)
3013 return;
3014
3015 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) {
3016 event = cpuc->events[bit];
3017 if (!event->attr.precise_ip)
3018 continue;
3019
3020 perf_sample_data_init(data, 0, event->hw.last_period);
3021 if (perf_event_overflow(event, data, regs))
3022 x86_pmu_stop(event, 0);
3023
3024 /* Inject one fake event is enough. */
3025 break;
3026 }
3027 }
3028
handle_pmi_common(struct pt_regs * regs,u64 status)3029 static int handle_pmi_common(struct pt_regs *regs, u64 status)
3030 {
3031 struct perf_sample_data data;
3032 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3033 int bit;
3034 int handled = 0;
3035 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
3036
3037 inc_irq_stat(apic_perf_irqs);
3038
3039 /*
3040 * Ignore a range of extra bits in status that do not indicate
3041 * overflow by themselves.
3042 */
3043 status &= ~(GLOBAL_STATUS_COND_CHG |
3044 GLOBAL_STATUS_ASIF |
3045 GLOBAL_STATUS_LBRS_FROZEN);
3046 if (!status)
3047 return 0;
3048 /*
3049 * In case multiple PEBS events are sampled at the same time,
3050 * it is possible to have GLOBAL_STATUS bit 62 set indicating
3051 * PEBS buffer overflow and also seeing at most 3 PEBS counters
3052 * having their bits set in the status register. This is a sign
3053 * that there was at least one PEBS record pending at the time
3054 * of the PMU interrupt. PEBS counters must only be processed
3055 * via the drain_pebs() calls and not via the regular sample
3056 * processing loop coming after that the function, otherwise
3057 * phony regular samples may be generated in the sampling buffer
3058 * not marked with the EXACT tag. Another possibility is to have
3059 * one PEBS event and at least one non-PEBS event which overflows
3060 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
3061 * not be set, yet the overflow status bit for the PEBS counter will
3062 * be on Skylake.
3063 *
3064 * To avoid this problem, we systematically ignore the PEBS-enabled
3065 * counters from the GLOBAL_STATUS mask and we always process PEBS
3066 * events via drain_pebs().
3067 */
3068 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
3069
3070 /*
3071 * PEBS overflow sets bit 62 in the global status register
3072 */
3073 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
3074 u64 pebs_enabled = cpuc->pebs_enabled;
3075
3076 handled++;
3077 x86_pmu_handle_guest_pebs(regs, &data);
3078 static_call(x86_pmu_drain_pebs)(regs, &data);
3079 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
3080
3081 /*
3082 * PMI throttle may be triggered, which stops the PEBS event.
3083 * Although cpuc->pebs_enabled is updated accordingly, the
3084 * MSR_IA32_PEBS_ENABLE is not updated. Because the
3085 * cpuc->enabled has been forced to 0 in PMI.
3086 * Update the MSR if pebs_enabled is changed.
3087 */
3088 if (pebs_enabled != cpuc->pebs_enabled)
3089 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
3090 }
3091
3092 /*
3093 * Intel PT
3094 */
3095 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
3096 handled++;
3097 if (!perf_guest_handle_intel_pt_intr())
3098 intel_pt_interrupt();
3099 }
3100
3101 /*
3102 * Intel Perf metrics
3103 */
3104 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
3105 handled++;
3106 static_call(intel_pmu_update_topdown_event)(NULL);
3107 }
3108
3109 /*
3110 * Checkpointed counters can lead to 'spurious' PMIs because the
3111 * rollback caused by the PMI will have cleared the overflow status
3112 * bit. Therefore always force probe these counters.
3113 */
3114 status |= cpuc->intel_cp_status;
3115
3116 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
3117 struct perf_event *event = cpuc->events[bit];
3118
3119 handled++;
3120
3121 if (!test_bit(bit, cpuc->active_mask))
3122 continue;
3123
3124 if (!intel_pmu_save_and_restart(event))
3125 continue;
3126
3127 perf_sample_data_init(&data, 0, event->hw.last_period);
3128
3129 if (has_branch_stack(event))
3130 intel_pmu_lbr_save_brstack(&data, cpuc, event);
3131
3132 if (perf_event_overflow(event, &data, regs))
3133 x86_pmu_stop(event, 0);
3134 }
3135
3136 return handled;
3137 }
3138
3139 /*
3140 * This handler is triggered by the local APIC, so the APIC IRQ handling
3141 * rules apply:
3142 */
intel_pmu_handle_irq(struct pt_regs * regs)3143 static int intel_pmu_handle_irq(struct pt_regs *regs)
3144 {
3145 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3146 bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
3147 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
3148 int loops;
3149 u64 status;
3150 int handled;
3151 int pmu_enabled;
3152
3153 /*
3154 * Save the PMU state.
3155 * It needs to be restored when leaving the handler.
3156 */
3157 pmu_enabled = cpuc->enabled;
3158 /*
3159 * In general, the early ACK is only applied for old platforms.
3160 * For the big core starts from Haswell, the late ACK should be
3161 * applied.
3162 * For the small core after Tremont, we have to do the ACK right
3163 * before re-enabling counters, which is in the middle of the
3164 * NMI handler.
3165 */
3166 if (!late_ack && !mid_ack)
3167 apic_write(APIC_LVTPC, APIC_DM_NMI);
3168 intel_bts_disable_local();
3169 cpuc->enabled = 0;
3170 __intel_pmu_disable_all(true);
3171 handled = intel_pmu_drain_bts_buffer();
3172 handled += intel_bts_interrupt();
3173 status = intel_pmu_get_status();
3174 if (!status)
3175 goto done;
3176
3177 loops = 0;
3178 again:
3179 intel_pmu_lbr_read();
3180 intel_pmu_ack_status(status);
3181 if (++loops > 100) {
3182 static bool warned;
3183
3184 if (!warned) {
3185 WARN(1, "perfevents: irq loop stuck!\n");
3186 perf_event_print_debug();
3187 warned = true;
3188 }
3189 intel_pmu_reset();
3190 goto done;
3191 }
3192
3193 handled += handle_pmi_common(regs, status);
3194
3195 /*
3196 * Repeat if there is more work to be done:
3197 */
3198 status = intel_pmu_get_status();
3199 if (status)
3200 goto again;
3201
3202 done:
3203 if (mid_ack)
3204 apic_write(APIC_LVTPC, APIC_DM_NMI);
3205 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
3206 cpuc->enabled = pmu_enabled;
3207 if (pmu_enabled)
3208 __intel_pmu_enable_all(0, true);
3209 intel_bts_enable_local();
3210
3211 /*
3212 * Only unmask the NMI after the overflow counters
3213 * have been reset. This avoids spurious NMIs on
3214 * Haswell CPUs.
3215 */
3216 if (late_ack)
3217 apic_write(APIC_LVTPC, APIC_DM_NMI);
3218 return handled;
3219 }
3220
3221 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)3222 intel_bts_constraints(struct perf_event *event)
3223 {
3224 if (unlikely(intel_pmu_has_bts(event)))
3225 return &bts_constraint;
3226
3227 return NULL;
3228 }
3229
3230 /*
3231 * Note: matches a fake event, like Fixed2.
3232 */
3233 static struct event_constraint *
intel_vlbr_constraints(struct perf_event * event)3234 intel_vlbr_constraints(struct perf_event *event)
3235 {
3236 struct event_constraint *c = &vlbr_constraint;
3237
3238 if (unlikely(constraint_match(c, event->hw.config))) {
3239 event->hw.flags |= c->flags;
3240 return c;
3241 }
3242
3243 return NULL;
3244 }
3245
intel_alt_er(struct cpu_hw_events * cpuc,int idx,u64 config)3246 static int intel_alt_er(struct cpu_hw_events *cpuc,
3247 int idx, u64 config)
3248 {
3249 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
3250 int alt_idx = idx;
3251
3252 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
3253 return idx;
3254
3255 if (idx == EXTRA_REG_RSP_0)
3256 alt_idx = EXTRA_REG_RSP_1;
3257
3258 if (idx == EXTRA_REG_RSP_1)
3259 alt_idx = EXTRA_REG_RSP_0;
3260
3261 if (config & ~extra_regs[alt_idx].valid_mask)
3262 return idx;
3263
3264 return alt_idx;
3265 }
3266
intel_fixup_er(struct perf_event * event,int idx)3267 static void intel_fixup_er(struct perf_event *event, int idx)
3268 {
3269 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
3270 event->hw.extra_reg.idx = idx;
3271
3272 if (idx == EXTRA_REG_RSP_0) {
3273 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3274 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
3275 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
3276 } else if (idx == EXTRA_REG_RSP_1) {
3277 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3278 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3279 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3280 }
3281 }
3282
3283 /*
3284 * manage allocation of shared extra msr for certain events
3285 *
3286 * sharing can be:
3287 * per-cpu: to be shared between the various events on a single PMU
3288 * per-core: per-cpu + shared by HT threads
3289 */
3290 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)3291 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3292 struct perf_event *event,
3293 struct hw_perf_event_extra *reg)
3294 {
3295 struct event_constraint *c = &emptyconstraint;
3296 struct er_account *era;
3297 unsigned long flags;
3298 int idx = reg->idx;
3299
3300 /*
3301 * reg->alloc can be set due to existing state, so for fake cpuc we
3302 * need to ignore this, otherwise we might fail to allocate proper fake
3303 * state for this extra reg constraint. Also see the comment below.
3304 */
3305 if (reg->alloc && !cpuc->is_fake)
3306 return NULL; /* call x86_get_event_constraint() */
3307
3308 again:
3309 era = &cpuc->shared_regs->regs[idx];
3310 /*
3311 * we use spin_lock_irqsave() to avoid lockdep issues when
3312 * passing a fake cpuc
3313 */
3314 raw_spin_lock_irqsave(&era->lock, flags);
3315
3316 if (!atomic_read(&era->ref) || era->config == reg->config) {
3317
3318 /*
3319 * If its a fake cpuc -- as per validate_{group,event}() we
3320 * shouldn't touch event state and we can avoid doing so
3321 * since both will only call get_event_constraints() once
3322 * on each event, this avoids the need for reg->alloc.
3323 *
3324 * Not doing the ER fixup will only result in era->reg being
3325 * wrong, but since we won't actually try and program hardware
3326 * this isn't a problem either.
3327 */
3328 if (!cpuc->is_fake) {
3329 if (idx != reg->idx)
3330 intel_fixup_er(event, idx);
3331
3332 /*
3333 * x86_schedule_events() can call get_event_constraints()
3334 * multiple times on events in the case of incremental
3335 * scheduling(). reg->alloc ensures we only do the ER
3336 * allocation once.
3337 */
3338 reg->alloc = 1;
3339 }
3340
3341 /* lock in msr value */
3342 era->config = reg->config;
3343 era->reg = reg->reg;
3344
3345 /* one more user */
3346 atomic_inc(&era->ref);
3347
3348 /*
3349 * need to call x86_get_event_constraint()
3350 * to check if associated event has constraints
3351 */
3352 c = NULL;
3353 } else {
3354 idx = intel_alt_er(cpuc, idx, reg->config);
3355 if (idx != reg->idx) {
3356 raw_spin_unlock_irqrestore(&era->lock, flags);
3357 goto again;
3358 }
3359 }
3360 raw_spin_unlock_irqrestore(&era->lock, flags);
3361
3362 return c;
3363 }
3364
3365 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)3366 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3367 struct hw_perf_event_extra *reg)
3368 {
3369 struct er_account *era;
3370
3371 /*
3372 * Only put constraint if extra reg was actually allocated. Also takes
3373 * care of event which do not use an extra shared reg.
3374 *
3375 * Also, if this is a fake cpuc we shouldn't touch any event state
3376 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3377 * either since it'll be thrown out.
3378 */
3379 if (!reg->alloc || cpuc->is_fake)
3380 return;
3381
3382 era = &cpuc->shared_regs->regs[reg->idx];
3383
3384 /* one fewer user */
3385 atomic_dec(&era->ref);
3386
3387 /* allocate again next time */
3388 reg->alloc = 0;
3389 }
3390
3391 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3392 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3393 struct perf_event *event)
3394 {
3395 struct event_constraint *c = NULL, *d;
3396 struct hw_perf_event_extra *xreg, *breg;
3397
3398 xreg = &event->hw.extra_reg;
3399 if (xreg->idx != EXTRA_REG_NONE) {
3400 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3401 if (c == &emptyconstraint)
3402 return c;
3403 }
3404 breg = &event->hw.branch_reg;
3405 if (breg->idx != EXTRA_REG_NONE) {
3406 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3407 if (d == &emptyconstraint) {
3408 __intel_shared_reg_put_constraints(cpuc, xreg);
3409 c = d;
3410 }
3411 }
3412 return c;
3413 }
3414
3415 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3416 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3417 struct perf_event *event)
3418 {
3419 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3420 struct event_constraint *c;
3421
3422 if (event_constraints) {
3423 for_each_event_constraint(c, event_constraints) {
3424 if (constraint_match(c, event->hw.config)) {
3425 event->hw.flags |= c->flags;
3426 return c;
3427 }
3428 }
3429 }
3430
3431 return &hybrid_var(cpuc->pmu, unconstrained);
3432 }
3433
3434 static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3435 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3436 struct perf_event *event)
3437 {
3438 struct event_constraint *c;
3439
3440 c = intel_vlbr_constraints(event);
3441 if (c)
3442 return c;
3443
3444 c = intel_bts_constraints(event);
3445 if (c)
3446 return c;
3447
3448 c = intel_shared_regs_constraints(cpuc, event);
3449 if (c)
3450 return c;
3451
3452 c = intel_pebs_constraints(event);
3453 if (c)
3454 return c;
3455
3456 return x86_get_event_constraints(cpuc, idx, event);
3457 }
3458
3459 static void
intel_start_scheduling(struct cpu_hw_events * cpuc)3460 intel_start_scheduling(struct cpu_hw_events *cpuc)
3461 {
3462 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3463 struct intel_excl_states *xl;
3464 int tid = cpuc->excl_thread_id;
3465
3466 /*
3467 * nothing needed if in group validation mode
3468 */
3469 if (cpuc->is_fake || !is_ht_workaround_enabled())
3470 return;
3471
3472 /*
3473 * no exclusion needed
3474 */
3475 if (WARN_ON_ONCE(!excl_cntrs))
3476 return;
3477
3478 xl = &excl_cntrs->states[tid];
3479
3480 xl->sched_started = true;
3481 /*
3482 * lock shared state until we are done scheduling
3483 * in stop_event_scheduling()
3484 * makes scheduling appear as a transaction
3485 */
3486 raw_spin_lock(&excl_cntrs->lock);
3487 }
3488
intel_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)3489 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3490 {
3491 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3492 struct event_constraint *c = cpuc->event_constraint[idx];
3493 struct intel_excl_states *xl;
3494 int tid = cpuc->excl_thread_id;
3495
3496 if (cpuc->is_fake || !is_ht_workaround_enabled())
3497 return;
3498
3499 if (WARN_ON_ONCE(!excl_cntrs))
3500 return;
3501
3502 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3503 return;
3504
3505 xl = &excl_cntrs->states[tid];
3506
3507 lockdep_assert_held(&excl_cntrs->lock);
3508
3509 if (c->flags & PERF_X86_EVENT_EXCL)
3510 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3511 else
3512 xl->state[cntr] = INTEL_EXCL_SHARED;
3513 }
3514
3515 static void
intel_stop_scheduling(struct cpu_hw_events * cpuc)3516 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3517 {
3518 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3519 struct intel_excl_states *xl;
3520 int tid = cpuc->excl_thread_id;
3521
3522 /*
3523 * nothing needed if in group validation mode
3524 */
3525 if (cpuc->is_fake || !is_ht_workaround_enabled())
3526 return;
3527 /*
3528 * no exclusion needed
3529 */
3530 if (WARN_ON_ONCE(!excl_cntrs))
3531 return;
3532
3533 xl = &excl_cntrs->states[tid];
3534
3535 xl->sched_started = false;
3536 /*
3537 * release shared state lock (acquired in intel_start_scheduling())
3538 */
3539 raw_spin_unlock(&excl_cntrs->lock);
3540 }
3541
3542 static struct event_constraint *
dyn_constraint(struct cpu_hw_events * cpuc,struct event_constraint * c,int idx)3543 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3544 {
3545 WARN_ON_ONCE(!cpuc->constraint_list);
3546
3547 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3548 struct event_constraint *cx;
3549
3550 /*
3551 * grab pre-allocated constraint entry
3552 */
3553 cx = &cpuc->constraint_list[idx];
3554
3555 /*
3556 * initialize dynamic constraint
3557 * with static constraint
3558 */
3559 *cx = *c;
3560
3561 /*
3562 * mark constraint as dynamic
3563 */
3564 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3565 c = cx;
3566 }
3567
3568 return c;
3569 }
3570
3571 static struct event_constraint *
intel_get_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,int idx,struct event_constraint * c)3572 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3573 int idx, struct event_constraint *c)
3574 {
3575 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3576 struct intel_excl_states *xlo;
3577 int tid = cpuc->excl_thread_id;
3578 int is_excl, i, w;
3579
3580 /*
3581 * validating a group does not require
3582 * enforcing cross-thread exclusion
3583 */
3584 if (cpuc->is_fake || !is_ht_workaround_enabled())
3585 return c;
3586
3587 /*
3588 * no exclusion needed
3589 */
3590 if (WARN_ON_ONCE(!excl_cntrs))
3591 return c;
3592
3593 /*
3594 * because we modify the constraint, we need
3595 * to make a copy. Static constraints come
3596 * from static const tables.
3597 *
3598 * only needed when constraint has not yet
3599 * been cloned (marked dynamic)
3600 */
3601 c = dyn_constraint(cpuc, c, idx);
3602
3603 /*
3604 * From here on, the constraint is dynamic.
3605 * Either it was just allocated above, or it
3606 * was allocated during a earlier invocation
3607 * of this function
3608 */
3609
3610 /*
3611 * state of sibling HT
3612 */
3613 xlo = &excl_cntrs->states[tid ^ 1];
3614
3615 /*
3616 * event requires exclusive counter access
3617 * across HT threads
3618 */
3619 is_excl = c->flags & PERF_X86_EVENT_EXCL;
3620 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3621 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3622 if (!cpuc->n_excl++)
3623 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3624 }
3625
3626 /*
3627 * Modify static constraint with current dynamic
3628 * state of thread
3629 *
3630 * EXCLUSIVE: sibling counter measuring exclusive event
3631 * SHARED : sibling counter measuring non-exclusive event
3632 * UNUSED : sibling counter unused
3633 */
3634 w = c->weight;
3635 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3636 /*
3637 * exclusive event in sibling counter
3638 * our corresponding counter cannot be used
3639 * regardless of our event
3640 */
3641 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3642 __clear_bit(i, c->idxmsk);
3643 w--;
3644 continue;
3645 }
3646 /*
3647 * if measuring an exclusive event, sibling
3648 * measuring non-exclusive, then counter cannot
3649 * be used
3650 */
3651 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3652 __clear_bit(i, c->idxmsk);
3653 w--;
3654 continue;
3655 }
3656 }
3657
3658 /*
3659 * if we return an empty mask, then switch
3660 * back to static empty constraint to avoid
3661 * the cost of freeing later on
3662 */
3663 if (!w)
3664 c = &emptyconstraint;
3665
3666 c->weight = w;
3667
3668 return c;
3669 }
3670
3671 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3672 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3673 struct perf_event *event)
3674 {
3675 struct event_constraint *c1, *c2;
3676
3677 c1 = cpuc->event_constraint[idx];
3678
3679 /*
3680 * first time only
3681 * - static constraint: no change across incremental scheduling calls
3682 * - dynamic constraint: handled by intel_get_excl_constraints()
3683 */
3684 c2 = __intel_get_event_constraints(cpuc, idx, event);
3685 if (c1) {
3686 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3687 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3688 c1->weight = c2->weight;
3689 c2 = c1;
3690 }
3691
3692 if (cpuc->excl_cntrs)
3693 return intel_get_excl_constraints(cpuc, event, idx, c2);
3694
3695 /* Not all counters support the branch counter feature. */
3696 if (branch_sample_counters(event)) {
3697 c2 = dyn_constraint(cpuc, c2, idx);
3698 c2->idxmsk64 &= x86_pmu.lbr_counters;
3699 c2->weight = hweight64(c2->idxmsk64);
3700 }
3701
3702 return c2;
3703 }
3704
intel_put_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3705 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3706 struct perf_event *event)
3707 {
3708 struct hw_perf_event *hwc = &event->hw;
3709 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3710 int tid = cpuc->excl_thread_id;
3711 struct intel_excl_states *xl;
3712
3713 /*
3714 * nothing needed if in group validation mode
3715 */
3716 if (cpuc->is_fake)
3717 return;
3718
3719 if (WARN_ON_ONCE(!excl_cntrs))
3720 return;
3721
3722 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3723 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3724 if (!--cpuc->n_excl)
3725 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3726 }
3727
3728 /*
3729 * If event was actually assigned, then mark the counter state as
3730 * unused now.
3731 */
3732 if (hwc->idx >= 0) {
3733 xl = &excl_cntrs->states[tid];
3734
3735 /*
3736 * put_constraint may be called from x86_schedule_events()
3737 * which already has the lock held so here make locking
3738 * conditional.
3739 */
3740 if (!xl->sched_started)
3741 raw_spin_lock(&excl_cntrs->lock);
3742
3743 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3744
3745 if (!xl->sched_started)
3746 raw_spin_unlock(&excl_cntrs->lock);
3747 }
3748 }
3749
3750 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3751 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3752 struct perf_event *event)
3753 {
3754 struct hw_perf_event_extra *reg;
3755
3756 reg = &event->hw.extra_reg;
3757 if (reg->idx != EXTRA_REG_NONE)
3758 __intel_shared_reg_put_constraints(cpuc, reg);
3759
3760 reg = &event->hw.branch_reg;
3761 if (reg->idx != EXTRA_REG_NONE)
3762 __intel_shared_reg_put_constraints(cpuc, reg);
3763 }
3764
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3765 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3766 struct perf_event *event)
3767 {
3768 intel_put_shared_regs_event_constraints(cpuc, event);
3769
3770 /*
3771 * is PMU has exclusive counter restrictions, then
3772 * all events are subject to and must call the
3773 * put_excl_constraints() routine
3774 */
3775 if (cpuc->excl_cntrs)
3776 intel_put_excl_constraints(cpuc, event);
3777 }
3778
intel_pebs_aliases_core2(struct perf_event * event)3779 static void intel_pebs_aliases_core2(struct perf_event *event)
3780 {
3781 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3782 /*
3783 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3784 * (0x003c) so that we can use it with PEBS.
3785 *
3786 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3787 * PEBS capable. However we can use INST_RETIRED.ANY_P
3788 * (0x00c0), which is a PEBS capable event, to get the same
3789 * count.
3790 *
3791 * INST_RETIRED.ANY_P counts the number of cycles that retires
3792 * CNTMASK instructions. By setting CNTMASK to a value (16)
3793 * larger than the maximum number of instructions that can be
3794 * retired per cycle (4) and then inverting the condition, we
3795 * count all cycles that retire 16 or less instructions, which
3796 * is every cycle.
3797 *
3798 * Thereby we gain a PEBS capable cycle counter.
3799 */
3800 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3801
3802 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3803 event->hw.config = alt_config;
3804 }
3805 }
3806
intel_pebs_aliases_snb(struct perf_event * event)3807 static void intel_pebs_aliases_snb(struct perf_event *event)
3808 {
3809 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3810 /*
3811 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3812 * (0x003c) so that we can use it with PEBS.
3813 *
3814 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3815 * PEBS capable. However we can use UOPS_RETIRED.ALL
3816 * (0x01c2), which is a PEBS capable event, to get the same
3817 * count.
3818 *
3819 * UOPS_RETIRED.ALL counts the number of cycles that retires
3820 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3821 * larger than the maximum number of micro-ops that can be
3822 * retired per cycle (4) and then inverting the condition, we
3823 * count all cycles that retire 16 or less micro-ops, which
3824 * is every cycle.
3825 *
3826 * Thereby we gain a PEBS capable cycle counter.
3827 */
3828 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3829
3830 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3831 event->hw.config = alt_config;
3832 }
3833 }
3834
intel_pebs_aliases_precdist(struct perf_event * event)3835 static void intel_pebs_aliases_precdist(struct perf_event *event)
3836 {
3837 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3838 /*
3839 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3840 * (0x003c) so that we can use it with PEBS.
3841 *
3842 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3843 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3844 * (0x01c0), which is a PEBS capable event, to get the same
3845 * count.
3846 *
3847 * The PREC_DIST event has special support to minimize sample
3848 * shadowing effects. One drawback is that it can be
3849 * only programmed on counter 1, but that seems like an
3850 * acceptable trade off.
3851 */
3852 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3853
3854 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3855 event->hw.config = alt_config;
3856 }
3857 }
3858
intel_pebs_aliases_ivb(struct perf_event * event)3859 static void intel_pebs_aliases_ivb(struct perf_event *event)
3860 {
3861 if (event->attr.precise_ip < 3)
3862 return intel_pebs_aliases_snb(event);
3863 return intel_pebs_aliases_precdist(event);
3864 }
3865
intel_pebs_aliases_skl(struct perf_event * event)3866 static void intel_pebs_aliases_skl(struct perf_event *event)
3867 {
3868 if (event->attr.precise_ip < 3)
3869 return intel_pebs_aliases_core2(event);
3870 return intel_pebs_aliases_precdist(event);
3871 }
3872
intel_pmu_large_pebs_flags(struct perf_event * event)3873 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3874 {
3875 unsigned long flags = x86_pmu.large_pebs_flags;
3876
3877 if (event->attr.use_clockid)
3878 flags &= ~PERF_SAMPLE_TIME;
3879 if (!event->attr.exclude_kernel)
3880 flags &= ~PERF_SAMPLE_REGS_USER;
3881 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3882 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3883 return flags;
3884 }
3885
intel_pmu_bts_config(struct perf_event * event)3886 static int intel_pmu_bts_config(struct perf_event *event)
3887 {
3888 struct perf_event_attr *attr = &event->attr;
3889
3890 if (unlikely(intel_pmu_has_bts(event))) {
3891 /* BTS is not supported by this architecture. */
3892 if (!x86_pmu.bts_active)
3893 return -EOPNOTSUPP;
3894
3895 /* BTS is currently only allowed for user-mode. */
3896 if (!attr->exclude_kernel)
3897 return -EOPNOTSUPP;
3898
3899 /* BTS is not allowed for precise events. */
3900 if (attr->precise_ip)
3901 return -EOPNOTSUPP;
3902
3903 /* disallow bts if conflicting events are present */
3904 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3905 return -EBUSY;
3906
3907 event->destroy = hw_perf_lbr_event_destroy;
3908 }
3909
3910 return 0;
3911 }
3912
core_pmu_hw_config(struct perf_event * event)3913 static int core_pmu_hw_config(struct perf_event *event)
3914 {
3915 int ret = x86_pmu_hw_config(event);
3916
3917 if (ret)
3918 return ret;
3919
3920 return intel_pmu_bts_config(event);
3921 }
3922
3923 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
3924 ((x86_pmu.num_topdown_events - 1) << 8))
3925
is_available_metric_event(struct perf_event * event)3926 static bool is_available_metric_event(struct perf_event *event)
3927 {
3928 return is_metric_event(event) &&
3929 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3930 }
3931
is_mem_loads_event(struct perf_event * event)3932 static inline bool is_mem_loads_event(struct perf_event *event)
3933 {
3934 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3935 }
3936
is_mem_loads_aux_event(struct perf_event * event)3937 static inline bool is_mem_loads_aux_event(struct perf_event *event)
3938 {
3939 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3940 }
3941
require_mem_loads_aux_event(struct perf_event * event)3942 static inline bool require_mem_loads_aux_event(struct perf_event *event)
3943 {
3944 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
3945 return false;
3946
3947 if (is_hybrid())
3948 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big;
3949
3950 return true;
3951 }
3952
intel_pmu_has_cap(struct perf_event * event,int idx)3953 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
3954 {
3955 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
3956
3957 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
3958 }
3959
intel_pmu_freq_start_period(struct perf_event * event)3960 static u64 intel_pmu_freq_start_period(struct perf_event *event)
3961 {
3962 int type = event->attr.type;
3963 u64 config, factor;
3964 s64 start;
3965
3966 /*
3967 * The 127 is the lowest possible recommended SAV (sample after value)
3968 * for a 4000 freq (default freq), according to the event list JSON file.
3969 * Also, assume the workload is idle 50% time.
3970 */
3971 factor = 64 * 4000;
3972 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE)
3973 goto end;
3974
3975 /*
3976 * The estimation of the start period in the freq mode is
3977 * based on the below assumption.
3978 *
3979 * For a cycles or an instructions event, 1GHZ of the
3980 * underlying platform, 1 IPC. The workload is idle 50% time.
3981 * The start period = 1,000,000,000 * 1 / freq / 2.
3982 * = 500,000,000 / freq
3983 *
3984 * Usually, the branch-related events occur less than the
3985 * instructions event. According to the Intel event list JSON
3986 * file, the SAV (sample after value) of a branch-related event
3987 * is usually 1/4 of an instruction event.
3988 * The start period of branch-related events = 125,000,000 / freq.
3989 *
3990 * The cache-related events occurs even less. The SAV is usually
3991 * 1/20 of an instruction event.
3992 * The start period of cache-related events = 25,000,000 / freq.
3993 */
3994 config = event->attr.config & PERF_HW_EVENT_MASK;
3995 if (type == PERF_TYPE_HARDWARE) {
3996 switch (config) {
3997 case PERF_COUNT_HW_CPU_CYCLES:
3998 case PERF_COUNT_HW_INSTRUCTIONS:
3999 case PERF_COUNT_HW_BUS_CYCLES:
4000 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND:
4001 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND:
4002 case PERF_COUNT_HW_REF_CPU_CYCLES:
4003 factor = 500000000;
4004 break;
4005 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS:
4006 case PERF_COUNT_HW_BRANCH_MISSES:
4007 factor = 125000000;
4008 break;
4009 case PERF_COUNT_HW_CACHE_REFERENCES:
4010 case PERF_COUNT_HW_CACHE_MISSES:
4011 factor = 25000000;
4012 break;
4013 default:
4014 goto end;
4015 }
4016 }
4017
4018 if (type == PERF_TYPE_HW_CACHE)
4019 factor = 25000000;
4020 end:
4021 /*
4022 * Usually, a prime or a number with less factors (close to prime)
4023 * is chosen as an SAV, which makes it less likely that the sampling
4024 * period synchronizes with some periodic event in the workload.
4025 * Minus 1 to make it at least avoiding values near power of twos
4026 * for the default freq.
4027 */
4028 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1;
4029
4030 if (start > x86_pmu.max_period)
4031 start = x86_pmu.max_period;
4032
4033 if (x86_pmu.limit_period)
4034 x86_pmu.limit_period(event, &start);
4035
4036 return start;
4037 }
4038
intel_pmu_hw_config(struct perf_event * event)4039 static int intel_pmu_hw_config(struct perf_event *event)
4040 {
4041 int ret = x86_pmu_hw_config(event);
4042
4043 if (ret)
4044 return ret;
4045
4046 ret = intel_pmu_bts_config(event);
4047 if (ret)
4048 return ret;
4049
4050 if (event->attr.freq && event->attr.sample_freq) {
4051 event->hw.sample_period = intel_pmu_freq_start_period(event);
4052 event->hw.last_period = event->hw.sample_period;
4053 local64_set(&event->hw.period_left, event->hw.sample_period);
4054 }
4055
4056 if (event->attr.precise_ip) {
4057 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
4058 return -EINVAL;
4059
4060 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
4061 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
4062 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) &&
4063 !has_aux_action(event)) {
4064 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
4065 event->attach_state |= PERF_ATTACH_SCHED_CB;
4066 }
4067 }
4068 if (x86_pmu.pebs_aliases)
4069 x86_pmu.pebs_aliases(event);
4070 }
4071
4072 if (needs_branch_stack(event)) {
4073 /* Avoid branch stack setup for counting events in SAMPLE READ */
4074 if (is_sampling_event(event) ||
4075 !(event->attr.sample_type & PERF_SAMPLE_READ))
4076 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4077 }
4078
4079 if (branch_sample_counters(event)) {
4080 struct perf_event *leader, *sibling;
4081 int num = 0;
4082
4083 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) ||
4084 (event->attr.config & ~INTEL_ARCH_EVENT_MASK))
4085 return -EINVAL;
4086
4087 /*
4088 * The branch counter logging is not supported in the call stack
4089 * mode yet, since we cannot simply flush the LBR during e.g.,
4090 * multiplexing. Also, there is no obvious usage with the call
4091 * stack mode. Simply forbids it for now.
4092 *
4093 * If any events in the group enable the branch counter logging
4094 * feature, the group is treated as a branch counter logging
4095 * group, which requires the extra space to store the counters.
4096 */
4097 leader = event->group_leader;
4098 if (branch_sample_call_stack(leader))
4099 return -EINVAL;
4100 if (branch_sample_counters(leader))
4101 num++;
4102 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS;
4103
4104 for_each_sibling_event(sibling, leader) {
4105 if (branch_sample_call_stack(sibling))
4106 return -EINVAL;
4107 if (branch_sample_counters(sibling))
4108 num++;
4109 }
4110
4111 if (num > fls(x86_pmu.lbr_counters))
4112 return -EINVAL;
4113 /*
4114 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't
4115 * require any branch stack setup.
4116 * Clear the bit to avoid unnecessary branch stack setup.
4117 */
4118 if (0 == (event->attr.branch_sample_type &
4119 ~(PERF_SAMPLE_BRANCH_PLM_ALL |
4120 PERF_SAMPLE_BRANCH_COUNTERS)))
4121 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4122
4123 /*
4124 * Force the leader to be a LBR event. So LBRs can be reset
4125 * with the leader event. See intel_pmu_lbr_del() for details.
4126 */
4127 if (!intel_pmu_needs_branch_stack(leader))
4128 return -EINVAL;
4129 }
4130
4131 if (intel_pmu_needs_branch_stack(event)) {
4132 ret = intel_pmu_setup_lbr_filter(event);
4133 if (ret)
4134 return ret;
4135 event->attach_state |= PERF_ATTACH_SCHED_CB;
4136
4137 /*
4138 * BTS is set up earlier in this path, so don't account twice
4139 */
4140 if (!unlikely(intel_pmu_has_bts(event))) {
4141 /* disallow lbr if conflicting events are present */
4142 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
4143 return -EBUSY;
4144
4145 event->destroy = hw_perf_lbr_event_destroy;
4146 }
4147 }
4148
4149 if (event->attr.aux_output) {
4150 if (!event->attr.precise_ip)
4151 return -EINVAL;
4152
4153 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
4154 }
4155
4156 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
4157 (event->attr.type == PERF_TYPE_HW_CACHE))
4158 return 0;
4159
4160 /*
4161 * Config Topdown slots and metric events
4162 *
4163 * The slots event on Fixed Counter 3 can support sampling,
4164 * which will be handled normally in x86_perf_event_update().
4165 *
4166 * Metric events don't support sampling and require being paired
4167 * with a slots event as group leader. When the slots event
4168 * is used in a metrics group, it too cannot support sampling.
4169 */
4170 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
4171 /* The metrics_clear can only be set for the slots event */
4172 if (event->attr.config1 &&
4173 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR)))
4174 return -EINVAL;
4175
4176 if (event->attr.config2)
4177 return -EINVAL;
4178
4179 /*
4180 * The TopDown metrics events and slots event don't
4181 * support any filters.
4182 */
4183 if (event->attr.config & X86_ALL_EVENT_FLAGS)
4184 return -EINVAL;
4185
4186 if (is_available_metric_event(event)) {
4187 struct perf_event *leader = event->group_leader;
4188
4189 /* The metric events don't support sampling. */
4190 if (is_sampling_event(event))
4191 return -EINVAL;
4192
4193 /* The metric events require a slots group leader. */
4194 if (!is_slots_event(leader))
4195 return -EINVAL;
4196
4197 /*
4198 * The leader/SLOTS must not be a sampling event for
4199 * metric use; hardware requires it starts at 0 when used
4200 * in conjunction with MSR_PERF_METRICS.
4201 */
4202 if (is_sampling_event(leader))
4203 return -EINVAL;
4204
4205 event->event_caps |= PERF_EV_CAP_SIBLING;
4206 /*
4207 * Only once we have a METRICs sibling do we
4208 * need TopDown magic.
4209 */
4210 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
4211 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
4212 }
4213 }
4214
4215 /*
4216 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
4217 * doesn't function quite right. As a work-around it needs to always be
4218 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
4219 * The actual count of this second event is irrelevant it just needs
4220 * to be active to make the first event function correctly.
4221 *
4222 * In a group, the auxiliary event must be in front of the load latency
4223 * event. The rule is to simplify the implementation of the check.
4224 * That's because perf cannot have a complete group at the moment.
4225 */
4226 if (require_mem_loads_aux_event(event) &&
4227 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
4228 is_mem_loads_event(event)) {
4229 struct perf_event *leader = event->group_leader;
4230 struct perf_event *sibling = NULL;
4231
4232 /*
4233 * When this memload event is also the first event (no group
4234 * exists yet), then there is no aux event before it.
4235 */
4236 if (leader == event)
4237 return -ENODATA;
4238
4239 if (!is_mem_loads_aux_event(leader)) {
4240 for_each_sibling_event(sibling, leader) {
4241 if (is_mem_loads_aux_event(sibling))
4242 break;
4243 }
4244 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
4245 return -ENODATA;
4246 }
4247 }
4248
4249 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
4250 return 0;
4251
4252 if (x86_pmu.version < 3)
4253 return -EINVAL;
4254
4255 ret = perf_allow_cpu(&event->attr);
4256 if (ret)
4257 return ret;
4258
4259 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
4260
4261 return 0;
4262 }
4263
4264 /*
4265 * Currently, the only caller of this function is the atomic_switch_perf_msrs().
4266 * The host perf context helps to prepare the values of the real hardware for
4267 * a set of msrs that need to be switched atomically in a vmx transaction.
4268 *
4269 * For example, the pseudocode needed to add a new msr should look like:
4270 *
4271 * arr[(*nr)++] = (struct perf_guest_switch_msr){
4272 * .msr = the hardware msr address,
4273 * .host = the value the hardware has when it doesn't run a guest,
4274 * .guest = the value the hardware has when it runs a guest,
4275 * };
4276 *
4277 * These values have nothing to do with the emulated values the guest sees
4278 * when it uses {RD,WR}MSR, which should be handled by the KVM context,
4279 * specifically in the intel_pmu_{get,set}_msr().
4280 */
intel_guest_get_msrs(int * nr,void * data)4281 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
4282 {
4283 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4284 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4285 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
4286 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
4287 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
4288 int global_ctrl, pebs_enable;
4289
4290 /*
4291 * In addition to obeying exclude_guest/exclude_host, remove bits being
4292 * used for PEBS when running a guest, because PEBS writes to virtual
4293 * addresses (not physical addresses).
4294 */
4295 *nr = 0;
4296 global_ctrl = (*nr)++;
4297 arr[global_ctrl] = (struct perf_guest_switch_msr){
4298 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
4299 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
4300 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask,
4301 };
4302
4303 if (!x86_pmu.pebs)
4304 return arr;
4305
4306 /*
4307 * If PMU counter has PEBS enabled it is not enough to
4308 * disable counter on a guest entry since PEBS memory
4309 * write can overshoot guest entry and corrupt guest
4310 * memory. Disabling PEBS solves the problem.
4311 *
4312 * Don't do this if the CPU already enforces it.
4313 */
4314 if (x86_pmu.pebs_no_isolation) {
4315 arr[(*nr)++] = (struct perf_guest_switch_msr){
4316 .msr = MSR_IA32_PEBS_ENABLE,
4317 .host = cpuc->pebs_enabled,
4318 .guest = 0,
4319 };
4320 return arr;
4321 }
4322
4323 if (!kvm_pmu || !x86_pmu.pebs_ept)
4324 return arr;
4325
4326 arr[(*nr)++] = (struct perf_guest_switch_msr){
4327 .msr = MSR_IA32_DS_AREA,
4328 .host = (unsigned long)cpuc->ds,
4329 .guest = kvm_pmu->ds_area,
4330 };
4331
4332 if (x86_pmu.intel_cap.pebs_baseline) {
4333 arr[(*nr)++] = (struct perf_guest_switch_msr){
4334 .msr = MSR_PEBS_DATA_CFG,
4335 .host = cpuc->active_pebs_data_cfg,
4336 .guest = kvm_pmu->pebs_data_cfg,
4337 };
4338 }
4339
4340 pebs_enable = (*nr)++;
4341 arr[pebs_enable] = (struct perf_guest_switch_msr){
4342 .msr = MSR_IA32_PEBS_ENABLE,
4343 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
4344 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask,
4345 };
4346
4347 if (arr[pebs_enable].host) {
4348 /* Disable guest PEBS if host PEBS is enabled. */
4349 arr[pebs_enable].guest = 0;
4350 } else {
4351 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
4352 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
4353 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
4354 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
4355 arr[global_ctrl].guest |= arr[pebs_enable].guest;
4356 }
4357
4358 return arr;
4359 }
4360
core_guest_get_msrs(int * nr,void * data)4361 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data)
4362 {
4363 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4364 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4365 int idx;
4366
4367 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
4368 struct perf_event *event = cpuc->events[idx];
4369
4370 arr[idx].msr = x86_pmu_config_addr(idx);
4371 arr[idx].host = arr[idx].guest = 0;
4372
4373 if (!test_bit(idx, cpuc->active_mask))
4374 continue;
4375
4376 arr[idx].host = arr[idx].guest =
4377 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
4378
4379 if (event->attr.exclude_host)
4380 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4381 else if (event->attr.exclude_guest)
4382 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4383 }
4384
4385 *nr = x86_pmu_max_num_counters(cpuc->pmu);
4386 return arr;
4387 }
4388
core_pmu_enable_event(struct perf_event * event)4389 static void core_pmu_enable_event(struct perf_event *event)
4390 {
4391 if (!event->attr.exclude_host)
4392 x86_pmu_enable_event(event);
4393 }
4394
core_pmu_enable_all(int added)4395 static void core_pmu_enable_all(int added)
4396 {
4397 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4398 int idx;
4399
4400 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
4401 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
4402
4403 if (!test_bit(idx, cpuc->active_mask) ||
4404 cpuc->events[idx]->attr.exclude_host)
4405 continue;
4406
4407 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
4408 }
4409 }
4410
hsw_hw_config(struct perf_event * event)4411 static int hsw_hw_config(struct perf_event *event)
4412 {
4413 int ret = intel_pmu_hw_config(event);
4414
4415 if (ret)
4416 return ret;
4417 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
4418 return 0;
4419 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
4420
4421 /*
4422 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
4423 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
4424 * this combination.
4425 */
4426 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
4427 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
4428 event->attr.precise_ip > 0))
4429 return -EOPNOTSUPP;
4430
4431 if (event_is_checkpointed(event)) {
4432 /*
4433 * Sampling of checkpointed events can cause situations where
4434 * the CPU constantly aborts because of a overflow, which is
4435 * then checkpointed back and ignored. Forbid checkpointing
4436 * for sampling.
4437 *
4438 * But still allow a long sampling period, so that perf stat
4439 * from KVM works.
4440 */
4441 if (event->attr.sample_period > 0 &&
4442 event->attr.sample_period < 0x7fffffff)
4443 return -EOPNOTSUPP;
4444 }
4445 return 0;
4446 }
4447
4448 static struct event_constraint counter0_constraint =
4449 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
4450
4451 static struct event_constraint counter1_constraint =
4452 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2);
4453
4454 static struct event_constraint counter0_1_constraint =
4455 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3);
4456
4457 static struct event_constraint counter2_constraint =
4458 EVENT_CONSTRAINT(0, 0x4, 0);
4459
4460 static struct event_constraint fixed0_constraint =
4461 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
4462
4463 static struct event_constraint fixed0_counter0_constraint =
4464 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
4465
4466 static struct event_constraint fixed0_counter0_1_constraint =
4467 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL);
4468
4469 static struct event_constraint counters_1_7_constraint =
4470 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL);
4471
4472 static struct event_constraint *
hsw_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4473 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4474 struct perf_event *event)
4475 {
4476 struct event_constraint *c;
4477
4478 c = intel_get_event_constraints(cpuc, idx, event);
4479
4480 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
4481 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
4482 if (c->idxmsk64 & (1U << 2))
4483 return &counter2_constraint;
4484 return &emptyconstraint;
4485 }
4486
4487 return c;
4488 }
4489
4490 static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4491 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4492 struct perf_event *event)
4493 {
4494 /*
4495 * Fixed counter 0 has less skid.
4496 * Force instruction:ppp in Fixed counter 0
4497 */
4498 if ((event->attr.precise_ip == 3) &&
4499 constraint_match(&fixed0_constraint, event->hw.config))
4500 return &fixed0_constraint;
4501
4502 return hsw_get_event_constraints(cpuc, idx, event);
4503 }
4504
4505 static struct event_constraint *
glc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4506 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4507 struct perf_event *event)
4508 {
4509 struct event_constraint *c;
4510
4511 c = icl_get_event_constraints(cpuc, idx, event);
4512
4513 /*
4514 * The :ppp indicates the Precise Distribution (PDist) facility, which
4515 * is only supported on the GP counter 0. If a :ppp event which is not
4516 * available on the GP counter 0, error out.
4517 * Exception: Instruction PDIR is only available on the fixed counter 0.
4518 */
4519 if ((event->attr.precise_ip == 3) &&
4520 !constraint_match(&fixed0_constraint, event->hw.config)) {
4521 if (c->idxmsk64 & BIT_ULL(0))
4522 return &counter0_constraint;
4523
4524 return &emptyconstraint;
4525 }
4526
4527 return c;
4528 }
4529
4530 static struct event_constraint *
glp_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4531 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4532 struct perf_event *event)
4533 {
4534 struct event_constraint *c;
4535
4536 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4537 if (event->attr.precise_ip == 3)
4538 return &counter0_constraint;
4539
4540 c = intel_get_event_constraints(cpuc, idx, event);
4541
4542 return c;
4543 }
4544
4545 static struct event_constraint *
tnt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4546 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4547 struct perf_event *event)
4548 {
4549 struct event_constraint *c;
4550
4551 c = intel_get_event_constraints(cpuc, idx, event);
4552
4553 /*
4554 * :ppp means to do reduced skid PEBS,
4555 * which is available on PMC0 and fixed counter 0.
4556 */
4557 if (event->attr.precise_ip == 3) {
4558 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4559 if (constraint_match(&fixed0_constraint, event->hw.config))
4560 return &fixed0_counter0_constraint;
4561
4562 return &counter0_constraint;
4563 }
4564
4565 return c;
4566 }
4567
4568 static bool allow_tsx_force_abort = true;
4569
4570 static struct event_constraint *
tfa_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4571 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4572 struct perf_event *event)
4573 {
4574 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4575
4576 /*
4577 * Without TFA we must not use PMC3.
4578 */
4579 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4580 c = dyn_constraint(cpuc, c, idx);
4581 c->idxmsk64 &= ~(1ULL << 3);
4582 c->weight--;
4583 }
4584
4585 return c;
4586 }
4587
4588 static struct event_constraint *
adl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4589 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4590 struct perf_event *event)
4591 {
4592 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4593
4594 if (pmu->pmu_type == hybrid_big)
4595 return glc_get_event_constraints(cpuc, idx, event);
4596 else if (pmu->pmu_type == hybrid_small)
4597 return tnt_get_event_constraints(cpuc, idx, event);
4598
4599 WARN_ON(1);
4600 return &emptyconstraint;
4601 }
4602
4603 static struct event_constraint *
cmt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4604 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4605 struct perf_event *event)
4606 {
4607 struct event_constraint *c;
4608
4609 c = intel_get_event_constraints(cpuc, idx, event);
4610
4611 /*
4612 * The :ppp indicates the Precise Distribution (PDist) facility, which
4613 * is only supported on the GP counter 0 & 1 and Fixed counter 0.
4614 * If a :ppp event which is not available on the above eligible counters,
4615 * error out.
4616 */
4617 if (event->attr.precise_ip == 3) {
4618 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */
4619 if (constraint_match(&fixed0_constraint, event->hw.config)) {
4620 /* The fixed counter 0 doesn't support LBR event logging. */
4621 if (branch_sample_counters(event))
4622 return &counter0_1_constraint;
4623 else
4624 return &fixed0_counter0_1_constraint;
4625 }
4626
4627 switch (c->idxmsk64 & 0x3ull) {
4628 case 0x1:
4629 return &counter0_constraint;
4630 case 0x2:
4631 return &counter1_constraint;
4632 case 0x3:
4633 return &counter0_1_constraint;
4634 }
4635 return &emptyconstraint;
4636 }
4637
4638 return c;
4639 }
4640
4641 static struct event_constraint *
rwc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4642 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4643 struct perf_event *event)
4644 {
4645 struct event_constraint *c;
4646
4647 c = glc_get_event_constraints(cpuc, idx, event);
4648
4649 /* The Retire Latency is not supported by the fixed counter 0. */
4650 if (event->attr.precise_ip &&
4651 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
4652 constraint_match(&fixed0_constraint, event->hw.config)) {
4653 /*
4654 * The Instruction PDIR is only available
4655 * on the fixed counter 0. Error out for this case.
4656 */
4657 if (event->attr.precise_ip == 3)
4658 return &emptyconstraint;
4659 return &counters_1_7_constraint;
4660 }
4661
4662 return c;
4663 }
4664
4665 static struct event_constraint *
mtl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4666 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4667 struct perf_event *event)
4668 {
4669 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4670
4671 if (pmu->pmu_type == hybrid_big)
4672 return rwc_get_event_constraints(cpuc, idx, event);
4673 if (pmu->pmu_type == hybrid_small)
4674 return cmt_get_event_constraints(cpuc, idx, event);
4675
4676 WARN_ON(1);
4677 return &emptyconstraint;
4678 }
4679
adl_hw_config(struct perf_event * event)4680 static int adl_hw_config(struct perf_event *event)
4681 {
4682 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4683
4684 if (pmu->pmu_type == hybrid_big)
4685 return hsw_hw_config(event);
4686 else if (pmu->pmu_type == hybrid_small)
4687 return intel_pmu_hw_config(event);
4688
4689 WARN_ON(1);
4690 return -EOPNOTSUPP;
4691 }
4692
adl_get_hybrid_cpu_type(void)4693 static enum hybrid_cpu_type adl_get_hybrid_cpu_type(void)
4694 {
4695 return HYBRID_INTEL_CORE;
4696 }
4697
erratum_hsw11(struct perf_event * event)4698 static inline bool erratum_hsw11(struct perf_event *event)
4699 {
4700 return (event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4701 X86_CONFIG(.event=0xc0, .umask=0x01);
4702 }
4703
4704 static struct event_constraint *
arl_h_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4705 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4706 struct perf_event *event)
4707 {
4708 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4709
4710 if (pmu->pmu_type == hybrid_tiny)
4711 return cmt_get_event_constraints(cpuc, idx, event);
4712
4713 return mtl_get_event_constraints(cpuc, idx, event);
4714 }
4715
arl_h_hw_config(struct perf_event * event)4716 static int arl_h_hw_config(struct perf_event *event)
4717 {
4718 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4719
4720 if (pmu->pmu_type == hybrid_tiny)
4721 return intel_pmu_hw_config(event);
4722
4723 return adl_hw_config(event);
4724 }
4725
4726 /*
4727 * The HSW11 requires a period larger than 100 which is the same as the BDM11.
4728 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL.
4729 *
4730 * The message 'interrupt took too long' can be observed on any counter which
4731 * was armed with a period < 32 and two events expired in the same NMI.
4732 * A minimum period of 32 is enforced for the rest of the events.
4733 */
hsw_limit_period(struct perf_event * event,s64 * left)4734 static void hsw_limit_period(struct perf_event *event, s64 *left)
4735 {
4736 *left = max(*left, erratum_hsw11(event) ? 128 : 32);
4737 }
4738
4739 /*
4740 * Broadwell:
4741 *
4742 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4743 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4744 * the two to enforce a minimum period of 128 (the smallest value that has bits
4745 * 0-5 cleared and >= 100).
4746 *
4747 * Because of how the code in x86_perf_event_set_period() works, the truncation
4748 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4749 * to make up for the 'lost' events due to carrying the 'error' in period_left.
4750 *
4751 * Therefore the effective (average) period matches the requested period,
4752 * despite coarser hardware granularity.
4753 */
bdw_limit_period(struct perf_event * event,s64 * left)4754 static void bdw_limit_period(struct perf_event *event, s64 *left)
4755 {
4756 if (erratum_hsw11(event)) {
4757 if (*left < 128)
4758 *left = 128;
4759 *left &= ~0x3fULL;
4760 }
4761 }
4762
nhm_limit_period(struct perf_event * event,s64 * left)4763 static void nhm_limit_period(struct perf_event *event, s64 *left)
4764 {
4765 *left = max(*left, 32LL);
4766 }
4767
glc_limit_period(struct perf_event * event,s64 * left)4768 static void glc_limit_period(struct perf_event *event, s64 *left)
4769 {
4770 if (event->attr.precise_ip == 3)
4771 *left = max(*left, 128LL);
4772 }
4773
4774 PMU_FORMAT_ATTR(event, "config:0-7" );
4775 PMU_FORMAT_ATTR(umask, "config:8-15" );
4776 PMU_FORMAT_ATTR(edge, "config:18" );
4777 PMU_FORMAT_ATTR(pc, "config:19" );
4778 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
4779 PMU_FORMAT_ATTR(inv, "config:23" );
4780 PMU_FORMAT_ATTR(cmask, "config:24-31" );
4781 PMU_FORMAT_ATTR(in_tx, "config:32" );
4782 PMU_FORMAT_ATTR(in_tx_cp, "config:33" );
4783 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */
4784
4785 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
4786
umask2_show(struct device * dev,struct device_attribute * attr,char * page)4787 static ssize_t umask2_show(struct device *dev,
4788 struct device_attribute *attr,
4789 char *page)
4790 {
4791 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2;
4792
4793 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2)
4794 return sprintf(page, "config:8-15,40-47\n");
4795
4796 /* Roll back to the old format if umask2 is not supported. */
4797 return sprintf(page, "config:8-15\n");
4798 }
4799
4800 static struct device_attribute format_attr_umask2 =
4801 __ATTR(umask, 0444, umask2_show, NULL);
4802
4803 static struct attribute *format_evtsel_ext_attrs[] = {
4804 &format_attr_umask2.attr,
4805 &format_attr_eq.attr,
4806 &format_attr_metrics_clear.attr,
4807 NULL
4808 };
4809
4810 static umode_t
evtsel_ext_is_visible(struct kobject * kobj,struct attribute * attr,int i)4811 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4812 {
4813 struct device *dev = kobj_to_dev(kobj);
4814 u64 mask;
4815
4816 /*
4817 * The umask and umask2 have different formats but share the
4818 * same attr name. In update mode, the previous value of the
4819 * umask is unconditionally removed before is_visible. If
4820 * umask2 format is not enumerated, it's impossible to roll
4821 * back to the old format.
4822 * Does the check in umask2_show rather than is_visible.
4823 */
4824 if (i == 0)
4825 return attr->mode;
4826
4827 mask = hybrid(dev_get_drvdata(dev), config_mask);
4828 if (i == 1)
4829 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0;
4830
4831 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
4832 if (i == 2) {
4833 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap);
4834
4835 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0;
4836 }
4837
4838 return 0;
4839 }
4840
4841 static struct attribute *intel_arch_formats_attr[] = {
4842 &format_attr_event.attr,
4843 &format_attr_umask.attr,
4844 &format_attr_edge.attr,
4845 &format_attr_pc.attr,
4846 &format_attr_inv.attr,
4847 &format_attr_cmask.attr,
4848 NULL,
4849 };
4850
intel_event_sysfs_show(char * page,u64 config)4851 ssize_t intel_event_sysfs_show(char *page, u64 config)
4852 {
4853 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4854
4855 return x86_event_sysfs_show(page, config, event);
4856 }
4857
allocate_shared_regs(int cpu)4858 static struct intel_shared_regs *allocate_shared_regs(int cpu)
4859 {
4860 struct intel_shared_regs *regs;
4861 int i;
4862
4863 regs = kzalloc_node(sizeof(struct intel_shared_regs),
4864 GFP_KERNEL, cpu_to_node(cpu));
4865 if (regs) {
4866 /*
4867 * initialize the locks to keep lockdep happy
4868 */
4869 for (i = 0; i < EXTRA_REG_MAX; i++)
4870 raw_spin_lock_init(®s->regs[i].lock);
4871
4872 regs->core_id = -1;
4873 }
4874 return regs;
4875 }
4876
allocate_excl_cntrs(int cpu)4877 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4878 {
4879 struct intel_excl_cntrs *c;
4880
4881 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4882 GFP_KERNEL, cpu_to_node(cpu));
4883 if (c) {
4884 raw_spin_lock_init(&c->lock);
4885 c->core_id = -1;
4886 }
4887 return c;
4888 }
4889
4890
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)4891 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4892 {
4893 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4894
4895 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4896 cpuc->shared_regs = allocate_shared_regs(cpu);
4897 if (!cpuc->shared_regs)
4898 goto err;
4899 }
4900
4901 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_BR_CNTR)) {
4902 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4903
4904 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4905 if (!cpuc->constraint_list)
4906 goto err_shared_regs;
4907 }
4908
4909 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4910 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4911 if (!cpuc->excl_cntrs)
4912 goto err_constraint_list;
4913
4914 cpuc->excl_thread_id = 0;
4915 }
4916
4917 return 0;
4918
4919 err_constraint_list:
4920 kfree(cpuc->constraint_list);
4921 cpuc->constraint_list = NULL;
4922
4923 err_shared_regs:
4924 kfree(cpuc->shared_regs);
4925 cpuc->shared_regs = NULL;
4926
4927 err:
4928 return -ENOMEM;
4929 }
4930
intel_pmu_cpu_prepare(int cpu)4931 static int intel_pmu_cpu_prepare(int cpu)
4932 {
4933 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4934 }
4935
flip_smm_bit(void * data)4936 static void flip_smm_bit(void *data)
4937 {
4938 unsigned long set = *(unsigned long *)data;
4939
4940 if (set > 0) {
4941 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4942 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4943 } else {
4944 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4945 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4946 }
4947 }
4948
intel_pmu_check_counters_mask(u64 * cntr_mask,u64 * fixed_cntr_mask,u64 * intel_ctrl)4949 static void intel_pmu_check_counters_mask(u64 *cntr_mask,
4950 u64 *fixed_cntr_mask,
4951 u64 *intel_ctrl)
4952 {
4953 unsigned int bit;
4954
4955 bit = fls64(*cntr_mask);
4956 if (bit > INTEL_PMC_MAX_GENERIC) {
4957 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
4958 bit, INTEL_PMC_MAX_GENERIC);
4959 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
4960 }
4961 *intel_ctrl = *cntr_mask;
4962
4963 bit = fls64(*fixed_cntr_mask);
4964 if (bit > INTEL_PMC_MAX_FIXED) {
4965 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
4966 bit, INTEL_PMC_MAX_FIXED);
4967 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
4968 }
4969
4970 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED;
4971 }
4972
4973 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
4974 u64 cntr_mask,
4975 u64 fixed_cntr_mask,
4976 u64 intel_ctrl);
4977
4978 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs);
4979
intel_pmu_broken_perf_cap(void)4980 static inline bool intel_pmu_broken_perf_cap(void)
4981 {
4982 /* The Perf Metric (Bit 15) is always cleared */
4983 if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||
4984 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L)
4985 return true;
4986
4987 return false;
4988 }
4989
update_pmu_cap(struct x86_hybrid_pmu * pmu)4990 static void update_pmu_cap(struct x86_hybrid_pmu *pmu)
4991 {
4992 unsigned int cntr, fixed_cntr, ecx, edx;
4993 union cpuid35_eax eax;
4994 union cpuid35_ebx ebx;
4995
4996 cpuid(ARCH_PERFMON_EXT_LEAF, &eax.full, &ebx.full, &ecx, &edx);
4997
4998 if (ebx.split.umask2)
4999 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_UMASK2;
5000 if (ebx.split.eq)
5001 pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ;
5002
5003 if (eax.split.cntr_subleaf) {
5004 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
5005 &cntr, &fixed_cntr, &ecx, &edx);
5006 pmu->cntr_mask64 = cntr;
5007 pmu->fixed_cntr_mask64 = fixed_cntr;
5008 }
5009
5010 if (!intel_pmu_broken_perf_cap()) {
5011 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */
5012 rdmsrl(MSR_IA32_PERF_CAPABILITIES, pmu->intel_cap.capabilities);
5013 }
5014 }
5015
intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu * pmu)5016 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu)
5017 {
5018 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64,
5019 &pmu->intel_ctrl);
5020 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
5021 pmu->unconstrained = (struct event_constraint)
5022 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
5023 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
5024
5025 if (pmu->intel_cap.perf_metrics)
5026 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
5027 else
5028 pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
5029
5030 intel_pmu_check_event_constraints(pmu->event_constraints,
5031 pmu->cntr_mask64,
5032 pmu->fixed_cntr_mask64,
5033 pmu->intel_ctrl);
5034
5035 intel_pmu_check_extra_regs(pmu->extra_regs);
5036 }
5037
find_hybrid_pmu_for_cpu(void)5038 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void)
5039 {
5040 u8 cpu_type = get_this_hybrid_cpu_type();
5041 int i;
5042
5043 /*
5044 * This is running on a CPU model that is known to have hybrid
5045 * configurations. But the CPU told us it is not hybrid, shame
5046 * on it. There should be a fixup function provided for these
5047 * troublesome CPUs (->get_hybrid_cpu_type).
5048 */
5049 if (cpu_type == HYBRID_INTEL_NONE) {
5050 if (x86_pmu.get_hybrid_cpu_type)
5051 cpu_type = x86_pmu.get_hybrid_cpu_type();
5052 else
5053 return NULL;
5054 }
5055
5056 /*
5057 * This essentially just maps between the 'hybrid_cpu_type'
5058 * and 'hybrid_pmu_type' enums except for ARL-H processor
5059 * which needs to compare atom uarch native id since ARL-H
5060 * contains two different atom uarchs.
5061 */
5062 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
5063 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type;
5064 u32 native_id;
5065
5066 if (cpu_type == HYBRID_INTEL_CORE && pmu_type == hybrid_big)
5067 return &x86_pmu.hybrid_pmu[i];
5068 if (cpu_type == HYBRID_INTEL_ATOM) {
5069 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small)
5070 return &x86_pmu.hybrid_pmu[i];
5071
5072 native_id = get_this_hybrid_cpu_native_id();
5073 if (native_id == skt_native_id && pmu_type == hybrid_small)
5074 return &x86_pmu.hybrid_pmu[i];
5075 if (native_id == cmt_native_id && pmu_type == hybrid_tiny)
5076 return &x86_pmu.hybrid_pmu[i];
5077 }
5078 }
5079
5080 return NULL;
5081 }
5082
init_hybrid_pmu(int cpu)5083 static bool init_hybrid_pmu(int cpu)
5084 {
5085 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5086 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu();
5087
5088 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
5089 cpuc->pmu = NULL;
5090 return false;
5091 }
5092
5093 /* Only check and dump the PMU information for the first CPU */
5094 if (!cpumask_empty(&pmu->supported_cpus))
5095 goto end;
5096
5097 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
5098 update_pmu_cap(pmu);
5099
5100 intel_pmu_check_hybrid_pmus(pmu);
5101
5102 if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask))
5103 return false;
5104
5105 pr_info("%s PMU driver: ", pmu->name);
5106
5107 pr_cont("\n");
5108
5109 x86_pmu_show_pmu_cap(&pmu->pmu);
5110
5111 end:
5112 cpumask_set_cpu(cpu, &pmu->supported_cpus);
5113 cpuc->pmu = &pmu->pmu;
5114
5115 return true;
5116 }
5117
intel_pmu_cpu_starting(int cpu)5118 static void intel_pmu_cpu_starting(int cpu)
5119 {
5120 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5121 int core_id = topology_core_id(cpu);
5122 int i;
5123
5124 if (is_hybrid() && !init_hybrid_pmu(cpu))
5125 return;
5126
5127 init_debug_store_on_cpu(cpu);
5128 /*
5129 * Deal with CPUs that don't clear their LBRs on power-up, and that may
5130 * even boot with LBRs enabled.
5131 */
5132 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr)
5133 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT);
5134 intel_pmu_lbr_reset();
5135
5136 cpuc->lbr_sel = NULL;
5137
5138 if (x86_pmu.flags & PMU_FL_TFA) {
5139 WARN_ON_ONCE(cpuc->tfa_shadow);
5140 cpuc->tfa_shadow = ~0ULL;
5141 intel_set_tfa(cpuc, false);
5142 }
5143
5144 if (x86_pmu.version > 1)
5145 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
5146
5147 /*
5148 * Disable perf metrics if any added CPU doesn't support it.
5149 *
5150 * Turn off the check for a hybrid architecture, because the
5151 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
5152 * the architecture features. The perf metrics is a model-specific
5153 * feature for now. The corresponding bit should always be 0 on
5154 * a hybrid platform, e.g., Alder Lake.
5155 */
5156 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
5157 union perf_capabilities perf_cap;
5158
5159 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
5160 if (!perf_cap.perf_metrics) {
5161 x86_pmu.intel_cap.perf_metrics = 0;
5162 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
5163 }
5164 }
5165
5166 if (!cpuc->shared_regs)
5167 return;
5168
5169 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
5170 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
5171 struct intel_shared_regs *pc;
5172
5173 pc = per_cpu(cpu_hw_events, i).shared_regs;
5174 if (pc && pc->core_id == core_id) {
5175 cpuc->kfree_on_online[0] = cpuc->shared_regs;
5176 cpuc->shared_regs = pc;
5177 break;
5178 }
5179 }
5180 cpuc->shared_regs->core_id = core_id;
5181 cpuc->shared_regs->refcnt++;
5182 }
5183
5184 if (x86_pmu.lbr_sel_map)
5185 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
5186
5187 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
5188 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
5189 struct cpu_hw_events *sibling;
5190 struct intel_excl_cntrs *c;
5191
5192 sibling = &per_cpu(cpu_hw_events, i);
5193 c = sibling->excl_cntrs;
5194 if (c && c->core_id == core_id) {
5195 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
5196 cpuc->excl_cntrs = c;
5197 if (!sibling->excl_thread_id)
5198 cpuc->excl_thread_id = 1;
5199 break;
5200 }
5201 }
5202 cpuc->excl_cntrs->core_id = core_id;
5203 cpuc->excl_cntrs->refcnt++;
5204 }
5205 }
5206
free_excl_cntrs(struct cpu_hw_events * cpuc)5207 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
5208 {
5209 struct intel_excl_cntrs *c;
5210
5211 c = cpuc->excl_cntrs;
5212 if (c) {
5213 if (c->core_id == -1 || --c->refcnt == 0)
5214 kfree(c);
5215 cpuc->excl_cntrs = NULL;
5216 }
5217
5218 kfree(cpuc->constraint_list);
5219 cpuc->constraint_list = NULL;
5220 }
5221
intel_pmu_cpu_dying(int cpu)5222 static void intel_pmu_cpu_dying(int cpu)
5223 {
5224 fini_debug_store_on_cpu(cpu);
5225 }
5226
intel_cpuc_finish(struct cpu_hw_events * cpuc)5227 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
5228 {
5229 struct intel_shared_regs *pc;
5230
5231 pc = cpuc->shared_regs;
5232 if (pc) {
5233 if (pc->core_id == -1 || --pc->refcnt == 0)
5234 kfree(pc);
5235 cpuc->shared_regs = NULL;
5236 }
5237
5238 free_excl_cntrs(cpuc);
5239 }
5240
intel_pmu_cpu_dead(int cpu)5241 static void intel_pmu_cpu_dead(int cpu)
5242 {
5243 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5244
5245 intel_cpuc_finish(cpuc);
5246
5247 if (is_hybrid() && cpuc->pmu)
5248 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
5249 }
5250
intel_pmu_sched_task(struct perf_event_pmu_context * pmu_ctx,struct task_struct * task,bool sched_in)5251 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
5252 struct task_struct *task, bool sched_in)
5253 {
5254 intel_pmu_pebs_sched_task(pmu_ctx, sched_in);
5255 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in);
5256 }
5257
intel_pmu_swap_task_ctx(struct perf_event_pmu_context * prev_epc,struct perf_event_pmu_context * next_epc)5258 static void intel_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
5259 struct perf_event_pmu_context *next_epc)
5260 {
5261 intel_pmu_lbr_swap_task_ctx(prev_epc, next_epc);
5262 }
5263
intel_pmu_check_period(struct perf_event * event,u64 value)5264 static int intel_pmu_check_period(struct perf_event *event, u64 value)
5265 {
5266 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
5267 }
5268
intel_aux_output_init(void)5269 static void intel_aux_output_init(void)
5270 {
5271 /* Refer also intel_pmu_aux_output_match() */
5272 if (x86_pmu.intel_cap.pebs_output_pt_available)
5273 x86_pmu.assign = intel_pmu_assign_event;
5274 }
5275
intel_pmu_aux_output_match(struct perf_event * event)5276 static int intel_pmu_aux_output_match(struct perf_event *event)
5277 {
5278 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
5279 if (!x86_pmu.intel_cap.pebs_output_pt_available)
5280 return 0;
5281
5282 return is_intel_pt_event(event);
5283 }
5284
intel_pmu_filter(struct pmu * pmu,int cpu,bool * ret)5285 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
5286 {
5287 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu);
5288
5289 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus);
5290 }
5291
5292 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
5293
5294 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
5295
5296 PMU_FORMAT_ATTR(frontend, "config1:0-23");
5297
5298 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
5299
5300 static struct attribute *intel_arch3_formats_attr[] = {
5301 &format_attr_event.attr,
5302 &format_attr_umask.attr,
5303 &format_attr_edge.attr,
5304 &format_attr_pc.attr,
5305 &format_attr_any.attr,
5306 &format_attr_inv.attr,
5307 &format_attr_cmask.attr,
5308 NULL,
5309 };
5310
5311 static struct attribute *hsw_format_attr[] = {
5312 &format_attr_in_tx.attr,
5313 &format_attr_in_tx_cp.attr,
5314 &format_attr_offcore_rsp.attr,
5315 &format_attr_ldlat.attr,
5316 NULL
5317 };
5318
5319 static struct attribute *nhm_format_attr[] = {
5320 &format_attr_offcore_rsp.attr,
5321 &format_attr_ldlat.attr,
5322 NULL
5323 };
5324
5325 static struct attribute *slm_format_attr[] = {
5326 &format_attr_offcore_rsp.attr,
5327 NULL
5328 };
5329
5330 static struct attribute *cmt_format_attr[] = {
5331 &format_attr_offcore_rsp.attr,
5332 &format_attr_ldlat.attr,
5333 &format_attr_snoop_rsp.attr,
5334 NULL
5335 };
5336
5337 static struct attribute *skl_format_attr[] = {
5338 &format_attr_frontend.attr,
5339 NULL,
5340 };
5341
5342 static __initconst const struct x86_pmu core_pmu = {
5343 .name = "core",
5344 .handle_irq = x86_pmu_handle_irq,
5345 .disable_all = x86_pmu_disable_all,
5346 .enable_all = core_pmu_enable_all,
5347 .enable = core_pmu_enable_event,
5348 .disable = x86_pmu_disable_event,
5349 .hw_config = core_pmu_hw_config,
5350 .schedule_events = x86_schedule_events,
5351 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
5352 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5353 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
5354 .event_map = intel_pmu_event_map,
5355 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
5356 .apic = 1,
5357 .large_pebs_flags = LARGE_PEBS_FLAGS,
5358
5359 /*
5360 * Intel PMCs cannot be accessed sanely above 32-bit width,
5361 * so we install an artificial 1<<31 period regardless of
5362 * the generic event period:
5363 */
5364 .max_period = (1ULL<<31) - 1,
5365 .get_event_constraints = intel_get_event_constraints,
5366 .put_event_constraints = intel_put_event_constraints,
5367 .event_constraints = intel_core_event_constraints,
5368 .guest_get_msrs = core_guest_get_msrs,
5369 .format_attrs = intel_arch_formats_attr,
5370 .events_sysfs_show = intel_event_sysfs_show,
5371
5372 /*
5373 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
5374 * together with PMU version 1 and thus be using core_pmu with
5375 * shared_regs. We need following callbacks here to allocate
5376 * it properly.
5377 */
5378 .cpu_prepare = intel_pmu_cpu_prepare,
5379 .cpu_starting = intel_pmu_cpu_starting,
5380 .cpu_dying = intel_pmu_cpu_dying,
5381 .cpu_dead = intel_pmu_cpu_dead,
5382
5383 .check_period = intel_pmu_check_period,
5384
5385 .lbr_reset = intel_pmu_lbr_reset_64,
5386 .lbr_read = intel_pmu_lbr_read_64,
5387 .lbr_save = intel_pmu_lbr_save,
5388 .lbr_restore = intel_pmu_lbr_restore,
5389 };
5390
5391 static __initconst const struct x86_pmu intel_pmu = {
5392 .name = "Intel",
5393 .handle_irq = intel_pmu_handle_irq,
5394 .disable_all = intel_pmu_disable_all,
5395 .enable_all = intel_pmu_enable_all,
5396 .enable = intel_pmu_enable_event,
5397 .disable = intel_pmu_disable_event,
5398 .add = intel_pmu_add_event,
5399 .del = intel_pmu_del_event,
5400 .read = intel_pmu_read_event,
5401 .set_period = intel_pmu_set_period,
5402 .update = intel_pmu_update,
5403 .hw_config = intel_pmu_hw_config,
5404 .schedule_events = x86_schedule_events,
5405 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
5406 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5407 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
5408 .event_map = intel_pmu_event_map,
5409 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
5410 .apic = 1,
5411 .large_pebs_flags = LARGE_PEBS_FLAGS,
5412 /*
5413 * Intel PMCs cannot be accessed sanely above 32 bit width,
5414 * so we install an artificial 1<<31 period regardless of
5415 * the generic event period:
5416 */
5417 .max_period = (1ULL << 31) - 1,
5418 .get_event_constraints = intel_get_event_constraints,
5419 .put_event_constraints = intel_put_event_constraints,
5420 .pebs_aliases = intel_pebs_aliases_core2,
5421
5422 .format_attrs = intel_arch3_formats_attr,
5423 .events_sysfs_show = intel_event_sysfs_show,
5424
5425 .cpu_prepare = intel_pmu_cpu_prepare,
5426 .cpu_starting = intel_pmu_cpu_starting,
5427 .cpu_dying = intel_pmu_cpu_dying,
5428 .cpu_dead = intel_pmu_cpu_dead,
5429
5430 .guest_get_msrs = intel_guest_get_msrs,
5431 .sched_task = intel_pmu_sched_task,
5432 .swap_task_ctx = intel_pmu_swap_task_ctx,
5433
5434 .check_period = intel_pmu_check_period,
5435
5436 .aux_output_match = intel_pmu_aux_output_match,
5437
5438 .lbr_reset = intel_pmu_lbr_reset_64,
5439 .lbr_read = intel_pmu_lbr_read_64,
5440 .lbr_save = intel_pmu_lbr_save,
5441 .lbr_restore = intel_pmu_lbr_restore,
5442
5443 /*
5444 * SMM has access to all 4 rings and while traditionally SMM code only
5445 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
5446 *
5447 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
5448 * between SMM or not, this results in what should be pure userspace
5449 * counters including SMM data.
5450 *
5451 * This is a clear privilege issue, therefore globally disable
5452 * counting SMM by default.
5453 */
5454 .attr_freeze_on_smi = 1,
5455 };
5456
intel_clovertown_quirk(void)5457 static __init void intel_clovertown_quirk(void)
5458 {
5459 /*
5460 * PEBS is unreliable due to:
5461 *
5462 * AJ67 - PEBS may experience CPL leaks
5463 * AJ68 - PEBS PMI may be delayed by one event
5464 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
5465 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
5466 *
5467 * AJ67 could be worked around by restricting the OS/USR flags.
5468 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
5469 *
5470 * AJ106 could possibly be worked around by not allowing LBR
5471 * usage from PEBS, including the fixup.
5472 * AJ68 could possibly be worked around by always programming
5473 * a pebs_event_reset[0] value and coping with the lost events.
5474 *
5475 * But taken together it might just make sense to not enable PEBS on
5476 * these chips.
5477 */
5478 pr_warn("PEBS disabled due to CPU errata\n");
5479 x86_pmu.pebs = 0;
5480 x86_pmu.pebs_constraints = NULL;
5481 }
5482
5483 static const struct x86_cpu_id isolation_ucodes[] = {
5484 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f),
5485 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e),
5486 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015),
5487 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037),
5488 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a),
5489 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023),
5490 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014),
5491 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010),
5492 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009),
5493 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009),
5494 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002),
5495 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014),
5496 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021),
5497 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000),
5498 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000),
5499 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c),
5500 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c),
5501 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e),
5502 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e),
5503 {}
5504 };
5505
intel_check_pebs_isolation(void)5506 static void intel_check_pebs_isolation(void)
5507 {
5508 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes);
5509 }
5510
intel_pebs_isolation_quirk(void)5511 static __init void intel_pebs_isolation_quirk(void)
5512 {
5513 WARN_ON_ONCE(x86_pmu.check_microcode);
5514 x86_pmu.check_microcode = intel_check_pebs_isolation;
5515 intel_check_pebs_isolation();
5516 }
5517
5518 static const struct x86_cpu_id pebs_ucodes[] = {
5519 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028),
5520 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618),
5521 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c),
5522 {}
5523 };
5524
intel_snb_pebs_broken(void)5525 static bool intel_snb_pebs_broken(void)
5526 {
5527 return !x86_match_min_microcode_rev(pebs_ucodes);
5528 }
5529
intel_snb_check_microcode(void)5530 static void intel_snb_check_microcode(void)
5531 {
5532 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
5533 return;
5534
5535 /*
5536 * Serialized by the microcode lock..
5537 */
5538 if (x86_pmu.pebs_broken) {
5539 pr_info("PEBS enabled due to microcode update\n");
5540 x86_pmu.pebs_broken = 0;
5541 } else {
5542 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
5543 x86_pmu.pebs_broken = 1;
5544 }
5545 }
5546
is_lbr_from(unsigned long msr)5547 static bool is_lbr_from(unsigned long msr)
5548 {
5549 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
5550
5551 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
5552 }
5553
5554 /*
5555 * Under certain circumstances, access certain MSR may cause #GP.
5556 * The function tests if the input MSR can be safely accessed.
5557 */
check_msr(unsigned long msr,u64 mask)5558 static bool check_msr(unsigned long msr, u64 mask)
5559 {
5560 u64 val_old, val_new, val_tmp;
5561
5562 /*
5563 * Disable the check for real HW, so we don't
5564 * mess with potentially enabled registers:
5565 */
5566 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
5567 return true;
5568
5569 /*
5570 * Read the current value, change it and read it back to see if it
5571 * matches, this is needed to detect certain hardware emulators
5572 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
5573 */
5574 if (rdmsrl_safe(msr, &val_old))
5575 return false;
5576
5577 /*
5578 * Only change the bits which can be updated by wrmsrl.
5579 */
5580 val_tmp = val_old ^ mask;
5581
5582 if (is_lbr_from(msr))
5583 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
5584
5585 if (wrmsrl_safe(msr, val_tmp) ||
5586 rdmsrl_safe(msr, &val_new))
5587 return false;
5588
5589 /*
5590 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
5591 * should equal rdmsrl()'s even with the quirk.
5592 */
5593 if (val_new != val_tmp)
5594 return false;
5595
5596 if (is_lbr_from(msr))
5597 val_old = lbr_from_signext_quirk_wr(val_old);
5598
5599 /* Here it's sure that the MSR can be safely accessed.
5600 * Restore the old value and return.
5601 */
5602 wrmsrl(msr, val_old);
5603
5604 return true;
5605 }
5606
intel_sandybridge_quirk(void)5607 static __init void intel_sandybridge_quirk(void)
5608 {
5609 x86_pmu.check_microcode = intel_snb_check_microcode;
5610 cpus_read_lock();
5611 intel_snb_check_microcode();
5612 cpus_read_unlock();
5613 }
5614
5615 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
5616 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
5617 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
5618 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
5619 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
5620 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
5621 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
5622 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
5623 };
5624
intel_arch_events_quirk(void)5625 static __init void intel_arch_events_quirk(void)
5626 {
5627 int bit;
5628
5629 /* disable event that reported as not present by cpuid */
5630 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
5631 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
5632 pr_warn("CPUID marked event: \'%s\' unavailable\n",
5633 intel_arch_events_map[bit].name);
5634 }
5635 }
5636
intel_nehalem_quirk(void)5637 static __init void intel_nehalem_quirk(void)
5638 {
5639 union cpuid10_ebx ebx;
5640
5641 ebx.full = x86_pmu.events_maskl;
5642 if (ebx.split.no_branch_misses_retired) {
5643 /*
5644 * Erratum AAJ80 detected, we work it around by using
5645 * the BR_MISP_EXEC.ANY event. This will over-count
5646 * branch-misses, but it's still much better than the
5647 * architectural event which is often completely bogus:
5648 */
5649 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
5650 ebx.split.no_branch_misses_retired = 0;
5651 x86_pmu.events_maskl = ebx.full;
5652 pr_info("CPU erratum AAJ80 worked around\n");
5653 }
5654 }
5655
5656 /*
5657 * enable software workaround for errata:
5658 * SNB: BJ122
5659 * IVB: BV98
5660 * HSW: HSD29
5661 *
5662 * Only needed when HT is enabled. However detecting
5663 * if HT is enabled is difficult (model specific). So instead,
5664 * we enable the workaround in the early boot, and verify if
5665 * it is needed in a later initcall phase once we have valid
5666 * topology information to check if HT is actually enabled
5667 */
intel_ht_bug(void)5668 static __init void intel_ht_bug(void)
5669 {
5670 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
5671
5672 x86_pmu.start_scheduling = intel_start_scheduling;
5673 x86_pmu.commit_scheduling = intel_commit_scheduling;
5674 x86_pmu.stop_scheduling = intel_stop_scheduling;
5675 }
5676
5677 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
5678 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
5679
5680 /* Haswell special events */
5681 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
5682 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
5683 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
5684 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
5685 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
5686 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
5687 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
5688 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
5689 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
5690 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
5691 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
5692 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
5693
5694 static struct attribute *hsw_events_attrs[] = {
5695 EVENT_PTR(td_slots_issued),
5696 EVENT_PTR(td_slots_retired),
5697 EVENT_PTR(td_fetch_bubbles),
5698 EVENT_PTR(td_total_slots),
5699 EVENT_PTR(td_total_slots_scale),
5700 EVENT_PTR(td_recovery_bubbles),
5701 EVENT_PTR(td_recovery_bubbles_scale),
5702 NULL
5703 };
5704
5705 static struct attribute *hsw_mem_events_attrs[] = {
5706 EVENT_PTR(mem_ld_hsw),
5707 EVENT_PTR(mem_st_hsw),
5708 NULL,
5709 };
5710
5711 static struct attribute *hsw_tsx_events_attrs[] = {
5712 EVENT_PTR(tx_start),
5713 EVENT_PTR(tx_commit),
5714 EVENT_PTR(tx_abort),
5715 EVENT_PTR(tx_capacity),
5716 EVENT_PTR(tx_conflict),
5717 EVENT_PTR(el_start),
5718 EVENT_PTR(el_commit),
5719 EVENT_PTR(el_abort),
5720 EVENT_PTR(el_capacity),
5721 EVENT_PTR(el_conflict),
5722 EVENT_PTR(cycles_t),
5723 EVENT_PTR(cycles_ct),
5724 NULL
5725 };
5726
5727 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
5728 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
5729 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
5730 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
5731
5732 static struct attribute *icl_events_attrs[] = {
5733 EVENT_PTR(mem_ld_hsw),
5734 EVENT_PTR(mem_st_hsw),
5735 NULL,
5736 };
5737
5738 static struct attribute *icl_td_events_attrs[] = {
5739 EVENT_PTR(slots),
5740 EVENT_PTR(td_retiring),
5741 EVENT_PTR(td_bad_spec),
5742 EVENT_PTR(td_fe_bound),
5743 EVENT_PTR(td_be_bound),
5744 NULL,
5745 };
5746
5747 static struct attribute *icl_tsx_events_attrs[] = {
5748 EVENT_PTR(tx_start),
5749 EVENT_PTR(tx_abort),
5750 EVENT_PTR(tx_commit),
5751 EVENT_PTR(tx_capacity_read),
5752 EVENT_PTR(tx_capacity_write),
5753 EVENT_PTR(tx_conflict),
5754 EVENT_PTR(el_start),
5755 EVENT_PTR(el_abort),
5756 EVENT_PTR(el_commit),
5757 EVENT_PTR(el_capacity_read),
5758 EVENT_PTR(el_capacity_write),
5759 EVENT_PTR(el_conflict),
5760 EVENT_PTR(cycles_t),
5761 EVENT_PTR(cycles_ct),
5762 NULL,
5763 };
5764
5765
5766 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
5767 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
5768
5769 static struct attribute *glc_events_attrs[] = {
5770 EVENT_PTR(mem_ld_hsw),
5771 EVENT_PTR(mem_st_spr),
5772 EVENT_PTR(mem_ld_aux),
5773 NULL,
5774 };
5775
5776 static struct attribute *glc_td_events_attrs[] = {
5777 EVENT_PTR(slots),
5778 EVENT_PTR(td_retiring),
5779 EVENT_PTR(td_bad_spec),
5780 EVENT_PTR(td_fe_bound),
5781 EVENT_PTR(td_be_bound),
5782 EVENT_PTR(td_heavy_ops),
5783 EVENT_PTR(td_br_mispredict),
5784 EVENT_PTR(td_fetch_lat),
5785 EVENT_PTR(td_mem_bound),
5786 NULL,
5787 };
5788
5789 static struct attribute *glc_tsx_events_attrs[] = {
5790 EVENT_PTR(tx_start),
5791 EVENT_PTR(tx_abort),
5792 EVENT_PTR(tx_commit),
5793 EVENT_PTR(tx_capacity_read),
5794 EVENT_PTR(tx_capacity_write),
5795 EVENT_PTR(tx_conflict),
5796 EVENT_PTR(cycles_t),
5797 EVENT_PTR(cycles_ct),
5798 NULL,
5799 };
5800
freeze_on_smi_show(struct device * cdev,struct device_attribute * attr,char * buf)5801 static ssize_t freeze_on_smi_show(struct device *cdev,
5802 struct device_attribute *attr,
5803 char *buf)
5804 {
5805 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
5806 }
5807
5808 static DEFINE_MUTEX(freeze_on_smi_mutex);
5809
freeze_on_smi_store(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)5810 static ssize_t freeze_on_smi_store(struct device *cdev,
5811 struct device_attribute *attr,
5812 const char *buf, size_t count)
5813 {
5814 unsigned long val;
5815 ssize_t ret;
5816
5817 ret = kstrtoul(buf, 0, &val);
5818 if (ret)
5819 return ret;
5820
5821 if (val > 1)
5822 return -EINVAL;
5823
5824 mutex_lock(&freeze_on_smi_mutex);
5825
5826 if (x86_pmu.attr_freeze_on_smi == val)
5827 goto done;
5828
5829 x86_pmu.attr_freeze_on_smi = val;
5830
5831 cpus_read_lock();
5832 on_each_cpu(flip_smm_bit, &val, 1);
5833 cpus_read_unlock();
5834 done:
5835 mutex_unlock(&freeze_on_smi_mutex);
5836
5837 return count;
5838 }
5839
update_tfa_sched(void * ignored)5840 static void update_tfa_sched(void *ignored)
5841 {
5842 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5843
5844 /*
5845 * check if PMC3 is used
5846 * and if so force schedule out for all event types all contexts
5847 */
5848 if (test_bit(3, cpuc->active_mask))
5849 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
5850 }
5851
show_sysctl_tfa(struct device * cdev,struct device_attribute * attr,char * buf)5852 static ssize_t show_sysctl_tfa(struct device *cdev,
5853 struct device_attribute *attr,
5854 char *buf)
5855 {
5856 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
5857 }
5858
set_sysctl_tfa(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)5859 static ssize_t set_sysctl_tfa(struct device *cdev,
5860 struct device_attribute *attr,
5861 const char *buf, size_t count)
5862 {
5863 bool val;
5864 ssize_t ret;
5865
5866 ret = kstrtobool(buf, &val);
5867 if (ret)
5868 return ret;
5869
5870 /* no change */
5871 if (val == allow_tsx_force_abort)
5872 return count;
5873
5874 allow_tsx_force_abort = val;
5875
5876 cpus_read_lock();
5877 on_each_cpu(update_tfa_sched, NULL, 1);
5878 cpus_read_unlock();
5879
5880 return count;
5881 }
5882
5883
5884 static DEVICE_ATTR_RW(freeze_on_smi);
5885
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)5886 static ssize_t branches_show(struct device *cdev,
5887 struct device_attribute *attr,
5888 char *buf)
5889 {
5890 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
5891 }
5892
5893 static DEVICE_ATTR_RO(branches);
5894
branch_counter_nr_show(struct device * cdev,struct device_attribute * attr,char * buf)5895 static ssize_t branch_counter_nr_show(struct device *cdev,
5896 struct device_attribute *attr,
5897 char *buf)
5898 {
5899 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters));
5900 }
5901
5902 static DEVICE_ATTR_RO(branch_counter_nr);
5903
branch_counter_width_show(struct device * cdev,struct device_attribute * attr,char * buf)5904 static ssize_t branch_counter_width_show(struct device *cdev,
5905 struct device_attribute *attr,
5906 char *buf)
5907 {
5908 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS);
5909 }
5910
5911 static DEVICE_ATTR_RO(branch_counter_width);
5912
5913 static struct attribute *lbr_attrs[] = {
5914 &dev_attr_branches.attr,
5915 &dev_attr_branch_counter_nr.attr,
5916 &dev_attr_branch_counter_width.attr,
5917 NULL
5918 };
5919
5920 static umode_t
lbr_is_visible(struct kobject * kobj,struct attribute * attr,int i)5921 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5922 {
5923 /* branches */
5924 if (i == 0)
5925 return x86_pmu.lbr_nr ? attr->mode : 0;
5926
5927 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0;
5928 }
5929
5930 static char pmu_name_str[30];
5931
5932 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str);
5933
5934 static struct attribute *intel_pmu_caps_attrs[] = {
5935 &dev_attr_pmu_name.attr.attr,
5936 NULL
5937 };
5938
5939 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
5940 show_sysctl_tfa,
5941 set_sysctl_tfa);
5942
5943 static struct attribute *intel_pmu_attrs[] = {
5944 &dev_attr_freeze_on_smi.attr,
5945 &dev_attr_allow_tsx_force_abort.attr,
5946 NULL,
5947 };
5948
5949 static umode_t
default_is_visible(struct kobject * kobj,struct attribute * attr,int i)5950 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5951 {
5952 if (attr == &dev_attr_allow_tsx_force_abort.attr)
5953 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
5954
5955 return attr->mode;
5956 }
5957
5958 static umode_t
tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)5959 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5960 {
5961 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
5962 }
5963
5964 static umode_t
pebs_is_visible(struct kobject * kobj,struct attribute * attr,int i)5965 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5966 {
5967 return x86_pmu.pebs ? attr->mode : 0;
5968 }
5969
5970 static umode_t
mem_is_visible(struct kobject * kobj,struct attribute * attr,int i)5971 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5972 {
5973 if (attr == &event_attr_mem_ld_aux.attr.attr)
5974 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;
5975
5976 return pebs_is_visible(kobj, attr, i);
5977 }
5978
5979 static umode_t
exra_is_visible(struct kobject * kobj,struct attribute * attr,int i)5980 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5981 {
5982 return x86_pmu.version >= 2 ? attr->mode : 0;
5983 }
5984
5985 static umode_t
td_is_visible(struct kobject * kobj,struct attribute * attr,int i)5986 td_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5987 {
5988 /*
5989 * Hide the perf metrics topdown events
5990 * if the feature is not enumerated.
5991 */
5992 if (x86_pmu.num_topdown_events)
5993 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0;
5994
5995 return attr->mode;
5996 }
5997
5998 static struct attribute_group group_events_td = {
5999 .name = "events",
6000 .is_visible = td_is_visible,
6001 };
6002
6003 static struct attribute_group group_events_mem = {
6004 .name = "events",
6005 .is_visible = mem_is_visible,
6006 };
6007
6008 static struct attribute_group group_events_tsx = {
6009 .name = "events",
6010 .is_visible = tsx_is_visible,
6011 };
6012
6013 static struct attribute_group group_caps_gen = {
6014 .name = "caps",
6015 .attrs = intel_pmu_caps_attrs,
6016 };
6017
6018 static struct attribute_group group_caps_lbr = {
6019 .name = "caps",
6020 .attrs = lbr_attrs,
6021 .is_visible = lbr_is_visible,
6022 };
6023
6024 static struct attribute_group group_format_extra = {
6025 .name = "format",
6026 .is_visible = exra_is_visible,
6027 };
6028
6029 static struct attribute_group group_format_extra_skl = {
6030 .name = "format",
6031 .is_visible = exra_is_visible,
6032 };
6033
6034 static struct attribute_group group_format_evtsel_ext = {
6035 .name = "format",
6036 .attrs = format_evtsel_ext_attrs,
6037 .is_visible = evtsel_ext_is_visible,
6038 };
6039
6040 static struct attribute_group group_default = {
6041 .attrs = intel_pmu_attrs,
6042 .is_visible = default_is_visible,
6043 };
6044
6045 static const struct attribute_group *attr_update[] = {
6046 &group_events_td,
6047 &group_events_mem,
6048 &group_events_tsx,
6049 &group_caps_gen,
6050 &group_caps_lbr,
6051 &group_format_extra,
6052 &group_format_extra_skl,
6053 &group_format_evtsel_ext,
6054 &group_default,
6055 NULL,
6056 };
6057
6058 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
6059 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
6060 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
6061 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
6062 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
6063 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
6064 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
6065 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
6066 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
6067
6068 static struct attribute *adl_hybrid_events_attrs[] = {
6069 EVENT_PTR(slots_adl),
6070 EVENT_PTR(td_retiring_adl),
6071 EVENT_PTR(td_bad_spec_adl),
6072 EVENT_PTR(td_fe_bound_adl),
6073 EVENT_PTR(td_be_bound_adl),
6074 EVENT_PTR(td_heavy_ops_adl),
6075 EVENT_PTR(td_br_mis_adl),
6076 EVENT_PTR(td_fetch_lat_adl),
6077 EVENT_PTR(td_mem_bound_adl),
6078 NULL,
6079 };
6080
6081 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small);
6082 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small);
6083 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small);
6084
6085 static struct attribute *lnl_hybrid_events_attrs[] = {
6086 EVENT_PTR(slots_adl),
6087 EVENT_PTR(td_retiring_lnl),
6088 EVENT_PTR(td_bad_spec_adl),
6089 EVENT_PTR(td_fe_bound_lnl),
6090 EVENT_PTR(td_be_bound_lnl),
6091 EVENT_PTR(td_heavy_ops_adl),
6092 EVENT_PTR(td_br_mis_adl),
6093 EVENT_PTR(td_fetch_lat_adl),
6094 EVENT_PTR(td_mem_bound_adl),
6095 NULL
6096 };
6097
6098 /* The event string must be in PMU IDX order. */
6099 EVENT_ATTR_STR_HYBRID(topdown-retiring,
6100 td_retiring_arl_h,
6101 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0",
6102 hybrid_big_small_tiny);
6103 EVENT_ATTR_STR_HYBRID(topdown-bad-spec,
6104 td_bad_spec_arl_h,
6105 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0",
6106 hybrid_big_small_tiny);
6107 EVENT_ATTR_STR_HYBRID(topdown-fe-bound,
6108 td_fe_bound_arl_h,
6109 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0",
6110 hybrid_big_small_tiny);
6111 EVENT_ATTR_STR_HYBRID(topdown-be-bound,
6112 td_be_bound_arl_h,
6113 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0",
6114 hybrid_big_small_tiny);
6115
6116 static struct attribute *arl_h_hybrid_events_attrs[] = {
6117 EVENT_PTR(slots_adl),
6118 EVENT_PTR(td_retiring_arl_h),
6119 EVENT_PTR(td_bad_spec_arl_h),
6120 EVENT_PTR(td_fe_bound_arl_h),
6121 EVENT_PTR(td_be_bound_arl_h),
6122 EVENT_PTR(td_heavy_ops_adl),
6123 EVENT_PTR(td_br_mis_adl),
6124 EVENT_PTR(td_fetch_lat_adl),
6125 EVENT_PTR(td_mem_bound_adl),
6126 NULL,
6127 };
6128
6129 /* Must be in IDX order */
6130 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
6131 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
6132 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
6133
6134 static struct attribute *adl_hybrid_mem_attrs[] = {
6135 EVENT_PTR(mem_ld_adl),
6136 EVENT_PTR(mem_st_adl),
6137 EVENT_PTR(mem_ld_aux_adl),
6138 NULL,
6139 };
6140
6141 static struct attribute *mtl_hybrid_mem_attrs[] = {
6142 EVENT_PTR(mem_ld_adl),
6143 EVENT_PTR(mem_st_adl),
6144 NULL
6145 };
6146
6147 EVENT_ATTR_STR_HYBRID(mem-loads,
6148 mem_ld_arl_h,
6149 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3",
6150 hybrid_big_small_tiny);
6151 EVENT_ATTR_STR_HYBRID(mem-stores,
6152 mem_st_arl_h,
6153 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6",
6154 hybrid_big_small_tiny);
6155
6156 static struct attribute *arl_h_hybrid_mem_attrs[] = {
6157 EVENT_PTR(mem_ld_arl_h),
6158 EVENT_PTR(mem_st_arl_h),
6159 NULL,
6160 };
6161
6162 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
6163 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
6164 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
6165 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
6166 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
6167 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
6168 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
6169 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
6170
6171 static struct attribute *adl_hybrid_tsx_attrs[] = {
6172 EVENT_PTR(tx_start_adl),
6173 EVENT_PTR(tx_abort_adl),
6174 EVENT_PTR(tx_commit_adl),
6175 EVENT_PTR(tx_capacity_read_adl),
6176 EVENT_PTR(tx_capacity_write_adl),
6177 EVENT_PTR(tx_conflict_adl),
6178 EVENT_PTR(cycles_t_adl),
6179 EVENT_PTR(cycles_ct_adl),
6180 NULL,
6181 };
6182
6183 FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
6184 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
6185 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny);
6186 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny);
6187 FORMAT_ATTR_HYBRID(frontend, hybrid_big);
6188
6189 #define ADL_HYBRID_RTM_FORMAT_ATTR \
6190 FORMAT_HYBRID_PTR(in_tx), \
6191 FORMAT_HYBRID_PTR(in_tx_cp)
6192
6193 #define ADL_HYBRID_FORMAT_ATTR \
6194 FORMAT_HYBRID_PTR(offcore_rsp), \
6195 FORMAT_HYBRID_PTR(ldlat), \
6196 FORMAT_HYBRID_PTR(frontend)
6197
6198 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
6199 ADL_HYBRID_RTM_FORMAT_ATTR,
6200 ADL_HYBRID_FORMAT_ATTR,
6201 NULL
6202 };
6203
6204 static struct attribute *adl_hybrid_extra_attr[] = {
6205 ADL_HYBRID_FORMAT_ATTR,
6206 NULL
6207 };
6208
6209 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny);
6210
6211 static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
6212 ADL_HYBRID_RTM_FORMAT_ATTR,
6213 ADL_HYBRID_FORMAT_ATTR,
6214 FORMAT_HYBRID_PTR(snoop_rsp),
6215 NULL
6216 };
6217
6218 static struct attribute *mtl_hybrid_extra_attr[] = {
6219 ADL_HYBRID_FORMAT_ATTR,
6220 FORMAT_HYBRID_PTR(snoop_rsp),
6221 NULL
6222 };
6223
is_attr_for_this_pmu(struct kobject * kobj,struct attribute * attr)6224 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
6225 {
6226 struct device *dev = kobj_to_dev(kobj);
6227 struct x86_hybrid_pmu *pmu =
6228 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6229 struct perf_pmu_events_hybrid_attr *pmu_attr =
6230 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
6231
6232 return pmu->pmu_type & pmu_attr->pmu_type;
6233 }
6234
hybrid_events_is_visible(struct kobject * kobj,struct attribute * attr,int i)6235 static umode_t hybrid_events_is_visible(struct kobject *kobj,
6236 struct attribute *attr, int i)
6237 {
6238 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
6239 }
6240
hybrid_find_supported_cpu(struct x86_hybrid_pmu * pmu)6241 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
6242 {
6243 int cpu = cpumask_first(&pmu->supported_cpus);
6244
6245 return (cpu >= nr_cpu_ids) ? -1 : cpu;
6246 }
6247
hybrid_tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)6248 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
6249 struct attribute *attr, int i)
6250 {
6251 struct device *dev = kobj_to_dev(kobj);
6252 struct x86_hybrid_pmu *pmu =
6253 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6254 int cpu = hybrid_find_supported_cpu(pmu);
6255
6256 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
6257 }
6258
hybrid_format_is_visible(struct kobject * kobj,struct attribute * attr,int i)6259 static umode_t hybrid_format_is_visible(struct kobject *kobj,
6260 struct attribute *attr, int i)
6261 {
6262 struct device *dev = kobj_to_dev(kobj);
6263 struct x86_hybrid_pmu *pmu =
6264 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6265 struct perf_pmu_format_hybrid_attr *pmu_attr =
6266 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
6267 int cpu = hybrid_find_supported_cpu(pmu);
6268
6269 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0;
6270 }
6271
hybrid_td_is_visible(struct kobject * kobj,struct attribute * attr,int i)6272 static umode_t hybrid_td_is_visible(struct kobject *kobj,
6273 struct attribute *attr, int i)
6274 {
6275 struct device *dev = kobj_to_dev(kobj);
6276 struct x86_hybrid_pmu *pmu =
6277 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6278
6279 if (!is_attr_for_this_pmu(kobj, attr))
6280 return 0;
6281
6282
6283 /* Only the big core supports perf metrics */
6284 if (pmu->pmu_type == hybrid_big)
6285 return pmu->intel_cap.perf_metrics ? attr->mode : 0;
6286
6287 return attr->mode;
6288 }
6289
6290 static struct attribute_group hybrid_group_events_td = {
6291 .name = "events",
6292 .is_visible = hybrid_td_is_visible,
6293 };
6294
6295 static struct attribute_group hybrid_group_events_mem = {
6296 .name = "events",
6297 .is_visible = hybrid_events_is_visible,
6298 };
6299
6300 static struct attribute_group hybrid_group_events_tsx = {
6301 .name = "events",
6302 .is_visible = hybrid_tsx_is_visible,
6303 };
6304
6305 static struct attribute_group hybrid_group_format_extra = {
6306 .name = "format",
6307 .is_visible = hybrid_format_is_visible,
6308 };
6309
intel_hybrid_get_attr_cpus(struct device * dev,struct device_attribute * attr,char * buf)6310 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
6311 struct device_attribute *attr,
6312 char *buf)
6313 {
6314 struct x86_hybrid_pmu *pmu =
6315 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
6316
6317 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus);
6318 }
6319
6320 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
6321 static struct attribute *intel_hybrid_cpus_attrs[] = {
6322 &dev_attr_cpus.attr,
6323 NULL,
6324 };
6325
6326 static struct attribute_group hybrid_group_cpus = {
6327 .attrs = intel_hybrid_cpus_attrs,
6328 };
6329
6330 static const struct attribute_group *hybrid_attr_update[] = {
6331 &hybrid_group_events_td,
6332 &hybrid_group_events_mem,
6333 &hybrid_group_events_tsx,
6334 &group_caps_gen,
6335 &group_caps_lbr,
6336 &hybrid_group_format_extra,
6337 &group_format_evtsel_ext,
6338 &group_default,
6339 &hybrid_group_cpus,
6340 NULL,
6341 };
6342
6343 static struct attribute *empty_attrs;
6344
intel_pmu_check_event_constraints(struct event_constraint * event_constraints,u64 cntr_mask,u64 fixed_cntr_mask,u64 intel_ctrl)6345 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
6346 u64 cntr_mask,
6347 u64 fixed_cntr_mask,
6348 u64 intel_ctrl)
6349 {
6350 struct event_constraint *c;
6351
6352 if (!event_constraints)
6353 return;
6354
6355 /*
6356 * event on fixed counter2 (REF_CYCLES) only works on this
6357 * counter, so do not extend mask to generic counters
6358 */
6359 for_each_event_constraint(c, event_constraints) {
6360 /*
6361 * Don't extend the topdown slots and metrics
6362 * events to the generic counters.
6363 */
6364 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
6365 /*
6366 * Disable topdown slots and metrics events,
6367 * if slots event is not in CPUID.
6368 */
6369 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
6370 c->idxmsk64 = 0;
6371 c->weight = hweight64(c->idxmsk64);
6372 continue;
6373 }
6374
6375 if (c->cmask == FIXED_EVENT_FLAGS) {
6376 /* Disabled fixed counters which are not in CPUID */
6377 c->idxmsk64 &= intel_ctrl;
6378
6379 /*
6380 * Don't extend the pseudo-encoding to the
6381 * generic counters
6382 */
6383 if (!use_fixed_pseudo_encoding(c->code))
6384 c->idxmsk64 |= cntr_mask;
6385 }
6386 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED);
6387 c->weight = hweight64(c->idxmsk64);
6388 }
6389 }
6390
intel_pmu_check_extra_regs(struct extra_reg * extra_regs)6391 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
6392 {
6393 struct extra_reg *er;
6394
6395 /*
6396 * Access extra MSR may cause #GP under certain circumstances.
6397 * E.g. KVM doesn't support offcore event
6398 * Check all extra_regs here.
6399 */
6400 if (!extra_regs)
6401 return;
6402
6403 for (er = extra_regs; er->msr; er++) {
6404 er->extra_msr_access = check_msr(er->msr, 0x11UL);
6405 /* Disable LBR select mapping */
6406 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
6407 x86_pmu.lbr_sel_map = NULL;
6408 }
6409 }
6410
intel_pmu_v6_addr_offset(int index,bool eventsel)6411 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel)
6412 {
6413 return MSR_IA32_PMC_V6_STEP * index;
6414 }
6415
6416 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
6417 { hybrid_small, "cpu_atom" },
6418 { hybrid_big, "cpu_core" },
6419 { hybrid_tiny, "cpu_lowpower" },
6420 };
6421
intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)6422 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
6423 {
6424 unsigned long pmus_mask = pmus;
6425 struct x86_hybrid_pmu *pmu;
6426 int idx = 0, bit;
6427
6428 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask);
6429 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus,
6430 sizeof(struct x86_hybrid_pmu),
6431 GFP_KERNEL);
6432 if (!x86_pmu.hybrid_pmu)
6433 return -ENOMEM;
6434
6435 static_branch_enable(&perf_is_hybrid);
6436 x86_pmu.filter = intel_pmu_filter;
6437
6438 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) {
6439 pmu = &x86_pmu.hybrid_pmu[idx++];
6440 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id;
6441 pmu->name = intel_hybrid_pmu_type_map[bit].name;
6442
6443 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
6444 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
6445 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
6446 pmu->config_mask = X86_RAW_EVENT_MASK;
6447 pmu->unconstrained = (struct event_constraint)
6448 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
6449 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
6450
6451 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6452 if (pmu->pmu_type & hybrid_small_tiny) {
6453 pmu->intel_cap.perf_metrics = 0;
6454 pmu->mid_ack = true;
6455 } else if (pmu->pmu_type & hybrid_big) {
6456 pmu->intel_cap.perf_metrics = 1;
6457 pmu->late_ack = true;
6458 }
6459 }
6460
6461 return 0;
6462 }
6463
intel_pmu_ref_cycles_ext(void)6464 static __always_inline void intel_pmu_ref_cycles_ext(void)
6465 {
6466 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))
6467 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c;
6468 }
6469
intel_pmu_init_glc(struct pmu * pmu)6470 static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
6471 {
6472 x86_pmu.late_ack = true;
6473 x86_pmu.limit_period = glc_limit_period;
6474 x86_pmu.pebs_aliases = NULL;
6475 x86_pmu.pebs_prec_dist = true;
6476 x86_pmu.pebs_block = true;
6477 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6478 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6479 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6480 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6481 x86_pmu.lbr_pt_coexist = true;
6482 x86_pmu.num_topdown_events = 8;
6483 static_call_update(intel_pmu_update_topdown_event,
6484 &icl_update_topdown_event);
6485 static_call_update(intel_pmu_set_topdown_event_period,
6486 &icl_set_topdown_event_period);
6487
6488 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6489 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6490 hybrid(pmu, event_constraints) = intel_glc_event_constraints;
6491 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
6492
6493 intel_pmu_ref_cycles_ext();
6494 }
6495
intel_pmu_init_grt(struct pmu * pmu)6496 static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
6497 {
6498 x86_pmu.mid_ack = true;
6499 x86_pmu.limit_period = glc_limit_period;
6500 x86_pmu.pebs_aliases = NULL;
6501 x86_pmu.pebs_prec_dist = true;
6502 x86_pmu.pebs_block = true;
6503 x86_pmu.lbr_pt_coexist = true;
6504 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6505 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6506
6507 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6508 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6509 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6510 hybrid(pmu, event_constraints) = intel_grt_event_constraints;
6511 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
6512 hybrid(pmu, extra_regs) = intel_grt_extra_regs;
6513
6514 intel_pmu_ref_cycles_ext();
6515 }
6516
intel_pmu_init_lnc(struct pmu * pmu)6517 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
6518 {
6519 intel_pmu_init_glc(pmu);
6520 hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
6521 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
6522 hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
6523 }
6524
intel_pmu_init_skt(struct pmu * pmu)6525 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
6526 {
6527 intel_pmu_init_grt(pmu);
6528 hybrid(pmu, event_constraints) = intel_skt_event_constraints;
6529 hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
6530 }
6531
intel_pmu_init(void)6532 __init int intel_pmu_init(void)
6533 {
6534 struct attribute **extra_skl_attr = &empty_attrs;
6535 struct attribute **extra_attr = &empty_attrs;
6536 struct attribute **td_attr = &empty_attrs;
6537 struct attribute **mem_attr = &empty_attrs;
6538 struct attribute **tsx_attr = &empty_attrs;
6539 union cpuid10_edx edx;
6540 union cpuid10_eax eax;
6541 union cpuid10_ebx ebx;
6542 unsigned int fixed_mask;
6543 bool pmem = false;
6544 int version, i;
6545 char *name;
6546 struct x86_hybrid_pmu *pmu;
6547
6548 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
6549 switch (boot_cpu_data.x86) {
6550 case 0x6:
6551 return p6_pmu_init();
6552 case 0xb:
6553 return knc_pmu_init();
6554 case 0xf:
6555 return p4_pmu_init();
6556 }
6557 return -ENODEV;
6558 }
6559
6560 /*
6561 * Check whether the Architectural PerfMon supports
6562 * Branch Misses Retired hw_event or not.
6563 */
6564 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
6565 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
6566 return -ENODEV;
6567
6568 version = eax.split.version_id;
6569 if (version < 2)
6570 x86_pmu = core_pmu;
6571 else
6572 x86_pmu = intel_pmu;
6573
6574 x86_pmu.version = version;
6575 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0);
6576 x86_pmu.cntval_bits = eax.split.bit_width;
6577 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
6578
6579 x86_pmu.events_maskl = ebx.full;
6580 x86_pmu.events_mask_len = eax.split.mask_length;
6581
6582 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64);
6583 x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
6584
6585 /*
6586 * Quirk: v2 perfmon does not report fixed-purpose events, so
6587 * assume at least 3 events, when not running in a hypervisor:
6588 */
6589 if (version > 1 && version < 5) {
6590 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
6591
6592 x86_pmu.fixed_cntr_mask64 =
6593 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0);
6594 } else if (version >= 5)
6595 x86_pmu.fixed_cntr_mask64 = fixed_mask;
6596
6597 if (boot_cpu_has(X86_FEATURE_PDCM)) {
6598 u64 capabilities;
6599
6600 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
6601 x86_pmu.intel_cap.capabilities = capabilities;
6602 }
6603
6604 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
6605 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
6606 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
6607 }
6608
6609 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
6610 intel_pmu_arch_lbr_init();
6611
6612 intel_ds_init();
6613
6614 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
6615
6616 if (version >= 5) {
6617 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
6618 if (x86_pmu.intel_cap.anythread_deprecated)
6619 pr_cont(" AnyThread deprecated, ");
6620 }
6621
6622 /*
6623 * Install the hw-cache-events table:
6624 */
6625 switch (boot_cpu_data.x86_vfm) {
6626 case INTEL_CORE_YONAH:
6627 pr_cont("Core events, ");
6628 name = "core";
6629 break;
6630
6631 case INTEL_CORE2_MEROM:
6632 x86_add_quirk(intel_clovertown_quirk);
6633 fallthrough;
6634
6635 case INTEL_CORE2_MEROM_L:
6636 case INTEL_CORE2_PENRYN:
6637 case INTEL_CORE2_DUNNINGTON:
6638 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
6639 sizeof(hw_cache_event_ids));
6640
6641 intel_pmu_lbr_init_core();
6642
6643 x86_pmu.event_constraints = intel_core2_event_constraints;
6644 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
6645 pr_cont("Core2 events, ");
6646 name = "core2";
6647 break;
6648
6649 case INTEL_NEHALEM:
6650 case INTEL_NEHALEM_EP:
6651 case INTEL_NEHALEM_EX:
6652 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
6653 sizeof(hw_cache_event_ids));
6654 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6655 sizeof(hw_cache_extra_regs));
6656
6657 intel_pmu_lbr_init_nhm();
6658
6659 x86_pmu.event_constraints = intel_nehalem_event_constraints;
6660 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
6661 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6662 x86_pmu.extra_regs = intel_nehalem_extra_regs;
6663 x86_pmu.limit_period = nhm_limit_period;
6664
6665 mem_attr = nhm_mem_events_attrs;
6666
6667 /* UOPS_ISSUED.STALLED_CYCLES */
6668 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6669 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6670 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6671 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6672 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6673
6674 intel_pmu_pebs_data_source_nhm();
6675 x86_add_quirk(intel_nehalem_quirk);
6676 x86_pmu.pebs_no_tlb = 1;
6677 extra_attr = nhm_format_attr;
6678
6679 pr_cont("Nehalem events, ");
6680 name = "nehalem";
6681 break;
6682
6683 case INTEL_ATOM_BONNELL:
6684 case INTEL_ATOM_BONNELL_MID:
6685 case INTEL_ATOM_SALTWELL:
6686 case INTEL_ATOM_SALTWELL_MID:
6687 case INTEL_ATOM_SALTWELL_TABLET:
6688 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
6689 sizeof(hw_cache_event_ids));
6690
6691 intel_pmu_lbr_init_atom();
6692
6693 x86_pmu.event_constraints = intel_gen_event_constraints;
6694 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
6695 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
6696 pr_cont("Atom events, ");
6697 name = "bonnell";
6698 break;
6699
6700 case INTEL_ATOM_SILVERMONT:
6701 case INTEL_ATOM_SILVERMONT_D:
6702 case INTEL_ATOM_SILVERMONT_MID:
6703 case INTEL_ATOM_AIRMONT:
6704 case INTEL_ATOM_AIRMONT_MID:
6705 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
6706 sizeof(hw_cache_event_ids));
6707 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
6708 sizeof(hw_cache_extra_regs));
6709
6710 intel_pmu_lbr_init_slm();
6711
6712 x86_pmu.event_constraints = intel_slm_event_constraints;
6713 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6714 x86_pmu.extra_regs = intel_slm_extra_regs;
6715 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6716 td_attr = slm_events_attrs;
6717 extra_attr = slm_format_attr;
6718 pr_cont("Silvermont events, ");
6719 name = "silvermont";
6720 break;
6721
6722 case INTEL_ATOM_GOLDMONT:
6723 case INTEL_ATOM_GOLDMONT_D:
6724 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
6725 sizeof(hw_cache_event_ids));
6726 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
6727 sizeof(hw_cache_extra_regs));
6728
6729 intel_pmu_lbr_init_skl();
6730
6731 x86_pmu.event_constraints = intel_slm_event_constraints;
6732 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
6733 x86_pmu.extra_regs = intel_glm_extra_regs;
6734 /*
6735 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6736 * for precise cycles.
6737 * :pp is identical to :ppp
6738 */
6739 x86_pmu.pebs_aliases = NULL;
6740 x86_pmu.pebs_prec_dist = true;
6741 x86_pmu.lbr_pt_coexist = true;
6742 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6743 td_attr = glm_events_attrs;
6744 extra_attr = slm_format_attr;
6745 pr_cont("Goldmont events, ");
6746 name = "goldmont";
6747 break;
6748
6749 case INTEL_ATOM_GOLDMONT_PLUS:
6750 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6751 sizeof(hw_cache_event_ids));
6752 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
6753 sizeof(hw_cache_extra_regs));
6754
6755 intel_pmu_lbr_init_skl();
6756
6757 x86_pmu.event_constraints = intel_slm_event_constraints;
6758 x86_pmu.extra_regs = intel_glm_extra_regs;
6759 /*
6760 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6761 * for precise cycles.
6762 */
6763 x86_pmu.pebs_aliases = NULL;
6764 x86_pmu.pebs_prec_dist = true;
6765 x86_pmu.lbr_pt_coexist = true;
6766 x86_pmu.pebs_capable = ~0ULL;
6767 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6768 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6769 x86_pmu.get_event_constraints = glp_get_event_constraints;
6770 td_attr = glm_events_attrs;
6771 /* Goldmont Plus has 4-wide pipeline */
6772 event_attr_td_total_slots_scale_glm.event_str = "4";
6773 extra_attr = slm_format_attr;
6774 pr_cont("Goldmont plus events, ");
6775 name = "goldmont_plus";
6776 break;
6777
6778 case INTEL_ATOM_TREMONT_D:
6779 case INTEL_ATOM_TREMONT:
6780 case INTEL_ATOM_TREMONT_L:
6781 x86_pmu.late_ack = true;
6782 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6783 sizeof(hw_cache_event_ids));
6784 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
6785 sizeof(hw_cache_extra_regs));
6786 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6787
6788 intel_pmu_lbr_init_skl();
6789
6790 x86_pmu.event_constraints = intel_slm_event_constraints;
6791 x86_pmu.extra_regs = intel_tnt_extra_regs;
6792 /*
6793 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6794 * for precise cycles.
6795 */
6796 x86_pmu.pebs_aliases = NULL;
6797 x86_pmu.pebs_prec_dist = true;
6798 x86_pmu.lbr_pt_coexist = true;
6799 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6800 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6801 td_attr = tnt_events_attrs;
6802 extra_attr = slm_format_attr;
6803 pr_cont("Tremont events, ");
6804 name = "Tremont";
6805 break;
6806
6807 case INTEL_ATOM_GRACEMONT:
6808 intel_pmu_init_grt(NULL);
6809 intel_pmu_pebs_data_source_grt();
6810 x86_pmu.pebs_latency_data = grt_latency_data;
6811 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6812 td_attr = tnt_events_attrs;
6813 mem_attr = grt_mem_attrs;
6814 extra_attr = nhm_format_attr;
6815 pr_cont("Gracemont events, ");
6816 name = "gracemont";
6817 break;
6818
6819 case INTEL_ATOM_CRESTMONT:
6820 case INTEL_ATOM_CRESTMONT_X:
6821 intel_pmu_init_grt(NULL);
6822 x86_pmu.extra_regs = intel_cmt_extra_regs;
6823 intel_pmu_pebs_data_source_cmt();
6824 x86_pmu.pebs_latency_data = cmt_latency_data;
6825 x86_pmu.get_event_constraints = cmt_get_event_constraints;
6826 td_attr = cmt_events_attrs;
6827 mem_attr = grt_mem_attrs;
6828 extra_attr = cmt_format_attr;
6829 pr_cont("Crestmont events, ");
6830 name = "crestmont";
6831 break;
6832
6833 case INTEL_WESTMERE:
6834 case INTEL_WESTMERE_EP:
6835 case INTEL_WESTMERE_EX:
6836 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
6837 sizeof(hw_cache_event_ids));
6838 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6839 sizeof(hw_cache_extra_regs));
6840
6841 intel_pmu_lbr_init_nhm();
6842
6843 x86_pmu.event_constraints = intel_westmere_event_constraints;
6844 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6845 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
6846 x86_pmu.extra_regs = intel_westmere_extra_regs;
6847 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6848
6849 mem_attr = nhm_mem_events_attrs;
6850
6851 /* UOPS_ISSUED.STALLED_CYCLES */
6852 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6853 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6854 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6855 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6856 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6857
6858 intel_pmu_pebs_data_source_nhm();
6859 extra_attr = nhm_format_attr;
6860 pr_cont("Westmere events, ");
6861 name = "westmere";
6862 break;
6863
6864 case INTEL_SANDYBRIDGE:
6865 case INTEL_SANDYBRIDGE_X:
6866 x86_add_quirk(intel_sandybridge_quirk);
6867 x86_add_quirk(intel_ht_bug);
6868 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6869 sizeof(hw_cache_event_ids));
6870 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6871 sizeof(hw_cache_extra_regs));
6872
6873 intel_pmu_lbr_init_snb();
6874
6875 x86_pmu.event_constraints = intel_snb_event_constraints;
6876 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
6877 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
6878 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X)
6879 x86_pmu.extra_regs = intel_snbep_extra_regs;
6880 else
6881 x86_pmu.extra_regs = intel_snb_extra_regs;
6882
6883
6884 /* all extra regs are per-cpu when HT is on */
6885 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6886 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6887
6888 td_attr = snb_events_attrs;
6889 mem_attr = snb_mem_events_attrs;
6890
6891 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6892 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6893 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6894 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
6895 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6896 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
6897
6898 extra_attr = nhm_format_attr;
6899
6900 pr_cont("SandyBridge events, ");
6901 name = "sandybridge";
6902 break;
6903
6904 case INTEL_IVYBRIDGE:
6905 case INTEL_IVYBRIDGE_X:
6906 x86_add_quirk(intel_ht_bug);
6907 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6908 sizeof(hw_cache_event_ids));
6909 /* dTLB-load-misses on IVB is different than SNB */
6910 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
6911
6912 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6913 sizeof(hw_cache_extra_regs));
6914
6915 intel_pmu_lbr_init_snb();
6916
6917 x86_pmu.event_constraints = intel_ivb_event_constraints;
6918 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
6919 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6920 x86_pmu.pebs_prec_dist = true;
6921 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X)
6922 x86_pmu.extra_regs = intel_snbep_extra_regs;
6923 else
6924 x86_pmu.extra_regs = intel_snb_extra_regs;
6925 /* all extra regs are per-cpu when HT is on */
6926 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6927 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6928
6929 td_attr = snb_events_attrs;
6930 mem_attr = snb_mem_events_attrs;
6931
6932 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6933 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6934 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6935
6936 extra_attr = nhm_format_attr;
6937
6938 pr_cont("IvyBridge events, ");
6939 name = "ivybridge";
6940 break;
6941
6942
6943 case INTEL_HASWELL:
6944 case INTEL_HASWELL_X:
6945 case INTEL_HASWELL_L:
6946 case INTEL_HASWELL_G:
6947 x86_add_quirk(intel_ht_bug);
6948 x86_add_quirk(intel_pebs_isolation_quirk);
6949 x86_pmu.late_ack = true;
6950 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6951 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6952
6953 intel_pmu_lbr_init_hsw();
6954
6955 x86_pmu.event_constraints = intel_hsw_event_constraints;
6956 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
6957 x86_pmu.extra_regs = intel_snbep_extra_regs;
6958 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6959 x86_pmu.pebs_prec_dist = true;
6960 /* all extra regs are per-cpu when HT is on */
6961 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6962 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6963
6964 x86_pmu.hw_config = hsw_hw_config;
6965 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6966 x86_pmu.limit_period = hsw_limit_period;
6967 x86_pmu.lbr_double_abort = true;
6968 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6969 hsw_format_attr : nhm_format_attr;
6970 td_attr = hsw_events_attrs;
6971 mem_attr = hsw_mem_events_attrs;
6972 tsx_attr = hsw_tsx_events_attrs;
6973 pr_cont("Haswell events, ");
6974 name = "haswell";
6975 break;
6976
6977 case INTEL_BROADWELL:
6978 case INTEL_BROADWELL_D:
6979 case INTEL_BROADWELL_G:
6980 case INTEL_BROADWELL_X:
6981 x86_add_quirk(intel_pebs_isolation_quirk);
6982 x86_pmu.late_ack = true;
6983 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6984 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6985
6986 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
6987 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
6988 BDW_L3_MISS|HSW_SNOOP_DRAM;
6989 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
6990 HSW_SNOOP_DRAM;
6991 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
6992 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6993 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
6994 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6995
6996 intel_pmu_lbr_init_hsw();
6997
6998 x86_pmu.event_constraints = intel_bdw_event_constraints;
6999 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
7000 x86_pmu.extra_regs = intel_snbep_extra_regs;
7001 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
7002 x86_pmu.pebs_prec_dist = true;
7003 /* all extra regs are per-cpu when HT is on */
7004 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7005 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7006
7007 x86_pmu.hw_config = hsw_hw_config;
7008 x86_pmu.get_event_constraints = hsw_get_event_constraints;
7009 x86_pmu.limit_period = bdw_limit_period;
7010 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7011 hsw_format_attr : nhm_format_attr;
7012 td_attr = hsw_events_attrs;
7013 mem_attr = hsw_mem_events_attrs;
7014 tsx_attr = hsw_tsx_events_attrs;
7015 pr_cont("Broadwell events, ");
7016 name = "broadwell";
7017 break;
7018
7019 case INTEL_XEON_PHI_KNL:
7020 case INTEL_XEON_PHI_KNM:
7021 memcpy(hw_cache_event_ids,
7022 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7023 memcpy(hw_cache_extra_regs,
7024 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7025 intel_pmu_lbr_init_knl();
7026
7027 x86_pmu.event_constraints = intel_slm_event_constraints;
7028 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
7029 x86_pmu.extra_regs = intel_knl_extra_regs;
7030
7031 /* all extra regs are per-cpu when HT is on */
7032 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7033 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7034 extra_attr = slm_format_attr;
7035 pr_cont("Knights Landing/Mill events, ");
7036 name = "knights-landing";
7037 break;
7038
7039 case INTEL_SKYLAKE_X:
7040 pmem = true;
7041 fallthrough;
7042 case INTEL_SKYLAKE_L:
7043 case INTEL_SKYLAKE:
7044 case INTEL_KABYLAKE_L:
7045 case INTEL_KABYLAKE:
7046 case INTEL_COMETLAKE_L:
7047 case INTEL_COMETLAKE:
7048 x86_add_quirk(intel_pebs_isolation_quirk);
7049 x86_pmu.late_ack = true;
7050 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7051 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7052 intel_pmu_lbr_init_skl();
7053
7054 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
7055 event_attr_td_recovery_bubbles.event_str_noht =
7056 "event=0xd,umask=0x1,cmask=1";
7057 event_attr_td_recovery_bubbles.event_str_ht =
7058 "event=0xd,umask=0x1,cmask=1,any=1";
7059
7060 x86_pmu.event_constraints = intel_skl_event_constraints;
7061 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
7062 x86_pmu.extra_regs = intel_skl_extra_regs;
7063 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
7064 x86_pmu.pebs_prec_dist = true;
7065 /* all extra regs are per-cpu when HT is on */
7066 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7067 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7068
7069 x86_pmu.hw_config = hsw_hw_config;
7070 x86_pmu.get_event_constraints = hsw_get_event_constraints;
7071 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7072 hsw_format_attr : nhm_format_attr;
7073 extra_skl_attr = skl_format_attr;
7074 td_attr = hsw_events_attrs;
7075 mem_attr = hsw_mem_events_attrs;
7076 tsx_attr = hsw_tsx_events_attrs;
7077 intel_pmu_pebs_data_source_skl(pmem);
7078
7079 /*
7080 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
7081 * TSX force abort hooks are not required on these systems. Only deploy
7082 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
7083 */
7084 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
7085 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
7086 x86_pmu.flags |= PMU_FL_TFA;
7087 x86_pmu.get_event_constraints = tfa_get_event_constraints;
7088 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
7089 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
7090 }
7091
7092 pr_cont("Skylake events, ");
7093 name = "skylake";
7094 break;
7095
7096 case INTEL_ICELAKE_X:
7097 case INTEL_ICELAKE_D:
7098 x86_pmu.pebs_ept = 1;
7099 pmem = true;
7100 fallthrough;
7101 case INTEL_ICELAKE_L:
7102 case INTEL_ICELAKE:
7103 case INTEL_TIGERLAKE_L:
7104 case INTEL_TIGERLAKE:
7105 case INTEL_ROCKETLAKE:
7106 x86_pmu.late_ack = true;
7107 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7108 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7109 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7110 intel_pmu_lbr_init_skl();
7111
7112 x86_pmu.event_constraints = intel_icl_event_constraints;
7113 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
7114 x86_pmu.extra_regs = intel_icl_extra_regs;
7115 x86_pmu.pebs_aliases = NULL;
7116 x86_pmu.pebs_prec_dist = true;
7117 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7118 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7119
7120 x86_pmu.hw_config = hsw_hw_config;
7121 x86_pmu.get_event_constraints = icl_get_event_constraints;
7122 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7123 hsw_format_attr : nhm_format_attr;
7124 extra_skl_attr = skl_format_attr;
7125 mem_attr = icl_events_attrs;
7126 td_attr = icl_td_events_attrs;
7127 tsx_attr = icl_tsx_events_attrs;
7128 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
7129 x86_pmu.lbr_pt_coexist = true;
7130 intel_pmu_pebs_data_source_skl(pmem);
7131 x86_pmu.num_topdown_events = 4;
7132 static_call_update(intel_pmu_update_topdown_event,
7133 &icl_update_topdown_event);
7134 static_call_update(intel_pmu_set_topdown_event_period,
7135 &icl_set_topdown_event_period);
7136 pr_cont("Icelake events, ");
7137 name = "icelake";
7138 break;
7139
7140 case INTEL_SAPPHIRERAPIDS_X:
7141 case INTEL_EMERALDRAPIDS_X:
7142 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
7143 x86_pmu.extra_regs = intel_glc_extra_regs;
7144 pr_cont("Sapphire Rapids events, ");
7145 name = "sapphire_rapids";
7146 goto glc_common;
7147
7148 case INTEL_GRANITERAPIDS_X:
7149 case INTEL_GRANITERAPIDS_D:
7150 x86_pmu.extra_regs = intel_rwc_extra_regs;
7151 pr_cont("Granite Rapids events, ");
7152 name = "granite_rapids";
7153
7154 glc_common:
7155 intel_pmu_init_glc(NULL);
7156 x86_pmu.pebs_ept = 1;
7157 x86_pmu.hw_config = hsw_hw_config;
7158 x86_pmu.get_event_constraints = glc_get_event_constraints;
7159 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7160 hsw_format_attr : nhm_format_attr;
7161 extra_skl_attr = skl_format_attr;
7162 mem_attr = glc_events_attrs;
7163 td_attr = glc_td_events_attrs;
7164 tsx_attr = glc_tsx_events_attrs;
7165 intel_pmu_pebs_data_source_skl(true);
7166 break;
7167
7168 case INTEL_ALDERLAKE:
7169 case INTEL_ALDERLAKE_L:
7170 case INTEL_RAPTORLAKE:
7171 case INTEL_RAPTORLAKE_P:
7172 case INTEL_RAPTORLAKE_S:
7173 /*
7174 * Alder Lake has 2 types of CPU, core and atom.
7175 *
7176 * Initialize the common PerfMon capabilities here.
7177 */
7178 intel_pmu_init_hybrid(hybrid_big_small);
7179
7180 x86_pmu.pebs_latency_data = grt_latency_data;
7181 x86_pmu.get_event_constraints = adl_get_event_constraints;
7182 x86_pmu.hw_config = adl_hw_config;
7183 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
7184
7185 td_attr = adl_hybrid_events_attrs;
7186 mem_attr = adl_hybrid_mem_attrs;
7187 tsx_attr = adl_hybrid_tsx_attrs;
7188 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7189 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
7190
7191 /* Initialize big core specific PerfMon capabilities.*/
7192 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7193 intel_pmu_init_glc(&pmu->pmu);
7194 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
7195 pmu->cntr_mask64 <<= 2;
7196 pmu->cntr_mask64 |= 0x3;
7197 pmu->fixed_cntr_mask64 <<= 1;
7198 pmu->fixed_cntr_mask64 |= 0x1;
7199 } else {
7200 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7201 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7202 }
7203
7204 /*
7205 * Quirk: For some Alder Lake machine, when all E-cores are disabled in
7206 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
7207 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
7208 * mistakenly add extra counters for P-cores. Correct the number of
7209 * counters here.
7210 */
7211 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) {
7212 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7213 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7214 }
7215
7216 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
7217 pmu->unconstrained = (struct event_constraint)
7218 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
7219 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
7220
7221 pmu->extra_regs = intel_glc_extra_regs;
7222
7223 /* Initialize Atom core specific PerfMon capabilities.*/
7224 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7225 intel_pmu_init_grt(&pmu->pmu);
7226
7227 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
7228 intel_pmu_pebs_data_source_adl();
7229 pr_cont("Alderlake Hybrid events, ");
7230 name = "alderlake_hybrid";
7231 break;
7232
7233 case INTEL_METEORLAKE:
7234 case INTEL_METEORLAKE_L:
7235 case INTEL_ARROWLAKE_U:
7236 intel_pmu_init_hybrid(hybrid_big_small);
7237
7238 x86_pmu.pebs_latency_data = cmt_latency_data;
7239 x86_pmu.get_event_constraints = mtl_get_event_constraints;
7240 x86_pmu.hw_config = adl_hw_config;
7241
7242 td_attr = adl_hybrid_events_attrs;
7243 mem_attr = mtl_hybrid_mem_attrs;
7244 tsx_attr = adl_hybrid_tsx_attrs;
7245 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7246 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7247
7248 /* Initialize big core specific PerfMon capabilities.*/
7249 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7250 intel_pmu_init_glc(&pmu->pmu);
7251 pmu->extra_regs = intel_rwc_extra_regs;
7252
7253 /* Initialize Atom core specific PerfMon capabilities.*/
7254 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7255 intel_pmu_init_grt(&pmu->pmu);
7256 pmu->extra_regs = intel_cmt_extra_regs;
7257
7258 intel_pmu_pebs_data_source_mtl();
7259 pr_cont("Meteorlake Hybrid events, ");
7260 name = "meteorlake_hybrid";
7261 break;
7262
7263 case INTEL_LUNARLAKE_M:
7264 case INTEL_ARROWLAKE:
7265 intel_pmu_init_hybrid(hybrid_big_small);
7266
7267 x86_pmu.pebs_latency_data = lnl_latency_data;
7268 x86_pmu.get_event_constraints = mtl_get_event_constraints;
7269 x86_pmu.hw_config = adl_hw_config;
7270
7271 td_attr = lnl_hybrid_events_attrs;
7272 mem_attr = mtl_hybrid_mem_attrs;
7273 tsx_attr = adl_hybrid_tsx_attrs;
7274 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7275 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7276
7277 /* Initialize big core specific PerfMon capabilities.*/
7278 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7279 intel_pmu_init_lnc(&pmu->pmu);
7280
7281 /* Initialize Atom core specific PerfMon capabilities.*/
7282 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7283 intel_pmu_init_skt(&pmu->pmu);
7284
7285 intel_pmu_pebs_data_source_lnl();
7286 pr_cont("Lunarlake Hybrid events, ");
7287 name = "lunarlake_hybrid";
7288 break;
7289
7290 case INTEL_ARROWLAKE_H:
7291 intel_pmu_init_hybrid(hybrid_big_small_tiny);
7292
7293 x86_pmu.pebs_latency_data = arl_h_latency_data;
7294 x86_pmu.get_event_constraints = arl_h_get_event_constraints;
7295 x86_pmu.hw_config = arl_h_hw_config;
7296
7297 td_attr = arl_h_hybrid_events_attrs;
7298 mem_attr = arl_h_hybrid_mem_attrs;
7299 tsx_attr = adl_hybrid_tsx_attrs;
7300 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
7301 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
7302
7303 /* Initialize big core specific PerfMon capabilities. */
7304 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
7305 intel_pmu_init_lnc(&pmu->pmu);
7306
7307 /* Initialize Atom core specific PerfMon capabilities. */
7308 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
7309 intel_pmu_init_skt(&pmu->pmu);
7310
7311 /* Initialize Lower Power Atom specific PerfMon capabilities. */
7312 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];
7313 intel_pmu_init_grt(&pmu->pmu);
7314 pmu->extra_regs = intel_cmt_extra_regs;
7315
7316 intel_pmu_pebs_data_source_arl_h();
7317 pr_cont("ArrowLake-H Hybrid events, ");
7318 name = "arrowlake_h_hybrid";
7319 break;
7320
7321 default:
7322 switch (x86_pmu.version) {
7323 case 1:
7324 x86_pmu.event_constraints = intel_v1_event_constraints;
7325 pr_cont("generic architected perfmon v1, ");
7326 name = "generic_arch_v1";
7327 break;
7328 case 2:
7329 case 3:
7330 case 4:
7331 /*
7332 * default constraints for v2 and up
7333 */
7334 x86_pmu.event_constraints = intel_gen_event_constraints;
7335 pr_cont("generic architected perfmon, ");
7336 name = "generic_arch_v2+";
7337 break;
7338 default:
7339 /*
7340 * The default constraints for v5 and up can support up to
7341 * 16 fixed counters. For the fixed counters 4 and later,
7342 * the pseudo-encoding is applied.
7343 * The constraints may be cut according to the CPUID enumeration
7344 * by inserting the EVENT_CONSTRAINT_END.
7345 */
7346 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED)
7347 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
7348 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1;
7349 x86_pmu.event_constraints = intel_v5_gen_event_constraints;
7350 pr_cont("generic architected perfmon, ");
7351 name = "generic_arch_v5+";
7352 break;
7353 }
7354 }
7355
7356 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
7357
7358 if (!is_hybrid()) {
7359 group_events_td.attrs = td_attr;
7360 group_events_mem.attrs = mem_attr;
7361 group_events_tsx.attrs = tsx_attr;
7362 group_format_extra.attrs = extra_attr;
7363 group_format_extra_skl.attrs = extra_skl_attr;
7364
7365 x86_pmu.attr_update = attr_update;
7366 } else {
7367 hybrid_group_events_td.attrs = td_attr;
7368 hybrid_group_events_mem.attrs = mem_attr;
7369 hybrid_group_events_tsx.attrs = tsx_attr;
7370 hybrid_group_format_extra.attrs = extra_attr;
7371
7372 x86_pmu.attr_update = hybrid_attr_update;
7373 }
7374
7375 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64,
7376 &x86_pmu.fixed_cntr_mask64,
7377 &x86_pmu.intel_ctrl);
7378
7379 /* AnyThread may be deprecated on arch perfmon v5 or later */
7380 if (x86_pmu.intel_cap.anythread_deprecated)
7381 x86_pmu.format_attrs = intel_arch_formats_attr;
7382
7383 intel_pmu_check_event_constraints(x86_pmu.event_constraints,
7384 x86_pmu.cntr_mask64,
7385 x86_pmu.fixed_cntr_mask64,
7386 x86_pmu.intel_ctrl);
7387 /*
7388 * Access LBR MSR may cause #GP under certain circumstances.
7389 * Check all LBR MSR here.
7390 * Disable LBR access if any LBR MSRs can not be accessed.
7391 */
7392 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
7393 x86_pmu.lbr_nr = 0;
7394 for (i = 0; i < x86_pmu.lbr_nr; i++) {
7395 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
7396 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
7397 x86_pmu.lbr_nr = 0;
7398 }
7399
7400 if (x86_pmu.lbr_nr) {
7401 intel_pmu_lbr_init();
7402
7403 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
7404
7405 /* only support branch_stack snapshot for perfmon >= v2 */
7406 if (x86_pmu.disable_all == intel_pmu_disable_all) {
7407 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
7408 static_call_update(perf_snapshot_branch_stack,
7409 intel_pmu_snapshot_arch_branch_stack);
7410 } else {
7411 static_call_update(perf_snapshot_branch_stack,
7412 intel_pmu_snapshot_branch_stack);
7413 }
7414 }
7415 }
7416
7417 intel_pmu_check_extra_regs(x86_pmu.extra_regs);
7418
7419 /* Support full width counters using alternative MSR range */
7420 if (x86_pmu.intel_cap.full_width_write) {
7421 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
7422 x86_pmu.perfctr = MSR_IA32_PMC0;
7423 pr_cont("full-width counters, ");
7424 }
7425
7426 /* Support V6+ MSR Aliasing */
7427 if (x86_pmu.version >= 6) {
7428 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR;
7429 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A;
7430 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR;
7431 x86_pmu.addr_offset = intel_pmu_v6_addr_offset;
7432 }
7433
7434 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
7435 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
7436
7437 if (x86_pmu.intel_cap.pebs_timing_info)
7438 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
7439
7440 intel_aux_output_init();
7441
7442 return 0;
7443 }
7444
7445 /*
7446 * HT bug: phase 2 init
7447 * Called once we have valid topology information to check
7448 * whether or not HT is enabled
7449 * If HT is off, then we disable the workaround
7450 */
fixup_ht_bug(void)7451 static __init int fixup_ht_bug(void)
7452 {
7453 int c;
7454 /*
7455 * problem not present on this CPU model, nothing to do
7456 */
7457 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
7458 return 0;
7459
7460 if (topology_max_smt_threads() > 1) {
7461 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
7462 return 0;
7463 }
7464
7465 cpus_read_lock();
7466
7467 hardlockup_detector_perf_stop();
7468
7469 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
7470
7471 x86_pmu.start_scheduling = NULL;
7472 x86_pmu.commit_scheduling = NULL;
7473 x86_pmu.stop_scheduling = NULL;
7474
7475 hardlockup_detector_perf_restart();
7476
7477 for_each_online_cpu(c)
7478 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
7479
7480 cpus_read_unlock();
7481 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
7482 return 0;
7483 }
7484 subsys_initcall(fixup_ht_bug)
7485