1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support for Medifield PNW Camera Imaging ISP subsystem.
4 *
5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved.
6 *
7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
8 */
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/pm_domain.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/pm_qos.h>
14 #include <linux/timer.h>
15 #include <linux/delay.h>
16 #include <linux/dmi.h>
17 #include <linux/interrupt.h>
18 #include <linux/bits.h>
19 #include <media/v4l2-fwnode.h>
20
21 #include <asm/iosf_mbi.h>
22
23 #include "../../include/linux/atomisp_gmin_platform.h"
24
25 #include "atomisp_cmd.h"
26 #include "atomisp_common.h"
27 #include "atomisp_fops.h"
28 #include "atomisp_ioctl.h"
29 #include "atomisp_internal.h"
30 #include "atomisp-regs.h"
31 #include "atomisp_dfs_tables.h"
32 #include "atomisp_drvfs.h"
33 #include "hmm/hmm.h"
34 #include "atomisp_trace_event.h"
35
36 #include "sh_css_firmware.h"
37
38 #include "device_access.h"
39
40 /* Timeouts to wait for all subdevs to be registered */
41 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */
42 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */
43
44 /* G-Min addition: pull this in from intel_mid_pm.h */
45 #define CSTATE_EXIT_LATENCY_C1 1
46
47 /* cross component debug message flag */
48 int dbg_level;
49 module_param(dbg_level, int, 0644);
50 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)");
51
52 /* log function switch */
53 int dbg_func = 1;
54 module_param(dbg_func, int, 0644);
55 MODULE_PARM_DESC(dbg_func,
56 "log function switch non/printk (default:printk)");
57
58 /*
59 * Set to 16x16 since this is the amount of lines and pixels the sensor
60 * exports extra. If these are kept at the 10x8 that they were on, in yuv
61 * downscaling modes incorrect resolutions where requested to the sensor
62 * driver with strange outcomes as a result. The proper way tot do this
63 * would be to have a list of tables the specify the sensor res, mipi rec,
64 * output res, and isp output res. however since we do not have this yet,
65 * the chosen solution is the next best thing.
66 */
67 int pad_w = 16;
68 module_param(pad_w, int, 0644);
69 MODULE_PARM_DESC(pad_w, "extra data for ISP processing");
70
71 int pad_h = 16;
72 module_param(pad_h, int, 0644);
73 MODULE_PARM_DESC(pad_h, "extra data for ISP processing");
74
75 /*
76 * FIXME: this is a hack to make easier to support ISP2401 variant.
77 * As a given system will either be ISP2401 or not, we can just use
78 * a boolean, in order to replace existing #ifdef ISP2401 everywhere.
79 *
80 * Once this driver gets into a better shape, however, the best would
81 * be to replace this to something stored inside atomisp allocated
82 * structures.
83 */
84
85 struct device *atomisp_dev;
86
87 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
88 {
89 .width = ISP_FREQ_RULE_ANY,
90 .height = ISP_FREQ_RULE_ANY,
91 .fps = ISP_FREQ_RULE_ANY,
92 .isp_freq = ISP_FREQ_400MHZ,
93 .run_mode = ATOMISP_RUN_MODE_VIDEO,
94 },
95 {
96 .width = ISP_FREQ_RULE_ANY,
97 .height = ISP_FREQ_RULE_ANY,
98 .fps = ISP_FREQ_RULE_ANY,
99 .isp_freq = ISP_FREQ_400MHZ,
100 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
101 },
102 {
103 .width = ISP_FREQ_RULE_ANY,
104 .height = ISP_FREQ_RULE_ANY,
105 .fps = ISP_FREQ_RULE_ANY,
106 .isp_freq = ISP_FREQ_400MHZ,
107 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
108 },
109 };
110
111 /* Merrifield and Moorefield DFS rules */
112 static const struct atomisp_dfs_config dfs_config_merr = {
113 .lowest_freq = ISP_FREQ_200MHZ,
114 .max_freq_at_vmin = ISP_FREQ_400MHZ,
115 .highest_freq = ISP_FREQ_457MHZ,
116 .dfs_table = dfs_rules_merr,
117 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
118 };
119
120 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
121 {
122 .width = ISP_FREQ_RULE_ANY,
123 .height = ISP_FREQ_RULE_ANY,
124 .fps = ISP_FREQ_RULE_ANY,
125 .isp_freq = ISP_FREQ_400MHZ,
126 .run_mode = ATOMISP_RUN_MODE_VIDEO,
127 },
128 {
129 .width = ISP_FREQ_RULE_ANY,
130 .height = ISP_FREQ_RULE_ANY,
131 .fps = ISP_FREQ_RULE_ANY,
132 .isp_freq = ISP_FREQ_400MHZ,
133 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
134 },
135 {
136 .width = ISP_FREQ_RULE_ANY,
137 .height = ISP_FREQ_RULE_ANY,
138 .fps = ISP_FREQ_RULE_ANY,
139 .isp_freq = ISP_FREQ_400MHZ,
140 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
141 },
142 };
143
144 static const struct atomisp_dfs_config dfs_config_merr_1179 = {
145 .lowest_freq = ISP_FREQ_200MHZ,
146 .max_freq_at_vmin = ISP_FREQ_400MHZ,
147 .highest_freq = ISP_FREQ_400MHZ,
148 .dfs_table = dfs_rules_merr_1179,
149 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
150 };
151
152 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
153 {
154 .width = 1920,
155 .height = 1080,
156 .fps = 30,
157 .isp_freq = ISP_FREQ_266MHZ,
158 .run_mode = ATOMISP_RUN_MODE_VIDEO,
159 },
160 {
161 .width = 1080,
162 .height = 1920,
163 .fps = 30,
164 .isp_freq = ISP_FREQ_266MHZ,
165 .run_mode = ATOMISP_RUN_MODE_VIDEO,
166 },
167 {
168 .width = 1920,
169 .height = 1080,
170 .fps = 45,
171 .isp_freq = ISP_FREQ_320MHZ,
172 .run_mode = ATOMISP_RUN_MODE_VIDEO,
173 },
174 {
175 .width = 1080,
176 .height = 1920,
177 .fps = 45,
178 .isp_freq = ISP_FREQ_320MHZ,
179 .run_mode = ATOMISP_RUN_MODE_VIDEO,
180 },
181 {
182 .width = ISP_FREQ_RULE_ANY,
183 .height = ISP_FREQ_RULE_ANY,
184 .fps = 60,
185 .isp_freq = ISP_FREQ_356MHZ,
186 .run_mode = ATOMISP_RUN_MODE_VIDEO,
187 },
188 {
189 .width = ISP_FREQ_RULE_ANY,
190 .height = ISP_FREQ_RULE_ANY,
191 .fps = ISP_FREQ_RULE_ANY,
192 .isp_freq = ISP_FREQ_200MHZ,
193 .run_mode = ATOMISP_RUN_MODE_VIDEO,
194 },
195 {
196 .width = ISP_FREQ_RULE_ANY,
197 .height = ISP_FREQ_RULE_ANY,
198 .fps = ISP_FREQ_RULE_ANY,
199 .isp_freq = ISP_FREQ_400MHZ,
200 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
201 },
202 {
203 .width = ISP_FREQ_RULE_ANY,
204 .height = ISP_FREQ_RULE_ANY,
205 .fps = ISP_FREQ_RULE_ANY,
206 .isp_freq = ISP_FREQ_200MHZ,
207 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
208 },
209 };
210
211 static struct atomisp_dfs_config dfs_config_merr_117a = {
212 .lowest_freq = ISP_FREQ_200MHZ,
213 .max_freq_at_vmin = ISP_FREQ_200MHZ,
214 .highest_freq = ISP_FREQ_400MHZ,
215 .dfs_table = dfs_rules_merr_117a,
216 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
217 };
218
219 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
220 {
221 .width = ISP_FREQ_RULE_ANY,
222 .height = ISP_FREQ_RULE_ANY,
223 .fps = ISP_FREQ_RULE_ANY,
224 .isp_freq = ISP_FREQ_400MHZ,
225 .run_mode = ATOMISP_RUN_MODE_VIDEO,
226 },
227 {
228 .width = ISP_FREQ_RULE_ANY,
229 .height = ISP_FREQ_RULE_ANY,
230 .fps = ISP_FREQ_RULE_ANY,
231 .isp_freq = ISP_FREQ_400MHZ,
232 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
233 },
234 {
235 .width = ISP_FREQ_RULE_ANY,
236 .height = ISP_FREQ_RULE_ANY,
237 .fps = ISP_FREQ_RULE_ANY,
238 .isp_freq = ISP_FREQ_400MHZ,
239 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
240 },
241 };
242
243 static const struct atomisp_dfs_config dfs_config_byt = {
244 .lowest_freq = ISP_FREQ_200MHZ,
245 .max_freq_at_vmin = ISP_FREQ_400MHZ,
246 .highest_freq = ISP_FREQ_400MHZ,
247 .dfs_table = dfs_rules_byt,
248 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
249 };
250
251 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
252 {
253 .width = ISP_FREQ_RULE_ANY,
254 .height = ISP_FREQ_RULE_ANY,
255 .fps = ISP_FREQ_RULE_ANY,
256 .isp_freq = ISP_FREQ_320MHZ,
257 .run_mode = ATOMISP_RUN_MODE_VIDEO,
258 },
259 {
260 .width = ISP_FREQ_RULE_ANY,
261 .height = ISP_FREQ_RULE_ANY,
262 .fps = ISP_FREQ_RULE_ANY,
263 .isp_freq = ISP_FREQ_356MHZ,
264 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
265 },
266 {
267 .width = ISP_FREQ_RULE_ANY,
268 .height = ISP_FREQ_RULE_ANY,
269 .fps = ISP_FREQ_RULE_ANY,
270 .isp_freq = ISP_FREQ_320MHZ,
271 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
272 },
273 };
274
275 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
276 {
277 .width = ISP_FREQ_RULE_ANY,
278 .height = ISP_FREQ_RULE_ANY,
279 .fps = ISP_FREQ_RULE_ANY,
280 .isp_freq = ISP_FREQ_356MHZ,
281 .run_mode = ATOMISP_RUN_MODE_VIDEO,
282 },
283 {
284 .width = ISP_FREQ_RULE_ANY,
285 .height = ISP_FREQ_RULE_ANY,
286 .fps = ISP_FREQ_RULE_ANY,
287 .isp_freq = ISP_FREQ_356MHZ,
288 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
289 },
290 {
291 .width = ISP_FREQ_RULE_ANY,
292 .height = ISP_FREQ_RULE_ANY,
293 .fps = ISP_FREQ_RULE_ANY,
294 .isp_freq = ISP_FREQ_320MHZ,
295 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
296 },
297 };
298
299 static const struct atomisp_dfs_config dfs_config_cht = {
300 .lowest_freq = ISP_FREQ_100MHZ,
301 .max_freq_at_vmin = ISP_FREQ_356MHZ,
302 .highest_freq = ISP_FREQ_356MHZ,
303 .dfs_table = dfs_rules_cht,
304 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
305 };
306
307 /* This one should be visible also by atomisp_cmd.c */
308 const struct atomisp_dfs_config dfs_config_cht_soc = {
309 .lowest_freq = ISP_FREQ_100MHZ,
310 .max_freq_at_vmin = ISP_FREQ_356MHZ,
311 .highest_freq = ISP_FREQ_356MHZ,
312 .dfs_table = dfs_rules_cht_soc,
313 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
314 };
315
atomisp_video_init(struct atomisp_video_pipe * video)316 int atomisp_video_init(struct atomisp_video_pipe *video)
317 {
318 int ret;
319
320 video->pad.flags = MEDIA_PAD_FL_SINK;
321 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad);
322 if (ret < 0)
323 return ret;
324
325 /* Initialize the video device. */
326 strscpy(video->vdev.name, "ATOMISP video output", sizeof(video->vdev.name));
327 video->vdev.fops = &atomisp_fops;
328 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
329 video->vdev.lock = &video->isp->mutex;
330 video->vdev.release = video_device_release_empty;
331 video_set_drvdata(&video->vdev, video->isp);
332
333 return 0;
334 }
335
atomisp_video_unregister(struct atomisp_video_pipe * video)336 void atomisp_video_unregister(struct atomisp_video_pipe *video)
337 {
338 if (video_is_registered(&video->vdev)) {
339 media_entity_cleanup(&video->vdev.entity);
340 video_unregister_device(&video->vdev);
341 }
342 }
343
atomisp_save_iunit_reg(struct atomisp_device * isp)344 static int atomisp_save_iunit_reg(struct atomisp_device *isp)
345 {
346 struct pci_dev *pdev = to_pci_dev(isp->dev);
347
348 dev_dbg(isp->dev, "%s\n", __func__);
349
350 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
351 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */
352 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
353 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
354 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
355 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
356 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control);
357
358 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs);
359 /* Ensure read/write combining is enabled. */
360 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control);
361 isp->saved_regs.i_control |=
362 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING |
363 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
364 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
365 &isp->saved_regs.csi_access_viol);
366 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
367 &isp->saved_regs.csi_rcomp_config);
368 /*
369 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE.
370 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path
371 * and sensor sending "continuous clock".
372 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence
373 * is missed, and IUNIT can hang.
374 * For both issues, setting this bit is a workaround.
375 */
376 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
377 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
378 &isp->saved_regs.csi_afe_dly);
379 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
380 &isp->saved_regs.csi_control);
381 if (isp->media_dev.hw_revision >=
382 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
383 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN;
384 /*
385 * On CHT CSI_READY bit should be enabled before stream on
386 */
387 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
388 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)))
389 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY;
390 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
391 &isp->saved_regs.csi_afe_rcomp_config);
392 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
393 &isp->saved_regs.csi_afe_hs_control);
394 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
395 &isp->saved_regs.csi_deadline_control);
396 return 0;
397 }
398
atomisp_restore_iunit_reg(struct atomisp_device * isp)399 static int atomisp_restore_iunit_reg(struct atomisp_device *isp)
400 {
401 struct pci_dev *pdev = to_pci_dev(isp->dev);
402
403 dev_dbg(isp->dev, "%s\n", __func__);
404
405 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
406 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
407 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap);
408 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
409 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data);
410 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
411 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control);
412 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control);
413
414 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs);
415 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
416 isp->saved_regs.csi_access_viol);
417 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
418 isp->saved_regs.csi_rcomp_config);
419 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
420 isp->saved_regs.csi_afe_dly);
421 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
422 isp->saved_regs.csi_control);
423 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
424 isp->saved_regs.csi_afe_rcomp_config);
425 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
426 isp->saved_regs.csi_afe_hs_control);
427 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
428 isp->saved_regs.csi_deadline_control);
429
430 /*
431 * for MRFLD, Software/firmware needs to write a 1 to bit0
432 * of the register at CSI_RECEIVER_SELECTION_REG to enable
433 * SH CSI backend write 0 will enable Arasan CSI backend,
434 * which has bugs(like sighting:4567697 and 4567699) and
435 * will be removed in B0
436 */
437 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
438 return 0;
439 }
440
atomisp_mrfld_pre_power_down(struct atomisp_device * isp)441 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
442 {
443 struct pci_dev *pdev = to_pci_dev(isp->dev);
444 u32 irq;
445 unsigned long flags;
446
447 spin_lock_irqsave(&isp->lock, flags);
448
449 /*
450 * MRFLD HAS requirement: cannot power off i-unit if
451 * ISP has IRQ not serviced.
452 * So, here we need to check if there is any pending
453 * IRQ, if so, waiting for it to be served
454 */
455 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
456 irq &= BIT(INTR_IIR);
457 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
458
459 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
460 if (!(irq & BIT(INTR_IIR)))
461 goto done;
462
463 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF);
464 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq);
465 if (irq != 0) {
466 dev_err(isp->dev,
467 "%s: fail to clear isp interrupt status reg=0x%x\n",
468 __func__, irq);
469 spin_unlock_irqrestore(&isp->lock, flags);
470 return -EAGAIN;
471 } else {
472 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
473 irq &= BIT(INTR_IIR);
474 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
475
476 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
477 if (!(irq & BIT(INTR_IIR))) {
478 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0);
479 goto done;
480 }
481 dev_err(isp->dev,
482 "%s: error in iunit interrupt. status reg=0x%x\n",
483 __func__, irq);
484 spin_unlock_irqrestore(&isp->lock, flags);
485 return -EAGAIN;
486 }
487 done:
488 /*
489 * MRFLD WORKAROUND:
490 * before powering off IUNIT, clear the pending interrupts
491 * and disable the interrupt. driver should avoid writing 0
492 * to IIR. It could block subsequent interrupt messages.
493 * HW sighting:4568410.
494 */
495 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
496 irq &= ~BIT(INTR_IER);
497 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
498
499 atomisp_msi_irq_uninit(isp);
500 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
501 spin_unlock_irqrestore(&isp->lock, flags);
502
503 return 0;
504 }
505
506 /*
507 * WA for DDR DVFS enable/disable
508 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS
509 */
punit_ddr_dvfs_enable(bool enable)510 static void punit_ddr_dvfs_enable(bool enable)
511 {
512 int reg;
513
514 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
515 if (enable) {
516 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1);
517 } else {
518 reg |= MRFLD_BIT1;
519 reg &= ~(MRFLD_BIT0);
520 }
521 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg);
522 }
523
atomisp_mrfld_power(struct atomisp_device * isp,bool enable)524 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable)
525 {
526 struct pci_dev *pdev = to_pci_dev(isp->dev);
527 unsigned long timeout;
528 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON :
529 MRFLD_ISPSSPM0_IUNIT_POWER_OFF;
530
531 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off");
532
533 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */
534 if (IS_CHT && enable && !isp->pm_only) {
535 punit_ddr_dvfs_enable(false);
536 msleep(20);
537 }
538
539 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */
540 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0,
541 val, MRFLD_ISPSSPM0_ISPSSC_MASK);
542
543 /* WA:Enable DVFS */
544 if (IS_CHT && !enable && !isp->pm_only)
545 punit_ddr_dvfs_enable(true);
546
547 /*
548 * There should be no IUNIT access while power-down is
549 * in progress. HW sighting: 4567865.
550 * Wait up to 50 ms for the IUNIT to shut down.
551 * And we do the same for power on.
552 */
553 timeout = jiffies + msecs_to_jiffies(50);
554 do {
555 u32 tmp;
556
557 /* Wait until ISPSSPM0 bit[25:24] shows the right value */
558 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp);
559 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK;
560 if (tmp == val) {
561 trace_ipu_cstate(enable);
562 pdev->current_state = enable ? PCI_D0 : PCI_D3cold;
563 return 0;
564 }
565
566 if (time_after(jiffies, timeout))
567 break;
568
569 /* FIXME: experienced value for delay */
570 usleep_range(100, 150);
571 } while (1);
572
573 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off");
574 return -EBUSY;
575 }
576
atomisp_power_off(struct device * dev)577 int atomisp_power_off(struct device *dev)
578 {
579 struct atomisp_device *isp = dev_get_drvdata(dev);
580 struct pci_dev *pdev = to_pci_dev(dev);
581 int ret;
582 u32 reg;
583
584 if (isp->pm_only) {
585 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, 0);
586 } else {
587 atomisp_css_uninit(isp);
588
589 ret = atomisp_mrfld_pre_power_down(isp);
590 if (ret)
591 return ret;
592 }
593
594 /*
595 * MRFLD IUNIT DPHY is located in an always-power-on island
596 * MRFLD HW design need all CSI ports are disabled before
597 * powering down the IUNIT.
598 */
599 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, ®);
600 reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK;
601 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg);
602
603 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
604 pci_save_state(pdev);
605 return atomisp_mrfld_power(isp, false);
606 }
607
atomisp_power_on(struct device * dev)608 int atomisp_power_on(struct device *dev)
609 {
610 struct atomisp_device *isp = (struct atomisp_device *)
611 dev_get_drvdata(dev);
612 int ret;
613
614 ret = atomisp_mrfld_power(isp, true);
615 if (ret)
616 return ret;
617
618 pci_restore_state(to_pci_dev(dev));
619 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
620
621 if (isp->pm_only)
622 return 0;
623
624 /*restore register values for iUnit and iUnitPHY registers*/
625 if (isp->saved_regs.pcicmdsts)
626 atomisp_restore_iunit_reg(isp);
627
628 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
629
630 return atomisp_css_init(isp);
631 }
632
atomisp_suspend(struct device * dev)633 static int atomisp_suspend(struct device *dev)
634 {
635 struct atomisp_device *isp = (struct atomisp_device *)
636 dev_get_drvdata(dev);
637 unsigned long flags;
638
639 /* FIXME: Suspend is not supported by sensors. Abort if streaming. */
640 spin_lock_irqsave(&isp->lock, flags);
641 if (isp->asd.streaming) {
642 spin_unlock_irqrestore(&isp->lock, flags);
643 dev_err(isp->dev, "atomisp cannot suspend at this time.\n");
644 return -EINVAL;
645 }
646 spin_unlock_irqrestore(&isp->lock, flags);
647
648 pm_runtime_resume(dev);
649
650 isp->asd.recreate_streams_on_resume = isp->asd.stream_prepared;
651 atomisp_destroy_pipes_stream(&isp->asd);
652
653 return atomisp_power_off(dev);
654 }
655
atomisp_resume(struct device * dev)656 static int atomisp_resume(struct device *dev)
657 {
658 struct atomisp_device *isp = dev_get_drvdata(dev);
659 int ret;
660
661 ret = atomisp_power_on(dev);
662 if (ret)
663 return ret;
664
665 if (isp->asd.recreate_streams_on_resume)
666 ret = atomisp_create_pipes_stream(&isp->asd);
667
668 return ret;
669 }
670
atomisp_csi_lane_config(struct atomisp_device * isp)671 int atomisp_csi_lane_config(struct atomisp_device *isp)
672 {
673 struct pci_dev *pdev = to_pci_dev(isp->dev);
674 static const struct {
675 u8 code;
676 u8 lanes[N_MIPI_PORT_ID];
677 } portconfigs[] = {
678 /* Tangier/Merrifield available lane configurations */
679 { 0x00, { 4, 1, 0 } }, /* 00000 */
680 { 0x01, { 3, 1, 0 } }, /* 00001 */
681 { 0x02, { 2, 1, 0 } }, /* 00010 */
682 { 0x03, { 1, 1, 0 } }, /* 00011 */
683 { 0x04, { 2, 1, 2 } }, /* 00100 */
684 { 0x08, { 3, 1, 1 } }, /* 01000 */
685 { 0x09, { 2, 1, 1 } }, /* 01001 */
686 { 0x0a, { 1, 1, 1 } }, /* 01010 */
687
688 /* Anniedale/Moorefield only configurations */
689 { 0x10, { 4, 2, 0 } }, /* 10000 */
690 { 0x11, { 3, 2, 0 } }, /* 10001 */
691 { 0x12, { 2, 2, 0 } }, /* 10010 */
692 { 0x13, { 1, 2, 0 } }, /* 10011 */
693 { 0x14, { 2, 2, 2 } }, /* 10100 */
694 { 0x18, { 3, 2, 1 } }, /* 11000 */
695 { 0x19, { 2, 2, 1 } }, /* 11001 */
696 { 0x1a, { 1, 2, 1 } }, /* 11010 */
697 };
698
699 unsigned int i, j;
700 u32 csi_control;
701 int nportconfigs;
702 u32 port_config_mask;
703 int port3_lanes_shift;
704
705 if (isp->media_dev.hw_revision <
706 ATOMISP_HW_REVISION_ISP2401_LEGACY <<
707 ATOMISP_HW_REVISION_SHIFT) {
708 /* Merrifield */
709 port_config_mask = MRFLD_PORT_CONFIG_MASK;
710 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT;
711 } else {
712 /* Moorefield / Cherryview */
713 port_config_mask = CHV_PORT_CONFIG_MASK;
714 port3_lanes_shift = CHV_PORT3_LANES_SHIFT;
715 }
716
717 if (isp->media_dev.hw_revision <
718 ATOMISP_HW_REVISION_ISP2401 <<
719 ATOMISP_HW_REVISION_SHIFT) {
720 /* Merrifield / Moorefield legacy input system */
721 nportconfigs = MRFLD_PORT_CONFIG_NUM;
722 } else {
723 /* Moorefield / Cherryview new input system */
724 nportconfigs = ARRAY_SIZE(portconfigs);
725 }
726
727 for (i = 0; i < nportconfigs; i++) {
728 for (j = 0; j < N_MIPI_PORT_ID; j++)
729 if (isp->sensor_lanes[j] &&
730 isp->sensor_lanes[j] != portconfigs[i].lanes[j])
731 break;
732
733 if (j == N_MIPI_PORT_ID)
734 break; /* Found matching setting */
735 }
736
737 if (i >= nportconfigs) {
738 dev_err(isp->dev,
739 "%s: could not find the CSI port setting for %d-%d-%d\n",
740 __func__,
741 isp->sensor_lanes[0], isp->sensor_lanes[1], isp->sensor_lanes[2]);
742 return -EINVAL;
743 }
744
745 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
746 csi_control &= ~port_config_mask;
747 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
748 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
749 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
750 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
751 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
752 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
753 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
754
755 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
756
757 dev_dbg(isp->dev,
758 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
759 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1],
760 portconfigs[i].lanes[2], csi_control);
761
762 return 0;
763 }
764
atomisp_subdev_probe(struct atomisp_device * isp)765 static int atomisp_subdev_probe(struct atomisp_device *isp)
766 {
767 const struct intel_v4l2_subdev_table *subdevs;
768 int ret, mipi_port;
769
770 ret = atomisp_csi2_bridge_parse_firmware(isp);
771 if (ret)
772 return ret;
773
774 /*
775 * TODO: this is left here for now to allow testing atomisp-sensor
776 * drivers which are still using the atomisp_gmin_platform infra before
777 * converting them to standard v4l2 sensor drivers using runtime-pm +
778 * ACPI for pm and v4l2_async_register_subdev_sensor() registration.
779 */
780 for (subdevs = atomisp_platform_get_subdevs(); subdevs->subdev; subdevs++) {
781 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdevs->subdev);
782 if (ret)
783 continue;
784
785 if (subdevs->port >= ATOMISP_CAMERA_NR_PORTS) {
786 dev_err(isp->dev, "port %d not supported\n", subdevs->port);
787 continue;
788 }
789
790 if (isp->sensor_subdevs[subdevs->port]) {
791 dev_err(isp->dev, "port %d already has a sensor attached\n",
792 subdevs->port);
793 continue;
794 }
795
796 mipi_port = atomisp_port_to_mipi_port(isp, subdevs->port);
797 isp->sensor_lanes[mipi_port] = subdevs->lanes;
798 isp->sensor_subdevs[subdevs->port] = subdevs->subdev;
799 }
800
801 return atomisp_csi_lane_config(isp);
802 }
803
atomisp_unregister_entities(struct atomisp_device * isp)804 static void atomisp_unregister_entities(struct atomisp_device *isp)
805 {
806 unsigned int i;
807 struct v4l2_subdev *sd, *next;
808
809 atomisp_subdev_unregister_entities(&isp->asd);
810 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
811 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
812
813 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list)
814 v4l2_device_unregister_subdev(sd);
815
816 v4l2_device_unregister(&isp->v4l2_dev);
817 media_device_unregister(&isp->media_dev);
818 media_device_cleanup(&isp->media_dev);
819
820 for (i = 0; i < isp->input_cnt; i++)
821 __v4l2_subdev_state_free(isp->inputs[i].try_sd_state);
822 }
823
atomisp_register_entities(struct atomisp_device * isp)824 static int atomisp_register_entities(struct atomisp_device *isp)
825 {
826 int ret = 0;
827 unsigned int i;
828
829 isp->media_dev.dev = isp->dev;
830
831 strscpy(isp->media_dev.model, "Intel Atom ISP",
832 sizeof(isp->media_dev.model));
833
834 media_device_init(&isp->media_dev);
835 isp->v4l2_dev.mdev = &isp->media_dev;
836 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
837 if (ret < 0) {
838 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
839 __func__, ret);
840 goto v4l2_device_failed;
841 }
842
843 ret = atomisp_subdev_probe(isp);
844 if (ret < 0)
845 goto csi_and_subdev_probe_failed;
846
847 /* Register internal entities */
848 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
849 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i],
850 &isp->v4l2_dev);
851 if (ret == 0)
852 continue;
853
854 /* error case */
855 dev_err(isp->dev, "failed to register the CSI port: %d\n", i);
856 /* deregister all registered CSI ports */
857 while (i--)
858 atomisp_mipi_csi2_unregister_entities(
859 &isp->csi2_port[i]);
860
861 goto csi_and_subdev_probe_failed;
862 }
863
864 ret = atomisp_subdev_register_subdev(&isp->asd, &isp->v4l2_dev);
865 if (ret < 0) {
866 dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n");
867 goto subdev_register_failed;
868 }
869
870 return 0;
871
872 subdev_register_failed:
873 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
874 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
875 csi_and_subdev_probe_failed:
876 v4l2_device_unregister(&isp->v4l2_dev);
877 v4l2_device_failed:
878 media_device_unregister(&isp->media_dev);
879 media_device_cleanup(&isp->media_dev);
880 return ret;
881 }
882
atomisp_init_sensor(struct atomisp_input_subdev * input)883 static void atomisp_init_sensor(struct atomisp_input_subdev *input)
884 {
885 static struct lock_class_key try_sd_state_key;
886 struct v4l2_subdev_mbus_code_enum mbus_code_enum = { };
887 struct v4l2_subdev_frame_size_enum fse = { };
888 struct v4l2_subdev_selection sel = { };
889 struct v4l2_subdev_state *try_sd_state, *act_sd_state;
890 int i, err;
891
892 /*
893 * FIXME: Drivers are not supposed to use __v4l2_subdev_state_alloc()
894 * but atomisp needs this for try_fmt on its /dev/video# node since
895 * it emulates a normal v4l2 device there, passing through try_fmt /
896 * set_fmt to the sensor.
897 */
898 try_sd_state = __v4l2_subdev_state_alloc(input->camera,
899 "atomisp:try_sd_state->lock", &try_sd_state_key);
900 if (IS_ERR(try_sd_state))
901 return;
902
903 input->try_sd_state = try_sd_state;
904
905 act_sd_state = v4l2_subdev_lock_and_get_active_state(input->camera);
906
907 mbus_code_enum.which = V4L2_SUBDEV_FORMAT_ACTIVE;
908 err = v4l2_subdev_call(input->camera, pad, enum_mbus_code,
909 act_sd_state, &mbus_code_enum);
910 if (!err)
911 input->code = mbus_code_enum.code;
912
913 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
914 sel.target = V4L2_SEL_TGT_NATIVE_SIZE;
915 err = v4l2_subdev_call(input->camera, pad, get_selection,
916 act_sd_state, &sel);
917 if (err)
918 goto unlock_act_sd_state;
919
920 input->native_rect = sel.r;
921
922 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
923 sel.target = V4L2_SEL_TGT_CROP_DEFAULT;
924 err = v4l2_subdev_call(input->camera, pad, get_selection,
925 act_sd_state, &sel);
926 if (err)
927 goto unlock_act_sd_state;
928
929 input->active_rect = sel.r;
930
931 /*
932 * Check for a framesize with half active_rect width and height,
933 * if found assume the sensor supports binning.
934 * Do this before changing the crop-rect since that may influence
935 * enum_frame_size results.
936 */
937 for (i = 0; ; i++) {
938 fse.index = i;
939 fse.code = input->code;
940 fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
941
942 err = v4l2_subdev_call(input->camera, pad, enum_frame_size,
943 act_sd_state, &fse);
944 if (err)
945 break;
946
947 if (fse.min_width <= (input->active_rect.width / 2) &&
948 fse.min_height <= (input->active_rect.height / 2)) {
949 input->binning_support = true;
950 break;
951 }
952 }
953
954 /*
955 * The ISP also wants the non-active pixels at the border of the sensor
956 * for padding, set the crop rect to cover the entire sensor instead
957 * of only the default active area.
958 *
959 * Do this for both try and active formats since the crop rect in
960 * try_sd_state may influence (clamp size) in calls with which == try.
961 */
962 sel.which = V4L2_SUBDEV_FORMAT_TRY;
963 sel.target = V4L2_SEL_TGT_CROP;
964 sel.r = input->native_rect;
965 v4l2_subdev_lock_state(input->try_sd_state);
966 err = v4l2_subdev_call(input->camera, pad, set_selection,
967 input->try_sd_state, &sel);
968 v4l2_subdev_unlock_state(input->try_sd_state);
969 if (err)
970 goto unlock_act_sd_state;
971
972 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
973 sel.target = V4L2_SEL_TGT_CROP;
974 sel.r = input->native_rect;
975 err = v4l2_subdev_call(input->camera, pad, set_selection,
976 act_sd_state, &sel);
977 if (err)
978 goto unlock_act_sd_state;
979
980 dev_info(input->camera->dev, "Supports crop native %dx%d active %dx%d binning %d\n",
981 input->native_rect.width, input->native_rect.height,
982 input->active_rect.width, input->active_rect.height,
983 input->binning_support);
984
985 input->crop_support = true;
986
987 unlock_act_sd_state:
988 if (act_sd_state)
989 v4l2_subdev_unlock_state(act_sd_state);
990 }
991
atomisp_register_device_nodes(struct atomisp_device * isp)992 int atomisp_register_device_nodes(struct atomisp_device *isp)
993 {
994 struct atomisp_input_subdev *input;
995 int i, err;
996
997 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
998 err = media_create_pad_link(&isp->csi2_port[i].subdev.entity,
999 CSI2_PAD_SOURCE, &isp->asd.subdev.entity,
1000 ATOMISP_SUBDEV_PAD_SINK, 0);
1001 if (err)
1002 return err;
1003
1004 if (!isp->sensor_subdevs[i])
1005 continue;
1006
1007 input = &isp->inputs[isp->input_cnt];
1008
1009 input->port = i;
1010 input->camera = isp->sensor_subdevs[i];
1011 input->csi_port = &isp->csi2_port[i].subdev;
1012
1013 atomisp_init_sensor(input);
1014
1015 err = media_create_pad_link(&input->camera->entity, 0,
1016 &isp->csi2_port[i].subdev.entity,
1017 CSI2_PAD_SINK,
1018 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1019 if (err)
1020 return err;
1021
1022 isp->input_cnt++;
1023 }
1024
1025 if (!isp->input_cnt)
1026 dev_warn(isp->dev, "no camera attached or fail to detect\n");
1027 else
1028 dev_info(isp->dev, "detected %d camera sensors\n", isp->input_cnt);
1029
1030 mutex_lock(&isp->media_dev.graph_mutex);
1031 atomisp_setup_input_links(isp);
1032 mutex_unlock(&isp->media_dev.graph_mutex);
1033
1034 isp->asd.video_out.vdev.v4l2_dev = &isp->v4l2_dev;
1035 isp->asd.video_out.vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1036 err = video_register_device(&isp->asd.video_out.vdev, VFL_TYPE_VIDEO, -1);
1037 if (err)
1038 return err;
1039
1040 err = media_create_pad_link(&isp->asd.subdev.entity, ATOMISP_SUBDEV_PAD_SOURCE,
1041 &isp->asd.video_out.vdev.entity, 0,
1042 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1043 if (err)
1044 return err;
1045
1046 err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1047 if (err)
1048 return err;
1049
1050 return media_device_register(&isp->media_dev);
1051 }
1052
atomisp_initialize_modules(struct atomisp_device * isp)1053 static int atomisp_initialize_modules(struct atomisp_device *isp)
1054 {
1055 int ret;
1056
1057 ret = atomisp_mipi_csi2_init(isp);
1058 if (ret < 0) {
1059 dev_err(isp->dev, "mipi csi2 initialization failed\n");
1060 goto error_mipi_csi2;
1061 }
1062
1063 ret = atomisp_subdev_init(isp);
1064 if (ret < 0) {
1065 dev_err(isp->dev, "ISP subdev initialization failed\n");
1066 goto error_isp_subdev;
1067 }
1068
1069 return 0;
1070
1071 error_isp_subdev:
1072 error_mipi_csi2:
1073 atomisp_mipi_csi2_cleanup(isp);
1074 return ret;
1075 }
1076
atomisp_uninitialize_modules(struct atomisp_device * isp)1077 static void atomisp_uninitialize_modules(struct atomisp_device *isp)
1078 {
1079 atomisp_mipi_csi2_cleanup(isp);
1080 }
1081
1082 const struct firmware *
atomisp_load_firmware(struct atomisp_device * isp)1083 atomisp_load_firmware(struct atomisp_device *isp)
1084 {
1085 const struct firmware *fw;
1086 int rc;
1087 char *fw_path = NULL;
1088
1089 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT) ==
1090 ATOMISP_HW_REVISION_ISP2401)
1091 fw_path = "intel/ipu/shisp_2401a0_v21.bin";
1092
1093 if (isp->media_dev.hw_revision ==
1094 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT) |
1095 ATOMISP_HW_STEPPING_A0))
1096 fw_path = "intel/ipu/shisp_2401a0_legacy_v21.bin";
1097
1098 if (isp->media_dev.hw_revision ==
1099 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT) |
1100 ATOMISP_HW_STEPPING_B0))
1101 fw_path = "intel/ipu/shisp_2400b0_v21.bin";
1102
1103 if (!fw_path) {
1104 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n",
1105 isp->media_dev.hw_revision);
1106 return NULL;
1107 }
1108
1109 rc = request_firmware(&fw, fw_path, isp->dev);
1110 /* Fallback to old fw_path without "intel/ipu/" prefix */
1111 if (rc)
1112 rc = request_firmware(&fw, kbasename(fw_path), isp->dev);
1113 if (rc) {
1114 dev_err(isp->dev,
1115 "atomisp: Error %d while requesting firmware %s\n",
1116 rc, fw_path);
1117 return NULL;
1118 }
1119
1120 return fw;
1121 }
1122
atomisp_pm_init(struct atomisp_device * isp)1123 static void atomisp_pm_init(struct atomisp_device *isp)
1124 {
1125 /*
1126 * The atomisp does not use standard PCI power-management through the
1127 * PCI config space. Instead this driver directly tells the P-Unit to
1128 * disable the ISP over the IOSF. The standard PCI subsystem pm_ops will
1129 * try to access the config space before (resume) / after (suspend) this
1130 * driver has turned the ISP on / off, resulting in the following errors:
1131 *
1132 * "Unable to change power state from D0 to D3hot, device inaccessible"
1133 * "Unable to change power state from D3cold to D0, device inaccessible"
1134 *
1135 * To avoid these errors override the pm_domain so that all the PCI
1136 * subsys suspend / resume handling is skipped.
1137 */
1138 isp->pm_domain.ops.runtime_suspend = atomisp_power_off;
1139 isp->pm_domain.ops.runtime_resume = atomisp_power_on;
1140 isp->pm_domain.ops.suspend = atomisp_suspend;
1141 isp->pm_domain.ops.resume = atomisp_resume;
1142
1143 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
1144 dev_pm_domain_set(isp->dev, &isp->pm_domain);
1145
1146 pm_runtime_allow(isp->dev);
1147 pm_runtime_put_sync_suspend(isp->dev);
1148 }
1149
atomisp_pm_uninit(struct atomisp_device * isp)1150 static void atomisp_pm_uninit(struct atomisp_device *isp)
1151 {
1152 pm_runtime_get_sync(isp->dev);
1153 pm_runtime_forbid(isp->dev);
1154 dev_pm_domain_set(isp->dev, NULL);
1155 cpu_latency_qos_remove_request(&isp->pm_qos);
1156 }
1157
1158 #define ATOM_ISP_PCI_BAR 0
1159
atomisp_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1160 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1161 {
1162 struct atomisp_device *isp;
1163 unsigned int start;
1164 u32 val;
1165 int err;
1166
1167 /* Pointer to struct device. */
1168 atomisp_dev = &pdev->dev;
1169
1170 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR);
1171 dev_dbg(&pdev->dev, "start: 0x%x\n", start);
1172
1173 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
1174 if (!isp)
1175 return -ENOMEM;
1176
1177 isp->dev = &pdev->dev;
1178 isp->saved_regs.ispmmadr = start;
1179 isp->asd.isp = isp;
1180
1181 mutex_init(&isp->mutex);
1182 spin_lock_init(&isp->lock);
1183
1184 /* This is not a true PCI device on SoC, so the delay is not needed. */
1185 pdev->d3hot_delay = 0;
1186
1187 pci_set_drvdata(pdev, isp);
1188
1189 switch (id->device) {
1190 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1191 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1192 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1193 isp->media_dev.hw_revision =
1194 (ATOMISP_HW_REVISION_ISP2400
1195 << ATOMISP_HW_REVISION_SHIFT) |
1196 ATOMISP_HW_STEPPING_B0;
1197
1198 switch (id->device) {
1199 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1200 isp->dfs = &dfs_config_merr_1179;
1201 break;
1202 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1203 isp->dfs = &dfs_config_merr_117a;
1204
1205 break;
1206 default:
1207 isp->dfs = &dfs_config_merr;
1208 break;
1209 }
1210 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1211 break;
1212 case ATOMISP_PCI_DEVICE_SOC_BYT:
1213 isp->media_dev.hw_revision =
1214 (ATOMISP_HW_REVISION_ISP2400
1215 << ATOMISP_HW_REVISION_SHIFT) |
1216 ATOMISP_HW_STEPPING_B0;
1217
1218 /*
1219 * Note: some Intel-based tablets with Android use a different
1220 * DFS table. Based on the comments at the Yocto Aero meta
1221 * version of this driver (at the ssid.h header), they're
1222 * identified via a "spid" var:
1223 *
1224 * androidboot.spid=vend:cust:manu:plat:prod:hard
1225 *
1226 * As we don't have this upstream, nor we know enough details
1227 * to use a DMI or PCI match table, the old code was just
1228 * removed, but let's keep a note here as a reminder that,
1229 * for certain devices, we may need to limit the max DFS
1230 * frequency to be below certain values, adjusting the
1231 * resolution accordingly.
1232 */
1233 isp->dfs = &dfs_config_byt;
1234
1235 /*
1236 * HPLL frequency is known to be device-specific, but we don't
1237 * have specs yet for exactly how it varies. Default to
1238 * BYT-CR but let provisioning set it via EFI variable
1239 */
1240 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ);
1241
1242 /*
1243 * for BYT/CHT we are put isp into D3cold to avoid pci registers access
1244 * in power off. Set d3cold_delay to 0 since default 100ms is not
1245 * necessary.
1246 */
1247 pdev->d3cold_delay = 0;
1248 break;
1249 case ATOMISP_PCI_DEVICE_SOC_ANN:
1250 isp->media_dev.hw_revision = (ATOMISP_HW_REVISION_ISP2401
1251 << ATOMISP_HW_REVISION_SHIFT);
1252 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1253 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1254 isp->dfs = &dfs_config_merr;
1255 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1256 break;
1257 case ATOMISP_PCI_DEVICE_SOC_CHT:
1258 isp->media_dev.hw_revision = (ATOMISP_HW_REVISION_ISP2401
1259 << ATOMISP_HW_REVISION_SHIFT);
1260 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1261 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1262
1263 isp->dfs = &dfs_config_cht;
1264 pdev->d3cold_delay = 0;
1265
1266 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val);
1267 switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1268 case 0x00:
1269 isp->hpll_freq = HPLL_FREQ_800MHZ;
1270 break;
1271 case 0x01:
1272 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1273 break;
1274 case 0x02:
1275 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1276 break;
1277 default:
1278 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1279 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n");
1280 }
1281 break;
1282 default:
1283 dev_err(&pdev->dev, "un-supported IUNIT device\n");
1284 return -ENODEV;
1285 }
1286
1287 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
1288 dev_err(&pdev->dev, "revision %d is not supported\n", pdev->revision);
1289 return -ENODEV;
1290 }
1291
1292 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq);
1293
1294 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1295
1296 /* Load isp firmware from user space */
1297 isp->firmware = atomisp_load_firmware(isp);
1298 if (!isp->firmware) {
1299 /* No firmware continue in pm-only mode for S0i3 support */
1300 dev_info(&pdev->dev, "Continuing in power-management only mode\n");
1301 isp->pm_only = true;
1302 atomisp_pm_init(isp);
1303 return 0;
1304 }
1305
1306 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data);
1307 if (err) {
1308 dev_dbg(&pdev->dev, "Firmware version check failed\n");
1309 goto error_release_firmware;
1310 }
1311
1312 err = pcim_enable_device(pdev);
1313 if (err) {
1314 dev_err(&pdev->dev, "Failed to enable ISP PCI device (%d)\n", err);
1315 goto error_release_firmware;
1316 }
1317
1318 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev));
1319 if (err) {
1320 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err);
1321 goto error_release_firmware;
1322 }
1323
1324 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR];
1325
1326 pci_set_master(pdev);
1327
1328 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1329 if (err < 0) {
1330 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err);
1331 goto error_release_firmware;
1332 }
1333
1334 atomisp_msi_irq_init(isp);
1335
1336 /*
1337 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of
1338 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI
1339 * backend write 0 will enable Arasan CSI backend, which has
1340 * bugs(like sighting:4567697 and 4567699) and will be removed
1341 * in B0
1342 */
1343 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
1344
1345 switch (id->device) {
1346 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1347 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1348 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1349 /*
1350 * Workaround for imbalance data eye issue which is observed
1351 * on TNG B0.
1352 */
1353 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &val);
1354 val &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1355 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1356 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT));
1357 val |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1358 (MRFLD_PCI_CSI2_HSRXCLKTRIM << MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1359 (MRFLD_PCI_CSI3_HSRXCLKTRIM << MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1360 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, val);
1361 break;
1362 default:
1363 break;
1364 }
1365
1366 err = atomisp_initialize_modules(isp);
1367 if (err < 0) {
1368 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err);
1369 goto error_irq_uninit;
1370 }
1371
1372 err = atomisp_register_entities(isp);
1373 if (err < 0) {
1374 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err);
1375 goto error_uninitialize_modules;
1376 }
1377
1378 INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work);
1379
1380 /* save the iunit context only once after all the values are init'ed. */
1381 atomisp_save_iunit_reg(isp);
1382
1383 /* Init ISP memory management */
1384 hmm_init();
1385
1386 err = devm_request_threaded_irq(&pdev->dev, pdev->irq,
1387 atomisp_isr, atomisp_isr_thread,
1388 IRQF_SHARED, "isp_irq", isp);
1389 if (err) {
1390 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err);
1391 goto error_unregister_entities;
1392 }
1393
1394 /* Load firmware into ISP memory */
1395 err = atomisp_css_load_firmware(isp);
1396 if (err) {
1397 dev_err(&pdev->dev, "Failed to init css.\n");
1398 goto error_free_irq;
1399 }
1400 /* Clear FW image from memory */
1401 release_firmware(isp->firmware);
1402 isp->firmware = NULL;
1403 isp->css_env.isp_css_fw.data = NULL;
1404
1405 atomisp_pm_init(isp);
1406
1407 err = v4l2_async_nf_register(&isp->notifier);
1408 if (err) {
1409 dev_err(isp->dev, "failed to register async notifier : %d\n", err);
1410 goto error_unload_firmware;
1411 }
1412
1413 return 0;
1414
1415 error_unload_firmware:
1416 atomisp_pm_uninit(isp);
1417 ia_css_unload_firmware();
1418 error_free_irq:
1419 devm_free_irq(&pdev->dev, pdev->irq, isp);
1420 error_unregister_entities:
1421 hmm_cleanup();
1422 atomisp_unregister_entities(isp);
1423 error_uninitialize_modules:
1424 atomisp_uninitialize_modules(isp);
1425 error_irq_uninit:
1426 atomisp_msi_irq_uninit(isp);
1427 pci_free_irq_vectors(pdev);
1428 error_release_firmware:
1429 release_firmware(isp->firmware);
1430 return err;
1431 }
1432
atomisp_pci_remove(struct pci_dev * pdev)1433 static void atomisp_pci_remove(struct pci_dev *pdev)
1434 {
1435 struct atomisp_device *isp = pci_get_drvdata(pdev);
1436
1437 atomisp_pm_uninit(isp);
1438
1439 if (isp->pm_only)
1440 return;
1441
1442 /* Undo ia_css_init() from atomisp_power_on() */
1443 atomisp_css_uninit(isp);
1444 ia_css_unload_firmware();
1445 devm_free_irq(&pdev->dev, pdev->irq, isp);
1446 hmm_cleanup();
1447
1448 atomisp_unregister_entities(isp);
1449 atomisp_uninitialize_modules(isp);
1450 atomisp_msi_irq_uninit(isp);
1451 pci_free_irq_vectors(pdev);
1452 }
1453
1454 static const struct pci_device_id atomisp_pci_tbl[] = {
1455 /* Merrifield */
1456 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)},
1457 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)},
1458 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)},
1459 /* Baytrail */
1460 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)},
1461 /* Anniedale (Merrifield+ / Moorefield) */
1462 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)},
1463 /* Cherrytrail */
1464 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)},
1465 {0,}
1466 };
1467 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl);
1468
1469 static struct pci_driver atomisp_pci_driver = {
1470 .driver = {
1471 .dev_groups = dbg_attr_groups,
1472 },
1473 .name = "atomisp-isp2",
1474 .id_table = atomisp_pci_tbl,
1475 .probe = atomisp_pci_probe,
1476 .remove = atomisp_pci_remove,
1477 };
1478
1479 module_pci_driver(atomisp_pci_driver);
1480
1481 MODULE_AUTHOR("Wen Wang <[email protected]>");
1482 MODULE_AUTHOR("Xiaolin Zhang <[email protected]>");
1483 MODULE_LICENSE("GPL");
1484 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
1485 MODULE_IMPORT_NS("INTEL_IPU_BRIDGE");
1486