1 /*===================== begin_copyright_notice ================================== 2 3 Copyright (c) 2017-2020, Intel Corporation 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included 13 in all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_vdbox_g12_X.h 26 //! \brief Defines structures used for constructing VDBox commands on Gen12-based platforms 27 //! 28 29 #ifndef _MHW_VDBOX_G12_H_ 30 #define _MHW_VDBOX_G12_H_ 31 32 #include "mos_os.h" 33 #include "mhw_vdbox.h" 34 35 #define MmcEnable(x) ((x) == MOS_MEMCOMP_RC || (x) == MOS_MEMCOMP_MC) 36 #define MmcIsRc(x) ((x) == MOS_MEMCOMP_RC) 37 38 // Meta/MV, DeBlock, SAO, VDEnc, HSAO 39 const bool RowStoreCacheEnableHEVC[16][5] = 40 { 41 { 1, 1, 1, 0, 1 }, { 1, 1, 1, 1, 1 }, { 1, 1, 0, 0, 0 }, { 1, 1, 0, 1, 0 }, 42 { 1, 1, 1, 1, 1 }, { 1, 1, 0, 0, 1 }, { 1, 1, 1, 0, 0 }, { 1, 0, 1, 0, 1 }, 43 { 1, 1, 1, 0, 0 }, { 1, 0, 1, 0, 1 }, { 1, 1, 1, 1, 1 }, { 1, 1, 0, 1, 1 }, 44 { 1, 1, 1, 1, 1 }, { 1, 0, 1, 1, 1 }, { 1, 1, 1, 1, 1 }, { 1, 0, 1, 1, 1 } 45 }; 46 47 const uint32_t RowStoreCacheAddrHEVC[16][5] = 48 { 49 { 0, 256, 1280, 0, 2048 }, { 0, 256, 1280, 1824, 1792 }, { 0, 512, 0, 0, 0 }, { 0, 256, 0, 2304, 0 }, 50 { 0, 256, 1024, 0, 1792 }, { 0, 512, 0, 0, 2048 }, { 0, 256, 1792, 0, 0 }, { 0, 0, 512, 0, 2048 }, 51 { 0, 256, 1792, 0, 0 }, { 0, 0, 256, 0, 1792 }, { 0, 256, 1024, 1568, 1536 }, { 0, 512, 0, 2112, 2048 }, 52 { 0, 256, 1792, 2336, 2304 }, { 0, 0, 512, 1600, 1536 }, { 0, 128, 1664, 2336, 2304 }, { 0, 0, 256, 1600, 1536 } 53 }; 54 55 // HVD, Meta/MV, DeBlock, VDEnc 56 const bool RowStoreCacheEnableVP9[13][4] = 57 { 58 { 1, 1, 1, 1 }, { 0, 0, 1, 1 }, { 1, 0, 1, 1 }, { 1, 1, 0, 1 }, 59 { 1, 1, 1, 1 }, { 0, 0, 1, 1 }, { 0, 0, 1, 0 }, { 1, 1, 0, 1 }, 60 { 1, 1, 1, 1 }, { 1, 1, 0, 1 }, { 1, 1, 1, 1 }, { 1, 1, 0, 1 }, 61 { 1, 1, 0, 1 } 62 }; 63 64 const uint32_t RowStoreCacheAddrVP9[13][4] = 65 { 66 { 0, 64, 384, 1536, }, { 0, 0, 0, 2304, }, { 0, 0, 64, 2368, }, { 0, 128, 0, 768, }, 67 { 0, 64, 384, 1536, }, { 0, 0, 0, 2304, }, { 0, 0, 0, 0, }, { 0, 128, 0, 768, }, 68 { 0, 64, 384, 2112, }, { 0, 128, 0, 768, }, { 0, 32, 192, 1920, }, { 0, 128, 0, 768, }, 69 { 0, 128, 0, 768, } 70 }; 71 72 struct MHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G12 : public MHW_VDBOX_PIPE_MODE_SELECT_PARAMS 73 { 74 // GEN12 specific 75 bool bTileBasedReplayMode = false; 76 bool bWirelessEncodeEnabled = false; 77 uint8_t ucWirelessSessionId = 0; 78 bool bRGBEncodingMode = false; 79 uint8_t ucPhaseIndicator = 0; 80 bool bBRCEnabled = false; 81 bool bHEVCSeparateTileProgramming = false; 82 bool bStreamingBufferEnabled = false; 83 bool bIsRandomAccess = false; 84 bool bLookaheadPass = false; 85 bool bAdaptiveRounding = false; 86 uint8_t tuMinus1 = 3; 87 uint8_t ucQuantizationPrecision = 0; 88 uint8_t tuSettingsRevision = 0; 89 bool frameReconDisable = false; 90 }; 91 using PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G12 = MHW_VDBOX_PIPE_MODE_SELECT_PARAMS_G12 *; 92 93 struct MHW_VDBOX_AVC_IMG_PARAMS_G12 : public MHW_VDBOX_AVC_IMG_PARAMS 94 { 95 bool bVDEncUltraModeEnabled = false; 96 bool oneOnOneMapping = false; 97 bool bStreamInMbQpEnabled = false; 98 uint8_t tuSettingsRevision = 0; 99 }; 100 using PMHW_VDBOX_AVC_IMG_PARAMS_G12 = MHW_VDBOX_AVC_IMG_PARAMS_G12 *; 101 102 struct MHW_VDBOX_STATE_CMDSIZE_PARAMS_G12 : public MHW_VDBOX_STATE_CMDSIZE_PARAMS 103 { 104 bool bScalableMode = 0; 105 }; 106 using PMHW_VDBOX_STATE_CMDSIZE_PARAMS_G12 = MHW_VDBOX_STATE_CMDSIZE_PARAMS_G12 *; 107 108 struct MHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 109 { 110 uint32_t NumOfTilesInFrame; 111 uint32_t NumOfTileColumnsInFrame; 112 uint32_t TileStartLCUX; 113 uint32_t TileStartLCUY; 114 uint16_t TileHeightInMinCbMinus1; 115 uint16_t TileWidthInMinCbMinus1; 116 bool IsLastTileofColumn; 117 bool IsLastTileofRow; 118 uint32_t TileRowStoreSelect; 119 uint32_t TileColumnStoreSelect; 120 uint32_t Mode; 121 bool IsFirstPass; 122 bool IsLastPass; 123 bool bTileReplayEnable; 124 125 // Offsets for scalability 126 uint32_t NumberOfActiveBePipes; 127 uint32_t BitstreamByteOffset; 128 uint32_t PakTileStatisticsOffset; 129 uint32_t CuLevelStreamoutOffset; 130 uint32_t SliceSizeStreamoutOffset; 131 uint32_t CuRecordOffset; 132 uint32_t SseRowstoreOffset; 133 uint32_t SaoRowstoreOffset; 134 uint32_t TileSizeStreamoutOffset; 135 uint32_t Vp9ProbabilityCounterStreamoutOffset; 136 uint32_t TileStreaminOffset; 137 uint32_t CumulativeCUTileOffset; 138 uint32_t TileLCUStreamOutOffset; 139 140 PMOS_RESOURCE presHcpSyncBuffer; // this buffer is not used for either HEVC/VP9 encoder and decoder. 141 142 //Decode specific sparameters 143 uint8_t ucNumDecodePipes; 144 uint8_t ucPipeIdx; 145 }; 146 using PMHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 = MHW_VDBOX_HCP_TILE_CODING_PARAMS_G12 *; 147 148 #endif 149