1 /*
2 * Copyright (C) 2018 The Android Open Source Project
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include <test-runner-arch.h>
26
27 #include <stdbool.h>
28 #include <stddef.h>
29 #include <stdint.h>
30
31 /* QEMU FW_CFG, dtb and kernel load addresses */
32 #define FW_CFG_BASE 0x09020000
33 #define DTB_ADDR 0x40000000
34 #define LOAD_ADDR 0x40080000
35 #define INITRD_ADDR 0x48000000
36
37 #define FW_CFG_KERNEL_SIZE 0x08
38 #define FW_CFG_KERNEL_DATA 0x11
39
40 #define FW_CFG_INITRD_SIZE 0x0b
41 #define FW_CFG_INITRD_DATA 0x12
42
43 #define FW_CFG_DMA_CTL_READ 0x02
44 #define FW_CFG_DMA_CTL_SELECT 0x08
45
46 /* Reverse byte order for 16, 32 or 64 bit registers. Compiles to rev* opcode */
rev(uint64_t val,unsigned bits)47 static uint64_t rev(uint64_t val, unsigned bits) {
48 uint64_t mask = ~0ULL;
49 for (unsigned shift = bits >> 1; shift >= 8; shift >>= 1) {
50 mask ^= mask << shift;
51 val = ((val >> shift) & mask) | ((val & mask) << shift);
52 }
53 return val;
54 }
55
rev16(uint16_t val)56 static uint16_t rev16(uint16_t val) {
57 return rev(val, 16);
58 }
59
rev32(uint32_t val)60 static uint32_t rev32(uint32_t val) {
61 return rev(val, 32);
62 }
63
rev64(uint64_t val)64 static uint64_t rev64(uint64_t val) {
65 return rev(val, 64);
66 }
67
load_image(uint64_t addr,uint16_t cfg_data,uint16_t cfg_size)68 static bool load_image(uint64_t addr, uint16_t cfg_data, uint16_t cfg_size) {
69 volatile uint32_t* cfg_data32 = (void*)FW_CFG_BASE;
70 volatile uint16_t* cfg_ctl = (void*)(FW_CFG_BASE + 0x8);
71 volatile uint64_t* cfg_dma = (void*)(FW_CFG_BASE + 0x10);
72
73 volatile struct {
74 uint32_t control;
75 uint32_t length;
76 uint64_t address;
77 } dma;
78
79 /*
80 * Setup dma description to select FW_CFG_KERNEL_DATA item and read from it.
81 * The FW_CFG interface is big-endian and the cpu is little-endian so we
82 * reverse the byte order.
83 *
84 * Interface is defined in external/qemu/hw/nvram/fw_cfg.c.
85 */
86 dma.control =
87 rev32(FW_CFG_DMA_CTL_READ | FW_CFG_DMA_CTL_SELECT | cfg_data << 16);
88
89 /*
90 * Select FW_CFG_KERNEL_SIZE item and copy it to the dma lenght descriptor.
91 * Both are big-endian so byte order reversal is needed.
92 */
93 *cfg_ctl = rev16(cfg_size);
94 dma.length = rev32(*cfg_data32);
95 if (!dma.length) {
96 /* Return if no image was provided */
97 return false;
98 }
99
100 /*
101 * Set the target address for the DMA. Reverse the byte order of the address
102 * since the dma descriptor expects big-endian byte order.
103 */
104 dma.address = rev64(addr);
105
106 /* Start the dma */
107 *cfg_dma = rev64((uint64_t)&dma);
108 if (dma.control != 0) {
109 /* Return if dma was not successful */
110 return false;
111 }
112 return true;
113 }
114
boot_next(void)115 void boot_next(void) {
116 typedef void (*entry_func_t)(uint64_t dtb_paddr);
117
118 if (!load_image(LOAD_ADDR, FW_CFG_KERNEL_DATA, FW_CFG_KERNEL_SIZE)) {
119 return;
120 }
121 load_image(INITRD_ADDR, FW_CFG_INITRD_DATA, FW_CFG_INITRD_SIZE);
122
123 /* Jump to the image we just loaded with the dtb address in x0 */
124 ((entry_func_t)LOAD_ADDR)(DTB_ADDR);
125 }
126