1 /*
2 * Copyright (c) 2017, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file cm_hal.h
24 //! \brief Main Entry point for CM HAL component
25 //!
26 #ifndef __CM_HAL_H__
27 #define __CM_HAL_H__
28
29 #include "renderhal_legacy.h"
30 #include "cm_common.h"
31 #include "cm_debug.h"
32 #include "cm_csync.h"
33 #include "cm_ish.h"
34 #include "mhw_vebox.h"
35 #include "cm_hal_generic.h"
36 #include "media_perf_profiler.h"
37 #include <string>
38 #include <map>
39
40 #define DiscardLow8Bits(x) (uint16_t)(0xff00 & x)
41 #define FloatToS3_12(x) (uint16_t)((short)(x * 4096))
42 #define FloatToS3_4(x) (DiscardLow8Bits(FloatToS3_12(x)))
43
44 #define CM_32K (32*1024)
45
46 #define HAL_CM_KERNEL_CACHE_MISS_THRESHOLD 4
47 #define HAL_CM_KERNEL_CACHE_HIT_TO_MISS_RATIO 100
48
49 #ifdef _WIN64
50 #define IGC_DLL_NAME "igc64.dll"
51 #else
52 #define IGC_DLL_NAME "igc32.dll"
53 #endif // _WIN64
54
55 #define SURFACE_FLAG_ASSUME_NOT_IN_USE 1
56 #define CM_THREADSPACE_MAX_COLOR_COUNT 16
57
58 static const uint32_t INVALID_STREAM_INDEX = 0xFFFFFFFF;
59
60 //*-----------------------------------------------------------------------------
61 //| Macro unsets bitPos bit in value
62 //*-----------------------------------------------------------------------------
63 #ifndef CM_HAL_UNSETBIT
64 #define CM_HAL_UNSETBIT(value, bitPos) \
65 { \
66 value = (value & ~(1 << bitPos)); \
67 }
68 #endif
69
70 #ifndef CM_HAL_UNSETBIT64
71 #define CM_HAL_UNSETBIT64(value, bitPos) \
72 { \
73 value = (value & ~(1i64 << bitPos)); \
74 }
75 #endif
76
77 //*-----------------------------------------------------------------------------
78 //| Macro sets bitPos bit in value
79 //*-----------------------------------------------------------------------------
80 #ifndef CM_HAL_SETBIT
81 #define CM_HAL_SETBIT(value, bitPos) \
82 { \
83 value = (value | (1 << bitPos)); \
84 }
85 #endif
86
87 #ifndef CM_HAL_SETBIT64
88 #define CM_HAL_SETBIT64(value, bitPos) \
89 { \
90 value = (value | (1i64 << bitPos)); \
91 }
92 #endif
93
94 //*-----------------------------------------------------------------------------
95 //| Macro checks if bitPos bit in value is set
96 //*-----------------------------------------------------------------------------
97 #ifndef CM_HAL_CHECKBIT_IS_SET
98 #define CM_HAL_CHECKBIT_IS_SET(bitIsSet, value, bitPos) \
99 { \
100 bitIsSet = ((value) & (1 << bitPos))? true: false; \
101 }
102 #endif
103
104 #ifndef CM_HAL_CHECKBIT_IS_SET64
105 #define CM_HAL_CHECKBIT_IS_SET64(bitIsSet, value, bitPos) \
106 { \
107 bitIsSet = ((value) & (1i64 << bitPos)); \
108 }
109 #endif
110
111 #define MAX_CUSTOMIZED_PERFTAG_INDEX 249
112 #define GPUINIT_PERFTAG_INDEX 250
113 #define GPUCOPY_READ_PERFTAG_INDEX 251
114 #define GPUCOPY_WRITE_PERFTAG_INDEX 252
115 #define GPUCOPY_G2G_PERFTAG_INDEX 253
116 #define GPUCOPY_C2C_PERFTAG_INDEX 254
117 #define VEBOX_TASK_PERFTAG_INDEX 255
118
119 #define MAX_COMBINE_NUM_IN_PERFTAG 16
120
121 #define MAX_ELEMENT_TYPE_COUNT 6
122
123 //Copied over from auxilarydevice to avoid inclusion of video acceleration APIs.
124 struct CMLOOKUP_ENTRY
125 {
126 void *osSurfaceHandle; // Surface defined in video acceleration APIs provided by the OS.
127 UMD_RESOURCE umdSurfaceHandle; // Surface defined in UMD.
128 uint32_t surfaceAllocationIndex; // Driver allocation index
129 };
130 typedef CMLOOKUP_ENTRY *PCMLOOKUP_ENTRY;
131
132 struct CMSURFACE_REG_TABLE
133 {
134 uint32_t count; // Number of entries
135 CMLOOKUP_ENTRY *entries; // Surface Lookup table
136 };
137
138 struct CM_HAL_MAX_VALUES
139 {
140 uint32_t maxTasks; // [in] Max Tasks
141 uint32_t maxKernelsPerTask; // [in] Max kernels per task
142 uint32_t maxKernelBinarySize; // [in] Max kernel binary size
143 uint32_t maxSpillSizePerHwThread; // [in] Max spill size per thread
144 uint32_t maxSamplerTableSize; // [in] Max sampler table size
145 uint32_t maxBufferTableSize; // [in] Max buffer/bufferUP table Size
146 uint32_t max2DSurfaceTableSize; // [in] Max 2D surface table Size
147 uint32_t max3DSurfaceTableSize; // [in] Max 3D surface table Size
148 uint32_t maxArgsPerKernel; // [in] Max arguments per kernel
149 uint32_t maxArgByteSizePerKernel; // [in] Max argument size in byte per kernel
150 uint32_t maxSurfacesPerKernel; // [in] Max Surfaces Per Kernel
151 uint32_t maxSamplersPerKernel; // [in] Max Samplers per kernel
152 uint32_t maxHwThreads; // [in] Max HW threads
153 uint32_t maxUserThreadsPerTask; // [in] Max user threads per task
154 uint32_t maxUserThreadsPerTaskNoThreadArg; // [in] Max user threads per task with no thread arg
155 };
156 typedef CM_HAL_MAX_VALUES *PCM_HAL_MAX_VALUES;
157
158 //------------------------------------------------------------------------------------------------
159 //| HAL CM Max Values extention which has more entries which are not included in CM_HAL_MAX_VALUES
160 //-------------------------------------------------------------------------------------------------
161 struct CM_HAL_MAX_VALUES_EX
162 {
163 uint32_t max2DUPSurfaceTableSize; // [in] Max 2D UP surface table Size
164 uint32_t maxSampler8x8TableSize; // [in] Max sampler 8x8 table size
165 uint32_t maxCURBESizePerKernel; // [in] Max CURBE size per kernel
166 uint32_t maxCURBESizePerTask; // [in] Max CURBE size per task
167 uint32_t maxIndirectDataSizePerKernel; // [in] Max indirect data size per kernel
168 uint32_t maxUserThreadsPerMediaWalker; // [in] Max user threads per media walker
169 uint32_t maxUserThreadsPerThreadGroup; // [in] Max user threads per thread group
170 };
171 typedef CM_HAL_MAX_VALUES_EX *PCM_HAL_MAX_VALUES_EX;
172
173 struct CM_INDIRECT_SURFACE_INFO
174 {
175 uint16_t kind; // Surface kind, values in CM_ARG_KIND. For now, only support ARG_KIND_SURFACE_1D/ARG_KIND_SURFACE_2D/ARG_KIND_SURFACE_2D_UP
176 uint16_t surfaceIndex; // Surface handle used in driver
177 uint16_t bindingTableIndex; // Binding table index
178 uint16_t numBTIPerSurf; // Binding table index count for per surface
179 };
180 typedef CM_INDIRECT_SURFACE_INFO *PCM_INDIRECT_SURFACE_INFO;
181
182 //*-----------------------------------------------------------------------------
183 //| HAL CM Indirect Data Param
184 //*-----------------------------------------------------------------------------
185 struct CM_HAL_INDIRECT_DATA_PARAM
186 {
187 uint16_t indirectDataSize; // [in] Indirect Data Size
188 uint16_t surfaceCount;
189 uint8_t *indirectData; // [in] Pointer to Indirect Data Block
190 PCM_INDIRECT_SURFACE_INFO surfaceInfo;
191 };
192 typedef CM_HAL_INDIRECT_DATA_PARAM *PCM_HAL_INDIRECT_DATA_PARAM;
193
194 //------------------------
195 //| HAL CM Create Param
196 //------------------------
197 struct CM_HAL_CREATE_PARAM
198 {
199 bool disableScratchSpace; // Flag to disable Scratch Space
200 uint32_t scratchSpaceSize; // Size of Scratch Space per HW thread
201 uint32_t maxTaskNumber; // Max Task Number
202 bool requestSliceShutdown; // Flag to enable slice shutdown
203 bool requestCustomGpuContext; // Flag to use CUSTOM GPU Context
204 uint32_t kernelBinarySizeinGSH; // Size to be reserved in GSH for kernel binary
205 bool dynamicStateHeap; // Use Dynamic State Heap management
206 bool disabledMidThreadPreemption; // Flag to enable mid thread preemption for GPGPU
207 bool enabledKernelDebug; // Flag to enable Kernel debug
208 bool refactor; // Flag to enable the fast path
209 bool disableVebox; // Flag to disable VEBOX API
210 };
211 typedef CM_HAL_CREATE_PARAM *PCM_HAL_CREATE_PARAM;
212
213 //------------------------------------------------------------------------------
214 //| CM Sampler Param
215 //------------------------------------------------------------------------------
216 enum CM_HAL_PIXEL_TYPE
217 {
218 CM_HAL_PIXEL_UINT,
219 CM_HAL_PIXEL_SINT,
220 CM_HAL_PIXEL_OTHER
221 };
222
223 struct CM_HAL_SAMPLER_PARAM
224 {
225 uint32_t magFilter; // [in] Mag Filter
226 uint32_t minFilter; // [in] Min Filter
227 uint32_t addressU; // [in] Address U
228 uint32_t addressV; // [in] Address V
229 uint32_t addressW; // [in] Address W
230 uint32_t handle; // [out] Handle
231
232 CM_HAL_PIXEL_TYPE surfaceFormat;
233 union
234 {
235 uint32_t borderColorRedU;
236 int32_t borderColorRedS;
237 float borderColorRedF;
238 };
239
240 union
241 {
242 uint32_t borderColorGreenU;
243 int32_t borderColorGreenS;
244 float borderColorGreenF;
245 };
246
247 union
248 {
249 uint32_t borderColorBlueU;
250 int32_t borderColorBlueS;
251 float borderColorBlueF;
252 };
253
254 union
255 {
256 uint32_t borderColorAlphaU;
257 int32_t borderColorAlphaS;
258 float borderColorAlphaF;
259 };
260 };
261 typedef CM_HAL_SAMPLER_PARAM *PCM_HAL_SAMPLER_PARAM;
262
263 struct CM_HAL_SURFACE_ENTRY_INFO_ARRAY
264 {
265 uint32_t maxEntryNum;
266 uint32_t usedIndex;
267 PCM_SURFACE_DETAILS surfEntryInfos;
268 uint32_t globalSurfNum;
269 PCM_SURFACE_DETAILS globalSurfInfos;
270 };
271
272 struct CM_HAL_SURFACE_ENTRY_INFO_ARRAYS
273 {
274 uint32_t kernelNum;
275 CM_HAL_SURFACE_ENTRY_INFO_ARRAY *surfEntryInfosArray;
276 };
277
278 //------------------------------------------------------------------------------
279 //| CM BARRIER MODES
280 //------------------------------------------------------------------------------
281 enum CM_BARRIER_MODE
282 {
283 CM_NO_BARRIER = 0,
284 CM_LOCAL_BARRIER = 1,
285 CM_GLOBAL_BARRIER = 2
286 };
287
288 struct CM_SAMPLER_BTI_ENTRY
289 {
290 uint32_t samplerIndex;
291 uint32_t samplerBTI;
292 };
293 typedef CM_SAMPLER_BTI_ENTRY *PCM_SAMPLER_BTI_ENTRY;
294
295 //*----------------
296 //| CM Query Type
297 //*----------------
298 enum CM_QUERY_TYPE
299 {
300 CM_QUERY_VERSION,
301 CM_QUERY_REG_HANDLE,
302 CM_QUERY_MAX_VALUES,
303 CM_QUERY_GPU,
304 CM_QUERY_GT,
305 CM_QUERY_MIN_RENDER_FREQ,
306 CM_QUERY_MAX_RENDER_FREQ,
307 CM_QUERY_STEP,
308 CM_QUERY_GPU_FREQ,
309 CM_QUERY_MAX_VALUES_EX,
310 CM_QUERY_SURFACE2D_FORMAT_COUNT,
311 CM_QUERY_SURFACE2D_FORMATS,
312 CM_QUERY_PLATFORM_INFO
313 };
314
315 //*-----------------------------------------------------------------------------
316 //| CM Query Caps
317 //*-----------------------------------------------------------------------------
318 struct CM_QUERY_CAPS
319 {
320 CM_QUERY_TYPE type;
321 union
322 {
323 int32_t version;
324 HANDLE hRegistration;
325 CM_HAL_MAX_VALUES maxValues;
326 CM_HAL_MAX_VALUES_EX maxValuesEx;
327 uint32_t maxVmeTableSize;
328 uint32_t genCore;
329 uint32_t genGT;
330 uint32_t minRenderFreq;
331 uint32_t maxRenderFreq;
332 uint32_t genStepId;
333 uint32_t gpuCurrentFreq;
334 uint32_t surface2DCount;
335 GMM_RESOURCE_FORMAT *surface2DFormats;
336 CM_PLATFORM_INFO platformInfo;
337 };
338 };
339 typedef CM_QUERY_CAPS *PCM_QUERY_CAPS;
340
341 //------------------------------------------------------------------------------
342 //| Enumeration for Task Status
343 //------------------------------------------------------------------------------
344 enum CM_HAL_TASK_STATUS
345 {
346 CM_TASK_QUEUED,
347 CM_TASK_IN_PROGRESS,
348 CM_TASK_FINISHED,
349 CM_TASK_RESET
350 };
351
352 //------------------------------------------------------------------------------
353 //| CM conditional batch buffer end information
354 //------------------------------------------------------------------------------
355 struct CM_HAL_CONDITIONAL_BB_END_INFO
356 {
357 uint32_t bufferTableIndex;
358 uint32_t offset;
359 uint32_t compareValue;
360 bool disableCompareMask;
361 bool endCurrentLevel;
362 uint32_t operatorCode;
363 };
364 typedef CM_HAL_CONDITIONAL_BB_END_INFO *PCM_HAL_CONDITIONAL_BB_END_INFO;
365
366 //------------------------------------------------------------------------------
367 //| HAL CM Query Task Param
368 //------------------------------------------------------------------------------
369 struct CM_HAL_QUERY_TASK_PARAM
370 {
371 int32_t taskId; // [in] Task ID
372 uint32_t taskType; // [in] Task type
373 CM_QUEUE_CREATE_OPTION queueOption; // [in] Queue type
374 CM_HAL_TASK_STATUS status; // [out] Task Status
375 uint64_t taskDurationNs; // [out] Task Duration
376 uint64_t taskDurationTicks; // [out] Task Duration in Ticks
377 uint64_t taskHWStartTimeStampInTicks; // [out] Task Start Time Stamp in Ticks
378 uint64_t taskHWEndTimeStampInTicks; // [out] Task End Time Stamp in Ticks
379 LARGE_INTEGER taskGlobalSubmitTimeCpu; // [out] The CM task submission time in CPU
380 LARGE_INTEGER taskSubmitTimeGpu; // [out] The CM task submission time in GPU
381 LARGE_INTEGER taskHWStartTimeStamp; // [out] The task start execution time in GPU
382 LARGE_INTEGER taskHWEndTimeStamp; // [out] The task end execution time in GPU
383 };
384 typedef CM_HAL_QUERY_TASK_PARAM *PCM_HAL_QUERY_TASK_PARAM;
385
386 //*-----------------------------------------------------------------------------
387 //| Execute Group data params
388 //*-----------------------------------------------------------------------------
389 struct CM_HAL_EXEC_TASK_GROUP_PARAM
390 {
391 PCM_HAL_KERNEL_PARAM *kernels; // [in] Array of Kernel data
392 uint32_t *kernelSizes; // [in] Parallel array of Kernel Size
393 uint32_t numKernels; // [in] Number of Kernels in a task
394 int32_t taskIdOut; // [out] Task ID
395 uint32_t threadSpaceWidth; // [in] thread space width within group
396 uint32_t threadSpaceHeight; // [in] thread space height within group
397 uint32_t threadSpaceDepth; // [in] thread space depth within group
398 uint32_t groupSpaceWidth; // [in] group space width
399 uint32_t groupSpaceHeight; // [in] group space height
400 uint32_t groupSpaceDepth; // [in] group space depth
401 uint32_t slmSize; // [in] SLM size per thread group in 1KB unit
402 CM_HAL_SURFACE_ENTRY_INFO_ARRAYS surEntryInfoArrays; // [in] GT-PIN
403 void *osData; // [out] Used for Linux OS data to pass to event
404 uint64_t syncBitmap; // [in] synchronization flag among kernels
405 bool globalSurfaceUsed; // [in] is global surface used
406 uint32_t *kernelCurbeOffset; // [in] Array of Kernel Curbe Offset
407 bool kernelDebugEnabled; // [in] kernel debug is enabled
408 CM_TASK_CONFIG taskConfig; // [in] task Config
409 CM_EXECUTION_CONFIG krnExecCfg[CM_MAX_KERNELS_PER_TASK]; // [in] kernel execution config in a task. replace numOfWalkers in CM_TASK_CONFIG.
410 void *userDefinedMediaState; // [in] pointer to a user defined media state heap block
411 CM_QUEUE_CREATE_OPTION queueOption; // [in] multiple contexts queue option
412 PMOS_VIRTUALENGINE_HINT_PARAMS mosVeHintParams; // [in] pointer to virtual engine paramter saved in CmQueueRT
413 uint64_t conditionalEndBitmap; // [in] bit map for conditional end b/w kernels
414 CM_HAL_CONDITIONAL_BB_END_INFO conditionalEndInfo[CM_MAX_CONDITIONAL_END_CMDS];
415 };
416 typedef CM_HAL_EXEC_TASK_GROUP_PARAM *PCM_HAL_EXEC_GROUP_TASK_PARAM;
417
418 struct CM_HAL_EXEC_HINTS_TASK_PARAM
419 {
420 PCM_HAL_KERNEL_PARAM *kernels; // [in] Array of kernel data
421 uint32_t *kernelSizes; // [in] Parallel array of kernel size
422 uint32_t numKernels; // [in] Number of kernels in a task
423 int32_t taskIdOut; // [out] Task ID
424 uint32_t hints; // [in] Hints
425 uint32_t numTasksGenerated; // [in] Number of task generated already for split task
426 bool isLastTask; // [in] Used to split tasks
427 void *osData; // [out] Used for Linux OS data to pass to event
428 uint32_t *kernelCurbeOffset; // [in] Kernel Curbe offset
429 void *userDefinedMediaState; // [in] pointer to a user defined media state heap block
430 CM_QUEUE_CREATE_OPTION queueOption; // [in] multiple contexts queue option
431 };
432 typedef CM_HAL_EXEC_HINTS_TASK_PARAM *PCM_HAL_EXEC_HINTS_TASK_PARAM;
433
434 //------------------------------------------------------------------------------
435 //| CM scoreboard XY with color,mask and slice-sub-slice select
436 //------------------------------------------------------------------------------
437 struct CM_HAL_SCOREBOARD
438 {
439 int32_t x;
440 int32_t y;
441 uint8_t mask;
442 uint8_t resetMask;
443 uint8_t color;
444 uint8_t sliceSelect;
445 uint8_t subSliceSelect;
446 };
447 typedef CM_HAL_SCOREBOARD *PCM_HAL_SCOREBOARD;
448
449 //------------------------------------------------------------------------------
450 //| CM scoreboard XY with mask and resetMask for Enqueue path
451 //------------------------------------------------------------------------------
452 struct CM_HAL_MASK_AND_RESET
453 {
454 uint8_t mask;
455 uint8_t resetMask;
456 };
457 typedef CM_HAL_MASK_AND_RESET *PCM_HAL_MASK_AND_RESET;
458
459 //------------------------------------------------------------------------------
460 //| CM dependency information
461 //------------------------------------------------------------------------------
462 struct CM_HAL_DEPENDENCY
463 {
464 uint32_t count;
465 int32_t deltaX[CM_HAL_MAX_DEPENDENCY_COUNT];
466 int32_t deltaY[CM_HAL_MAX_DEPENDENCY_COUNT];
467 };
468
469 struct CM_HAL_EXEC_TASK_PARAM
470 {
471 PCM_HAL_KERNEL_PARAM *kernels; // [in] Array of Kernel data
472 uint32_t *kernelSizes; // [in] Parallel array of Kernel Size
473 uint32_t numKernels; // [in] Number of Kernels in a task
474 int32_t taskIdOut; // [out] Task ID
475 CM_HAL_SCOREBOARD **threadCoordinates; // [in] Scoreboard(x,y)
476 CM_DEPENDENCY_PATTERN dependencyPattern; // [in] pattern
477 uint32_t threadSpaceWidth; // [in] width
478 uint32_t threadSpaceHeight; // [in] height
479 CM_HAL_SURFACE_ENTRY_INFO_ARRAYS surfEntryInfoArrays; // [out] Used by GT-Pin
480 void *osData; // [out] Used for Linux OS data to pass to event
481 uint32_t colorCountMinusOne; // [in]
482 PCM_HAL_MASK_AND_RESET *dependencyMasks; // [in] media object thread dependency masks
483 uint64_t syncBitmap; // [in] bit map for sync b/w kernels
484 bool globalSurfaceUsed; // [in] if global surface used
485 uint32_t *kernelCurbeOffset; // [in] array of kernel's curbe offset
486 CM_WALKING_PATTERN walkingPattern; // [in] media walking pattern
487 uint8_t walkingParamsValid; // [in] for engineering build
488 CM_WALKING_PARAMETERS walkingParams; // [in] for engineering build
489 uint8_t dependencyVectorsValid; // [in] for engineering build
490 CM_HAL_DEPENDENCY dependencyVectors; // [in] for engineering build
491 CM_MW_GROUP_SELECT mediaWalkerGroupSelect; // [in]
492 bool kernelDebugEnabled; // [in] kernel debug is enabled
493 uint64_t conditionalEndBitmap; // [in] bit map for conditional end b/w kernels
494 CM_HAL_CONDITIONAL_BB_END_INFO conditionalEndInfo[CM_MAX_CONDITIONAL_END_CMDS];
495 CM_TASK_CONFIG taskConfig; // [in] task Config
496 void *userDefinedMediaState; // [in] pointer to a user defined media state heap block
497 CM_QUEUE_CREATE_OPTION queueOption; // [in] multiple contexts queue option
498 };
499 typedef CM_HAL_EXEC_TASK_PARAM *PCM_HAL_EXEC_TASK_PARAM;
500
501 //*-----------------------------------------------------------------------------
502 //| HAL CM Task Param
503 //*-----------------------------------------------------------------------------
504 struct CM_HAL_TASK_PARAM
505 {
506 uint32_t numKernels; // [in] number of kernels
507 uint64_t syncBitmap; // [in] Sync bitmap
508 uint32_t batchBufferSize; // [in] Size of Batch Buffer Needed
509 uint32_t vfeCurbeSize; // [out] Sum of CURBE Size
510 uint32_t urbEntrySize; // [out] Maximum Payload Size
511 CM_HAL_SCOREBOARD **threadCoordinates; // [in] Scoreboard(x,y)
512 CM_DEPENDENCY_PATTERN dependencyPattern; // [in] pattern
513 uint32_t threadSpaceWidth; // [in] width
514 uint32_t threadSpaceHeight; // [in] height
515 uint32_t groupSpaceWidth; // [in] group space width
516 uint32_t groupSpaceHeight; // [in] group space height
517 uint32_t slmSize; // [in] size of SLM
518 CM_HAL_SURFACE_ENTRY_INFO_ARRAYS surfEntryInfoArrays; // [in] GTPin
519 uint32_t curKernelIndex;
520 uint32_t colorCountMinusOne; // [in] color count
521 PCM_HAL_MASK_AND_RESET *dependencyMasks; // [in] Thread dependency masks
522 uint8_t reuseBBUpdateMask; // [in] re-use batch buffer and just update mask
523 uint32_t surfacePerBT; // [out] surface number for binding table
524 bool blGpGpuWalkerEnabled; // [out]
525 CM_WALKING_PATTERN walkingPattern; // [in] media walking pattern
526 bool hasBarrier; // [in] if there is barrier
527 uint8_t walkingParamsValid; // [in] for engineering build
528 CM_WALKING_PARAMETERS walkingParams; // [in] for engineering build
529 uint8_t dependencyVectorsValid; // [in] for engineering build
530 CM_HAL_DEPENDENCY dependencyVectors; // [in] for engineering build
531 CM_MW_GROUP_SELECT mediaWalkerGroupSelect; // [in]
532 uint32_t kernelDebugEnabled; // [in]
533 uint64_t conditionalEndBitmap; // [in] conditional end bitmap
534 CM_HAL_CONDITIONAL_BB_END_INFO
535 conditionalEndInfo[CM_MAX_CONDITIONAL_END_CMDS]; // [in] conditional BB end info used to fill conditionalBBEndParams
536
537 MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS
538 conditionalBBEndParams[CM_MAX_CONDITIONAL_END_CMDS];
539
540 CM_TASK_CONFIG taskConfig; // [in] task Config
541 CM_EXECUTION_CONFIG krnExecCfg[CM_MAX_KERNELS_PER_TASK]; // [in] kernel execution config in a task. replace numOfWalkers in CM_TASK_CONFIG.
542
543 void *userDefinedMediaState; // [in] pointer to a user defined media state heap block
544
545 // [in] each kernel's sampler heap offset from the DSH sampler heap base
546 unsigned int samplerOffsetsByKernel[CM_MAX_KERNELS_PER_TASK];
547
548 // [in] each kernel's sampler count
549 unsigned int samplerCountsByKernel[CM_MAX_KERNELS_PER_TASK];
550
551 // [in] each kernel's indirect sampler heap offset from the DSH sampler heap base
552 unsigned int samplerIndirectOffsetsByKernel[CM_MAX_KERNELS_PER_TASK];
553
554 CM_QUEUE_CREATE_OPTION queueOption; // [in] multiple contexts queue option
555 PMOS_VIRTUALENGINE_HINT_PARAMS mosVeHintParams; // [in] pointer to virtual engine paramter saved in CmQueueRT
556 };
557 typedef CM_HAL_TASK_PARAM *PCM_HAL_TASK_PARAM;
558
559 //------------------------------------------------------------------------------
560 //| CM batch buffer dirty status
561 //------------------------------------------------------------------------------
562 enum CM_HAL_BB_DIRTY_STATUS
563 {
564 CM_HAL_BB_CLEAN = 0,
565 CM_HAL_BB_DIRTY = 1
566 };
567
568 //------------------------------------------------------------------------------
569 //| CM dispatch information for 26Z (for EnqueueWithHints)
570 //------------------------------------------------------------------------------
571 struct CM_HAL_WAVEFRONT26Z_DISPATCH_INFO
572 {
573 uint32_t numWaves;
574 uint32_t *numThreadsInWave;
575 };
576
577 //*-----------------------------------------------------------------------------
578 //| HAL CM Kernel Threadspace Param
579 //*-----------------------------------------------------------------------------
580 struct CM_HAL_KERNEL_THREADSPACE_PARAM
581 {
582 uint16_t threadSpaceWidth; // [in] Kernel Threadspace width
583 uint16_t threadSpaceHeight; // [in] Kernel Threadspace height
584 CM_DEPENDENCY_PATTERN patternType; // [in] Kernel dependency as enum
585 CM_HAL_DEPENDENCY dependencyInfo; // [in] Kernel dependency
586 PCM_HAL_SCOREBOARD threadCoordinates; // [in]
587 uint8_t reuseBBUpdateMask; // [in]
588 CM_HAL_WAVEFRONT26Z_DISPATCH_INFO dispatchInfo; // [in]
589 uint8_t globalDependencyMask; // [in] dependency mask in gloabal dependency vectors
590 uint8_t walkingParamsValid; // [in] for engineering build
591 CM_WALKING_PARAMETERS walkingParams; // [in] for engineering build
592 uint8_t dependencyVectorsValid; // [in] for engineering build
593 CM_HAL_DEPENDENCY dependencyVectors; // [in] for engineering build
594 uint32_t colorCountMinusOne; // [in] for color count minus one
595 CM_MW_GROUP_SELECT groupSelect; // [in] for group select on BDW+
596 CM_HAL_BB_DIRTY_STATUS bbDirtyStatus; // [in] batch buffer dirty status
597 CM_WALKING_PATTERN walkingPattern; // [in] media walking pattern as enum
598 };
599 typedef CM_HAL_KERNEL_THREADSPACE_PARAM *PCM_HAL_KERNEL_THREADSPACE_PARAM;
600
601 //------------------------------------------------------------------------------
602 //| CM buffer types
603 //------------------------------------------------------------------------------
604 enum CM_BUFFER_TYPE
605 {
606 CM_BUFFER_N = 0,
607 CM_BUFFER_UP = 1,
608 CM_BUFFER_SVM = 2,
609 CM_BUFFER_GLOBAL = 3,
610 CM_BUFFER_STATE = 4,
611 CM_BUFFER_STATELESS = 5
612 };
613
614 //------------------------------------------------------------------------------
615 //| CM shift direction. Used for CloneKernel API to adjust head kernel allocation ID.
616 //| Need to adjust IDs after the kernel allocation entries are shifted
617 //| i.e. neighboring free kernel allocation entries are combined into a single larger entry
618 //------------------------------------------------------------------------------
619 enum CM_SHIFT_DIRECTION
620 {
621 CM_SHIFT_LEFT = 0,
622 CM_SHIFT_RIGHT = 1
623 };
624
625 //---------------
626 //| CM clone type
627 //---------------
628 enum CM_CLONE_TYPE
629 {
630 CM_NO_CLONE = 0, // regular kernel, not created from CloneKernel API and has no kernels that were cloned from it
631 CM_CLONE_ENTRY = 1, // 64B kernel allocation entry for a cloned kernel (will point to the head kernel's binary)
632 CM_HEAD_KERNEL = 2, // kernel allocation entry that contains kernel binary (clone kernels will use this offset)
633 CM_CLONE_AS_HEAD_KERNEL = 3 // cloned kernel is serving as a head kernel (original kernel and other clones can use this offset)
634 };
635
636 enum CM_STATE_BUFFER_TYPE
637 {
638 CM_STATE_BUFFER_NONE = 0,
639 CM_STATE_BUFFER_CURBE = 1,
640 };
641
642 //*-----------------------------------------------------------------------------
643 //| Enumeration for Kernel argument type
644 //*-----------------------------------------------------------------------------
645 enum CM_HAL_KERNEL_ARG_KIND
646 {
647 CM_ARGUMENT_GENERAL = 0x0,
648 CM_ARGUMENT_SAMPLER = 0x1,
649 CM_ARGUMENT_SURFACE2D = 0x2,
650 CM_ARGUMENT_SURFACEBUFFER = 0x3,
651 CM_ARGUMENT_SURFACE3D = 0x4,
652 CM_ARGUMENT_SURFACE_VME = 0x5,
653 CM_ARGUMENT_VME_STATE = 0x6,
654 CM_ARGUMENT_SURFACE2D_UP = 0x7,
655 CM_ARGUMENT_SURFACE_SAMPLER8X8_AVS = 0x8,
656 CM_ARGUMENT_SURFACE_SAMPLER8X8_VA = 0x9,
657 CM_ARGUMENT_SURFACE2D_SAMPLER = 0xb,
658 CM_ARGUMENT_SURFACE = 0xc,
659 CM_ARGUMENT_SURFACE2DUP_SAMPLER= 0xd,
660 CM_ARGUMENT_IMPLICT_LOCALSIZE = 0xe,
661 CM_ARGUMENT_IMPLICT_GROUPSIZE = 0xf,
662 CM_ARGUMENT_IMPLICIT_LOCALID = 0x10,
663 CM_ARGUMENT_STATE_BUFFER = 0x11,
664 CM_ARGUMENT_GENERAL_DEPVEC = 0x20,
665 CM_ARGUMENT_SURFACE2D_SCOREBOARD = 0x2A //used for SW scoreboarding
666 };
667
668 //*-----------------------------------------------------------------------------
669 //| HAL CM Kernel Argument Param
670 //*-----------------------------------------------------------------------------
671 struct CM_HAL_KERNEL_ARG_PARAM
672 {
673 CM_HAL_KERNEL_ARG_KIND kind; // [in] Kind of argument
674 uint32_t unitCount; // [in] 1 if argument is kernel arg, otherwise equal to thread count
675 uint32_t unitSize; // [in] Unit Size of the argument
676 uint32_t payloadOffset; // [in] Offset to Thread Payload
677 bool perThread; // [in] Per kernel / per thread argument
678 uint8_t *firstValue; // [in] Byte Pointer to First Value.
679 uint32_t nCustomValue; // [in] CM defined value for the special kind of argument
680 uint32_t aliasIndex; // [in] Alias index, used for CmSurface2D alias
681 bool aliasCreated; // [in] Whether or not alias was created for this argument
682 bool isNull; // [in] Whether this argument is a null surface
683 };
684 typedef CM_HAL_KERNEL_ARG_PARAM *PCM_HAL_KERNEL_ARG_PARAM;
685
686 //*-----------------------------------------------------------------------------
687 //| HAL CM Sampler BTI Entry
688 //*-----------------------------------------------------------------------------
689 struct CM_HAL_SAMPLER_BTI_ENTRY
690 {
691 uint32_t samplerIndex;
692 uint32_t samplerBTI;
693 };
694 typedef CM_HAL_SAMPLER_BTI_ENTRY *PCM_HAL_SAMPLER_BTI_ENTRY;
695
696 //*-----------------------------------------------------------------------------
697 //| HAL CM Sampler BTI Param
698 //*-----------------------------------------------------------------------------
699 struct CM_HAL_SAMPLER_BTI_PARAM
700 {
701 CM_HAL_SAMPLER_BTI_ENTRY samplerInfo[ CM_MAX_SAMPLER_TABLE_SIZE ];
702 uint32_t samplerCount;
703 };
704 typedef CM_HAL_SAMPLER_BTI_PARAM *PCM_HAL_SAMPLER_BTI_PARAM;
705
706 struct CM_HAL_CLONED_KERNEL_PARAM
707 {
708 bool isClonedKernel;
709 int32_t kernelID;
710 bool hasClones;
711 };
712
713 struct CM_GPGPU_WALKER_PARAMS
714 {
715 uint32_t interfaceDescriptorOffset : 5;
716 uint32_t gpgpuEnabled : 1;
717 uint32_t : 26;
718 uint32_t threadWidth;
719 uint32_t threadHeight;
720 uint32_t threadDepth;
721 uint32_t groupWidth;
722 uint32_t groupHeight;
723 uint32_t groupDepth;
724 };
725 typedef CM_GPGPU_WALKER_PARAMS *PCM_GPGPU_WALKER_PARAMS;
726
727 struct CM_SAMPLER_STATISTICS
728 {
729 uint32_t samplerCount[MAX_ELEMENT_TYPE_COUNT];
730 uint32_t samplerMultiplier[MAX_ELEMENT_TYPE_COUNT]; //used for distinguishing whether need to take two
731 uint32_t samplerIndexBase[MAX_ELEMENT_TYPE_COUNT];
732 };
733
734 //*-----------------------------------------------------------------------------
735 //| HAL CM Kernel Param
736 //*-----------------------------------------------------------------------------
737 struct CM_HAL_KERNEL_PARAM
738 {
739 CM_HAL_KERNEL_ARG_PARAM argParams[CM_MAX_ARGS_PER_KERNEL];
740 CM_SAMPLER_STATISTICS samplerStatistics; // [in] each sampler element type count in the kernel argument
741 uint8_t *kernelData; // [in] Pointer to Kernel data
742 uint32_t kernelDataSize; // [in] Size of Kernel Data
743 uint8_t *movInsData; // [in] pointer to move instruction data
744 uint32_t movInsDataSize; // [in] size of move instructions
745 uint8_t *kernelBinary; // [in] Execution code for the kernel
746 uint32_t kernelBinarySize; // [in] Size of Kernel Binary
747 uint32_t numThreads; // [in] Number of threads
748 uint32_t numArgs; // [in] Number of Kernel Args
749 bool perThreadArgExisted;
750 uint32_t numSurfaces; // [in] Number of Surfaces used in this kernel
751 uint32_t payloadSize; // [in] Kernel Payload Size
752 uint32_t totalCurbeSize; // [in] total CURBE size, GPGPU
753 uint32_t curbeOffset; // [in] curbe offset of kernel
754 uint32_t curbeSizePerThread; // [in] CURBE size per thread
755 uint32_t crossThreadConstDataLen; // [in] Cross-thread constant data length HSW+
756 uint32_t barrierMode; // [in] Barrier mode, 0-No barrier, 1-local barrier, 2-global barrier
757 uint32_t numberThreadsInGroup; // [in] Number of Threads in Thread Group
758 uint32_t slmSize; // [in] SLM size in 1K-Bytes or 4K-Bytes
759 uint32_t spillSize; // [in] Kernel spill area, obtained from JITTER
760 uint32_t cmFlags; // [in] Kernel flags
761 uint64_t kernelId; // [in] Kernel Id
762 CM_HAL_KERNEL_THREADSPACE_PARAM kernelThreadSpaceParam; // [in] ThreadSpace Information
763 CM_HAL_WALKER_PARAMS walkerParams; // [out] Media walker parameters for kernel:filled in HalCm_ParseTask
764 bool globalSurfaceUsed; // [in] Global surface used
765 uint32_t globalSurface[CM_MAX_GLOBAL_SURFACE_NUMBER]; // [in] Global Surface indexes
766 CM_GPGPU_WALKER_PARAMS gpgpuWalkerParams;
767 bool kernelDebugEnabled; // [in] kernel debug is enabled
768 CM_HAL_INDIRECT_DATA_PARAM indirectDataParam;
769 char kernelName[ CM_MAX_KERNEL_NAME_SIZE_IN_BYTE ]; // [in] A fixed size array to hold the kernel name
770 CM_HAL_SAMPLER_BTI_PARAM samplerBTIParam;
771 uint32_t localIdIndex; //local ID index has different location with different compiler version
772 CM_HAL_CLONED_KERNEL_PARAM clonedKernelParam;
773 CM_STATE_BUFFER_TYPE stateBufferType;
774 std::list<SamplerParam> *samplerHeap;
775 };
776 typedef CM_HAL_KERNEL_PARAM *PCM_HAL_KERNEL_PARAM;
777
778 //*----------------------
779 //| CM Set Type
780 //*----------------------
781 enum CM_SET_TYPE
782 {
783 CM_SET_MAX_HW_THREADS,
784 CM_SET_HW_L3_CONFIG
785 };
786
787 struct CM_HAL_MAX_SET_CAPS_PARAM
788 {
789 CM_SET_TYPE type;
790 union
791 {
792 uint32_t maxValue;
793 L3ConfigRegisterValues l3CacheValues;
794 };
795
796 };
797 typedef CM_HAL_MAX_SET_CAPS_PARAM *PCM_HAL_MAX_SET_CAPS_PARAM;
798
799 //------------------------------------------------------------------------------
800 //| CM Buffer Param
801 //------------------------------------------------------------------------------
802 typedef struct _CM_HAL_BUFFER_PARAM
803 {
804 size_t size; // [in] Buffer Size
805 CM_BUFFER_TYPE type; // [in] Buffer type: Buffer, UP, SVM
806 void *data; // [in/out] System address of this buffer
807 uint32_t handle; // [in/out] Handle
808 uint32_t lockFlag; // [in] Lock flag
809 PMOS_RESOURCE mosResource; // [in] Mos resource
810 bool isAllocatedbyCmrtUmd; // [in] Flag for Cmrt@umd Created Buffer
811 uint64_t gfxAddress; // [out] GFX address of this buffer
812 } CM_HAL_BUFFER_PARAM, *PCM_HAL_BUFFER_PARAM;
813
814 //------------------------------------------------------------------------------
815 //| CM Buffer Set Surface State Param
816 //------------------------------------------------------------------------------
817 typedef struct _CM_HAL_BUFFER_SURFACE_STATE_PARAM
818 {
819 size_t size; // [in] Surface State Size
820 uint32_t offset; // [in] Surface State Base Address Offset
821 uint16_t mocs; // [in] Surface State mocs settings
822 uint32_t aliasIndex; // [in] Surface Alias Index
823 uint32_t handle; // [in] Handle
824 } CM_HAL_BUFFER_SURFACE_STATE_PARAM, *PCM_HAL_BUFFER_SURFACE_STATE_PARAM;
825
826 //------------------------------------------------------------------------------
827 //| CM BB Args
828 //------------------------------------------------------------------------------
829 typedef struct _CM_HAL_BB_ARGS
830 {
831 uint64_t kernelIds[CM_MAX_KERNELS_PER_TASK];
832 uint64_t refCount;
833 bool latest;
834 } CM_HAL_BB_ARGS, *PCM_HAL_BB_ARGS;
835
836 //------------------------------------------------------------------------------
837 //| CM 2DUP Param
838 //------------------------------------------------------------------------------
839 typedef struct _CM_HAL_SURFACE2D_UP_PARAM
840 {
841 uint32_t width; // [in] Surface Width
842 uint32_t height; // [in] Surface Height
843 MOS_FORMAT format; // [in] Surface Format
844 void *data; // [in/out] Pointer to data
845 uint32_t pitch; // [out] Pitch
846 uint32_t physicalSize; // [out] Physical size
847 uint32_t handle; // [in/out] Handle
848 } CM_HAL_SURFACE2D_UP_PARAM, *PCM_HAL_SURFACE2D_UP_PARAM;
849
850 //------------------------------------------------------------------------------
851 //| CM 2D Get Surface Information Param
852 //------------------------------------------------------------------------------
853 typedef struct _CM_HAL_SURFACE2D_INFO_PARAM
854 {
855 uint32_t width; // [out] Surface Width
856 uint32_t height; // [out] Surface Height
857 MOS_FORMAT format; // [out] Surface Format
858 uint32_t pitch; // [out] Pitch
859 UMD_RESOURCE surfaceHandle ; // [in] Driver Handler
860 uint32_t surfaceAllocationIndex; // [in] KMD Driver Handler
861 } CM_HAL_SURFACE2D_INFO_PARAM, *PCM_HAL_SURFACE2D_INFO_PARAM;
862
863 //------------------------------------------------------------------------------
864 //| CM 2D Set Surface State Param
865 //------------------------------------------------------------------------------
866 typedef struct _CM_HAL_SURFACE2D_SURFACE_STATE_PARAM
867 {
868 uint32_t format;
869 uint32_t width;
870 uint32_t height;
871 uint32_t depth;
872 uint32_t pitch;
873 uint16_t memoryObjectControl;
874 uint32_t surfaceXOffset;
875 uint32_t surfaceYOffset;
876 uint32_t surfaceOffset;
877 } CM_HAL_SURFACE2D_SURFACE_STATE_PARAM, *PCM_HAL_SURFACE2D_SURFACE_STATE_PARAM;
878
879 //------------------------------------------------------------------------------
880 //| CM 2D Lock/Unlock Param
881 //------------------------------------------------------------------------------
882 typedef struct _CM_HAL_SURFACE2D_LOCK_UNLOCK_PARAM
883 {
884 uint32_t width; // [in] Surface Width
885 uint32_t height; // [in] Surface Height
886 uint32_t size; // [in] Surface total size
887 MOS_FORMAT format; // [in] Surface Format
888 void *data; // [in/out] Pointer to data
889 uint32_t pitch; // [out] Pitch
890 MOS_PLANE_OFFSET YSurfaceOffset; // [out] Y plane Offset
891 MOS_PLANE_OFFSET USurfaceOffset; // [out] U plane Offset
892 MOS_PLANE_OFFSET VSurfaceOffset; // [out] V plane Offset
893 uint32_t lockFlag; // [out] lock flag
894 uint32_t handle; // [in/out] Handle
895 bool useGmmOffset; // [in/out] Only use Gmm offset in Linux
896 } CM_HAL_SURFACE2D_LOCK_UNLOCK_PARAM, *PCM_HAL_SURFACE2D_LOCK_UNLOCK_PARAM;
897
898 //*-----------------------------------------------------------------------------
899 //| Compression state
900 //*-----------------------------------------------------------------------------
901 enum MEMCOMP_STATE
902 {
903 MEMCOMP_DISABLED = 0,
904 MEMCOMP_HORIZONTAL,
905 MEMCOMP_VERTICAL
906 };
907
908 //------------------------------------------------------------------------------
909 //| CM 2D Surface Compression Parameter
910 //------------------------------------------------------------------------------
911 typedef struct _CM_HAL_SURFACE2D_COMPRESSION_PARAM
912 {
913 uint32_t handle;
914 MEMCOMP_STATE mmcMode;
915 }CM_HAL_SURFACE2D_COMPRESSIOM_PARAM, *PCM_HAL_SURFACE2D_COMPRESSION_PARAM;
916
917 //------------------------------------------------------------------------------
918 //| CM 2D Param
919 //------------------------------------------------------------------------------
920 typedef struct _CM_HAL_SURFACE2D_PARAM
921 {
922 uint32_t isAllocatedbyCmrtUmd; // [in] Flag for Cmrt@umd Created Surface
923 PMOS_RESOURCE mosResource; // [in] Mos resource
924 uint32_t width; // [in] Surface Width
925 uint32_t height; // [in] Surface Height
926 MOS_FORMAT format; // [in] Surface Format
927 void *data; // [in] PData
928 uint32_t pitch; // [out] Pitch
929 uint32_t handle; // [in/out] Handle
930 } CM_HAL_SURFACE2D_PARAM, *PCM_HAL_SURFACE2D_PARAM;
931
932 //------------------------------------------------------------------------------
933 //| CM 3D Param
934 //------------------------------------------------------------------------------
935 typedef struct _CM_HAL_3DRESOURCE_PARAM
936 {
937 uint32_t height; // [in] Surface Height
938 uint32_t width; // [in] Surface Width
939 uint32_t depth; // [in] Surface Depth
940 MOS_FORMAT format;
941 void *data; // [in/out] Pointer to data
942 uint32_t handle; // [in/out] Handle
943 uint32_t lockFlag; // [in] Lock flag
944 uint32_t pitch; // [out] Pitch of Resource
945 uint32_t qpitch; // [out] QPitch of the Resource
946 bool qpitchEnabled; // [out] if QPitch is supported by hw
947 } CM_HAL_3DRESOURCE_PARAM, *PCM_HAL_3DRESOURCE_PARAM;
948
949 //------------------------------------------------------------------------------
950 //| HalCm Kernel Param
951 //------------------------------------------------------------------------------
952 typedef struct _CM_HAL_KERNEL_SETUP
953 {
954 RENDERHAL_KERNEL_PARAM renderParam;
955 MHW_KERNEL_PARAM cacheEntry;
956 } CM_HAL_KERNEL_SETUP, *PCM_HAL_KERNEL_SETUP;
957
958 //------------------------------------------------------------------------------
959 //| CM vebox settings
960 //------------------------------------------------------------------------------
961 typedef struct _CM_VEBOX_SETTINGS
962 {
963 bool diEnabled;
964 bool dndiFirstFrame;
965 bool iecpEnabled;
966 bool dnEnabled;
967 uint32_t diOutputFrames;
968 bool demosaicEnabled;
969 bool vignetteEnabled;
970 bool hotPixelFilterEnabled;
971 }CM_VEBOX_SETTINGS;
972
973 #define VEBOX_SURFACE_NUMBER (16) //MAX
974
975 #define CM_VEBOX_PARAM_PAGE_SIZE 0x1000
976 #define CM_VEBOX_PARAM_PAGE_NUM 5
977
978 typedef struct _CM_AVS_TABLE_STATE_PARAMS {
979 bool bypassXAF;
980 bool bypassYAF;
981 uint8_t defaultSharpLevel;
982 uint8_t maxDerivative4Pixels;
983 uint8_t maxDerivative8Pixels;
984 uint8_t transitionArea4Pixels;
985 uint8_t transitionArea8Pixels;
986 CM_AVS_COEFF_TABLE tbl0X[ NUM_POLYPHASE_TABLES ];
987 CM_AVS_COEFF_TABLE tbl0Y[ NUM_POLYPHASE_TABLES ];
988 CM_AVS_COEFF_TABLE tbl1X[ NUM_POLYPHASE_TABLES ];
989 CM_AVS_COEFF_TABLE tbl1Y[ NUM_POLYPHASE_TABLES ];
990 bool enableRgbAdaptive;
991 bool adaptiveFilterAllChannels;
992 } CM_AVS_TABLE_STATE_PARAMS, *PCM_AVS_TABLE_STATE_PARAMS;
993
994 typedef struct _CM_HAL_AVS_PARAM {
995 MHW_SAMPLER_STATE_AVS_PARAM avsState; // [in] avs state table.
996 CM_AVS_TABLE_STATE_PARAMS avsTable; // [in] avs table.
997 } CM_HAL_AVS_PARAM, *PCM_HAL_AVS_PARAM;
998
999 /*
1000 * CONVOLVE STATE DATA STRUCTURES
1001 */
1002 typedef struct _CM_HAL_CONVOLVE_COEFF_TABLE{
1003 float FilterCoeff_0_0;
1004 float FilterCoeff_0_1;
1005 float FilterCoeff_0_2;
1006 float FilterCoeff_0_3;
1007 float FilterCoeff_0_4;
1008 float FilterCoeff_0_5;
1009 float FilterCoeff_0_6;
1010 float FilterCoeff_0_7;
1011 float FilterCoeff_0_8;
1012 float FilterCoeff_0_9;
1013 float FilterCoeff_0_10;
1014 float FilterCoeff_0_11;
1015 float FilterCoeff_0_12;
1016 float FilterCoeff_0_13;
1017 float FilterCoeff_0_14;
1018 float FilterCoeff_0_15;
1019 float FilterCoeff_0_16;
1020 float FilterCoeff_0_17;
1021 float FilterCoeff_0_18;
1022 float FilterCoeff_0_19;
1023 float FilterCoeff_0_20;
1024 float FilterCoeff_0_21;
1025 float FilterCoeff_0_22;
1026 float FilterCoeff_0_23;
1027 float FilterCoeff_0_24;
1028 float FilterCoeff_0_25;
1029 float FilterCoeff_0_26;
1030 float FilterCoeff_0_27;
1031 float FilterCoeff_0_28;
1032 float FilterCoeff_0_29;
1033 float FilterCoeff_0_30;
1034 float FilterCoeff_0_31;
1035 }CM_HAL_CONVOLVE_COEFF_TABLE;
1036
1037 #define CM_NUM_CONVOLVE_ROWS_SKL 31
1038 typedef struct _CM_HAL_CONVOLVE_STATE_MSG{
1039 bool coeffSize; //true 16-bit, false 8-bit
1040 uint8_t scaleDownValue; //Scale down value
1041 uint8_t width; //Kernel Width
1042 uint8_t height; //Kernel Height
1043 //SKL mode
1044 bool isVertical32Mode;
1045 bool isHorizontal32Mode;
1046 bool sklMode; // new added
1047 CM_CONVOLVE_SKL_TYPE nConvolveType;
1048 CM_HAL_CONVOLVE_COEFF_TABLE table[ CM_NUM_CONVOLVE_ROWS_SKL ];
1049 } CM_HAL_CONVOLVE_STATE_MSG;
1050
1051 /*
1052 * MISC SAMPLER8x8 State
1053 */
1054 typedef struct _CM_HAL_MISC_STATE {
1055 //uint32_t 0
1056 union{
1057 struct{
1058 uint32_t Height : 4;
1059 uint32_t Width : 4;
1060 uint32_t Reserved : 8;
1061 uint32_t Row0 : 16;
1062 };
1063 struct{
1064 uint32_t value;
1065 };
1066 }DW0;
1067
1068 //uint32_t 1
1069 union{
1070 struct{
1071 uint32_t Row1 : 16;
1072 uint32_t Row2 : 16;
1073 };
1074 struct{
1075 uint32_t value;
1076 };
1077 }DW1;
1078
1079 //uint32_t 2
1080 union{
1081 struct{
1082 uint32_t Row3 : 16;
1083 uint32_t Row4 : 16;
1084 };
1085 struct{
1086 uint32_t value;
1087 };
1088 }DW2;
1089
1090 //uint32_t 3
1091 union{
1092 struct{
1093 uint32_t Row5 : 16;
1094 uint32_t Row6 : 16;
1095 };
1096 struct{
1097 uint32_t value;
1098 };
1099 }DW3;
1100
1101 //uint32_t 4
1102 union{
1103 struct{
1104 uint32_t Row7 : 16;
1105 uint32_t Row8 : 16;
1106 };
1107 struct{
1108 uint32_t value;
1109 };
1110 }DW4;
1111
1112 //uint32_t 5
1113 union{
1114 struct{
1115 uint32_t Row9 : 16;
1116 uint32_t Row10 : 16;
1117 };
1118 struct{
1119 uint32_t value;
1120 };
1121 }DW5;
1122
1123 //uint32_t 6
1124 union{
1125 struct{
1126 uint32_t Row11 : 16;
1127 uint32_t Row12 : 16;
1128 };
1129 struct{
1130 uint32_t value;
1131 };
1132 }DW6;
1133
1134 //uint32_t 7
1135 union{
1136 struct{
1137 uint32_t Row13 : 16;
1138 uint32_t Row14 : 16;
1139 };
1140 struct{
1141 uint32_t value;
1142 };
1143 }DW7;
1144 } CM_HAL_MISC_STATE;
1145
1146 typedef struct _CM_HAL_SAMPLER_8X8_STATE
1147 {
1148 CM_HAL_SAMPLER_8X8_TYPE stateType; // [in] types of Sampler8x8
1149 union {
1150 CM_HAL_AVS_PARAM avsParam; // [in] avs parameters.
1151 CM_HAL_CONVOLVE_STATE_MSG convolveState;
1152 CM_HAL_MISC_STATE miscState;
1153 //Will add other sampler8x8 types later.
1154 };
1155 } CM_HAL_SAMPLER_8X8_STATE;
1156
1157 typedef struct _CM_HAL_SAMPLER_8X8_TABLE
1158 {
1159 CM_HAL_SAMPLER_8X8_TYPE stateType; // [in] types of Sampler8x8
1160 MHW_SAMPLER_AVS_TABLE_PARAM mhwSamplerAvsTableParam; // [in] Sampler8x8 avs table
1161 } CM_HAL_SAMPLER_8X8_TABLE, *PCM_HAL_SAMPLER_8X8_TABLE;
1162
1163 typedef struct _CM_HAL_SAMPLER_8X8_PARAM
1164 {
1165 CM_HAL_SAMPLER_8X8_STATE sampler8x8State; // [in] Sampler8x8 states
1166 uint32_t handle; // [out] Handle
1167 } CM_HAL_SAMPLER_8X8_PARAM, *PCM_HAL_SAMPLER_8X8_PARAM;
1168
1169 typedef struct _CM_HAL_SAMPLER_8X8_ENTRY{
1170 CM_HAL_SAMPLER_8X8_TABLE sampler8x8State; // [in] Sampler8x8 states
1171 bool inUse; // [out] If the entry has been occupied.
1172 } CM_HAL_SAMPLER_8X8_ENTRY, *PCM_HAL_SAMPLER_8X8_ENTRY;
1173
1174 typedef struct _CM_HAL_BUFFER_SURFACE_STATE_ENTRY
1175 {
1176 size_t surfaceStateSize;
1177 uint32_t surfaceStateOffset;
1178 uint16_t surfaceStateMOCS;
1179 } CM_HAL_BUFFER_SURFACE_STATE_ENTRY, *PCM_HAL_BUFFER_SURFACE_STATE_ENTRY;
1180
1181 //------------------------------------------------------------------------------
1182 //| HAL CM Buffer Table
1183 //------------------------------------------------------------------------------
1184 class CmSurfaceStateBufferMgr;
1185 typedef struct _CM_HAL_BUFFER_ENTRY
1186 {
1187 MOS_RESOURCE osResource; // [in] Pointer to OS Resource
1188 size_t size; // [in] Size of Buffer
1189 void *address; // [in] SVM address
1190 void *gmmResourceInfo; // [out] GMM resource info
1191 bool isAllocatedbyCmrtUmd; // [in] Whether Surface allocated by CMRT
1192 uint16_t memObjCtl; // [in] MOCS value set from CMRT
1193 CM_HAL_BUFFER_SURFACE_STATE_ENTRY surfaceStateEntry[CM_HAL_MAX_NUM_BUFFER_ALIASES]; // [in] width/height of surface to be used in surface state
1194 CmSurfaceStateBufferMgr *surfStateMgr;
1195 bool surfStateSet;
1196 } CM_HAL_BUFFER_ENTRY, *PCM_HAL_BUFFER_ENTRY;
1197
1198 //------------------------------------------------------------------------------
1199 //| HAL CM 2D UP Table
1200 //------------------------------------------------------------------------------
1201 class CmSurfaceState2Dor3DMgr;
1202 typedef struct _CM_HAL_SURFACE2D_UP_ENTRY
1203 {
1204 MOS_RESOURCE osResource; // [in] Pointer to OS Resource
1205 uint32_t width; // [in] Width of Surface
1206 uint32_t height; // [in] Height of Surface
1207 MOS_FORMAT format; // [in] Format of Surface
1208 void *gmmResourceInfo; // [out] GMM resource info
1209 uint16_t memObjCtl; // [in] MOCS value set from CMRT
1210 CmSurfaceState2Dor3DMgr *surfStateMgr;
1211 } CM_HAL_SURFACE2D_UP_ENTRY, *PCM_HAL_SURFACE2D_UP_ENTRY;
1212
1213 typedef struct _CM_HAL_SURFACE_STATE_ENTRY
1214 {
1215 uint32_t surfaceStateWidth;
1216 uint32_t surfaceStateHeight;
1217 } CM_HAL_SURFACE_STATE_ENTRY, *PCM_HAL_SURFACE_STATE_ENTRY;
1218
1219 typedef struct _CM_HAL_VME_ARG_VALUE
1220 {
1221 uint32_t fwRefNum;
1222 uint32_t bwRefNum;
1223 CM_HAL_SURFACE_STATE_ENTRY surfStateParam;
1224 uint32_t curSurface;
1225 // IMPORTANT: in realization, this struct is always followed by ref surfaces array, fw followed by bw
1226 // Please use CmSurfaceVme::GetVmeCmArgSize() to allocate the memory for this structure
1227 }CM_HAL_VME_ARG_VALUE, *PCM_HAL_VME_ARG_VALUE;
1228
findRefInVmeArg(PCM_HAL_VME_ARG_VALUE value)1229 inline uint32_t *findRefInVmeArg(PCM_HAL_VME_ARG_VALUE value)
1230 {
1231 return (uint32_t *)(value+1);
1232 }
1233
findFwRefInVmeArg(PCM_HAL_VME_ARG_VALUE value)1234 inline uint32_t *findFwRefInVmeArg(PCM_HAL_VME_ARG_VALUE value)
1235 {
1236 return (uint32_t *)(value+1);
1237 }
1238
findBwRefInVmeArg(PCM_HAL_VME_ARG_VALUE value)1239 inline uint32_t *findBwRefInVmeArg(PCM_HAL_VME_ARG_VALUE value)
1240 {
1241 return &((uint32_t *)(value+1))[value->fwRefNum];
1242 }
1243
getVmeArgValueSize(PCM_HAL_VME_ARG_VALUE value)1244 inline uint32_t getVmeArgValueSize(PCM_HAL_VME_ARG_VALUE value)
1245 {
1246 return sizeof(CM_HAL_VME_ARG_VALUE) + (value->fwRefNum + value->bwRefNum) * sizeof(uint32_t);
1247 }
1248
getSurfNumFromArgArraySize(uint32_t argArraySize,uint32_t argNum)1249 inline uint32_t getSurfNumFromArgArraySize(uint32_t argArraySize, uint32_t argNum)
1250 {
1251 return (argArraySize - argNum*sizeof(CM_HAL_VME_ARG_VALUE))/sizeof(uint32_t) + argNum; // substract the overhead of the structure to get number of references, then add the currenct surface
1252 }
1253
1254 //------------------------------------------------------------------------------
1255 //| HAL CM 2D Table
1256 //------------------------------------------------------------------------------
1257 class CmSurfaceState2Dor3DMgr;
1258 typedef struct _CM_HAL_SURFACE2D_ENTRY
1259 {
1260 MOS_RESOURCE osResource; // [in] Pointer to OS Resource
1261 uint32_t width; // [in] Width of Surface
1262 uint32_t height; // [in] Height of Surface
1263 MOS_FORMAT format; // [in] Format of Surface
1264 void *gmmResourceInfo; // [out] GMM resource info
1265 uint32_t isAllocatedbyCmrtUmd; // [in] Whether Surface allocated by CMRT
1266 uint32_t surfaceStateWidth; // [in] Width of Surface to be set in surface state
1267 uint32_t surfaceStateHeight; // [in] Height of Surface to be set in surface state
1268 bool readSyncs[MOS_GPU_CONTEXT_MAX]; // [in] Used in on demand sync for each gpu context
1269 CM_HAL_SURFACE2D_SURFACE_STATE_PARAM surfaceStateParam[CM_HAL_MAX_NUM_2D_ALIASES]; // [in] width/height of surface to be used in surface state
1270 MHW_ROTATION rotationFlag;
1271 int32_t chromaSiting;
1272 CM_FRAME_TYPE frameType;
1273 uint16_t memObjCtl; // [in] MOCS value set from CMRT
1274 CmSurfaceState2Dor3DMgr *surfStateMgr;
1275 bool surfStateSet;
1276 } CM_HAL_SURFACE2D_ENTRY, *PCM_HAL_SURFACE2D_ENTRY;
1277
1278 //------------------------------------------------------------------------------
1279 //| HAL CM Buffer Table
1280 //------------------------------------------------------------------------------
1281 typedef struct _CM_HAL_3DRESOURCE_ENTRY
1282 {
1283 MOS_RESOURCE osResource; // [in] Pointer to OS Resource
1284 uint32_t width; // [in] Width of Surface
1285 uint32_t height; // [in] Height of Surface
1286 uint32_t depth; // [in] Depth of Surface
1287 MOS_FORMAT format; // [in] Format of Surface
1288 uint16_t memObjCtl; // [in] MOCS value set from CMRT
1289 CmSurfaceState2Dor3DMgr *surfStateMgr;
1290 } CM_HAL_3DRESOURCE_ENTRY, *PCM_HAL_3DRESOURCE_ENTRY;
1291
1292 //*-----------------------------------------------------------------------------
1293 //| TimeStamp Resource. Used for storing task begin and end timestamps
1294 //*-----------------------------------------------------------------------------
1295 typedef struct _CM_HAL_TS_RESOURCE
1296 {
1297 MOS_RESOURCE osResource; // [in] OS Resource
1298 bool locked; // [in] Locked Flag
1299 uint8_t *data; // [in] Linear Data
1300 } CM_HAL_TS_RESOURCE, *PCM_HAL_TS_RESOURCE;
1301
1302 class FrameTrackerProducer;
1303 struct CM_HAL_HEAP_PARAM
1304 {
1305 uint32_t initialSizeGSH;
1306 uint32_t extendSizeGSH;
1307 FrameTrackerProducer *trackerProducer;
1308 HeapManager::Behavior behaviorGSH;
1309 };
1310
1311 //------------------------------------------------------------------------------
1312 //| HAL CM Struct for a multiple usage mapping from OSResource to BTI states
1313 //------------------------------------------------------------------------------
1314 typedef struct _CM_HAL_MULTI_USE_BTI_ENTRY
1315 {
1316 union
1317 {
1318 struct
1319 {
1320 uint32_t regularSurfIndex : 8;
1321 uint32_t samplerSurfIndex : 8;
1322 uint32_t vmeSurfIndex : 8;
1323 uint32_t sampler8x8SurfIndex : 8;
1324 };
1325 struct
1326 {
1327 uint32_t value;
1328 };
1329 } BTI;
1330
1331 struct
1332 {
1333 void *regularBtiEntryPosition;
1334 void *samplerBtiEntryPosition;
1335 void *vmeBtiEntryPosition;
1336 void *sampler8x8BtiEntryPosition;
1337 } BTITableEntry;
1338 uint32_t nPlaneNumber;
1339 } CM_HAL_MULTI_USE_BTI_ENTRY, *PCM_HAL_MULTI_USE_BTI_ENTRY;
1340
1341 //------------------------------------------------------------------------------
1342 //| HAL CM Struct for a table entry for state buffer
1343 //------------------------------------------------------------------------------
1344 typedef struct _CM_HAL_STATE_BUFFER_ENTRY
1345 {
1346 void *kernelPtr;
1347 uint32_t stateBufferIndex;
1348 CM_STATE_BUFFER_TYPE stateBufferType;
1349 uint32_t stateBufferSize;
1350 uint64_t stateBufferVaPtr;
1351 PRENDERHAL_MEDIA_STATE mediaStatePtr;
1352 } CM_HAL_STATE_BUFFER_ENTRY;
1353
1354 typedef struct _CM_HAL_STATE *PCM_HAL_STATE;
1355
1356 //------------------------------------------------------------------------------
1357 //| HAL CM Struct for a L3 settings
1358 //------------------------------------------------------------------------------
1359 typedef struct CmHalL3Settings
1360 {
1361 bool enableSlm; // Enable SLM cache configuration
1362 bool overrideSettings; // Override cache settings
1363 // Override values
1364 bool l3CachingEnabled;
1365
1366 bool cntlRegOverride;
1367 bool cntlReg2Override;
1368 bool cntlReg3Override;
1369 bool sqcReg1Override;
1370 bool sqcReg4Override;
1371 bool lra1RegOverride;
1372 bool tcCntlRegOverride;
1373 bool allocRegOverride;
1374
1375 unsigned long cntlReg;
1376 unsigned long cntlReg2;
1377 unsigned long cntlReg3;
1378 unsigned long sqcReg1;
1379 unsigned long sqcReg4;
1380 unsigned long lra1Reg;
1381 unsigned long tcCntlReg;
1382 unsigned long allocReg;
1383 } *PCmHalL3Settings;
1384
1385 //------------------------------------------------------------------------------
1386 //| HAL CM Device Param
1387 //------------------------------------------------------------------------------
1388 struct CM_HAL_DEVICE_PARAM
1389 {
1390 uint32_t maxTasks; // [in] Max Tasks
1391 uint32_t maxKernelsPerTask; // [in] Maximum Number of Kernels Per Task
1392 uint32_t maxKernelBinarySize; // [in] Maximum binary size of the kernel
1393 uint32_t maxSamplerTableSize; // [in] Max sampler table size
1394 uint32_t maxBufferTableSize; // [in] Buffer table Size
1395 uint32_t max2DSurfaceUPTableSize; // [in] 2D surfaceUP table Size
1396 uint32_t max2DSurfaceTableSize; // [in] 2D surface table Size
1397 uint32_t max3DSurfaceTableSize; // [in] 3D table Size
1398 uint32_t maxSampler8x8TableSize; // [in] Max Sampler 8x8 table size
1399 uint32_t maxPerThreadScratchSpaceSize; // [in] Max per hw thread scratch space size
1400 uint32_t maxAvsSamplers; // [in] Max Number of AVS Samplers
1401 int32_t maxGshKernelEntries; // [in] Max number of kernel entries in GSH
1402 };
1403 typedef CM_HAL_DEVICE_PARAM *PCM_HAL_DEVICE_PARAM;
1404
1405 //------------------------------------------------------------------------------
1406 //| CM max parallelism information (for EnqueueWithHints)
1407 //------------------------------------------------------------------------------
1408 struct CM_HAL_PARALLELISM_GRAPH_INFO
1409 {
1410 uint32_t maxParallelism;
1411 uint32_t numMaxRepeat;
1412 uint32_t numSteps;
1413 };
1414 typedef CM_HAL_PARALLELISM_GRAPH_INFO *PCM_HAL_PARALLELISM_GRAPH_INFO;
1415
1416 //----------------------------------------------------
1417 //| CM kernel group information (for EnqueueWithHints)
1418 //----------------------------------------------------
1419 struct CM_HAL_KERNEL_GROUP_INFO
1420 {
1421 uint32_t numKernelsFinished;
1422 uint32_t numKernelsInGroup;
1423 uint32_t groupFinished;
1424 uint32_t numStepsInGrp;
1425 uint32_t freqDispatch;
1426 };
1427 typedef CM_HAL_KERNEL_GROUP_INFO *PCM_HAL_KERNEL_GROUP_INFO;
1428
1429 //------------------------------------------------------------------------------
1430 //| CM max hardware threads
1431 //------------------------------------------------------------------------------
1432 struct CM_HAL_MAX_HW_THREAD_VALUES
1433 {
1434 uint32_t userFeatureValue;
1435 uint32_t apiValue;
1436 };
1437
1438 struct CM_HAL_EXEC_VEBOX_TASK_PARAM;
1439 typedef CM_HAL_EXEC_VEBOX_TASK_PARAM *PCM_HAL_EXEC_VEBOX_TASK_PARAM;
1440
1441 //------------------------------------------------------------------------------
1442 //| HAL CM Register DmaCompleteEvent Handle Param
1443 //------------------------------------------------------------------------------
1444 struct CM_HAL_OSSYNC_PARAM
1445 {
1446 HANDLE osSyncEvent; //BB complete Notification
1447 };
1448 typedef CM_HAL_OSSYNC_PARAM *PCM_HAL_OSSYNC_PARAM;
1449
1450 struct CM_HAL_TASK_TIMESTAMP
1451 {
1452 LARGE_INTEGER submitTimeInCpu[CM_MAXIMUM_TASKS]; // [out] The CM task submission time in CPU
1453 uint64_t submitTimeInGpu[CM_MAXIMUM_TASKS]; // [out] The CM task submission time in GPU
1454 };
1455 typedef CM_HAL_TASK_TIMESTAMP *PCM_HAL_TASK_TIMESTAMP;
1456
1457 struct CM_HAL_HINT_TASK_INDEXES
1458 {
1459 uint32_t kernelIndexes[CM_MAX_TASKS_EU_SATURATION]; // [in/out] kernel indexes used for EU saturation
1460 uint32_t dispatchIndexes[CM_MAX_TASKS_EU_SATURATION]; // [in/out] dispatch indexes used for EU saturation
1461 };
1462
1463 //-------------------------------
1464 //| CM HW GT system info
1465 //-------------------------------
1466 struct CM_GT_SYSTEM_INFO
1467 {
1468 uint32_t numMaxSlicesSupported;
1469 uint32_t numMaxSubSlicesSupported;
1470 GT_SLICE_INFO sliceInfo[GT_MAX_SLICE];
1471 bool isSliceInfoValid;
1472 };
1473 typedef CM_GT_SYSTEM_INFO *PCM_GT_SYSTEM_INFO;
1474
1475 //------------------------------------------------------------------------------
1476 //| HAL CM State
1477 //------------------------------------------------------------------------------
1478 class CmExecutionAdv;
1479 typedef struct _CM_HAL_STATE
1480 {
1481 // Internal/private structures
1482 PLATFORM platform;
1483 MEDIA_FEATURE_TABLE *skuTable;
1484 MEDIA_WA_TABLE *waTable;
1485 PMOS_INTERFACE osInterface; // OS Interface [*]
1486 PRENDERHAL_INTERFACE_LEGACY renderHal; // Render Engine Interface [*]
1487 MhwVeboxInterface *veboxInterface; // Vebox Interface
1488 MhwCpInterface* cpInterface; // Cp Interface
1489 PMHW_BATCH_BUFFER batchBuffers; // Array of Batch Buffers [*]
1490 PCM_HAL_TASK_PARAM taskParam; // Pointer to Task Param [*]
1491 PCM_HAL_TASK_TIMESTAMP taskTimeStamp; // Pointer to Task Time Stamp
1492 CM_HAL_TS_RESOURCE renderTimeStampResource; // Resource to store timestamps [*]
1493 CM_HAL_TS_RESOURCE veboxTimeStampResource; // Resource to store timestamps [*]
1494 CM_HAL_TS_RESOURCE sipResource; // Resource to store debug info [*]
1495 MOS_RESOURCE csrResource; // Resource to store CSR info
1496 void *tableMemories; // Single Memory for all lookup and temp tables [*]
1497 CM_HAL_HINT_TASK_INDEXES hintIndexes; // Indexes for EU Saturation API
1498 bool requestSingleSlice; // Requests single slice for life of CM device
1499 bool midThreadPreemptionDisabled; // set the flag to indicate to disable the midthread preemption
1500 bool kernelDebugEnabled; // set the flag to indicate to enable SIP debugging
1501 PCMLOOKUP_ENTRY surf2DTable; // Surface registration lookup entries
1502 PCM_HAL_SURFACE2D_ENTRY umdSurf2DTable; // Surface2D entries used by CMRT@Driver
1503 PCM_HAL_BUFFER_ENTRY bufferTable; // Buffer registration table
1504 PCM_HAL_SURFACE2D_UP_ENTRY surf2DUPTable; // Buffer registration table
1505 PCM_HAL_3DRESOURCE_ENTRY surf3DTable; // 3D surface registration table
1506 PMHW_SAMPLER_STATE_PARAM samplerTable; // Sampler table
1507 CM_SAMPLER_STATISTICS samplerStatistics;
1508 PCM_HAL_SAMPLER_8X8_ENTRY sampler8x8Table; // Sampler 8x8 table
1509 char *taskStatusTable; // Table for task status
1510 int32_t currentTaskEntry; // Current task status entry id
1511 PCM_HAL_MULTI_USE_BTI_ENTRY bti2DIndexTable; // Table to store Used 2D binding indexes (temporary)
1512 PCM_HAL_MULTI_USE_BTI_ENTRY bti2DUPIndexTable; // Table to store Used 2D binding indexes (temporary)
1513 PCM_HAL_MULTI_USE_BTI_ENTRY bti3DIndexTable; // Table to store Used 3D binding indexes (temporary)
1514 PCM_HAL_MULTI_USE_BTI_ENTRY btiBufferIndexTable; // Table to store Buffer Binding indexes (temporary)
1515 char *samplerIndexTable; // Table to store Used Sampler indexes (temporary)
1516 char *vmeIndexTable; // Table to store Used VME indexes (temporary)
1517 char *sampler8x8IndexTable; // Table to store Used Sampler8x8 indexes (temporary)
1518
1519 CMSURFACE_REG_TABLE surfaceRegTable; // Surface registration table
1520 CM_HAL_DEVICE_PARAM cmDeviceParam; // Device Param
1521 RENDERHAL_KRN_ALLOCATION kernelParamsRenderHal; // RenderHal Kernel Setup
1522 MHW_KERNEL_PARAM kernelParamsMhw; // MHW Kernel setup
1523 int32_t numBatchBuffers; // Number of batch buffers
1524 uint32_t dummyArg; // Dummy Argument for no argument kernel
1525 CM_HAL_MAX_HW_THREAD_VALUES maxHWThreadValues; // Maximum number of hardware threads values
1526 MHW_VFE_SCOREBOARD scoreboardParams; // Scoreboard Parameters
1527 MHW_WALKER_PARAMS walkerParams; // Walker Parameters
1528 void *resourceList; // List of resource handles (temporary) NOTE: Only use this for enqueue
1529
1530 bool nullHwRenderCm; // Null rendering flag for Cm function
1531 HMODULE hLibModule; // module handle pointing to the dynamically opened library
1532
1533 bool dshEnabled; // Enable Dynamic State Heap
1534 uint32_t dshKernelCacheHit; // Kernel Cache hit count
1535 uint32_t dshKernelCacheMiss; // Kernel Cache miss count
1536
1537 RENDERHAL_SURFACE cmVeboxSurfaces[CM_HAL_MAX_VEBOX_SURF_NUM]; // cm vebox surfaces
1538 CM_VEBOX_SETTINGS cmVeboxSettings; // cm vebox settings
1539 RENDERHAL_SURFACE cmVebeboxParamSurf;
1540 uint32_t cmDebugBTIndex; // cm Debug BT index
1541
1542 void *drmVMap; //for libdrm's patched function "drm_intel_bo_from_vmapping"
1543
1544 CM_POWER_OPTION powerOption; // Power option
1545 bool euSaturationEnabled; // EU saturation enabled
1546
1547 int32_t kernelNumInGsh; // current kernel number in GSH
1548 int32_t *totalKernelSize; // Total size table of every kernel in GSH kernel entries
1549
1550 uint32_t surfaceArraySize; // size of surface array used for 2D surface alias
1551
1552 bool vtuneProfilerOn; // Vtune profiling on or not
1553 bool cbbEnabled; // if conditional batch buffer enabled
1554
1555 uint32_t currentPerfTagIndex[MAX_COMBINE_NUM_IN_PERFTAG];
1556 std::map<std::string, int> *perfTagIndexMap[MAX_COMBINE_NUM_IN_PERFTAG]; // mapping from kernel name to perf tag
1557 MediaPerfProfiler *perfProfiler; // unified media perf profiler
1558
1559 PCM_HAL_GENERIC cmHalInterface; // pointer to genX interfaces
1560
1561 std::map< void *, CM_HAL_STATE_BUFFER_ENTRY > *state_buffer_list_ptr; // table of bounded state buffer and kernel ptr
1562
1563 CmHalL3Settings l3Settings;
1564
1565 bool useNewSamplerHeap;
1566
1567 bool svmBufferUsed;
1568
1569 bool statelessBufferUsed;
1570
1571 CMRT_UMD::CSync *criticalSectionDSH;
1572
1573 uint32_t tsFrequency;
1574
1575 bool forceKernelReload;
1576
1577 CmExecutionAdv *advExecutor = nullptr;
1578
1579 bool refactor = false;
1580
1581 bool requestCustomGpuContext = false;
1582
1583 bool veboxDisabled = false;
1584
1585 bool syncOnResource = false;
1586
1587 // Pointer to the buffer for sychronizing tasks in a queue.
1588 MOS_RESOURCE *syncBuffer = nullptr;
1589
1590 //********************************************************************************
1591 // Export Interface methods called by CMRT@UMD <START>
1592 //********************************************************************************
1593 MOS_STATUS (* pfnCmAllocate)
1594 ( PCM_HAL_STATE state);
1595
1596 MOS_STATUS (* pfnGetMaxValues)
1597 ( PCM_HAL_STATE state,
1598 PCM_HAL_MAX_VALUES maxValues);
1599
1600 MOS_STATUS (* pfnGetMaxValuesEx)
1601 ( PCM_HAL_STATE state,
1602 PCM_HAL_MAX_VALUES_EX maxValuesEx);
1603
1604 MOS_STATUS (* pfnExecuteTask)
1605 ( PCM_HAL_STATE state,
1606 PCM_HAL_EXEC_TASK_PARAM param);
1607
1608 MOS_STATUS (* pfnExecuteGroupTask)
1609 ( PCM_HAL_STATE state,
1610 PCM_HAL_EXEC_GROUP_TASK_PARAM param);
1611
1612 MOS_STATUS (* pfnExecuteVeboxTask)
1613 ( PCM_HAL_STATE state,
1614 PCM_HAL_EXEC_VEBOX_TASK_PARAM param);
1615
1616 MOS_STATUS (* pfnExecuteHintsTask)
1617 ( PCM_HAL_STATE state,
1618 PCM_HAL_EXEC_HINTS_TASK_PARAM param);
1619
1620 MOS_STATUS (* pfnQueryTask)
1621 ( PCM_HAL_STATE state,
1622 PCM_HAL_QUERY_TASK_PARAM param);
1623
1624 MOS_STATUS (* pfnRegisterUMDNotifyEventHandle)
1625 ( PCM_HAL_STATE state,
1626 PCM_HAL_OSSYNC_PARAM param);
1627
1628 MOS_STATUS (* pfnRegisterSampler)
1629 ( PCM_HAL_STATE state,
1630 PCM_HAL_SAMPLER_PARAM param);
1631
1632 MOS_STATUS (* pfnUnRegisterSampler)
1633 ( PCM_HAL_STATE state,
1634 uint32_t handle);
1635
1636 MOS_STATUS (* pfnRegisterSampler8x8)
1637 ( PCM_HAL_STATE state,
1638 PCM_HAL_SAMPLER_8X8_PARAM param);
1639
1640 MOS_STATUS (* pfnUnRegisterSampler8x8)
1641 ( PCM_HAL_STATE state,
1642 uint32_t handle);
1643
1644 MOS_STATUS (*pfnAllocateBuffer)
1645 ( PCM_HAL_STATE state,
1646 PCM_HAL_BUFFER_PARAM param);
1647
1648 MOS_STATUS (*pfnFreeBuffer)
1649 ( PCM_HAL_STATE state,
1650 uint32_t handle);
1651
1652 MOS_STATUS (*pfnLockBuffer)
1653 ( PCM_HAL_STATE state,
1654 PCM_HAL_BUFFER_PARAM param);
1655
1656 MOS_STATUS (*pfnUnlockBuffer)
1657 ( PCM_HAL_STATE state,
1658 PCM_HAL_BUFFER_PARAM param);
1659
1660 MOS_STATUS (*pfnAllocateSurface2DUP)
1661 ( PCM_HAL_STATE state,
1662 PCM_HAL_SURFACE2D_UP_PARAM param);
1663
1664 MOS_STATUS (*pfnFreeSurface2DUP)
1665 ( PCM_HAL_STATE state,
1666 uint32_t handle);
1667
1668 MOS_STATUS (*pfnGetSurface2DPitchAndSize)
1669 ( PCM_HAL_STATE state,
1670 PCM_HAL_SURFACE2D_UP_PARAM param);
1671
1672 MOS_STATUS (*pfnAllocate3DResource)
1673 ( PCM_HAL_STATE state,
1674 PCM_HAL_3DRESOURCE_PARAM param);
1675
1676 MOS_STATUS (*pfnFree3DResource)
1677 ( PCM_HAL_STATE state,
1678 uint32_t handle);
1679
1680 MOS_STATUS (*pfnLock3DResource)
1681 ( PCM_HAL_STATE state,
1682 PCM_HAL_3DRESOURCE_PARAM param);
1683
1684 MOS_STATUS (*pfnUnlock3DResource)
1685 ( PCM_HAL_STATE state,
1686 PCM_HAL_3DRESOURCE_PARAM param);
1687
1688 MOS_STATUS (*pfnAllocateSurface2D)
1689 ( PCM_HAL_STATE state,
1690 PCM_HAL_SURFACE2D_PARAM param);
1691
1692 MOS_STATUS (*pfnUpdateSurface2D)
1693 ( PCM_HAL_STATE state,
1694 PCM_HAL_SURFACE2D_PARAM param);
1695
1696 MOS_STATUS (*pfnUpdateBuffer)
1697 ( PCM_HAL_STATE state,
1698 PCM_HAL_BUFFER_PARAM param);
1699
1700 MOS_STATUS (*pfnFreeSurface2D)
1701 ( PCM_HAL_STATE state,
1702 uint32_t handle);
1703
1704 MOS_STATUS (*pfnLock2DResource)
1705 ( PCM_HAL_STATE state,
1706 PCM_HAL_SURFACE2D_LOCK_UNLOCK_PARAM param);
1707
1708 MOS_STATUS (*pfnUnlock2DResource)
1709 ( PCM_HAL_STATE state,
1710 PCM_HAL_SURFACE2D_LOCK_UNLOCK_PARAM param);
1711
1712 MOS_STATUS (*pfnGetSurface2DTileYPitch)
1713 ( PCM_HAL_STATE state,
1714 PCM_HAL_SURFACE2D_PARAM param);
1715
1716 MOS_STATUS (*pfnSetCaps)
1717 ( PCM_HAL_STATE state,
1718 PCM_HAL_MAX_SET_CAPS_PARAM param);
1719
1720 MOS_STATUS (*pfnGetGPUCurrentFrequency)
1721 ( PCM_HAL_STATE state,
1722 uint32_t *gpucurrentFreq);
1723
1724 MOS_STATUS (*pfnSet2DSurfaceStateParam)
1725 ( PCM_HAL_STATE state,
1726 PCM_HAL_SURFACE2D_SURFACE_STATE_PARAM param,
1727 uint32_t aliasIndex,
1728 uint32_t handle);
1729
1730 MOS_STATUS (*pfnSetBufferSurfaceStatePara) (
1731 PCM_HAL_STATE state,
1732 PCM_HAL_BUFFER_SURFACE_STATE_PARAM param);
1733
1734 MOS_STATUS (*pfnSetSurfaceMOCS) (
1735 PCM_HAL_STATE state,
1736 uint32_t hanlde,
1737 uint16_t mocs,
1738 uint32_t argKind);
1739
1740 MOS_STATUS (*pfnSetPowerOption)
1741 ( PCM_HAL_STATE state,
1742 PCM_POWER_OPTION powerOption);
1743
1744 //********************************************************************************
1745 // Export Interface methods called by CMRT@UMD <END>
1746 //********************************************************************************
1747
1748 //********************************************************************************
1749 // Internal interface methods called by CM HAL only <START>
1750 //********************************************************************************
1751 int32_t (*pfnGetTaskSyncLocation)
1752 ( PCM_HAL_STATE state,
1753 int32_t taskId);
1754
1755 MOS_STATUS (*pfnGetGpuTime)
1756 ( PCM_HAL_STATE state,
1757 uint64_t *gpuTime);
1758
1759 MOS_STATUS (*pfnConvertToQPCTime)
1760 ( uint64_t nanoseconds,
1761 LARGE_INTEGER *qpcTime );
1762
1763 MOS_STATUS (*pfnGetGlobalTime)
1764 ( LARGE_INTEGER *globalTime);
1765
1766 MOS_STATUS (*pfnSendMediaWalkerState)
1767 ( PCM_HAL_STATE state,
1768 PCM_HAL_KERNEL_PARAM kernelParam,
1769 PMOS_COMMAND_BUFFER cmdBuffer);
1770
1771 MOS_STATUS (*pfnSendGpGpuWalkerState)
1772 ( PCM_HAL_STATE state,
1773 PCM_HAL_KERNEL_PARAM kernelParam,
1774 PMOS_COMMAND_BUFFER cmdBuffer);
1775
1776 MOS_STATUS (*pfnUpdatePowerOption)
1777 ( PCM_HAL_STATE state,
1778 PCM_POWER_OPTION powerOption);
1779
1780 MOS_STATUS (*pfnGetSipBinary)
1781 ( PCM_HAL_STATE state);
1782
1783 MOS_STATUS(*pfnGetPlatformInfo)
1784 ( PCM_HAL_STATE state,
1785 PCM_PLATFORM_INFO platformInfo,
1786 bool euSaturated);
1787
1788 MOS_STATUS(*pfnGetGTSystemInfo)
1789 ( PCM_HAL_STATE state,
1790 PCM_GT_SYSTEM_INFO systemInfo);
1791
1792 MOS_STATUS (*pfnSetSurfaceReadFlag)
1793 ( PCM_HAL_STATE state,
1794 uint32_t handle,
1795 bool readSync,
1796 MOS_GPU_CONTEXT gpuContext);
1797
1798 MOS_STATUS (*pfnSetVtuneProfilingFlag)
1799 ( PCM_HAL_STATE state,
1800 bool vtuneOn);
1801
1802 MOS_STATUS(*pfnReferenceCommandBuffer)
1803 ( PMOS_RESOURCE osResource,
1804 void **cmdBuffer);
1805
1806 MOS_STATUS(*pfnSetCommandBufferResource)
1807 ( PMOS_RESOURCE osResource,
1808 void **cmdBuffer);
1809
1810 MOS_STATUS(*pfnEnableTurboBoost)
1811 ( PCM_HAL_STATE state);
1812
1813 MOS_STATUS(*pfnSetCompressionMode)
1814 (
1815 PCM_HAL_STATE state,
1816 CM_HAL_SURFACE2D_COMPRESSIOM_PARAM MmcParam
1817 );
1818
1819 bool (*pfnIsWASLMinL3Cache)( );
1820
1821 MOS_STATUS( *pfnDeleteFromStateBufferList )
1822 (
1823 PCM_HAL_STATE state,
1824 void *kernelPtr );
1825
1826 PRENDERHAL_MEDIA_STATE( *pfnGetMediaStatePtrForKernel )
1827 (
1828 PCM_HAL_STATE state,
1829 void *kernelPtr );
1830
1831 uint64_t( *pfnGetStateBufferVAPtrForSurfaceIndex )
1832 (
1833 PCM_HAL_STATE state,
1834 uint32_t surfIndex );
1835
1836 PRENDERHAL_MEDIA_STATE( *pfnGetMediaStatePtrForSurfaceIndex )
1837 (
1838 PCM_HAL_STATE state,
1839 uint32_t surfIndex );
1840
1841 uint64_t( *pfnGetStateBufferVAPtrForMediaStatePtr )
1842 (
1843 PCM_HAL_STATE state,
1844 PRENDERHAL_MEDIA_STATE mediaStatePtr );
1845
1846 uint32_t( *pfnGetStateBufferSizeForKernel )
1847 (
1848 PCM_HAL_STATE state,
1849 void *kernelPtr );
1850
1851 CM_STATE_BUFFER_TYPE( *pfnGetStateBufferTypeForKernel )
1852 (
1853 PCM_HAL_STATE state,
1854 void *kernelPtr );
1855
1856 MOS_STATUS(*pfnCreateGPUContext)
1857 (
1858 PCM_HAL_STATE state,
1859 MOS_GPU_CONTEXT gpuContext,
1860 MOS_GPU_NODE gpuNode,
1861 PMOS_GPUCTX_CREATOPTIONS mosCreateOption);
1862
1863 GPU_CONTEXT_HANDLE (*pfnCreateGpuComputeContext) (
1864 PCM_HAL_STATE state,
1865 MOS_GPUCTX_CREATOPTIONS *mosCreateOption);
1866
1867 MOS_STATUS(*pfnGetGfxMapFilter) (
1868 uint32_t filter,
1869 MHW_GFX3DSTATE_MAPFILTER *pGfxFilter);
1870
1871 MOS_STATUS(*pfnGetGfxTextAddress) (
1872 uint32_t addressMode,
1873 MHW_GFX3DSTATE_TEXCOORDMODE *gfxAddress);
1874
1875 MOS_STATUS(*pfnDecompressSurface) (
1876 PCM_HAL_STATE state,
1877 PCM_HAL_KERNEL_ARG_PARAM argParam,
1878 uint32_t threadIndex);
1879
1880 MOS_STATUS (*pfnSetOsResourceFromDdi)(
1881 PMOS_RESOURCE resource,
1882 PMOS_RESOURCE osResource,
1883 uint32_t mipSlice);
1884
1885 int32_t (*pfnSyncKernel)(
1886 PCM_HAL_STATE state,
1887 uint32_t sync);
1888
1889 MOS_STATUS (*pfnSurfaceSync)(
1890 PCM_HAL_STATE pState,
1891 PMOS_SURFACE pSurface,
1892 bool bReadSync);
1893
1894 MOS_STATUS (*pfnSyncOnResource)(
1895 PCM_HAL_STATE state,
1896 PMOS_SURFACE surface,
1897 bool isWrite);
1898
1899 MOS_STATUS (*pfnCreateSipKernel)(
1900 PCM_HAL_STATE state,
1901 CmISH *cmISH);
1902
1903 //*-----------------------------------------------------------------------------
1904 //| Purpose: Selects the required stream index and sets the correct GPU context for further function calls.
1905 //| Returns: Previous stream index.
1906 //| Note: On Linux, context handle is used exclusively to retrieve the correct GPU context. Stream index is used on other operating systems.
1907 //*-----------------------------------------------------------------------------
1908 uint32_t (*pfnSetGpuContext)(PCM_HAL_STATE halState,
1909 MOS_GPU_CONTEXT contextName,
1910 uint32_t streamIndex,
1911 GPU_CONTEXT_HANDLE contextHandle);
1912
1913 MOS_STATUS (*pfnUpdateTrackerResource)
1914 (
1915 PCM_HAL_STATE state,
1916 PMOS_COMMAND_BUFFER cmdBuffer,
1917 uint32_t tag);
1918
1919 //*-----------------------------------------------------------------------------
1920 //| Purpose: Selects the buffer for synchronizing tasks in a CmQueue.
1921 //| Returns: Result of this operation.
1922 //| Note: Synchronization buffer is most useful on Linux. It's not required on other operating systems.
1923 //*-----------------------------------------------------------------------------
1924 MOS_STATUS (*pfnSelectSyncBuffer) (PCM_HAL_STATE state, uint32_t bufferIdx);
1925
1926 //********************************************************************************
1927 // Internal interface methods called by CM HAL only <END>
1928 //********************************************************************************
1929
1930 #if (_DEBUG || _RELEASE_INTERNAL)
1931 bool dumpCommandBuffer; //flag to enable command buffer dump
1932 bool dumpCurbeData; //flag to enable curbe data dump
1933 bool dumpSurfaceContent; //flag to enable surface content dump
1934 bool dumpSurfaceState; //flag to enable surface state dump
1935 bool enableCMDDumpTimeStamp; //flag to enable command buffer dump time stamp
1936 bool enableSurfaceStateDumpTimeStamp; //flag to enable surface state dump time stamp
1937 bool dumpIDData; //flag to enable surface state dump time stamp
1938 bool enableIDDumpTimeStamp; //flag to enable surface state dump time stamp
1939
1940 int32_t(*pfnInitDumpCommandBuffer)
1941 (
1942 PCM_HAL_STATE state);
1943 int32_t(*pfnDumpCommadBuffer)
1944 (
1945 PCM_HAL_STATE state,
1946 PMOS_COMMAND_BUFFER cmdBuffer,
1947 int offsetSurfaceState,
1948 size_t sizeOfSurfaceState);
1949
1950 int32_t(*pfnInitDumpSurfaceState)
1951 (
1952 PCM_HAL_STATE state);
1953 int32_t(*pfnDumpSurfaceState)
1954 (
1955 PCM_HAL_STATE state,
1956 int offsetSurfaceState,
1957 size_t sizeOfSurfaceState);
1958
1959 #endif //(_DEBUG || _RELEASE_INTERNAL)
1960
1961 MOS_STATUS(*pfnDSHUnregisterKernel)
1962 (
1963 PCM_HAL_STATE state,
1964 uint64_t kernelId);
1965
1966 uint32_t (*pfnRegisterStream) (PCM_HAL_STATE state);
1967
1968 void(*pfnUnRegisterStream)
1969 (
1970 uint32_t streamIndex,
1971 PCM_HAL_STATE state);
1972
1973 } CM_HAL_STATE, *PCM_HAL_STATE;
1974
1975 typedef struct _CM_HAL_MI_REG_OFFSETS
1976 {
1977 uint32_t timeStampOffset;
1978 uint32_t gprOffset;
1979 } CM_HAL_MI_REG_OFFSETS, *PCM_HAL_MI_REG_OFFSETS;
1980
1981 //*-----------------------------------------------------------------------------
1982 //| HAL CM Index Param
1983 //| Used for temporarily storing indices count used
1984 //*-----------------------------------------------------------------------------
1985 struct CM_HAL_INDEX_PARAM
1986 {
1987 uint32_t samplerIndexCount; // [in] sampler indices used
1988 uint32_t vmeIndexCount; // [in] VME indices used
1989 uint32_t sampler8x8IndexCount; // [in] Sampler8x8 indices used
1990 uint32_t btArray[8]; // [in] 256 indexes
1991 };
1992 typedef CM_HAL_INDEX_PARAM *PCM_HAL_INDEX_PARAM;
1993
1994 //------------------------------------------------------------------------------
1995 //| Functions
1996 //------------------------------------------------------------------------------
1997
1998 // inline functions
1999 //*-----------------------------------------------------------------------------
2000 //| Purpose: Get a New Task ID for the new task. If not found, return error
2001 //| Returns: Result of the operation
2002 //*-----------------------------------------------------------------------------
HalCm_GetNewTaskId(PCM_HAL_STATE state,int32_t * piIndex)2003 __inline MOS_STATUS HalCm_GetNewTaskId(
2004 PCM_HAL_STATE state, // [in] Pointer to HAL CM State
2005 int32_t *piIndex) // [out] Pointer to Task Index
2006 {
2007 uint32_t i, j;
2008 uint32_t maxTasks;
2009
2010 i = state->currentTaskEntry;
2011 maxTasks = state->cmDeviceParam.maxTasks;
2012
2013 for (j = maxTasks; j > 0; j--, i = (i + 1) % maxTasks)
2014 {
2015 if (state->taskStatusTable[i] == CM_INVALID_INDEX)
2016 {
2017 *piIndex = i;
2018 state->currentTaskEntry = (i + 1) % maxTasks;
2019 return MOS_STATUS_SUCCESS;
2020 }
2021 }
2022
2023 // Not found
2024 CM_ASSERTMESSAGE("Unable to find a free slot for Task.");
2025 return MOS_STATUS_UNKNOWN;
2026 }
2027
2028 MOS_STATUS HalCm_Create(
2029 PMOS_CONTEXT osDriverContext,
2030 PCM_HAL_CREATE_PARAM cmCreateParam,
2031 PCM_HAL_STATE *cmState);
2032
2033 void HalCm_Destroy(
2034 PCM_HAL_STATE state);
2035
2036 void HalCm_GetUserFeatureSettings(
2037 PCM_HAL_STATE state);
2038
2039 MOS_STATUS HalCm_GetSurfaceDetails(
2040 PCM_HAL_STATE state,
2041 PCM_HAL_INDEX_PARAM indexParam,
2042 uint32_t btindex,
2043 MOS_SURFACE& mosSurface,
2044 int16_t globalSurface,
2045 PRENDERHAL_SURFACE_STATE_ENTRY surfaceEntry,
2046 uint32_t tempPlaneIndex,
2047 RENDERHAL_SURFACE_STATE_PARAMS surfaceParam,
2048 CM_HAL_KERNEL_ARG_KIND argKind);
2049
2050 MOS_STATUS HalCm_AllocateTsResource(
2051 PCM_HAL_STATE state);
2052
2053 MOS_STATUS HalCm_InitializeDynamicStateHeaps(
2054 PCM_HAL_STATE state,
2055 CM_HAL_HEAP_PARAM *heapParam);
2056
2057 MOS_STATUS HalCm_AllocateTrackerResource(
2058 PCM_HAL_STATE state);
2059
2060 MOS_STATUS HalCm_AllocateTables(
2061 PCM_HAL_STATE state);
2062
2063 MOS_STATUS HalCm_Allocate(
2064 PCM_HAL_STATE state);
2065
2066 MOS_STATUS HalCm_SetupSipSurfaceState(
2067 PCM_HAL_STATE state,
2068 PCM_HAL_INDEX_PARAM indexParam,
2069 int32_t bindingTable);
2070
2071 //===============<Below are Os-dependent Private/Non-DDI Functions>============================================
2072
2073 void HalCm_OsInitInterface(
2074 PCM_HAL_STATE cmState);
2075
2076 MOS_STATUS HalCm_GetSurfaceAndRegister(
2077 PCM_HAL_STATE state,
2078 PRENDERHAL_SURFACE renderHalSurface,
2079 CM_HAL_KERNEL_ARG_KIND surfKind,
2080 uint32_t index,
2081 bool pixelPitch);
2082
2083 MOS_STATUS HalCm_SendMediaWalkerState(
2084 PCM_HAL_STATE state,
2085 PCM_HAL_KERNEL_PARAM kernelParam,
2086 PMOS_COMMAND_BUFFER cmdBuffer);
2087
2088 MOS_STATUS HalCm_SendGpGpuWalkerState(
2089 PCM_HAL_STATE state,
2090 PCM_HAL_KERNEL_PARAM kernelParam,
2091 PMOS_COMMAND_BUFFER cmdBuffer);
2092
2093 MOS_STATUS HalCm_SetOsResourceFromDdi(
2094 PMOS_RESOURCE resource,
2095 PMOS_RESOURCE osResource,
2096 uint32_t mipSlice = 0);
2097
2098 MOS_STATUS HalCm_GetSurface2DPitchAndSize(
2099 PCM_HAL_STATE state,
2100 PCM_HAL_SURFACE2D_UP_PARAM param);
2101
2102 MOS_STATUS HalCm_GetGPUCurrentFrequency(
2103 PCM_HAL_STATE state,
2104 uint32_t *currentFreq);
2105
2106 MOS_STATUS HalCm_RegisterUMDNotifyEventHandle(
2107 PCM_HAL_STATE state,
2108 PCM_HAL_OSSYNC_PARAM syncParam);
2109
2110 MOS_STATUS HalCm_GetGpuTime(
2111 PCM_HAL_STATE state,
2112 uint64_t *gpuTime);
2113
2114 uint32_t HalCm_RegisterStream(
2115 PCM_HAL_STATE state);
2116
2117 void HalCm_UnRegisterStream(
2118 uint32_t streamIndex,
2119 PCM_HAL_STATE state);
2120
2121 MOS_STATUS HalCm_GetSipBinary(
2122 PCM_HAL_STATE state);
2123
2124 MOS_STATUS HalCm_CreateSipKernel(
2125 PCM_HAL_STATE state,
2126 CmISH *cmISH);
2127
2128 //===============<Below are Os-non-dependent Private/Non-DDI Functions>=========================================
2129
2130 uint32_t HalCm_GetFreeBindingIndex(
2131 PCM_HAL_STATE state,
2132 PCM_HAL_INDEX_PARAM indexParam,
2133 uint32_t count);
2134
2135 void HalCm_PreSetBindingIndex(
2136 PCM_HAL_INDEX_PARAM indexParam,
2137 uint32_t start,
2138 uint32_t end);
2139
2140 MOS_STATUS HalCm_Setup2DSurfaceStateWithBTIndex(
2141 PCM_HAL_STATE state,
2142 int32_t bindingTable,
2143 uint32_t surfIndex,
2144 uint32_t btIndex,
2145 bool pixelPitch);
2146
2147 MOS_STATUS HalCm_SetupBufferSurfaceStateWithBTIndex(
2148 PCM_HAL_STATE state,
2149 int32_t bindingTable,
2150 uint32_t surfIndex,
2151 uint32_t btIndex,
2152 bool pixelPitch);
2153
2154 MOS_STATUS HalCm_Setup2DSurfaceUPStateWithBTIndex(
2155 PCM_HAL_STATE state,
2156 int32_t bindingTable,
2157 uint32_t surfIndex,
2158 uint32_t btIndex,
2159 bool pixelPitch);
2160
2161 MOS_STATUS HalCm_SetupSampler8x8SurfaceStateWithBTIndex(
2162 PCM_HAL_STATE state,
2163 int32_t bindingTable,
2164 uint32_t surfIndex,
2165 uint32_t btIndex,
2166 bool pixelPitch,
2167 CM_HAL_KERNEL_ARG_KIND kind,
2168 uint32_t addressControl );
2169
2170 MOS_STATUS HalCm_Setup3DSurfaceStateWithBTIndex(
2171 PCM_HAL_STATE state,
2172 int32_t bindingTable,
2173 uint32_t surfIndex,
2174 uint32_t btIndex);
2175
2176 MOS_STATUS HalCm_SyncOnResource(
2177 PCM_HAL_STATE state,
2178 PMOS_SURFACE surface,
2179 bool isWrite);
2180
2181 void HalCm_OsResource_Unreference(
2182 PMOS_RESOURCE osResource);
2183
2184 void HalCm_OsResource_Reference(
2185 PMOS_RESOURCE osResource);
2186
2187 MOS_STATUS HalCm_SetSurfaceReadFlag(
2188 PCM_HAL_STATE state,
2189 uint32_t handle,
2190 MOS_GPU_CONTEXT gpuContext);
2191
2192 MOS_STATUS HalCm_SetVtuneProfilingFlag(
2193 PCM_HAL_STATE state,
2194 bool vtuneOn);
2195
2196 #if (_DEBUG || _RELEASE_INTERNAL)
2197 int32_t HalCm_InitDumpCommandBuffer(
2198 PCM_HAL_STATE state);
2199
2200 int32_t HalCm_DumpCommadBuffer(
2201 PCM_HAL_STATE state,
2202 PMOS_COMMAND_BUFFER cmdBuffer,
2203 int offsetSurfaceState,
2204 size_t sizeOfSurfaceState);
2205 #endif //(_DEBUG || _RELEASE_INTERNAL)
2206
2207 MOS_STATUS HalCm_Convert_RENDERHAL_SURFACE_To_MHW_VEBOX_SURFACE(
2208 PRENDERHAL_SURFACE renderHalSurface,
2209 PMHW_VEBOX_SURFACE_PARAMS mhwVeboxSurface);
2210
2211 bool HalCm_IsCbbEnabled(
2212 PCM_HAL_STATE state);
2213
2214 int32_t HalCm_SyncKernel(
2215 PCM_HAL_STATE state,
2216 uint32_t sync);
2217
2218 MOS_STATUS HalCm_GetGfxTextAddress(
2219 uint32_t addressMode,
2220 MHW_GFX3DSTATE_TEXCOORDMODE *gfxAddress);
2221
2222 MOS_STATUS HalCm_GetGfxMapFilter(
2223 uint32_t filterMode,
2224 MHW_GFX3DSTATE_MAPFILTER *gfxFilter);
2225
2226 MOS_STATUS HalCm_Unlock2DResource(
2227 PCM_HAL_STATE state,
2228 PCM_HAL_SURFACE2D_LOCK_UNLOCK_PARAM param);
2229
2230 MOS_STATUS HalCm_Lock2DResource(
2231 PCM_HAL_STATE state,
2232 PCM_HAL_SURFACE2D_LOCK_UNLOCK_PARAM param);
2233
2234 int32_t HalCm_GetTaskSyncLocation(
2235 PCM_HAL_STATE state,
2236 int32_t taskId);
2237
2238 MOS_STATUS HalCm_SetL3Cache(
2239 const L3ConfigRegisterValues *l3Values,
2240 PCmHalL3Settings cmHalL3Cache );
2241
2242 MOS_STATUS HalCm_AllocateSipResource(PCM_HAL_STATE state);
2243
2244 MOS_STATUS HalCm_AllocateCSRResource(PCM_HAL_STATE state);
2245
2246 MOS_STATUS HalCm_OsAddArtifactConditionalPipeControl(
2247 PCM_HAL_MI_REG_OFFSETS offsets,
2248 PCM_HAL_STATE state,
2249 PMOS_COMMAND_BUFFER cmdBuffer,
2250 int32_t syncOffset,
2251 PMHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS conditionalParams,
2252 uint32_t trackerTag);
2253
2254 //!
2255 //! \brief Get the number of command buffers according to the max task number
2256 //! \details Get the number of command buffers according to the max task number
2257 //! the returned number will be passed to pfnCreateGpuContext()
2258 //! \param [in] osInterface
2259 //! pointer to OS interface
2260 //! \param [in] maxTaskNumber
2261 //! max number of task to support
2262 //! \return uint32_t
2263 //!
2264 uint32_t HalCm_GetNumCmdBuffers(PMOS_INTERFACE osInterface, uint32_t maxTaskNumber);
2265
2266 void HalCm_GetLegacyRenderHalL3Setting( CmHalL3Settings *l3SettingsPtr, RENDERHAL_L3_CACHE_SETTINGS *l3SettingsLegacyPtr );
2267
2268 MOS_STATUS HalCm_GetNumKernelsPerGroup(
2269 uint8_t hintsBits,
2270 uint32_t numKernels,
2271 uint32_t *numKernelsPerGroup,
2272 uint32_t *numKernelGroups,
2273 uint32_t *remapKernelToGroup,
2274 uint32_t *pRemapGroupToKernel
2275 );
2276
2277 MOS_STATUS HalCm_GetParallelGraphInfo(
2278 uint32_t maximum,
2279 uint32_t numThreads,
2280 uint32_t width,
2281 uint32_t height,
2282 PCM_HAL_PARALLELISM_GRAPH_INFO graphInfo,
2283 CM_DEPENDENCY_PATTERN pattern,
2284 bool noDependencyCase);
2285
2286 MOS_STATUS HalCm_SetDispatchPattern(
2287 CM_HAL_PARALLELISM_GRAPH_INFO graphInfo,
2288 CM_DEPENDENCY_PATTERN pattern,
2289 uint32_t *dispatchFreq
2290 );
2291
2292 MOS_STATUS HalCm_SetKernelGrpFreqDispatch(
2293 PCM_HAL_PARALLELISM_GRAPH_INFO graphInfo,
2294 PCM_HAL_KERNEL_GROUP_INFO groupInfo,
2295 uint32_t numKernelGroups,
2296 uint32_t *minSteps);
2297
2298 MOS_STATUS HalCm_SetNoDependKernelDispatchPattern(
2299 uint32_t numThreads,
2300 uint32_t minSteps,
2301 uint32_t *dispatchFreq);
2302
2303 MOS_STATUS HalCm_SetupSamplerState(
2304 PCM_HAL_STATE state,
2305 PCM_HAL_KERNEL_PARAM kernelParam,
2306 PCM_HAL_KERNEL_ARG_PARAM argParam,
2307 PCM_HAL_INDEX_PARAM indexParam,
2308 int32_t mediaID,
2309 uint32_t threadIndex,
2310 uint8_t *buffer);
2311
2312 MOS_STATUS HalCm_SetupBufferSurfaceState(
2313 PCM_HAL_STATE state,
2314 PCM_HAL_KERNEL_ARG_PARAM argParam,
2315 PCM_HAL_INDEX_PARAM indexParam,
2316 int32_t bindingTable,
2317 int16_t globalSurface,
2318 uint32_t threadIndex,
2319 uint8_t *buffer);
2320
2321 MOS_STATUS HalCm_Setup2DSurfaceUPState(
2322 PCM_HAL_STATE state,
2323 PCM_HAL_KERNEL_ARG_PARAM argParam,
2324 PCM_HAL_INDEX_PARAM indexParam,
2325 int32_t bindingTable,
2326 uint32_t threadIndex,
2327 uint8_t *buffer);
2328
2329 MOS_STATUS HalCm_Setup2DSurfaceUPSamplerState(
2330 PCM_HAL_STATE state,
2331 PCM_HAL_KERNEL_ARG_PARAM argParam,
2332 PCM_HAL_INDEX_PARAM indexParam,
2333 int32_t bindingTable,
2334 uint32_t threadIndex,
2335 uint8_t *buffer);
2336
2337 MOS_STATUS HalCm_Setup2DSurfaceSamplerState(
2338 PCM_HAL_STATE state,
2339 PCM_HAL_KERNEL_ARG_PARAM argParam,
2340 PCM_HAL_INDEX_PARAM indexParam,
2341 int32_t bindingTable,
2342 uint32_t threadIndex,
2343 uint8_t *buffer);
2344
2345 MOS_STATUS HalCm_Setup2DSurfaceState(
2346 PCM_HAL_STATE state,
2347 PCM_HAL_KERNEL_ARG_PARAM argParam,
2348 PCM_HAL_INDEX_PARAM indexParam,
2349 int32_t bindingTable,
2350 uint32_t threadIndex,
2351 uint8_t *buffer);
2352
2353 MOS_STATUS HalCm_Setup3DSurfaceState(
2354 PCM_HAL_STATE state,
2355 PCM_HAL_KERNEL_ARG_PARAM argParam,
2356 PCM_HAL_INDEX_PARAM indexParam,
2357 int32_t bindingTable,
2358 uint32_t threadIndex,
2359 uint8_t *buffer);
2360
2361 MOS_STATUS HalCm_SetupVmeSurfaceState(
2362 PCM_HAL_STATE state,
2363 PCM_HAL_KERNEL_ARG_PARAM argParam,
2364 PCM_HAL_INDEX_PARAM indexParam,
2365 int32_t bindingTable,
2366 uint32_t threadIndex,
2367 uint8_t *buffer);
2368
2369 MOS_STATUS HalCm_SetupSampler8x8SurfaceState(
2370 PCM_HAL_STATE state,
2371 PCM_HAL_KERNEL_ARG_PARAM argParam,
2372 PCM_HAL_INDEX_PARAM indexParam,
2373 int32_t bindingTable,
2374 uint32_t threadIndex,
2375 uint8_t *buffer);
2376
2377 uint64_t HalCm_ConvertTicksToNanoSeconds(
2378 PCM_HAL_STATE state,
2379 uint64_t ticks);
2380
2381 bool HalCm_IsValidGpuContext(
2382 MOS_GPU_CONTEXT gpuContext);
2383
2384 MOS_STATUS HalCm_PrepareVEHintParam(
2385 PCM_HAL_STATE state,
2386 bool bScalable,
2387 PMOS_VIRTUALENGINE_HINT_PARAMS pVeHintParam);
2388
2389 MOS_STATUS HalCm_DecompressSurface(
2390 PCM_HAL_STATE state,
2391 PCM_HAL_KERNEL_ARG_PARAM argParam,
2392 uint32_t threadIndex);
2393
2394 MOS_STATUS HalCm_SurfaceSync(
2395 PCM_HAL_STATE pState,
2396 PMOS_SURFACE pSurface,
2397 bool bReadSync);
2398
2399 //*-----------------------------------------------------------------------------
2400 //| Helper functions for EnqueueWithHints
2401 //*-----------------------------------------------------------------------------
2402
2403 #endif // __CM_HAL_H__
2404