1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <arch/clock.h>
5 #include <device/mmio.h>
6 #include <console/console.h>
7 #include <delay.h>
8 #include <soc/addressmap.h>
9 #include <soc/clk_rst.h>
10 #include <soc/clock.h>
11 #include <soc/flow.h>
12 #include <soc/maincpu.h>
13 #include <soc/pmc.h>
14 #include <soc/sysctr.h>
15 #include <symbols.h>
16
17 static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
18 static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE;
19 static struct tegra_pmc_regs *pmc = (void *)TEGRA_PMC_BASE;
20 static struct sysctr_regs *sysctr = (void *)TEGRA_SYSCTR0_BASE;
21
22 struct pll_dividers {
23 u32 n : 10;
24 u32 m : 8;
25 u32 p : 4;
26 u32 cpcon : 4;
27 u32 lfcon : 4;
28 u32 : 2;
29 };
30
31 /* Some PLLs have more restrictive divider bit lengths or are missing some
32 * fields. Make sure to use the right struct in the osc_table definition to get
33 * compile-time checking, but keep the bits aligned with struct pll_dividers so
34 * they can be used interchangeably at run time. Add new formats as required. */
35 struct pllcx_dividers {
36 u32 n : 8;
37 u32 : 2;
38 u32 m : 8;
39 u32 p : 4;
40 u32 : 10;
41 };
42 struct pllpad_dividers {
43 u32 n : 10;
44 u32 m : 5;
45 u32 : 3;
46 u32 p : 3;
47 u32 : 1;
48 u32 cpcon : 4;
49 u32 : 6;
50 };
51 struct pllu_dividers {
52 u32 n : 10;
53 u32 m : 5;
54 u32 : 3;
55 u32 p : 1;
56 u32 : 3;
57 u32 cpcon : 4;
58 u32 lfcon : 4;
59 u32 : 2;
60 };
61
62 union __attribute__((transparent_union)) pll_fields {
63 u32 raw;
64 struct pll_dividers div;
65 struct pllcx_dividers cx;
66 struct pllpad_dividers pad;
67 struct pllu_dividers u;
68 };
69
70 /* This table defines the frequency dividers for every PLL to turn the external
71 * OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h.
72 * All PLLs have three dividers (n, m and p), with the governing formula for
73 * the output frequency being CF = (IN / m), VCO = CF * n and OUT = VCO / (2^p).
74 * All divisor configurations must meet the PLL's constraints for VCO and CF:
75 * PLLX: 12 MHz < CF < 50 MHz, 700 MHz < VCO < 3000 MHz
76 * PLLC: 12 MHz < CF < 50 MHz, 600 MHz < VCO < 1400 MHz
77 * PLLM: 12 MHz < CF < 50 MHz, 400 MHz < VCO < 1066 MHz
78 * PLLP: 1 MHz < CF < 6 MHz, 200 MHz < VCO < 700 MHz
79 * PLLD: 1 MHz < CF < 6 MHz, 500 MHz < VCO < 1000 MHz
80 * PLLU: 1 MHz < CF < 6 MHz, 480 MHz < VCO < 960 MHz
81 * PLLDP: 12 MHz < CF < 38 MHz, 600 MHz < VCO < 1200 MHz
82 * (values taken from Linux' drivers/clk/tegra/clk-tegra124.c). */
83 static const struct {
84 int khz;
85 struct pllcx_dividers pllx; /* target: CONFIG_PLLX_KHZ */
86 struct pllcx_dividers pllc; /* target: 600 MHz */
87 /* PLLM is set up dynamically by clock_sdram(). */
88 /* PLLP is hardwired to 408 MHz in HW (unless we set BASE_OVRD). */
89 struct pllu_dividers pllu; /* target; 960 MHz */
90 struct pllcx_dividers plldp; /* target; 270 MHz */
91 /* PLLDP treats p differently (OUT = VCO / (p + 1) for p < 6). */
92 } osc_table[16] = {
93 [OSC_FREQ_12] = {
94 .khz = 12000,
95 .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0},
96 .pllc = {.n = 50, .m = 1, .p = 0},
97 .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
98 .plldp = {.n = 90, .m = 1, .p = 3},
99 },
100 [OSC_FREQ_13] = {
101 .khz = 13000,
102 .pllx = {.n = TEGRA_PLLX_KHZ / 13000, .m = 1, .p = 0},
103 .pllc = {.n = 46, .m = 1, .p = 0}, /* 598.0 MHz */
104 .pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12, .lfcon = 2},
105 .plldp = {.n = 83, .m = 1, .p = 3}, /* 269.8 MHz */
106 },
107 [OSC_FREQ_16P8] = {
108 .khz = 16800,
109 .pllx = {.n = TEGRA_PLLX_KHZ / 16800, .m = 1, .p = 0},
110 .pllc = {.n = 71, .m = 1, .p = 1}, /* 596.4 MHz */
111 .pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 5, .lfcon = 2},
112 .plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */
113 },
114 [OSC_FREQ_19P2] = {
115 .khz = 19200,
116 .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0},
117 .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */
118 .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2},
119 .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */
120 },
121 [OSC_FREQ_26] = {
122 .khz = 26000,
123 .pllx = {.n = TEGRA_PLLX_KHZ / 26000, .m = 1, .p = 0},
124 .pllc = {.n = 23, .m = 1, .p = 0}, /* 598.0 MHz */
125 .pllu = {.n = 960, .m = 26, .p = 0, .cpcon = 12, .lfcon = 2},
126 .plldp = {.n = 83, .m = 2, .p = 3}, /* 269.8 MHz */
127 },
128 /* These oscillators get predivided as PLL inputs... n/m/p divisors for
129 * 38.4 should always match 19.2, and 48 should always match 12. */
130 [OSC_FREQ_38P4] = {
131 .khz = 38400,
132 .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0},
133 .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */
134 .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2},
135 .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */
136 },
137 [OSC_FREQ_48] = {
138 .khz = 48000,
139 .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0},
140 .pllc = {.n = 50, .m = 1, .p = 0},
141 .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2},
142 .plldp = {.n = 90, .m = 1, .p = 3},
143 },
144 };
145
146 /* Get the oscillator frequency, from the corresponding hardware
147 * configuration field. This is actually a per-soc thing. Avoid the
148 * temptation to make it common.
149 */
clock_get_osc_bits(void)150 static u32 clock_get_osc_bits(void)
151 {
152 return (read32(&clk_rst->osc_ctrl) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
153 }
154
clock_get_osc_khz(void)155 int clock_get_osc_khz(void)
156 {
157 return osc_table[clock_get_osc_bits()].khz;
158 }
159
clock_get_pll_input_khz(void)160 int clock_get_pll_input_khz(void)
161 {
162 u32 osc_ctrl = read32(&clk_rst->osc_ctrl);
163 u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
164 u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT;
165 return osc_table[osc_bits].khz >> pll_ref_div;
166 }
167
clock_init_arm_generic_timer(void)168 void clock_init_arm_generic_timer(void)
169 {
170 uint32_t freq = clock_get_osc_khz() * 1000;
171 // Set the cntfrq register.
172 set_cntfrq(freq);
173
174 // Record the system timer frequency.
175 write32(&sysctr->cntfid0, freq);
176 // Enable the system counter.
177 uint32_t cntcr = read32(&sysctr->cntcr);
178 cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG;
179 write32(&sysctr->cntcr, cntcr);
180 }
181
182 #define SOR0_CLK_SEL0 (1 << 14)
183 #define SOR0_CLK_SEL1 (1 << 15)
184
sor_clock_stop(void)185 void sor_clock_stop(void)
186 {
187 /* The Serial Output Resource clock has to be off
188 * before we start the plldp. Learned the hard way.
189 * FIXME: this has to be cleaned up a bit more.
190 * Waiting on some new info from Nvidia.
191 */
192 clrbits32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1);
193 }
194
sor_clock_start(void)195 void sor_clock_start(void)
196 {
197 /* uses PLLP, has a non-standard bit layout. */
198 setbits32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0);
199 }
200
init_pll(u32 * base,u32 * misc,const union pll_fields pll,u32 lock)201 static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock)
202 {
203 u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT |
204 pll.div.m << PLL_BASE_DIVM_SHIFT |
205 pll.div.p << PLL_BASE_DIVP_SHIFT;
206 u32 misc_con = pll.div.cpcon << PLL_MISC_CPCON_SHIFT |
207 pll.div.lfcon << PLL_MISC_LFCON_SHIFT;
208
209 /* Write dividers but BYPASS the PLL while we're messing with it. */
210 write32(base, dividers | PLL_BASE_BYPASS);
211 /*
212 * Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't
213 * exist for this PLL)
214 */
215 write32(misc, lock | misc_con);
216
217 /* Enable PLL and take it back out of BYPASS */
218 write32(base, dividers | PLL_BASE_ENABLE);
219
220 /* Wait for lock ready */
221 while (!(read32(base) & PLL_BASE_LOCK));
222 }
223
init_utmip_pll(void)224 static void init_utmip_pll(void)
225 {
226 int khz = clock_get_pll_input_khz();
227
228 /* Shut off PLL crystal clock while we mess with it */
229 clrbits32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
230 udelay(1);
231
232 write32(&clk_rst->utmip_pll_cfg0, /* 960MHz * 1 / 80 == 12 MHz */
233 80 << 16 | /* (rst) phy_divn */
234 1 << 8); /* (rst) phy_divm */
235
236 write32(&clk_rst->utmip_pll_cfg1,
237 DIV_ROUND_UP(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */
238 0 << 16 | /* PLLU pwrdn */
239 0 << 14 | /* pll_enable pwrdn */
240 0 << 12 | /* pll_active pwrdn */
241 DIV_ROUND_UP(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */
242
243 /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
244 write32(&clk_rst->utmip_pll_cfg2,
245 0 << 24 | /* SAMP_D/XDEV pwrdn */
246 DIV_ROUND_UP(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */
247 DIV_ROUND_UP(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */
248 0 << 4 | /* SAMP_C/USB3 pwrdn */
249 0 << 2 | /* SAMP_B/XHOST pwrdn */
250 0 << 0); /* SAMP_A/USBD pwrdn */
251
252 setbits32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
253 }
254
255 /* Graphics just has to be different. There's a few more bits we
256 * need to set in here, but it makes sense just to restrict all the
257 * special bits to this one function.
258 */
graphics_pll(void)259 static void graphics_pll(void)
260 {
261 int osc = clock_get_osc_bits();
262 u32 *cfg = &clk_rst->plldp_ss_cfg;
263 /* the vendor code sets the dither bit (28)
264 * an undocumented bit (24)
265 * and clamp while we mess with it (22)
266 * Dither is pretty important to display port
267 * so we really do need to handle these bits.
268 * I'm not willing to not clamp it, even if
269 * it might "mostly work" with it not set,
270 * I don't want to find out in a few months
271 * that it is needed.
272 */
273 u32 scfg = (1<<28) | (1<<24) | (1<<22);
274 write32(cfg, scfg);
275 init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc,
276 osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE);
277 /* leave dither and undoc bits set, release clamp */
278 scfg = (1<<28) | (1<<24);
279 write32(cfg, scfg);
280
281 /* disp1 will be set when panel information (pixel clock) is
282 * retrieved (clock_display).
283 */
284 }
285
286 /*
287 * Init PLLD clock source.
288 *
289 * @frequency: the requested plld frequency
290 *
291 * Return the plld frequency if success, otherwise return 0.
292 */
293 u32
clock_display(u32 frequency)294 clock_display(u32 frequency)
295 {
296 /**
297 * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz
298 * = (cf * n) >> p, where 1MHz < cf < 6MHz
299 * = ((ref / m) * n) >> p
300 *
301 * Iterate the possible values of p (3 bits, 2^7) to find out a minimum
302 * safe vco, then find best (m, n). since m has only 5 bits, we can
303 * iterate all possible values. Note Tegra 124 supports 11 bits for n,
304 * but our pll_fields has only 10 bits for n.
305 *
306 * Note values undershoot or overshoot target output frequency may not
307 * work if the values are not in "safe" range by panel specification.
308 */
309 struct pllpad_dividers plld = { 0 };
310 u32 ref = clock_get_pll_input_khz() * 1000, m, n, p = 0;
311 u32 cf, vco, rounded_rate = frequency;
312 u32 diff, best_diff;
313 const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3,
314 mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz,
315 min_cf = 1 * mhz, max_cf = 6 * mhz;
316
317 for (vco = frequency; vco < min_vco && p < max_p; p++)
318 vco <<= 1;
319
320 if (vco < min_vco || vco > max_vco) {
321 printk(BIOS_ERR, "%s: Cannot find out a supported VCO"
322 " for Frequency (%u).\n", __func__, frequency);
323 return 0;
324 }
325
326 plld.p = p;
327 best_diff = vco;
328
329 for (m = 1; m < max_m && best_diff; m++) {
330 cf = ref / m;
331 if (cf < min_cf)
332 break;
333 if (cf > max_cf)
334 continue;
335
336 n = vco / cf;
337 if (n >= max_n)
338 continue;
339
340 diff = vco - n * cf;
341 if (n + 1 < max_n && diff > cf / 2) {
342 n++;
343 diff = cf - diff;
344 }
345
346 if (diff >= best_diff)
347 continue;
348
349 best_diff = diff;
350 plld.m = m;
351 plld.n = n;
352 }
353
354 if (plld.n < 50)
355 plld.cpcon = 2;
356 else if (plld.n < 300)
357 plld.cpcon = 3;
358 else if (plld.n < 600)
359 plld.cpcon = 8;
360 else
361 plld.cpcon = 12;
362
363 if (best_diff) {
364 printk(BIOS_WARNING, "%s: Failed to match output frequency %u, "
365 "best difference is %u.\n", __func__, frequency,
366 best_diff);
367 assert(plld.m != 0);
368 rounded_rate = (ref / plld.m * plld.n) >> plld.p;
369 }
370
371 printk(BIOS_DEBUG, "%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n",
372 __func__, rounded_rate, ref, plld.m, plld.n, plld.p, plld.cpcon);
373
374 init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, plld,
375 (PLLUD_MISC_LOCK_ENABLE | PLLD_MISC_CLK_ENABLE));
376
377 return rounded_rate;
378 }
379
380 /* Initialize the UART and put it on CLK_M so we can use it during clock_init().
381 * Will later move it to PLLP in clock_config(). The divisor must be very small
382 * to accommodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
383 * CLK_SOURCE divider to get more precision. (This might still not be enough for
384 * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has
385 * been determined through trial and error (must lead to div 13 at 24MHz). */
clock_early_uart(void)386 void clock_early_uart(void)
387 {
388 write32(&clk_rst->clk_src_uarta, CLK_M << CLK_SOURCE_SHIFT |
389 CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900));
390 setbits32(&clk_rst->clk_out_enb_l, CLK_L_UARTA);
391 udelay(2);
392 clrbits32(&clk_rst->rst_dev_l, CLK_L_UARTA);
393 }
394
395 /* Enable output clock (CLK1~3) for external peripherals. */
clock_external_output(int clk_id)396 void clock_external_output(int clk_id)
397 {
398 switch (clk_id) {
399 case 1:
400 setbits32(&pmc->clk_out_cntrl, 1 << 2);
401 break;
402 case 2:
403 setbits32(&pmc->clk_out_cntrl, 1 << 10);
404 break;
405 case 3:
406 setbits32(&pmc->clk_out_cntrl, 1 << 18);
407 break;
408 default:
409 printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n",
410 clk_id);
411 break;
412 }
413 }
414
415 /* Start PLLM for SDRAM. */
clock_sdram(u32 m,u32 n,u32 p,u32 setup,u32 ph45,u32 ph90,u32 ph135,u32 kvco,u32 kcp,u32 stable_time,u32 emc_source,u32 same_freq)416 void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
417 u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source,
418 u32 same_freq)
419 {
420 u32 misc1 = ((setup << PLLM_MISC1_SETUP_SHIFT) |
421 (ph45 << PLLM_MISC1_PD_LSHIFT_PH45_SHIFT) |
422 (ph90 << PLLM_MISC1_PD_LSHIFT_PH90_SHIFT) |
423 (ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)),
424 misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) |
425 (kcp << PLLM_MISC2_KCP_SHIFT)),
426 base;
427
428 if (same_freq)
429 emc_source |= CLK_SOURCE_EMC_MC_EMC_SAME_FREQ;
430 else
431 emc_source &= ~CLK_SOURCE_EMC_MC_EMC_SAME_FREQ;
432
433 /*
434 * Note PLLM_BASE.PLLM_OUT1_RSTN must be in RESET_ENABLE mode, and
435 * PLLM_BASE.ENABLE must be in DISABLE state (both are the default
436 * values after coldboot reset).
437 */
438
439 write32(&clk_rst->pllm_misc1, misc1);
440 write32(&clk_rst->pllm_misc2, misc2);
441
442 /* PLLM.BASE needs BYPASS=0, different from general init_pll */
443 base = read32(&clk_rst->pllm_base);
444 base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK |
445 PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS);
446 base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) |
447 (p << PLL_BASE_DIVP_SHIFT));
448 write32(&clk_rst->pllm_base, base);
449
450 setbits32(&clk_rst->pllm_base, PLL_BASE_ENABLE);
451 /* stable_time is required, before we can start to check lock. */
452 udelay(stable_time);
453
454 while (!(read32(&clk_rst->pllm_base) & PLL_BASE_LOCK)) {
455 udelay(1);
456 }
457 /*
458 * After PLLM reports being locked, we have to delay 10us before
459 * enabling PLLM_OUT.
460 */
461 udelay(10);
462
463 /* Put OUT1 out of reset state (start to output). */
464 setbits32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE);
465
466 /* Enable and start MEM(MC) and EMC. */
467 clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0);
468 write32(&clk_rst->clk_src_emc, emc_source);
469 udelay(IO_STABILIZATION_DELAY);
470 }
471
clock_cpu0_config(void * entry)472 void clock_cpu0_config(void *entry)
473 {
474 void *const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;
475
476 write32(&maincpu_stack_pointer, (uintptr_t)_estack);
477 write32(&maincpu_entry_point, (uintptr_t)entry);
478 write32(evp_cpu_reset, (uintptr_t)&maincpu_setup);
479
480 /* Set active CPU cluster to G */
481 clrbits32(&flow->cluster_control, 1);
482
483 // Set up cclk_brst and divider.
484 write32(&clk_rst->cclk_brst_pol,
485 (CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) |
486 (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) |
487 (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) |
488 (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) |
489 (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28));
490 write32(&clk_rst->super_cclk_div,
491 CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB);
492
493 // Enable the clocks for CPUs 0-3.
494 uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr);
495 cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP |
496 CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP;
497 write32(&clk_rst->clk_cpu_cmplx_clr, cpu_cmplx_clr);
498
499 // Enable other CPU related clocks.
500 setbits32(&clk_rst->clk_out_enb_l, CLK_L_CPU);
501 setbits32(&clk_rst->clk_out_enb_v, CLK_V_CPUG);
502 setbits32(&clk_rst->clk_out_enb_v, CLK_V_CPULP);
503 }
504
clock_cpu0_remove_reset(void)505 void clock_cpu0_remove_reset(void)
506 {
507 // Disable the reset on the non-CPU parts of the fast cluster.
508 write32(&clk_rst->rst_cpug_cmplx_clr, CRC_RST_CPUG_CLR_NONCPU);
509 // Disable the various resets on the CPUs.
510 write32(&clk_rst->rst_cpug_cmplx_clr,
511 CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 |
512 CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 |
513 CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 |
514 CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 |
515 CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 |
516 CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 |
517 CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 |
518 CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 |
519 CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG);
520
521 // Disable the reset on the non-CPU parts of the slow cluster.
522 write32(&clk_rst->rst_cpulp_cmplx_clr, CRC_RST_CPULP_CLR_NONCPU);
523 // Disable the various resets on the LP CPU.
524 write32(&clk_rst->rst_cpulp_cmplx_clr,
525 CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 |
526 CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 |
527 CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG);
528 }
529
clock_halt_avp(void)530 void clock_halt_avp(void)
531 {
532 for (;;) {
533 write32(&flow->halt_cop_events,
534 FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ |
535 FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT);
536 }
537 }
538
clock_init(void)539 void clock_init(void)
540 {
541 u32 osc = clock_get_osc_bits();
542
543 /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */
544 write32(&clk_rst->pllc_misc2, 0x2b << 17 | 0xb << 9);
545
546 /* Max out the AVP clock before everything else (need PLLC for that). */
547 init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc,
548 osc_table[osc].pllc, PLLC_MISC_LOCK_ENABLE);
549
550 /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
551 * features section in the TRM). */
552 write32(&clk_rst->clk_sys_rate,
553 TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT |
554 TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT);
555 write32(&clk_rst->pllc_out, CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ)
556 << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN);
557 write32(&clk_rst->sclk_brst_pol, /* sclk = 300 MHz */
558 SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
559 SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT);
560
561 /* Change the oscillator drive strength (from U-Boot -- why?) */
562 clrsetbits32(&clk_rst->osc_ctrl, OSC_XOFS_MASK,
563 OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
564
565 /*
566 * Ambiguous quote from u-boot. TODO: what's this mean?
567 * "should update same value in PMC_OSC_EDPD_OVER XOFS
568 * field for warmboot "
569 */
570 clrsetbits32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK,
571 OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
572
573 /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */
574 clrbits32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK);
575
576 /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
577 write32(&clk_rst->pllp_outa,
578 (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT |
579 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT |
580 (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT |
581 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT);
582 write32(&clk_rst->pllp_outb,
583 (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT |
584 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT |
585 (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT |
586 PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT);
587
588 /* init pllx */
589 init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc,
590 osc_table[osc].pllx, PLLPAXS_MISC_LOCK_ENABLE);
591
592 /* init pllu */
593 init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc,
594 osc_table[osc].pllu, PLLUD_MISC_LOCK_ENABLE);
595
596 init_utmip_pll();
597 graphics_pll();
598 }
599
clock_enable_clear_reset(u32 l,u32 h,u32 u,u32 v,u32 w,u32 x)600 void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
601 {
602 if (l) write32(&clk_rst->clk_enb_l_set, l);
603 if (h) write32(&clk_rst->clk_enb_h_set, h);
604 if (u) write32(&clk_rst->clk_enb_u_set, u);
605 if (v) write32(&clk_rst->clk_enb_v_set, v);
606 if (w) write32(&clk_rst->clk_enb_w_set, w);
607 if (x) write32(&clk_rst->clk_enb_x_set, x);
608
609 /* Give clocks time to stabilize. */
610 udelay(IO_STABILIZATION_DELAY);
611
612 if (l) write32(&clk_rst->rst_dev_l_clr, l);
613 if (h) write32(&clk_rst->rst_dev_h_clr, h);
614 if (u) write32(&clk_rst->rst_dev_u_clr, u);
615 if (v) write32(&clk_rst->rst_dev_v_clr, v);
616 if (w) write32(&clk_rst->rst_dev_w_clr, w);
617 if (x) write32(&clk_rst->rst_dev_x_clr, x);
618 }
619
clock_reset_l(u32 bit)620 void clock_reset_l(u32 bit)
621 {
622 write32(&clk_rst->rst_dev_l_set, bit);
623 udelay(1);
624 write32(&clk_rst->rst_dev_l_clr, bit);
625 }
626
clock_reset_h(u32 bit)627 void clock_reset_h(u32 bit)
628 {
629 write32(&clk_rst->rst_dev_h_set, bit);
630 udelay(1);
631 write32(&clk_rst->rst_dev_h_clr, bit);
632 }
633
clock_reset_u(u32 bit)634 void clock_reset_u(u32 bit)
635 {
636 write32(&clk_rst->rst_dev_u_set, bit);
637 udelay(1);
638 write32(&clk_rst->rst_dev_u_clr, bit);
639 }
640
clock_reset_v(u32 bit)641 void clock_reset_v(u32 bit)
642 {
643 write32(&clk_rst->rst_dev_v_set, bit);
644 udelay(1);
645 write32(&clk_rst->rst_dev_v_clr, bit);
646 }
647
clock_reset_w(u32 bit)648 void clock_reset_w(u32 bit)
649 {
650 write32(&clk_rst->rst_dev_w_set, bit);
651 udelay(1);
652 write32(&clk_rst->rst_dev_w_clr, bit);
653 }
654
clock_reset_x(u32 bit)655 void clock_reset_x(u32 bit)
656 {
657 write32(&clk_rst->rst_dev_x_set, bit);
658 udelay(1);
659 write32(&clk_rst->rst_dev_x_clr, bit);
660 }
661