1 /*
2 * Copyright 2010 Jerome Glisse <[email protected]>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 */
7 #ifndef SI_PIPE_H
8 #define SI_PIPE_H
9
10 #include "si_shader.h"
11 #include "si_state.h"
12 #include "winsys/radeon_winsys.h"
13 #include "util/u_blitter.h"
14 #include "util/u_idalloc.h"
15 #include "util/u_suballoc.h"
16 #include "util/u_threaded_context.h"
17 #include "util/u_vertex_state_cache.h"
18 #include "util/perf/u_trace.h"
19 #include "ac_descriptors.h"
20 #include "ac_sqtt.h"
21 #include "ac_spm.h"
22 #include "si_perfetto.h"
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 struct ac_llvm_compiler;
29
30 #define SHADER_DEBUG_LOG 0
31
32 #define ATI_VENDOR_ID 0x1002
33 #define SI_NOT_QUERY 0xffffffff
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST MESA_PRIM_COUNT
37
38 /* The primitive restart can be any number, but we must pick one which will
39 * mean "unknown" for the purpose of state tracking and the number shouldn't
40 * be a commonly-used one.
41 */
42 #define SI_RESTART_INDEX_UNKNOWN ((unsigned)INT_MIN)
43 #define SI_INSTANCE_COUNT_UNKNOWN ((unsigned)INT_MIN)
44 #define SI_NUM_SMOOTH_AA_SAMPLES 4
45 #define SI_MAX_POINT_SIZE 2048
46 #define SI_GS_PER_ES 128
47 /* Alignment for optimal CP DMA performance. */
48 #define SI_CPDMA_ALIGNMENT 32
49
50 /* Pipeline & streamout query start/stop events. */
51 #define SI_BARRIER_EVENT_PIPELINESTAT_START BITFIELD_BIT(0)
52 #define SI_BARRIER_EVENT_PIPELINESTAT_STOP BITFIELD_BIT(1)
53 /* Events only used by workarounds. These shouldn't be used for API barriers. */
54 #define SI_BARRIER_EVENT_FLUSH_AND_INV_DB_META BITFIELD_BIT(2)
55 #define SI_BARRIER_EVENT_VGT_FLUSH BITFIELD_BIT(3)
56 /* PFP waits for ME to finish. Used to sync for index and indirect buffers and render condition. */
57 #define SI_BARRIER_PFP_SYNC_ME BITFIELD_BIT(4)
58 /* Instruction cache. */
59 #define SI_BARRIER_INV_ICACHE BITFIELD_BIT(5)
60 /* Scalar cache. (GFX6-9: scalar L1; GFX10+: scalar L0)
61 * GFX10: This also invalidates the L1 shader array cache. */
62 #define SI_BARRIER_INV_SMEM BITFIELD_BIT(6)
63 /* Vector cache. (GFX6-9: vector L1; GFX10+: vector L0)
64 * GFX10: This also invalidates the L1 shader array cache. */
65 #define SI_BARRIER_INV_VMEM BITFIELD_BIT(7)
66 /* L2 cache + L2 metadata cache writeback & invalidate.
67 * GFX6-8: Used by shaders only. GFX9+: Used by everything. */
68 #define SI_BARRIER_INV_L2 BITFIELD_BIT(8)
69 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
70 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
71 * GFX6-7 will do complete invalidation because the writeback is unsupported. */
72 #define SI_BARRIER_WB_L2 BITFIELD_BIT(9)
73 /* Writeback & invalidate the L2 metadata cache only. */
74 #define SI_BARRIER_INV_L2_METADATA BITFIELD_BIT(10)
75 /* These wait for shaders to finish. (SYNC_VS = wait for the whole geometry pipeline to finish) */
76 #define SI_BARRIER_SYNC_VS BITFIELD_BIT(11)
77 #define SI_BARRIER_SYNC_PS BITFIELD_BIT(12)
78 #define SI_BARRIER_SYNC_CS BITFIELD_BIT(13)
79 /* Framebuffer caches. */
80 #define SI_BARRIER_SYNC_AND_INV_DB BITFIELD_BIT(14)
81 #define SI_BARRIER_SYNC_AND_INV_CB BITFIELD_BIT(15)
82
83 #define SI_PREFETCH_LS (1 << 1)
84 #define SI_PREFETCH_HS (1 << 2)
85 #define SI_PREFETCH_ES (1 << 3)
86 #define SI_PREFETCH_GS (1 << 4)
87 #define SI_PREFETCH_VS (1 << 5)
88 #define SI_PREFETCH_PS (1 << 6)
89
90 #define SI_MAX_BORDER_COLORS 4096
91 #define SI_MAX_VIEWPORTS 16
92 #define SI_MAP_BUFFER_ALIGNMENT 64
93 /* We only support the minimum allowed value (512), so that we can pack a 3D block size
94 * in 1 SGPR. */
95 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 512
96
97 #define SI_CONTEXT_FLAG_AUX (1u << 31)
98
99 #define SI_RESOURCE_FLAG_FORCE_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
100 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
101 #define SI_RESOURCE_FLAG_GL2_BYPASS (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
102 #define SI_RESOURCE_FLAG_DISCARDABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 3) /* Discard instead of evict. */
103 #define SI_RESOURCE_FLAG_DRIVER_INTERNAL (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
104 #define SI_RESOURCE_AUX_PLANE (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
105 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
106 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
107
108 enum si_has_gs {
109 GS_OFF,
110 GS_ON,
111 };
112
113 enum si_has_tess {
114 TESS_OFF,
115 TESS_ON,
116 };
117
118 enum si_has_ngg {
119 NGG_OFF,
120 NGG_ON,
121 };
122
123 #define DCC_CODE(x) (((x) << 24) | ((x) << 16) | ((x) << 8) | (x))
124
125 enum si_clear_code
126 {
127 /* Common clear codes. */
128 DCC_CLEAR_0000 = DCC_CODE(0x00), /* all bits are 0 */
129 DCC_UNCOMPRESSED = DCC_CODE(0xFF),
130
131 GFX8_DCC_CLEAR_0000 = DCC_CLEAR_0000,
132 GFX8_DCC_CLEAR_0001 = DCC_CODE(0x40),
133 GFX8_DCC_CLEAR_1110 = DCC_CODE(0x80),
134 GFX8_DCC_CLEAR_1111 = DCC_CODE(0xC0),
135 GFX8_DCC_CLEAR_REG = DCC_CODE(0x20),
136 GFX9_DCC_CLEAR_SINGLE = DCC_CODE(0x10),
137
138 GFX11_DCC_CLEAR_SINGLE = DCC_CODE(0x01),
139 GFX11_DCC_CLEAR_0000 = DCC_CLEAR_0000, /* all bits are 0 */
140 GFX11_DCC_CLEAR_1111_UNORM = DCC_CODE(0x02), /* all bits are 1 */
141 GFX11_DCC_CLEAR_1111_FP16 = DCC_CODE(0x04), /* all 16-bit words are 0x3c00, max 64bpp */
142 GFX11_DCC_CLEAR_1111_FP32 = DCC_CODE(0x06), /* all 32-bit words are 0x3f800000 */
143 /* Color bits are 0, alpha bits are 1; only 88, 8888, 16161616 */
144 GFX11_DCC_CLEAR_0001_UNORM = DCC_CODE(0x08),
145 /* Color bits are 1, alpha bits are 0, only 88, 8888, 16161616 */
146 GFX11_DCC_CLEAR_1110_UNORM = DCC_CODE(0x0A),
147 };
148
149 #define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
150 #define SI_IMAGE_ACCESS_ALLOW_DCC_STORE (1 << 9)
151 #define SI_IMAGE_ACCESS_BLOCK_FORMAT_AS_UINT (1 << 10) /* for compressed/subsampled images */
152
153 enum si_occlusion_query_mode {
154 SI_OCCLUSION_QUERY_MODE_DISABLE,
155 SI_OCCLUSION_QUERY_MODE_PRECISE_INTEGER,
156 SI_OCCLUSION_QUERY_MODE_PRECISE_BOOLEAN,
157 SI_OCCLUSION_QUERY_MODE_CONSERVATIVE_BOOLEAN,
158 };
159
160 /* Debug flags. */
161 enum
162 {
163 /* Shader logging options: */
164 DBG_VS = MESA_SHADER_VERTEX,
165 DBG_TCS = MESA_SHADER_TESS_CTRL,
166 DBG_TES = MESA_SHADER_TESS_EVAL,
167 DBG_GS = MESA_SHADER_GEOMETRY,
168 DBG_PS = MESA_SHADER_FRAGMENT,
169 DBG_CS = MESA_SHADER_COMPUTE,
170 DBG_INIT_NIR,
171 DBG_NIR,
172 DBG_INIT_LLVM,
173 DBG_LLVM,
174 DBG_INIT_ACO,
175 DBG_ACO,
176 DBG_ASM,
177 DBG_STATS,
178
179 /* Shader compiler options the shader cache should be aware of: */
180 DBG_W32_GE,
181 DBG_W32_PS,
182 DBG_W32_CS,
183 DBG_W64_GE,
184 DBG_W64_PS,
185 DBG_W64_CS,
186
187 /* Shader compiler options (with no effect on the shader cache): */
188 DBG_CHECK_IR,
189 DBG_MONOLITHIC_SHADERS,
190 DBG_NO_OPT_VARIANT,
191
192 /* Information logging options: */
193 DBG_INFO,
194 DBG_TEX,
195 DBG_COMPUTE,
196 DBG_VM,
197 DBG_CACHE_STATS,
198 DBG_IB,
199 DBG_VERTEX_ELEMENTS,
200
201 /* Driver options: */
202 DBG_NO_WC,
203 DBG_NO_WC_STREAM,
204 DBG_CHECK_VM,
205 DBG_RESERVE_VMID,
206 DBG_SHADOW_REGS,
207 DBG_NO_FAST_DISPLAY_LIST,
208 DBG_NO_DMA_SHADERS,
209
210 /* Multimedia options: */
211 DBG_NO_EFC,
212 DBG_LOW_LATENCY_ENCODE,
213
214 /* 3D engine options: */
215 DBG_NO_NGG,
216 DBG_ALWAYS_NGG_CULLING_ALL,
217 DBG_NO_NGG_CULLING,
218 DBG_SWITCH_ON_EOP,
219 DBG_NO_OUT_OF_ORDER,
220 DBG_NO_DPBB,
221 DBG_DPBB,
222 DBG_NO_HYPERZ,
223 DBG_NO_2D_TILING,
224 DBG_NO_TILING,
225 DBG_NO_DISPLAY_TILING,
226 DBG_NO_DISPLAY_DCC,
227 DBG_NO_EXPORTED_DCC,
228 DBG_NO_DCC,
229 DBG_NO_DCC_CLEAR,
230 DBG_NO_DCC_STORE,
231 DBG_DCC_STORE,
232 DBG_NO_DCC_MSAA,
233 DBG_NO_FMASK,
234 DBG_NO_DMA,
235
236 DBG_EXTRA_METADATA,
237
238 DBG_TMZ,
239 DBG_SQTT,
240 DBG_USE_ACO,
241
242 DBG_COUNT
243 };
244
245 enum
246 {
247 /* Tests: */
248 DBG_TEST_CLEAR_BUFFER,
249 DBG_TEST_COPY_BUFFER,
250 DBG_TEST_IMAGE_COPY,
251 DBG_TEST_CB_RESOLVE,
252 DBG_TEST_COMPUTE_BLIT,
253 DBG_TEST_VMFAULT_CP,
254 DBG_TEST_VMFAULT_SHADER,
255 DBG_TEST_DMA_PERF,
256 DBG_TEST_MEM_PERF,
257 DBG_TEST_BLIT_PERF,
258 };
259
260 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
261 #define DBG(name) (1ull << DBG_##name)
262
263 #define SI_BIND_CONSTANT_BUFFER_SHIFT 0
264 #define SI_BIND_SHADER_BUFFER_SHIFT 6
265 #define SI_BIND_IMAGE_BUFFER_SHIFT 12
266 #define SI_BIND_SAMPLER_BUFFER_SHIFT 18
267 #define SI_BIND_OTHER_BUFFER_SHIFT 24
268
269 /* Bind masks for all 6 shader stages. */
270 #define SI_BIND_CONSTANT_BUFFER_ALL (0x3f << SI_BIND_CONSTANT_BUFFER_SHIFT)
271 #define SI_BIND_SHADER_BUFFER_ALL (0x3f << SI_BIND_SHADER_BUFFER_SHIFT)
272 #define SI_BIND_IMAGE_BUFFER_ALL (0x3f << SI_BIND_IMAGE_BUFFER_SHIFT)
273 #define SI_BIND_SAMPLER_BUFFER_ALL (0x3f << SI_BIND_SAMPLER_BUFFER_SHIFT)
274
275 #define SI_BIND_CONSTANT_BUFFER(shader) ((1 << (shader)) << SI_BIND_CONSTANT_BUFFER_SHIFT)
276 #define SI_BIND_SHADER_BUFFER(shader) ((1 << (shader)) << SI_BIND_SHADER_BUFFER_SHIFT)
277 #define SI_BIND_IMAGE_BUFFER(shader) ((1 << (shader)) << SI_BIND_IMAGE_BUFFER_SHIFT)
278 #define SI_BIND_SAMPLER_BUFFER(shader) ((1 << (shader)) << SI_BIND_SAMPLER_BUFFER_SHIFT)
279 #define SI_BIND_VERTEX_BUFFER (1 << (SI_BIND_OTHER_BUFFER_SHIFT + 0))
280 #define SI_BIND_STREAMOUT_BUFFER (1 << (SI_BIND_OTHER_BUFFER_SHIFT + 1))
281
282 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
283 * at the moment.
284 */
285 struct si_resource {
286 struct threaded_resource b;
287
288 /* If we remove this seemingly useless padding, performance in Viewperf2020/catiav5test1
289 * decreases by 8%.
290 */
291 uint32_t _pad;
292
293 /* Winsys objects. */
294 struct pb_buffer_lean *buf;
295 uint64_t gpu_address;
296
297 /* Resource properties. */
298 uint64_t bo_size;
299 uint8_t bo_alignment_log2;
300 enum radeon_bo_domain domains:8;
301 enum radeon_bo_flag flags:16;
302 unsigned bind_history; /* bitmask of SI_BIND_xxx_BUFFER */
303
304 /* The buffer range which is initialized (with a write transfer,
305 * streamout, DMA, or as a random access target). The rest of
306 * the buffer is considered invalid and can be mapped unsynchronized.
307 *
308 * This allows unsynchronized mapping of a buffer range which hasn't
309 * been used yet. It's for applications which forget to use
310 * the unsynchronized map flag and expect the driver to figure it out.
311 */
312 struct util_range valid_buffer_range;
313
314 /* For buffers only. This indicates that a write operation has been
315 * performed by L2, but the cache hasn't been flushed.
316 * Any hw block which doesn't use or bypasses L2 should check this
317 * flag and flush the cache before using the buffer.
318 *
319 * For example, L2 must be flushed if a buffer which has been
320 * modified by a shader store instruction is about to be used as
321 * an index buffer. The reason is that VGT DMA index fetching doesn't
322 * use L2.
323 */
324 bool L2_cache_dirty;
325
326 /* Whether this resource is referenced by bindless handles. */
327 bool texture_handle_allocated;
328 bool image_handle_allocated;
329
330 /* Whether the resource has been exported via resource_get_handle. */
331 uint8_t external_usage; /* PIPE_HANDLE_USAGE_* */
332 };
333
334 struct si_transfer {
335 struct threaded_transfer b;
336 struct si_resource *staging;
337 };
338
339 struct si_texture {
340 struct si_resource buffer;
341
342 struct radeon_surf surface;
343 struct si_texture *flushed_depth_texture;
344
345 /* One texture allocation can contain these buffers:
346 * - image (pixel data)
347 * - FMASK buffer (MSAA compression)
348 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
349 * - HTILE buffer (Z/S compression and fast Z/S clear)
350 * - DCC buffer (color compression and new fast color clear)
351 * - displayable DCC buffer (if the DCC buffer is not displayable)
352 */
353 uint64_t cmask_base_address_reg;
354 struct si_resource *cmask_buffer;
355 unsigned cb_color_info; /* fast clear enable bit */
356 unsigned color_clear_value[2]; /* not on gfx11 */
357 unsigned last_msaa_resolve_target_micro_mode;
358 bool swap_rgb_to_bgr_on_next_clear;
359 bool swap_rgb_to_bgr;
360 unsigned num_level0_transfers;
361 unsigned plane_index; /* other planes are different pipe_resources */
362 unsigned num_planes;
363 enum pipe_format multi_plane_format;
364
365 /* Depth buffer compression and fast clear. */
366 float depth_clear_value[RADEON_SURF_MAX_LEVELS];
367 uint8_t stencil_clear_value[RADEON_SURF_MAX_LEVELS];
368 uint16_t depth_cleared_level_mask_once; /* if it was cleared at least once */
369 uint16_t depth_cleared_level_mask; /* track if it's cleared (can be false negative) */
370 uint16_t stencil_cleared_level_mask_once; /* if it was cleared at least once */
371 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
372 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
373 enum pipe_format db_render_format : 16;
374 bool fmask_is_identity : 1;
375 bool tc_compatible_htile : 1;
376 bool enable_tc_compatible_htile_next_clear : 1;
377 bool htile_stencil_disabled : 1;
378 bool upgraded_depth : 1; /* upgraded from unorm to Z32_FLOAT */
379 bool is_depth : 1;
380 bool db_compatible : 1;
381 bool can_sample_z : 1;
382 bool can_sample_s : 1;
383 bool need_flush_after_depth_decompression: 1;
384
385 /* We need to track DCC dirtiness, because st/dri usually calls
386 * flush_resource twice per frame (not a bug) and we don't wanna
387 * decompress DCC twice.
388 */
389 bool displayable_dcc_dirty : 1;
390
391 /* Counter that should be non-zero if the texture is bound to a
392 * framebuffer.
393 */
394 unsigned framebuffers_bound;
395 };
396
397 /* State trackers create separate textures in a next-chain for extra planes
398 * even if those are planes created purely for modifiers. Because the linking
399 * of the chain happens outside of the driver, and NULL is interpreted as
400 * failure, let's create some dummy texture structs. We could use these
401 * later to use the offsets for linking if we really wanted to.
402 *
403 * For now just create a dummy struct and completely ignore it.
404 *
405 * Potentially in the future we could store stride/offset and use it during
406 * creation, though we might want to change how linking is done first.
407 */
408 struct si_auxiliary_texture {
409 struct threaded_resource b;
410 struct pb_buffer_lean *buffer;
411 uint32_t offset;
412 uint32_t stride;
413 };
414
415 struct si_surface {
416 struct pipe_surface base;
417
418 /* These can vary with block-compressed textures. */
419 uint16_t width0;
420 uint16_t height0;
421
422 bool color_initialized : 1;
423 bool depth_initialized : 1;
424
425 /* Misc. color flags. */
426 bool color_is_int8 : 1;
427 bool color_is_int10 : 1;
428 bool dcc_incompatible : 1;
429 uint8_t db_format_index : 3;
430
431 /* Color registers. */
432 struct ac_cb_surface cb;
433
434 unsigned spi_shader_col_format : 8; /* no blending, no alpha-to-coverage. */
435 unsigned spi_shader_col_format_alpha : 8; /* alpha-to-coverage */
436 unsigned spi_shader_col_format_blend : 8; /* blending without alpha. */
437 unsigned spi_shader_col_format_blend_alpha : 8; /* blending with alpha. */
438
439 /* DB registers. */
440 struct ac_ds_surface ds;
441 };
442
443 struct si_mmio_counter {
444 unsigned busy;
445 unsigned idle;
446 };
447
448 union si_mmio_counters {
449 struct si_mmio_counters_named {
450 /* For global GPU load including SDMA. */
451 struct si_mmio_counter gpu;
452
453 /* GRBM_STATUS */
454 struct si_mmio_counter spi;
455 struct si_mmio_counter gui;
456 struct si_mmio_counter ta;
457 struct si_mmio_counter gds;
458 struct si_mmio_counter vgt;
459 struct si_mmio_counter ia;
460 struct si_mmio_counter sx;
461 struct si_mmio_counter wd;
462 struct si_mmio_counter bci;
463 struct si_mmio_counter sc;
464 struct si_mmio_counter pa;
465 struct si_mmio_counter db;
466 struct si_mmio_counter cp;
467 struct si_mmio_counter cb;
468
469 /* SRBM_STATUS2 */
470 struct si_mmio_counter sdma;
471
472 /* CP_STAT */
473 struct si_mmio_counter pfp;
474 struct si_mmio_counter meq;
475 struct si_mmio_counter me;
476 struct si_mmio_counter surf_sync;
477 struct si_mmio_counter cp_dma;
478 struct si_mmio_counter scratch_ram;
479 } named;
480
481 unsigned array[sizeof(struct si_mmio_counters_named) / sizeof(unsigned)];
482 };
483
484 struct si_memory_object {
485 struct pipe_memory_object b;
486 struct pb_buffer_lean *buf;
487 uint32_t stride;
488 };
489
490 /* Saved CS data for debugging features. */
491 struct radeon_saved_cs {
492 uint32_t *ib;
493 unsigned num_dw;
494
495 struct radeon_bo_list_item *bo_list;
496 unsigned bo_count;
497 };
498
499 struct si_aux_context {
500 struct pipe_context *ctx;
501 mtx_t lock;
502 };
503
504 struct si_screen {
505 struct pipe_screen b;
506 struct radeon_winsys *ws;
507 struct disk_cache *disk_shader_cache;
508
509 struct radeon_info info;
510 struct nir_shader_compiler_options *nir_options;
511 uint64_t debug_flags;
512 char renderer_string[183];
513
514 void (*make_texture_descriptor)(struct si_screen *screen, struct si_texture *tex, bool sampler,
515 enum pipe_texture_target target, enum pipe_format pipe_format,
516 const unsigned char state_swizzle[4], unsigned first_level,
517 unsigned last_level, unsigned first_layer, unsigned last_layer,
518 unsigned width, unsigned height, unsigned depth,
519 bool get_bo_metadata, uint32_t *state, uint32_t *fmask_state);
520
521 unsigned pa_sc_raster_config;
522 unsigned pa_sc_raster_config_1;
523 unsigned se_tile_repeat;
524 unsigned gs_table_depth;
525 struct ac_hs_info hs;
526 unsigned eqaa_force_coverage_samples;
527 unsigned eqaa_force_z_samples;
528 unsigned eqaa_force_color_samples;
529 unsigned pbb_context_states_per_bin;
530 unsigned pbb_persistent_states_per_bin;
531 bool has_draw_indirect_multi;
532 bool dpbb_allowed;
533 bool use_ngg;
534 bool use_ngg_culling;
535 bool allow_dcc_msaa_clear_to_reg_for_bpp[5]; /* indexed by log2(Bpp) */
536 bool always_allow_dcc_stores;
537 bool use_aco;
538
539 struct {
540 #define OPT_BOOL(name, dflt, description) bool name : 1;
541 #define OPT_INT(name, dflt, description) int name;
542 #include "si_debug_options.h"
543 } options;
544
545 /* Whether shaders are monolithic (1-part) or separate (3-part). */
546 bool use_monolithic_shaders;
547 bool record_llvm_ir;
548 const char *context_roll_log_filename;
549
550 struct slab_parent_pool pool_transfers;
551
552 /* Texture filter settings. */
553 int force_aniso; /* -1 = disabled */
554
555 unsigned max_texel_buffer_elements;
556
557 /* Auxiliary context. Used to initialize resources and upload shaders. */
558 union {
559 struct {
560 struct si_aux_context general;
561
562 /* Second auxiliary context for uploading shaders. When the first auxiliary context is
563 * locked and wants to compile and upload shaders, we need to use a second auxiliary
564 * context because the first one is locked.
565 */
566 struct si_aux_context shader_upload;
567 } aux_context;
568 struct si_aux_context aux_contexts[2];
569 };
570
571 /* Async compute context for DRI_PRIME copies. */
572 struct pipe_context *async_compute_context;
573 simple_mtx_t async_compute_context_lock;
574
575 /* This must be in the screen, because UE4 uses one context for
576 * compilation and another one for rendering.
577 */
578 unsigned num_compilations;
579 /* Along with ST_DEBUG=precompile, this should show if applications
580 * are loading shaders on demand. This is a monotonic counter.
581 */
582 unsigned num_shaders_created;
583 unsigned num_memory_shader_cache_hits;
584 unsigned num_memory_shader_cache_misses;
585 unsigned num_disk_shader_cache_hits;
586 unsigned num_disk_shader_cache_misses;
587
588 /* GPU load thread. */
589 simple_mtx_t gpu_load_mutex;
590 thrd_t gpu_load_thread;
591 bool gpu_load_thread_created;
592 union si_mmio_counters mmio_counters;
593 volatile unsigned gpu_load_stop_thread; /* bool */
594
595 /* Performance counters. */
596 struct si_perfcounters *perfcounters;
597
598 /* If pipe_screen wants to recompute and re-emit the framebuffer,
599 * sampler, and image states of all contexts, it should atomically
600 * increment this.
601 *
602 * Each context will compare this with its own last known value of
603 * the counter before drawing and re-emit the states accordingly.
604 */
605 unsigned dirty_tex_counter;
606 unsigned dirty_buf_counter;
607
608 /* Atomically increment this counter when an existing texture's
609 * metadata is enabled or disabled in a way that requires changing
610 * contexts' compressed texture binding masks.
611 */
612 unsigned compressed_colortex_counter;
613
614 simple_mtx_t shader_parts_mutex;
615 struct si_shader_part *ps_prologs;
616 struct si_shader_part *ps_epilogs;
617
618 /* Shader cache in memory.
619 *
620 * Design & limitations:
621 * - The shader cache is per screen (= per process), never saved to
622 * disk, and skips redundant shader compilations from NIR to bytecode.
623 * - It can only be used with one-variant-per-shader support, in which
624 * case only the main (typically middle) part of shaders is cached.
625 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
626 * variants of VS and TES are cached, so LS and ES aren't.
627 * - GS and CS aren't cached, but it's certainly possible to cache
628 * those as well.
629 */
630 simple_mtx_t shader_cache_mutex;
631 struct hash_table *shader_cache;
632 /* Maximum and current size */
633 uint32_t shader_cache_size;
634 uint32_t shader_cache_max_size;
635
636 /* Shader cache of live shaders. */
637 struct util_live_shader_cache live_shader_cache;
638
639 /* Shader compiler queue for multithreaded compilation. */
640 struct util_queue shader_compiler_queue;
641 /* Compiler instances for asynchronous shader compilation of new shader CSOs,
642 * one for each thread of the shader compiler queue.
643 */
644 struct ac_llvm_compiler *compiler[24]; /* used by the queue only */
645
646 struct util_queue shader_compiler_queue_opt_variants;
647 /* Compiler instances for asynchronous shader compilation of optimized shader variants,
648 * one for each thread of the low-priority shader compiler queue. */
649 struct ac_llvm_compiler *compiler_lowp[10];
650
651 struct util_idalloc_mt buffer_ids;
652 struct util_vertex_state_cache vertex_state_cache;
653
654 struct si_resource *attribute_pos_prim_ring;
655
656 simple_mtx_t tess_ring_lock;
657 struct pipe_resource *tess_rings;
658 struct pipe_resource *tess_rings_tmz;
659
660 /* NGG streamout. */
661 simple_mtx_t gds_mutex;
662 struct pb_buffer_lean *gds_oa;
663 };
664
665 struct si_compute {
666 struct si_shader_selector sel;
667 struct si_shader shader;
668
669 unsigned ir_type;
670 unsigned input_size;
671
672 int max_global_buffers;
673 struct pipe_resource **global_buffers;
674 };
675
676 struct si_sampler_view {
677 struct pipe_sampler_view base;
678 /* [0..7] = image descriptor
679 * [4..7] = buffer descriptor */
680 uint32_t state[8];
681 uint32_t fmask_state[8];
682 const struct legacy_surf_level *base_level_info;
683 uint8_t block_width;
684 bool is_stencil_sampler;
685 bool dcc_incompatible;
686 };
687
688 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
689
690 struct si_sampler_state {
691 #ifndef NDEBUG
692 unsigned magic;
693 #endif
694 uint32_t val[4];
695 uint32_t upgraded_depth_val[4];
696 };
697
698 struct si_cs_shader_state {
699 struct si_compute *program;
700 struct si_compute *emitted_program;
701 unsigned offset;
702 uint32_t variable_shared_size;
703 };
704
705 struct si_samplers {
706 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
707 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
708
709 /* The i-th bit is set if that element is enabled (non-NULL resource). */
710 unsigned enabled_mask;
711 uint32_t has_depth_tex_mask;
712 uint32_t needs_depth_decompress_mask;
713 uint32_t needs_color_decompress_mask;
714 };
715
716 struct si_images {
717 struct pipe_image_view views[SI_NUM_IMAGES];
718 uint32_t needs_color_decompress_mask;
719 unsigned enabled_mask;
720 unsigned display_dcc_store_mask;
721 };
722
723 struct si_framebuffer {
724 struct pipe_framebuffer_state state;
725 unsigned colorbuf_enabled_4bit;
726 unsigned spi_shader_col_format;
727 unsigned spi_shader_col_format_alpha;
728 unsigned spi_shader_col_format_blend;
729 unsigned spi_shader_col_format_blend_alpha;
730 uint8_t nr_samples : 5; /* at most 16xAA */
731 uint8_t log_samples : 3; /* at most 4 = 16xAA */
732 uint8_t nr_color_samples; /* at most 8xAA */
733 uint8_t compressed_cb_mask;
734 uint8_t uncompressed_cb_mask;
735 uint8_t color_is_int8;
736 uint8_t color_is_int10;
737 uint8_t dirty_cbufs;
738 uint8_t min_bytes_per_pixel;
739 bool dirty_zsbuf;
740 bool any_dst_linear;
741 bool CB_has_shader_readable_metadata;
742 bool DB_has_shader_readable_metadata;
743 bool all_DCC_pipe_aligned;
744 bool has_dcc_msaa;
745 bool disable_vrs_flat_shading;
746 bool has_stencil;
747 bool has_hiz_his;
748 };
749
750 enum si_quant_mode
751 {
752 /* This is the list we want to support. */
753 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
754 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
755 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
756 };
757
758 struct si_signed_scissor {
759 int minx;
760 int miny;
761 int maxx;
762 int maxy;
763 enum si_quant_mode quant_mode;
764 };
765
766 struct si_viewports {
767 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
768 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
769 };
770
771 struct si_streamout_target {
772 struct pipe_stream_output_target b;
773
774 /* The buffer where BUFFER_FILLED_SIZE is stored. */
775 struct si_resource *buf_filled_size;
776 unsigned buf_filled_size_offset;
777 unsigned buf_filled_size_draw_count_offset;
778 bool buf_filled_size_valid;
779
780 unsigned stride_in_dw;
781 };
782
783 struct si_streamout {
784 bool begin_emitted;
785
786 unsigned enabled_mask;
787 unsigned num_targets;
788 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
789
790 unsigned append_bitmask;
791 bool suspended;
792
793 /* External state which comes from the vertex shader,
794 * it must be set explicitly when binding a shader. */
795 uint8_t *stride_in_dw;
796 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
797
798 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
799 unsigned hw_enabled_mask;
800
801 /* The state of VGT_STRMOUT_(CONFIG|EN). */
802 bool streamout_enabled;
803 bool prims_gen_query_enabled;
804 int num_prims_gen_queries;
805 };
806
807 /* A shader state consists of the shader selector, which is a constant state
808 * object shared by multiple contexts and shouldn't be modified, and
809 * the current shader variant selected for this context.
810 */
811 struct si_shader_ctx_state {
812 struct si_shader_selector *cso;
813 struct si_shader *current;
814 /* The shader variant key representing the current state. */
815 union si_shader_key key;
816 };
817
818 #define SI_NUM_VGT_PARAM_KEY_BITS 12
819 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
820
821 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
822 * Some fields are set by state-change calls, most are set by draw_vbo.
823 */
824 union si_vgt_param_key {
825 struct {
826 #if UTIL_ARCH_LITTLE_ENDIAN
827 uint16_t prim : 4;
828 uint16_t uses_instancing : 1;
829 uint16_t multi_instances_smaller_than_primgroup : 1;
830 uint16_t primitive_restart : 1;
831 uint16_t count_from_stream_output : 1;
832 uint16_t line_stipple_enabled : 1;
833 uint16_t uses_tess : 1;
834 uint16_t tess_uses_prim_id : 1;
835 uint16_t uses_gs : 1;
836 uint16_t _pad : 16 - SI_NUM_VGT_PARAM_KEY_BITS;
837 #else /* UTIL_ARCH_BIG_ENDIAN */
838 uint16_t _pad : 16 - SI_NUM_VGT_PARAM_KEY_BITS;
839 uint16_t uses_gs : 1;
840 uint16_t tess_uses_prim_id : 1;
841 uint16_t uses_tess : 1;
842 uint16_t line_stipple_enabled : 1;
843 uint16_t count_from_stream_output : 1;
844 uint16_t primitive_restart : 1;
845 uint16_t multi_instances_smaller_than_primgroup : 1;
846 uint16_t uses_instancing : 1;
847 uint16_t prim : 4;
848 #endif
849 } u;
850 uint16_t index;
851 };
852
853 struct si_texture_handle {
854 unsigned desc_slot;
855 bool desc_dirty;
856 struct pipe_sampler_view *view;
857 struct si_sampler_state sstate;
858 };
859
860 struct si_image_handle {
861 unsigned desc_slot;
862 bool desc_dirty;
863 struct pipe_image_view view;
864 };
865
866 struct si_saved_cs {
867 struct pipe_reference reference;
868 struct si_context *ctx;
869 struct radeon_saved_cs gfx;
870 struct radeon_saved_cs compute;
871 struct si_resource *trace_buf;
872 unsigned trace_id;
873
874 unsigned gfx_last_dw;
875 bool flushed;
876 int64_t time_flush;
877 };
878
879 struct si_sqtt_fake_pipeline {
880 struct si_pm4_state pm4; /* base class */
881 uint64_t code_hash;
882 struct si_resource *bo;
883 };
884
885 struct si_small_prim_cull_info {
886 float scale[2], translate[2];
887 float scale_no_aa[2], translate_no_aa[2];
888 float clip_half_line_width[2]; /* line_width * 0.5 in clip space in X and Y directions */
889 };
890
891 struct si_vertex_state {
892 struct pipe_vertex_state b;
893 struct si_vertex_elements velems;
894 uint32_t descriptors[4 * SI_MAX_ATTRIBS];
895 };
896
897 /* The structure layout is identical to a pair of registers in SET_*_REG_PAIRS_PACKED. */
898 struct gfx11_reg_pair {
899 union {
900 /* A pair of register offsets. */
901 struct {
902 uint16_t reg_offset[2];
903 };
904 /* The same pair of register offsets as a dword. */
905 uint32_t reg_offsets;
906 };
907 /* A pair of register values for the register offsets above. */
908 uint32_t reg_value[2];
909 };
910
911 /* A pair of values for SET_*_REG_PAIRS. */
912 struct gfx12_reg {
913 uint32_t reg_offset;
914 uint32_t reg_value;
915 };
916
917 typedef void (*pipe_draw_vertex_state_func)(struct pipe_context *ctx,
918 struct pipe_vertex_state *vstate,
919 uint32_t partial_velem_mask,
920 struct pipe_draw_vertex_state_info info,
921 const struct pipe_draw_start_count_bias *draws,
922 unsigned num_draws);
923
924 struct si_context {
925 struct pipe_context b; /* base class */
926
927 enum radeon_family family;
928 enum amd_gfx_level gfx_level;
929
930 struct radeon_winsys *ws;
931 struct radeon_winsys_ctx *ctx;
932 struct radeon_cmdbuf gfx_cs; /* compute IB if graphics is disabled */
933 struct radeon_cmdbuf *sdma_cs;
934 struct pipe_fence_handle *last_gfx_fence;
935 struct si_resource *eop_bug_scratch;
936 struct si_resource *eop_bug_scratch_tmz;
937 struct u_upload_mgr *cached_gtt_allocator;
938 struct threaded_context *tc;
939 struct u_suballocator allocator_zeroed_memory;
940 struct slab_child_pool pool_transfers;
941 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
942 struct pipe_device_reset_callback device_reset_callback;
943 struct u_log_context *log;
944 void *query_result_shader;
945 void *sh_query_result_shader;
946 struct {
947 /* Memory where the shadowed registers will be saved and loaded from. */
948 struct si_resource *registers;
949 /* Context Save Area: scratch area to save other required data. Only
950 * used if info->has_fw_based_mcbp is true.
951 */
952 struct si_resource *csa;
953 } shadowing;
954
955 void (*emit_barrier)(struct si_context *ctx, struct radeon_cmdbuf *cs);
956
957 struct blitter_context *blitter;
958 void *noop_blend;
959 void *noop_dsa;
960 void *no_velems_state;
961 void *discard_rasterizer_state;
962 void *custom_dsa_flush;
963 void *custom_blend_resolve;
964 void *custom_blend_fmask_decompress;
965 void *custom_blend_eliminate_fastclear;
966 void *custom_blend_dcc_decompress;
967 void *vs_blit_pos;
968 void *vs_blit_pos_layered;
969 void *vs_blit_color;
970 void *vs_blit_color_layered;
971 void *vs_blit_texcoord;
972 void *cs_clear_buffer_rmw;
973 void *cs_ubyte_to_ushort;
974 void *cs_dcc_retile[32];
975 void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
976 struct hash_table_u64 *cs_dma_shaders; /* clear_buffer and copy_buffer shaders */
977 struct hash_table_u64 *cs_blit_shaders;
978 struct hash_table_u64 *ps_resolve_shaders;
979 struct si_screen *screen;
980 struct util_debug_callback debug;
981 struct ac_llvm_compiler *compiler; /* only non-threaded compilation */
982 struct hash_table *fixed_func_tcs_shader_cache;
983 struct si_resource *wait_mem_scratch;
984 struct si_resource *wait_mem_scratch_tmz;
985 unsigned wait_mem_number;
986 uint16_t prefetch_L2_mask;
987
988 bool blitter_running:1;
989 bool suppress_update_ps_colorbuf0_slot:1;
990 bool is_noop:1;
991 bool has_graphics:1;
992 bool gfx_flush_in_progress : 1;
993 bool gfx_last_ib_is_busy : 1;
994 bool compute_is_busy : 1;
995 bool gfx11_force_msaa_num_samples_zero:1;
996 int8_t pipeline_stats_enabled; /* -1 = unknown, 0 = disabled, 1 = enabled */
997
998 unsigned num_gfx_cs_flushes;
999 unsigned initial_gfx_cs_size;
1000 unsigned last_dirty_tex_counter;
1001 unsigned last_dirty_buf_counter;
1002 unsigned last_compressed_colortex_counter;
1003 struct {
1004 unsigned with_cb;
1005 unsigned with_db;
1006 } num_draw_calls_sh_coherent;
1007 unsigned barrier_flags;
1008
1009 /* Atoms (state emit functions). */
1010 union si_state_atoms atoms;
1011 uint64_t dirty_atoms; /* mask */
1012 union si_state queued;
1013 union si_state emitted;
1014
1015 /* Gfx11+: Buffered SH registers for SET_SH_REG_PAIRS_*. */
1016 unsigned num_buffered_gfx_sh_regs;
1017 unsigned num_buffered_compute_sh_regs;
1018 union {
1019 struct {
1020 struct gfx11_reg_pair buffered_gfx_sh_regs[32];
1021 struct gfx11_reg_pair buffered_compute_sh_regs[32];
1022 } gfx11;
1023
1024 struct {
1025 struct gfx12_reg buffered_gfx_sh_regs[64];
1026 struct gfx12_reg buffered_compute_sh_regs[64];
1027 } gfx12;
1028 };
1029
1030 /* Atom declarations. */
1031 struct si_framebuffer framebuffer;
1032 unsigned sample_locs_num_samples;
1033 uint16_t sample_mask;
1034 unsigned last_cb_target_mask;
1035 struct pipe_blend_color blend_color;
1036 struct pipe_clip_state clip_state;
1037 struct si_shader_data shader_pointers;
1038 struct si_stencil_ref stencil_ref;
1039 bool blend_color_any_nonzeros:1;
1040 bool clip_state_any_nonzeros:1;
1041 bool viewport0_y_inverted;
1042 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
1043 struct si_streamout streamout;
1044 struct si_viewports viewports;
1045 unsigned num_window_rectangles;
1046 bool window_rectangles_include;
1047 struct pipe_scissor_state window_rectangles[4];
1048
1049 /* Precomputed states. */
1050 struct si_pm4_state *cs_preamble_state;
1051 struct si_pm4_state *cs_preamble_state_tmz;
1052 uint16_t gs_ring_state_dw_offset;
1053 uint16_t gs_ring_state_dw_offset_tmz;
1054 bool cs_preamble_has_vgt_flush;
1055 bool cs_preamble_has_vgt_flush_tmz;
1056 uint32_t vgt_shader_stages_en;
1057 uint32_t ge_cntl;
1058
1059 /* shaders */
1060 union {
1061 struct {
1062 struct si_shader_ctx_state vs;
1063 struct si_shader_ctx_state tcs;
1064 struct si_shader_ctx_state tes;
1065 struct si_shader_ctx_state gs;
1066 struct si_shader_ctx_state ps;
1067 } shader;
1068 /* indexed access using pipe_shader_type (not by MESA_SHADER_*) */
1069 struct si_shader_ctx_state shaders[SI_NUM_GRAPHICS_SHADERS];
1070 };
1071 struct si_cs_shader_state cs_shader_state;
1072 bool compute_ping_pong_launch;
1073 /* if current tcs set by user */
1074 bool is_user_tcs;
1075
1076 /* video context */
1077 bool vcn_has_ctx;
1078 enum vcn_version vcn_ip_ver;
1079
1080 /* shader information */
1081 uint64_t ps_inputs_read_or_disabled;
1082 struct si_vertex_elements *vertex_elements;
1083 unsigned num_vertex_elements;
1084 unsigned cs_max_waves_per_sh;
1085 uint32_t compute_tmpring_size;
1086 bool uses_nontrivial_vs_inputs;
1087 bool force_trivial_vs_inputs;
1088 bool do_update_shaders;
1089 bool compute_shaderbuf_sgprs_dirty;
1090 bool compute_image_sgprs_dirty;
1091 bool vs_uses_base_instance;
1092 bool vs_uses_draw_id;
1093 uint8_t patch_vertices;
1094 bool has_tessellation; /* whether si_screen::tess_rings* are valid */
1095
1096 /* shader descriptors */
1097 struct si_descriptors descriptors[SI_NUM_DESCS];
1098 unsigned descriptors_dirty;
1099 unsigned shader_pointers_dirty;
1100 unsigned shader_needs_decompress_mask;
1101 unsigned shader_has_depth_tex;
1102 struct si_buffer_resources internal_bindings;
1103 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1104 struct si_samplers samplers[SI_NUM_SHADERS];
1105 struct si_images images[SI_NUM_SHADERS];
1106 bool bo_list_add_all_resident_resources;
1107 bool bo_list_add_all_compute_resources;
1108
1109 /* other shader resources */
1110 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1111 struct pipe_resource *esgs_ring;
1112 struct pipe_resource *gsvs_ring;
1113 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1114 struct si_resource *border_color_buffer;
1115 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1116 unsigned border_color_count;
1117 unsigned num_vs_blit_sgprs;
1118 uint32_t vs_blit_sh_data[MAX_SI_VS_BLIT_SGPRS];
1119 uint32_t cs_user_data[8];
1120
1121 /* Vertex buffers. */
1122 bool vertex_buffers_dirty;
1123 uint8_t num_vertex_buffers;
1124 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1125 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1126
1127 /* Even though we don't need this variable, u_upload_alloc has an optimization that skips
1128 * reference counting when the new upload buffer is the same as the last one. So keep
1129 * the last upload buffer here and always pass &last_const_upload_buffer to u_upload_alloc.
1130 */
1131 struct si_resource *last_const_upload_buffer;
1132
1133 /* MSAA config state. */
1134 int ps_iter_samples;
1135 bool ps_uses_fbfetch;
1136 bool smoothing_enabled;
1137
1138 /* point smoothing state.*/
1139 bool point_smoothing_enabled;
1140
1141 /* DB render state. */
1142 unsigned ps_db_shader_control;
1143 unsigned ps_pa_sc_hisz_control;
1144 unsigned dbcb_copy_sample;
1145 bool dbcb_depth_copy_enabled : 1;
1146 bool dbcb_stencil_copy_enabled : 1;
1147 bool db_flush_depth_inplace : 1;
1148 bool db_flush_stencil_inplace : 1;
1149 bool db_depth_clear : 1;
1150 bool db_depth_disable_expclear : 1;
1151 bool db_stencil_clear : 1;
1152 bool db_stencil_disable_expclear : 1;
1153 bool occlusion_queries_disabled : 1;
1154 bool generate_mipmap_for_depth : 1;
1155 bool allow_flat_shading : 1;
1156
1157 /* Emitted draw state. */
1158 bool ngg : 1;
1159 bool disable_instance_packing : 1;
1160 uint16_t ngg_culling;
1161 unsigned last_index_size;
1162 unsigned last_instance_count;
1163 int last_primitive_restart_en;
1164 unsigned last_restart_index;
1165 unsigned last_prim;
1166 unsigned current_vs_state; /* all VS bits */
1167 unsigned current_gs_state; /* only GS and NGG bits */
1168 unsigned last_vs_state;
1169 unsigned last_gs_state;
1170 enum mesa_prim current_rast_prim; /* primitive type after TES, GS */
1171 unsigned gs_out_prim;
1172
1173 struct si_small_prim_cull_info last_small_prim_cull_info;
1174 struct si_resource *small_prim_cull_info_buf;
1175 uint64_t small_prim_cull_info_address;
1176
1177 /* Scratch buffer */
1178 struct si_resource *scratch_buffer;
1179 unsigned spi_tmpring_size;
1180 unsigned max_seen_scratch_bytes_per_wave;
1181 unsigned max_seen_compute_scratch_bytes_per_wave;
1182
1183 struct si_resource *compute_scratch_buffer;
1184
1185 /* Emitted derived tessellation state. */
1186 /* Local shader (VS), or HS if LS-HS are merged. */
1187 struct si_shader *last_ls;
1188 struct si_shader_selector *last_tcs;
1189 unsigned last_num_tcs_input_cp;
1190 unsigned last_tes_sh_base;
1191 bool last_tess_uses_primid;
1192 unsigned num_patches_per_workgroup;
1193 unsigned tcs_offchip_layout;
1194 unsigned tes_offchip_ring_va_sgpr;
1195 unsigned ls_hs_rsrc2;
1196 unsigned ls_hs_config;
1197
1198 /* Debug state. */
1199 bool is_debug;
1200 struct si_saved_cs *current_saved_cs;
1201 uint64_t dmesg_timestamp;
1202 unsigned apitrace_call_number;
1203
1204 /* Other state */
1205 bool need_check_render_feedback;
1206 bool decompression_enabled;
1207 bool dpbb_force_off;
1208 bool dpbb_force_off_profile_vs;
1209 bool dpbb_force_off_profile_ps;
1210 bool vs_writes_viewport_index;
1211 bool vs_disables_clipping_viewport;
1212 bool has_reset_been_notified;
1213
1214 /* The number of pixels outside the viewport that are not culled by the clipper.
1215 * Normally, the clipper clips everything outside the viewport, however, points and lines
1216 * can have vertices outside the viewport, but their edges can be inside the viewport. Those
1217 * shouldn't be culled. The problem is that the register setting (PA_CL_GB_*_DISC_ADJ) that
1218 * controls the discard distance, which depends on the point size and line width, applies to
1219 * all primitive types, and we would have to set 0 distance for triangles and non-zero for
1220 * points and lines whenever the primitive type changes, which would add overhead and cause
1221 * context rolls.
1222 *
1223 * To reduce that, whenever the discard distance changes for points and lines, we keep it
1224 * at that higher value up to a certain small number for all primitive types including all
1225 * points and lines within a specific size. This is slightly inefficient, but it eliminates
1226 * a lot of guardband state updates and context register changes.
1227 */
1228 float min_clip_discard_distance_watermark;
1229 float current_clip_discard_distance;
1230
1231 /* Precomputed IA_MULTI_VGT_PARAM */
1232 union si_vgt_param_key ia_multi_vgt_param_key;
1233 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1234
1235 /* Bindless descriptors. */
1236 struct si_descriptors bindless_descriptors;
1237 struct util_idalloc bindless_used_slots;
1238 unsigned num_bindless_descriptors;
1239 bool bindless_descriptors_dirty;
1240 bool graphics_internal_bindings_pointer_dirty;
1241 bool compute_internal_bindings_pointer_dirty;
1242 bool graphics_bindless_pointer_dirty;
1243 bool compute_bindless_pointer_dirty;
1244 bool gs_attribute_ring_pointer_dirty;
1245
1246 /* Allocated bindless handles */
1247 struct hash_table *tex_handles;
1248 struct hash_table *img_handles;
1249
1250 /* Resident bindless handles */
1251 struct util_dynarray resident_tex_handles;
1252 struct util_dynarray resident_img_handles;
1253
1254 /* Resident bindless handles which need decompression */
1255 struct util_dynarray resident_tex_needs_color_decompress;
1256 struct util_dynarray resident_img_needs_color_decompress;
1257 struct util_dynarray resident_tex_needs_depth_decompress;
1258
1259 /* Bindless state */
1260 bool uses_bindless_samplers;
1261 bool uses_bindless_images;
1262
1263 /* MSAA sample locations.
1264 * The first index is the sample index.
1265 * The second index is the coordinate: X, Y. */
1266 struct {
1267 float x1[1][2];
1268 float x2[2][2];
1269 float x4[4][2];
1270 float x8[8][2];
1271 float x16[16][2];
1272 } sample_positions;
1273 struct pipe_resource *sample_pos_buffer;
1274
1275 /* Misc stats. */
1276 unsigned num_draw_calls;
1277 unsigned num_decompress_calls;
1278 unsigned last_cb_flush_num_draw_calls;
1279 unsigned last_db_flush_num_draw_calls;
1280 unsigned last_cb_flush_num_decompress_calls;
1281 unsigned last_db_flush_num_decompress_calls;
1282 unsigned num_compute_calls;
1283 unsigned num_cp_dma_calls;
1284 unsigned num_vs_flushes;
1285 unsigned num_ps_flushes;
1286 unsigned num_cs_flushes;
1287 unsigned num_cb_cache_flushes;
1288 unsigned num_db_cache_flushes;
1289 unsigned num_L2_invalidates;
1290 unsigned num_L2_writebacks;
1291 unsigned num_resident_handles;
1292 uint64_t num_alloc_tex_transfer_bytes;
1293 unsigned last_tex_ps_draw_ratio; /* for query */
1294 unsigned context_roll;
1295
1296 /* Queries. */
1297 /* Maintain the list of active queries for pausing between IBs. */
1298 enum si_occlusion_query_mode occlusion_query_mode;
1299 int num_integer_occlusion_queries;
1300 int num_boolean_occlusion_queries;
1301 int num_conservative_occlusion_queries;
1302 int num_pipeline_stat_queries;
1303 int num_pipeline_stat_emulated_queries;
1304 int num_hw_pipestat_streamout_queries;
1305 struct list_head active_queries;
1306 unsigned num_cs_dw_queries_suspend;
1307 /* Shared buffer for pipeline stats queries implemented with an atomic op */
1308 struct si_resource *pipeline_stats_query_buf;
1309
1310 /* Render condition. */
1311 struct pipe_query *render_cond;
1312 unsigned render_cond_mode;
1313 bool render_cond_invert;
1314 bool render_cond_enabled; /* for u_blitter */
1315
1316 /* Shader-based queries. */
1317 struct list_head shader_query_buffers;
1318 unsigned num_active_shader_queries;
1319
1320 struct {
1321 bool with_cb;
1322 bool with_db;
1323 } force_shader_coherency;
1324
1325 struct si_tracked_regs tracked_regs;
1326
1327 /* Resources that need to be flushed, but will not get an explicit
1328 * flush_resource from the frontend and that will need to get flushed during
1329 * a context flush.
1330 */
1331 struct hash_table *dirty_implicit_resources;
1332
1333 pipe_draw_func draw_vbo[2][2][2];
1334 pipe_draw_vertex_state_func draw_vertex_state[2][2][2];
1335 /* When b.draw_vbo is a wrapper, real_draw_vbo is the real draw_vbo function */
1336 pipe_draw_func real_draw_vbo;
1337 pipe_draw_vertex_state_func real_draw_vertex_state;
1338 void (*emit_spi_map[33])(struct si_context *sctx, unsigned index);
1339
1340 /* SQTT */
1341 struct ac_sqtt *sqtt;
1342 struct ac_spm spm;
1343 struct pipe_fence_handle *last_sqtt_fence;
1344 enum rgp_sqtt_marker_event_type sqtt_next_event;
1345 bool sqtt_enabled;
1346
1347 unsigned context_flags;
1348
1349 /* Shaders. */
1350 void *cs_clear_image_dcc_single[2][3]; /* [is_msaa][wg_dim] */
1351 /* Only used for DCC MSAA clears with 4-8 fragments and 4-16 samples. */
1352 void *cs_clear_dcc_msaa[32][5][2][3][2]; /* [swizzle_mode][log2(bpe)][fragments == 8][log2(samples)-2][is_array] */
1353
1354 /* u_trace logging*/
1355 struct si_ds_device ds;
1356 /** Where tracepoints are recorded */
1357 struct u_trace trace;
1358 struct si_ds_queue ds_queue;
1359 uint32_t *last_timestamp_cmd;
1360 unsigned int last_timestamp_cmd_cdw;
1361 };
1362
1363 /* si_barrier.c */
1364 #define SI_FB_BARRIER_SYNC_CB BITFIELD_BIT(0)
1365 #define SI_FB_BARRIER_SYNC_DB BITFIELD_BIT(1)
1366 #define SI_FB_BARRIER_SYNC_ALL BITFIELD_RANGE(0, 2)
1367
1368 void si_barrier_before_internal_op(struct si_context *sctx, unsigned flags,
1369 unsigned num_buffers,
1370 const struct pipe_shader_buffer *buffers,
1371 unsigned writable_buffers_mask,
1372 unsigned num_images,
1373 const struct pipe_image_view *images);
1374 void si_barrier_after_internal_op(struct si_context *sctx, unsigned flags,
1375 unsigned num_buffers,
1376 const struct pipe_shader_buffer *buffers,
1377 unsigned writable_buffers_mask,
1378 unsigned num_images,
1379 const struct pipe_image_view *images);
1380 void si_barrier_before_simple_buffer_op(struct si_context *sctx, unsigned flags,
1381 struct pipe_resource *dst, struct pipe_resource *src);
1382 void si_barrier_after_simple_buffer_op(struct si_context *sctx, unsigned flags,
1383 struct pipe_resource *dst, struct pipe_resource *src);
1384 void si_fb_barrier_before_rendering(struct si_context *sctx);
1385 void si_fb_barrier_after_rendering(struct si_context *sctx, unsigned flags);
1386 void si_init_barrier_functions(struct si_context *sctx);
1387
1388 /* si_blit.c */
1389 enum si_blitter_op /* bitmask */
1390 {
1391 SI_SAVE_TEXTURES = 1,
1392 SI_SAVE_FRAMEBUFFER = 2,
1393 SI_SAVE_FRAGMENT_STATE = 4,
1394 SI_SAVE_FRAGMENT_CONSTANT = 8,
1395 SI_DISABLE_RENDER_COND = 16,
1396 };
1397
1398 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1399 void si_blitter_end(struct si_context *sctx);
1400 void si_init_blit_functions(struct si_context *sctx);
1401 void gfx6_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1402 void gfx11_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1403 void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
1404 unsigned level, unsigned first_layer, unsigned last_layer,
1405 bool need_fmask_expand);
1406 void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
1407 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1408 struct pipe_resource *src, unsigned src_level,
1409 const struct pipe_box *src_box);
1410 void si_gfx_copy_image(struct si_context *sctx, struct pipe_resource *dst,
1411 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1412 struct pipe_resource *src, unsigned src_level,
1413 const struct pipe_box *src_box);
1414 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1415 void si_flush_implicit_resources(struct si_context *sctx);
1416 bool si_msaa_resolve_blit_via_CB(struct pipe_context *ctx, const struct pipe_blit_info *info,
1417 bool fail_if_slow);
1418 void si_gfx_blit(struct pipe_context *ctx, const struct pipe_blit_info *info);
1419
1420 /* si_nir_optim.c */
1421 bool si_nir_is_output_const_if_tex_is_const(struct nir_shader *shader, float *in, float *out, int *texunit);
1422
1423 /* si_buffer.c */
1424 bool si_cs_is_buffer_referenced(struct si_context *sctx, struct pb_buffer_lean *buf,
1425 unsigned usage);
1426 void *si_buffer_map(struct si_context *sctx, struct si_resource *resource,
1427 unsigned usage);
1428 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
1429 unsigned alignment);
1430 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res);
1431 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1432 unsigned usage, unsigned size, unsigned alignment);
1433 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1434 unsigned usage, unsigned size, unsigned alignment);
1435 struct pipe_resource *si_buffer_from_winsys_buffer(struct pipe_screen *screen,
1436 const struct pipe_resource *templ,
1437 struct pb_buffer_lean *imported_buf,
1438 uint64_t offset);
1439 void si_replace_buffer_storage(struct pipe_context *ctx, struct pipe_resource *dst,
1440 struct pipe_resource *src, unsigned num_rebinds,
1441 uint32_t rebind_mask, uint32_t delete_buffer_id);
1442 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1443 void si_init_buffer_functions(struct si_context *sctx);
1444
1445 /* si_clear.c */
1446 #define SI_CLEAR_TYPE_CMASK (1 << 0)
1447 #define SI_CLEAR_TYPE_DCC (1 << 1)
1448 #define SI_CLEAR_TYPE_HTILE (1 << 2)
1449
1450 struct si_clear_info {
1451 struct pipe_resource *resource;
1452 uint64_t offset;
1453 uint32_t size;
1454 uint32_t clear_value;
1455 uint32_t writemask;
1456 bool is_dcc_msaa; /* Clear it as a DCC MSAA image. */
1457 uint8_t level;
1458 enum pipe_format format;
1459 union pipe_color_union color;
1460 };
1461
1462 bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsigned level,
1463 unsigned clear_value, struct si_clear_info *out);
1464 void si_init_buffer_clear(struct si_clear_info *info,
1465 struct pipe_resource *resource, uint64_t offset,
1466 uint32_t size, uint32_t clear_value);
1467 void si_execute_clears(struct si_context *sctx, struct si_clear_info *info,
1468 unsigned num_clears, unsigned types, bool render_condition_enabled);
1469 bool si_compute_fast_clear_image(struct si_context *sctx, struct pipe_resource *tex,
1470 enum pipe_format format, unsigned level, const struct pipe_box *box,
1471 const union pipe_color_union *color, bool render_condition_enable,
1472 bool fail_if_slow);
1473 void si_gfx_clear_render_target(struct pipe_context *ctx, struct pipe_surface *dst,
1474 const union pipe_color_union *color, unsigned dstx,
1475 unsigned dsty, unsigned width, unsigned height,
1476 bool render_condition_enabled);
1477 void si_init_clear_functions(struct si_context *sctx);
1478
1479 /* si_compute.c */
1480 void si_destroy_compute(struct si_compute *program);
1481
1482 /* si_compute_blit.c */
1483 bool si_should_blit_clamp_to_edge(const struct pipe_blit_info *info, unsigned coord_mask);
1484 void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_info *info,
1485 void *shader, unsigned num_buffers,
1486 const struct pipe_shader_buffer *buffers,
1487 unsigned writeable_bitmask, bool render_condition_enable);
1488 bool si_compute_clear_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1489 unsigned dst_offset, struct pipe_resource *src,
1490 unsigned src_offset, unsigned size,
1491 const uint32_t *clear_value, unsigned clear_value_size,
1492 unsigned dwords_per_thread, bool render_condition_enable,
1493 bool fail_if_slow);
1494 enum si_clear_method {
1495 SI_COMPUTE_CLEAR_METHOD,
1496 SI_AUTO_SELECT_CLEAR_METHOD
1497 };
1498 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1499 uint64_t offset, uint64_t size, uint32_t *clear_value,
1500 uint32_t clear_value_size, enum si_clear_method method,
1501 bool render_condition_enable);
1502 void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *dst,
1503 unsigned dst_offset, unsigned size, uint32_t clear_value,
1504 uint32_t writebitmask, bool render_condition_enable);
1505 void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1506 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1507 void si_compute_shorten_ubyte_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1508 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1509 bool render_condition_enable);
1510 void si_compute_clear_image_dcc_single(struct si_context *sctx, struct si_texture *tex,
1511 unsigned level, enum pipe_format format,
1512 const union pipe_color_union *color,
1513 bool render_condition_enable);
1514 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1515 void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value,
1516 bool render_condition_enable);
1517 void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex);
1518 bool si_compute_clear_image(struct si_context *sctx, struct pipe_resource *tex,
1519 enum pipe_format format, unsigned level, const struct pipe_box *box,
1520 const union pipe_color_union *color, bool render_condition_enable,
1521 bool fail_if_slow);
1522 bool si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
1523 struct pipe_resource *src, unsigned src_level, unsigned dstx,
1524 unsigned dsty, unsigned dstz, const struct pipe_box *src_box,
1525 bool fail_if_slow);
1526 bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info,
1527 const union pipe_color_union *clear_color, unsigned dst_access,
1528 unsigned src_access, bool fail_if_slow);
1529 void si_init_compute_blit_functions(struct si_context *sctx);
1530
1531 /* si_cp_dma.c */
1532 void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs);
1533 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1534 struct pipe_resource *dst, uint64_t offset, uint64_t size,
1535 unsigned value);
1536 void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1537 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
1538 unsigned size);
1539 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
1540 unsigned size, unsigned dst_sel, unsigned engine, const void *data);
1541 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1542 struct si_resource *dst, unsigned dst_offset, unsigned src_sel,
1543 struct si_resource *src, unsigned src_offset);
1544
1545 /* si_cp_reg_shadowing.c */
1546 void si_init_cp_reg_shadowing(struct si_context *sctx);
1547
1548 /* si_cp_utils.c */
1549 void si_cp_release_mem_pws(struct si_context *sctx, struct radeon_cmdbuf *cs,
1550 unsigned event_type, unsigned gcr_cntl);
1551 void si_cp_acquire_mem_pws(struct si_context *sctx, struct radeon_cmdbuf *cs,
1552 unsigned event_type, unsigned stage_sel, unsigned gcr_cntl,
1553 unsigned distance, unsigned sqtt_flush_flags);
1554 void si_cp_release_acquire_mem_pws(struct si_context *sctx, struct radeon_cmdbuf *cs,
1555 unsigned event_type, unsigned gcr_cntl, unsigned stage_sel,
1556 unsigned sqtt_flush_flags);
1557 void si_cp_acquire_mem(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned gcr_cntl,
1558 unsigned engine);
1559 void si_cp_pfp_sync_me(struct radeon_cmdbuf *cs);
1560
1561 /* si_debug.c */
1562 void si_gather_context_rolls(struct si_context *sctx);
1563 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
1564 bool get_buffer_list);
1565 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1566 void si_destroy_saved_cs(struct si_saved_cs *scs);
1567 void si_auto_log_cs(void *data, struct u_log_context *log);
1568 void si_log_hw_flush(struct si_context *sctx);
1569 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1570 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1571 void si_init_debug_functions(struct si_context *sctx);
1572 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved);
1573 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1574 void si_print_current_ib(struct si_context *sctx, FILE *f);
1575
1576 /* si_fence.c */
1577 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event,
1578 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1579 struct si_resource *buf, uint64_t va, uint32_t new_fence,
1580 unsigned query_type);
1581 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1582 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref,
1583 uint32_t mask, unsigned flags);
1584 void si_init_fence_functions(struct si_context *ctx);
1585 void si_init_screen_fence_functions(struct si_screen *screen);
1586 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1587 struct tc_unflushed_batch_token *tc_token);
1588
1589 /* si_get.c */
1590 void si_init_screen_get_functions(struct si_screen *sscreen);
1591
1592 bool si_sdma_copy_image(struct si_context *ctx, struct si_texture *dst, struct si_texture *src);
1593
1594 /* si_gfx_cs.c */
1595 void si_reset_debug_log_buffer(struct si_context *sctx);
1596 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
1597 void si_allocate_gds(struct si_context *ctx);
1598 void si_set_tracked_regs_to_clear_state(struct si_context *ctx);
1599 void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs);
1600 void si_trace_emit(struct si_context *sctx);
1601 void si_emit_ts(struct si_context *sctx, struct si_resource* buffer, unsigned int offset);
1602 /* Replace the sctx->b.draw_vbo function with a wrapper. This can be use to implement
1603 * optimizations without affecting the normal draw_vbo functions perf.
1604 */
1605 void si_install_draw_wrapper(struct si_context *sctx, pipe_draw_func wrapper,
1606 pipe_draw_vertex_state_func vstate_wrapper);
1607
1608 /* si_gpu_load.c */
1609 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1610 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1611 unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin);
1612
1613 /* si_compute.c */
1614 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1615 void si_init_compute_functions(struct si_context *sctx);
1616
1617 /* si_pipe.c */
1618 struct ac_llvm_compiler *si_create_llvm_compiler(struct si_screen *sscreen);
1619 void si_init_aux_async_compute_ctx(struct si_screen *sscreen);
1620 struct si_context *si_get_aux_context(struct si_aux_context *ctx);
1621 void si_put_aux_context_flush(struct si_aux_context *ctx);
1622 void si_put_aux_shader_upload_context_flush(struct si_screen *sscreen);
1623 void si_destroy_screen(struct pipe_screen *pscreen);
1624
1625 /* si_perfcounters.c */
1626 void si_init_perfcounters(struct si_screen *screen);
1627 void si_destroy_perfcounters(struct si_screen *screen);
1628 void si_inhibit_clockgating(struct si_context *sctx, struct radeon_cmdbuf *cs, bool inhibit);
1629 void si_pc_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders);
1630 void si_pc_emit_spm_start(struct radeon_cmdbuf *cs);
1631 void si_pc_emit_spm_stop(struct radeon_cmdbuf *cs, bool never_stop_sq_perf_counters,
1632 bool never_send_perfcounter_stop);
1633 void si_pc_emit_spm_reset(struct radeon_cmdbuf *cs);
1634 void si_emit_spm_setup(struct si_context *sctx, struct radeon_cmdbuf *cs);
1635 bool si_spm_init(struct si_context *sctx);
1636 void si_spm_finish(struct si_context *sctx);
1637
1638 /* si_query.c */
1639 void si_init_screen_query_functions(struct si_screen *sscreen);
1640 void si_init_query_functions(struct si_context *sctx);
1641 void si_suspend_queries(struct si_context *sctx);
1642 void si_resume_queries(struct si_context *sctx);
1643
1644 /* si_shaderlib_nir.c */
1645
1646 void *si_create_shader_state(struct si_context *sctx, struct nir_shader *nir);
1647 void *si_create_dcc_retile_cs(struct si_context *sctx, struct radeon_surf *surf);
1648 void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *tex);
1649 void *si_create_passthrough_tcs(struct si_context *sctx);
1650 void *si_clear_image_dcc_single_shader(struct si_context *sctx, bool is_msaa, unsigned wg_dim);
1651 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1652 unsigned num_layers);
1653 void *si_create_ubyte_to_ushort_compute_shader(struct si_context *sctx);
1654 void *si_create_clear_buffer_rmw_cs(struct si_context *sctx);
1655 void *si_create_fmask_expand_cs(struct si_context *sctx, unsigned num_samples, bool is_array);
1656 void *si_create_query_result_cs(struct si_context *sctx);
1657 void *gfx11_create_sh_query_result_cs(struct si_context *sctx);
1658
1659 /* gfx11_query.c */
1660 void si_gfx11_init_query(struct si_context *sctx);
1661 void si_gfx11_destroy_query(struct si_context *sctx);
1662
1663 /* si_test_image_copy_region.c */
1664 void si_test_image_copy_region(struct si_screen *sscreen);
1665 void si_test_blit(struct si_screen *sscreen, unsigned test_flags);
1666
1667 /* si_test_dma_perf.c */
1668 void si_test_dma_perf(struct si_screen *sscreen);
1669 void si_test_mem_perf(struct si_screen *sscreen);
1670 void si_test_clear_buffer(struct si_screen *sscreen);
1671 void si_test_copy_buffer(struct si_screen *sscreen);
1672
1673 /* si_test_blit_perf.c */
1674 void si_test_blit_perf(struct si_screen *sscreen);
1675
1676 /* si_uvd.c */
1677 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1678 const struct pipe_video_codec *templ);
1679
1680 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1681 const struct pipe_video_buffer *tmpl);
1682 struct pipe_video_buffer *si_video_buffer_create_with_modifiers(struct pipe_context *pipe,
1683 const struct pipe_video_buffer *tmpl,
1684 const uint64_t *modifiers,
1685 unsigned int modifiers_count);
1686
1687 /* si_state_viewport.c */
1688 void si_update_vs_viewport_state(struct si_context *ctx);
1689 void si_init_viewport_functions(struct si_context *ctx);
1690
1691 /* si_texture.c */
1692 void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex,
1693 bool *ctx_flushed);
1694 void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex);
1695 bool si_init_flushed_depth_texture(struct pipe_context *ctx, struct pipe_resource *texture);
1696 void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
1697 struct u_log_context *log);
1698 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1699 const struct pipe_resource *templ);
1700 bool si_texture_commit(struct si_context *ctx, struct si_resource *res, unsigned level,
1701 struct pipe_box *box, bool commit);
1702 bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format format1,
1703 enum pipe_format format2);
1704 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level,
1705 enum pipe_format view_format);
1706 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex,
1707 unsigned level, enum pipe_format view_format);
1708 bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex);
1709 void si_init_screen_texture_functions(struct si_screen *sscreen);
1710 void si_init_context_texture_functions(struct si_context *sctx);
1711
1712 /* si_sqtt.c */
1713 void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1714 enum rgp_sqtt_marker_event_type api_type,
1715 uint32_t vertex_offset_user_data,
1716 uint32_t instance_offset_user_data,
1717 uint32_t draw_index_user_data);
1718 bool si_sqtt_register_pipeline(struct si_context* sctx, struct si_sqtt_fake_pipeline *pipeline,
1719 uint32_t *gfx_sh_offsets);
1720 bool si_sqtt_pipeline_is_registered(struct ac_sqtt *sqtt,
1721 uint64_t pipeline_hash);
1722 void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point);
1723 void
1724 si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1725 enum rgp_sqtt_marker_event_type api_type,
1726 uint32_t x, uint32_t y, uint32_t z);
1727 void
1728 si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1729 enum rgp_sqtt_marker_user_event_type type,
1730 const char *str, int len);
1731 void
1732 si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs);
1733 void
1734 si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs, unsigned flags);
1735 bool si_init_sqtt(struct si_context *sctx);
1736 void si_destroy_sqtt(struct si_context *sctx);
1737 void si_handle_sqtt(struct si_context *sctx, struct radeon_cmdbuf *rcs);
1738
1739 /*
1740 * common helpers
1741 */
1742
1743 /* Use this helper when casting pipe_resouce::screen to get a real si_screen
1744 * instance (= this is only useful when intending to access si_screen members directly)
1745 */
1746 static inline struct si_screen *
si_screen(struct pipe_screen * pscreen)1747 si_screen(struct pipe_screen *pscreen)
1748 {
1749 struct pipe_screen *s =
1750 pscreen->get_driver_pipe_screen ? pscreen->get_driver_pipe_screen(pscreen) : pscreen;
1751 assert(s->destroy == si_destroy_screen);
1752 return (struct si_screen *)s;
1753 }
1754
si_compute_reference(struct si_compute ** dst,struct si_compute * src)1755 static inline void si_compute_reference(struct si_compute **dst, struct si_compute *src)
1756 {
1757 if (pipe_reference(&(*dst)->sel.base.reference, &src->sel.base.reference))
1758 si_destroy_compute(*dst);
1759
1760 *dst = src;
1761 }
1762
si_resource(struct pipe_resource * r)1763 static inline struct si_resource *si_resource(struct pipe_resource *r)
1764 {
1765 return (struct si_resource *)r;
1766 }
1767
si_resource_reference(struct si_resource ** ptr,struct si_resource * res)1768 static inline void si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1769 {
1770 pipe_resource_reference((struct pipe_resource **)ptr, (struct pipe_resource *)res);
1771 }
1772
si_texture_reference(struct si_texture ** ptr,struct si_texture * res)1773 static inline void si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1774 {
1775 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1776 }
1777
1778 static inline void
si_shader_selector_reference(struct si_context * sctx,struct si_shader_selector ** dst,struct si_shader_selector * src)1779 si_shader_selector_reference(struct si_context *sctx, /* sctx can optionally be NULL */
1780 struct si_shader_selector **dst, struct si_shader_selector *src)
1781 {
1782 if (*dst == src)
1783 return;
1784
1785 struct si_screen *sscreen = src ? src->screen : (*dst)->screen;
1786 util_shader_reference(&sctx->b, &sscreen->live_shader_cache, (void **)dst, src);
1787 }
1788
vi_dcc_enabled(struct si_texture * tex,unsigned level)1789 static inline bool vi_dcc_enabled(struct si_texture *tex, unsigned level)
1790 {
1791 /* Gfx12 always returns false because DCC is transparent to the driver.
1792 * I think DCC doesn't have to be disabled if a color buffer is simultaneously bound as a sampler.
1793 */
1794 return !tex->is_depth && tex->surface.meta_offset && level < tex->surface.num_meta_levels;
1795 }
1796
si_get_minimum_num_gfx_cs_dwords(struct si_context * sctx,unsigned num_draws)1797 static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx,
1798 unsigned num_draws)
1799 {
1800 /* Don't count the needed CS space exactly and just use an upper bound.
1801 *
1802 * Also reserve space for stopping queries at the end of IB, because
1803 * the number of active queries is unlimited in theory.
1804 */
1805 return 2048 + sctx->num_cs_dw_queries_suspend + num_draws * 10;
1806 }
1807
si_get_atom_bit(struct si_context * sctx,struct si_atom * atom)1808 static inline uint64_t si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1809 {
1810 return 1ull << (atom - sctx->atoms.array);
1811 }
1812
si_set_atom_dirty(struct si_context * sctx,struct si_atom * atom,bool dirty)1813 static inline void si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1814 {
1815 uint64_t bit = si_get_atom_bit(sctx, atom);
1816
1817 if (dirty)
1818 sctx->dirty_atoms |= bit;
1819 else
1820 sctx->dirty_atoms &= ~bit;
1821 }
1822
si_is_atom_dirty(struct si_context * sctx,struct si_atom * atom)1823 static inline bool si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1824 {
1825 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1826 }
1827
si_mark_atom_dirty(struct si_context * sctx,struct si_atom * atom)1828 static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1829 {
1830 si_set_atom_dirty(sctx, atom, true);
1831 }
1832
1833 /* This should be evaluated at compile time if all parameters except sctx are constants. */
1834 static ALWAYS_INLINE struct si_shader_ctx_state *
si_get_vs_inline(struct si_context * sctx,enum si_has_tess has_tess,enum si_has_gs has_gs)1835 si_get_vs_inline(struct si_context *sctx, enum si_has_tess has_tess, enum si_has_gs has_gs)
1836 {
1837 if (has_gs)
1838 return &sctx->shader.gs;
1839 if (has_tess)
1840 return &sctx->shader.tes;
1841
1842 return &sctx->shader.vs;
1843 }
1844
si_get_vs(struct si_context * sctx)1845 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1846 {
1847 return si_get_vs_inline(sctx, sctx->shader.tes.cso ? TESS_ON : TESS_OFF,
1848 sctx->shader.gs.cso ? GS_ON : GS_OFF);
1849 }
1850
si_get_strmout_en(struct si_context * sctx)1851 static inline bool si_get_strmout_en(struct si_context *sctx)
1852 {
1853 return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled;
1854 }
1855
si_optimal_tcc_alignment(struct si_context * sctx,unsigned upload_size)1856 static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1857 {
1858 unsigned alignment, tcc_cache_line_size;
1859
1860 /* If the upload size is less than the cache line size (e.g. 16, 32),
1861 * the whole thing will fit into a cache line if we align it to its size.
1862 * The idea is that multiple small uploads can share a cache line.
1863 * If the upload size is greater, align it to the cache line size.
1864 */
1865 alignment = util_next_power_of_two(upload_size);
1866 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1867 return MIN2(alignment, tcc_cache_line_size);
1868 }
1869
si_saved_cs_reference(struct si_saved_cs ** dst,struct si_saved_cs * src)1870 static inline void si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1871 {
1872 if (pipe_reference(&(*dst)->reference, &src->reference))
1873 si_destroy_saved_cs(*dst);
1874
1875 *dst = src;
1876 }
1877
si_make_CB_shader_coherent(struct si_context * sctx,unsigned num_samples,bool shaders_read_metadata,bool dcc_pipe_aligned)1878 static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1879 bool shaders_read_metadata, bool dcc_pipe_aligned)
1880 {
1881 sctx->barrier_flags |= SI_BARRIER_SYNC_AND_INV_CB | SI_BARRIER_INV_VMEM;
1882 sctx->force_shader_coherency.with_cb = false;
1883
1884 if (sctx->gfx_level >= GFX10 && sctx->gfx_level < GFX12) {
1885 if (sctx->screen->info.tcc_rb_non_coherent)
1886 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1887 else if (shaders_read_metadata)
1888 sctx->barrier_flags |= SI_BARRIER_INV_L2_METADATA;
1889 } else if (sctx->gfx_level == GFX9) {
1890 /* Single-sample color is coherent with shaders on GFX9, but
1891 * L2 metadata must be flushed if shaders read metadata.
1892 * (DCC, CMASK).
1893 */
1894 if (num_samples >= 2 || (shaders_read_metadata && !dcc_pipe_aligned))
1895 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1896 else if (shaders_read_metadata)
1897 sctx->barrier_flags |= SI_BARRIER_INV_L2_METADATA;
1898 } else if (sctx->gfx_level <= GFX8) {
1899 /* GFX6-GFX8 */
1900 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1901 }
1902
1903 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1904 }
1905
si_make_DB_shader_coherent(struct si_context * sctx,unsigned num_samples,bool include_stencil,bool shaders_read_metadata)1906 static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1907 bool include_stencil, bool shaders_read_metadata)
1908 {
1909 sctx->barrier_flags |= SI_BARRIER_SYNC_AND_INV_DB | SI_BARRIER_INV_VMEM;
1910 sctx->force_shader_coherency.with_db = false;
1911
1912 if (sctx->gfx_level >= GFX10 && sctx->gfx_level < GFX12) {
1913 if (sctx->screen->info.tcc_rb_non_coherent)
1914 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1915 else if (shaders_read_metadata)
1916 sctx->barrier_flags |= SI_BARRIER_INV_L2_METADATA;
1917 } else if (sctx->gfx_level == GFX9) {
1918 /* Single-sample depth (not stencil) is coherent with shaders
1919 * on GFX9, but L2 metadata must be flushed if shaders read
1920 * metadata.
1921 */
1922 if (num_samples >= 2 || include_stencil)
1923 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1924 else if (shaders_read_metadata)
1925 sctx->barrier_flags |= SI_BARRIER_INV_L2_METADATA;
1926 } else if (sctx->gfx_level <= GFX8) {
1927 /* GFX6-GFX8 */
1928 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1929 }
1930
1931 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1932 }
1933
si_can_sample_zs(struct si_texture * tex,bool stencil_sampler)1934 static inline bool si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1935 {
1936 return (stencil_sampler && tex->can_sample_s) || (!stencil_sampler && tex->can_sample_z);
1937 }
1938
si_htile_enabled(struct si_texture * tex,unsigned level,unsigned zs_mask)1939 static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1940 {
1941 struct si_screen *sscreen = si_screen(tex->buffer.b.b.screen);
1942
1943 /* Gfx12 should never call this. */
1944 assert(sscreen->info.gfx_level < GFX12);
1945
1946 if (zs_mask == PIPE_MASK_S && (tex->htile_stencil_disabled || !tex->surface.has_stencil))
1947 return false;
1948
1949 if (!tex->is_depth || !tex->surface.meta_offset)
1950 return false;
1951
1952 if (sscreen->info.gfx_level >= GFX8) {
1953 return level < tex->surface.num_meta_levels;
1954 } else {
1955 /* GFX6-7 don't have TC-compatible HTILE, which means they have to run
1956 * a decompression pass for every mipmap level before texturing, so compress
1957 * only one level to reduce the number of decompression passes to a minimum.
1958 */
1959 return level == 0;
1960 }
1961 }
1962
vi_tc_compat_htile_enabled(struct si_texture * tex,unsigned level,unsigned zs_mask)1963 static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level,
1964 unsigned zs_mask)
1965 {
1966 struct si_screen *sscreen = si_screen(tex->buffer.b.b.screen);
1967
1968 /* Gfx12 should never call this. */
1969 assert(sscreen->info.gfx_level < GFX12);
1970
1971 assert(!tex->tc_compatible_htile || tex->surface.meta_offset);
1972 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1973 }
1974
si_get_ps_iter_samples(struct si_context * sctx)1975 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1976 {
1977 if (sctx->gfx11_force_msaa_num_samples_zero)
1978 return 1;
1979
1980 if (sctx->ps_uses_fbfetch)
1981 return sctx->framebuffer.nr_color_samples;
1982
1983 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1984 }
1985
si_any_colorbuffer_written(struct si_context * sctx)1986 static inline bool si_any_colorbuffer_written(struct si_context *sctx)
1987 {
1988 if (sctx->queued.named.rasterizer->rasterizer_discard)
1989 return false;
1990
1991 struct si_shader_selector *ps = sctx->shader.ps.cso;
1992 if (!ps || !ps->info.colors_written_4bit)
1993 return false;
1994
1995 return (sctx->framebuffer.colorbuf_enabled_4bit &
1996 sctx->queued.named.blend->cb_target_enabled_4bit &
1997 (ps->info.color0_writes_all_cbufs ? ~0 : ps->info.colors_written_4bit)) != 0;
1998 }
1999
2000 #define UTIL_ALL_PRIM_LINE_MODES \
2001 ((1 << MESA_PRIM_LINES) | (1 << MESA_PRIM_LINE_LOOP) | (1 << MESA_PRIM_LINE_STRIP) | \
2002 (1 << MESA_PRIM_LINES_ADJACENCY) | (1 << MESA_PRIM_LINE_STRIP_ADJACENCY))
2003
2004 #define UTIL_ALL_PRIM_TRIANGLE_MODES \
2005 ((1 << MESA_PRIM_TRIANGLES) | (1 << MESA_PRIM_TRIANGLE_STRIP) | \
2006 (1 << MESA_PRIM_TRIANGLE_FAN) | (1 << MESA_PRIM_QUADS) | (1 << MESA_PRIM_QUAD_STRIP) | \
2007 (1 << MESA_PRIM_POLYGON) | (1 << MESA_PRIM_TRIANGLES_ADJACENCY) | \
2008 (1 << MESA_PRIM_TRIANGLE_STRIP_ADJACENCY))
2009
util_prim_is_lines(unsigned prim)2010 static inline bool util_prim_is_lines(unsigned prim)
2011 {
2012 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
2013 }
2014
util_prim_is_points_or_lines(unsigned prim)2015 static inline bool util_prim_is_points_or_lines(unsigned prim)
2016 {
2017 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | (1 << MESA_PRIM_POINTS))) != 0;
2018 }
2019
util_rast_prim_is_triangles(unsigned prim)2020 static inline bool util_rast_prim_is_triangles(unsigned prim)
2021 {
2022 return ((1 << prim) & UTIL_ALL_PRIM_TRIANGLE_MODES) != 0;
2023 }
2024
util_rast_prim_is_lines_or_triangles(unsigned prim)2025 static inline bool util_rast_prim_is_lines_or_triangles(unsigned prim)
2026 {
2027 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | UTIL_ALL_PRIM_TRIANGLE_MODES)) != 0;
2028 }
2029
si_need_gfx_cs_space(struct si_context * ctx,unsigned num_draws)2030 static inline void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws)
2031 {
2032 struct radeon_cmdbuf *cs = &ctx->gfx_cs;
2033
2034 if (!ctx->ws->cs_check_space(cs, si_get_minimum_num_gfx_cs_dwords(ctx, num_draws)))
2035 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2036 }
2037
2038 /**
2039 * Add a buffer to the buffer list for the given command stream (CS).
2040 *
2041 * All buffers used by a CS must be added to the list. This tells the kernel
2042 * driver which buffers are used by GPU commands. Other buffers can
2043 * be swapped out (not accessible) during execution.
2044 *
2045 * The buffer list becomes empty after every context flush and must be
2046 * rebuilt.
2047 */
radeon_add_to_buffer_list(struct si_context * sctx,struct radeon_cmdbuf * cs,struct si_resource * bo,unsigned usage)2048 static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs,
2049 struct si_resource *bo, unsigned usage)
2050 {
2051 assert(usage);
2052 sctx->ws->cs_add_buffer(cs, bo->buf, usage | RADEON_USAGE_SYNCHRONIZED,
2053 bo->domains);
2054 }
2055
si_select_draw_vbo(struct si_context * sctx)2056 static inline void si_select_draw_vbo(struct si_context *sctx)
2057 {
2058 pipe_draw_func draw_vbo = sctx->draw_vbo[!!sctx->shader.tes.cso]
2059 [!!sctx->shader.gs.cso]
2060 [sctx->ngg];
2061 pipe_draw_vertex_state_func draw_vertex_state =
2062 sctx->draw_vertex_state[!!sctx->shader.tes.cso]
2063 [!!sctx->shader.gs.cso]
2064 [sctx->ngg];
2065 assert(draw_vbo);
2066 assert(draw_vertex_state);
2067
2068 if (unlikely(sctx->real_draw_vbo)) {
2069 assert(sctx->real_draw_vertex_state);
2070 sctx->real_draw_vbo = draw_vbo;
2071 sctx->real_draw_vertex_state = draw_vertex_state;
2072 } else {
2073 assert(!sctx->real_draw_vertex_state);
2074 sctx->b.draw_vbo = draw_vbo;
2075 sctx->b.draw_vertex_state = draw_vertex_state;
2076 }
2077 }
2078
2079 /* Return the number of samples that the rasterizer uses. */
si_get_num_coverage_samples(struct si_context * sctx)2080 static inline unsigned si_get_num_coverage_samples(struct si_context *sctx)
2081 {
2082 if (sctx->framebuffer.nr_samples > 1 &&
2083 sctx->queued.named.rasterizer->multisample_enable)
2084 return sctx->framebuffer.nr_samples;
2085
2086 /* Note that smoothing_enabled is set by si_update_shaders. */
2087 if (sctx->smoothing_enabled)
2088 return SI_NUM_SMOOTH_AA_SAMPLES;
2089
2090 return 1;
2091 }
2092
2093 static unsigned ALWAYS_INLINE
si_num_vbos_in_user_sgprs_inline(enum amd_gfx_level gfx_level)2094 si_num_vbos_in_user_sgprs_inline(enum amd_gfx_level gfx_level)
2095 {
2096 /* This decreases CPU overhead if all descriptors are in user SGPRs because we don't
2097 * have to allocate and count references for the upload buffer.
2098 */
2099 return gfx_level >= GFX9 ? 5 : 1;
2100 }
2101
si_num_vbos_in_user_sgprs(struct si_screen * sscreen)2102 static inline unsigned si_num_vbos_in_user_sgprs(struct si_screen *sscreen)
2103 {
2104 return si_num_vbos_in_user_sgprs_inline(sscreen->info.gfx_level);
2105 }
2106
2107 static inline
si_check_dirty_buffers_textures(struct si_context * sctx)2108 void si_check_dirty_buffers_textures(struct si_context *sctx)
2109 {
2110 /* Recompute and re-emit the texture resource states if needed. */
2111 unsigned dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
2112 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
2113 sctx->last_dirty_tex_counter = dirty_tex_counter;
2114 sctx->framebuffer.dirty_cbufs |= ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
2115 sctx->framebuffer.dirty_zsbuf = true;
2116 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2117 si_update_all_texture_descriptors(sctx);
2118 }
2119
2120 unsigned dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
2121 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
2122 sctx->last_dirty_buf_counter = dirty_buf_counter;
2123 /* Rebind all buffers unconditionally. */
2124 si_rebind_buffer(sctx, NULL);
2125 }
2126 }
2127
si_set_clip_discard_distance(struct si_context * sctx,float distance)2128 static inline void si_set_clip_discard_distance(struct si_context *sctx, float distance)
2129 {
2130 /* Determine whether the guardband registers change.
2131 *
2132 * When we see a value greater than min_clip_discard_distance_watermark, we increase it
2133 * up to a certain number to eliminate those state changes next time they happen.
2134 * See the comment at min_clip_discard_distance_watermark.
2135 */
2136 if (distance > sctx->min_clip_discard_distance_watermark) {
2137 /* The maximum number was determined from Viewperf. The number is in units of half-pixels. */
2138 sctx->min_clip_discard_distance_watermark = MIN2(distance, 6);
2139
2140 float old_distance = sctx->current_clip_discard_distance;
2141 float new_distance = MAX2(distance, sctx->min_clip_discard_distance_watermark);
2142
2143 if (old_distance != new_distance) {
2144 sctx->current_clip_discard_distance = new_distance;
2145 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
2146 }
2147 }
2148 }
2149
2150 /* Update these two GS_STATE fields. They depend on whatever the last shader before PS is
2151 * and the rasterizer state.
2152 *
2153 * It's expected that hw_vs and ngg are inline constants in draw_vbo after optimizations.
2154 */
2155 static inline void
si_update_ngg_sgpr_state_provoking_vtx(struct si_context * sctx,struct si_shader * hw_vs,bool ngg)2156 si_update_ngg_sgpr_state_provoking_vtx(struct si_context *sctx, struct si_shader *hw_vs, bool ngg)
2157 {
2158 if (ngg && hw_vs && hw_vs->uses_vs_state_provoking_vertex) {
2159 SET_FIELD(sctx->current_gs_state, GS_STATE_PROVOKING_VTX_FIRST,
2160 sctx->queued.named.rasterizer->flatshade_first);
2161 }
2162 }
2163
2164 static inline void
si_update_ngg_sgpr_state_out_prim(struct si_context * sctx,struct si_shader * hw_vs,bool ngg)2165 si_update_ngg_sgpr_state_out_prim(struct si_context *sctx, struct si_shader *hw_vs, bool ngg)
2166 {
2167 if (ngg && hw_vs && hw_vs->uses_gs_state_outprim)
2168 SET_FIELD(sctx->current_gs_state, GS_STATE_OUTPRIM, sctx->gs_out_prim);
2169 }
2170
2171 /* Set the primitive type seen by the rasterizer. GS and tessellation affect this.
2172 * It's expected that hw_vs and ngg are inline constants in draw_vbo after optimizations.
2173 */
2174 static ALWAYS_INLINE void
si_set_rasterized_prim(struct si_context * sctx,enum mesa_prim rast_prim,struct si_shader * hw_vs,bool ngg)2175 si_set_rasterized_prim(struct si_context *sctx, enum mesa_prim rast_prim,
2176 struct si_shader *hw_vs, bool ngg)
2177 {
2178 if (rast_prim != sctx->current_rast_prim) {
2179 bool is_rect = rast_prim == SI_PRIM_RECTANGLE_LIST;
2180 bool is_points = rast_prim == MESA_PRIM_POINTS;
2181 bool is_lines = util_prim_is_lines(rast_prim);
2182
2183 if (is_points) {
2184 si_set_clip_discard_distance(sctx, sctx->queued.named.rasterizer->max_point_size);
2185 sctx->gs_out_prim = V_028A6C_POINTLIST;
2186 } else if (is_lines) {
2187 si_set_clip_discard_distance(sctx, sctx->queued.named.rasterizer->line_width);
2188 sctx->gs_out_prim = V_028A6C_LINESTRIP;
2189 } else if (is_rect) {
2190 /* Don't change the clip discard distance for rectangles. */
2191 sctx->gs_out_prim = V_028A6C_RECTLIST;
2192 } else {
2193 si_set_clip_discard_distance(sctx, 0);
2194 sctx->gs_out_prim = V_028A6C_TRISTRIP;
2195 }
2196
2197 sctx->current_rast_prim = rast_prim;
2198 si_vs_ps_key_update_rast_prim_smooth_stipple(sctx);
2199 si_update_ngg_sgpr_state_out_prim(sctx, hw_vs, ngg);
2200 }
2201 }
2202
2203 /* There are 3 ways to flush caches and all of them are correct.
2204 *
2205 * 1) sctx->flags |= ...;
2206 * si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier); // deferred
2207 *
2208 * 2) sctx->flags |= ...;
2209 * si_emit_barrier_direct(sctx); // immediate
2210 *
2211 * 3) sctx->flags |= ...;
2212 * sctx->emit_barrier(sctx, cs); // immediate (2 is better though)
2213 */
si_emit_barrier_direct(struct si_context * sctx)2214 static inline void si_emit_barrier_direct(struct si_context *sctx)
2215 {
2216 if (sctx->barrier_flags) {
2217 sctx->emit_barrier(sctx, &sctx->gfx_cs);
2218 sctx->dirty_atoms &= ~SI_ATOM_BIT(barrier);
2219 }
2220 }
2221
2222 #define PRINT_ERR(fmt, args...) \
2223 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
2224
2225 #ifdef __cplusplus
2226 }
2227 #endif
2228
2229 #endif
2230