1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _EDP_REG_H_ 4 #define _EDP_REG_H_ 5 6 #include <types.h> 7 8 struct edp_ahbclk_regs { 9 uint32_t hw_version; 10 uint32_t reserved0[3]; 11 uint32_t sw_reset; 12 uint32_t phy_ctrl; 13 uint32_t clk_ctrl; 14 uint32_t clk_active; 15 uint32_t interrupt_status; 16 uint32_t interrupt_status2; 17 uint32_t interrupt_status3; 18 }; 19 20 check_member(edp_ahbclk_regs, sw_reset, 0x10); 21 22 struct edp_auxclk_regs { 23 uint32_t hpd_ctrl; 24 uint32_t hpd_int_status; 25 uint32_t hpd_int_ack; 26 uint32_t hpd_int_mask; 27 uint32_t reserved0[2]; 28 uint32_t hpd_reftimer; 29 uint32_t hpd_event_time0; 30 uint32_t hpd_event_time1; 31 uint32_t reserved1[3]; 32 uint32_t aux_ctrl; 33 uint32_t aux_data; 34 uint32_t aux_trans_ctrl; 35 uint32_t timeout_count; 36 uint32_t aux_limits; 37 uint32_t status; 38 uint32_t reserved2[22]; 39 uint32_t interrupt_trans_num; 40 }; 41 check_member(edp_auxclk_regs, hpd_reftimer, 0x18); 42 check_member(edp_auxclk_regs, aux_ctrl, 0x30); 43 check_member(edp_auxclk_regs, interrupt_trans_num, 0xa0); 44 45 struct edp_lclk_regs { 46 uint32_t mainlink_ctrl; 47 uint32_t state_ctrl; 48 uint32_t configuration_ctrl; 49 uint32_t top_bot_interlaced_num_of_lanes; 50 uint32_t software_mvid; 51 uint32_t reserved0; 52 uint32_t software_nvid; 53 uint32_t total_hor_ver; 54 uint32_t start_hor_ver_from_sync; 55 uint32_t hysnc_vsync_width_polarity; 56 uint32_t active_hor_ver; 57 uint32_t misc1_misc0; 58 uint32_t valid_boundary; 59 uint32_t valid_boundary2; 60 uint32_t logcial2physical_lane_mapping; 61 uint32_t reserved1; 62 uint32_t mainlink_ready; 63 uint32_t mainlink_levels; 64 uint32_t mainlink_levels2; 65 uint32_t tu; 66 }; 67 68 struct edp_p0clk_regs { 69 uint32_t bist_enable; 70 uint32_t reserved0[3]; 71 uint32_t timing_engine_en; 72 uint32_t intf_config; 73 uint32_t hsync_ctl; 74 uint32_t vsync_period_f0; 75 uint32_t vsync_period_f1; 76 uint32_t vsync_pulse_width_f0; 77 uint32_t vsync_pulse_width_f1; 78 uint32_t display_v_start_f0; 79 uint32_t display_v_start_f1; 80 uint32_t display_v_end_f0; 81 uint32_t display_v_end_f1; 82 uint32_t active_v_start_f0; 83 uint32_t active_v_start_f1; 84 uint32_t active_v_end_f0; 85 uint32_t active_v_end_f1; 86 uint32_t display_hctl; 87 uint32_t active_hctl; 88 uint32_t hsync_skew; 89 uint32_t polarity_ctl; 90 uint32_t reserved1; 91 uint32_t tpg_main_control; 92 uint32_t tpg_video_config; 93 uint32_t tpg_component_limits; 94 uint32_t tpg_rectangle; 95 uint32_t tpg_initial_value; 96 uint32_t tpg_color_changing_frames; 97 uint32_t tpg_rgb_mapping; 98 uint32_t dsc_dto; 99 }; 100 101 check_member(edp_p0clk_regs, dsc_dto, 0x7c); 102 103 struct edp_phy_regs { 104 uint32_t revision_id0; 105 uint32_t revision_id1; 106 uint32_t revision_id2; 107 uint32_t revision_id3; 108 uint32_t cfg; 109 uint32_t cfg1; 110 uint32_t cfg2; 111 uint32_t pd_ctl; 112 uint32_t mode; 113 uint32_t aux_cfg[13]; 114 uint32_t aux_interrupt_mask; 115 uint32_t aux_interrupt_clr; 116 uint32_t aux_bist_cfg; 117 uint32_t aux_bist_prbs_seed; 118 uint32_t aux_bist_prbs_poly; 119 uint32_t aux_tx_prog_pat_16b_lsb; 120 uint32_t aux_tx_prog_pat_16b_msb; 121 uint32_t vco_div; 122 uint32_t tsync_ovrd; 123 uint32_t tx0_tx1_lane_ctl; 124 uint32_t tx0_tx1_bist_cfg[4]; 125 uint32_t tx0_tx1_prbs_seed_byte0; 126 uint32_t tx0_tx1_prbs_seed_byte1; 127 uint32_t tx0_tx1_bist_pattern0; 128 uint32_t tx0_tx1_bist_pattern1; 129 uint32_t tx2_tx3_lane_ctl; 130 uint32_t tx2_tx3_bist_cfg[4]; 131 uint32_t tx2_tx3_prbs_seed_byte0; 132 uint32_t tx2_tx3_prbs_seed_byte1; 133 uint32_t tx2_tx3_bist_pattern0; 134 uint32_t tx2_tx3_bist_pattern1; 135 uint32_t misr_ctl; 136 uint32_t debug_bus_sel; 137 uint32_t spare[4]; 138 uint32_t aux_interrupt_status; 139 uint32_t status; 140 }; 141 142 struct edp_phy_lane_regs { 143 uint32_t tx_clk_buf_enable; 144 uint32_t tx_emp_post1_lvl; 145 uint32_t tx_post2_emph; 146 uint32_t tx_boost_lvl_up_dn; 147 uint32_t tx_idle_lvl_large_amp; 148 uint32_t tx_drv_lvl; 149 uint32_t tx_drv_lvl_offset; 150 uint32_t tx_reset_tsync_en; 151 uint32_t tx_pre_emph; 152 uint32_t tx_interface_select; 153 uint32_t tx_tx_band; 154 uint32_t tx_slew_cntl; 155 uint32_t tx_lpb0_cfg[3]; 156 uint32_t tx_rescode_lane_tx; 157 uint32_t tx_rescode_lane_tx1; 158 uint32_t tx_rescode_lane_offset_tx0; 159 uint32_t tx_rescode_lane_offset_tx1; 160 uint32_t tx_serdes_byp_en_out; 161 uint32_t tx_dbg_bus_sel; 162 uint32_t tx_transceiver_bias_en; 163 uint32_t tx_highz_drvr_en; 164 uint32_t tx_tx_pol_inv; 165 uint32_t tx_parrate_rec_detect_idle_en; 166 uint32_t tx_lane_mode1; 167 uint32_t tx_lane_mode2; 168 uint32_t tx_atb_sel1; 169 uint32_t tx_atb_sel2; 170 uint32_t tx_reset_gen_muxes; 171 uint32_t tx_tran_drvr_emp_en; 172 uint32_t tx_vmode_ctrl1; 173 uint32_t tx_lane_dig_config; 174 uint32_t tx_ldo_config; 175 uint32_t tx_dig_bkup_ctrl; 176 }; 177 178 struct edp_phy_pll_regs { 179 uint32_t qserdes_com_atb_sel1; 180 uint32_t qserdes_com_atb_sel2; 181 uint32_t qserdes_com_freq_update; 182 uint32_t qserdes_com_bg_timer; 183 uint32_t qserdes_com_ssc_en_center; 184 uint32_t qserdes_com_ssc_adj_per1; 185 uint32_t qserdes_com_ssc_adj_per2; 186 uint32_t qserdes_com_ssc_per1; 187 uint32_t qserdes_com_ssc_per2; 188 uint32_t qserdes_com_ssc_step_size1_mode0; 189 uint32_t qserdes_com_ssc_step_size2_mode0; 190 uint32_t qserdes_com_ssc_step_size3_mode0; 191 uint32_t qserdes_com_ssc_step_size1_mode1; 192 uint32_t qserdes_com_ssc_step_size2_mode1; 193 uint32_t qserdes_com_ssc_step_size3_mode1; 194 uint32_t qserdes_com_post_div; 195 uint32_t qserdes_com_post_div_mux; 196 uint32_t qserdes_com_bias_en_clkbuflr_en; 197 uint32_t qserdes_com_clk_enable1; 198 uint32_t qserdes_com_sys_clk_ctrl; 199 uint32_t qserdes_com_sysclk_buf_enable; 200 uint32_t qserdes_com_pll_en; 201 uint32_t qserdes_com_pll_ivco; 202 uint32_t qserdes_com_cmn_iterim; 203 uint32_t qserdes_com_cmn_iptrim; 204 uint32_t qserdes_com_ep_clk_detect_ctrl; 205 uint32_t qserdes_com_sysclk_det_comp_status; 206 uint32_t qserdes_com_clk_ep_div_mode0; 207 uint32_t qserdes_com_clk_ep_div_mode1; 208 uint32_t qserdes_com_cp_ctrl_mode0; 209 uint32_t qserdes_com_cp_ctrl_mode1; 210 uint32_t qserdes_com_pll_rctrl_mode0; 211 uint32_t qserdes_com_pll_rctrl_mode1; 212 uint32_t qserdes_com_pll_cctrl_mode0; 213 uint32_t qserdes_com_pll_cctrl_mode1; 214 uint32_t qserdes_com_pll_cntrl; 215 uint32_t qserdes_com_bias_en_ctrl_by_psm; 216 uint32_t qserdes_com_sysclk_en_sel; 217 uint32_t qserdes_com_cml_sysclk_sel; 218 uint32_t qserdes_com_resetsm_cntrl; 219 uint32_t qserdes_com_resetsm_cntrl2; 220 uint32_t qserdes_com_lock_cmp_en; 221 uint32_t qserdes_com_lock_cmp_cfg; 222 uint32_t qserdes_com_lock_cmp1_mode0; 223 uint32_t qserdes_com_lock_cmp2_mode0; 224 uint32_t qserdes_com_lock_cmp1_mode1; 225 uint32_t qserdes_com_lock_cmp2_mode1; 226 uint32_t qserdes_com_dec_start_mode0; 227 uint32_t qserdes_com_dec_start_msb_mode0; 228 uint32_t qserdes_com_dec_start_mode1; 229 uint32_t qserdes_com_dec_start_msb_mode1; 230 uint32_t qserdes_com_div_frac_start1_mode0; 231 uint32_t qserdes_com_div_frac_start2_mode0; 232 uint32_t qserdes_com_div_frac_start3_mode0; 233 uint32_t qserdes_com_div_frac_start1_mode1; 234 uint32_t qserdes_com_div_frac_start2_mode1; 235 uint32_t qserdes_com_div_frac_start3_mode1; 236 uint32_t qserdes_com_integloop_initval; 237 uint32_t qserdes_com_integloop_en; 238 uint32_t qserdes_com_integloop_gain0_mode0; 239 uint32_t qserdes_com_integloop_gain1_mode0; 240 uint32_t qserdes_com_integloop_gain0_mode1; 241 uint32_t qserdes_com_integloop_gain1_mode1; 242 uint32_t qserdes_com_integloop_p_path_gain0; 243 uint32_t qserdes_com_integloop_p_path_gain1; 244 uint32_t qserdes_com_vcoval_deadman_ctrl; 245 uint32_t qserdes_com_vco_tune_ctrl; 246 uint32_t qserdes_com_vco_tune_map; 247 uint32_t qserdes_com_vco_tune1_mode0; 248 uint32_t qserdes_com_vco_tune2_mode0; 249 uint32_t qserdes_com_vco_tune1_mode1; 250 uint32_t qserdes_com_vco_tune2_mode1; 251 uint32_t qserdes_com_vco_tune_initval1; 252 uint32_t qserdes_com_vco_tune_initval2; 253 uint32_t qserdes_com_vco_tune_minval1; 254 uint32_t qserdes_com_vco_tune_minval2; 255 uint32_t qserdes_com_vco_tune_maxval1; 256 uint32_t qserdes_com_vco_tune_maxval2; 257 uint32_t qserdes_com_vco_tune_timer1; 258 uint32_t qserdes_com_vco_tune_timer2; 259 uint32_t qserdes_com_cmn_status; 260 uint32_t qserdes_com_reset_sm_status; 261 uint32_t qserdes_com_restrim_code_status; 262 uint32_t qserdes_com_pllcal_code1_status; 263 uint32_t qserdes_com_pllcal_code2_status; 264 uint32_t qserdes_com_clk_sel; 265 uint32_t qserdes_com_hsclk_sel; 266 uint32_t qserdes_com_hsclk_hs_switch_sel; 267 uint32_t qserdes_com_integloop_bincode_status; 268 uint32_t qserdes_com_pll_analog; 269 uint32_t qserdes_com_coreclk_div_mode0; 270 uint32_t qserdes_com_coreclk_div_mode1; 271 uint32_t qserdes_com_sw_reset; 272 uint32_t qserdes_com_core_clk_en; 273 uint32_t qserdes_com_c_ready_status; 274 uint32_t qserdes_com_cmn_config; 275 uint32_t qserdes_com_cmn_rate_override; 276 uint32_t qserdes_com_svs_mode_clk_sel; 277 }; 278 279 /* EDP_STATE_CTRL */ 280 enum { 281 SW_LINK_TRAINING_PATTERN1 = BIT(0), 282 SW_LINK_TRAINING_PATTERN2 = BIT(1), 283 SW_LINK_TRAINING_PATTERN3 = BIT(2), 284 SW_LINK_TRAINING_PATTERN4 = BIT(3), 285 SW_LINK_SYMBOL_ERROR_RATE_MEASUREMENT = BIT(4), 286 SW_LINK_PRBS7 = BIT(5), 287 SW_LINK_TEST_CUSTOM_80BIT_PATTERN = BIT(6), 288 SW_SEND_VIDEO = BIT(7), 289 SW_PUSH_IDLE = BIT(8), 290 }; 291 292 /* EDP_PHY_AUX_INTERRUPT_CLEAR */ 293 enum { 294 RX_STOP_ERR = BIT(0), 295 RX_DEC_ERR = BIT(1), 296 RX_SYNC_ERR = BIT(2), 297 RX_ALIGN_ERR = BIT(3), 298 TX_REQ_ERR = BIT(4), 299 GLOBE_REQ_CLR = BIT(5), 300 }; 301 302 enum { 303 EDP_CTRL_BASE = 0xAEA0000, 304 DP_EDP_PHY_BASE = 0xAEC0000, 305 }; 306 307 enum { 308 EDP_AHBCLK_BASE = EDP_CTRL_BASE, 309 EDP_AUXCLK_BASE = EDP_CTRL_BASE + 0x200, 310 EDP_LCLK_BASE = EDP_CTRL_BASE + 0x400, 311 EDP_P0CLK_BASE = EDP_CTRL_BASE + 0x1000, 312 EDP_PHY_BASE = DP_EDP_PHY_BASE + 0x2A00, 313 EDP_PHY_LANE_TX0_BASE = DP_EDP_PHY_BASE + 0x2200, 314 EDP_PHY_LANE_TX1_BASE = DP_EDP_PHY_BASE + 0x2600, 315 EDP_PHY_PLL_BASE = DP_EDP_PHY_BASE + 0x2000, 316 }; 317 318 static struct edp_ahbclk_regs *const edp_ahbclk = (void *)EDP_AHBCLK_BASE; 319 static struct edp_auxclk_regs *const edp_auxclk = (void *)EDP_AUXCLK_BASE; 320 static struct edp_lclk_regs *const edp_lclk = (void *)EDP_LCLK_BASE; 321 static struct edp_p0clk_regs *const edp_p0clk = (void *)EDP_P0CLK_BASE; 322 static struct edp_phy_regs *const edp_phy = (void *)EDP_PHY_BASE; 323 static struct edp_phy_lane_regs *const edp_phy_lane_tx0 = (void *)EDP_PHY_LANE_TX0_BASE; 324 static struct edp_phy_lane_regs *const edp_phy_lane_tx1 = (void *)EDP_PHY_LANE_TX1_BASE; 325 static struct edp_phy_pll_regs *const edp_phy_pll = (void *)EDP_PHY_PLL_BASE; 326 327 #endif 328