1 #include <stdbool.h>
2 #include <stdint.h>
3 #include <stdlib.h>
4 #include <stddef.h>
5 #include <string.h>
6
7 #include <linux/api.h>
8 #include <arm/linux/api.h>
9 #include <arm/midr.h>
10 #include <cpuinfo/log.h>
11
12 /*
13 * Size, in chars, of the on-stack buffer used for parsing lines of /proc/cpuinfo.
14 * This is also the limit on the length of a single line.
15 */
16 #define BUFFER_SIZE 1024
17
18
parse_processor_number(const char * processor_start,const char * processor_end)19 static uint32_t parse_processor_number(
20 const char* processor_start,
21 const char* processor_end)
22 {
23 const size_t processor_length = (size_t) (processor_end - processor_start);
24
25 if (processor_length == 0) {
26 cpuinfo_log_warning("Processor number in /proc/cpuinfo is ignored: string is empty");
27 return 0;
28 }
29
30 uint32_t processor_number = 0;
31 for (const char* digit_ptr = processor_start; digit_ptr != processor_end; digit_ptr++) {
32 const uint32_t digit = (uint32_t) (*digit_ptr - '0');
33 if (digit > 10) {
34 cpuinfo_log_warning("non-decimal suffix %.*s in /proc/cpuinfo processor number is ignored",
35 (int) (processor_end - digit_ptr), digit_ptr);
36 break;
37 }
38
39 processor_number = processor_number * 10 + digit;
40 }
41
42 return processor_number;
43 }
44
45 /*
46 * Full list of ARM features reported in /proc/cpuinfo:
47 *
48 * * swp - support for SWP instruction (deprecated in ARMv7, can be removed in future)
49 * * half - support for half-word loads and stores. These instruction are part of ARMv4,
50 * so no need to check it on supported CPUs.
51 * * thumb - support for 16-bit Thumb instruction set. Note that BX instruction is detected
52 * by ARMv4T architecture, not by this flag.
53 * * 26bit - old CPUs merged 26-bit PC and program status register (flags) into 32-bit PC
54 * and had special instructions for working with packed PC. Now it is all deprecated.
55 * * fastmult - most old ARM CPUs could only compute 2 bits of multiplication result per clock
56 * cycle, but CPUs with M suffix (e.g. ARM7TDMI) could compute 4 bits per cycle.
57 * Of course, now it makes no sense.
58 * * fpa - floating point accelerator available. On original ARM ABI all floating-point operations
59 * generated FPA instructions. If FPA was not available, these instructions generated
60 * "illegal operation" interrupts, and the OS processed them by emulating the FPA instructions.
61 * Debian used this ABI before it switched to EABI. Now FPA is deprecated.
62 * * vfp - vector floating point instructions. Available on most modern CPUs (as part of VFPv3).
63 * Required by Android ARMv7A ABI and by Ubuntu on ARM.
64 * Note: there is no flag for VFPv2.
65 * * edsp - V5E instructions: saturating add/sub and 16-bit x 16-bit -> 32/64-bit multiplications.
66 * Required on Android, supported by all CPUs in production.
67 * * java - Jazelle extension. Supported on most CPUs.
68 * * iwmmxt - Intel/Marvell Wireless MMX instructions. 64-bit integer SIMD.
69 * Supported on XScale (Since PXA270) and Sheeva (PJ1, PJ4) architectures.
70 * Note that there is no flag for WMMX2 instructions.
71 * * crunch - Maverick Crunch instructions. Junk.
72 * * thumbee - ThumbEE instructions. Almost no documentation is available.
73 * * neon - NEON instructions (aka Advanced SIMD). MVFR1 register gives more
74 * fine-grained information on particular supported features, but
75 * the Linux kernel exports only a single flag for all of them.
76 * According to ARMv7A docs it also implies the availability of VFPv3
77 * (with 32 double-precision registers d0-d31).
78 * * vfpv3 - VFPv3 instructions. Available on most modern CPUs. Augment VFPv2 by
79 * conversion to/from integers and load constant instructions.
80 * Required by Android ARMv7A ABI and by Ubuntu on ARM.
81 * * vfpv3d16 - VFPv3 instructions with only 16 double-precision registers (d0-d15).
82 * * tls - software thread ID registers.
83 * Used by kernel (and likely libc) for efficient implementation of TLS.
84 * * vfpv4 - fused multiply-add instructions.
85 * * idiva - DIV instructions available in ARM mode.
86 * * idivt - DIV instructions available in Thumb mode.
87 * * vfpd32 - VFP (of any version) with 32 double-precision registers d0-d31.
88 * * lpae - Large Physical Address Extension (physical address up to 40 bits).
89 * * evtstrm - generation of Event Stream by timer.
90 * * aes - AES instructions.
91 * * pmull - Polinomial Multiplication instructions.
92 * * sha1 - SHA1 instructions.
93 * * sha2 - SHA2 instructions.
94 * * crc32 - CRC32 instructions.
95 *
96 * /proc/cpuinfo on ARM is populated in file arch/arm/kernel/setup.c in Linux kernel
97 * Note that some devices may use patched Linux kernels with different feature names.
98 * However, the names above were checked on a large number of /proc/cpuinfo listings.
99 */
parse_features(const char * features_start,const char * features_end,struct cpuinfo_arm_linux_processor processor[restrict static1])100 static void parse_features(
101 const char* features_start,
102 const char* features_end,
103 struct cpuinfo_arm_linux_processor processor[restrict static 1])
104 {
105 const char* feature_start = features_start;
106 const char* feature_end;
107
108 /* Mark the features as valid */
109 processor->flags |= CPUINFO_ARM_LINUX_VALID_FEATURES | CPUINFO_ARM_LINUX_VALID_PROCESSOR;
110
111 do {
112 feature_end = feature_start + 1;
113 for (; feature_end != features_end; feature_end++) {
114 if (*feature_end == ' ') {
115 break;
116 }
117 }
118 const size_t feature_length = (size_t) (feature_end - feature_start);
119
120 switch (feature_length) {
121 case 2:
122 if (memcmp(feature_start, "fp", feature_length) == 0) {
123 #if CPUINFO_ARCH_ARM64
124 processor->features |= CPUINFO_ARM_LINUX_FEATURE_FP;
125 #endif
126 #if CPUINFO_ARCH_ARM
127 } else if (memcmp(feature_start, "wp", feature_length) == 0) {
128 /*
129 * Some AArch64 kernels, including the one on Nexus 5X,
130 * erroneously report "swp" as "wp" to AArch32 programs
131 */
132 processor->features |= CPUINFO_ARM_LINUX_FEATURE_SWP;
133 #endif
134 } else {
135 goto unexpected;
136 }
137 break;
138 case 3:
139 if (memcmp(feature_start, "aes", feature_length) == 0) {
140 #if CPUINFO_ARCH_ARM
141 processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_AES;
142 #elif CPUINFO_ARCH_ARM64
143 processor->features |= CPUINFO_ARM_LINUX_FEATURE_AES;
144 #endif
145 #if CPUINFO_ARCH_ARM
146 } else if (memcmp(feature_start, "swp", feature_length) == 0) {
147 processor->features |= CPUINFO_ARM_LINUX_FEATURE_SWP;
148 } else if (memcmp(feature_start, "fpa", feature_length) == 0) {
149 processor->features |= CPUINFO_ARM_LINUX_FEATURE_FPA;
150 } else if (memcmp(feature_start, "vfp", feature_length) == 0) {
151 processor->features |= CPUINFO_ARM_LINUX_FEATURE_VFP;
152 } else if (memcmp(feature_start, "tls", feature_length) == 0) {
153 processor->features |= CPUINFO_ARM_LINUX_FEATURE_TLS;
154 #endif /* CPUINFO_ARCH_ARM */
155 } else {
156 goto unexpected;
157 }
158 break;
159 case 4:
160 if (memcmp(feature_start, "sha1", feature_length) == 0) {
161 #if CPUINFO_ARCH_ARM
162 processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_SHA1;
163 #elif CPUINFO_ARCH_ARM64
164 processor->features |= CPUINFO_ARM_LINUX_FEATURE_SHA1;
165 #endif
166 } else if (memcmp(feature_start, "sha2", feature_length) == 0) {
167 #if CPUINFO_ARCH_ARM
168 processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_SHA2;
169 #elif CPUINFO_ARCH_ARM64
170 processor->features |= CPUINFO_ARM_LINUX_FEATURE_SHA2;
171 #endif
172 } else if (memcmp(feature_start, "fphp", feature_length) == 0) {
173 #if CPUINFO_ARCH_ARM64
174 processor->features |= CPUINFO_ARM_LINUX_FEATURE_FPHP;
175 #endif
176 } else if (memcmp(feature_start, "fcma", feature_length) == 0) {
177 #if CPUINFO_ARCH_ARM64
178 processor->features |= CPUINFO_ARM_LINUX_FEATURE_FCMA;
179 #endif
180 } else if (memcmp(feature_start, "i8mm", feature_length) == 0) {
181 #if CPUINFO_ARCH_ARM64
182 processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_I8MM;
183 #endif
184 #if CPUINFO_ARCH_ARM
185 } else if (memcmp(feature_start, "half", feature_length) == 0) {
186 processor->features |= CPUINFO_ARM_LINUX_FEATURE_HALF;
187 } else if (memcmp(feature_start, "edsp", feature_length) == 0) {
188 processor->features |= CPUINFO_ARM_LINUX_FEATURE_EDSP;
189 } else if (memcmp(feature_start, "java", feature_length) == 0) {
190 processor->features |= CPUINFO_ARM_LINUX_FEATURE_JAVA;
191 } else if (memcmp(feature_start, "neon", feature_length) == 0) {
192 processor->features |= CPUINFO_ARM_LINUX_FEATURE_NEON;
193 } else if (memcmp(feature_start, "lpae", feature_length) == 0) {
194 processor->features |= CPUINFO_ARM_LINUX_FEATURE_LPAE;
195 } else if (memcmp(feature_start, "tlsi", feature_length) == 0) {
196 /*
197 * Some AArch64 kernels, including the one on Nexus 5X,
198 * erroneously report "tls" as "tlsi" to AArch32 programs
199 */
200 processor->features |= CPUINFO_ARM_LINUX_FEATURE_TLS;
201 #endif /* CPUINFO_ARCH_ARM */
202 } else {
203 goto unexpected;
204 }
205 break;
206 case 5:
207 if (memcmp(feature_start, "pmull", feature_length) == 0) {
208 #if CPUINFO_ARCH_ARM
209 processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_PMULL;
210 #elif CPUINFO_ARCH_ARM64
211 processor->features |= CPUINFO_ARM_LINUX_FEATURE_PMULL;
212 #endif
213 } else if (memcmp(feature_start, "crc32", feature_length) == 0) {
214 #if CPUINFO_ARCH_ARM
215 processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_CRC32;
216 #elif CPUINFO_ARCH_ARM64
217 processor->features |= CPUINFO_ARM_LINUX_FEATURE_CRC32;
218 #endif
219 } else if (memcmp(feature_start, "asimd", feature_length) == 0) {
220 #if CPUINFO_ARCH_ARM64
221 processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMD;
222 #endif
223 } else if (memcmp(feature_start, "cpuid", feature_length) == 0) {
224 #if CPUINFO_ARCH_ARM64
225 processor->features |= CPUINFO_ARM_LINUX_FEATURE_CPUID;
226 #endif
227 } else if (memcmp(feature_start, "jscvt", feature_length) == 0) {
228 #if CPUINFO_ARCH_ARM64
229 processor->features |= CPUINFO_ARM_LINUX_FEATURE_JSCVT;
230 #endif
231 } else if (memcmp(feature_start, "lrcpc", feature_length) == 0) {
232 #if CPUINFO_ARCH_ARM64
233 processor->features |= CPUINFO_ARM_LINUX_FEATURE_LRCPC;
234 #endif
235 #if CPUINFO_ARCH_ARM
236 } else if (memcmp(feature_start, "thumb", feature_length) == 0) {
237 processor->features |= CPUINFO_ARM_LINUX_FEATURE_THUMB;
238 } else if (memcmp(feature_start, "26bit", feature_length) == 0) {
239 processor->features |= CPUINFO_ARM_LINUX_FEATURE_26BIT;
240 } else if (memcmp(feature_start, "vfpv3", feature_length) == 0) {
241 processor->features |= CPUINFO_ARM_LINUX_FEATURE_VFPV3;
242 } else if (memcmp(feature_start, "vfpv4", feature_length) == 0) {
243 processor->features |= CPUINFO_ARM_LINUX_FEATURE_VFPV4;
244 } else if (memcmp(feature_start, "idiva", feature_length) == 0) {
245 processor->features |= CPUINFO_ARM_LINUX_FEATURE_IDIVA;
246 } else if (memcmp(feature_start, "idivt", feature_length) == 0) {
247 processor->features |= CPUINFO_ARM_LINUX_FEATURE_IDIVT;
248 #endif /* CPUINFO_ARCH_ARM */
249 } else {
250 goto unexpected;
251 }
252 break;
253 #if CPUINFO_ARCH_ARM
254 case 6:
255 if (memcmp(feature_start, "iwmmxt", feature_length) == 0) {
256 processor->features |= CPUINFO_ARM_LINUX_FEATURE_IWMMXT;
257 } else if (memcmp(feature_start, "crunch", feature_length) == 0) {
258 processor->features |= CPUINFO_ARM_LINUX_FEATURE_CRUNCH;
259 } else if (memcmp(feature_start, "vfpd32", feature_length) == 0) {
260 processor->features |= CPUINFO_ARM_LINUX_FEATURE_VFPD32;
261 } else {
262 goto unexpected;
263 }
264 break;
265 #endif /* CPUINFO_ARCH_ARM */
266 case 7:
267 if (memcmp(feature_start, "evtstrm", feature_length) == 0) {
268 processor->features |= CPUINFO_ARM_LINUX_FEATURE_EVTSTRM;
269 } else if (memcmp(feature_start, "atomics", feature_length) == 0) {
270 #if CPUINFO_ARCH_ARM64
271 processor->features |= CPUINFO_ARM_LINUX_FEATURE_ATOMICS;
272 #endif
273 } else if (memcmp(feature_start, "asimdhp", feature_length) == 0) {
274 #if CPUINFO_ARCH_ARM64
275 processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDHP;
276 #endif
277 #if CPUINFO_ARCH_ARM
278 } else if (memcmp(feature_start, "thumbee", feature_length) == 0) {
279 processor->features |= CPUINFO_ARM_LINUX_FEATURE_THUMBEE;
280 #endif /* CPUINFO_ARCH_ARM */
281 } else {
282 goto unexpected;
283 }
284 break;
285 case 8:
286 if (memcmp(feature_start, "asimdrdm", feature_length) == 0) {
287 #if CPUINFO_ARCH_ARM64
288 processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM;
289 #endif
290 } else if (memcmp(feature_start, "asimdfhm", feature_length) == 0) {
291 #if CPUINFO_ARCH_ARM64
292 processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDFHM;
293 #endif
294 #if CPUINFO_ARCH_ARM
295 } else if (memcmp(feature_start, "fastmult", feature_length) == 0) {
296 processor->features |= CPUINFO_ARM_LINUX_FEATURE_FASTMULT;
297 } else if (memcmp(feature_start, "vfpv3d16", feature_length) == 0) {
298 processor->features |= CPUINFO_ARM_LINUX_FEATURE_VFPV3D16;
299 #endif /* CPUINFO_ARCH_ARM */
300 } else {
301 goto unexpected;
302 }
303 break;
304 default:
305 unexpected:
306 cpuinfo_log_warning("unexpected /proc/cpuinfo feature \"%.*s\" is ignored",
307 (int) feature_length, feature_start);
308 break;
309 }
310 feature_start = feature_end;
311 for (; feature_start != features_end; feature_start++) {
312 if (*feature_start != ' ') {
313 break;
314 }
315 }
316 } while (feature_start != feature_end);
317 }
318
parse_cpu_architecture(const char * cpu_architecture_start,const char * cpu_architecture_end,struct cpuinfo_arm_linux_processor processor[restrict static1])319 static void parse_cpu_architecture(
320 const char* cpu_architecture_start,
321 const char* cpu_architecture_end,
322 struct cpuinfo_arm_linux_processor processor[restrict static 1])
323 {
324 const size_t cpu_architecture_length = (size_t) (cpu_architecture_end - cpu_architecture_start);
325 /* Early AArch64 kernels report "CPU architecture: AArch64" instead of a numeric value 8 */
326 if (cpu_architecture_length == 7) {
327 if (memcmp(cpu_architecture_start, "AArch64", cpu_architecture_length) == 0) {
328 processor->midr = midr_set_architecture(processor->midr, UINT32_C(0xF));
329 processor->architecture_version = 8;
330 processor->flags |= CPUINFO_ARM_LINUX_VALID_ARCHITECTURE | CPUINFO_ARM_LINUX_VALID_PROCESSOR;
331 return;
332 }
333 }
334
335
336 uint32_t architecture = 0;
337 const char* cpu_architecture_ptr = cpu_architecture_start;
338 for (; cpu_architecture_ptr != cpu_architecture_end; cpu_architecture_ptr++) {
339 const uint32_t digit = (*cpu_architecture_ptr) - '0';
340
341 /* Verify that CPU architecture is a decimal number */
342 if (digit >= 10) {
343 break;
344 }
345
346 architecture = architecture * 10 + digit;
347 }
348
349 if (cpu_architecture_ptr == cpu_architecture_start) {
350 cpuinfo_log_warning("CPU architecture %.*s in /proc/cpuinfo is ignored due to non-digit at the beginning of the string",
351 (int) cpu_architecture_length, cpu_architecture_start);
352 } else {
353 if (architecture != 0) {
354 processor->architecture_version = architecture;
355 processor->flags |= CPUINFO_ARM_LINUX_VALID_ARCHITECTURE | CPUINFO_ARM_LINUX_VALID_PROCESSOR;
356
357 for (; cpu_architecture_ptr != cpu_architecture_end; cpu_architecture_ptr++) {
358 const char feature = *cpu_architecture_ptr;
359 switch (feature) {
360 #if CPUINFO_ARCH_ARM
361 case 'T':
362 processor->architecture_flags |= CPUINFO_ARM_LINUX_ARCH_T;
363 break;
364 case 'E':
365 processor->architecture_flags |= CPUINFO_ARM_LINUX_ARCH_E;
366 break;
367 case 'J':
368 processor->architecture_flags |= CPUINFO_ARM_LINUX_ARCH_J;
369 break;
370 #endif /* CPUINFO_ARCH_ARM */
371 case ' ':
372 case '\t':
373 /* Ignore whitespace at the end */
374 break;
375 default:
376 cpuinfo_log_warning("skipped unknown architectural feature '%c' for ARMv%"PRIu32,
377 feature, architecture);
378 break;
379 }
380 }
381 } else {
382 cpuinfo_log_warning("CPU architecture %.*s in /proc/cpuinfo is ignored due to invalid value (0)",
383 (int) cpu_architecture_length, cpu_architecture_start);
384 }
385 }
386
387 uint32_t midr_architecture = UINT32_C(0xF);
388 #if CPUINFO_ARCH_ARM
389 switch (processor->architecture_version) {
390 case 6:
391 midr_architecture = UINT32_C(0x7); /* ARMv6 */
392 break;
393 case 5:
394 if ((processor->architecture_flags & CPUINFO_ARM_LINUX_ARCH_TEJ) == CPUINFO_ARM_LINUX_ARCH_TEJ) {
395 midr_architecture = UINT32_C(0x6); /* ARMv5TEJ */
396 } else if ((processor->architecture_flags & CPUINFO_ARM_LINUX_ARCH_TE) == CPUINFO_ARM_LINUX_ARCH_TE) {
397 midr_architecture = UINT32_C(0x5); /* ARMv5TE */
398 } else {
399 midr_architecture = UINT32_C(0x4); /* ARMv5T */
400 }
401 break;
402 }
403 #endif
404 processor->midr = midr_set_architecture(processor->midr, midr_architecture);
405 }
406
parse_cpu_part(const char * cpu_part_start,const char * cpu_part_end,struct cpuinfo_arm_linux_processor processor[restrict static1])407 static void parse_cpu_part(
408 const char* cpu_part_start,
409 const char* cpu_part_end,
410 struct cpuinfo_arm_linux_processor processor[restrict static 1])
411 {
412 const size_t cpu_part_length = (size_t) (cpu_part_end - cpu_part_start);
413
414 /*
415 * CPU part should contain hex prefix (0x) and one to three hex digits.
416 * I have never seen less than three digits as a value of this field,
417 * but I don't think it is impossible to see such values in future.
418 * Value can not contain more than three hex digits since
419 * Main ID Register (MIDR) assigns only a 12-bit value for CPU part.
420 */
421 if (cpu_part_length < 3 || cpu_part_length > 5) {
422 cpuinfo_log_warning("CPU part %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)",
423 (int) cpu_part_length, cpu_part_start, cpu_part_length);
424 return;
425 }
426
427 /* Verify the presence of hex prefix */
428 if (cpu_part_start[0] != '0' || cpu_part_start[1] != 'x') {
429 cpuinfo_log_warning("CPU part %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix",
430 (int) cpu_part_length, cpu_part_start);
431 return;
432 }
433
434 /* Verify that characters after hex prefix are hexadecimal digits and decode them */
435 uint32_t cpu_part = 0;
436 for (const char* digit_ptr = cpu_part_start + 2; digit_ptr != cpu_part_end; digit_ptr++) {
437 const char digit_char = *digit_ptr;
438 uint32_t digit;
439 if (digit_char >= '0' && digit_char <= '9') {
440 digit = digit_char - '0';
441 } else if ((uint32_t) (digit_char - 'A') < 6) {
442 digit = 10 + (digit_char - 'A');
443 } else if ((uint32_t) (digit_char - 'a') < 6) {
444 digit = 10 + (digit_char - 'a');
445 } else {
446 cpuinfo_log_warning("CPU part %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character %c at offset %zu",
447 (int) cpu_part_length, cpu_part_start, digit_char, (size_t) (digit_ptr - cpu_part_start));
448 return;
449 }
450 cpu_part = cpu_part * 16 + digit;
451 }
452
453 processor->midr = midr_set_part(processor->midr, cpu_part);
454 processor->flags |= CPUINFO_ARM_LINUX_VALID_PART | CPUINFO_ARM_LINUX_VALID_PROCESSOR;
455 }
456
parse_cpu_implementer(const char * cpu_implementer_start,const char * cpu_implementer_end,struct cpuinfo_arm_linux_processor processor[restrict static1])457 static void parse_cpu_implementer(
458 const char* cpu_implementer_start,
459 const char* cpu_implementer_end,
460 struct cpuinfo_arm_linux_processor processor[restrict static 1])
461 {
462 const size_t cpu_implementer_length = cpu_implementer_end - cpu_implementer_start;
463
464 /*
465 * Value should contain hex prefix (0x) and one or two hex digits.
466 * I have never seen single hex digit as a value of this field,
467 * but I don't think it is impossible in future.
468 * Value can not contain more than two hex digits since
469 * Main ID Register (MIDR) assigns only an 8-bit value for CPU implementer.
470 */
471 switch (cpu_implementer_length) {
472 case 3:
473 case 4:
474 break;
475 default:
476 cpuinfo_log_warning("CPU implementer %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)",
477 (int) cpu_implementer_length, cpu_implementer_start, cpu_implementer_length);
478 return;
479 }
480
481 /* Verify the presence of hex prefix */
482 if (cpu_implementer_start[0] != '0' || cpu_implementer_start[1] != 'x') {
483 cpuinfo_log_warning("CPU implementer %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix",
484 (int) cpu_implementer_length, cpu_implementer_start);
485 return;
486 }
487
488 /* Verify that characters after hex prefix are hexadecimal digits and decode them */
489 uint32_t cpu_implementer = 0;
490 for (const char* digit_ptr = cpu_implementer_start + 2; digit_ptr != cpu_implementer_end; digit_ptr++) {
491 const char digit_char = *digit_ptr;
492 uint32_t digit;
493 if (digit_char >= '0' && digit_char <= '9') {
494 digit = digit_char - '0';
495 } else if ((uint32_t) (digit_char - 'A') < 6) {
496 digit = 10 + (digit_char - 'A');
497 } else if ((uint32_t) (digit_char - 'a') < 6) {
498 digit = 10 + (digit_char - 'a');
499 } else {
500 cpuinfo_log_warning("CPU implementer %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character '%c' at offset %zu",
501 (int) cpu_implementer_length, cpu_implementer_start, digit_char, (size_t) (digit_ptr - cpu_implementer_start));
502 return;
503 }
504 cpu_implementer = cpu_implementer * 16 + digit;
505 }
506
507 processor->midr = midr_set_implementer(processor->midr, cpu_implementer);
508 processor->flags |= CPUINFO_ARM_LINUX_VALID_IMPLEMENTER | CPUINFO_ARM_LINUX_VALID_PROCESSOR;
509 }
510
parse_cpu_variant(const char * cpu_variant_start,const char * cpu_variant_end,struct cpuinfo_arm_linux_processor processor[restrict static1])511 static void parse_cpu_variant(
512 const char* cpu_variant_start,
513 const char* cpu_variant_end,
514 struct cpuinfo_arm_linux_processor processor[restrict static 1])
515 {
516 const size_t cpu_variant_length = cpu_variant_end - cpu_variant_start;
517
518 /*
519 * Value should contain hex prefix (0x) and one hex digit.
520 * Value can not contain more than one hex digits since
521 * Main ID Register (MIDR) assigns only a 4-bit value for CPU variant.
522 */
523 if (cpu_variant_length != 3) {
524 cpuinfo_log_warning("CPU variant %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)",
525 (int) cpu_variant_length, cpu_variant_start, cpu_variant_length);
526 return;
527 }
528
529 /* Skip if there is no hex prefix (0x) */
530 if (cpu_variant_start[0] != '0' || cpu_variant_start[1] != 'x') {
531 cpuinfo_log_warning("CPU variant %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix",
532 (int) cpu_variant_length, cpu_variant_start);
533 return;
534 }
535
536 /* Check if the value after hex prefix is indeed a hex digit and decode it. */
537 const char digit_char = cpu_variant_start[2];
538 uint32_t cpu_variant;
539 if ((uint32_t) (digit_char - '0') < 10) {
540 cpu_variant = (uint32_t) (digit_char - '0');
541 } else if ((uint32_t) (digit_char - 'A') < 6) {
542 cpu_variant = 10 + (uint32_t) (digit_char - 'A');
543 } else if ((uint32_t) (digit_char - 'a') < 6) {
544 cpu_variant = 10 + (uint32_t) (digit_char - 'a');
545 } else {
546 cpuinfo_log_warning("CPU variant %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character '%c'",
547 (int) cpu_variant_length, cpu_variant_start, digit_char);
548 return;
549 }
550
551 processor->midr = midr_set_variant(processor->midr, cpu_variant);
552 processor->flags |= CPUINFO_ARM_LINUX_VALID_VARIANT | CPUINFO_ARM_LINUX_VALID_PROCESSOR;
553 }
554
parse_cpu_revision(const char * cpu_revision_start,const char * cpu_revision_end,struct cpuinfo_arm_linux_processor processor[restrict static1])555 static void parse_cpu_revision(
556 const char* cpu_revision_start,
557 const char* cpu_revision_end,
558 struct cpuinfo_arm_linux_processor processor[restrict static 1])
559 {
560 uint32_t cpu_revision = 0;
561 for (const char* digit_ptr = cpu_revision_start; digit_ptr != cpu_revision_end; digit_ptr++) {
562 const uint32_t digit = (uint32_t) (*digit_ptr - '0');
563
564 /* Verify that the character in CPU revision is a decimal digit */
565 if (digit >= 10) {
566 cpuinfo_log_warning("CPU revision %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu",
567 (int) (cpu_revision_end - cpu_revision_start), cpu_revision_start,
568 *digit_ptr, (size_t) (digit_ptr - cpu_revision_start));
569 return;
570 }
571
572 cpu_revision = cpu_revision * 10 + digit;
573 }
574
575 processor->midr = midr_set_revision(processor->midr, cpu_revision);
576 processor->flags |= CPUINFO_ARM_LINUX_VALID_REVISION | CPUINFO_ARM_LINUX_VALID_PROCESSOR;
577 }
578
579 #if CPUINFO_ARCH_ARM
580 /*
581 * Decode one of the cache-related numbers reported by Linux kernel
582 * for pre-ARMv7 architecture.
583 * An example cache-related information in /proc/cpuinfo:
584 *
585 * I size : 32768
586 * I assoc : 4
587 * I line length : 32
588 * I sets : 256
589 * D size : 16384
590 * D assoc : 4
591 * D line length : 32
592 * D sets : 128
593 *
594 */
parse_cache_number(const char * number_start,const char * number_end,const char * number_name,uint32_t number_ptr[restrict static1],uint32_t flags[restrict static1],uint32_t number_mask)595 static void parse_cache_number(
596 const char* number_start,
597 const char* number_end,
598 const char* number_name,
599 uint32_t number_ptr[restrict static 1],
600 uint32_t flags[restrict static 1],
601 uint32_t number_mask)
602 {
603 uint32_t number = 0;
604 for (const char* digit_ptr = number_start; digit_ptr != number_end; digit_ptr++) {
605 const uint32_t digit = *digit_ptr - '0';
606 if (digit >= 10) {
607 cpuinfo_log_warning("%s %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu",
608 number_name, (int) (number_end - number_start), number_start,
609 *digit_ptr, (size_t) (digit_ptr - number_start));
610 return;
611 }
612
613 number = number * 10 + digit;
614 }
615
616 if (number == 0) {
617 cpuinfo_log_warning("%s %.*s in /proc/cpuinfo is ignored due to invalid value of zero reported by the kernel",
618 number_name, (int) (number_end - number_start), number_start);
619 }
620
621 /* If the number specifies a cache line size, verify that is a reasonable power of 2 */
622 if (number_mask & CPUINFO_ARM_LINUX_VALID_CACHE_LINE) {
623 switch (number) {
624 case 16:
625 case 32:
626 case 64:
627 case 128:
628 break;
629 default:
630 cpuinfo_log_warning("invalid %s %.*s is ignored: a value of 16, 32, 64, or 128 expected",
631 number_name, (int) (number_end - number_start), number_start);
632 }
633 }
634
635 *number_ptr = number;
636 *flags |= number_mask | CPUINFO_ARM_LINUX_VALID_PROCESSOR;
637 }
638 #endif /* CPUINFO_ARCH_ARM */
639
640 struct proc_cpuinfo_parser_state {
641 char* hardware;
642 char* revision;
643 uint32_t processor_index;
644 uint32_t max_processors_count;
645 struct cpuinfo_arm_linux_processor* processors;
646 struct cpuinfo_arm_linux_processor dummy_processor;
647 };
648
649 /*
650 * Decode a single line of /proc/cpuinfo information.
651 * Lines have format <words-with-spaces>[ ]*:[ ]<space-separated words>
652 * An example of /proc/cpuinfo (from Pandaboard-ES):
653 *
654 * Processor : ARMv7 Processor rev 10 (v7l)
655 * processor : 0
656 * BogoMIPS : 1392.74
657 *
658 * processor : 1
659 * BogoMIPS : 1363.33
660 *
661 * Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3
662 * CPU implementer : 0x41
663 * CPU architecture: 7
664 * CPU variant : 0x2
665 * CPU part : 0xc09
666 * CPU revision : 10
667 *
668 * Hardware : OMAP4 Panda board
669 * Revision : 0020
670 * Serial : 0000000000000000
671 */
parse_line(const char * line_start,const char * line_end,struct proc_cpuinfo_parser_state state[restrict static1],uint64_t line_number)672 static bool parse_line(
673 const char* line_start,
674 const char* line_end,
675 struct proc_cpuinfo_parser_state state[restrict static 1],
676 uint64_t line_number)
677 {
678 /* Empty line. Skip. */
679 if (line_start == line_end) {
680 return true;
681 }
682
683 /* Search for ':' on the line. */
684 const char* separator = line_start;
685 for (; separator != line_end; separator++) {
686 if (*separator == ':') {
687 break;
688 }
689 }
690 /* Skip line if no ':' separator was found. */
691 if (separator == line_end) {
692 cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found",
693 (int) (line_end - line_start), line_start);
694 return true;
695 }
696
697 /* Skip trailing spaces in key part. */
698 const char* key_end = separator;
699 for (; key_end != line_start; key_end--) {
700 if (key_end[-1] != ' ' && key_end[-1] != '\t') {
701 break;
702 }
703 }
704 /* Skip line if key contains nothing but spaces. */
705 if (key_end == line_start) {
706 cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: key contains only spaces",
707 (int) (line_end - line_start), line_start);
708 return true;
709 }
710
711 /* Skip leading spaces in value part. */
712 const char* value_start = separator + 1;
713 for (; value_start != line_end; value_start++) {
714 if (*value_start != ' ') {
715 break;
716 }
717 }
718 /* Value part contains nothing but spaces. Skip line. */
719 if (value_start == line_end) {
720 cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: value contains only spaces",
721 (int) (line_end - line_start), line_start);
722 return true;
723 }
724
725 /* Skip trailing spaces in value part (if any) */
726 const char* value_end = line_end;
727 for (; value_end != value_start; value_end--) {
728 if (value_end[-1] != ' ') {
729 break;
730 }
731 }
732
733 const uint32_t processor_index = state->processor_index;
734 const uint32_t max_processors_count = state->max_processors_count;
735 struct cpuinfo_arm_linux_processor* processors = state->processors;
736 struct cpuinfo_arm_linux_processor* processor = &state->dummy_processor;
737 if (processor_index < max_processors_count) {
738 processor = &processors[processor_index];
739 }
740
741 const size_t key_length = key_end - line_start;
742 switch (key_length) {
743 case 6:
744 if (memcmp(line_start, "Serial", key_length) == 0) {
745 /* Usually contains just zeros, useless */
746 #if CPUINFO_ARCH_ARM
747 } else if (memcmp(line_start, "I size", key_length) == 0) {
748 parse_cache_number(value_start, value_end,
749 "instruction cache size", &processor->proc_cpuinfo_cache.i_size,
750 &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_SIZE);
751 } else if (memcmp(line_start, "I sets", key_length) == 0) {
752 parse_cache_number(value_start, value_end,
753 "instruction cache sets", &processor->proc_cpuinfo_cache.i_sets,
754 &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_SETS);
755 } else if (memcmp(line_start, "D size", key_length) == 0) {
756 parse_cache_number(value_start, value_end,
757 "data cache size", &processor->proc_cpuinfo_cache.d_size,
758 &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_SIZE);
759 } else if (memcmp(line_start, "D sets", key_length) == 0) {
760 parse_cache_number(value_start, value_end,
761 "data cache sets", &processor->proc_cpuinfo_cache.d_sets,
762 &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_SETS);
763 #endif /* CPUINFO_ARCH_ARM */
764 } else {
765 goto unknown;
766 }
767 break;
768 #if CPUINFO_ARCH_ARM
769 case 7:
770 if (memcmp(line_start, "I assoc", key_length) == 0) {
771 parse_cache_number(value_start, value_end,
772 "instruction cache associativity", &processor->proc_cpuinfo_cache.i_assoc,
773 &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_WAYS);
774 } else if (memcmp(line_start, "D assoc", key_length) == 0) {
775 parse_cache_number(value_start, value_end,
776 "data cache associativity", &processor->proc_cpuinfo_cache.d_assoc,
777 &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_WAYS);
778 } else {
779 goto unknown;
780 }
781 break;
782 #endif /* CPUINFO_ARCH_ARM */
783 case 8:
784 if (memcmp(line_start, "CPU part", key_length) == 0) {
785 parse_cpu_part(value_start, value_end, processor);
786 } else if (memcmp(line_start, "Features", key_length) == 0) {
787 parse_features(value_start, value_end, processor);
788 } else if (memcmp(line_start, "BogoMIPS", key_length) == 0) {
789 /* BogoMIPS is useless, don't parse */
790 } else if (memcmp(line_start, "Hardware", key_length) == 0) {
791 size_t value_length = value_end - value_start;
792 if (value_length > CPUINFO_HARDWARE_VALUE_MAX) {
793 cpuinfo_log_info(
794 "length of Hardware value \"%.*s\" in /proc/cpuinfo exceeds limit (%d): truncating to the limit",
795 (int) value_length, value_start, CPUINFO_HARDWARE_VALUE_MAX);
796 value_length = CPUINFO_HARDWARE_VALUE_MAX;
797 } else {
798 state->hardware[value_length] = '\0';
799 }
800 memcpy(state->hardware, value_start, value_length);
801 cpuinfo_log_debug("parsed /proc/cpuinfo Hardware = \"%.*s\"", (int) value_length, value_start);
802 } else if (memcmp(line_start, "Revision", key_length) == 0) {
803 size_t value_length = value_end - value_start;
804 if (value_length > CPUINFO_REVISION_VALUE_MAX) {
805 cpuinfo_log_info(
806 "length of Revision value \"%.*s\" in /proc/cpuinfo exceeds limit (%d): truncating to the limit",
807 (int) value_length, value_start, CPUINFO_REVISION_VALUE_MAX);
808 value_length = CPUINFO_REVISION_VALUE_MAX;
809 } else {
810 state->revision[value_length] = '\0';
811 }
812 memcpy(state->revision, value_start, value_length);
813 cpuinfo_log_debug("parsed /proc/cpuinfo Revision = \"%.*s\"", (int) value_length, value_start);
814 } else {
815 goto unknown;
816 }
817 break;
818 case 9:
819 if (memcmp(line_start, "processor", key_length) == 0) {
820 const uint32_t new_processor_index = parse_processor_number(value_start, value_end);
821 if (new_processor_index < processor_index) {
822 /* Strange: decreasing processor number */
823 cpuinfo_log_warning(
824 "unexpectedly low processor number %"PRIu32" following processor %"PRIu32" in /proc/cpuinfo",
825 new_processor_index, processor_index);
826 } else if (new_processor_index > processor_index + 1) {
827 /* Strange, but common: skipped processor $(processor_index + 1) */
828 cpuinfo_log_info(
829 "unexpectedly high processor number %"PRIu32" following processor %"PRIu32" in /proc/cpuinfo",
830 new_processor_index, processor_index);
831 }
832 if (new_processor_index < max_processors_count) {
833 /* Record that the processor was mentioned in /proc/cpuinfo */
834 processors[new_processor_index].flags |= CPUINFO_ARM_LINUX_VALID_PROCESSOR;
835 } else {
836 /* Log and ignore processor */
837 cpuinfo_log_warning("processor %"PRIu32" in /proc/cpuinfo is ignored: index exceeds system limit %"PRIu32,
838 new_processor_index, max_processors_count - 1);
839 }
840 state->processor_index = new_processor_index;
841 return true;
842 } else if (memcmp(line_start, "Processor", key_length) == 0) {
843 /* TODO: parse to fix misreported architecture, similar to Android's cpufeatures */
844 } else {
845 goto unknown;
846 }
847 break;
848 case 11:
849 if (memcmp(line_start, "CPU variant", key_length) == 0) {
850 parse_cpu_variant(value_start, value_end, processor);
851 } else {
852 goto unknown;
853 }
854 break;
855 case 12:
856 if (memcmp(line_start, "CPU revision", key_length) == 0) {
857 parse_cpu_revision(value_start, value_end, processor);
858 } else {
859 goto unknown;
860 }
861 break;
862 #if CPUINFO_ARCH_ARM
863 case 13:
864 if (memcmp(line_start, "I line length", key_length) == 0) {
865 parse_cache_number(value_start, value_end,
866 "instruction cache line size", &processor->proc_cpuinfo_cache.i_line_length,
867 &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_LINE);
868 } else if (memcmp(line_start, "D line length", key_length) == 0) {
869 parse_cache_number(value_start, value_end,
870 "data cache line size", &processor->proc_cpuinfo_cache.d_line_length,
871 &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_LINE);
872 } else {
873 goto unknown;
874 }
875 break;
876 #endif /* CPUINFO_ARCH_ARM */
877 case 15:
878 if (memcmp(line_start, "CPU implementer", key_length) == 0) {
879 parse_cpu_implementer(value_start, value_end, processor);
880 } else if (memcmp(line_start, "CPU implementor", key_length) == 0) {
881 parse_cpu_implementer(value_start, value_end, processor);
882 } else {
883 goto unknown;
884 }
885 break;
886 case 16:
887 if (memcmp(line_start, "CPU architecture", key_length) == 0) {
888 parse_cpu_architecture(value_start, value_end, processor);
889 } else {
890 goto unknown;
891 }
892 break;
893 default:
894 unknown:
895 cpuinfo_log_debug("unknown /proc/cpuinfo key: %.*s", (int) key_length, line_start);
896
897 }
898 return true;
899 }
900
cpuinfo_arm_linux_parse_proc_cpuinfo(char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX],char revision[restrict static CPUINFO_REVISION_VALUE_MAX],uint32_t max_processors_count,struct cpuinfo_arm_linux_processor processors[restrict static max_processors_count])901 bool cpuinfo_arm_linux_parse_proc_cpuinfo(
902 char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX],
903 char revision[restrict static CPUINFO_REVISION_VALUE_MAX],
904 uint32_t max_processors_count,
905 struct cpuinfo_arm_linux_processor processors[restrict static max_processors_count])
906 {
907 struct proc_cpuinfo_parser_state state = {
908 .hardware = hardware,
909 .revision = revision,
910 .processor_index = 0,
911 .max_processors_count = max_processors_count,
912 .processors = processors,
913 };
914 return cpuinfo_linux_parse_multiline_file("/proc/cpuinfo", BUFFER_SIZE,
915 (cpuinfo_line_callback) parse_line, &state);
916 }
917