1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_FCS_H 8 #define SOCFPGA_FCS_H 9 10 /* FCS Definitions */ 11 12 #define FCS_RANDOM_WORD_SIZE 8U 13 #define FCS_PROV_DATA_WORD_SIZE 44U 14 #define FCS_SHA384_WORD_SIZE 12U 15 16 #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 17 #define FCS_RANDOM_EXT_MAX_WORD_SIZE 1020U 18 #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 19 #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 20 21 #define FCS_RANDOM_EXT_OFFSET 3 22 23 #define FCS_MODE_DECRYPT 0x0 24 #define FCS_MODE_ENCRYPT 0x1 25 #define FCS_ENCRYPTION_DATA_0 0x10100 26 #define FCS_DECRYPTION_DATA_0 0x10102 27 #define FCS_OWNER_ID_OFFSET 0xC 28 #define FCS_CRYPTION_CRYPTO_HEADER 0x07000000 29 #define FCS_CRYPTION_RESP_WORD_SIZE 4U 30 #define FCS_CRYPTION_RESP_SIZE_OFFSET 3U 31 32 #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 33 #define PSGSIGMA_SESSION_ID_ONE 0x1 34 #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF 35 36 #define RESERVED_AS_ZERO 0x0 37 /* FCS Single cert */ 38 39 #define FCS_BIG_CNTR_SEL 0x1 40 41 #define FCS_SVN_CNTR_0_SEL 0x2 42 #define FCS_SVN_CNTR_1_SEL 0x3 43 #define FCS_SVN_CNTR_2_SEL 0x4 44 #define FCS_SVN_CNTR_3_SEL 0x5 45 46 #define FCS_BIG_CNTR_VAL_MAX 495U 47 #define FCS_SVN_CNTR_VAL_MAX 64U 48 49 /* FCS Attestation Cert Request Parameter */ 50 51 #define FCS_ATTEST_FIRMWARE_CERT 0x01 52 #define FCS_ATTEST_DEV_ID_SELF_SIGN_CERT 0x02 53 #define FCS_ATTEST_DEV_ID_ENROLL_CERT 0x04 54 #define FCS_ATTEST_ENROLL_SELF_SIGN_CERT 0x08 55 #define FCS_ATTEST_ALIAS_CERT 0x10 56 #define FCS_ATTEST_CERT_MAX_REQ_PARAM 0xFF 57 58 /* FCS Crypto Service */ 59 60 #define FCS_CS_KEY_OBJ_MAX_WORD_SIZE 88U 61 #define FCS_CS_KEY_INFO_MAX_WORD_SIZE 36U 62 #define FCS_CS_KEY_RESP_STATUS_MASK 0xFF 63 #define FCS_CS_KEY_RESP_STATUS_OFFSET 16U 64 65 #define FCS_CS_FIELD_SIZE_MASK 0xFFFF 66 #define FCS_CS_FIELD_FLAG_OFFSET 24 67 #define FCS_CS_FIELD_FLAG_INIT BIT(0) 68 #define FCS_CS_FIELD_FLAG_UPDATE BIT(1) 69 #define FCS_CS_FIELD_FLAG_FINALIZE BIT(2) 70 71 #define FCS_AES_MAX_DATA_SIZE 0x10000000 /* 256 MB */ 72 #define FCS_AES_MIN_DATA_SIZE 0x20 /* 32 Byte */ 73 #define FCS_AES_CMD_MAX_WORD_SIZE 15U 74 75 #define FCS_MAX_DATA_SIZE 0x20000000 /* 512 MB */ 76 #define FCS_MIN_DATA_SIZE 0x8 /* 8 Bytes */ 77 78 #define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U 79 #define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U 80 #define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U 81 #define FCS_MAC_VERIFY_RESP_MAX_WORD_SIZE 4U 82 #define FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET 8U 83 84 #define FCS_ECDSA_GET_PUBKEY_MAX_WORD_SIZE 5U 85 #define FCS_ECDSA_SHA2_DATA_SIGN_CMD_MAX_WORD_SIZE 7U 86 #define FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE 43U 87 #define FCS_ECDSA_HASH_SIGN_CMD_MAX_WORD_SIZE 17U 88 #define FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE 52U 89 #define FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE 29U 90 91 #define FCS_CRYPTO_ECB_BUFFER_SIZE 12U 92 #define FCS_CRYPTO_CBC_CTR_BUFFER_SIZE 28U 93 #define FCS_CRYPTO_BLOCK_MODE_MASK 0x07 94 #define FCS_CRYPTO_ECB_MODE 0x00 95 #define FCS_CRYPTO_CBC_MODE 0x01 96 #define FCS_CRYPTO_CTR_MODE 0x02 97 98 /* FCS Payload Structure */ 99 typedef struct fcs_rng_payload_t { 100 uint32_t session_id; 101 uint32_t context_id; 102 uint32_t crypto_header; 103 uint32_t size; 104 } fcs_rng_payload; 105 106 typedef struct fcs_encrypt_payload_t { 107 uint32_t first_word; 108 uint32_t src_addr; 109 uint32_t src_size; 110 uint32_t dst_addr; 111 uint32_t dst_size; 112 } fcs_encrypt_payload; 113 114 typedef struct fcs_decrypt_payload_t { 115 uint32_t first_word; 116 uint32_t owner_id[2]; 117 uint32_t src_addr; 118 uint32_t src_size; 119 uint32_t dst_addr; 120 uint32_t dst_size; 121 } fcs_decrypt_payload; 122 123 typedef struct fcs_encrypt_ext_payload_t { 124 uint32_t session_id; 125 uint32_t context_id; 126 uint32_t crypto_header; 127 uint32_t src_addr; 128 uint32_t src_size; 129 uint32_t dst_addr; 130 uint32_t dst_size; 131 } fcs_encrypt_ext_payload; 132 133 typedef struct fcs_decrypt_ext_payload_t { 134 uint32_t session_id; 135 uint32_t context_id; 136 uint32_t crypto_header; 137 uint32_t owner_id[2]; 138 uint32_t src_addr; 139 uint32_t src_size; 140 uint32_t dst_addr; 141 uint32_t dst_size; 142 } fcs_decrypt_ext_payload; 143 144 typedef struct psgsigma_teardown_msg_t { 145 uint32_t reserved_word; 146 uint32_t magic_word; 147 uint32_t session_id; 148 } psgsigma_teardown_msg; 149 150 typedef struct fcs_cntr_set_preauth_payload_t { 151 uint32_t first_word; 152 uint32_t counter_value; 153 } fcs_cntr_set_preauth_payload; 154 155 typedef struct fcs_cs_key_payload_t { 156 uint32_t session_id; 157 uint32_t reserved0; 158 uint32_t reserved1; 159 uint32_t key_id; 160 } fcs_cs_key_payload; 161 162 typedef struct fcs_crypto_service_data_t { 163 uint32_t session_id; 164 uint32_t context_id; 165 uint32_t key_id; 166 uint32_t crypto_param_size; 167 uint64_t crypto_param; 168 uint8_t is_updated; 169 } fcs_crypto_service_data; 170 171 typedef struct fcs_crypto_service_aes_data_t { 172 uint32_t session_id; 173 uint32_t context_id; 174 uint32_t param_size; 175 uint32_t key_id; 176 uint32_t crypto_param[7]; 177 uint8_t is_updated; 178 } fcs_crypto_service_aes_data; 179 180 /* Functions Definitions */ 181 182 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 183 uint32_t *mbox_error); 184 int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id, 185 uint32_t size, uint32_t *send_id); 186 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, 187 uint32_t *send_id); 188 uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 189 uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type, 190 int32_t counter_value, 191 uint32_t test_bit, 192 uint32_t *mbox_error); 193 uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, 194 uint32_t dst_addr, uint32_t dst_size, 195 uint32_t *send_id); 196 197 uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, 198 uint32_t dst_addr, uint32_t dst_size, 199 uint32_t *send_id); 200 201 int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id, 202 uint32_t src_addr, uint32_t src_size, 203 uint32_t dst_addr, uint32_t *dst_size, 204 uint32_t *mbox_error); 205 int intel_fcs_decryption_ext(uint32_t sesion_id, uint32_t context_id, 206 uint32_t src_addr, uint32_t src_size, 207 uint32_t dst_addr, uint32_t *dst_size, 208 uint32_t *mbox_error); 209 210 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); 211 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); 212 int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, 213 uint64_t dst_addr, uint32_t *dst_size, 214 uint32_t *mbox_error); 215 int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, 216 uint64_t dst_addr, uint32_t *dst_size, 217 uint32_t *mbox_error); 218 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 219 uint32_t *mbox_error); 220 221 int intel_fcs_create_cert_on_reload(uint32_t cert_request, 222 uint32_t *mbox_error); 223 int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr, 224 uint32_t *dst_size, uint32_t *mbox_error); 225 226 int intel_fcs_open_crypto_service_session(uint32_t *session_id, 227 uint32_t *mbox_error); 228 int intel_fcs_close_crypto_service_session(uint32_t session_id, 229 uint32_t *mbox_error); 230 231 int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size, 232 uint32_t *mbox_error); 233 int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id, 234 uint64_t dst_addr, uint32_t *dst_size, 235 uint32_t *mbox_error); 236 int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id, 237 uint32_t *mbox_error); 238 int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id, 239 uint64_t dst_addr, uint32_t *dst_size, 240 uint32_t *mbox_error); 241 242 int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id, 243 uint32_t key_id, uint32_t param_size, 244 uint64_t param_data, uint32_t *mbox_error); 245 int intel_fcs_get_digest_update_finalize(uint32_t session_id, uint32_t context_id, 246 uint32_t src_addr, uint32_t src_size, 247 uint64_t dst_addr, uint32_t *dst_size, 248 uint8_t is_finalised, uint32_t *mbox_error); 249 int intel_fcs_get_digest_smmu_update_finalize(uint32_t session_id, uint32_t context_id, 250 uint32_t src_addr, uint32_t src_size, 251 uint64_t dst_addr, uint32_t *dst_size, 252 uint8_t is_finalised, uint32_t *mbox_error, 253 uint32_t *send_id); 254 255 int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id, 256 uint32_t key_id, uint32_t param_size, 257 uint64_t param_data, uint32_t *mbox_error); 258 int intel_fcs_mac_verify_update_finalize(uint32_t session_id, uint32_t context_id, 259 uint32_t src_addr, uint32_t src_size, 260 uint64_t dst_addr, uint32_t *dst_size, 261 uint32_t data_size, uint8_t is_finalised, 262 uint32_t *mbox_error); 263 int intel_fcs_mac_verify_smmu_update_finalize(uint32_t session_id, uint32_t context_id, 264 uint32_t src_addr, uint32_t src_size, 265 uint64_t dst_addr, uint32_t *dst_size, 266 uint32_t data_size, uint8_t is_finalised, 267 uint32_t *mbox_error, uint32_t *send_id); 268 269 int intel_fcs_ecdsa_hash_sign_init(uint32_t session_id, uint32_t context_id, 270 uint32_t key_id, uint32_t param_size, 271 uint64_t param_data, uint32_t *mbox_error); 272 int intel_fcs_ecdsa_hash_sign_finalize(uint32_t session_id, uint32_t context_id, 273 uint32_t src_addr, uint32_t src_size, 274 uint64_t dst_addr, uint32_t *dst_size, 275 uint32_t *mbox_error); 276 277 int intel_fcs_ecdsa_hash_sig_verify_init(uint32_t session_id, uint32_t context_id, 278 uint32_t key_id, uint32_t param_size, 279 uint64_t param_data, uint32_t *mbox_error); 280 int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t session_id, uint32_t context_id, 281 uint32_t src_addr, uint32_t src_size, 282 uint64_t dst_addr, uint32_t *dst_size, 283 uint32_t *mbox_error); 284 285 int intel_fcs_ecdsa_sha2_data_sign_init(uint32_t session_id, 286 uint32_t context_id, uint32_t key_id, 287 uint32_t param_size, uint64_t param_data, 288 uint32_t *mbox_error); 289 int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t session_id, 290 uint32_t context_id, uint32_t src_addr, 291 uint32_t src_size, uint64_t dst_addr, 292 uint32_t *dst_size, uint8_t is_finalised, 293 uint32_t *mbox_error); 294 int intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(uint32_t session_id, 295 uint32_t context_id, uint32_t src_addr, 296 uint32_t src_size, uint64_t dst_addr, 297 uint32_t *dst_size, uint8_t is_finalised, 298 uint32_t *mbox_error, uint32_t *send_id); 299 300 int intel_fcs_ecdsa_sha2_data_sig_verify_init(uint32_t session_id, 301 uint32_t context_id, uint32_t key_id, 302 uint32_t param_size, uint64_t param_data, 303 uint32_t *mbox_error); 304 int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t session_id, 305 uint32_t context_id, uint32_t src_addr, 306 uint32_t src_size, uint64_t dst_addr, 307 uint32_t *dst_size, uint32_t data_size, 308 uint8_t is_finalised, uint32_t *mbox_error); 309 int intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(uint32_t session_id, 310 uint32_t context_id, uint32_t src_addr, 311 uint32_t src_size, uint64_t dst_addr, 312 uint32_t *dst_size, uint32_t data_size, 313 uint8_t is_finalised, uint32_t *mbox_error, 314 uint32_t *send_id); 315 316 int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id, 317 uint32_t key_id, uint32_t param_size, 318 uint64_t param_data, uint32_t *mbox_error); 319 int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t session_id, uint32_t context_id, 320 uint64_t dst_addr, uint32_t *dst_size, 321 uint32_t *mbox_error); 322 323 int intel_fcs_ecdh_request_init(uint32_t session_id, uint32_t context_id, 324 uint32_t key_id, uint32_t param_size, 325 uint64_t param_data, uint32_t *mbox_error); 326 int intel_fcs_ecdh_request_finalize(uint32_t session_id, uint32_t context_id, 327 uint32_t src_addr, uint32_t src_size, 328 uint64_t dst_addr, uint32_t *dst_size, 329 uint32_t *mbox_error); 330 331 int intel_fcs_aes_crypt_init(uint32_t session_id, uint32_t context_id, 332 uint32_t key_id, uint64_t param_addr, 333 uint32_t param_size, uint32_t *mbox_error); 334 int intel_fcs_aes_crypt_update_finalize(uint32_t session_id, 335 uint32_t context_id, uint64_t src_addr, 336 uint32_t src_size, uint64_t dst_addr, 337 uint32_t dst_size, uint8_t is_finalised, 338 uint32_t *send_id); 339 340 #endif /* SOCFPGA_FCS_H */ 341