1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_NVIDIA_TEGRA124_EMC_H__ 4 #define __SOC_NVIDIA_TEGRA124_EMC_H__ 5 6 #include <stddef.h> 7 #include <stdint.h> 8 9 enum { 10 EMC_PIN_RESET_MASK = 1 << 8, 11 EMC_PIN_RESET_ACTIVE = 0 << 8, 12 EMC_PIN_RESET_INACTIVE = 1 << 8, 13 EMC_PIN_DQM_MASK = 1 << 4, 14 EMC_PIN_DQM_NORMAL = 0 << 4, 15 EMC_PIN_DQM_INACTIVE = 1 << 4, 16 EMC_PIN_CKE_MASK = 1 << 0, 17 EMC_PIN_CKE_POWERDOWN = 0 << 0, 18 EMC_PIN_CKE_NORMAL = 1 << 0, 19 20 EMC_REF_CMD_MASK = 1 << 0, 21 EMC_REF_CMD_REFRESH = 1 << 0, 22 EMC_REF_NORMAL_MASK = 1 << 1, 23 EMC_REF_NORMAL_INIT = 0 << 1, 24 EMC_REF_NORMAL_ENABLED = 1 << 1, 25 EMC_REF_NUM_SHIFT = 8, 26 EMC_REF_NUM_MASK = 0xFF << EMC_REF_NUM_SHIFT, 27 EMC_REF_DEV_SELECTN_SHIFT = 30, 28 EMC_REF_DEV_SELECTN_MASK = 3 << EMC_REF_DEV_SELECTN_SHIFT, 29 30 EMC_REFCTRL_REF_VALID_MASK = 1 << 31, 31 EMC_REFCTRL_REF_VALID_DISABLED = 0 << 31, 32 EMC_REFCTRL_REF_VALID_ENABLED = 1 << 31, 33 34 EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK = 1 << 1, 35 EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK = 1 << 2, 36 EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK = 1 << 3, 37 38 EMC_NOP_NOP_CMD_SHIFT = 0, 39 EMC_NOP_NOP_CMD_MASK = 1 << EMC_NOP_NOP_CMD_SHIFT, 40 EMC_NOP_NOP_DEV_SELECTN_SHIFT = 30, 41 EMC_NOP_NOP_DEV_SELECTN_MASK = 3 << EMC_NOP_NOP_DEV_SELECTN_SHIFT, 42 43 EMC_TIMING_CONTROL_TIMING_UPDATE = 1, 44 }; 45 46 struct tegra_emc_regs { 47 uint32_t intstatus; /* 0x0 */ 48 uint32_t intmask; /* 0x4 */ 49 uint32_t dbg; /* 0x8 */ 50 uint32_t cfg; /* 0xc */ 51 uint32_t adr_cfg; /* 0x10 */ 52 uint32_t rsvd_0x14[3]; /* 0x14 */ 53 54 uint32_t refctrl; /* 0x20 */ 55 uint32_t pin; /* 0x24 */ 56 uint32_t timing_control; /* 0x28 */ 57 uint32_t rc; /* 0x2c */ 58 uint32_t rfc; /* 0x30 */ 59 uint32_t ras; /* 0x34 */ 60 uint32_t rp; /* 0x38 */ 61 uint32_t r2w; /* 0x3c */ 62 uint32_t w2r; /* 0x40 */ 63 uint32_t r2p; /* 0x44 */ 64 uint32_t w2p; /* 0x48 */ 65 uint32_t rd_rcd; /* 0x4c */ 66 uint32_t wr_rcd; /* 0x50 */ 67 uint32_t rrd; /* 0x54 */ 68 uint32_t rext; /* 0x58 */ 69 uint32_t wdv; /* 0x5c */ 70 uint32_t quse; /* 0x60 */ 71 uint32_t qrst; /* 0x64 */ 72 uint32_t qsafe; /* 0x68 */ 73 uint32_t rdv; /* 0x6c */ 74 uint32_t refresh; /* 0x70 */ 75 uint32_t burst_refresh_num; /* 0x74 */ 76 uint32_t pdex2wr; /* 0x78 */ 77 uint32_t pdex2rd; /* 0x7c */ 78 uint32_t pchg2pden; /* 0x80 */ 79 uint32_t act2pden; /* 0x84 */ 80 uint32_t ar2pden; /* 0x88 */ 81 uint32_t rw2pden; /* 0x8c */ 82 uint32_t txsr; /* 0x90 */ 83 uint32_t tcke; /* 0x94 */ 84 uint32_t tfaw; /* 0x98 */ 85 uint32_t trpab; /* 0x9c */ 86 uint32_t tclkstable; /* 0xa0 */ 87 uint32_t tclkstop; /* 0xa4 */ 88 uint32_t trefbw; /* 0xa8 */ 89 uint32_t rsvd_0xac[1]; /* 0xac */ 90 uint32_t odt_write; /* 0xb0 */ 91 uint32_t odt_read; /* 0xb4 */ 92 uint32_t wext; /* 0xb8 */ 93 uint32_t ctt; /* 0xbc */ 94 uint32_t rfc_slr; /* 0xc0 */ 95 uint32_t mrs_wait_cnt2; /* 0xc4 */ 96 uint32_t mrs_wait_cnt; /* 0xc8 */ 97 uint32_t mrs; /* 0xcc */ 98 uint32_t emrs; /* 0xd0 */ 99 uint32_t ref; /* 0xd4 */ 100 uint32_t pre; /* 0xd8 */ 101 uint32_t nop; /* 0xdc */ 102 uint32_t self_ref; /* 0xe0 */ 103 uint32_t dpd; /* 0xe4 */ 104 uint32_t mrw; /* 0xe8 */ 105 uint32_t mrr; /* 0xec */ 106 uint32_t cmdq; /* 0xf0 */ 107 uint32_t mc2emcq; /* 0xf4 */ 108 uint32_t xm2dqspadctrl3; /* 0xf8 */ 109 uint32_t rsvd_0xfc[1]; /* 0xfc */ 110 uint32_t fbio_spare; /* 0x100 */ 111 uint32_t fbio_cfg5; /* 0x104 */ 112 uint32_t fbio_wrptr_eq_2; /* 0x108 */ 113 uint32_t rsvd_0x10c[2]; /* 0x10c */ 114 115 uint32_t fbio_cfg6; /* 0x114 */ 116 uint32_t rsvd_0x118[2]; /* 0x118 */ 117 118 uint32_t cfg_rsv; /* 0x120 */ 119 uint32_t acpd_control; /* 0x124 */ 120 uint32_t rsvd_0x128[1]; /* 0x128 */ 121 uint32_t emrs2; /* 0x12c */ 122 uint32_t emrs3; /* 0x130 */ 123 uint32_t mrw2; /* 0x134 */ 124 uint32_t mrw3; /* 0x138 */ 125 uint32_t mrw4; /* 0x13c */ 126 uint32_t clken_override; /* 0x140 */ 127 uint32_t r2r; /* 0x144 */ 128 uint32_t w2w; /* 0x148 */ 129 uint32_t einput; /* 0x14c */ 130 uint32_t einput_duration; /* 0x150 */ 131 uint32_t puterm_extra; /* 0x154 */ 132 uint32_t tckesr; /* 0x158 */ 133 uint32_t tpd; /* 0x15c */ 134 uint32_t rsvd_0x160[81]; /* 0x160 */ 135 136 uint32_t auto_cal_config; /* 0x2a4 */ 137 uint32_t auto_cal_interval; /* 0x2a8 */ 138 uint32_t auto_cal_status; /* 0x2ac */ 139 uint32_t req_ctrl; /* 0x2b0 */ 140 uint32_t status; /* 0x2b4 */ 141 uint32_t cfg_2; /* 0x2b8 */ 142 uint32_t cfg_dig_dll; /* 0x2bc */ 143 uint32_t cfg_dig_dll_period; /* 0x2c0 */ 144 uint32_t rsvd_0x2c4[1]; /* 0x2c4 */ 145 uint32_t dig_dll_status; /* 0x2c8 */ 146 uint32_t rdv_mask; /* 0x2cc */ 147 uint32_t wdv_mask; /* 0x2d0 */ 148 uint32_t rsvd_0x2d4[1]; /* 0x2d4 */ 149 uint32_t ctt_duration; /* 0x2d8 */ 150 uint32_t ctt_term_ctrl; /* 0x2dc */ 151 uint32_t zcal_interval; /* 0x2e0 */ 152 uint32_t zcal_wait_cnt; /* 0x2e4 */ 153 uint32_t zcal_mrw_cmd; /* 0x2e8 */ 154 uint32_t zq_cal; /* 0x2ec */ 155 uint32_t xm2cmdpadctrl; /* 0x2f0 */ 156 uint32_t xm2cmdpadctrl2; /* 0x2f4 */ 157 uint32_t xm2dqspadctrl; /* 0x2f8 */ 158 uint32_t xm2dqspadctrl2; /* 0x2fc */ 159 uint32_t xm2dqpadctrl; /* 0x300 */ 160 uint32_t xm2dqpadctrl2; /* 0x304 */ 161 uint32_t xm2clkpadctrl; /* 0x308 */ 162 uint32_t xm2comppadctrl; /* 0x30c */ 163 uint32_t xm2vttgenpadctrl; /* 0x310 */ 164 uint32_t xm2vttgenpadctrl2; /* 0x314 */ 165 uint32_t xm2vttgenpadctrl3; /* 0x318 */ 166 uint32_t emcpaden; /* 0x31c */ 167 uint32_t xm2dqspadctrl4; /* 0x320 */ 168 uint32_t scratch0; /* 0x324 */ 169 uint32_t dll_xform_dqs0; /* 0x328 */ 170 uint32_t dll_xform_dqs1; /* 0x32c */ 171 uint32_t dll_xform_dqs2; /* 0x330 */ 172 uint32_t dll_xform_dqs3; /* 0x334 */ 173 uint32_t dll_xform_dqs4; /* 0x338 */ 174 uint32_t dll_xform_dqs5; /* 0x33c */ 175 uint32_t dll_xform_dqs6; /* 0x340 */ 176 uint32_t dll_xform_dqs7; /* 0x344 */ 177 uint32_t dll_xform_quse0; /* 0x348 */ 178 uint32_t dll_xform_quse1; /* 0x34c */ 179 uint32_t dll_xform_quse2; /* 0x350 */ 180 uint32_t dll_xform_quse3; /* 0x354 */ 181 uint32_t dll_xform_quse4; /* 0x358 */ 182 uint32_t dll_xform_quse5; /* 0x35c */ 183 uint32_t dll_xform_quse6; /* 0x360 */ 184 uint32_t dll_xform_quse7; /* 0x364 */ 185 uint32_t dll_xform_dq0; /* 0x368 */ 186 uint32_t dll_xform_dq1; /* 0x36c */ 187 uint32_t dll_xform_dq2; /* 0x370 */ 188 uint32_t dll_xform_dq3; /* 0x374 */ 189 uint32_t dli_rx_trim0; /* 0x378 */ 190 uint32_t dli_rx_trim1; /* 0x37c */ 191 uint32_t dli_rx_trim2; /* 0x380 */ 192 uint32_t dli_rx_trim3; /* 0x384 */ 193 uint32_t dli_rx_trim4; /* 0x388 */ 194 uint32_t dli_rx_trim5; /* 0x38c */ 195 uint32_t dli_rx_trim6; /* 0x390 */ 196 uint32_t dli_rx_trim7; /* 0x394 */ 197 uint32_t dli_tx_trim0; /* 0x398 */ 198 uint32_t dli_tx_trim1; /* 0x39c */ 199 uint32_t dli_tx_trim2; /* 0x3a0 */ 200 uint32_t dli_tx_trim3; /* 0x3a4 */ 201 uint32_t dli_trim_txdqs0; /* 0x3a8 */ 202 uint32_t dli_trim_txdqs1; /* 0x3ac */ 203 uint32_t dli_trim_txdqs2; /* 0x3b0 */ 204 uint32_t dli_trim_txdqs3; /* 0x3b4 */ 205 uint32_t dli_trim_txdqs4; /* 0x3b8 */ 206 uint32_t dli_trim_txdqs5; /* 0x3bc */ 207 uint32_t dli_trim_txdqs6; /* 0x3c0 */ 208 uint32_t dli_trim_txdqs7; /* 0x3c4 */ 209 uint32_t rsvd_0x3c8[1]; /* 0x3c8 */ 210 uint32_t stall_then_exe_after_clkchange; /* 0x3cc */ 211 uint32_t rsvd_0x3d0[1]; /* 0x3d0 */ 212 uint32_t auto_cal_clk_status; /* 0x3d4 */ 213 uint32_t sel_dpd_ctrl; /* 0x3d8 */ 214 uint32_t pre_refresh_req_cnt; /* 0x3dc */ 215 uint32_t dyn_self_ref_control; /* 0x3e0 */ 216 uint32_t txsrdll; /* 0x3e4 */ 217 uint32_t ccfifo_addr; /* 0x3e8 */ 218 uint32_t ccfifo_data; /* 0x3ec */ 219 uint32_t ccfifo_status; /* 0x3f0 */ 220 uint32_t cdb_cntl_1; /* 0x3f4 */ 221 uint32_t cdb_cntl_2; /* 0x3f8 */ 222 uint32_t xm2clkpadctrl2; /* 0x3fc */ 223 uint32_t swizzle_rank0_byte_cfg; /* 0x400 */ 224 uint32_t swizzle_rank0_byte0; /* 0x404 */ 225 uint32_t swizzle_rank0_byte1; /* 0x408 */ 226 uint32_t swizzle_rank0_byte2; /* 0x40c */ 227 uint32_t swizzle_rank0_byte3; /* 0x410 */ 228 uint32_t swizzle_rank1_byte_cfg; /* 0x414 */ 229 uint32_t swizzle_rank1_byte0; /* 0x418 */ 230 uint32_t swizzle_rank1_byte1; /* 0x41c */ 231 uint32_t swizzle_rank1_byte2; /* 0x420 */ 232 uint32_t swizzle_rank1_byte3; /* 0x424 */ 233 uint32_t ca_training_start; /* 0x428 */ 234 uint32_t ca_training_busy; /* 0x42c */ 235 uint32_t ca_training_cfg; /* 0x430 */ 236 uint32_t ca_training_timing_cntl1; /* 0x434 */ 237 uint32_t ca_training_timing_cntl2; /* 0x438 */ 238 uint32_t ca_training_ca_lead_in; /* 0x43c */ 239 uint32_t ca_training_ca; /* 0x440 */ 240 uint32_t ca_training_ca_lead_out; /* 0x444 */ 241 uint32_t ca_training_result1; /* 0x448 */ 242 uint32_t ca_training_result2; /* 0x44c */ 243 uint32_t ca_training_result3; /* 0x450 */ 244 uint32_t ca_training_result4; /* 0x454 */ 245 uint32_t auto_cal_config2; /* 0x458 */ 246 uint32_t auto_cal_config3; /* 0x45c */ 247 uint32_t auto_cal_status2; /* 0x460 */ 248 uint32_t xm2cmdpadctrl3; /* 0x464 */ 249 uint32_t ibdly; /* 0x468 */ 250 uint32_t dll_xform_addr0; /* 0x46c */ 251 uint32_t dll_xform_addr1; /* 0x470 */ 252 uint32_t dll_xform_addr2; /* 0x474 */ 253 uint32_t dli_addr_trim; /* 0x478 */ 254 uint32_t dsr_vttgen_drv; /* 0x47c */ 255 uint32_t txdsrvttgen; /* 0x480 */ 256 uint32_t xm2cmdpadctrl4; /* 0x484 */ 257 uint32_t xm2cmdpadctrl5; /* 0x488 */ 258 uint32_t rsvd_0x48c[5]; /* 0x48c */ 259 260 uint32_t dll_xform_dqs8; /* 0x4a0 */ 261 uint32_t dll_xform_dqs9; /* 0x4a4 */ 262 uint32_t dll_xform_dqs10; /* 0x4a8 */ 263 uint32_t dll_xform_dqs11; /* 0x4ac */ 264 uint32_t dll_xform_dqs12; /* 0x4b0 */ 265 uint32_t dll_xform_dqs13; /* 0x4b4 */ 266 uint32_t dll_xform_dqs14; /* 0x4b8 */ 267 uint32_t dll_xform_dqs15; /* 0x4bc */ 268 uint32_t dll_xform_quse8; /* 0x4c0 */ 269 uint32_t dll_xform_quse9; /* 0x4c4 */ 270 uint32_t dll_xform_quse10; /* 0x4c8 */ 271 uint32_t dll_xform_quse11; /* 0x4cc */ 272 uint32_t dll_xform_quse12; /* 0x4d0 */ 273 uint32_t dll_xform_quse13; /* 0x4d4 */ 274 uint32_t dll_xform_quse14; /* 0x4d8 */ 275 uint32_t dll_xform_quse15; /* 0x4dc */ 276 uint32_t dll_xform_dq4; /* 0x4e0 */ 277 uint32_t dll_xform_dq5; /* 0x4e4 */ 278 uint32_t dll_xform_dq6; /* 0x4e8 */ 279 uint32_t dll_xform_dq7; /* 0x4ec */ 280 uint32_t rsvd_0x4f0[12]; /* 0x4f0 */ 281 282 uint32_t dli_trim_txdqs8; /* 0x520 */ 283 uint32_t dli_trim_txdqs9; /* 0x524 */ 284 uint32_t dli_trim_txdqs10; /* 0x528 */ 285 uint32_t dli_trim_txdqs11; /* 0x52c */ 286 uint32_t dli_trim_txdqs12; /* 0x530 */ 287 uint32_t dli_trim_txdqs13; /* 0x534 */ 288 uint32_t dli_trim_txdqs14; /* 0x538 */ 289 uint32_t dli_trim_txdqs15; /* 0x53c */ 290 uint32_t cdb_cntl_3; /* 0x540 */ 291 uint32_t xm2dqspadctrl5; /* 0x544 */ 292 uint32_t xm2dqspadctrl6; /* 0x548 */ 293 uint32_t xm2dqpadctrl3; /* 0x54c */ 294 uint32_t dll_xform_addr3; /* 0x550 */ 295 uint32_t dll_xform_addr4; /* 0x554 */ 296 uint32_t dll_xform_addr5; /* 0x558 */ 297 uint32_t rsvd_0x55c[1]; /* 0x55c */ 298 uint32_t cfg_pipe; /* 0x560 */ 299 uint32_t qpop; /* 0x564 */ 300 uint32_t quse_width; /* 0x568 */ 301 uint32_t puterm_width; /* 0x56c */ 302 uint32_t bgbias_ctl0; /* 0x570 */ 303 uint32_t puterm_adj; /* 0x574 */ 304 } __packed; 305 306 check_member(tegra_emc_regs, puterm_adj, 0x574); 307 308 #endif /* __SOC_NVIDIA_TEGRA124_EMC_H__ */ 309