xref: /aosp_15_r20/external/coreboot/src/northbridge/intel/e7505/raminit.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef RAMINIT_H
4 #define RAMINIT_H
5 
6 #include <stdint.h>
7 
8 #define MAX_DIMM_SOCKETS_PER_CHANNEL 4
9 #define MAX_NUM_CHANNELS 2
10 #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)
11 
12 struct mem_controller {
13 	pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller
14 
15 	// SMBus addresses of DIMM slots for each channel,
16 	// in order from closest to MCH to furthest away
17 	// 0 == not present
18 	uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL];
19 	uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
20 };
21 
22 void sdram_initialize(void);
23 
24 #endif /* RAMINIT_H */
25