1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 /*
24 * dc_debug.c
25 *
26 * Created on: Nov 3, 2016
27 * Author: yonsun
28 */
29
30 #include "dm_services.h"
31
32 #include "dc.h"
33
34 #include "core_status.h"
35 #include "core_types.h"
36
37 #include "resource.h"
38
39 #define DC_LOGGER \
40 dc->ctx->logger
41 #define DC_LOGGER_INIT(logger)
42
43
44 #define SURFACE_TRACE(...) do {\
45 if (dc->debug.surface_trace) \
46 DC_LOG_IF_TRACE(__VA_ARGS__); \
47 } while (0)
48
49 #define CLOCK_TRACE(...) do {\
50 if (dc->debug.clock_trace) \
51 DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \
52 } while (0)
53
pre_surface_trace(struct dc * dc,const struct dc_plane_state * const * plane_states,int surface_count)54 void pre_surface_trace(
55 struct dc *dc,
56 const struct dc_plane_state *const *plane_states,
57 int surface_count)
58 {
59 int i;
60 DC_LOGGER_INIT(dc->ctx->logger);
61
62 for (i = 0; i < surface_count; i++) {
63 const struct dc_plane_state *plane_state = plane_states[i];
64
65 SURFACE_TRACE("Planes %d:\n", i);
66
67 SURFACE_TRACE(
68 "plane_state->visible = %d;\n"
69 "plane_state->flip_immediate = %d;\n"
70 "plane_state->address.type = %d;\n"
71 "plane_state->address.grph.addr.quad_part = 0x%llX;\n"
72 "plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n"
73 "plane_state->scaling_quality.h_taps = %d;\n"
74 "plane_state->scaling_quality.v_taps = %d;\n"
75 "plane_state->scaling_quality.h_taps_c = %d;\n"
76 "plane_state->scaling_quality.v_taps_c = %d;\n",
77 plane_state->visible,
78 plane_state->flip_immediate,
79 plane_state->address.type,
80 plane_state->address.grph.addr.quad_part,
81 plane_state->address.grph.meta_addr.quad_part,
82 plane_state->scaling_quality.h_taps,
83 plane_state->scaling_quality.v_taps,
84 plane_state->scaling_quality.h_taps_c,
85 plane_state->scaling_quality.v_taps_c);
86
87 SURFACE_TRACE(
88 "plane_state->src_rect.x = %d;\n"
89 "plane_state->src_rect.y = %d;\n"
90 "plane_state->src_rect.width = %d;\n"
91 "plane_state->src_rect.height = %d;\n"
92 "plane_state->dst_rect.x = %d;\n"
93 "plane_state->dst_rect.y = %d;\n"
94 "plane_state->dst_rect.width = %d;\n"
95 "plane_state->dst_rect.height = %d;\n"
96 "plane_state->clip_rect.x = %d;\n"
97 "plane_state->clip_rect.y = %d;\n"
98 "plane_state->clip_rect.width = %d;\n"
99 "plane_state->clip_rect.height = %d;\n",
100 plane_state->src_rect.x,
101 plane_state->src_rect.y,
102 plane_state->src_rect.width,
103 plane_state->src_rect.height,
104 plane_state->dst_rect.x,
105 plane_state->dst_rect.y,
106 plane_state->dst_rect.width,
107 plane_state->dst_rect.height,
108 plane_state->clip_rect.x,
109 plane_state->clip_rect.y,
110 plane_state->clip_rect.width,
111 plane_state->clip_rect.height);
112
113 SURFACE_TRACE(
114 "plane_state->plane_size.surface_size.x = %d;\n"
115 "plane_state->plane_size.surface_size.y = %d;\n"
116 "plane_state->plane_size.surface_size.width = %d;\n"
117 "plane_state->plane_size.surface_size.height = %d;\n"
118 "plane_state->plane_size.surface_pitch = %d;\n",
119 plane_state->plane_size.surface_size.x,
120 plane_state->plane_size.surface_size.y,
121 plane_state->plane_size.surface_size.width,
122 plane_state->plane_size.surface_size.height,
123 plane_state->plane_size.surface_pitch);
124
125
126 SURFACE_TRACE(
127 "plane_state->tiling_info.gfx8.num_banks = %d;\n"
128 "plane_state->tiling_info.gfx8.bank_width = %d;\n"
129 "plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
130 "plane_state->tiling_info.gfx8.bank_height = %d;\n"
131 "plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
132 "plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
133 "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
134 "plane_state->tiling_info.gfx8.tile_split = %d;\n"
135 "plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
136 "plane_state->tiling_info.gfx8.tile_mode = %d;\n"
137 "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n",
138 plane_state->tiling_info.gfx8.num_banks,
139 plane_state->tiling_info.gfx8.bank_width,
140 plane_state->tiling_info.gfx8.bank_width_c,
141 plane_state->tiling_info.gfx8.bank_height,
142 plane_state->tiling_info.gfx8.bank_height_c,
143 plane_state->tiling_info.gfx8.tile_aspect,
144 plane_state->tiling_info.gfx8.tile_aspect_c,
145 plane_state->tiling_info.gfx8.tile_split,
146 plane_state->tiling_info.gfx8.tile_split_c,
147 plane_state->tiling_info.gfx8.tile_mode,
148 plane_state->tiling_info.gfx8.tile_mode_c);
149
150 SURFACE_TRACE(
151 "plane_state->tiling_info.gfx8.pipe_config = %d;\n"
152 "plane_state->tiling_info.gfx8.array_mode = %d;\n"
153 "plane_state->color_space = %d;\n"
154 "plane_state->dcc.enable = %d;\n"
155 "plane_state->format = %d;\n"
156 "plane_state->rotation = %d;\n"
157 "plane_state->stereo_format = %d;\n",
158 plane_state->tiling_info.gfx8.pipe_config,
159 plane_state->tiling_info.gfx8.array_mode,
160 plane_state->color_space,
161 plane_state->dcc.enable,
162 plane_state->format,
163 plane_state->rotation,
164 plane_state->stereo_format);
165
166 SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
167 plane_state->tiling_info.gfx9.swizzle);
168
169 SURFACE_TRACE("\n");
170 }
171 SURFACE_TRACE("\n");
172 }
173
update_surface_trace(struct dc * dc,const struct dc_surface_update * updates,int surface_count)174 void update_surface_trace(
175 struct dc *dc,
176 const struct dc_surface_update *updates,
177 int surface_count)
178 {
179 int i;
180 DC_LOGGER_INIT(dc->ctx->logger);
181
182 for (i = 0; i < surface_count; i++) {
183 const struct dc_surface_update *update = &updates[i];
184
185 SURFACE_TRACE("Update %d\n", i);
186 if (update->flip_addr) {
187 SURFACE_TRACE("flip_addr->address.type = %d;\n"
188 "flip_addr->address.grph.addr.quad_part = 0x%llX;\n"
189 "flip_addr->address.grph.meta_addr.quad_part = 0x%llX;\n"
190 "flip_addr->flip_immediate = %d;\n",
191 update->flip_addr->address.type,
192 update->flip_addr->address.grph.addr.quad_part,
193 update->flip_addr->address.grph.meta_addr.quad_part,
194 update->flip_addr->flip_immediate);
195 }
196
197 if (update->plane_info) {
198 SURFACE_TRACE(
199 "plane_info->color_space = %d;\n"
200 "plane_info->format = %d;\n"
201 "plane_info->plane_size.surface_pitch = %d;\n"
202 "plane_info->plane_size.surface_size.height = %d;\n"
203 "plane_info->plane_size.surface_size.width = %d;\n"
204 "plane_info->plane_size.surface_size.x = %d;\n"
205 "plane_info->plane_size.surface_size.y = %d;\n"
206 "plane_info->rotation = %d;\n"
207 "plane_info->stereo_format = %d;\n",
208 update->plane_info->color_space,
209 update->plane_info->format,
210 update->plane_info->plane_size.surface_pitch,
211 update->plane_info->plane_size.surface_size.height,
212 update->plane_info->plane_size.surface_size.width,
213 update->plane_info->plane_size.surface_size.x,
214 update->plane_info->plane_size.surface_size.y,
215 update->plane_info->rotation,
216 update->plane_info->stereo_format);
217
218 SURFACE_TRACE(
219 "plane_info->tiling_info.gfx8.num_banks = %d;\n"
220 "plane_info->tiling_info.gfx8.bank_width = %d;\n"
221 "plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
222 "plane_info->tiling_info.gfx8.bank_height = %d;\n"
223 "plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
224 "plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
225 "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
226 "plane_info->tiling_info.gfx8.tile_split = %d;\n"
227 "plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
228 "plane_info->tiling_info.gfx8.tile_mode = %d;\n"
229 "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
230 update->plane_info->tiling_info.gfx8.num_banks,
231 update->plane_info->tiling_info.gfx8.bank_width,
232 update->plane_info->tiling_info.gfx8.bank_width_c,
233 update->plane_info->tiling_info.gfx8.bank_height,
234 update->plane_info->tiling_info.gfx8.bank_height_c,
235 update->plane_info->tiling_info.gfx8.tile_aspect,
236 update->plane_info->tiling_info.gfx8.tile_aspect_c,
237 update->plane_info->tiling_info.gfx8.tile_split,
238 update->plane_info->tiling_info.gfx8.tile_split_c,
239 update->plane_info->tiling_info.gfx8.tile_mode,
240 update->plane_info->tiling_info.gfx8.tile_mode_c);
241
242 SURFACE_TRACE(
243 "plane_info->tiling_info.gfx8.pipe_config = %d;\n"
244 "plane_info->tiling_info.gfx8.array_mode = %d;\n"
245 "plane_info->visible = %d;\n"
246 "plane_info->per_pixel_alpha = %d;\n",
247 update->plane_info->tiling_info.gfx8.pipe_config,
248 update->plane_info->tiling_info.gfx8.array_mode,
249 update->plane_info->visible,
250 update->plane_info->per_pixel_alpha);
251
252 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
253 update->plane_info->tiling_info.gfx9.swizzle);
254 }
255
256 if (update->scaling_info) {
257 SURFACE_TRACE(
258 "scaling_info->src_rect.x = %d;\n"
259 "scaling_info->src_rect.y = %d;\n"
260 "scaling_info->src_rect.width = %d;\n"
261 "scaling_info->src_rect.height = %d;\n"
262 "scaling_info->dst_rect.x = %d;\n"
263 "scaling_info->dst_rect.y = %d;\n"
264 "scaling_info->dst_rect.width = %d;\n"
265 "scaling_info->dst_rect.height = %d;\n"
266 "scaling_info->clip_rect.x = %d;\n"
267 "scaling_info->clip_rect.y = %d;\n"
268 "scaling_info->clip_rect.width = %d;\n"
269 "scaling_info->clip_rect.height = %d;\n"
270 "scaling_info->scaling_quality.h_taps = %d;\n"
271 "scaling_info->scaling_quality.v_taps = %d;\n"
272 "scaling_info->scaling_quality.h_taps_c = %d;\n"
273 "scaling_info->scaling_quality.v_taps_c = %d;\n",
274 update->scaling_info->src_rect.x,
275 update->scaling_info->src_rect.y,
276 update->scaling_info->src_rect.width,
277 update->scaling_info->src_rect.height,
278 update->scaling_info->dst_rect.x,
279 update->scaling_info->dst_rect.y,
280 update->scaling_info->dst_rect.width,
281 update->scaling_info->dst_rect.height,
282 update->scaling_info->clip_rect.x,
283 update->scaling_info->clip_rect.y,
284 update->scaling_info->clip_rect.width,
285 update->scaling_info->clip_rect.height,
286 update->scaling_info->scaling_quality.h_taps,
287 update->scaling_info->scaling_quality.v_taps,
288 update->scaling_info->scaling_quality.h_taps_c,
289 update->scaling_info->scaling_quality.v_taps_c);
290 }
291 SURFACE_TRACE("\n");
292 }
293 SURFACE_TRACE("\n");
294 }
295
post_surface_trace(struct dc * dc)296 void post_surface_trace(struct dc *dc)
297 {
298 DC_LOGGER_INIT(dc->ctx->logger);
299
300 SURFACE_TRACE("post surface process.\n");
301
302 }
303
context_clock_trace(struct dc * dc,struct dc_state * context)304 void context_clock_trace(
305 struct dc *dc,
306 struct dc_state *context)
307 {
308 DC_LOGGER_INIT(dc->ctx->logger);
309 CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
310 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
311 context->bw_ctx.bw.dcn.clk.dispclk_khz,
312 context->bw_ctx.bw.dcn.clk.dppclk_khz,
313 context->bw_ctx.bw.dcn.clk.dcfclk_khz,
314 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
315 context->bw_ctx.bw.dcn.clk.fclk_khz,
316 context->bw_ctx.bw.dcn.clk.socclk_khz);
317 CLOCK_TRACE("Calculated: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
318 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
319 context->bw_ctx.bw.dcn.clk.dispclk_khz,
320 context->bw_ctx.bw.dcn.clk.dppclk_khz,
321 context->bw_ctx.bw.dcn.clk.dcfclk_khz,
322 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
323 context->bw_ctx.bw.dcn.clk.fclk_khz,
324 context->bw_ctx.bw.dcn.clk.socclk_khz);
325 }
326
327 /**
328 * dc_status_to_str - convert dc_status to a human readable string
329 * @status: dc_status to be converted
330 *
331 * Return:
332 * A string describing the DC status.
333 */
dc_status_to_str(enum dc_status status)334 char *dc_status_to_str(enum dc_status status)
335 {
336 switch (status) {
337 case DC_OK:
338 return "DC OK";
339 case DC_NO_CONTROLLER_RESOURCE:
340 return "No controller resource";
341 case DC_NO_STREAM_ENC_RESOURCE:
342 return "No stream encoder";
343 case DC_NO_CLOCK_SOURCE_RESOURCE:
344 return "No clock source";
345 case DC_FAIL_CONTROLLER_VALIDATE:
346 return "Controller validation failure";
347 case DC_FAIL_ENC_VALIDATE:
348 return "Encoder validation failure";
349 case DC_FAIL_ATTACH_SURFACES:
350 return "Surfaces attachment failure";
351 case DC_FAIL_DETACH_SURFACES:
352 return "Surfaces detachment failure";
353 case DC_FAIL_SURFACE_VALIDATE:
354 return "Surface validation failure";
355 case DC_NO_DP_LINK_BANDWIDTH:
356 return "No DP link bandwidth";
357 case DC_EXCEED_DONGLE_CAP:
358 return "Exceed dongle capability";
359 case DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED:
360 return "Unsupported pixel format";
361 case DC_FAIL_BANDWIDTH_VALIDATE:
362 return "Bandwidth validation failure (BW and Watermark)";
363 case DC_FAIL_SCALING:
364 return "Scaling failure";
365 case DC_FAIL_DP_LINK_TRAINING:
366 return "DP link training failure";
367 case DC_FAIL_DSC_VALIDATE:
368 return "DSC validation failure";
369 case DC_NO_DSC_RESOURCE:
370 return "No DSC resource";
371 case DC_FAIL_UNSUPPORTED_1:
372 return "Unsupported";
373 case DC_FAIL_CLK_EXCEED_MAX:
374 return "Clk exceed max failure";
375 case DC_FAIL_CLK_BELOW_MIN:
376 return "Fail clk below minimum";
377 case DC_FAIL_CLK_BELOW_CFG_REQUIRED:
378 return "Fail clk below required CFG (hard_min in PPLIB)";
379 case DC_NOT_SUPPORTED:
380 return "The operation is not supported.";
381 case DC_UNSUPPORTED_VALUE:
382 return "The value specified is not supported.";
383 case DC_NO_LINK_ENC_RESOURCE:
384 return "No link encoder resource";
385 case DC_FAIL_DP_PAYLOAD_ALLOCATION:
386 return "Fail dp payload allocation";
387 case DC_FAIL_DP_LINK_BANDWIDTH:
388 return "Insufficient DP link bandwidth";
389 case DC_ERROR_UNEXPECTED:
390 return "Unexpected error";
391 }
392
393 return "Unexpected status error";
394 }
395
dc_pixel_encoding_to_str(enum dc_pixel_encoding pixel_encoding)396 char *dc_pixel_encoding_to_str(enum dc_pixel_encoding pixel_encoding)
397 {
398 switch (pixel_encoding) {
399 case PIXEL_ENCODING_RGB:
400 return "RGB";
401 case PIXEL_ENCODING_YCBCR422:
402 return "YUV422";
403 case PIXEL_ENCODING_YCBCR444:
404 return "YUV444";
405 case PIXEL_ENCODING_YCBCR420:
406 return "YUV420";
407 default:
408 return "Unknown";
409 }
410 }
411
dc_color_depth_to_str(enum dc_color_depth color_depth)412 char *dc_color_depth_to_str(enum dc_color_depth color_depth)
413 {
414 switch (color_depth) {
415 case COLOR_DEPTH_666:
416 return "6-bpc";
417 case COLOR_DEPTH_888:
418 return "8-bpc";
419 case COLOR_DEPTH_101010:
420 return "10-bpc";
421 case COLOR_DEPTH_121212:
422 return "12-bpc";
423 case COLOR_DEPTH_141414:
424 return "14-bpc";
425 case COLOR_DEPTH_161616:
426 return "16-bpc";
427 case COLOR_DEPTH_999:
428 return "9-bpc";
429 case COLOR_DEPTH_111111:
430 return "11-bpc";
431 default:
432 return "Unknown";
433 }
434 }
435