1 /* 2 * Copyright © 2017 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef AC_SURFACE_H 8 #define AC_SURFACE_H 9 10 #include "amd_family.h" 11 #include "util/format/u_format.h" 12 13 /* NIR is optional. Some components don't want to include NIR with ac_surface.h. */ 14 #ifdef AC_SURFACE_INCLUDE_NIR 15 #include "compiler/nir/nir_builder.h" 16 #endif 17 18 #include <stdbool.h> 19 #include <stdint.h> 20 #include <stdio.h> 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Forward declarations. */ 27 struct ac_addrlib; 28 29 struct amdgpu_gpu_info; 30 struct radeon_info; 31 32 #define RADEON_SURF_MAX_LEVELS 17 33 34 enum radeon_surf_mode 35 { 36 RADEON_SURF_MODE_LINEAR_ALIGNED = 1, 37 RADEON_SURF_MODE_1D = 2, 38 RADEON_SURF_MODE_2D = 3, 39 }; 40 41 /* This describes D/S/Z/R swizzle modes. 42 * Defined in the GB_TILE_MODEn.MICRO_TILE_MODE_NEW order. 43 */ 44 enum radeon_micro_mode 45 { 46 RADEON_MICRO_MODE_DISPLAY = 0, 47 RADEON_MICRO_MODE_STANDARD = 1, 48 RADEON_MICRO_MODE_DEPTH = 2, 49 RADEON_MICRO_MODE_RENDER = 3, /* gfx9 and older: rotated */ 50 }; 51 52 /* the first 16 bits are reserved for libdrm_radeon, don't use them */ 53 #define RADEON_SURF_SCANOUT (1 << 16) 54 #define RADEON_SURF_ZBUFFER (1 << 17) 55 #define RADEON_SURF_SBUFFER (1 << 18) 56 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) 57 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */ 58 #define RADEON_SURF_FMASK (1 << 21) 59 #define RADEON_SURF_DISABLE_DCC (1ull << 22) 60 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1ull << 23) 61 #define RADEON_SURF_IMPORTED (1ull << 24) 62 #define RADEON_SURF_CONTIGUOUS_DCC_LAYERS (1ull << 25) 63 #define RADEON_SURF_SHAREABLE (1ull << 26) 64 #define RADEON_SURF_NO_RENDER_TARGET (1ull << 27) 65 /* Force a swizzle mode (gfx9+) or tile mode (gfx6-8). 66 * If this is not set, optimize for space. */ 67 #define RADEON_SURF_FORCE_SWIZZLE_MODE (1ull << 28) 68 #define RADEON_SURF_NO_FMASK (1ull << 29) 69 /* This disables HTILE on gfx6-11, and HiZ/HiS on gfx12, */ 70 #define RADEON_SURF_NO_HTILE (1ull << 30) 71 #define RADEON_SURF_FORCE_MICRO_TILE_MODE (1ull << 31) 72 #define RADEON_SURF_PRT (1ull << 32) 73 #define RADEON_SURF_VRS_RATE (1ull << 33) 74 /* Block compressed + linear format is not supported in addrlib. These surface can be 75 * used as transfer resource. This flag indicates not to set flags.texture flag for 76 * color surface in gfx9_compute_surface(). */ 77 #define RADEON_SURF_NO_TEXTURE (1ull << 34) 78 #define RADEON_SURF_NO_STENCIL_ADJUST (1ull << 35) 79 #define RADEON_SURF_PREFER_4K_ALIGNMENT (1ull << 36) 80 #define RADEON_SURF_PREFER_64K_ALIGNMENT (1ull << 37) 81 82 enum radeon_enc_hevc_surface_alignment 83 { 84 RADEON_ENC_HEVC_SURFACE_LOG2_WIDTH_ALIGNMENT = 6, 85 RADEON_ENC_HEVC_SURFACE_LOG2_HEIGHT_ALIGNMENT = 4, 86 }; 87 88 struct legacy_surf_level { 89 uint32_t offset_256B; /* divided by 256, the hw can only do 40-bit addresses */ 90 uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */ 91 unsigned nblk_x : 15; 92 unsigned nblk_y : 15; 93 enum radeon_surf_mode mode : 2; 94 }; 95 96 struct legacy_surf_dcc_level { 97 uint32_t dcc_offset; /* relative offset within DCC mip tree */ 98 uint32_t dcc_fast_clear_size; 99 uint32_t dcc_slice_fast_clear_size; 100 }; 101 102 struct legacy_surf_fmask { 103 unsigned slice_tile_max; /* max 4M */ 104 uint8_t tiling_index; /* max 31 */ 105 uint8_t bankh; /* max 8 */ 106 uint16_t pitch_in_pixels; 107 }; 108 109 struct legacy_surf_layout { 110 unsigned bankw : 4; /* max 8 */ 111 unsigned bankh : 4; /* max 8 */ 112 unsigned mtilea : 4; /* max 8 */ 113 unsigned tile_split : 13; /* max 4K */ 114 unsigned stencil_tile_split : 13; /* max 4K */ 115 unsigned pipe_config : 5; /* max 17 */ 116 unsigned num_banks : 5; /* max 16 */ 117 unsigned macro_tile_index : 4; /* max 15 */ 118 119 /* Whether the depth miptree or stencil miptree as used by the DB are 120 * adjusted from their TC compatible form to ensure depth/stencil 121 * compatibility. If either is true, the corresponding plane cannot be 122 * sampled from. 123 */ 124 unsigned depth_adjusted : 1; 125 unsigned stencil_adjusted : 1; 126 127 struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS]; 128 uint8_t tiling_index[RADEON_SURF_MAX_LEVELS]; 129 130 union { 131 /* Color layout */ 132 struct { 133 struct legacy_surf_dcc_level dcc_level[RADEON_SURF_MAX_LEVELS]; 134 struct legacy_surf_fmask fmask; 135 unsigned cmask_slice_tile_max; 136 } color; 137 138 /* Z/S layout */ 139 struct { 140 struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; 141 uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS]; 142 } zs; 143 }; 144 }; 145 146 /* Same as addrlib - AddrResourceType. */ 147 enum gfx9_resource_type 148 { 149 RADEON_RESOURCE_1D = 0, 150 RADEON_RESOURCE_2D, 151 RADEON_RESOURCE_3D, 152 }; 153 154 struct gfx9_surf_meta_flags { 155 uint8_t rb_aligned : 1; /* optimal for RBs */ 156 uint8_t pipe_aligned : 1; /* optimal for L2 */ 157 uint8_t independent_64B_blocks : 1; 158 uint8_t independent_128B_blocks : 1; 159 uint8_t max_compressed_block_size : 2; 160 uint8_t display_equation_valid : 1; 161 }; 162 163 struct gfx9_surf_meta_level { 164 unsigned offset; 165 unsigned size; /* the size of one level in one layer (the image is an array of layers 166 * where each layer has an array of levels) */ 167 }; 168 169 /** 170 * Meta address equation. 171 * 172 * DCC/HTILE address equation for doing DCC/HTILE address computations in shaders. 173 * 174 * ac_surface_meta_address_test.c contains the reference implementation. 175 * ac_nir_{dcc,htile}_addr_from_coord is the NIR implementation. 176 * 177 * For DCC: 178 * The gfx9 equation doesn't support mipmapping. 179 * The gfx10 equation doesn't support mipmapping and MSAA. 180 * (those are also limitations of Addr2ComputeDccAddrFromCoord) 181 * 182 * For HTILE: 183 * The gfx9 equation isn't implemented. 184 * The gfx10 equation doesn't support mipmapping. 185 */ 186 struct gfx9_meta_equation { 187 uint16_t meta_block_width; 188 uint16_t meta_block_height; 189 uint16_t meta_block_depth; 190 191 union { 192 /* The gfx9 DCC equation is chip-specific, and it varies with: 193 * - resource type 194 * - swizzle_mode 195 * - bpp 196 * - number of samples 197 * - number of fragments 198 * - pipe_aligned 199 * - rb_aligned 200 */ 201 struct { 202 uint8_t num_bits; 203 uint8_t num_pipe_bits; 204 205 struct { 206 struct { 207 uint8_t dim:3; /* 0..4 */ 208 uint8_t ord:5; /* 0..31 */ 209 } coord[5]; /* 0..num_coords-1 */ 210 } bit[20]; /* 0..num_bits-1 */ 211 } gfx9; 212 213 /* The gfx10 DCC equation is chip-specific, it requires 64KB_R_X, and it varies with: 214 * - bpp 215 * - number of samples 216 * - number of fragments 217 * - pipe_aligned 218 * 219 * The gfx10 HTILE equation is chip-specific, it requires 64KB_Z_X, and it varies with: 220 * - number of samples 221 */ 222 uint16_t gfx10_bits[64]; 223 } u; 224 }; 225 226 struct gfx12_hiz_his_layout { 227 uint64_t offset; 228 uint32_t size; 229 uint16_t width_in_tiles; 230 uint16_t height_in_tiles; 231 uint8_t swizzle_mode; 232 uint8_t alignment_log2; 233 }; 234 235 struct gfx9_surf_layout { 236 uint16_t epitch; /* gfx9 only, not on gfx10 */ 237 uint8_t swizzle_mode; /* color or depth */ 238 bool uses_custom_pitch; /* only used by gfx10.3+ */ 239 bool gfx12_enable_dcc; /* set AMDGPU_GEM_CREATE_GFX12_DCC if the placement is VRAM */ 240 241 enum gfx9_resource_type resource_type:8; /* 1D, 2D or 3D */ 242 uint32_t surf_pitch; /* up to 64K (in blocks) */ 243 uint32_t surf_height; /* up to 64K */ 244 245 uint64_t surf_offset; /* 0 unless imported with an offset */ 246 /* The size of the 2D plane containing all mipmap levels. */ 247 uint64_t surf_slice_size; 248 /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */ 249 uint64_t offset[RADEON_SURF_MAX_LEVELS]; /* up to 64K * 64K * 16 * ~1.33 */ 250 /* Mipmap level pitch in elements. Only valid for LINEAR. */ 251 uint32_t pitch[RADEON_SURF_MAX_LEVELS]; /* up to 64K */ 252 253 uint32_t base_mip_width; /* up to 64K */ 254 uint32_t base_mip_height; /* up to 64K */ 255 256 /* Pitch of level in blocks, only valid for prt images. */ 257 uint32_t prt_level_pitch[RADEON_SURF_MAX_LEVELS]; /* up to 64K */ 258 /* Offset within slice in bytes, only valid for prt images. */ 259 uint64_t prt_level_offset[RADEON_SURF_MAX_LEVELS]; /* up to 64K * 64K * 16 * ~1.33 */ 260 261 /* DCC or HTILE level info */ 262 struct gfx9_surf_meta_level meta_levels[RADEON_SURF_MAX_LEVELS]; 263 264 union { 265 /* Color */ 266 struct { 267 struct gfx9_surf_meta_flags dcc; /* metadata of color */ 268 uint8_t fmask_swizzle_mode; 269 uint16_t fmask_epitch; /* gfx9 only, not on gfx10 */ 270 271 uint16_t dcc_pitch_max; 272 uint16_t dcc_height; 273 274 uint8_t dcc_block_width; 275 uint8_t dcc_block_height; 276 uint8_t dcc_block_depth; 277 278 /* Gfx12 DCC recompression settings used by kernel memory management. 279 * The driver sets these, not ac_compute_surface. 280 */ 281 uint8_t dcc_number_type; /* CB_COLOR0_INFO.NUMBER_TYPE */ 282 uint8_t dcc_data_format; /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 283 284 /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0. 285 * The 3D engine doesn't support that layout except for chips with 1 RB. 286 * All other chips must set rb_aligned=1. 287 * A compute shader needs to convert from aligned DCC to unaligned. 288 */ 289 uint8_t display_dcc_alignment_log2; 290 uint32_t display_dcc_size; 291 uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */ 292 uint16_t display_dcc_height; 293 bool dcc_retile_use_uint16; /* if all values fit into uint16_t */ 294 uint32_t dcc_retile_num_elements; 295 void *dcc_retile_map; 296 297 /* CMASK level info (only level 0) */ 298 struct gfx9_surf_meta_level cmask_level0; 299 300 /* For DCC retiling. */ 301 struct gfx9_meta_equation dcc_equation; /* 2D only */ 302 struct gfx9_meta_equation display_dcc_equation; 303 304 /* For FCE compute. */ 305 struct gfx9_meta_equation cmask_equation; /* 2D only */ 306 } color; 307 308 /* Z/S */ 309 struct { 310 uint64_t stencil_offset; /* separate stencil */ 311 uint16_t stencil_epitch; /* gfx9 only, not on gfx10 */ 312 uint8_t stencil_swizzle_mode; 313 314 struct gfx12_hiz_his_layout hiz, his; 315 316 /* For HTILE VRS. (only Gfx103-Gfx11) */ 317 struct gfx9_meta_equation htile_equation; 318 } zs; 319 }; 320 }; 321 322 struct radeon_surf { 323 /* Format properties. */ 324 uint8_t blk_w : 4; 325 uint8_t blk_h : 4; 326 uint8_t bpe : 5; 327 /* Display, standard(thin), depth, render(rotated). AKA D,S,Z,R swizzle modes. */ 328 uint8_t micro_tile_mode : 3; 329 /* Number of mipmap levels where DCC or HTILE is enabled starting from level 0. 330 * Non-zero levels may be disabled due to alignment constraints, but not 331 * the first level. 332 */ 333 uint8_t num_meta_levels : 4; 334 uint8_t is_linear : 1; 335 uint8_t has_stencil : 1; 336 /* This might be true even if micro_tile_mode isn't displayable or rotated. */ 337 uint8_t is_displayable : 1; 338 /* Thick tiling means 3D tiles. Use 3D compute workgroups for blits. (4x4x4 works well) */ 339 uint8_t thick_tiling : 1; 340 uint8_t first_mip_tail_level : 4; 341 342 /* These are return values. Some of them can be set by the caller, but 343 * they will be treated as hints (e.g. bankw, bankh) and might be 344 * changed by the calculator. 345 */ 346 347 /* Not supported yet for depth + stencil. */ 348 uint16_t prt_tile_width; /* up to 256 roughly (for 64KB tiles) */ 349 uint16_t prt_tile_height; /* up to 256 roughly (for 64KB tiles) */ 350 uint16_t prt_tile_depth; /* up to 32 roughly (for 64KB thick tiles) */ 351 352 /* Tile swizzle can be OR'd with low bits of the BASE_256B address. 353 * The value is the same for all mipmap levels. Supported tile modes: 354 * - GFX6: Only macro tiling. 355 * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip 356 * tail. 357 * 358 * Only these surfaces are allowed to set it: 359 * - color (if it doesn't have to be displayable) 360 * - DCC (same tile swizzle as color) 361 * - FMASK 362 * - CMASK if it's TC-compatible or if the gen is GFX9 363 * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9 364 */ 365 uint16_t tile_swizzle; /* it has 16 bits because gfx11 shifts it by 2 bits */ 366 uint8_t fmask_tile_swizzle; 367 368 /* Use (1 << log2) to compute the alignment. */ 369 uint8_t surf_alignment_log2; 370 uint8_t fmask_alignment_log2; 371 uint8_t meta_alignment_log2; /* DCC or HTILE */ 372 uint8_t cmask_alignment_log2; 373 uint8_t alignment_log2; 374 375 /* DRM format modifier. Set to DRM_FORMAT_MOD_INVALID to have addrlib 376 * select tiling parameters instead. 377 */ 378 uint64_t modifier; 379 uint64_t flags; 380 381 uint64_t surf_size; 382 uint64_t fmask_size; 383 uint32_t fmask_slice_size; /* max 2^31 (16K * 16K * 8) */ 384 385 /* DCC and HTILE (they are very small) */ 386 uint32_t meta_size; 387 uint32_t meta_slice_size; 388 uint32_t meta_pitch; 389 390 uint32_t cmask_size; 391 uint32_t cmask_slice_size; 392 uint16_t cmask_pitch; /* GFX9+ */ 393 uint16_t cmask_height; /* GFX9+ */ 394 395 /* All buffers combined. */ 396 uint64_t meta_offset; /* DCC (Gfx8-Gfx11) or HTILE (Gfx6-Gfx11) */ 397 uint64_t fmask_offset; /* Gfx6-Gfx10 */ 398 uint64_t cmask_offset; /* Gfx6-Gfx10 */ 399 uint64_t display_dcc_offset; /* Gfx9-Gfx11 */ 400 uint64_t total_size; 401 402 union { 403 /* Gfx3-8 surface info. 404 * 405 * Some of them can be set by the caller if certain parameters are 406 * desirable. The allocator will try to obey them. 407 */ 408 struct legacy_surf_layout legacy; 409 410 /* Gfx9+ surface info. */ 411 struct gfx9_surf_layout gfx9; 412 } u; 413 }; 414 415 struct ac_surf_info { 416 uint32_t width; /* up to 64K */ 417 uint32_t height; /* up to 64K */ 418 uint32_t depth; /* up to 16K */ 419 uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */ 420 uint8_t storage_samples; /* For color: allocated samples */ 421 uint8_t levels; 422 uint8_t num_channels; /* heuristic for displayability */ 423 uint16_t array_size; 424 uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */ 425 uint32_t *fmask_surf_index; 426 }; 427 428 struct ac_surf_config { 429 struct ac_surf_info info; 430 unsigned is_1d : 1; 431 unsigned is_3d : 1; 432 unsigned is_cube : 1; 433 unsigned is_array : 1; 434 }; 435 436 /* Output parameters for ac_surface_compute_nbc_view */ 437 struct ac_surf_nbc_view { 438 bool valid; 439 uint32_t width; /* up to 64K */ 440 uint32_t height; /* up to 64K */ 441 uint32_t level; 442 uint32_t num_levels; /* Used for max_mip in the resource descriptor */ 443 uint8_t tile_swizzle; 444 uint64_t base_address_offset; 445 }; 446 447 struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info, uint64_t *max_alignment); 448 void ac_addrlib_destroy(struct ac_addrlib *addrlib); 449 void *ac_addrlib_get_handle(struct ac_addrlib *addrlib); 450 451 int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info, 452 const struct ac_surf_config *config, enum radeon_surf_mode mode, 453 struct radeon_surf *surf); 454 void ac_surface_zero_dcc_fields(struct radeon_surf *surf); 455 unsigned ac_pipe_config_to_num_pipes(unsigned pipe_config); 456 457 void ac_surface_apply_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, 458 uint64_t tiling_flags, enum radeon_surf_mode *mode); 459 void ac_surface_compute_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, 460 uint64_t *tiling_flags); 461 462 bool ac_surface_apply_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, 463 unsigned num_storage_samples, unsigned num_mipmap_levels, 464 unsigned size_metadata, const uint32_t metadata[64]); 465 void ac_surface_compute_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, 466 unsigned num_mipmap_levels, uint32_t desc[8], 467 unsigned *size_metadata, uint32_t metadata[64], 468 bool include_tool_md); 469 470 bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf, 471 unsigned num_layers, unsigned num_mipmap_levels, 472 uint64_t offset, unsigned pitch); 473 474 struct ac_modifier_options { 475 bool dcc; /* Whether to allow DCC. */ 476 bool dcc_retile; /* Whether to allow use of a DCC retile map. */ 477 }; 478 479 bool ac_is_modifier_supported(const struct radeon_info *info, 480 const struct ac_modifier_options *options, 481 enum pipe_format format, 482 uint64_t modifier); 483 bool ac_get_supported_modifiers(const struct radeon_info *info, 484 const struct ac_modifier_options *options, 485 enum pipe_format format, 486 unsigned *mod_count, 487 uint64_t *mods); 488 bool ac_modifier_has_dcc(uint64_t modifier); 489 bool ac_modifier_has_dcc_retile(uint64_t modifier); 490 bool ac_modifier_supports_dcc_image_stores(enum amd_gfx_level gfx_level, uint64_t modifier); 491 void ac_modifier_max_extent(const struct radeon_info *info, 492 uint64_t modifier, uint32_t *width, uint32_t *height); 493 494 unsigned ac_surface_get_nplanes(const struct radeon_surf *surf); 495 uint64_t ac_surface_get_plane_offset(enum amd_gfx_level gfx_level, 496 const struct radeon_surf *surf, 497 unsigned plane, unsigned layer); 498 uint64_t ac_surface_get_plane_stride(enum amd_gfx_level gfx_level, 499 const struct radeon_surf *surf, 500 unsigned plane, unsigned level); 501 /* Of the whole miplevel, not an individual layer */ 502 uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf, 503 unsigned plane); 504 505 uint64_t ac_surface_addr_from_coord(struct ac_addrlib *addrlib, const struct radeon_info *info, 506 const struct radeon_surf *surf, 507 const struct ac_surf_info *surf_info, unsigned level, 508 unsigned x, unsigned y, unsigned layer, bool is_3d); 509 void ac_surface_compute_nbc_view(struct ac_addrlib *addrlib, const struct radeon_info *info, 510 const struct radeon_surf *surf, 511 const struct ac_surf_info *surf_info, unsigned level, 512 unsigned layer, struct ac_surf_nbc_view *out); 513 514 void ac_surface_print_info(FILE *out, const struct radeon_info *info, 515 const struct radeon_surf *surf); 516 517 bool ac_surface_supports_dcc_image_stores(enum amd_gfx_level gfx_level, 518 const struct radeon_surf *surf); 519 520 #ifdef AC_SURFACE_INCLUDE_NIR 521 nir_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info, 522 unsigned bpe, const struct gfx9_meta_equation *equation, 523 nir_def *dcc_pitch, nir_def *dcc_height, 524 nir_def *dcc_slice_size, 525 nir_def *x, nir_def *y, nir_def *z, 526 nir_def *sample, nir_def *pipe_xor); 527 528 nir_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info, 529 const struct gfx9_meta_equation *equation, 530 nir_def *cmask_pitch, nir_def *cmask_height, 531 nir_def *cmask_slice_size, 532 nir_def *x, nir_def *y, nir_def *z, 533 nir_def *pipe_xor, 534 nir_def **bit_position); 535 536 nir_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info, 537 const struct gfx9_meta_equation *equation, 538 nir_def *htile_pitch, 539 nir_def *htile_slice_size, 540 nir_def *x, nir_def *y, nir_def *z, 541 nir_def *pipe_xor); 542 #endif 543 544 #ifdef __cplusplus 545 } 546 #endif 547 548 #endif /* AC_SURFACE_H */ 549