1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30
31 // For dce12_get_dp_ref_freq_khz
32 #include "dce100/dce_clk_mgr.h"
33
34 // For dcn20_update_clocks_update_dpp_dto
35 #include "dcn20/dcn20_clk_mgr.h"
36
37
38
39 #include "dcn31_clk_mgr.h"
40
41 #include "reg_helper.h"
42 #include "core_types.h"
43 #include "dcn31_smu.h"
44 #include "dm_helpers.h"
45
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48
49 #include "dc_dmub_srv.h"
50 #include "link.h"
51
52 #include "logger_types.h"
53
54
55 #include "yellow_carp_offset.h"
56 #undef DC_LOGGER
57 #define DC_LOGGER \
58 clk_mgr->base.base.ctx->logger
59
60 #define regCLK1_CLK_PLL_REQ 0x0237
61 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
62
63 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
64 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
65 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
66 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
67 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
68 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
69
70 #define REG(reg_name) \
71 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
72
73 #define TO_CLK_MGR_DCN31(clk_mgr)\
74 container_of(clk_mgr, struct clk_mgr_dcn31, base)
75
dcn31_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)76 static int dcn31_get_active_display_cnt_wa(
77 struct dc *dc,
78 struct dc_state *context)
79 {
80 int i, display_count;
81 bool tmds_present = false;
82
83 display_count = 0;
84 for (i = 0; i < context->stream_count; i++) {
85 const struct dc_stream_state *stream = context->streams[i];
86
87 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
88 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
89 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
90 tmds_present = true;
91
92 /* Checking stream / link detection ensuring that PHY is active*/
93 if (dc_is_dp_signal(stream->signal) && !stream->dpms_off)
94 display_count++;
95
96 }
97
98 for (i = 0; i < dc->link_count; i++) {
99 const struct dc_link *link = dc->links[i];
100
101 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
102 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
103 link->link_enc->funcs->is_dig_enabled(link->link_enc))
104 display_count++;
105 }
106
107 /* WA for hang on HDMI after display off back back on*/
108 if (display_count == 0 && tmds_present)
109 display_count = 1;
110
111 return display_count;
112 }
113
dcn31_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool disable)114 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
115 {
116 struct dc *dc = clk_mgr_base->ctx->dc;
117 int i;
118
119 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
120 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
121
122 if (pipe->top_pipe || pipe->prev_odm_pipe)
123 continue;
124 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
125 if (disable) {
126 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
127 reset_sync_context_for_pipe(dc, context, i);
128 } else
129 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
130 }
131 }
132 }
133
dcn31_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)134 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
135 struct dc_state *context,
136 bool safe_to_lower)
137 {
138 union dmub_rb_cmd cmd;
139 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
140 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
141 struct dc *dc = clk_mgr_base->ctx->dc;
142 int display_count;
143 bool update_dppclk = false;
144 bool update_dispclk = false;
145 bool dpp_clock_lowered = false;
146
147 if (dc->work_arounds.skip_clock_update)
148 return;
149
150 /*
151 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
152 * also if safe to lower is false, we just go in the higher state
153 */
154 if (safe_to_lower) {
155 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
156 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
157 dcn31_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
158 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
159 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
160 }
161
162 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
163 dcn31_smu_set_dtbclk(clk_mgr, false);
164 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
165 }
166 /* check that we're not already in lower */
167 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
168 display_count = dcn31_get_active_display_cnt_wa(dc, context);
169 /* if we can go lower, go lower */
170 if (display_count == 0) {
171 union display_idle_optimization_u idle_info = { 0 };
172 idle_info.idle_info.df_request_disabled = 1;
173 idle_info.idle_info.phy_ref_clk_off = 1;
174 idle_info.idle_info.s0i2_rdy = 1;
175 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
176 /* update power state */
177 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
178 }
179 }
180 } else {
181 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
182 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
183 dcn31_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
184 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
185 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
186 }
187
188 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
189 dcn31_smu_set_dtbclk(clk_mgr, true);
190 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
191 }
192
193 /* check that we're not already in D0 */
194 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
195 union display_idle_optimization_u idle_info = { 0 };
196 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
197 /* update power state */
198 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
199 }
200 }
201
202 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
203 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
204 dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
205 }
206
207 if (should_set_clock(safe_to_lower,
208 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
209 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
210 dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
211 }
212
213 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
214 if (new_clocks->dppclk_khz < 100000)
215 new_clocks->dppclk_khz = 100000;
216
217 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
218 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
219 dpp_clock_lowered = true;
220 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
221 update_dppclk = true;
222 }
223
224 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
225 dcn31_disable_otg_wa(clk_mgr_base, context, true);
226
227 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
228 dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
229 dcn31_disable_otg_wa(clk_mgr_base, context, false);
230
231 update_dispclk = true;
232 }
233
234 if (dpp_clock_lowered) {
235 // increase per DPP DTO before lowering global dppclk
236 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
237 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
238 } else {
239 // increase global DPPCLK before lowering per DPP DTO
240 if (update_dppclk || update_dispclk)
241 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
242 // always update dtos unless clock is lowered and not safe to lower
243 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
244 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
245 }
246
247 // notify DMCUB of latest clocks
248 memset(&cmd, 0, sizeof(cmd));
249 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
250 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
251 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
252 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
253 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
254 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
255 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
256
257 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
258 }
259
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)260 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
261 {
262 /* get FbMult value */
263 struct fixed31_32 pll_req;
264 unsigned int fbmult_frac_val = 0;
265 unsigned int fbmult_int_val = 0;
266
267 /*
268 * Register value of fbmult is in 8.16 format, we are converting to 31.32
269 * to leverage the fix point operations available in driver
270 */
271
272 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
273 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
274
275 pll_req = dc_fixpt_from_int(fbmult_int_val);
276
277 /*
278 * since fractional part is only 16 bit in register definition but is 32 bit
279 * in our fix point definiton, need to shift left by 16 to obtain correct value
280 */
281 pll_req.value |= fbmult_frac_val << 16;
282
283 /* multiply by REFCLK period */
284 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
285
286 /* integer part is now VCO frequency in kHz */
287 return dc_fixpt_floor(pll_req);
288 }
289
dcn31_enable_pme_wa(struct clk_mgr * clk_mgr_base)290 static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
291 {
292 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
293
294 dcn31_smu_enable_pme_wa(clk_mgr);
295 }
296
dcn31_init_clocks(struct clk_mgr * clk_mgr)297 void dcn31_init_clocks(struct clk_mgr *clk_mgr)
298 {
299 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
300
301 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
302 // Assumption is that boot state always supports pstate
303 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
304 clk_mgr->clks.p_state_change_support = true;
305 clk_mgr->clks.prev_p_state_change_support = true;
306 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
307 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
308 }
309
dcn31_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)310 bool dcn31_are_clock_states_equal(struct dc_clocks *a,
311 struct dc_clocks *b)
312 {
313 if (a->dispclk_khz != b->dispclk_khz)
314 return false;
315 else if (a->dppclk_khz != b->dppclk_khz)
316 return false;
317 else if (a->dcfclk_khz != b->dcfclk_khz)
318 return false;
319 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
320 return false;
321 else if (a->zstate_support != b->zstate_support)
322 return false;
323 else if (a->dtbclk_en != b->dtbclk_en)
324 return false;
325
326 return true;
327 }
328
dcn31_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)329 static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
330 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
331 {
332 return;
333 }
334
335 static struct clk_bw_params dcn31_bw_params = {
336 .vram_type = Ddr4MemType,
337 .num_channels = 1,
338 .clk_table = {
339 .num_entries = 4,
340 },
341
342 };
343
344 static struct wm_table ddr5_wm_table = {
345 .entries = {
346 {
347 .wm_inst = WM_A,
348 .wm_type = WM_TYPE_PSTATE_CHG,
349 .pstate_latency_us = 11.72,
350 .sr_exit_time_us = 9,
351 .sr_enter_plus_exit_time_us = 11,
352 .valid = true,
353 },
354 {
355 .wm_inst = WM_B,
356 .wm_type = WM_TYPE_PSTATE_CHG,
357 .pstate_latency_us = 11.72,
358 .sr_exit_time_us = 9,
359 .sr_enter_plus_exit_time_us = 11,
360 .valid = true,
361 },
362 {
363 .wm_inst = WM_C,
364 .wm_type = WM_TYPE_PSTATE_CHG,
365 .pstate_latency_us = 11.72,
366 .sr_exit_time_us = 9,
367 .sr_enter_plus_exit_time_us = 11,
368 .valid = true,
369 },
370 {
371 .wm_inst = WM_D,
372 .wm_type = WM_TYPE_PSTATE_CHG,
373 .pstate_latency_us = 11.72,
374 .sr_exit_time_us = 9,
375 .sr_enter_plus_exit_time_us = 11,
376 .valid = true,
377 },
378 }
379 };
380
381 static struct wm_table lpddr5_wm_table = {
382 .entries = {
383 {
384 .wm_inst = WM_A,
385 .wm_type = WM_TYPE_PSTATE_CHG,
386 .pstate_latency_us = 11.65333,
387 .sr_exit_time_us = 11.5,
388 .sr_enter_plus_exit_time_us = 14.5,
389 .valid = true,
390 },
391 {
392 .wm_inst = WM_B,
393 .wm_type = WM_TYPE_PSTATE_CHG,
394 .pstate_latency_us = 11.65333,
395 .sr_exit_time_us = 11.5,
396 .sr_enter_plus_exit_time_us = 14.5,
397 .valid = true,
398 },
399 {
400 .wm_inst = WM_C,
401 .wm_type = WM_TYPE_PSTATE_CHG,
402 .pstate_latency_us = 11.65333,
403 .sr_exit_time_us = 11.5,
404 .sr_enter_plus_exit_time_us = 14.5,
405 .valid = true,
406 },
407 {
408 .wm_inst = WM_D,
409 .wm_type = WM_TYPE_PSTATE_CHG,
410 .pstate_latency_us = 11.65333,
411 .sr_exit_time_us = 11.5,
412 .sr_enter_plus_exit_time_us = 14.5,
413 .valid = true,
414 },
415 }
416 };
417
418 static DpmClocks_t dummy_clocks;
419
420 static struct dcn31_watermarks dummy_wms = { 0 };
421
dcn31_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn31_watermarks * table)422 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
423 {
424 int i, num_valid_sets;
425
426 num_valid_sets = 0;
427
428 for (i = 0; i < WM_SET_COUNT; i++) {
429 /* skip empty entries, the smu array has no holes*/
430 if (!bw_params->wm_table.entries[i].valid)
431 continue;
432
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
434 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
435 /* We will not select WM based on fclk, so leave it as unconstrained */
436 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
437 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
438
439 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
440 if (i == 0)
441 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
442 else {
443 /* add 1 to make it non-overlapping with next lvl */
444 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
445 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
446 }
447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
448 bw_params->clk_table.entries[i].dcfclk_mhz;
449
450 } else {
451 /* unconstrained for memory retraining */
452 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
453 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
454
455 /* Modify previous watermark range to cover up to max */
456 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
457 }
458 num_valid_sets++;
459 }
460
461 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
462
463 /* modify the min and max to make sure we cover the whole range*/
464 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
465 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
466 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
467 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
468
469 /* This is for writeback only, does not matter currently as no writeback support*/
470 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
471 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
472 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
473 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
474 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
475 }
476
dcn31_notify_wm_ranges(struct clk_mgr * clk_mgr_base)477 static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
478 {
479 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
480 struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr);
481 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set;
482
483 if (!clk_mgr->smu_ver)
484 return;
485
486 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0)
487 return;
488
489 memset(table, 0, sizeof(*table));
490
491 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table);
492
493 dcn31_smu_set_dram_addr_high(clk_mgr,
494 clk_mgr_dcn31->smu_wm_set.mc_address.high_part);
495 dcn31_smu_set_dram_addr_low(clk_mgr,
496 clk_mgr_dcn31->smu_wm_set.mc_address.low_part);
497 dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr);
498 }
499
dcn31_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn31_smu_dpm_clks * smu_dpm_clks)500 static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
501 struct dcn31_smu_dpm_clks *smu_dpm_clks)
502 {
503 DpmClocks_t *table = smu_dpm_clks->dpm_clks;
504
505 if (!clk_mgr->smu_ver)
506 return;
507
508 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
509 return;
510
511 memset(table, 0, sizeof(*table));
512
513 dcn31_smu_set_dram_addr_high(clk_mgr,
514 smu_dpm_clks->mc_address.high_part);
515 dcn31_smu_set_dram_addr_low(clk_mgr,
516 smu_dpm_clks->mc_address.low_part);
517 dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
518 }
519
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)520 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
521 {
522 uint32_t max = 0;
523 int i;
524
525 for (i = 0; i < num_clocks; ++i) {
526 if (clocks[i] > max)
527 max = clocks[i];
528 }
529
530 return max;
531 }
532
find_clk_for_voltage(const DpmClocks_t * clock_table,const uint32_t clocks[],unsigned int voltage)533 static unsigned int find_clk_for_voltage(
534 const DpmClocks_t *clock_table,
535 const uint32_t clocks[],
536 unsigned int voltage)
537 {
538 int i;
539 int max_voltage = 0;
540 int clock = 0;
541
542 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
543 if (clock_table->SocVoltage[i] == voltage) {
544 return clocks[i];
545 } else if (clock_table->SocVoltage[i] >= max_voltage &&
546 clock_table->SocVoltage[i] < voltage) {
547 max_voltage = clock_table->SocVoltage[i];
548 clock = clocks[i];
549 }
550 }
551
552 ASSERT(clock);
553 return clock;
554 }
555
dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks_t * clock_table)556 static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
557 struct integrated_info *bios_info,
558 const DpmClocks_t *clock_table)
559 {
560 int i, j;
561 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
562 uint32_t max_dispclk = 0, max_dppclk = 0;
563
564 j = -1;
565
566 static_assert(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL,
567 "number of reported pstate levels exceeds maximum");
568
569 /* Find lowest DPM, FCLK is filled in reverse order*/
570
571 for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
572 if (clock_table->DfPstateTable[i].FClk != 0) {
573 j = i;
574 break;
575 }
576 }
577
578 if (j == -1) {
579 /* clock table is all 0s, just use our own hardcode */
580 ASSERT(0);
581 return;
582 }
583
584 bw_params->clk_table.num_entries = j + 1;
585
586 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
587 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
588 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
589 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
590 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
591 } else {
592 ASSERT(0);
593 }
594
595 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
596 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
597 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
598 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
599 switch (clock_table->DfPstateTable[j].WckRatio) {
600 case WCK_RATIO_1_2:
601 bw_params->clk_table.entries[i].wck_ratio = 2;
602 break;
603 case WCK_RATIO_1_4:
604 bw_params->clk_table.entries[i].wck_ratio = 4;
605 break;
606 default:
607 bw_params->clk_table.entries[i].wck_ratio = 1;
608 }
609 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
610 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
611 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
612 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
613 }
614
615 bw_params->vram_type = bios_info->memory_type;
616
617 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
618 //bw_params->dram_channel_width_bytes = dc->ctx->asic_id.vram_width;
619 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
620 for (i = 0; i < WM_SET_COUNT; i++) {
621 bw_params->wm_table.entries[i].wm_inst = i;
622
623 if (i >= bw_params->clk_table.num_entries) {
624 bw_params->wm_table.entries[i].valid = false;
625 continue;
626 }
627
628 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
629 bw_params->wm_table.entries[i].valid = true;
630 }
631 }
632
dcn31_set_low_power_state(struct clk_mgr * clk_mgr_base)633 static void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base)
634 {
635 int display_count;
636 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
637 struct dc *dc = clk_mgr_base->ctx->dc;
638 struct dc_state *context = dc->current_state;
639
640 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
641 display_count = dcn31_get_active_display_cnt_wa(dc, context);
642 /* if we can go lower, go lower */
643 if (display_count == 0) {
644 union display_idle_optimization_u idle_info = { 0 };
645
646 idle_info.idle_info.df_request_disabled = 1;
647 idle_info.idle_info.phy_ref_clk_off = 1;
648 idle_info.idle_info.s0i2_rdy = 1;
649 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
650 /* update power state */
651 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
652 }
653 }
654 }
655
dcn31_get_dtb_ref_freq_khz(struct clk_mgr * clk_mgr_base)656 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)
657 {
658 return clk_mgr_base->clks.ref_dtbclk_khz;
659 }
660
661 static struct clk_mgr_funcs dcn31_funcs = {
662 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
663 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
664 .update_clocks = dcn31_update_clocks,
665 .init_clocks = dcn31_init_clocks,
666 .enable_pme_wa = dcn31_enable_pme_wa,
667 .are_clock_states_equal = dcn31_are_clock_states_equal,
668 .notify_wm_ranges = dcn31_notify_wm_ranges,
669 .set_low_power_state = dcn31_set_low_power_state
670 };
671 extern struct clk_mgr_funcs dcn3_fpga_funcs;
672
dcn31_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn31 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)673 void dcn31_clk_mgr_construct(
674 struct dc_context *ctx,
675 struct clk_mgr_dcn31 *clk_mgr,
676 struct pp_smu_funcs *pp_smu,
677 struct dccg *dccg)
678 {
679 struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };
680 struct clk_log_info log_info = {0};
681
682 clk_mgr->base.base.ctx = ctx;
683 clk_mgr->base.base.funcs = &dcn31_funcs;
684
685 clk_mgr->base.pp_smu = pp_smu;
686
687 clk_mgr->base.dccg = dccg;
688 clk_mgr->base.dfs_bypass_disp_clk = 0;
689
690 clk_mgr->base.dprefclk_ss_percentage = 0;
691 clk_mgr->base.dprefclk_ss_divider = 1000;
692 clk_mgr->base.ss_on_dprefclk = false;
693 clk_mgr->base.dfs_ref_freq_khz = 48000;
694
695 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
696 clk_mgr->base.base.ctx,
697 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
698 sizeof(struct dcn31_watermarks),
699 &clk_mgr->smu_wm_set.mc_address.quad_part);
700
701 if (!clk_mgr->smu_wm_set.wm_set) {
702 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
703 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
704 }
705 ASSERT(clk_mgr->smu_wm_set.wm_set);
706
707 smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
708 clk_mgr->base.base.ctx,
709 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
710 sizeof(DpmClocks_t),
711 &smu_dpm_clks.mc_address.quad_part);
712
713 if (smu_dpm_clks.dpm_clks == NULL) {
714 smu_dpm_clks.dpm_clks = &dummy_clocks;
715 smu_dpm_clks.mc_address.quad_part = 0;
716 }
717
718 ASSERT(smu_dpm_clks.dpm_clks);
719
720 clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base);
721
722 if (clk_mgr->base.smu_ver)
723 clk_mgr->base.smu_present = true;
724
725 /* TODO: Check we get what we expect during bringup */
726 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
727
728 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
729 dcn31_bw_params.wm_table = lpddr5_wm_table;
730 } else {
731 dcn31_bw_params.wm_table = ddr5_wm_table;
732 }
733 /* Saved clocks configured at boot for debug purposes */
734 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
735 &clk_mgr->base.base, &log_info);
736
737 clk_mgr->base.base.dprefclk_khz = 600000;
738 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
739 dce_clock_read_ss_info(&clk_mgr->base);
740 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/
741 //clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz);
742
743 clk_mgr->base.base.bw_params = &dcn31_bw_params;
744
745 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
746 int i;
747
748 dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
749
750 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
751 "NumDispClkLevelsEnabled: %d\n"
752 "NumSocClkLevelsEnabled: %d\n"
753 "VcnClkLevelsEnabled: %d\n"
754 "NumDfPst atesEnabled: %d\n"
755 "MinGfxClk: %d\n"
756 "MaxGfxClk: %d\n",
757 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
758 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
759 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
760 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
761 smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
762 smu_dpm_clks.dpm_clks->MinGfxClk,
763 smu_dpm_clks.dpm_clks->MaxGfxClk);
764 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
765 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
766 i,
767 smu_dpm_clks.dpm_clks->DcfClocks[i]);
768 }
769 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
770 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
771 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
772 }
773 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
774 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
775 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
776 }
777 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
778 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
779 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
780
781 for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
782 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
783 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
784 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
785 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
786 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
787 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
788 }
789 if (ctx->dc_bios->integrated_info) {
790 dcn31_clk_mgr_helper_populate_bw_params(
791 &clk_mgr->base,
792 ctx->dc_bios->integrated_info,
793 smu_dpm_clks.dpm_clks);
794 }
795 }
796
797 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
798 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
799 smu_dpm_clks.dpm_clks);
800 }
801
dcn31_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)802 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
803 {
804 struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int);
805
806 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
807 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
808 clk_mgr->smu_wm_set.wm_set);
809 }
810