1 /***********************license start*********************************** 2 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). 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THE ENTIRE RISK 37 * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 #ifndef __LIBDRAM_CONFIG_H__ 40 #define __LIBDRAM_CONFIG_H__ 41 42 #include <libbdk-arch/bdk-csrs-lmc.h> 43 44 #define DDR_CFG_T_MAX_DIMMS 2 /* ThunderX supports a max of two DIMMs per LMC */ 45 46 /* Structure that provides DIMM information, either in the form of an SPD TWSI 47 address, or a pointer to an array that contains SPD data. One of the two 48 fields must be valid. Note that these fields historically were dimension 2, left 49 over from CN38XX/CN58XX. These chips supported a 128 bit wide LMC, requiring 50 two DIMMs. All other chips use a 64bit wide LMC with multiple LMCs. All 51 Thunder chips use one DIMM for 64bits, so we no longer use an index */ 52 typedef struct { 53 uint16_t spd_addr; /* TWSI address of SPD, 0 if not used */ 54 const uint8_t *spd_ptr; /* pointer to SPD data array, NULL if not used */ 55 } dimm_config_t; 56 57 typedef struct { 58 uint8_t odt_ena; /* FIX: dqx_ctl for Octeon 3 DDR4 */ 59 uint64_t odt_mask; /* FIX: wodt_mask for Octeon 3 */ 60 bdk_lmcx_modereg_params1_t odt_mask1; 61 bdk_lmcx_modereg_params2_t odt_mask2; /* FIX: needed for DDR4 */ 62 uint8_t qs_dic; /* FIX: rodt_ctl for Octeon 3 */ 63 uint64_t rodt_ctl; /* FIX: rodt_mask for Octeon 3 */ 64 } dimm_odt_config_t; 65 66 /* 67 The parameters below make up the custom_lmc_config data structure. 68 This structure is used to customize the way that the LMC DRAM 69 Controller is configured for a particular board design. 70 71 The HRM describes LMC Read Leveling which supports automatic 72 selection of per byte-lane delays. When measuring the read delays 73 the LMC configuration software sweeps through a range of settings 74 for LMC0_COMP_CTL2[RODT_CTL], the Octeon II on-die-termination 75 resistance and LMC0_MODEREG_PARAMS1[RTT_NOM_XX], the DRAM 76 on-die-termination resistance. The minimum and maximum parameters 77 for rtt_nom_idx and rodt_ctl listed below determine the ranges of 78 ODT settings used for the measurements. Note that for rtt_nom an 79 index is used into a sorted table rather than the direct csr setting 80 in order to optimize the sweep. 81 82 .min_rtt_nom_idx: 1=120ohms, 2=60ohms, 3=40ohms, 4=30ohms, 5=20ohms 83 .max_rtt_nom_idx: 1=120ohms, 2=60ohms, 3=40ohms, 4=30ohms, 5=20ohms 84 .min_rodt_ctl: 1=20ohms, 2=30ohms, 3=40ohms, 4=60ohms, 5=120ohms 85 .max_rodt_ctl: 1=20ohms, 2=30ohms, 3=40ohms, 4=60ohms, 5=120ohms 86 87 The settings below control the Octeon II drive strength for the CK, 88 ADD/CMD, and DQ/DQS signals. 1=24ohms, 2=26.67ohms, 3=30ohms, 89 4=34.3ohms, 5=40ohms, 6=48ohms, 6=60ohms. 90 91 .dqx_ctl: Drive strength control for DDR_DQX/DDR_DQS_X_P/N drivers. 92 .ck_ctl: Drive strength control for DDR_CK_X_P/DDR_DIMMX_CSX_L/DDR_DIMMX_ODT_X drivers. 93 .cmd_ctl: Drive strength control for CMD/A/RESET_L/CKEX drivers. 94 95 The LMC controller software selects the most optimal CAS Latency 96 that complies with the appropriate SPD values and the frequency 97 that the DRAMS are being operated. When operating the DRAMs at 98 frequencies substantially lower than their rated frequencies it 99 might be necessary to limit the minimum CAS Latency the LMC 100 controller software is allowed to select in order to make the DRAM 101 work reliably. 102 103 .min_cas_latency: Minimum allowed CAS Latency 104 105 106 The value used for LMC0_RLEVEL_CTL[OFFSET_EN] determine how the 107 read-leveling information that the Octeon II gathers is interpreted 108 to determine the per-byte read delays. 109 110 .offset_en: Value used for LMC0_RLEVEL_CTL[OFFSET_EN]. 111 .offset_udimm: Value used for LMC0_RLEVEL_CTL[OFFSET] for UDIMMS. 112 .offset_rdimm: Value used for LMC0_RLEVEL_CTL[OFFSET] for RDIMMS. 113 114 115 The LMC configuration software sweeps through a range of ODT 116 settings while measuring the per-byte read delays. During those 117 measurements the software makes an assessment of the quality of the 118 measurements in order to determine which measurements provide the 119 most accurate delays. The automatic settings provide the option to 120 allow that same assessment to determine the most optimal RODT_CTL 121 and/or RTT_NOM settings. 122 123 The automatic approach might provide the best means to determine 124 the settings used for initial poweron of a new design. However, 125 the final settings should be determined by board analysis, testing, 126 and experience. 127 128 .ddr_rtt_nom_auto: 1 means automatically set RTT_NOM value. 129 .ddr_rodt_ctl_auto: 1 means automatically set RODT_CTL value. 130 131 .rlevel_compute: Enables software interpretation of per-byte read 132 delays using the measurements collected by the 133 Octeon II rather than completely relying on the 134 Octeon II to determine the delays. 1=software 135 computation is recommended since a more complete 136 analysis is implemented in software. 137 138 .rlevel_comp_offset: Set to 2 unless instructed differently by Cavium. 139 140 .rlevel_average_loops: Determines the number of times the read-leveling 141 sequence is run for each rank. The results is 142 then averaged across the number of loops. The 143 default setting is 1. 144 145 .ddr2t_udimm: 146 .ddr2t_rdimm: Turn on the DDR 2T mode. 2-cycle window for CMD and 147 address. This mode helps relieve setup time pressure 148 on the address and command bus. Please refer to 149 Micron's tech note tn_47_01 titled DDR2-533 Memory 150 Design Guide for Two Dimm Unbuffered Systems for 151 physical details. 152 153 .disable_sequential_delay_check: As result of the flyby topology 154 prescribed in the JEDEC specifications the byte delays should 155 maintain a consistent increasing or decreasing trend across 156 the bytes on standard dimms. This setting can be used disable 157 that check for unusual circumstances where the check is not 158 useful. 159 160 .maximum_adjacent_rlevel_delay_increment: An additional sequential 161 delay check for the delays that result from the flyby 162 topology. This value specifies the maximum difference between 163 the delays of adjacent bytes. A value of 0 disables this 164 check. 165 166 .fprch2 Front Porch Enable: When set, the turn-off 167 time for the default DDR_DQ/DQS drivers is FPRCH2 CKs earlier. 168 00 = 0 CKs 169 01 = 1 CKs 170 10 = 2 CKs 171 172 .parity: The parity input signal PAR_IN on each dimm must be 173 strapped high or low on the board. This bit is programmed 174 into LMC0_DIMM_CTL[PARITY] and it must be set to match the 175 board strapping. This signal is typically strapped low. 176 177 .mode32b: Enable 32-bit datapath mode. Set to 1 if only 32 DQ pins 178 are used. (cn61xx, cn71xx) 179 180 .dll_write_offset: FIXME: Add description 181 .dll_read_offset: FIXME: Add description 182 */ 183 184 185 typedef struct { 186 const char *part; 187 int speed; 188 uint64_t rlevel_rank[4][4]; 189 } rlevel_table_t; 190 191 typedef struct { 192 uint8_t min_rtt_nom_idx; 193 uint8_t max_rtt_nom_idx; 194 uint8_t min_rodt_ctl; 195 uint8_t max_rodt_ctl; 196 //uint8_t dqx_ctl; 197 uint8_t ck_ctl; 198 uint8_t cmd_ctl; 199 uint8_t ctl_ctl; 200 uint8_t min_cas_latency; 201 uint8_t offset_en; 202 uint8_t offset_udimm; 203 uint8_t offset_rdimm; 204 uint8_t rlevel_compute; 205 uint8_t ddr_rtt_nom_auto; 206 uint8_t ddr_rodt_ctl_auto; 207 uint8_t rlevel_comp_offset_udimm; 208 uint8_t rlevel_comp_offset_rdimm; 209 uint8_t rlevel_average_loops; 210 uint8_t ddr2t_udimm; 211 uint8_t ddr2t_rdimm; 212 uint8_t disable_sequential_delay_check; 213 uint8_t maximum_adjacent_rlevel_delay_increment; 214 uint8_t parity; 215 uint8_t fprch2; 216 uint8_t mode32b; 217 uint8_t measured_vref; 218 const int8_t *dll_write_offset; /* Indexed by byte number (0-8, includes ecc byte) */ 219 const int8_t *dll_read_offset; /* Indexed by byte number (0-8, includes ecc byte) */ 220 const rlevel_table_t *rlevel_table; /* Only used if ENABLE_CUSTOM_RLEVEL_TABLE. List of DIMMs to check */ 221 } ddr3_custom_config_t; 222 223 typedef struct { 224 dimm_config_t dimm_config_table[DDR_CFG_T_MAX_DIMMS]; /* Indexed by DIMM */ 225 dimm_odt_config_t odt_1rank_config[DDR_CFG_T_MAX_DIMMS]; /* Indexed by number of DIMMs minus 1 */ 226 dimm_odt_config_t odt_2rank_config[DDR_CFG_T_MAX_DIMMS]; /* Indexed by number of DIMMs minus 1 */ 227 dimm_odt_config_t odt_4rank_config[DDR_CFG_T_MAX_DIMMS]; /* Indexed by number of DIMMs minus 1 */ 228 ddr3_custom_config_t custom_lmc_config; 229 } ddr_configuration_t; 230 231 typedef struct { 232 const char *name; 233 ddr_configuration_t config[4]; /* Indexed by LMC */ 234 int ddr_clock_hertz; 235 } dram_config_t; 236 237 extern int libdram_config(int node, const dram_config_t *dram_config, int ddr_clock_override); 238 extern int libdram_tune(int node); 239 //extern int libdram_margin_write_voltage(int node); 240 //extern int libdram_margin_read_voltage(int node); 241 //extern int libdram_margin_read_timing(int node); 242 //extern int libdram_margin_write_timing(int node); 243 extern int libdram_margin(int node); 244 extern uint32_t libdram_get_freq(int node); 245 extern uint32_t libdram_get_freq_from_pll(int node, int lmc); 246 247 /** 248 * Load a DRAM configuration based on the current bdk-config settings 249 * 250 * @param node Node the DRAM config is for 251 * 252 * @return Pointer to __libdram_global_cfg, a global structure. Returns NULL if bdk-config 253 * lacks information about DRAM. 254 */ 255 extern const dram_config_t* libdram_config_load(bdk_node_t node); 256 257 /* The various DRAM configs in the libdram/configs directory need space 258 to store the DRAM config. Since only one config is ever in active use 259 at a time, store the configs in __libdram_global_cfg. In a multi-node 260 setup, independent calls to get the DRAM config will load first node 0's 261 config, then node 1's */ 262 extern dram_config_t __libdram_global_cfg; 263 264 #endif /* __LIBDRAM_CONFIG_H__ */ 265