1 /***********************license start*********************************** 2 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * This Software, including technical data, may be subject to U.S. export 24 * control laws, including the U.S. Export Administration Act and its 25 * associated regulations, and may be subject to export or import 26 * regulations in other countries. 27 * 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT 31 * TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 32 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 33 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 34 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 35 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, 36 * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK 37 * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 extern const dimm_odt_config_t disable_odt_config[]; 41 42 #define rttnom_none 0 /* Rtt_Nom disabled */ 43 #define rttnom_60ohm 1 /* RZQ/4 = 240/4 = 60 ohms */ 44 #define rttnom_120ohm 2 /* RZQ/2 = 240/2 = 120 ohms */ 45 #define rttnom_40ohm 3 /* RZQ/6 = 240/6 = 40 ohms */ 46 #define rttnom_20ohm 4 /* RZQ/12 = 240/12 = 20 ohms */ 47 #define rttnom_30ohm 5 /* RZQ/8 = 240/8 = 30 ohms */ 48 #define rttnom_rsrv1 6 /* Reserved */ 49 #define rttnom_rsrv2 7 /* Reserved */ 50 51 #define rttwr_none 0 /* Dynamic ODT off */ 52 #define rttwr_60ohm 1 /* RZQ/4 = 240/4 = 60 ohms */ 53 #define rttwr_120ohm 2 /* RZQ/2 = 240/2 = 120 ohms */ 54 #define rttwr_rsrv1 3 /* Reserved */ 55 56 #define dic_40ohm 0 /* RZQ/6 = 240/6 = 40 ohms */ 57 #define dic_34ohm 1 /* RZQ/7 = 240/7 = 34 ohms */ 58 59 #define driver_24_ohm 1 60 #define driver_27_ohm 2 61 #define driver_30_ohm 3 62 #define driver_34_ohm 4 63 #define driver_40_ohm 5 64 #define driver_48_ohm 6 65 #define driver_60_ohm 7 66 67 #define rodt_ctl_none 0 68 #define rodt_ctl_20_ohm 1 69 #define rodt_ctl_30_ohm 2 70 #define rodt_ctl_40_ohm 3 71 #define rodt_ctl_60_ohm 4 72 #define rodt_ctl_120_ohm 5 73 74 #define ddr4_rttnom_none 0 /* Rtt_Nom disabled */ 75 #define ddr4_rttnom_60ohm 1 /* RZQ/4 = 240/4 = 60 ohms */ 76 #define ddr4_rttnom_120ohm 2 /* RZQ/2 = 240/2 = 120 ohms */ 77 #define ddr4_rttnom_40ohm 3 /* RZQ/6 = 240/6 = 40 ohms */ 78 #define ddr4_rttnom_240ohm 4 /* RZQ/1 = 240/1 = 240 ohms */ 79 #define ddr4_rttnom_48ohm 5 /* RZQ/5 = 240/5 = 48 ohms */ 80 #define ddr4_rttnom_80ohm 6 /* RZQ/3 = 240/3 = 80 ohms */ 81 #define ddr4_rttnom_34ohm 7 /* RZQ/7 = 240/7 = 34 ohms */ 82 83 #define ddr4_rttwr_none 0 /* Dynamic ODT off */ 84 #define ddr4_rttwr_120ohm 1 /* RZQ/2 = 240/2 = 120 ohms */ 85 #define ddr4_rttwr_240ohm 2 /* RZQ/1 = 240/1 = 240 ohms */ 86 #define ddr4_rttwr_HiZ 3 /* HiZ */ 87 /* This setting will be available for cn78xx cn88xx pass 2 and cn73xx 88 pass 1. It is disabled for now. */ 89 //#define ddr4_rttwr_80ohm 4 /* RZQ/3 = 240/3 = 80 ohms */ 90 91 #define ddr4_dic_34ohm 0 /* RZQ/7 = 240/7 = 34 ohms */ 92 #define ddr4_dic_48ohm 1 /* RZQ/5 = 240/5 = 48 ohms */ 93 94 #define ddr4_rttpark_none 0 /* Rtt_Park disabled */ 95 #define ddr4_rttpark_60ohm 1 /* RZQ/4 = 240/4 = 60 ohms */ 96 #define ddr4_rttpark_120ohm 2 /* RZQ/2 = 240/2 = 120 ohms */ 97 #define ddr4_rttpark_40ohm 3 /* RZQ/6 = 240/6 = 40 ohms */ 98 #define ddr4_rttpark_240ohm 4 /* RZQ/1 = 240/1 = 240 ohms */ 99 #define ddr4_rttpark_48ohm 5 /* RZQ/5 = 240/5 = 48 ohms */ 100 #define ddr4_rttpark_80ohm 6 /* RZQ/3 = 240/3 = 80 ohms */ 101 #define ddr4_rttpark_34ohm 7 /* RZQ/7 = 240/7 = 34 ohms */ 102 103 #define ddr4_driver_26_ohm 2 104 #define ddr4_driver_30_ohm 3 105 #define ddr4_driver_34_ohm 4 106 #define ddr4_driver_40_ohm 5 107 #define ddr4_driver_48_ohm 6 108 109 #define ddr4_dqx_driver_24_ohm 1 110 #define ddr4_dqx_driver_27_ohm 2 111 #define ddr4_dqx_driver_30_ohm 3 112 #define ddr4_dqx_driver_34_ohm 4 113 #define ddr4_dqx_driver_40_ohm 5 114 #define ddr4_dqx_driver_48_ohm 6 115 #define ddr4_dqx_driver_60_ohm 7 116 117 #define ddr4_rodt_ctl_none 0 118 #define ddr4_rodt_ctl_40_ohm 1 119 #define ddr4_rodt_ctl_60_ohm 2 120 #define ddr4_rodt_ctl_80_ohm 3 121 #define ddr4_rodt_ctl_120_ohm 4 122 #define ddr4_rodt_ctl_240_ohm 5 123 #define ddr4_rodt_ctl_34_ohm 6 124 #define ddr4_rodt_ctl_48_ohm 7 125