1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_MT8183_EMI_H 4 #define SOC_MEDIATEK_MT8183_EMI_H 5 6 #include <types.h> 7 #include <soc/dramc_common_mt8183.h> 8 9 enum DRAMC_PARAM_SOURCE { 10 DRAMC_PARAM_SOURCE_SDRAM_INVALID = 0, 11 DRAMC_PARAM_SOURCE_SDRAM_CONFIG, 12 DRAMC_PARAM_SOURCE_FLASH, 13 }; 14 15 struct sdram_params { 16 u16 source; /* DRAMC_PARAM_SOURCE */ 17 u16 frequency; 18 u32 rank_num; 19 u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ 20 u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; 21 22 /* DUTY */ 23 s8 duty_clk_delay[CHANNEL_MAX]; 24 s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER]; 25 26 /* CBT */ 27 u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; 28 u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]; 29 u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; 30 u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; 31 u8 cbt_ca_perbit_delay[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER]; 32 33 /* Gating */ 34 u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; 35 u8 gating05T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; 36 u8 gating_fine_tune[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; 37 u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; 38 39 /* TX perbit */ 40 u8 tx_vref[CHANNEL_MAX][RANK_MAX]; 41 u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; 42 u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; 43 u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; 44 u16 tx_first_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; 45 u16 tx_last_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; 46 47 /* datlat */ 48 u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; 49 50 /* RX perbit */ 51 u8 rx_vref[CHANNEL_MAX]; 52 s16 rx_firspass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; 53 u8 rx_lastpass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH]; 54 55 u32 emi_cona_val; 56 u32 emi_conh_val; 57 u32 emi_conf_val; 58 u32 chn_emi_cona_val[CHANNEL_MAX]; 59 u32 cbt_mode_extern; 60 u16 delay_cell_unit; 61 }; 62 63 struct dramc_param; 64 struct dramc_param_ops; 65 66 enum { 67 LP4X_DDR1600, 68 LP4X_DDR2400, 69 LP4X_DDR3200, 70 LP4X_DDR3600, 71 LP4X_DDRFREQ_MAX, 72 }; 73 74 struct dram_impedance { 75 u32 data[ODT_MAX][4]; 76 }; 77 78 struct mr_value { 79 u8 MR01Value[FSP_MAX]; 80 u8 MR13Value; 81 }; 82 83 struct dram_shared_data { 84 struct dram_impedance impedance; 85 struct mr_value mr; 86 }; 87 88 extern const u8 phy_mapping[CHANNEL_MAX][16]; 89 90 int complex_mem_test(u8 *start, unsigned int len); 91 size_t sdram_size(void); 92 const struct sdram_params *get_sdram_config(void); 93 void enable_emi_dcm(void); 94 int mt_set_emi(const struct dramc_param *dparam); 95 void mt_mem_init(struct dramc_param_ops *dparam_ops); 96 97 #endif /* SOC_MEDIATEK_MT8183_EMI_H */ 98