1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef __IA_CSS_EED1_8_PARAM_H 8 #define __IA_CSS_EED1_8_PARAM_H 9 10 #include "type_support.h" 11 #include "vmem.h" /* needed for VMEM_ARRAY */ 12 13 #include "ia_css_eed1_8_types.h" /* IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS */ 14 15 /* Configuration parameters: */ 16 17 /* Enable median for false color correction 18 * 0: Do not use median 19 * 1: Use median 20 * Default: 1 21 */ 22 #define EED1_8_FC_ENABLE_MEDIAN 1 23 24 /* Coring Threshold minima 25 * Used in Tint color suppression. 26 * Default: 1 27 */ 28 #define EED1_8_CORINGTHMIN 1 29 30 /* Define size of the state..... TODO: check if this is the correct place */ 31 /* 4 planes : GR, R, B, GB */ 32 #define NUM_PLANES 4 33 34 /* 5 lines state per color plane input_line_state */ 35 #define EED1_8_STATE_INPUT_BUFFER_HEIGHT (5 * NUM_PLANES) 36 37 /* Each plane has width equal to half frame line */ 38 #define EED1_8_STATE_INPUT_BUFFER_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 39 40 /* 1 line state per color plane LD_H state */ 41 #define EED1_8_STATE_LD_H_HEIGHT (1 * NUM_PLANES) 42 #define EED1_8_STATE_LD_H_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 43 44 /* 1 line state per color plane LD_V state */ 45 #define EED1_8_STATE_LD_V_HEIGHT (1 * NUM_PLANES) 46 #define EED1_8_STATE_LD_V_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 47 48 /* 1 line (single plane) state for D_Hr state */ 49 #define EED1_8_STATE_D_HR_HEIGHT 1 50 #define EED1_8_STATE_D_HR_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 51 52 /* 1 line (single plane) state for D_Hb state */ 53 #define EED1_8_STATE_D_HB_HEIGHT 1 54 #define EED1_8_STATE_D_HB_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 55 56 /* 2 lines (single plane) state for D_Vr state */ 57 #define EED1_8_STATE_D_VR_HEIGHT 2 58 #define EED1_8_STATE_D_VR_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 59 60 /* 2 line (single plane) state for D_Vb state */ 61 #define EED1_8_STATE_D_VB_HEIGHT 2 62 #define EED1_8_STATE_D_VB_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 63 64 /* 2 lines state for R and B (= 2 planes) rb_zipped_state */ 65 #define EED1_8_STATE_RB_ZIPPED_HEIGHT (2 * 2) 66 #define EED1_8_STATE_RB_ZIPPED_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 67 68 #if EED1_8_FC_ENABLE_MEDIAN 69 /* 1 full input line (GR-R color line) for Yc state */ 70 #define EED1_8_STATE_YC_HEIGHT 1 71 #define EED1_8_STATE_YC_WIDTH MAX_FRAME_SIMDWIDTH 72 73 /* 1 line state per color plane Cg_state */ 74 #define EED1_8_STATE_CG_HEIGHT (1 * NUM_PLANES) 75 #define EED1_8_STATE_CG_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 76 77 /* 1 line state per color plane Co_state */ 78 #define EED1_8_STATE_CO_HEIGHT (1 * NUM_PLANES) 79 #define EED1_8_STATE_CO_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) 80 81 /* 1 full input line (GR-R color line) for AbsK state */ 82 #define EED1_8_STATE_ABSK_HEIGHT 1 83 #define EED1_8_STATE_ABSK_WIDTH MAX_FRAME_SIMDWIDTH 84 #endif 85 86 struct eed1_8_vmem_params { 87 VMEM_ARRAY(e_dew_enh_x, ISP_VEC_NELEMS); 88 SVMEM_ARRAY(e_dew_enh_y, ISP_VEC_NELEMS); 89 SVMEM_ARRAY(e_dew_enh_a, ISP_VEC_NELEMS); 90 VMEM_ARRAY(e_dew_enh_f, ISP_VEC_NELEMS); 91 VMEM_ARRAY(chgrinv_x, ISP_VEC_NELEMS); 92 VMEM_ARRAY(chgrinv_a, ISP_VEC_NELEMS); 93 VMEM_ARRAY(chgrinv_b, ISP_VEC_NELEMS); 94 VMEM_ARRAY(chgrinv_c, ISP_VEC_NELEMS); 95 VMEM_ARRAY(fcinv_x, ISP_VEC_NELEMS); 96 VMEM_ARRAY(fcinv_a, ISP_VEC_NELEMS); 97 VMEM_ARRAY(fcinv_b, ISP_VEC_NELEMS); 98 VMEM_ARRAY(fcinv_c, ISP_VEC_NELEMS); 99 VMEM_ARRAY(tcinv_x, ISP_VEC_NELEMS); 100 VMEM_ARRAY(tcinv_a, ISP_VEC_NELEMS); 101 VMEM_ARRAY(tcinv_b, ISP_VEC_NELEMS); 102 VMEM_ARRAY(tcinv_c, ISP_VEC_NELEMS); 103 }; 104 105 /* EED (Edge Enhancing Demosaic) ISP parameters */ 106 struct eed1_8_dmem_params { 107 s32 rbzp_strength; 108 109 s32 fcstrength; 110 s32 fcthres_0; 111 s32 fc_sat_coef; 112 s32 fc_coring_prm; 113 s32 fc_slope; 114 115 s32 aerel_thres0; 116 s32 aerel_gain0; 117 s32 aerel_thres_diff; 118 s32 aerel_gain_diff; 119 120 s32 derel_thres0; 121 s32 derel_gain0; 122 s32 derel_thres_diff; 123 s32 derel_gain_diff; 124 125 s32 coring_pos0; 126 s32 coring_pos_diff; 127 s32 coring_neg0; 128 s32 coring_neg_diff; 129 130 s32 gain_exp; 131 s32 gain_pos0; 132 s32 gain_pos_diff; 133 s32 gain_neg0; 134 s32 gain_neg_diff; 135 136 s32 margin_pos0; 137 s32 margin_pos_diff; 138 s32 margin_neg0; 139 s32 margin_neg_diff; 140 141 s32 e_dew_enh_asr; 142 s32 dedgew_max; 143 }; 144 145 #endif /* __IA_CSS_EED1_8_PARAM_H */ 146