1 /*
2 * Copyright (C) 2021 Icecream95
3 * Copyright (C) 2019 Google LLC
4 * Copyright (C) 2024 Collabora, Ltd.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <limits.h>
27 #include <stdio.h>
28 #include <stdlib.h>
29 #include "drm-shim/drm_shim.h"
30 #include "drm-uapi/panfrost_drm.h"
31 #include "drm-uapi/panthor_drm.h"
32
33 #include "util/os_mman.h"
34 #include "util/u_math.h"
35
36 /* Default GPU ID if PAN_GPU_ID is not set. This defaults to Mali-G52. */
37 #define PAN_GPU_ID_DEFAULT (0x7212)
38
39 bool drm_shim_driver_prefers_first_render_node = true;
40
41 static uint64_t
pan_get_gpu_id(void)42 pan_get_gpu_id(void)
43 {
44 char *override_version = getenv("PAN_GPU_ID");
45
46 if (override_version)
47 return strtol(override_version, NULL, 16);
48
49 return PAN_GPU_ID_DEFAULT;
50 }
51
52 static int
pan_ioctl_noop(int fd,unsigned long request,void * arg)53 pan_ioctl_noop(int fd, unsigned long request, void *arg)
54 {
55 return 0;
56 }
57
58 static int
panfrost_ioctl_get_param(int fd,unsigned long request,void * arg)59 panfrost_ioctl_get_param(int fd, unsigned long request, void *arg)
60 {
61 struct drm_panfrost_get_param *gp = arg;
62
63 switch (gp->param) {
64 case DRM_PANFROST_PARAM_GPU_PROD_ID: {
65 gp->value = pan_get_gpu_id();
66 return 0;
67 }
68
69 case DRM_PANFROST_PARAM_SHADER_PRESENT:
70 /* Assume an MP4 GPU */
71 gp->value = 0xF;
72 return 0;
73 case DRM_PANFROST_PARAM_TILER_FEATURES:
74 gp->value = 0x809;
75 return 0;
76 case DRM_PANFROST_PARAM_TEXTURE_FEATURES0:
77 case DRM_PANFROST_PARAM_TEXTURE_FEATURES1:
78 case DRM_PANFROST_PARAM_TEXTURE_FEATURES2:
79 case DRM_PANFROST_PARAM_TEXTURE_FEATURES3:
80 /* Allow all compressed textures */
81 gp->value = ~0;
82 return 0;
83 case DRM_PANFROST_PARAM_GPU_REVISION:
84 case DRM_PANFROST_PARAM_THREAD_TLS_ALLOC:
85 case DRM_PANFROST_PARAM_AFBC_FEATURES:
86 case DRM_PANFROST_PARAM_THREAD_FEATURES:
87 case DRM_PANFROST_PARAM_MEM_FEATURES:
88 /* lazy default, but works for the purposes of drm_shim */
89 gp->value = 0x0;
90 return 0;
91 case DRM_PANFROST_PARAM_MMU_FEATURES:
92 /* default for most hardware so far */
93 gp->value = 0x00280030;
94 return 0;
95 case DRM_PANFROST_PARAM_MAX_THREADS:
96 case DRM_PANFROST_PARAM_THREAD_MAX_WORKGROUP_SZ:
97 gp->value = 256;
98 return 0;
99 default:
100 fprintf(stderr, "Unknown DRM_IOCTL_PANFROST_GET_PARAM %d\n", gp->param);
101 return -1;
102 }
103 }
104
105 static int
panfrost_ioctl_create_bo(int fd,unsigned long request,void * arg)106 panfrost_ioctl_create_bo(int fd, unsigned long request, void *arg)
107 {
108 struct drm_panfrost_create_bo *create = arg;
109
110 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
111 struct shim_bo *bo = calloc(1, sizeof(*bo));
112 size_t size = ALIGN(create->size, 4096);
113
114 drm_shim_bo_init(bo, size);
115
116 create->handle = drm_shim_bo_get_handle(shim_fd, bo);
117 create->offset = bo->mem_addr;
118
119 drm_shim_bo_put(bo);
120
121 return 0;
122 }
123
124 static int
panfrost_ioctl_mmap_bo(int fd,unsigned long request,void * arg)125 panfrost_ioctl_mmap_bo(int fd, unsigned long request, void *arg)
126 {
127 struct drm_panfrost_mmap_bo *mmap_bo = arg;
128
129 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
130 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, mmap_bo->handle);
131
132 mmap_bo->offset = drm_shim_bo_get_mmap_offset(shim_fd, bo);
133
134 return 0;
135 }
136
137 static int
panfrost_ioctl_madvise(int fd,unsigned long request,void * arg)138 panfrost_ioctl_madvise(int fd, unsigned long request, void *arg)
139 {
140 struct drm_panfrost_madvise *madvise = arg;
141
142 madvise->retained = 1;
143
144 return 0;
145 }
146
147 static ioctl_fn_t panfrost_driver_ioctls[] = {
148 [DRM_PANFROST_SUBMIT] = pan_ioctl_noop,
149 [DRM_PANFROST_WAIT_BO] = pan_ioctl_noop,
150 [DRM_PANFROST_CREATE_BO] = panfrost_ioctl_create_bo,
151 [DRM_PANFROST_MMAP_BO] = panfrost_ioctl_mmap_bo,
152 [DRM_PANFROST_GET_PARAM] = panfrost_ioctl_get_param,
153 [DRM_PANFROST_GET_BO_OFFSET] = pan_ioctl_noop,
154 [DRM_PANFROST_PERFCNT_ENABLE] = pan_ioctl_noop,
155 [DRM_PANFROST_PERFCNT_DUMP] = pan_ioctl_noop,
156 [DRM_PANFROST_MADVISE] = panfrost_ioctl_madvise,
157 };
158
159 static int
panthor_ioctl_dev_query(int fd,unsigned long request,void * arg)160 panthor_ioctl_dev_query(int fd, unsigned long request, void *arg)
161 {
162 struct drm_panthor_dev_query *dev_query = arg;
163
164 switch (dev_query->type) {
165 case DRM_PANTHOR_DEV_QUERY_GPU_INFO: {
166 struct drm_panthor_gpu_info *gpu_info =
167 (struct drm_panthor_gpu_info *)dev_query->pointer;
168
169 gpu_info->gpu_id = pan_get_gpu_id() << 16;
170 gpu_info->gpu_rev = 0;
171
172 /* Dumped from a G610 */
173 gpu_info->csf_id = 0x40a0412;
174 gpu_info->l2_features = 0x7120306;
175 gpu_info->tiler_features = 0x809;
176 gpu_info->mem_features = 0x301;
177 gpu_info->mmu_features = 0x2830;
178 gpu_info->thread_features = 0x4010000;
179 gpu_info->max_threads = 2048;
180 gpu_info->thread_max_workgroup_size = 1024;
181 gpu_info->thread_max_barrier_size = 1024;
182 gpu_info->coherency_features = 0;
183 gpu_info->texture_features[0] = 0xc1ffff9e;
184 gpu_info->as_present = 0xff;
185 gpu_info->shader_present = 0x50005;
186 gpu_info->l2_present = 1;
187 gpu_info->tiler_present = 1;
188 return 0;
189 }
190 case DRM_PANTHOR_DEV_QUERY_CSIF_INFO: {
191 struct drm_panthor_csif_info *csif_info =
192 (struct drm_panthor_csif_info *)dev_query->pointer;
193
194 /* Dumped from a G610 */
195 csif_info->csg_slot_count = 8;
196 csif_info->cs_slot_count = 8;
197 csif_info->cs_reg_count = 96;
198 csif_info->scoreboard_slot_count = 8;
199 csif_info->unpreserved_cs_reg_count = 4;
200 return 0;
201 }
202 default:
203 fprintf(stderr, "Unknown DRM_IOCTL_PANTHOR_DEV_QUERY %d\n",
204 dev_query->type);
205 return -1;
206 }
207
208 return 0;
209 }
210
211 static int
panthor_ioctl_bo_create(int fd,unsigned long request,void * arg)212 panthor_ioctl_bo_create(int fd, unsigned long request, void *arg)
213 {
214 struct drm_panthor_bo_create *bo_create = arg;
215
216 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
217 struct shim_bo *bo = calloc(1, sizeof(*bo));
218 size_t size = ALIGN(bo_create->size, 4096);
219
220 drm_shim_bo_init(bo, size);
221
222 bo_create->handle = drm_shim_bo_get_handle(shim_fd, bo);
223
224 drm_shim_bo_put(bo);
225
226 return 0;
227 }
228
229 static int
panthor_ioctl_bo_mmap_offset(int fd,unsigned long request,void * arg)230 panthor_ioctl_bo_mmap_offset(int fd, unsigned long request, void *arg)
231 {
232 struct drm_panthor_bo_mmap_offset *mmap_offset = arg;
233
234 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
235 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, mmap_offset->handle);
236
237 mmap_offset->offset = drm_shim_bo_get_mmap_offset(shim_fd, bo);
238
239 return 0;
240 }
241
242 static ioctl_fn_t panthor_driver_ioctls[] = {
243 [DRM_PANTHOR_DEV_QUERY] = panthor_ioctl_dev_query,
244 [DRM_PANTHOR_VM_CREATE] = pan_ioctl_noop,
245 [DRM_PANTHOR_VM_DESTROY] = pan_ioctl_noop,
246 [DRM_PANTHOR_VM_BIND] = pan_ioctl_noop,
247 [DRM_PANTHOR_VM_GET_STATE] = pan_ioctl_noop,
248 [DRM_PANTHOR_BO_CREATE] = panthor_ioctl_bo_create,
249 [DRM_PANTHOR_BO_MMAP_OFFSET] = panthor_ioctl_bo_mmap_offset,
250 [DRM_PANTHOR_GROUP_CREATE] = pan_ioctl_noop,
251 [DRM_PANTHOR_GROUP_DESTROY] = pan_ioctl_noop,
252 [DRM_PANTHOR_GROUP_SUBMIT] = pan_ioctl_noop,
253 [DRM_PANTHOR_GROUP_GET_STATE] = pan_ioctl_noop,
254 [DRM_PANTHOR_TILER_HEAP_CREATE] = pan_ioctl_noop,
255 [DRM_PANTHOR_TILER_HEAP_DESTROY] = pan_ioctl_noop,
256 };
257
258 static void *flush_id_mmap;
259
260 static void *
panthor_iomem_mmap(size_t size,int prot,int flags,off64_t offset)261 panthor_iomem_mmap(size_t size, int prot, int flags, off64_t offset)
262 {
263 switch (offset) {
264 case DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSET:
265 if (prot != PROT_READ || flags != MAP_SHARED || size != getpagesize())
266 return MAP_FAILED;
267
268 return flush_id_mmap;
269
270 default:
271 return MAP_FAILED;
272 }
273 }
274
275 void
drm_shim_driver_init(void)276 drm_shim_driver_init(void)
277 {
278 uint64_t gpu_id = pan_get_gpu_id();
279 bool is_csf_based = (gpu_id >> 12) > 9;
280
281 shim_device.bus_type = DRM_BUS_PLATFORM;
282
283 /* panfrost uses the DRM version to expose features, instead of getparam. */
284 shim_device.version_major = 1;
285 shim_device.version_minor = 1;
286 shim_device.version_patchlevel = 0;
287
288 if (is_csf_based) {
289 shim_device.driver_name = "panthor";
290 shim_device.driver_ioctls = panthor_driver_ioctls;
291 shim_device.driver_ioctl_count = ARRAY_SIZE(panthor_driver_ioctls);
292
293 flush_id_mmap = os_mmap(NULL, getpagesize(), PROT_READ | PROT_WRITE,
294 MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);
295 assert(flush_id_mmap != MAP_FAILED);
296 memset(flush_id_mmap, 0, getpagesize());
297
298 drm_shim_init_iomem_region(DRM_PANTHOR_USER_MMIO_OFFSET, getpagesize(),
299 panthor_iomem_mmap);
300
301 drm_shim_override_file("DRIVER=panthor\n"
302 "OF_FULLNAME=/soc/mali\n"
303 "OF_COMPATIBLE_0=arm,mali-valhall-csf\n"
304 "OF_COMPATIBLE_N=1\n",
305 "/sys/dev/char/%d:%d/device/uevent", DRM_MAJOR,
306 render_node_minor);
307 } else {
308 shim_device.driver_name = "panfrost";
309 shim_device.driver_ioctls = panfrost_driver_ioctls;
310 shim_device.driver_ioctl_count = ARRAY_SIZE(panfrost_driver_ioctls);
311
312 drm_shim_override_file("DRIVER=panfrost\n"
313 "OF_FULLNAME=/soc/mali\n"
314 "OF_COMPATIBLE_0=arm,mali-t860\n"
315 "OF_COMPATIBLE_N=1\n",
316 "/sys/dev/char/%d:%d/device/uevent", DRM_MAJOR,
317 render_node_minor);
318 }
319 }
320