1 #ifndef __BDK_CSRS_GSER_H__
2 #define __BDK_CSRS_GSER_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
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15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
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23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
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29 * regulations, and may be subject to export or import regulations in other
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31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium GSER.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration gser_bar_e
57 *
58 * GSER Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_GSER_BAR_E_GSERX_PF_BAR0(a) (0x87e090000000ll + 0x1000000ll * (a))
62 #define BDK_GSER_BAR_E_GSERX_PF_BAR0_SIZE 0x800000ull
63
64 /**
65 * Enumeration gser_lmode_e
66 *
67 * GSER Lane Mode Enumeration
68 * Enumerates the SerDes lane modes. See GSER()_LANE_MODE[LMODE].
69 */
70 #define BDK_GSER_LMODE_E_R_103125G_REFCLK15625_KR (5)
71 #define BDK_GSER_LMODE_E_R_125G_REFCLK15625_KX (3)
72 #define BDK_GSER_LMODE_E_R_125G_REFCLK15625_SGMII (6)
73 #define BDK_GSER_LMODE_E_R_25G_REFCLK100 (0)
74 #define BDK_GSER_LMODE_E_R_25G_REFCLK125 (9)
75 #define BDK_GSER_LMODE_E_R_3125G_REFCLK15625_XAUI (4)
76 #define BDK_GSER_LMODE_E_R_5G_REFCLK100 (1)
77 #define BDK_GSER_LMODE_E_R_5G_REFCLK125 (0xa)
78 #define BDK_GSER_LMODE_E_R_5G_REFCLK15625_QSGMII (7)
79 #define BDK_GSER_LMODE_E_R_625G_REFCLK15625_RXAUI (8)
80 #define BDK_GSER_LMODE_E_R_8G_REFCLK100 (2)
81 #define BDK_GSER_LMODE_E_R_8G_REFCLK125 (0xb)
82
83 /**
84 * Enumeration gser_qlm_e
85 *
86 * GSER QLM/CCPI Enumeration
87 * Enumerates the GSER to QLM.
88 */
89 #define BDK_GSER_QLM_E_GSER0 (0)
90 #define BDK_GSER_QLM_E_GSER1 (1)
91 #define BDK_GSER_QLM_E_GSER10 (0xa)
92 #define BDK_GSER_QLM_E_GSER11 (0xb)
93 #define BDK_GSER_QLM_E_GSER12 (0xc)
94 #define BDK_GSER_QLM_E_GSER13 (0xd)
95 #define BDK_GSER_QLM_E_GSER2 (2)
96 #define BDK_GSER_QLM_E_GSER3 (3)
97 #define BDK_GSER_QLM_E_GSER4 (4)
98 #define BDK_GSER_QLM_E_GSER5 (5)
99 #define BDK_GSER_QLM_E_GSER6 (6)
100 #define BDK_GSER_QLM_E_GSER7 (7)
101 #define BDK_GSER_QLM_E_GSER8 (8)
102 #define BDK_GSER_QLM_E_GSER9 (9)
103
104 /**
105 * Register (RSL) gser#_ana_atest
106 *
107 * GSER Analog Test Register
108 */
109 union bdk_gserx_ana_atest
110 {
111 uint64_t u;
112 struct bdk_gserx_ana_atest_s
113 {
114 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
115 uint64_t reserved_12_63 : 52;
116 uint64_t ana_dac_b : 7; /**< [ 11: 5](R/W) Controls the B-side DAC input to the analog test block. Note that the GSER2
117 register
118 is tied to the analog test block. The other GSER()_ANA_ATEST registers are
119 unused. For diagnostic use only. */
120 uint64_t ana_dac_a : 5; /**< [ 4: 0](R/W) Controls the A-side DAC input to the analog test block. Note that the GSER2 register is
121 tied to the analog test block. The other GSER()_ANA_ATEST registers are unused.
122 For diagnostic use only. */
123 #else /* Word 0 - Little Endian */
124 uint64_t ana_dac_a : 5; /**< [ 4: 0](R/W) Controls the A-side DAC input to the analog test block. Note that the GSER2 register is
125 tied to the analog test block. The other GSER()_ANA_ATEST registers are unused.
126 For diagnostic use only. */
127 uint64_t ana_dac_b : 7; /**< [ 11: 5](R/W) Controls the B-side DAC input to the analog test block. Note that the GSER2
128 register
129 is tied to the analog test block. The other GSER()_ANA_ATEST registers are
130 unused. For diagnostic use only. */
131 uint64_t reserved_12_63 : 52;
132 #endif /* Word 0 - End */
133 } s;
134 /* struct bdk_gserx_ana_atest_s cn81xx; */
135 struct bdk_gserx_ana_atest_cn88xx
136 {
137 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
138 uint64_t reserved_12_63 : 52;
139 uint64_t ana_dac_b : 7; /**< [ 11: 5](R/W) Controls the B-side DAC input to the analog test block. Note that the QLM4 register
140 is tied to the analog test block, for non-CCPI links. Note that the CCPI4 register is tied
141 to the analog test block, for CCPI links. The other GSER()_ANA_ATEST registers are
142 unused. For diagnostic use only. */
143 uint64_t ana_dac_a : 5; /**< [ 4: 0](R/W) Controls the A-side DAC input to the analog test block. Note that the QLM4 register is
144 tied to the analog test block, for non-CCPI links. Note that the CCPI4 register is tied to
145 the analog test block, for CCPI links. The other GSER()_ANA_ATEST registers are unused.
146 For diagnostic use only. */
147 #else /* Word 0 - Little Endian */
148 uint64_t ana_dac_a : 5; /**< [ 4: 0](R/W) Controls the A-side DAC input to the analog test block. Note that the QLM4 register is
149 tied to the analog test block, for non-CCPI links. Note that the CCPI4 register is tied to
150 the analog test block, for CCPI links. The other GSER()_ANA_ATEST registers are unused.
151 For diagnostic use only. */
152 uint64_t ana_dac_b : 7; /**< [ 11: 5](R/W) Controls the B-side DAC input to the analog test block. Note that the QLM4 register
153 is tied to the analog test block, for non-CCPI links. Note that the CCPI4 register is tied
154 to the analog test block, for CCPI links. The other GSER()_ANA_ATEST registers are
155 unused. For diagnostic use only. */
156 uint64_t reserved_12_63 : 52;
157 #endif /* Word 0 - End */
158 } cn88xx;
159 struct bdk_gserx_ana_atest_cn83xx
160 {
161 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
162 uint64_t reserved_12_63 : 52;
163 uint64_t ana_dac_b : 7; /**< [ 11: 5](R/W) Controls the B-side DAC input to the analog test block. Note that only
164 the GSER(4)_ANA_TEST[ANA_DAC_B] is tied to the analog test block.
165 The other GSER(0..3,5..6)_ANA_ATEST[ANA_DAC_B] are unused.
166 For diagnostic use only. */
167 uint64_t ana_dac_a : 5; /**< [ 4: 0](R/W) Controls A-side DAC input to the analog test block. Note that only
168 the GSER(4)_ANA_TEST[ANA_DAC_A] is tied to the analog test bloc.
169 The other GSER(0..3,5..6)_ANA_ATEST[ANA_DAC_A] are unused.
170 For diagnostic use only. */
171 #else /* Word 0 - Little Endian */
172 uint64_t ana_dac_a : 5; /**< [ 4: 0](R/W) Controls A-side DAC input to the analog test block. Note that only
173 the GSER(4)_ANA_TEST[ANA_DAC_A] is tied to the analog test bloc.
174 The other GSER(0..3,5..6)_ANA_ATEST[ANA_DAC_A] are unused.
175 For diagnostic use only. */
176 uint64_t ana_dac_b : 7; /**< [ 11: 5](R/W) Controls the B-side DAC input to the analog test block. Note that only
177 the GSER(4)_ANA_TEST[ANA_DAC_B] is tied to the analog test block.
178 The other GSER(0..3,5..6)_ANA_ATEST[ANA_DAC_B] are unused.
179 For diagnostic use only. */
180 uint64_t reserved_12_63 : 52;
181 #endif /* Word 0 - End */
182 } cn83xx;
183 };
184 typedef union bdk_gserx_ana_atest bdk_gserx_ana_atest_t;
185
186 static inline uint64_t BDK_GSERX_ANA_ATEST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_ANA_ATEST(unsigned long a)187 static inline uint64_t BDK_GSERX_ANA_ATEST(unsigned long a)
188 {
189 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
190 return 0x87e090000800ll + 0x1000000ll * ((a) & 0x3);
191 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
192 return 0x87e090000800ll + 0x1000000ll * ((a) & 0x7);
193 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
194 return 0x87e090000800ll + 0x1000000ll * ((a) & 0xf);
195 __bdk_csr_fatal("GSERX_ANA_ATEST", 1, a, 0, 0, 0);
196 }
197
198 #define typedef_BDK_GSERX_ANA_ATEST(a) bdk_gserx_ana_atest_t
199 #define bustype_BDK_GSERX_ANA_ATEST(a) BDK_CSR_TYPE_RSL
200 #define basename_BDK_GSERX_ANA_ATEST(a) "GSERX_ANA_ATEST"
201 #define device_bar_BDK_GSERX_ANA_ATEST(a) 0x0 /* PF_BAR0 */
202 #define busnum_BDK_GSERX_ANA_ATEST(a) (a)
203 #define arguments_BDK_GSERX_ANA_ATEST(a) (a),-1,-1,-1
204
205 /**
206 * Register (RSL) gser#_ana_sel
207 *
208 * GSER Analog Select Register
209 */
210 union bdk_gserx_ana_sel
211 {
212 uint64_t u;
213 struct bdk_gserx_ana_sel_s
214 {
215 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
216 uint64_t reserved_9_63 : 55;
217 uint64_t ana_sel : 9; /**< [ 8: 0](R/W) Controls the adr_global input to the analog test block. Note that the
218 GSER(2)_ANA_SEL.ANA_SEL register is tied to the analog test block.
219 The other GSER()_ANA_SEL registers are unused.
220 For diagnostic use only.
221
222 Used to power down the common clock input receiver to reduce power
223 consumption if the common clock input is not used.
224 If the common clock DLMC_REFCLK1_P/N input is unused program the GSER(2)_ANA_SEL.ANA_SEL
225 field to 0x1fd.
226 If the common clock DLMC_REFCLK0_P/N input is unused program the GSER(2)_ANA_SEL.ANA_SEL
227 field to 0x1fe.
228 If both common clock DLMC_REFCLK0_P/N and DLMC_REFCLK1_P/N inputs are unused program the
229 GSER(2)_ANA_SEL.ANA_SEL field to 0x1fc. */
230 #else /* Word 0 - Little Endian */
231 uint64_t ana_sel : 9; /**< [ 8: 0](R/W) Controls the adr_global input to the analog test block. Note that the
232 GSER(2)_ANA_SEL.ANA_SEL register is tied to the analog test block.
233 The other GSER()_ANA_SEL registers are unused.
234 For diagnostic use only.
235
236 Used to power down the common clock input receiver to reduce power
237 consumption if the common clock input is not used.
238 If the common clock DLMC_REFCLK1_P/N input is unused program the GSER(2)_ANA_SEL.ANA_SEL
239 field to 0x1fd.
240 If the common clock DLMC_REFCLK0_P/N input is unused program the GSER(2)_ANA_SEL.ANA_SEL
241 field to 0x1fe.
242 If both common clock DLMC_REFCLK0_P/N and DLMC_REFCLK1_P/N inputs are unused program the
243 GSER(2)_ANA_SEL.ANA_SEL field to 0x1fc. */
244 uint64_t reserved_9_63 : 55;
245 #endif /* Word 0 - End */
246 } s;
247 struct bdk_gserx_ana_sel_cn88xxp1
248 {
249 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
250 uint64_t reserved_9_63 : 55;
251 uint64_t ana_sel : 9; /**< [ 8: 0](R/W) Controls the adr_global input to the analog test block. Note that the QLM0 register
252 is tied to the analog test block, for non-CCPI links. Note that the QLM8 register is tied
253 to the analog test block, for CCPI links. The other GSER()_ANA_SEL registers are unused.
254 For diagnostic use only. */
255 #else /* Word 0 - Little Endian */
256 uint64_t ana_sel : 9; /**< [ 8: 0](R/W) Controls the adr_global input to the analog test block. Note that the QLM0 register
257 is tied to the analog test block, for non-CCPI links. Note that the QLM8 register is tied
258 to the analog test block, for CCPI links. The other GSER()_ANA_SEL registers are unused.
259 For diagnostic use only. */
260 uint64_t reserved_9_63 : 55;
261 #endif /* Word 0 - End */
262 } cn88xxp1;
263 /* struct bdk_gserx_ana_sel_s cn81xx; */
264 struct bdk_gserx_ana_sel_cn83xx
265 {
266 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
267 uint64_t reserved_9_63 : 55;
268 uint64_t ana_sel : 9; /**< [ 8: 0](R/W) Controls the adr_global input to the analog test block. Note that only
269 the GSER(4)_ANA_SEL.ANA_SEL register is tied to the analog test block.
270 The GSER(0..3,5..6)_ANA_SEL.ANA_SEL registers are unused.
271
272 Used to power down the common clock input receiver to reduce power consumption
273 if the common clock input is not used.
274 If the common clock QLMC_REFCLK1_P/N input is unused program the
275 GSER(4)_ANA_SEL.ANA_SEL field to 0x1FD.
276 If the common clock QLMC_REFCLK0_P/N input is unused program the
277 GSER(4)_ANA_SEL.ANA_SEL field to 0x1FE.
278 If both common clock QLMC_REFCLK0_P/N and QLMC_REFCLK1_P/N inputs are unused program the
279 GSER(4)_ANA_SEL[ANA_SEL] field to 0x1FC.
280 For diagnostic use only. */
281 #else /* Word 0 - Little Endian */
282 uint64_t ana_sel : 9; /**< [ 8: 0](R/W) Controls the adr_global input to the analog test block. Note that only
283 the GSER(4)_ANA_SEL.ANA_SEL register is tied to the analog test block.
284 The GSER(0..3,5..6)_ANA_SEL.ANA_SEL registers are unused.
285
286 Used to power down the common clock input receiver to reduce power consumption
287 if the common clock input is not used.
288 If the common clock QLMC_REFCLK1_P/N input is unused program the
289 GSER(4)_ANA_SEL.ANA_SEL field to 0x1FD.
290 If the common clock QLMC_REFCLK0_P/N input is unused program the
291 GSER(4)_ANA_SEL.ANA_SEL field to 0x1FE.
292 If both common clock QLMC_REFCLK0_P/N and QLMC_REFCLK1_P/N inputs are unused program the
293 GSER(4)_ANA_SEL[ANA_SEL] field to 0x1FC.
294 For diagnostic use only. */
295 uint64_t reserved_9_63 : 55;
296 #endif /* Word 0 - End */
297 } cn83xx;
298 struct bdk_gserx_ana_sel_cn88xxp2
299 {
300 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
301 uint64_t reserved_9_63 : 55;
302 uint64_t ana_sel : 9; /**< [ 8: 0](R/W) Controls the adr_global input to the analog test block. Note that the
303 GSER(0)_ANA_SEL.ANA_SEL register is tied to the analog test block, for non-CCPI links.
304 Note that the GSER(8)_ANA_SEL.ANA_SEL register is tied to the analog test block, for
305 CCPI links. The other GSER()_ANA_SEL registers are unused.
306 For diagnostic use only.
307
308 For non-CCPI links used to power down the common clock input receiver to reduce power
309 consumption if the common clock input is not used.
310 If the common clock QLMC_REFCLK1_P/N input is unused, program GSER(0)_ANA_SEL[ANA_SEL]
311 to 0x1FD.
312 If the common clock QLMC_REFCLK0_P/N input is unused, program GSER(0)_ANA_SEL[ANA_SEL]
313 to 0x1FE.
314 If both common clock QLMC_REFCLK0_P/N and QLMC_REFCLK1_P/N inputs are unused, program
315 GSER(0)_ANA_SEL[ANA_SEL] to 0x1FC.
316
317 For CCPI links used to power down the common clock input receiver to reduce power
318 consumption if the common clock input is not used.
319 If the common clock OCIC_REF_CLK_P/N input is unused, program GSER(8)_ANA_SEL[ANA_SEL]
320 field to 0x1FC. */
321 #else /* Word 0 - Little Endian */
322 uint64_t ana_sel : 9; /**< [ 8: 0](R/W) Controls the adr_global input to the analog test block. Note that the
323 GSER(0)_ANA_SEL.ANA_SEL register is tied to the analog test block, for non-CCPI links.
324 Note that the GSER(8)_ANA_SEL.ANA_SEL register is tied to the analog test block, for
325 CCPI links. The other GSER()_ANA_SEL registers are unused.
326 For diagnostic use only.
327
328 For non-CCPI links used to power down the common clock input receiver to reduce power
329 consumption if the common clock input is not used.
330 If the common clock QLMC_REFCLK1_P/N input is unused, program GSER(0)_ANA_SEL[ANA_SEL]
331 to 0x1FD.
332 If the common clock QLMC_REFCLK0_P/N input is unused, program GSER(0)_ANA_SEL[ANA_SEL]
333 to 0x1FE.
334 If both common clock QLMC_REFCLK0_P/N and QLMC_REFCLK1_P/N inputs are unused, program
335 GSER(0)_ANA_SEL[ANA_SEL] to 0x1FC.
336
337 For CCPI links used to power down the common clock input receiver to reduce power
338 consumption if the common clock input is not used.
339 If the common clock OCIC_REF_CLK_P/N input is unused, program GSER(8)_ANA_SEL[ANA_SEL]
340 field to 0x1FC. */
341 uint64_t reserved_9_63 : 55;
342 #endif /* Word 0 - End */
343 } cn88xxp2;
344 };
345 typedef union bdk_gserx_ana_sel bdk_gserx_ana_sel_t;
346
347 static inline uint64_t BDK_GSERX_ANA_SEL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_ANA_SEL(unsigned long a)348 static inline uint64_t BDK_GSERX_ANA_SEL(unsigned long a)
349 {
350 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
351 return 0x87e090000808ll + 0x1000000ll * ((a) & 0x3);
352 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
353 return 0x87e090000808ll + 0x1000000ll * ((a) & 0x7);
354 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
355 return 0x87e090000808ll + 0x1000000ll * ((a) & 0xf);
356 __bdk_csr_fatal("GSERX_ANA_SEL", 1, a, 0, 0, 0);
357 }
358
359 #define typedef_BDK_GSERX_ANA_SEL(a) bdk_gserx_ana_sel_t
360 #define bustype_BDK_GSERX_ANA_SEL(a) BDK_CSR_TYPE_RSL
361 #define basename_BDK_GSERX_ANA_SEL(a) "GSERX_ANA_SEL"
362 #define device_bar_BDK_GSERX_ANA_SEL(a) 0x0 /* PF_BAR0 */
363 #define busnum_BDK_GSERX_ANA_SEL(a) (a)
364 #define arguments_BDK_GSERX_ANA_SEL(a) (a),-1,-1,-1
365
366 /**
367 * Register (RSL) gser#_br_rx#_ctl
368 *
369 * GSER Base-R RX Control Register
370 */
371 union bdk_gserx_br_rxx_ctl
372 {
373 uint64_t u;
374 struct bdk_gserx_br_rxx_ctl_s
375 {
376 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
377 uint64_t reserved_4_63 : 60;
378 uint64_t rxt_adtmout_disable : 1; /**< [ 3: 3](R/W) For BASE-R links the terminating condition for link training receiver adaptation
379 is a 330 milliseconds time-out timer. When the receiver adaptation time-out timer
380 expires the receiver adaptation process is concluded and the link is considered good.
381 Note that when BASE-R link training is performed under software control,
382 (GSER()_BR_RX()_CTL[RXT_SWM] is set), the receiver adaptation time-out timer is disabled
383 and not used.
384
385 Set this bit to a one to disable the link training receiver adaptation time-out
386 timer during BASE-R link training under hardware control. For diagnostic use only. */
387 uint64_t rxt_swm : 1; /**< [ 2: 2](R/W) Set when RX BASE-R link training is to be performed under software control.
388
389 See GSER()_BR_RX()_EER[EXT_EER]. */
390 uint64_t rxt_preset : 1; /**< [ 1: 1](R/W) For all link training, this bit determines how to configure the preset bit in the
391 coefficient update message that is sent to the far end transmitter. When set, a one time
392 request is made that the coefficients be set to a state where equalization is turned off.
393
394 To perform a preset, set this bit prior to link training. Link training needs to be
395 disabled to complete the request and get the rxtrain state machine back to idle. Note that
396 it is illegal to set both the preset and initialize bits at the same time. For diagnostic
397 use only. */
398 uint64_t rxt_initialize : 1; /**< [ 0: 0](R/W) For all link training, this bit determines how to configure the initialize bit in the
399 coefficient update message that is sent to the far end transmitter of RX training. When
400 set, a request is made that the coefficients be set to its INITIALIZE state. To perform an
401 initialize prior to link training, set this bit prior to performing link training. Note
402 that it is illegal to set both the preset and initialize bits at the same time. Since the
403 far end transmitter is required to be initialized prior to starting link training, it is
404 not expected that software will need to set this bit. For diagnostic use only. */
405 #else /* Word 0 - Little Endian */
406 uint64_t rxt_initialize : 1; /**< [ 0: 0](R/W) For all link training, this bit determines how to configure the initialize bit in the
407 coefficient update message that is sent to the far end transmitter of RX training. When
408 set, a request is made that the coefficients be set to its INITIALIZE state. To perform an
409 initialize prior to link training, set this bit prior to performing link training. Note
410 that it is illegal to set both the preset and initialize bits at the same time. Since the
411 far end transmitter is required to be initialized prior to starting link training, it is
412 not expected that software will need to set this bit. For diagnostic use only. */
413 uint64_t rxt_preset : 1; /**< [ 1: 1](R/W) For all link training, this bit determines how to configure the preset bit in the
414 coefficient update message that is sent to the far end transmitter. When set, a one time
415 request is made that the coefficients be set to a state where equalization is turned off.
416
417 To perform a preset, set this bit prior to link training. Link training needs to be
418 disabled to complete the request and get the rxtrain state machine back to idle. Note that
419 it is illegal to set both the preset and initialize bits at the same time. For diagnostic
420 use only. */
421 uint64_t rxt_swm : 1; /**< [ 2: 2](R/W) Set when RX BASE-R link training is to be performed under software control.
422
423 See GSER()_BR_RX()_EER[EXT_EER]. */
424 uint64_t rxt_adtmout_disable : 1; /**< [ 3: 3](R/W) For BASE-R links the terminating condition for link training receiver adaptation
425 is a 330 milliseconds time-out timer. When the receiver adaptation time-out timer
426 expires the receiver adaptation process is concluded and the link is considered good.
427 Note that when BASE-R link training is performed under software control,
428 (GSER()_BR_RX()_CTL[RXT_SWM] is set), the receiver adaptation time-out timer is disabled
429 and not used.
430
431 Set this bit to a one to disable the link training receiver adaptation time-out
432 timer during BASE-R link training under hardware control. For diagnostic use only. */
433 uint64_t reserved_4_63 : 60;
434 #endif /* Word 0 - End */
435 } s;
436 struct bdk_gserx_br_rxx_ctl_cn88xxp1
437 {
438 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
439 uint64_t reserved_4_63 : 60;
440 uint64_t reserved_3 : 1;
441 uint64_t rxt_swm : 1; /**< [ 2: 2](R/W) Set when RX BASE-R link training is to be performed under software control.
442
443 See GSER()_BR_RX()_EER[EXT_EER]. */
444 uint64_t rxt_preset : 1; /**< [ 1: 1](R/W) For all link training, this bit determines how to configure the preset bit in the
445 coefficient update message that is sent to the far end transmitter. When set, a one time
446 request is made that the coefficients be set to a state where equalization is turned off.
447
448 To perform a preset, set this bit prior to link training. Link training needs to be
449 disabled to complete the request and get the rxtrain state machine back to idle. Note that
450 it is illegal to set both the preset and initialize bits at the same time. For diagnostic
451 use only. */
452 uint64_t rxt_initialize : 1; /**< [ 0: 0](R/W) For all link training, this bit determines how to configure the initialize bit in the
453 coefficient update message that is sent to the far end transmitter of RX training. When
454 set, a request is made that the coefficients be set to its INITIALIZE state. To perform an
455 initialize prior to link training, set this bit prior to performing link training. Note
456 that it is illegal to set both the preset and initialize bits at the same time. Since the
457 far end transmitter is required to be initialized prior to starting link training, it is
458 not expected that software will need to set this bit. For diagnostic use only. */
459 #else /* Word 0 - Little Endian */
460 uint64_t rxt_initialize : 1; /**< [ 0: 0](R/W) For all link training, this bit determines how to configure the initialize bit in the
461 coefficient update message that is sent to the far end transmitter of RX training. When
462 set, a request is made that the coefficients be set to its INITIALIZE state. To perform an
463 initialize prior to link training, set this bit prior to performing link training. Note
464 that it is illegal to set both the preset and initialize bits at the same time. Since the
465 far end transmitter is required to be initialized prior to starting link training, it is
466 not expected that software will need to set this bit. For diagnostic use only. */
467 uint64_t rxt_preset : 1; /**< [ 1: 1](R/W) For all link training, this bit determines how to configure the preset bit in the
468 coefficient update message that is sent to the far end transmitter. When set, a one time
469 request is made that the coefficients be set to a state where equalization is turned off.
470
471 To perform a preset, set this bit prior to link training. Link training needs to be
472 disabled to complete the request and get the rxtrain state machine back to idle. Note that
473 it is illegal to set both the preset and initialize bits at the same time. For diagnostic
474 use only. */
475 uint64_t rxt_swm : 1; /**< [ 2: 2](R/W) Set when RX BASE-R link training is to be performed under software control.
476
477 See GSER()_BR_RX()_EER[EXT_EER]. */
478 uint64_t reserved_3 : 1;
479 uint64_t reserved_4_63 : 60;
480 #endif /* Word 0 - End */
481 } cn88xxp1;
482 /* struct bdk_gserx_br_rxx_ctl_s cn81xx; */
483 /* struct bdk_gserx_br_rxx_ctl_s cn83xx; */
484 /* struct bdk_gserx_br_rxx_ctl_s cn88xxp2; */
485 };
486 typedef union bdk_gserx_br_rxx_ctl bdk_gserx_br_rxx_ctl_t;
487
488 static inline uint64_t BDK_GSERX_BR_RXX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_BR_RXX_CTL(unsigned long a,unsigned long b)489 static inline uint64_t BDK_GSERX_BR_RXX_CTL(unsigned long a, unsigned long b)
490 {
491 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=3)))
492 return 0x87e090000400ll + 0x1000000ll * ((a) & 0x3) + 0x80ll * ((b) & 0x3);
493 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
494 return 0x87e090000400ll + 0x1000000ll * ((a) & 0x7) + 0x80ll * ((b) & 0x3);
495 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
496 return 0x87e090000400ll + 0x1000000ll * ((a) & 0xf) + 0x80ll * ((b) & 0x3);
497 __bdk_csr_fatal("GSERX_BR_RXX_CTL", 2, a, b, 0, 0);
498 }
499
500 #define typedef_BDK_GSERX_BR_RXX_CTL(a,b) bdk_gserx_br_rxx_ctl_t
501 #define bustype_BDK_GSERX_BR_RXX_CTL(a,b) BDK_CSR_TYPE_RSL
502 #define basename_BDK_GSERX_BR_RXX_CTL(a,b) "GSERX_BR_RXX_CTL"
503 #define device_bar_BDK_GSERX_BR_RXX_CTL(a,b) 0x0 /* PF_BAR0 */
504 #define busnum_BDK_GSERX_BR_RXX_CTL(a,b) (a)
505 #define arguments_BDK_GSERX_BR_RXX_CTL(a,b) (a),(b),-1,-1
506
507 /**
508 * Register (RSL) gser#_br_rx#_eer
509 *
510 * GSER Base-R RX Equalization Evaluation Request Register
511 * GSER software BASE-R RX link training equalization evaluation request (EER). A write to
512 * [RXT_EER] initiates a equalization request to the RAW PCS. A read of this register returns the
513 * equalization status message and a valid bit indicating it was updated. These registers are for
514 * diagnostic use only.
515 */
516 union bdk_gserx_br_rxx_eer
517 {
518 uint64_t u;
519 struct bdk_gserx_br_rxx_eer_s
520 {
521 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
522 uint64_t reserved_16_63 : 48;
523 uint64_t rxt_eer : 1; /**< [ 15: 15](WO) When RX BASE-R link training is being performed under software control,
524 (GSER()_BR_RX()_CTL[RXT_SWM] is set), writing this bit initiates an equalization
525 request to the RAW PCS. Reading this bit always returns a zero.
526
527 When auto-negotiated link training is not present and link speed \>= 5 Gbaud,
528 including XFI, receiver (only) equalization should be manually performed.
529 After GSER()_BR_RX()_CTL[RXT_SWM] is set, writing this CSR with
530 [RXT_EER]=1 initiates this manual equalization. The operation may take up to
531 2 milliseconds, and then hardware sets [RXT_ESV]. The SerDes input should
532 be a pattern (something similar to the BASE-R training sequence, ideally)
533 during this receiver-only training. If DFE is to be disabled
534 (recommended for 5 Gbaud and below), do it prior to this receiver-only
535 initialization. (GSER()_LANE()_RX_VALBBD_CTRL_0, GSER()_LANE()_RX_VALBBD_CTRL_1,
536 and GSER()_LANE()_RX_VALBBD_CTRL_2 configure the DFE.) */
537 uint64_t rxt_esv : 1; /**< [ 14: 14](R/W) When performing an equalization request (RXT_EER), this bit, when set, indicates that the
538 Equalization Status (RXT_ESM) is valid. When issuing a RXT_EER request, it is expected
539 that RXT_ESV will get written to zero so that a valid RXT_ESM can be determined. */
540 uint64_t rxt_esm : 14; /**< [ 13: 0](RO) When performing an equalization request (RXT_EER), this is the equalization status message
541 from the RAW PCS. It is valid when RXT_ESV is set.
542
543 _ \<13:6\>: Figure of merit. An 8-bit output from the PHY indicating the quality of the
544 received data eye. A higher value indicates better link equalization, with 8'd0 indicating
545 worst equalization setting and 8'd255 indicating the best equalization setting.
546
547 _ \<5:4\>: RX recommended TXPOST direction change.
548
549 _ \<3:2\>: RX recommended TXMAIN direction change.
550
551 _ \<1:0\>: RX recommended TXPRE direction change.
552
553 Recommended direction change outputs from the PHY for the link partner transmitter
554 coefficients.
555 0x0 = Hold.
556 0x1 = Increment.
557 0x2 = Decrement.
558 0x3 = Hold. */
559 #else /* Word 0 - Little Endian */
560 uint64_t rxt_esm : 14; /**< [ 13: 0](RO) When performing an equalization request (RXT_EER), this is the equalization status message
561 from the RAW PCS. It is valid when RXT_ESV is set.
562
563 _ \<13:6\>: Figure of merit. An 8-bit output from the PHY indicating the quality of the
564 received data eye. A higher value indicates better link equalization, with 8'd0 indicating
565 worst equalization setting and 8'd255 indicating the best equalization setting.
566
567 _ \<5:4\>: RX recommended TXPOST direction change.
568
569 _ \<3:2\>: RX recommended TXMAIN direction change.
570
571 _ \<1:0\>: RX recommended TXPRE direction change.
572
573 Recommended direction change outputs from the PHY for the link partner transmitter
574 coefficients.
575 0x0 = Hold.
576 0x1 = Increment.
577 0x2 = Decrement.
578 0x3 = Hold. */
579 uint64_t rxt_esv : 1; /**< [ 14: 14](R/W) When performing an equalization request (RXT_EER), this bit, when set, indicates that the
580 Equalization Status (RXT_ESM) is valid. When issuing a RXT_EER request, it is expected
581 that RXT_ESV will get written to zero so that a valid RXT_ESM can be determined. */
582 uint64_t rxt_eer : 1; /**< [ 15: 15](WO) When RX BASE-R link training is being performed under software control,
583 (GSER()_BR_RX()_CTL[RXT_SWM] is set), writing this bit initiates an equalization
584 request to the RAW PCS. Reading this bit always returns a zero.
585
586 When auto-negotiated link training is not present and link speed \>= 5 Gbaud,
587 including XFI, receiver (only) equalization should be manually performed.
588 After GSER()_BR_RX()_CTL[RXT_SWM] is set, writing this CSR with
589 [RXT_EER]=1 initiates this manual equalization. The operation may take up to
590 2 milliseconds, and then hardware sets [RXT_ESV]. The SerDes input should
591 be a pattern (something similar to the BASE-R training sequence, ideally)
592 during this receiver-only training. If DFE is to be disabled
593 (recommended for 5 Gbaud and below), do it prior to this receiver-only
594 initialization. (GSER()_LANE()_RX_VALBBD_CTRL_0, GSER()_LANE()_RX_VALBBD_CTRL_1,
595 and GSER()_LANE()_RX_VALBBD_CTRL_2 configure the DFE.) */
596 uint64_t reserved_16_63 : 48;
597 #endif /* Word 0 - End */
598 } s;
599 /* struct bdk_gserx_br_rxx_eer_s cn; */
600 };
601 typedef union bdk_gserx_br_rxx_eer bdk_gserx_br_rxx_eer_t;
602
603 static inline uint64_t BDK_GSERX_BR_RXX_EER(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_BR_RXX_EER(unsigned long a,unsigned long b)604 static inline uint64_t BDK_GSERX_BR_RXX_EER(unsigned long a, unsigned long b)
605 {
606 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=3)))
607 return 0x87e090000418ll + 0x1000000ll * ((a) & 0x3) + 0x80ll * ((b) & 0x3);
608 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
609 return 0x87e090000418ll + 0x1000000ll * ((a) & 0x7) + 0x80ll * ((b) & 0x3);
610 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
611 return 0x87e090000418ll + 0x1000000ll * ((a) & 0xf) + 0x80ll * ((b) & 0x3);
612 __bdk_csr_fatal("GSERX_BR_RXX_EER", 2, a, b, 0, 0);
613 }
614
615 #define typedef_BDK_GSERX_BR_RXX_EER(a,b) bdk_gserx_br_rxx_eer_t
616 #define bustype_BDK_GSERX_BR_RXX_EER(a,b) BDK_CSR_TYPE_RSL
617 #define basename_BDK_GSERX_BR_RXX_EER(a,b) "GSERX_BR_RXX_EER"
618 #define device_bar_BDK_GSERX_BR_RXX_EER(a,b) 0x0 /* PF_BAR0 */
619 #define busnum_BDK_GSERX_BR_RXX_EER(a,b) (a)
620 #define arguments_BDK_GSERX_BR_RXX_EER(a,b) (a),(b),-1,-1
621
622 /**
623 * Register (RSL) gser#_br_tx#_ctl
624 *
625 * GSER Base-R TX Control Register
626 */
627 union bdk_gserx_br_txx_ctl
628 {
629 uint64_t u;
630 struct bdk_gserx_br_txx_ctl_s
631 {
632 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
633 uint64_t reserved_1_63 : 63;
634 uint64_t txt_swm : 1; /**< [ 0: 0](R/W) Set when TX BASE-R link training is to be performed under software control. For diagnostic
635 use only. */
636 #else /* Word 0 - Little Endian */
637 uint64_t txt_swm : 1; /**< [ 0: 0](R/W) Set when TX BASE-R link training is to be performed under software control. For diagnostic
638 use only. */
639 uint64_t reserved_1_63 : 63;
640 #endif /* Word 0 - End */
641 } s;
642 /* struct bdk_gserx_br_txx_ctl_s cn; */
643 };
644 typedef union bdk_gserx_br_txx_ctl bdk_gserx_br_txx_ctl_t;
645
646 static inline uint64_t BDK_GSERX_BR_TXX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_BR_TXX_CTL(unsigned long a,unsigned long b)647 static inline uint64_t BDK_GSERX_BR_TXX_CTL(unsigned long a, unsigned long b)
648 {
649 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=3)))
650 return 0x87e090000420ll + 0x1000000ll * ((a) & 0x3) + 0x80ll * ((b) & 0x3);
651 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
652 return 0x87e090000420ll + 0x1000000ll * ((a) & 0x7) + 0x80ll * ((b) & 0x3);
653 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
654 return 0x87e090000420ll + 0x1000000ll * ((a) & 0xf) + 0x80ll * ((b) & 0x3);
655 __bdk_csr_fatal("GSERX_BR_TXX_CTL", 2, a, b, 0, 0);
656 }
657
658 #define typedef_BDK_GSERX_BR_TXX_CTL(a,b) bdk_gserx_br_txx_ctl_t
659 #define bustype_BDK_GSERX_BR_TXX_CTL(a,b) BDK_CSR_TYPE_RSL
660 #define basename_BDK_GSERX_BR_TXX_CTL(a,b) "GSERX_BR_TXX_CTL"
661 #define device_bar_BDK_GSERX_BR_TXX_CTL(a,b) 0x0 /* PF_BAR0 */
662 #define busnum_BDK_GSERX_BR_TXX_CTL(a,b) (a)
663 #define arguments_BDK_GSERX_BR_TXX_CTL(a,b) (a),(b),-1,-1
664
665 /**
666 * Register (RSL) gser#_br_tx#_cur
667 *
668 * GSER Base-R TX Coefficient Update Register
669 */
670 union bdk_gserx_br_txx_cur
671 {
672 uint64_t u;
673 struct bdk_gserx_br_txx_cur_s
674 {
675 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
676 uint64_t reserved_14_63 : 50;
677 uint64_t txt_cur : 14; /**< [ 13: 0](R/W) When TX BASE-R link training is being performed under software control,
678 (GSER()_BR_TX()_CTL[TXT_SWM] is set), this is the coefficient update to be written to the
679 PHY.
680 For diagnostic use only.
681 \<13:9\> = TX_POST\<4:0\>.
682 \<8:4\> = TX_SWING\<4:0\>.
683 \<3:0\> = TX_PRE\<3:0\>. */
684 #else /* Word 0 - Little Endian */
685 uint64_t txt_cur : 14; /**< [ 13: 0](R/W) When TX BASE-R link training is being performed under software control,
686 (GSER()_BR_TX()_CTL[TXT_SWM] is set), this is the coefficient update to be written to the
687 PHY.
688 For diagnostic use only.
689 \<13:9\> = TX_POST\<4:0\>.
690 \<8:4\> = TX_SWING\<4:0\>.
691 \<3:0\> = TX_PRE\<3:0\>. */
692 uint64_t reserved_14_63 : 50;
693 #endif /* Word 0 - End */
694 } s;
695 /* struct bdk_gserx_br_txx_cur_s cn; */
696 };
697 typedef union bdk_gserx_br_txx_cur bdk_gserx_br_txx_cur_t;
698
699 static inline uint64_t BDK_GSERX_BR_TXX_CUR(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_BR_TXX_CUR(unsigned long a,unsigned long b)700 static inline uint64_t BDK_GSERX_BR_TXX_CUR(unsigned long a, unsigned long b)
701 {
702 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=3)))
703 return 0x87e090000438ll + 0x1000000ll * ((a) & 0x3) + 0x80ll * ((b) & 0x3);
704 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
705 return 0x87e090000438ll + 0x1000000ll * ((a) & 0x7) + 0x80ll * ((b) & 0x3);
706 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
707 return 0x87e090000438ll + 0x1000000ll * ((a) & 0xf) + 0x80ll * ((b) & 0x3);
708 __bdk_csr_fatal("GSERX_BR_TXX_CUR", 2, a, b, 0, 0);
709 }
710
711 #define typedef_BDK_GSERX_BR_TXX_CUR(a,b) bdk_gserx_br_txx_cur_t
712 #define bustype_BDK_GSERX_BR_TXX_CUR(a,b) BDK_CSR_TYPE_RSL
713 #define basename_BDK_GSERX_BR_TXX_CUR(a,b) "GSERX_BR_TXX_CUR"
714 #define device_bar_BDK_GSERX_BR_TXX_CUR(a,b) 0x0 /* PF_BAR0 */
715 #define busnum_BDK_GSERX_BR_TXX_CUR(a,b) (a)
716 #define arguments_BDK_GSERX_BR_TXX_CUR(a,b) (a),(b),-1,-1
717
718 /**
719 * Register (RSL) gser#_br_tx#_ini
720 *
721 * GSER Base-R TX Coefficient Tap Initialize Register
722 * GSER BASE-R link training TX taps equalization initialize value. When BASE-R hardware link
723 * training is enabled the transmitter
724 * equalizer taps (Pre/Swing/Post) are initialized with the values in this register. Also,
725 * during 10GBase-KR hardware link training if a
726 * coefficient update request message is received from the link partner with the initialize
727 * control bit set the local device transmitter
728 * taps (Pre/Swing/Post) will be updated with the values in this register.
729 */
730 union bdk_gserx_br_txx_ini
731 {
732 uint64_t u;
733 struct bdk_gserx_br_txx_ini_s
734 {
735 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
736 uint64_t reserved_14_63 : 50;
737 uint64_t txt_post_init : 5; /**< [ 13: 9](R/W/H) During TX BASE-R link training, the TX post-tap value that is used
738 when the initialize coefficients update is received. It is also the TX post-tap
739 value used when the BASE-R link training begins.
740 For diagnostic use only. */
741 uint64_t txt_swing_init : 5; /**< [ 8: 4](R/W/H) During TX BASE-R link training, the TX swing-tap value that is used
742 when the initialize coefficients update is received. It is also the TX swing-tap
743 value used when the BASE-R link training begins.
744 For diagnostic use only. */
745 uint64_t txt_pre_init : 4; /**< [ 3: 0](R/W/H) During TX BASE-R link training, the TX pre-tap value that is used
746 when the initialize coefficients update is received. It is also the TX pre-tap
747 value used when the BASE-R link training begins.
748 For diagnostic use only. */
749 #else /* Word 0 - Little Endian */
750 uint64_t txt_pre_init : 4; /**< [ 3: 0](R/W/H) During TX BASE-R link training, the TX pre-tap value that is used
751 when the initialize coefficients update is received. It is also the TX pre-tap
752 value used when the BASE-R link training begins.
753 For diagnostic use only. */
754 uint64_t txt_swing_init : 5; /**< [ 8: 4](R/W/H) During TX BASE-R link training, the TX swing-tap value that is used
755 when the initialize coefficients update is received. It is also the TX swing-tap
756 value used when the BASE-R link training begins.
757 For diagnostic use only. */
758 uint64_t txt_post_init : 5; /**< [ 13: 9](R/W/H) During TX BASE-R link training, the TX post-tap value that is used
759 when the initialize coefficients update is received. It is also the TX post-tap
760 value used when the BASE-R link training begins.
761 For diagnostic use only. */
762 uint64_t reserved_14_63 : 50;
763 #endif /* Word 0 - End */
764 } s;
765 /* struct bdk_gserx_br_txx_ini_s cn; */
766 };
767 typedef union bdk_gserx_br_txx_ini bdk_gserx_br_txx_ini_t;
768
769 static inline uint64_t BDK_GSERX_BR_TXX_INI(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_BR_TXX_INI(unsigned long a,unsigned long b)770 static inline uint64_t BDK_GSERX_BR_TXX_INI(unsigned long a, unsigned long b)
771 {
772 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=3)))
773 return 0x87e090000448ll + 0x1000000ll * ((a) & 0x3) + 0x80ll * ((b) & 0x3);
774 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
775 return 0x87e090000448ll + 0x1000000ll * ((a) & 0x7) + 0x80ll * ((b) & 0x3);
776 __bdk_csr_fatal("GSERX_BR_TXX_INI", 2, a, b, 0, 0);
777 }
778
779 #define typedef_BDK_GSERX_BR_TXX_INI(a,b) bdk_gserx_br_txx_ini_t
780 #define bustype_BDK_GSERX_BR_TXX_INI(a,b) BDK_CSR_TYPE_RSL
781 #define basename_BDK_GSERX_BR_TXX_INI(a,b) "GSERX_BR_TXX_INI"
782 #define device_bar_BDK_GSERX_BR_TXX_INI(a,b) 0x0 /* PF_BAR0 */
783 #define busnum_BDK_GSERX_BR_TXX_INI(a,b) (a)
784 #define arguments_BDK_GSERX_BR_TXX_INI(a,b) (a),(b),-1,-1
785
786 /**
787 * Register (RSL) gser#_br_tx#_tap
788 *
789 * GSER Base-R TX Coefficient Tap Register
790 */
791 union bdk_gserx_br_txx_tap
792 {
793 uint64_t u;
794 struct bdk_gserx_br_txx_tap_s
795 {
796 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
797 uint64_t reserved_14_63 : 50;
798 uint64_t txt_pre : 4; /**< [ 13: 10](RO/H) After TX BASE-R link training, this is the resultant POST Tap value that was
799 written to the PHY. This field has no meaning if TX BASE-R link training was
800 not performed.
801 For diagnostic use only. */
802 uint64_t txt_swing : 5; /**< [ 9: 5](RO/H) After TX BASE-R link training, this is the resultant SWING Tap value that was
803 written to the PHY. This field has no meaning if TX BASE-R link training was
804 not performed.
805 For diagnostic use only. */
806 uint64_t txt_post : 5; /**< [ 4: 0](RO/H) After TX BASE-R link training, this is the resultant POST Tap value that was
807 written to the PHY. This field has no meaning if TX BASE-R link training was
808 not performed.
809 For diagnostic use only. */
810 #else /* Word 0 - Little Endian */
811 uint64_t txt_post : 5; /**< [ 4: 0](RO/H) After TX BASE-R link training, this is the resultant POST Tap value that was
812 written to the PHY. This field has no meaning if TX BASE-R link training was
813 not performed.
814 For diagnostic use only. */
815 uint64_t txt_swing : 5; /**< [ 9: 5](RO/H) After TX BASE-R link training, this is the resultant SWING Tap value that was
816 written to the PHY. This field has no meaning if TX BASE-R link training was
817 not performed.
818 For diagnostic use only. */
819 uint64_t txt_pre : 4; /**< [ 13: 10](RO/H) After TX BASE-R link training, this is the resultant POST Tap value that was
820 written to the PHY. This field has no meaning if TX BASE-R link training was
821 not performed.
822 For diagnostic use only. */
823 uint64_t reserved_14_63 : 50;
824 #endif /* Word 0 - End */
825 } s;
826 /* struct bdk_gserx_br_txx_tap_s cn; */
827 };
828 typedef union bdk_gserx_br_txx_tap bdk_gserx_br_txx_tap_t;
829
830 static inline uint64_t BDK_GSERX_BR_TXX_TAP(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_BR_TXX_TAP(unsigned long a,unsigned long b)831 static inline uint64_t BDK_GSERX_BR_TXX_TAP(unsigned long a, unsigned long b)
832 {
833 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=3)))
834 return 0x87e090000440ll + 0x1000000ll * ((a) & 0x3) + 0x80ll * ((b) & 0x3);
835 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
836 return 0x87e090000440ll + 0x1000000ll * ((a) & 0x7) + 0x80ll * ((b) & 0x3);
837 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
838 return 0x87e090000440ll + 0x1000000ll * ((a) & 0xf) + 0x80ll * ((b) & 0x3);
839 __bdk_csr_fatal("GSERX_BR_TXX_TAP", 2, a, b, 0, 0);
840 }
841
842 #define typedef_BDK_GSERX_BR_TXX_TAP(a,b) bdk_gserx_br_txx_tap_t
843 #define bustype_BDK_GSERX_BR_TXX_TAP(a,b) BDK_CSR_TYPE_RSL
844 #define basename_BDK_GSERX_BR_TXX_TAP(a,b) "GSERX_BR_TXX_TAP"
845 #define device_bar_BDK_GSERX_BR_TXX_TAP(a,b) 0x0 /* PF_BAR0 */
846 #define busnum_BDK_GSERX_BR_TXX_TAP(a,b) (a)
847 #define arguments_BDK_GSERX_BR_TXX_TAP(a,b) (a),(b),-1,-1
848
849 /**
850 * Register (RSL) gser#_cfg
851 *
852 * GSER Configuration Register
853 */
854 union bdk_gserx_cfg
855 {
856 uint64_t u;
857 struct bdk_gserx_cfg_s
858 {
859 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
860 uint64_t reserved_6_63 : 58;
861 uint64_t sata : 1; /**< [ 5: 5](R/W) When set, indicates the GSER is configured for SATA mode. [SATA] must not be set
862 when either of [BGX,PCIE] are set. */
863 uint64_t bgx_quad : 1; /**< [ 4: 4](R/W) When set, indicates the QLM is in BGX quad aggregation mode. [BGX_QUAD] must only be
864 set when [BGX] is set and [BGX_DUAL] is clear.
865
866 When [BGX_QUAD] is set, GSER bundles all four lanes for one BGX controller.
867 [BGX_QUAD] must only be set for the XAUI/DXAUI protocols.
868
869 Internal:
870 Not used in CCPI QLMs. */
871 uint64_t bgx_dual : 1; /**< [ 3: 3](R/W) When set, indicates the QLM is in BGX dual aggregation mode. [BGX_DUAL] must only be
872 set when [BGX] is also set and [BGX_QUAD] is clear.
873
874 When [BGX_DUAL] is set, GSER bundles lanes 0 and 1 for one BGX controller and bundles
875 lanes 2 and 3 for another BGX controller. [BGX_DUAL] must only be set for the RXAUI
876 protocol.
877
878 Internal:
879 Not used in CCPI QLMs. */
880 uint64_t bgx : 1; /**< [ 2: 2](R/W) When set, indicates the GSER is configured for BGX mode. [BGX] must not be set
881 when either of [PCIE,SATA] are set.
882
883 When [BGX] is set and both [BGX_DUAL,BGX_QUAD] are clear, GSER exposes each lane to an
884 independent BGX controller.
885
886 Internal:
887 Not used in CCPI QLMs. */
888 uint64_t ila : 1; /**< [ 1: 1](R/W) Reserved. */
889 uint64_t pcie : 1; /**< [ 0: 0](R/W/H) When set, indicates the GSER is configured for PCIE mode. [PCIE] must not be
890 set when either of [BGX,SATA] is set.
891
892 Internal:
893 Not used in CCPI QLMs. */
894 #else /* Word 0 - Little Endian */
895 uint64_t pcie : 1; /**< [ 0: 0](R/W/H) When set, indicates the GSER is configured for PCIE mode. [PCIE] must not be
896 set when either of [BGX,SATA] is set.
897
898 Internal:
899 Not used in CCPI QLMs. */
900 uint64_t ila : 1; /**< [ 1: 1](R/W) Reserved. */
901 uint64_t bgx : 1; /**< [ 2: 2](R/W) When set, indicates the GSER is configured for BGX mode. [BGX] must not be set
902 when either of [PCIE,SATA] are set.
903
904 When [BGX] is set and both [BGX_DUAL,BGX_QUAD] are clear, GSER exposes each lane to an
905 independent BGX controller.
906
907 Internal:
908 Not used in CCPI QLMs. */
909 uint64_t bgx_dual : 1; /**< [ 3: 3](R/W) When set, indicates the QLM is in BGX dual aggregation mode. [BGX_DUAL] must only be
910 set when [BGX] is also set and [BGX_QUAD] is clear.
911
912 When [BGX_DUAL] is set, GSER bundles lanes 0 and 1 for one BGX controller and bundles
913 lanes 2 and 3 for another BGX controller. [BGX_DUAL] must only be set for the RXAUI
914 protocol.
915
916 Internal:
917 Not used in CCPI QLMs. */
918 uint64_t bgx_quad : 1; /**< [ 4: 4](R/W) When set, indicates the QLM is in BGX quad aggregation mode. [BGX_QUAD] must only be
919 set when [BGX] is set and [BGX_DUAL] is clear.
920
921 When [BGX_QUAD] is set, GSER bundles all four lanes for one BGX controller.
922 [BGX_QUAD] must only be set for the XAUI/DXAUI protocols.
923
924 Internal:
925 Not used in CCPI QLMs. */
926 uint64_t sata : 1; /**< [ 5: 5](R/W) When set, indicates the GSER is configured for SATA mode. [SATA] must not be set
927 when either of [BGX,PCIE] are set. */
928 uint64_t reserved_6_63 : 58;
929 #endif /* Word 0 - End */
930 } s;
931 struct bdk_gserx_cfg_cn81xx
932 {
933 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
934 uint64_t reserved_6_63 : 58;
935 uint64_t sata : 1; /**< [ 5: 5](R/W) When set, indicates the GSER is configured for SATA mode. [SATA] must not be set
936 when either of [BGX,PCIE] are set. [SATA] must only be set for DLM3 (i.e. GSER3). */
937 uint64_t bgx_quad : 1; /**< [ 4: 4](R/W) When set, indicates the QLM is in BGX quad aggregation mode. [BGX_QUAD] must only be
938 set when [BGX] is set and [BGX_DUAL] is clear.
939
940 When [BGX_QUAD] is set, GSER bundles all four lanes for one BGX controller.
941 [BGX_QUAD] must only be set for the XAUI/DXAUI protocols.
942
943 Internal:
944 Not used in CCPI QLMs. */
945 uint64_t bgx_dual : 1; /**< [ 3: 3](R/W) When set, indicates the QLM is in BGX dual aggregation mode. [BGX_DUAL] must only be
946 set when [BGX] is also set and [BGX_QUAD] is clear.
947
948 When [BGX_DUAL] is set, GSER bundles lanes 0 and 1 for one BGX controller and bundles
949 lanes 2 and 3 for another BGX controller. [BGX_DUAL] must only be set for the RXAUI
950 protocol.
951
952 Internal:
953 Not used in CCPI QLMs. */
954 uint64_t bgx : 1; /**< [ 2: 2](R/W) When set, indicates the GSER is configured for BGX mode. [BGX] must not be set
955 when either of [PCIE,SATA] are set.
956
957 When [BGX] is set and both [BGX_DUAL,BGX_QUAD] are clear, GSER exposes each lane to an
958 independent BGX controller.
959
960 Internal:
961 Not used in CCPI QLMs. */
962 uint64_t ila : 1; /**< [ 1: 1](R/W) Reserved. */
963 uint64_t pcie : 1; /**< [ 0: 0](R/W/H) When set, indicates the GSER is configured for PCIE mode. [PCIE] must not be
964 set when either of [BGX,SATA] is set.
965
966 Internal:
967 Not used in CCPI QLMs. */
968 #else /* Word 0 - Little Endian */
969 uint64_t pcie : 1; /**< [ 0: 0](R/W/H) When set, indicates the GSER is configured for PCIE mode. [PCIE] must not be
970 set when either of [BGX,SATA] is set.
971
972 Internal:
973 Not used in CCPI QLMs. */
974 uint64_t ila : 1; /**< [ 1: 1](R/W) Reserved. */
975 uint64_t bgx : 1; /**< [ 2: 2](R/W) When set, indicates the GSER is configured for BGX mode. [BGX] must not be set
976 when either of [PCIE,SATA] are set.
977
978 When [BGX] is set and both [BGX_DUAL,BGX_QUAD] are clear, GSER exposes each lane to an
979 independent BGX controller.
980
981 Internal:
982 Not used in CCPI QLMs. */
983 uint64_t bgx_dual : 1; /**< [ 3: 3](R/W) When set, indicates the QLM is in BGX dual aggregation mode. [BGX_DUAL] must only be
984 set when [BGX] is also set and [BGX_QUAD] is clear.
985
986 When [BGX_DUAL] is set, GSER bundles lanes 0 and 1 for one BGX controller and bundles
987 lanes 2 and 3 for another BGX controller. [BGX_DUAL] must only be set for the RXAUI
988 protocol.
989
990 Internal:
991 Not used in CCPI QLMs. */
992 uint64_t bgx_quad : 1; /**< [ 4: 4](R/W) When set, indicates the QLM is in BGX quad aggregation mode. [BGX_QUAD] must only be
993 set when [BGX] is set and [BGX_DUAL] is clear.
994
995 When [BGX_QUAD] is set, GSER bundles all four lanes for one BGX controller.
996 [BGX_QUAD] must only be set for the XAUI/DXAUI protocols.
997
998 Internal:
999 Not used in CCPI QLMs. */
1000 uint64_t sata : 1; /**< [ 5: 5](R/W) When set, indicates the GSER is configured for SATA mode. [SATA] must not be set
1001 when either of [BGX,PCIE] are set. [SATA] must only be set for DLM3 (i.e. GSER3). */
1002 uint64_t reserved_6_63 : 58;
1003 #endif /* Word 0 - End */
1004 } cn81xx;
1005 struct bdk_gserx_cfg_cn88xx
1006 {
1007 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1008 uint64_t reserved_6_63 : 58;
1009 uint64_t sata : 1; /**< [ 5: 5](R/W) When set, indicates the GSER is configured for SATA mode. [SATA] must not be set
1010 when either of [BGX,PCIE] are set. */
1011 uint64_t bgx_quad : 1; /**< [ 4: 4](R/W) When set, indicates the QLM is in BGX quad aggregation mode. [BGX_QUAD] must only be
1012 set when [BGX] is set and [BGX_DUAL] is clear.
1013
1014 When [BGX_QUAD] is set, GSER bundles all four lanes for one BGX controller.
1015 [BGX_QUAD] must only be set for the XAUI/DXAUI and XLAUI protocols.
1016
1017 Internal:
1018 Not used in CCPI QLMs. */
1019 uint64_t bgx_dual : 1; /**< [ 3: 3](R/W) When set, indicates the QLM is in BGX dual aggregation mode. [BGX_DUAL] must only be
1020 set when [BGX] is also set and [BGX_QUAD] is clear.
1021
1022 When [BGX_DUAL] is set, GSER bundles lanes 0 and 1 for one BGX controller and bundles
1023 lanes 2 and 3 for another BGX controller. [BGX_DUAL] must only be set for the RXAUI
1024 protocol.
1025
1026 Internal:
1027 Not used in CCPI QLMs. */
1028 uint64_t bgx : 1; /**< [ 2: 2](R/W) When set, indicates the GSER is configured for BGX mode. [BGX] must not be set
1029 when either of [PCIE,SATA] are set. For CCPI links, [BGX] must be clear.
1030
1031 When [BGX] is set and both [BGX_DUAL,BGX_QUAD] are clear, GSER exposes each lane to an
1032 independent BGX controller.
1033
1034 Internal:
1035 Not used in CCPI QLMs. */
1036 uint64_t ila : 1; /**< [ 1: 1](R/W) Reserved. */
1037 uint64_t pcie : 1; /**< [ 0: 0](R/W/H) When set, indicates the GSER is configured for PCIE mode. [PCIE] must not be
1038 set when either of [BGX,SATA] is set. For CCPI QLMs, [PCIE] must be clear.
1039
1040 Internal:
1041 Not used in CCPI QLMs. */
1042 #else /* Word 0 - Little Endian */
1043 uint64_t pcie : 1; /**< [ 0: 0](R/W/H) When set, indicates the GSER is configured for PCIE mode. [PCIE] must not be
1044 set when either of [BGX,SATA] is set. For CCPI QLMs, [PCIE] must be clear.
1045
1046 Internal:
1047 Not used in CCPI QLMs. */
1048 uint64_t ila : 1; /**< [ 1: 1](R/W) Reserved. */
1049 uint64_t bgx : 1; /**< [ 2: 2](R/W) When set, indicates the GSER is configured for BGX mode. [BGX] must not be set
1050 when either of [PCIE,SATA] are set. For CCPI links, [BGX] must be clear.
1051
1052 When [BGX] is set and both [BGX_DUAL,BGX_QUAD] are clear, GSER exposes each lane to an
1053 independent BGX controller.
1054
1055 Internal:
1056 Not used in CCPI QLMs. */
1057 uint64_t bgx_dual : 1; /**< [ 3: 3](R/W) When set, indicates the QLM is in BGX dual aggregation mode. [BGX_DUAL] must only be
1058 set when [BGX] is also set and [BGX_QUAD] is clear.
1059
1060 When [BGX_DUAL] is set, GSER bundles lanes 0 and 1 for one BGX controller and bundles
1061 lanes 2 and 3 for another BGX controller. [BGX_DUAL] must only be set for the RXAUI
1062 protocol.
1063
1064 Internal:
1065 Not used in CCPI QLMs. */
1066 uint64_t bgx_quad : 1; /**< [ 4: 4](R/W) When set, indicates the QLM is in BGX quad aggregation mode. [BGX_QUAD] must only be
1067 set when [BGX] is set and [BGX_DUAL] is clear.
1068
1069 When [BGX_QUAD] is set, GSER bundles all four lanes for one BGX controller.
1070 [BGX_QUAD] must only be set for the XAUI/DXAUI and XLAUI protocols.
1071
1072 Internal:
1073 Not used in CCPI QLMs. */
1074 uint64_t sata : 1; /**< [ 5: 5](R/W) When set, indicates the GSER is configured for SATA mode. [SATA] must not be set
1075 when either of [BGX,PCIE] are set. */
1076 uint64_t reserved_6_63 : 58;
1077 #endif /* Word 0 - End */
1078 } cn88xx;
1079 struct bdk_gserx_cfg_cn83xx
1080 {
1081 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1082 uint64_t reserved_6_63 : 58;
1083 uint64_t sata : 1; /**< [ 5: 5](R/W) When set, indicates the GSER is configured for SATA mode. [SATA] must not be set
1084 when either of [BGX,PCIE] are set. */
1085 uint64_t bgx_quad : 1; /**< [ 4: 4](R/W) When set, indicates the QLM is in BGX quad aggregation mode. [BGX_QUAD] must only be
1086 set when [BGX] is set and [BGX_DUAL] is clear.
1087
1088 When [BGX_QUAD] is set, GSER bundles all four lanes for one BGX controller.
1089 [BGX_QUAD] must only be set for the XAUI/DXAUI and XLAUI protocols.
1090
1091 Internal:
1092 There is hardware to pair DLM 5 and 6 together when [BGX_QUAD] is set in DLM5.
1093 But we currently do not support XAUI/DXAUI/XLAUI on DLM's. */
1094 uint64_t bgx_dual : 1; /**< [ 3: 3](R/W) When set, indicates the QLM is in BGX dual aggregation mode. [BGX_DUAL] must only be
1095 set when [BGX] is also set and [BGX_QUAD] is clear.
1096
1097 When [BGX_DUAL] is set, GSER bundles lanes 0 and 1 for one BGX controller and bundles
1098 lanes 2 and 3 for another BGX controller. [BGX_DUAL] must only be set for the RXAUI
1099 protocol.
1100
1101 [BGX_DUAL] must not be set in a DLM.
1102
1103 Internal:
1104 [BGX_DUAL] should work in a DLM (lanes 0 and 1 bundled for one BGX controller), but
1105 we currently do not support RXAUI in a DLM. */
1106 uint64_t bgx : 1; /**< [ 2: 2](R/W) When set, indicates the GSER is configured for BGX mode. [BGX] must not be set
1107 when either of [PCIE,SATA] are set.
1108
1109 When [BGX] is set and both [BGX_DUAL,BGX_QUAD] are clear, GSER exposes each lane to an
1110 independent BGX controller. */
1111 uint64_t ila : 1; /**< [ 1: 1](R/W) Reserved. */
1112 uint64_t pcie : 1; /**< [ 0: 0](R/W/H) When set, indicates the GSER is configured for PCIE mode. [PCIE] must not be
1113 set when either of [BGX,SATA] is set. */
1114 #else /* Word 0 - Little Endian */
1115 uint64_t pcie : 1; /**< [ 0: 0](R/W/H) When set, indicates the GSER is configured for PCIE mode. [PCIE] must not be
1116 set when either of [BGX,SATA] is set. */
1117 uint64_t ila : 1; /**< [ 1: 1](R/W) Reserved. */
1118 uint64_t bgx : 1; /**< [ 2: 2](R/W) When set, indicates the GSER is configured for BGX mode. [BGX] must not be set
1119 when either of [PCIE,SATA] are set.
1120
1121 When [BGX] is set and both [BGX_DUAL,BGX_QUAD] are clear, GSER exposes each lane to an
1122 independent BGX controller. */
1123 uint64_t bgx_dual : 1; /**< [ 3: 3](R/W) When set, indicates the QLM is in BGX dual aggregation mode. [BGX_DUAL] must only be
1124 set when [BGX] is also set and [BGX_QUAD] is clear.
1125
1126 When [BGX_DUAL] is set, GSER bundles lanes 0 and 1 for one BGX controller and bundles
1127 lanes 2 and 3 for another BGX controller. [BGX_DUAL] must only be set for the RXAUI
1128 protocol.
1129
1130 [BGX_DUAL] must not be set in a DLM.
1131
1132 Internal:
1133 [BGX_DUAL] should work in a DLM (lanes 0 and 1 bundled for one BGX controller), but
1134 we currently do not support RXAUI in a DLM. */
1135 uint64_t bgx_quad : 1; /**< [ 4: 4](R/W) When set, indicates the QLM is in BGX quad aggregation mode. [BGX_QUAD] must only be
1136 set when [BGX] is set and [BGX_DUAL] is clear.
1137
1138 When [BGX_QUAD] is set, GSER bundles all four lanes for one BGX controller.
1139 [BGX_QUAD] must only be set for the XAUI/DXAUI and XLAUI protocols.
1140
1141 Internal:
1142 There is hardware to pair DLM 5 and 6 together when [BGX_QUAD] is set in DLM5.
1143 But we currently do not support XAUI/DXAUI/XLAUI on DLM's. */
1144 uint64_t sata : 1; /**< [ 5: 5](R/W) When set, indicates the GSER is configured for SATA mode. [SATA] must not be set
1145 when either of [BGX,PCIE] are set. */
1146 uint64_t reserved_6_63 : 58;
1147 #endif /* Word 0 - End */
1148 } cn83xx;
1149 };
1150 typedef union bdk_gserx_cfg bdk_gserx_cfg_t;
1151
1152 static inline uint64_t BDK_GSERX_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_CFG(unsigned long a)1153 static inline uint64_t BDK_GSERX_CFG(unsigned long a)
1154 {
1155 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1156 return 0x87e090000080ll + 0x1000000ll * ((a) & 0x3);
1157 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1158 return 0x87e090000080ll + 0x1000000ll * ((a) & 0x7);
1159 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1160 return 0x87e090000080ll + 0x1000000ll * ((a) & 0xf);
1161 __bdk_csr_fatal("GSERX_CFG", 1, a, 0, 0, 0);
1162 }
1163
1164 #define typedef_BDK_GSERX_CFG(a) bdk_gserx_cfg_t
1165 #define bustype_BDK_GSERX_CFG(a) BDK_CSR_TYPE_RSL
1166 #define basename_BDK_GSERX_CFG(a) "GSERX_CFG"
1167 #define device_bar_BDK_GSERX_CFG(a) 0x0 /* PF_BAR0 */
1168 #define busnum_BDK_GSERX_CFG(a) (a)
1169 #define arguments_BDK_GSERX_CFG(a) (a),-1,-1,-1
1170
1171 /**
1172 * Register (RSL) gser#_dbg
1173 *
1174 * GSER Debug Control Register
1175 */
1176 union bdk_gserx_dbg
1177 {
1178 uint64_t u;
1179 struct bdk_gserx_dbg_s
1180 {
1181 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1182 uint64_t reserved_1_63 : 63;
1183 uint64_t rxqtm_on : 1; /**< [ 0: 0](R/W) For non-BGX configurations, setting this bit enables the RX FIFOs. This allows
1184 received data to become visible to the RSL debug port. For diagnostic use only. */
1185 #else /* Word 0 - Little Endian */
1186 uint64_t rxqtm_on : 1; /**< [ 0: 0](R/W) For non-BGX configurations, setting this bit enables the RX FIFOs. This allows
1187 received data to become visible to the RSL debug port. For diagnostic use only. */
1188 uint64_t reserved_1_63 : 63;
1189 #endif /* Word 0 - End */
1190 } s;
1191 /* struct bdk_gserx_dbg_s cn; */
1192 };
1193 typedef union bdk_gserx_dbg bdk_gserx_dbg_t;
1194
1195 static inline uint64_t BDK_GSERX_DBG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_DBG(unsigned long a)1196 static inline uint64_t BDK_GSERX_DBG(unsigned long a)
1197 {
1198 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1199 return 0x87e090000098ll + 0x1000000ll * ((a) & 0x3);
1200 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1201 return 0x87e090000098ll + 0x1000000ll * ((a) & 0x7);
1202 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1203 return 0x87e090000098ll + 0x1000000ll * ((a) & 0xf);
1204 __bdk_csr_fatal("GSERX_DBG", 1, a, 0, 0, 0);
1205 }
1206
1207 #define typedef_BDK_GSERX_DBG(a) bdk_gserx_dbg_t
1208 #define bustype_BDK_GSERX_DBG(a) BDK_CSR_TYPE_RSL
1209 #define basename_BDK_GSERX_DBG(a) "GSERX_DBG"
1210 #define device_bar_BDK_GSERX_DBG(a) 0x0 /* PF_BAR0 */
1211 #define busnum_BDK_GSERX_DBG(a) (a)
1212 #define arguments_BDK_GSERX_DBG(a) (a),-1,-1,-1
1213
1214 /**
1215 * Register (RSL) gser#_eq_wait_time
1216 *
1217 * GSER TX and RX Equalization Wait Times Register
1218 * These registers are for diagnostic use only.
1219 * These registers are reset by hardware only during chip cold reset.
1220 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1221 */
1222 union bdk_gserx_eq_wait_time
1223 {
1224 uint64_t u;
1225 struct bdk_gserx_eq_wait_time_s
1226 {
1227 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1228 uint64_t reserved_8_63 : 56;
1229 uint64_t rxeq_wait_cnt : 4; /**< [ 7: 4](R/W) Determines the wait time after VMA RX-EQ completes and before sampling
1230 tap1 and starting the precorrelation check. */
1231 uint64_t txeq_wait_cnt : 4; /**< [ 3: 0](R/W) Determines the wait time from applying the TX-EQ controls (swing/pre/post)
1232 to the sampling of the sds_pcs_tx_comp_out. */
1233 #else /* Word 0 - Little Endian */
1234 uint64_t txeq_wait_cnt : 4; /**< [ 3: 0](R/W) Determines the wait time from applying the TX-EQ controls (swing/pre/post)
1235 to the sampling of the sds_pcs_tx_comp_out. */
1236 uint64_t rxeq_wait_cnt : 4; /**< [ 7: 4](R/W) Determines the wait time after VMA RX-EQ completes and before sampling
1237 tap1 and starting the precorrelation check. */
1238 uint64_t reserved_8_63 : 56;
1239 #endif /* Word 0 - End */
1240 } s;
1241 /* struct bdk_gserx_eq_wait_time_s cn; */
1242 };
1243 typedef union bdk_gserx_eq_wait_time bdk_gserx_eq_wait_time_t;
1244
1245 static inline uint64_t BDK_GSERX_EQ_WAIT_TIME(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_EQ_WAIT_TIME(unsigned long a)1246 static inline uint64_t BDK_GSERX_EQ_WAIT_TIME(unsigned long a)
1247 {
1248 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1249 return 0x87e0904e0000ll + 0x1000000ll * ((a) & 0x3);
1250 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1251 return 0x87e0904e0000ll + 0x1000000ll * ((a) & 0x7);
1252 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1253 return 0x87e0904e0000ll + 0x1000000ll * ((a) & 0xf);
1254 __bdk_csr_fatal("GSERX_EQ_WAIT_TIME", 1, a, 0, 0, 0);
1255 }
1256
1257 #define typedef_BDK_GSERX_EQ_WAIT_TIME(a) bdk_gserx_eq_wait_time_t
1258 #define bustype_BDK_GSERX_EQ_WAIT_TIME(a) BDK_CSR_TYPE_RSL
1259 #define basename_BDK_GSERX_EQ_WAIT_TIME(a) "GSERX_EQ_WAIT_TIME"
1260 #define device_bar_BDK_GSERX_EQ_WAIT_TIME(a) 0x0 /* PF_BAR0 */
1261 #define busnum_BDK_GSERX_EQ_WAIT_TIME(a) (a)
1262 #define arguments_BDK_GSERX_EQ_WAIT_TIME(a) (a),-1,-1,-1
1263
1264 /**
1265 * Register (RSL) gser#_glbl_misc_config_1
1266 *
1267 * GSER Global Miscellaneous Configuration 1 Register
1268 * These registers are for diagnostic use only.
1269 * These registers are reset by hardware only during chip cold reset.
1270 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1271 */
1272 union bdk_gserx_glbl_misc_config_1
1273 {
1274 uint64_t u;
1275 struct bdk_gserx_glbl_misc_config_1_s
1276 {
1277 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1278 uint64_t reserved_10_63 : 54;
1279 uint64_t pcs_sds_vref_tr : 4; /**< [ 9: 6](R/W) Trim the BGR (band gap reference) reference (all external and internal currents
1280 are affected).
1281 For diagnostic use only. */
1282 uint64_t pcs_sds_trim_chp_reg : 2; /**< [ 5: 4](R/W) Trim current going to CML-CMOS stage at output of VCO.
1283 For diagnostic use only. */
1284 uint64_t pcs_sds_vco_reg_tr : 2; /**< [ 3: 2](R/W) Trims regulator voltage.
1285 For diagnostic use only. */
1286 uint64_t pcs_sds_cvbg_en : 1; /**< [ 1: 1](R/W) Forces 0.6 V from VDDHV onto VBG node.
1287 For diagnostic use only. */
1288 uint64_t pcs_sds_extvbg_en : 1; /**< [ 0: 0](R/W) Force external VBG through AMON pin in TMA5 mode.
1289 For diagnostic use only. */
1290 #else /* Word 0 - Little Endian */
1291 uint64_t pcs_sds_extvbg_en : 1; /**< [ 0: 0](R/W) Force external VBG through AMON pin in TMA5 mode.
1292 For diagnostic use only. */
1293 uint64_t pcs_sds_cvbg_en : 1; /**< [ 1: 1](R/W) Forces 0.6 V from VDDHV onto VBG node.
1294 For diagnostic use only. */
1295 uint64_t pcs_sds_vco_reg_tr : 2; /**< [ 3: 2](R/W) Trims regulator voltage.
1296 For diagnostic use only. */
1297 uint64_t pcs_sds_trim_chp_reg : 2; /**< [ 5: 4](R/W) Trim current going to CML-CMOS stage at output of VCO.
1298 For diagnostic use only. */
1299 uint64_t pcs_sds_vref_tr : 4; /**< [ 9: 6](R/W) Trim the BGR (band gap reference) reference (all external and internal currents
1300 are affected).
1301 For diagnostic use only. */
1302 uint64_t reserved_10_63 : 54;
1303 #endif /* Word 0 - End */
1304 } s;
1305 /* struct bdk_gserx_glbl_misc_config_1_s cn; */
1306 };
1307 typedef union bdk_gserx_glbl_misc_config_1 bdk_gserx_glbl_misc_config_1_t;
1308
1309 static inline uint64_t BDK_GSERX_GLBL_MISC_CONFIG_1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_GLBL_MISC_CONFIG_1(unsigned long a)1310 static inline uint64_t BDK_GSERX_GLBL_MISC_CONFIG_1(unsigned long a)
1311 {
1312 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1313 return 0x87e090460030ll + 0x1000000ll * ((a) & 0x3);
1314 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1315 return 0x87e090460030ll + 0x1000000ll * ((a) & 0x7);
1316 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1317 return 0x87e090460030ll + 0x1000000ll * ((a) & 0xf);
1318 __bdk_csr_fatal("GSERX_GLBL_MISC_CONFIG_1", 1, a, 0, 0, 0);
1319 }
1320
1321 #define typedef_BDK_GSERX_GLBL_MISC_CONFIG_1(a) bdk_gserx_glbl_misc_config_1_t
1322 #define bustype_BDK_GSERX_GLBL_MISC_CONFIG_1(a) BDK_CSR_TYPE_RSL
1323 #define basename_BDK_GSERX_GLBL_MISC_CONFIG_1(a) "GSERX_GLBL_MISC_CONFIG_1"
1324 #define device_bar_BDK_GSERX_GLBL_MISC_CONFIG_1(a) 0x0 /* PF_BAR0 */
1325 #define busnum_BDK_GSERX_GLBL_MISC_CONFIG_1(a) (a)
1326 #define arguments_BDK_GSERX_GLBL_MISC_CONFIG_1(a) (a),-1,-1,-1
1327
1328 /**
1329 * Register (RSL) gser#_glbl_pll_cfg_0
1330 *
1331 * GSER Global PLL Configuration 0 Register
1332 * These registers are for diagnostic use only.
1333 * These registers are reset by hardware only during chip cold reset.
1334 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1335 */
1336 union bdk_gserx_glbl_pll_cfg_0
1337 {
1338 uint64_t u;
1339 struct bdk_gserx_glbl_pll_cfg_0_s
1340 {
1341 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1342 uint64_t reserved_14_63 : 50;
1343 uint64_t pcs_sds_pll_vco_reset_b : 1;/**< [ 13: 13](R/W) VCO reset, active low.
1344 For diagnostic use only. */
1345 uint64_t pcs_sds_pll_strt_cal_b : 1; /**< [ 12: 12](R/W) Start PLL calibration, active low.
1346 For diagnostic use only. */
1347 uint64_t pcs_sds_pll_cripple : 1; /**< [ 11: 11](R/W) Ripple capacitor tuning.
1348 For diagnostic use only. */
1349 uint64_t reserved_8_10 : 3;
1350 uint64_t pcs_sds_pll_fthresh : 2; /**< [ 7: 6](R/W/H) PLL frequency comparison threshold.
1351 For diagnostic use only. */
1352 uint64_t reserved_0_5 : 6;
1353 #else /* Word 0 - Little Endian */
1354 uint64_t reserved_0_5 : 6;
1355 uint64_t pcs_sds_pll_fthresh : 2; /**< [ 7: 6](R/W/H) PLL frequency comparison threshold.
1356 For diagnostic use only. */
1357 uint64_t reserved_8_10 : 3;
1358 uint64_t pcs_sds_pll_cripple : 1; /**< [ 11: 11](R/W) Ripple capacitor tuning.
1359 For diagnostic use only. */
1360 uint64_t pcs_sds_pll_strt_cal_b : 1; /**< [ 12: 12](R/W) Start PLL calibration, active low.
1361 For diagnostic use only. */
1362 uint64_t pcs_sds_pll_vco_reset_b : 1;/**< [ 13: 13](R/W) VCO reset, active low.
1363 For diagnostic use only. */
1364 uint64_t reserved_14_63 : 50;
1365 #endif /* Word 0 - End */
1366 } s;
1367 /* struct bdk_gserx_glbl_pll_cfg_0_s cn; */
1368 };
1369 typedef union bdk_gserx_glbl_pll_cfg_0 bdk_gserx_glbl_pll_cfg_0_t;
1370
1371 static inline uint64_t BDK_GSERX_GLBL_PLL_CFG_0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_GLBL_PLL_CFG_0(unsigned long a)1372 static inline uint64_t BDK_GSERX_GLBL_PLL_CFG_0(unsigned long a)
1373 {
1374 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1375 return 0x87e090460000ll + 0x1000000ll * ((a) & 0x3);
1376 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1377 return 0x87e090460000ll + 0x1000000ll * ((a) & 0x7);
1378 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1379 return 0x87e090460000ll + 0x1000000ll * ((a) & 0xf);
1380 __bdk_csr_fatal("GSERX_GLBL_PLL_CFG_0", 1, a, 0, 0, 0);
1381 }
1382
1383 #define typedef_BDK_GSERX_GLBL_PLL_CFG_0(a) bdk_gserx_glbl_pll_cfg_0_t
1384 #define bustype_BDK_GSERX_GLBL_PLL_CFG_0(a) BDK_CSR_TYPE_RSL
1385 #define basename_BDK_GSERX_GLBL_PLL_CFG_0(a) "GSERX_GLBL_PLL_CFG_0"
1386 #define device_bar_BDK_GSERX_GLBL_PLL_CFG_0(a) 0x0 /* PF_BAR0 */
1387 #define busnum_BDK_GSERX_GLBL_PLL_CFG_0(a) (a)
1388 #define arguments_BDK_GSERX_GLBL_PLL_CFG_0(a) (a),-1,-1,-1
1389
1390 /**
1391 * Register (RSL) gser#_glbl_pll_cfg_1
1392 *
1393 * GSER Global PLL Configuration 1 Register
1394 * These registers are for diagnostic use only.
1395 * These registers are reset by hardware only during chip cold reset.
1396 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1397 */
1398 union bdk_gserx_glbl_pll_cfg_1
1399 {
1400 uint64_t u;
1401 struct bdk_gserx_glbl_pll_cfg_1_s
1402 {
1403 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1404 uint64_t reserved_10_63 : 54;
1405 uint64_t cfg_pll_ctrl_en : 1; /**< [ 9: 9](R/W) PLL reset control enable.
1406 0 = PLL RESETs/cal start are not active.
1407 1 = All PLL RESETs/cal start are enabled.
1408
1409 For diagnostic use only. */
1410 uint64_t pcs_sds_pll_calmode : 3; /**< [ 8: 6](R/W) PLL calibration mode.
1411 0 = Force PLL loop into calibration mode.
1412 1 = Normal operation.
1413
1414 For diagnostic use only. */
1415 uint64_t pcs_sds_pll_cal_ovrd_en : 1;/**< [ 5: 5](R/W) Manual PLL coarse calibration override enable.
1416 For diagnostic use only. */
1417 uint64_t pcs_sds_pll_cal_ovrd : 5; /**< [ 4: 0](R/W) Manual PLL coarse calibration override value.
1418 For diagnostic use only. */
1419 #else /* Word 0 - Little Endian */
1420 uint64_t pcs_sds_pll_cal_ovrd : 5; /**< [ 4: 0](R/W) Manual PLL coarse calibration override value.
1421 For diagnostic use only. */
1422 uint64_t pcs_sds_pll_cal_ovrd_en : 1;/**< [ 5: 5](R/W) Manual PLL coarse calibration override enable.
1423 For diagnostic use only. */
1424 uint64_t pcs_sds_pll_calmode : 3; /**< [ 8: 6](R/W) PLL calibration mode.
1425 0 = Force PLL loop into calibration mode.
1426 1 = Normal operation.
1427
1428 For diagnostic use only. */
1429 uint64_t cfg_pll_ctrl_en : 1; /**< [ 9: 9](R/W) PLL reset control enable.
1430 0 = PLL RESETs/cal start are not active.
1431 1 = All PLL RESETs/cal start are enabled.
1432
1433 For diagnostic use only. */
1434 uint64_t reserved_10_63 : 54;
1435 #endif /* Word 0 - End */
1436 } s;
1437 /* struct bdk_gserx_glbl_pll_cfg_1_s cn; */
1438 };
1439 typedef union bdk_gserx_glbl_pll_cfg_1 bdk_gserx_glbl_pll_cfg_1_t;
1440
1441 static inline uint64_t BDK_GSERX_GLBL_PLL_CFG_1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_GLBL_PLL_CFG_1(unsigned long a)1442 static inline uint64_t BDK_GSERX_GLBL_PLL_CFG_1(unsigned long a)
1443 {
1444 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1445 return 0x87e090460008ll + 0x1000000ll * ((a) & 0x3);
1446 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1447 return 0x87e090460008ll + 0x1000000ll * ((a) & 0x7);
1448 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1449 return 0x87e090460008ll + 0x1000000ll * ((a) & 0xf);
1450 __bdk_csr_fatal("GSERX_GLBL_PLL_CFG_1", 1, a, 0, 0, 0);
1451 }
1452
1453 #define typedef_BDK_GSERX_GLBL_PLL_CFG_1(a) bdk_gserx_glbl_pll_cfg_1_t
1454 #define bustype_BDK_GSERX_GLBL_PLL_CFG_1(a) BDK_CSR_TYPE_RSL
1455 #define basename_BDK_GSERX_GLBL_PLL_CFG_1(a) "GSERX_GLBL_PLL_CFG_1"
1456 #define device_bar_BDK_GSERX_GLBL_PLL_CFG_1(a) 0x0 /* PF_BAR0 */
1457 #define busnum_BDK_GSERX_GLBL_PLL_CFG_1(a) (a)
1458 #define arguments_BDK_GSERX_GLBL_PLL_CFG_1(a) (a),-1,-1,-1
1459
1460 /**
1461 * Register (RSL) gser#_glbl_pll_cfg_2
1462 *
1463 * GSER Global PLL Configuration 2 Register
1464 * These registers are for diagnostic use only.
1465 * These registers are reset by hardware only during chip cold reset.
1466 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1467 */
1468 union bdk_gserx_glbl_pll_cfg_2
1469 {
1470 uint64_t u;
1471 struct bdk_gserx_glbl_pll_cfg_2_s
1472 {
1473 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1474 uint64_t reserved_15_63 : 49;
1475 uint64_t pll_div_ovrrd_en : 1; /**< [ 14: 14](R/W) Override global power state machine and mac_pcs_pll_div control signal.
1476 When asserted, pcs_sds_pll_div is specified from
1477 GSER()_LANE()_PCS_PLL_CTLIFC_0[PLL_DIV_OVRRD_VAL],
1478 global power state machine and mac_pcs_pll_div control signals are ignored.
1479 For diagnostic use only. */
1480 uint64_t reserved_10_13 : 4;
1481 uint64_t pcs_sds_pll_lock_override : 1;/**< [ 9: 9](R/W) Not used.
1482 For diagnostic use only. */
1483 uint64_t pcs_sds_pll_counter_resetn : 1;/**< [ 8: 8](R/W) Not used.
1484 For diagnostic use only. */
1485 uint64_t pll_sdsck_pd_ovrrd_val : 1; /**< [ 7: 7](R/W) Clock tree powerdown override value.
1486 For diagnostic use only. */
1487 uint64_t pll_sdsck_pd_ovrrd_en : 1; /**< [ 6: 6](R/W) Clock tree powerdown override enable.
1488 For diagnostic use only. */
1489 uint64_t pll_pd_ovrrd_val : 1; /**< [ 5: 5](R/W) PLL powerdown override value.
1490 For diagnostic use only. */
1491 uint64_t pll_pd_ovrrd_en : 1; /**< [ 4: 4](R/W) When asserted, overrides PLL powerdown from state machine.
1492 For diagnostic use only. */
1493 uint64_t pcs_sds_pll_div5_byp : 1; /**< [ 3: 3](R/W) Not used.
1494 For diagnostic use only. */
1495 uint64_t pll_band_sel_ovrrd_val : 1; /**< [ 2: 2](R/W) State machine override value for VCO band select.
1496 0 = Low band VCO0 (RO-VCO).
1497 1 = High band VCO1 (LC-VCO).
1498
1499 For diagnostic use only. */
1500 uint64_t pll_band_sel_ovrrd_en : 1; /**< [ 1: 1](R/W) PLL band select override enable.
1501 For diagnostic use only. */
1502 uint64_t pll_pcs_div_ovrrd_en : 1; /**< [ 0: 0](R/W) Override global power state machine and mac_pcs_pll_div control signal.
1503 When asserted, pcs_sds_pll_div is specified from
1504 GSER()_LANE()_PCS_PLL_CTLIFC_1[PLL_PCS_DIV_OVRRD_VAL],
1505 global power state machine and mac_pcs_pll_div control signals are ignored.
1506 For diagnostic use only. */
1507 #else /* Word 0 - Little Endian */
1508 uint64_t pll_pcs_div_ovrrd_en : 1; /**< [ 0: 0](R/W) Override global power state machine and mac_pcs_pll_div control signal.
1509 When asserted, pcs_sds_pll_div is specified from
1510 GSER()_LANE()_PCS_PLL_CTLIFC_1[PLL_PCS_DIV_OVRRD_VAL],
1511 global power state machine and mac_pcs_pll_div control signals are ignored.
1512 For diagnostic use only. */
1513 uint64_t pll_band_sel_ovrrd_en : 1; /**< [ 1: 1](R/W) PLL band select override enable.
1514 For diagnostic use only. */
1515 uint64_t pll_band_sel_ovrrd_val : 1; /**< [ 2: 2](R/W) State machine override value for VCO band select.
1516 0 = Low band VCO0 (RO-VCO).
1517 1 = High band VCO1 (LC-VCO).
1518
1519 For diagnostic use only. */
1520 uint64_t pcs_sds_pll_div5_byp : 1; /**< [ 3: 3](R/W) Not used.
1521 For diagnostic use only. */
1522 uint64_t pll_pd_ovrrd_en : 1; /**< [ 4: 4](R/W) When asserted, overrides PLL powerdown from state machine.
1523 For diagnostic use only. */
1524 uint64_t pll_pd_ovrrd_val : 1; /**< [ 5: 5](R/W) PLL powerdown override value.
1525 For diagnostic use only. */
1526 uint64_t pll_sdsck_pd_ovrrd_en : 1; /**< [ 6: 6](R/W) Clock tree powerdown override enable.
1527 For diagnostic use only. */
1528 uint64_t pll_sdsck_pd_ovrrd_val : 1; /**< [ 7: 7](R/W) Clock tree powerdown override value.
1529 For diagnostic use only. */
1530 uint64_t pcs_sds_pll_counter_resetn : 1;/**< [ 8: 8](R/W) Not used.
1531 For diagnostic use only. */
1532 uint64_t pcs_sds_pll_lock_override : 1;/**< [ 9: 9](R/W) Not used.
1533 For diagnostic use only. */
1534 uint64_t reserved_10_13 : 4;
1535 uint64_t pll_div_ovrrd_en : 1; /**< [ 14: 14](R/W) Override global power state machine and mac_pcs_pll_div control signal.
1536 When asserted, pcs_sds_pll_div is specified from
1537 GSER()_LANE()_PCS_PLL_CTLIFC_0[PLL_DIV_OVRRD_VAL],
1538 global power state machine and mac_pcs_pll_div control signals are ignored.
1539 For diagnostic use only. */
1540 uint64_t reserved_15_63 : 49;
1541 #endif /* Word 0 - End */
1542 } s;
1543 /* struct bdk_gserx_glbl_pll_cfg_2_s cn; */
1544 };
1545 typedef union bdk_gserx_glbl_pll_cfg_2 bdk_gserx_glbl_pll_cfg_2_t;
1546
1547 static inline uint64_t BDK_GSERX_GLBL_PLL_CFG_2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_GLBL_PLL_CFG_2(unsigned long a)1548 static inline uint64_t BDK_GSERX_GLBL_PLL_CFG_2(unsigned long a)
1549 {
1550 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1551 return 0x87e090460010ll + 0x1000000ll * ((a) & 0x3);
1552 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1553 return 0x87e090460010ll + 0x1000000ll * ((a) & 0x7);
1554 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1555 return 0x87e090460010ll + 0x1000000ll * ((a) & 0xf);
1556 __bdk_csr_fatal("GSERX_GLBL_PLL_CFG_2", 1, a, 0, 0, 0);
1557 }
1558
1559 #define typedef_BDK_GSERX_GLBL_PLL_CFG_2(a) bdk_gserx_glbl_pll_cfg_2_t
1560 #define bustype_BDK_GSERX_GLBL_PLL_CFG_2(a) BDK_CSR_TYPE_RSL
1561 #define basename_BDK_GSERX_GLBL_PLL_CFG_2(a) "GSERX_GLBL_PLL_CFG_2"
1562 #define device_bar_BDK_GSERX_GLBL_PLL_CFG_2(a) 0x0 /* PF_BAR0 */
1563 #define busnum_BDK_GSERX_GLBL_PLL_CFG_2(a) (a)
1564 #define arguments_BDK_GSERX_GLBL_PLL_CFG_2(a) (a),-1,-1,-1
1565
1566 /**
1567 * Register (RSL) gser#_glbl_pll_cfg_3
1568 *
1569 * GSER Global PLL Configuration 3 Register
1570 * These registers are for diagnostic use only.
1571 * These registers are reset by hardware only during chip cold reset.
1572 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1573 */
1574 union bdk_gserx_glbl_pll_cfg_3
1575 {
1576 uint64_t u;
1577 struct bdk_gserx_glbl_pll_cfg_3_s
1578 {
1579 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1580 uint64_t reserved_10_63 : 54;
1581 uint64_t pcs_sds_pll_vco_amp : 2; /**< [ 9: 8](R/W) Adjusts the VCO amplitude control current.
1582 For diagnostic use only.
1583 0x0 = Add 25 uA.
1584 0x1 = OFF (default).
1585 0x2 = Sink 25 uA.
1586 0x3 = Sink 50 uA. */
1587 uint64_t pll_bypass_uq : 1; /**< [ 7: 7](R/W) PLL bypass enable. When asserted, multiplexes in the feedback divider clock.
1588 For diagnostic use only. */
1589 uint64_t pll_vctrl_sel_ovrrd_en : 1; /**< [ 6: 6](R/W) Override enable for selecting current for Vctrl in open loop operation.
1590 For diagnostic use only. */
1591 uint64_t pll_vctrl_sel_ovrrd_val : 2;/**< [ 5: 4](R/W) Override value for selecting current for Vctrl in open loop operation.
1592 For diagnostic use only. */
1593 uint64_t pll_vctrl_sel_lcvco_val : 2;/**< [ 3: 2](R/W) Selects current for Vctrl in open loop operation for LC-tank VCO.
1594 For diagnostic use only. */
1595 uint64_t pll_vctrl_sel_rovco_val : 2;/**< [ 1: 0](R/W) Selects current for Vctrl in open loop operation for ring oscillator VCO.
1596 For diagnostic use only. */
1597 #else /* Word 0 - Little Endian */
1598 uint64_t pll_vctrl_sel_rovco_val : 2;/**< [ 1: 0](R/W) Selects current for Vctrl in open loop operation for ring oscillator VCO.
1599 For diagnostic use only. */
1600 uint64_t pll_vctrl_sel_lcvco_val : 2;/**< [ 3: 2](R/W) Selects current for Vctrl in open loop operation for LC-tank VCO.
1601 For diagnostic use only. */
1602 uint64_t pll_vctrl_sel_ovrrd_val : 2;/**< [ 5: 4](R/W) Override value for selecting current for Vctrl in open loop operation.
1603 For diagnostic use only. */
1604 uint64_t pll_vctrl_sel_ovrrd_en : 1; /**< [ 6: 6](R/W) Override enable for selecting current for Vctrl in open loop operation.
1605 For diagnostic use only. */
1606 uint64_t pll_bypass_uq : 1; /**< [ 7: 7](R/W) PLL bypass enable. When asserted, multiplexes in the feedback divider clock.
1607 For diagnostic use only. */
1608 uint64_t pcs_sds_pll_vco_amp : 2; /**< [ 9: 8](R/W) Adjusts the VCO amplitude control current.
1609 For diagnostic use only.
1610 0x0 = Add 25 uA.
1611 0x1 = OFF (default).
1612 0x2 = Sink 25 uA.
1613 0x3 = Sink 50 uA. */
1614 uint64_t reserved_10_63 : 54;
1615 #endif /* Word 0 - End */
1616 } s;
1617 /* struct bdk_gserx_glbl_pll_cfg_3_s cn; */
1618 };
1619 typedef union bdk_gserx_glbl_pll_cfg_3 bdk_gserx_glbl_pll_cfg_3_t;
1620
1621 static inline uint64_t BDK_GSERX_GLBL_PLL_CFG_3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_GLBL_PLL_CFG_3(unsigned long a)1622 static inline uint64_t BDK_GSERX_GLBL_PLL_CFG_3(unsigned long a)
1623 {
1624 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1625 return 0x87e090460018ll + 0x1000000ll * ((a) & 0x3);
1626 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1627 return 0x87e090460018ll + 0x1000000ll * ((a) & 0x7);
1628 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1629 return 0x87e090460018ll + 0x1000000ll * ((a) & 0xf);
1630 __bdk_csr_fatal("GSERX_GLBL_PLL_CFG_3", 1, a, 0, 0, 0);
1631 }
1632
1633 #define typedef_BDK_GSERX_GLBL_PLL_CFG_3(a) bdk_gserx_glbl_pll_cfg_3_t
1634 #define bustype_BDK_GSERX_GLBL_PLL_CFG_3(a) BDK_CSR_TYPE_RSL
1635 #define basename_BDK_GSERX_GLBL_PLL_CFG_3(a) "GSERX_GLBL_PLL_CFG_3"
1636 #define device_bar_BDK_GSERX_GLBL_PLL_CFG_3(a) 0x0 /* PF_BAR0 */
1637 #define busnum_BDK_GSERX_GLBL_PLL_CFG_3(a) (a)
1638 #define arguments_BDK_GSERX_GLBL_PLL_CFG_3(a) (a),-1,-1,-1
1639
1640 /**
1641 * Register (RSL) gser#_glbl_pll_monitor
1642 *
1643 * GSER Monitor for SerDes Global to Raw PCS Global interface Register
1644 * These registers are for diagnostic use only.
1645 * These registers are reset by hardware only during chip cold reset.
1646 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1647 */
1648 union bdk_gserx_glbl_pll_monitor
1649 {
1650 uint64_t u;
1651 struct bdk_gserx_glbl_pll_monitor_s
1652 {
1653 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1654 uint64_t reserved_14_63 : 50;
1655 uint64_t sds_pcs_glbl_status : 6; /**< [ 13: 8](RO/H) Spare reserved for future use. Read data should be ignored. */
1656 uint64_t sds_pcs_pll_lock : 1; /**< [ 7: 7](RO/H) Status signal from global indicates that PLL is locked. Not a true "lock" signal.
1657 Used to debug/test the PLL. */
1658 uint64_t sds_pcs_clock_ready : 1; /**< [ 6: 6](RO/H) Clock status signal, can be overridden with (I_PLL_CTRL_EN == 1).
1659 0 = Clock not ready.
1660 1 = Clock ready. */
1661 uint64_t sds_pcs_pll_calstates : 5; /**< [ 5: 1](RO/H) PLL calibration code. */
1662 uint64_t sds_pcs_pll_caldone : 1; /**< [ 0: 0](RO/H) PLL calibration done signal. */
1663 #else /* Word 0 - Little Endian */
1664 uint64_t sds_pcs_pll_caldone : 1; /**< [ 0: 0](RO/H) PLL calibration done signal. */
1665 uint64_t sds_pcs_pll_calstates : 5; /**< [ 5: 1](RO/H) PLL calibration code. */
1666 uint64_t sds_pcs_clock_ready : 1; /**< [ 6: 6](RO/H) Clock status signal, can be overridden with (I_PLL_CTRL_EN == 1).
1667 0 = Clock not ready.
1668 1 = Clock ready. */
1669 uint64_t sds_pcs_pll_lock : 1; /**< [ 7: 7](RO/H) Status signal from global indicates that PLL is locked. Not a true "lock" signal.
1670 Used to debug/test the PLL. */
1671 uint64_t sds_pcs_glbl_status : 6; /**< [ 13: 8](RO/H) Spare reserved for future use. Read data should be ignored. */
1672 uint64_t reserved_14_63 : 50;
1673 #endif /* Word 0 - End */
1674 } s;
1675 struct bdk_gserx_glbl_pll_monitor_cn
1676 {
1677 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1678 uint64_t reserved_16_63 : 48;
1679 uint64_t reserved_14_15 : 2;
1680 uint64_t sds_pcs_glbl_status : 6; /**< [ 13: 8](RO/H) Spare reserved for future use. Read data should be ignored. */
1681 uint64_t sds_pcs_pll_lock : 1; /**< [ 7: 7](RO/H) Status signal from global indicates that PLL is locked. Not a true "lock" signal.
1682 Used to debug/test the PLL. */
1683 uint64_t sds_pcs_clock_ready : 1; /**< [ 6: 6](RO/H) Clock status signal, can be overridden with (I_PLL_CTRL_EN == 1).
1684 0 = Clock not ready.
1685 1 = Clock ready. */
1686 uint64_t sds_pcs_pll_calstates : 5; /**< [ 5: 1](RO/H) PLL calibration code. */
1687 uint64_t sds_pcs_pll_caldone : 1; /**< [ 0: 0](RO/H) PLL calibration done signal. */
1688 #else /* Word 0 - Little Endian */
1689 uint64_t sds_pcs_pll_caldone : 1; /**< [ 0: 0](RO/H) PLL calibration done signal. */
1690 uint64_t sds_pcs_pll_calstates : 5; /**< [ 5: 1](RO/H) PLL calibration code. */
1691 uint64_t sds_pcs_clock_ready : 1; /**< [ 6: 6](RO/H) Clock status signal, can be overridden with (I_PLL_CTRL_EN == 1).
1692 0 = Clock not ready.
1693 1 = Clock ready. */
1694 uint64_t sds_pcs_pll_lock : 1; /**< [ 7: 7](RO/H) Status signal from global indicates that PLL is locked. Not a true "lock" signal.
1695 Used to debug/test the PLL. */
1696 uint64_t sds_pcs_glbl_status : 6; /**< [ 13: 8](RO/H) Spare reserved for future use. Read data should be ignored. */
1697 uint64_t reserved_14_15 : 2;
1698 uint64_t reserved_16_63 : 48;
1699 #endif /* Word 0 - End */
1700 } cn;
1701 };
1702 typedef union bdk_gserx_glbl_pll_monitor bdk_gserx_glbl_pll_monitor_t;
1703
1704 static inline uint64_t BDK_GSERX_GLBL_PLL_MONITOR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_GLBL_PLL_MONITOR(unsigned long a)1705 static inline uint64_t BDK_GSERX_GLBL_PLL_MONITOR(unsigned long a)
1706 {
1707 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1708 return 0x87e090460100ll + 0x1000000ll * ((a) & 0x3);
1709 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1710 return 0x87e090460100ll + 0x1000000ll * ((a) & 0x7);
1711 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1712 return 0x87e090460100ll + 0x1000000ll * ((a) & 0xf);
1713 __bdk_csr_fatal("GSERX_GLBL_PLL_MONITOR", 1, a, 0, 0, 0);
1714 }
1715
1716 #define typedef_BDK_GSERX_GLBL_PLL_MONITOR(a) bdk_gserx_glbl_pll_monitor_t
1717 #define bustype_BDK_GSERX_GLBL_PLL_MONITOR(a) BDK_CSR_TYPE_RSL
1718 #define basename_BDK_GSERX_GLBL_PLL_MONITOR(a) "GSERX_GLBL_PLL_MONITOR"
1719 #define device_bar_BDK_GSERX_GLBL_PLL_MONITOR(a) 0x0 /* PF_BAR0 */
1720 #define busnum_BDK_GSERX_GLBL_PLL_MONITOR(a) (a)
1721 #define arguments_BDK_GSERX_GLBL_PLL_MONITOR(a) (a),-1,-1,-1
1722
1723 /**
1724 * Register (RSL) gser#_glbl_tad
1725 *
1726 * GSER Global Test Analog and Digital Monitor Register
1727 * These registers are for diagnostic use only.
1728 * These registers are reset by hardware only during chip cold reset.
1729 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1730 */
1731 union bdk_gserx_glbl_tad
1732 {
1733 uint64_t u;
1734 struct bdk_gserx_glbl_tad_s
1735 {
1736 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1737 uint64_t reserved_9_63 : 55;
1738 uint64_t pcs_sds_tad_8_5 : 4; /**< [ 8: 5](R/W) AMON specific mode selection.
1739 Set GSER()_GLBL_TM_ADMON[AMON_ON].
1740 Decodes 0x0 - 0x4 require GSER()_GLBL_TM_ADMON[LSEL] set.
1741 Decodes 0x5 - 0x5 do not require GSER()_GLBL_TM_ADMON[LSEL] set.
1742 In both cases, the resulting signals can be observed on the AMON pin.
1743
1744 0x0 = TX txdrv DAC 100ua sink current monitor.
1745 0x1 = TX vcnt precision dcc.
1746 0x2 = RX sdll topregout.
1747 0x3 = RX ldll vctrl_i.
1748 0x4 = RX RX term VCM voltage.
1749 0x5 = Global bandgap voltage.
1750 0x6 = Global CTAT voltage.
1751 0x7 = Global internal 100ua reference current.
1752 0x8 = Global external 100ua reference current.
1753 0x9 = Global Rterm calibration reference voltage.
1754 0xA = Global Rterm calibration comparator voltage.
1755 0xB = Global force VCNT through DAC.
1756 0xC = Global VDD voltage.
1757 0xD = Global VDDCLK voltage.
1758 0xE = Global PLL regulate VCO supply.
1759 0xF = Global VCTRL for VCO varactor control. */
1760 uint64_t pcs_sds_tad_4_0 : 5; /**< [ 4: 0](R/W) DMON specific mode selection.
1761 Set GSER()_GLBL_TM_ADMON[DMON_ON].
1762 Decodes 0x0 - 0xe require GSER()_GLBL_TM_ADMON[LSEL] set.
1763 Decodes 0xf - 0x1f do not require GSER()_GLBL_TM_ADMON[LSEL] set.
1764 In both cases, the resulting signals can be observed on the DMON pin.
1765
1766 0x00 = DFE Data Q.
1767 0x01 = DFE Edge I.
1768 0x02 = DFE CK Q.
1769 0x03 = DFE CK I.
1770 0x04 = DLL use GSER()_SLICE()_RX_SDLL_CTRL.PCS_SDS_RX_SDLL_SWSEL to select signal
1771 in the slice DLL.
1772 0x05-0x7 = Reserved.
1773 0x08 = RX ld_rx[0].
1774 0x09 = RX rx_clk.
1775 0x0A = RX q_error_stg.
1776 0x0B = RX q_data_stg.
1777 0x0C-0x0E = Reserved.
1778 0x0F = Special case to observe supply in global. Sds_vdda and a internal regulated supply
1779 can be observed on DMON and DMONB
1780 respectively. sds_vss can be observed on AMON. GSER()_GLBL_TM_ADMON[AMON_ON]
1781 must not be set.
1782 0x10 = PLL_CLK 0 degree.
1783 0x11 = Sds_tst_fb_clk.
1784 0x12 = Buffered refclk.
1785 0x13 = Div 8 of core clock (core_clk_out).
1786 0x14-0x1F: Reserved. */
1787 #else /* Word 0 - Little Endian */
1788 uint64_t pcs_sds_tad_4_0 : 5; /**< [ 4: 0](R/W) DMON specific mode selection.
1789 Set GSER()_GLBL_TM_ADMON[DMON_ON].
1790 Decodes 0x0 - 0xe require GSER()_GLBL_TM_ADMON[LSEL] set.
1791 Decodes 0xf - 0x1f do not require GSER()_GLBL_TM_ADMON[LSEL] set.
1792 In both cases, the resulting signals can be observed on the DMON pin.
1793
1794 0x00 = DFE Data Q.
1795 0x01 = DFE Edge I.
1796 0x02 = DFE CK Q.
1797 0x03 = DFE CK I.
1798 0x04 = DLL use GSER()_SLICE()_RX_SDLL_CTRL.PCS_SDS_RX_SDLL_SWSEL to select signal
1799 in the slice DLL.
1800 0x05-0x7 = Reserved.
1801 0x08 = RX ld_rx[0].
1802 0x09 = RX rx_clk.
1803 0x0A = RX q_error_stg.
1804 0x0B = RX q_data_stg.
1805 0x0C-0x0E = Reserved.
1806 0x0F = Special case to observe supply in global. Sds_vdda and a internal regulated supply
1807 can be observed on DMON and DMONB
1808 respectively. sds_vss can be observed on AMON. GSER()_GLBL_TM_ADMON[AMON_ON]
1809 must not be set.
1810 0x10 = PLL_CLK 0 degree.
1811 0x11 = Sds_tst_fb_clk.
1812 0x12 = Buffered refclk.
1813 0x13 = Div 8 of core clock (core_clk_out).
1814 0x14-0x1F: Reserved. */
1815 uint64_t pcs_sds_tad_8_5 : 4; /**< [ 8: 5](R/W) AMON specific mode selection.
1816 Set GSER()_GLBL_TM_ADMON[AMON_ON].
1817 Decodes 0x0 - 0x4 require GSER()_GLBL_TM_ADMON[LSEL] set.
1818 Decodes 0x5 - 0x5 do not require GSER()_GLBL_TM_ADMON[LSEL] set.
1819 In both cases, the resulting signals can be observed on the AMON pin.
1820
1821 0x0 = TX txdrv DAC 100ua sink current monitor.
1822 0x1 = TX vcnt precision dcc.
1823 0x2 = RX sdll topregout.
1824 0x3 = RX ldll vctrl_i.
1825 0x4 = RX RX term VCM voltage.
1826 0x5 = Global bandgap voltage.
1827 0x6 = Global CTAT voltage.
1828 0x7 = Global internal 100ua reference current.
1829 0x8 = Global external 100ua reference current.
1830 0x9 = Global Rterm calibration reference voltage.
1831 0xA = Global Rterm calibration comparator voltage.
1832 0xB = Global force VCNT through DAC.
1833 0xC = Global VDD voltage.
1834 0xD = Global VDDCLK voltage.
1835 0xE = Global PLL regulate VCO supply.
1836 0xF = Global VCTRL for VCO varactor control. */
1837 uint64_t reserved_9_63 : 55;
1838 #endif /* Word 0 - End */
1839 } s;
1840 /* struct bdk_gserx_glbl_tad_s cn; */
1841 };
1842 typedef union bdk_gserx_glbl_tad bdk_gserx_glbl_tad_t;
1843
1844 static inline uint64_t BDK_GSERX_GLBL_TAD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_GLBL_TAD(unsigned long a)1845 static inline uint64_t BDK_GSERX_GLBL_TAD(unsigned long a)
1846 {
1847 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1848 return 0x87e090460400ll + 0x1000000ll * ((a) & 0x3);
1849 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1850 return 0x87e090460400ll + 0x1000000ll * ((a) & 0x7);
1851 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1852 return 0x87e090460400ll + 0x1000000ll * ((a) & 0xf);
1853 __bdk_csr_fatal("GSERX_GLBL_TAD", 1, a, 0, 0, 0);
1854 }
1855
1856 #define typedef_BDK_GSERX_GLBL_TAD(a) bdk_gserx_glbl_tad_t
1857 #define bustype_BDK_GSERX_GLBL_TAD(a) BDK_CSR_TYPE_RSL
1858 #define basename_BDK_GSERX_GLBL_TAD(a) "GSERX_GLBL_TAD"
1859 #define device_bar_BDK_GSERX_GLBL_TAD(a) 0x0 /* PF_BAR0 */
1860 #define busnum_BDK_GSERX_GLBL_TAD(a) (a)
1861 #define arguments_BDK_GSERX_GLBL_TAD(a) (a),-1,-1,-1
1862
1863 /**
1864 * Register (RSL) gser#_glbl_tm_admon
1865 *
1866 * GSER Global Test Mode Analog/Digital Monitor Enable Register
1867 * These registers are for diagnostic use only.
1868 * These registers are reset by hardware only during chip cold reset.
1869 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1870 */
1871 union bdk_gserx_glbl_tm_admon
1872 {
1873 uint64_t u;
1874 struct bdk_gserx_glbl_tm_admon_s
1875 {
1876 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1877 uint64_t reserved_8_63 : 56;
1878 uint64_t amon_on : 1; /**< [ 7: 7](R/W) When set, AMON test mode is enabled; see GSER()_GLBL_TAD. */
1879 uint64_t dmon_on : 1; /**< [ 6: 6](R/W) When set, DMON test mode is enabled; see GSER()_GLBL_TAD. */
1880 uint64_t reserved_3_5 : 3;
1881 uint64_t lsel : 3; /**< [ 2: 0](R/W) Three bits to select 1 out of 4 lanes for AMON/DMON test.
1882 0x0 = Selects lane 0.
1883 0x1 = Selects lane 1.
1884 0x2 = Selects lane 2.
1885 0x3 = Selects lane 3.
1886 0x4-0x7 = Reserved. */
1887 #else /* Word 0 - Little Endian */
1888 uint64_t lsel : 3; /**< [ 2: 0](R/W) Three bits to select 1 out of 4 lanes for AMON/DMON test.
1889 0x0 = Selects lane 0.
1890 0x1 = Selects lane 1.
1891 0x2 = Selects lane 2.
1892 0x3 = Selects lane 3.
1893 0x4-0x7 = Reserved. */
1894 uint64_t reserved_3_5 : 3;
1895 uint64_t dmon_on : 1; /**< [ 6: 6](R/W) When set, DMON test mode is enabled; see GSER()_GLBL_TAD. */
1896 uint64_t amon_on : 1; /**< [ 7: 7](R/W) When set, AMON test mode is enabled; see GSER()_GLBL_TAD. */
1897 uint64_t reserved_8_63 : 56;
1898 #endif /* Word 0 - End */
1899 } s;
1900 /* struct bdk_gserx_glbl_tm_admon_s cn; */
1901 };
1902 typedef union bdk_gserx_glbl_tm_admon bdk_gserx_glbl_tm_admon_t;
1903
1904 static inline uint64_t BDK_GSERX_GLBL_TM_ADMON(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_GLBL_TM_ADMON(unsigned long a)1905 static inline uint64_t BDK_GSERX_GLBL_TM_ADMON(unsigned long a)
1906 {
1907 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1908 return 0x87e090460408ll + 0x1000000ll * ((a) & 0x3);
1909 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1910 return 0x87e090460408ll + 0x1000000ll * ((a) & 0x7);
1911 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1912 return 0x87e090460408ll + 0x1000000ll * ((a) & 0xf);
1913 __bdk_csr_fatal("GSERX_GLBL_TM_ADMON", 1, a, 0, 0, 0);
1914 }
1915
1916 #define typedef_BDK_GSERX_GLBL_TM_ADMON(a) bdk_gserx_glbl_tm_admon_t
1917 #define bustype_BDK_GSERX_GLBL_TM_ADMON(a) BDK_CSR_TYPE_RSL
1918 #define basename_BDK_GSERX_GLBL_TM_ADMON(a) "GSERX_GLBL_TM_ADMON"
1919 #define device_bar_BDK_GSERX_GLBL_TM_ADMON(a) 0x0 /* PF_BAR0 */
1920 #define busnum_BDK_GSERX_GLBL_TM_ADMON(a) (a)
1921 #define arguments_BDK_GSERX_GLBL_TM_ADMON(a) (a),-1,-1,-1
1922
1923 /**
1924 * Register (RSL) gser#_iddq_mode
1925 *
1926 * GSER IDDQ Mode Register
1927 * These registers are reset by hardware only during chip cold reset. The values of the CSR
1928 * fields in these registers do not change during chip warm or soft resets.
1929 */
1930 union bdk_gserx_iddq_mode
1931 {
1932 uint64_t u;
1933 struct bdk_gserx_iddq_mode_s
1934 {
1935 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1936 uint64_t reserved_1_63 : 63;
1937 uint64_t phy_iddq_mode : 1; /**< [ 0: 0](R/W) When set, power downs all circuitry in PHY for IDDQ testing */
1938 #else /* Word 0 - Little Endian */
1939 uint64_t phy_iddq_mode : 1; /**< [ 0: 0](R/W) When set, power downs all circuitry in PHY for IDDQ testing */
1940 uint64_t reserved_1_63 : 63;
1941 #endif /* Word 0 - End */
1942 } s;
1943 /* struct bdk_gserx_iddq_mode_s cn; */
1944 };
1945 typedef union bdk_gserx_iddq_mode bdk_gserx_iddq_mode_t;
1946
1947 static inline uint64_t BDK_GSERX_IDDQ_MODE(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_IDDQ_MODE(unsigned long a)1948 static inline uint64_t BDK_GSERX_IDDQ_MODE(unsigned long a)
1949 {
1950 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
1951 return 0x87e090000018ll + 0x1000000ll * ((a) & 0x3);
1952 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
1953 return 0x87e090000018ll + 0x1000000ll * ((a) & 0x7);
1954 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
1955 return 0x87e090000018ll + 0x1000000ll * ((a) & 0xf);
1956 __bdk_csr_fatal("GSERX_IDDQ_MODE", 1, a, 0, 0, 0);
1957 }
1958
1959 #define typedef_BDK_GSERX_IDDQ_MODE(a) bdk_gserx_iddq_mode_t
1960 #define bustype_BDK_GSERX_IDDQ_MODE(a) BDK_CSR_TYPE_RSL
1961 #define basename_BDK_GSERX_IDDQ_MODE(a) "GSERX_IDDQ_MODE"
1962 #define device_bar_BDK_GSERX_IDDQ_MODE(a) 0x0 /* PF_BAR0 */
1963 #define busnum_BDK_GSERX_IDDQ_MODE(a) (a)
1964 #define arguments_BDK_GSERX_IDDQ_MODE(a) (a),-1,-1,-1
1965
1966 /**
1967 * Register (RSL) gser#_lane#_lbert_cfg
1968 *
1969 * GSER Lane LBERT Configuration Registers
1970 * These registers are reset by hardware only during chip cold reset.
1971 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
1972 */
1973 union bdk_gserx_lanex_lbert_cfg
1974 {
1975 uint64_t u;
1976 struct bdk_gserx_lanex_lbert_cfg_s
1977 {
1978 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1979 uint64_t reserved_16_63 : 48;
1980 uint64_t lbert_pg_err_insert : 1; /**< [ 15: 15](WO/H) Insert one bit error into the LSB of the LBERT generated
1981 stream. A single write to this bit inserts a single bit
1982 error. */
1983 uint64_t lbert_pm_sync_start : 1; /**< [ 14: 14](WO/H) Synchronize the pattern matcher LFSR with the incoming
1984 data. Writing this bit resets the error counter and
1985 starts a synchronization of the PM. There is no need
1986 to write this bit back to a zero to run normally. */
1987 uint64_t lbert_pg_en : 1; /**< [ 13: 13](R/W) Enable the LBERT pattern generator. */
1988 uint64_t lbert_pg_width : 2; /**< [ 12: 11](R/W) LBERT pattern generator data width:
1989 0x0 = 8-bit data.
1990 0x1 = 10-bit data.
1991 0x2 = 16-bit data.
1992 0x3 = 20-bit data. */
1993 uint64_t lbert_pg_mode : 4; /**< [ 10: 7](R/W) LBERT pattern generator mode; when changing modes,
1994 must be disabled first:
1995 0x0 = Disabled.
1996 0x1 = lfsr31 = X^31 + X^28 + 1.
1997 0x2 = lfsr23 = X^23 + X^18 + 1.
1998 0x3 = lfsr23 = X^23 + X^21 + X^16 + X^8 + X^5 + X^2 + 1.
1999 0x4 = lfsr16 = X^16 + X^5 + X^4 + X^3 + 1.
2000 0x5 = lfsr15 = X^15 + X^14 + 1.
2001 0x6 = lfsr11 = X^11 + X^9 + 1.
2002 0x7 = lfsr7 = X^7 + X^6 + 1.
2003 0x8 = Fixed word (PAT0).
2004 0x9 = DC-balanced word (PAT0, ~PAT0).
2005 0xA = Fixed Pattern (000, PAT0, 3ff, ~PAT0).
2006 0xB-F = Reserved. */
2007 uint64_t lbert_pm_en : 1; /**< [ 6: 6](R/W) Enable LBERT pattern matcher. */
2008 uint64_t lbert_pm_width : 2; /**< [ 5: 4](R/W) LBERT pattern matcher data width.
2009 0x0 = 8-bit data.
2010 0x1 = 10-bit data.
2011 0x2 = 16-bit data.
2012 0x3 = 20-bit data. */
2013 uint64_t lbert_pm_mode : 4; /**< [ 3: 0](R/W) LBERT pattern matcher mode; when changing modes,
2014 must be disabled first:
2015 0x0 = Disabled.
2016 0x1 = lfsr31 = X^31 + X^28 + 1.
2017 0x2 = lfsr23 = X^23 + X^18 + 1.
2018 0x3 = lfsr23 = X^23 + X^21 + X^16 + X^8 + X^5 + X^2 + 1.
2019 0x4 = lfsr16 = X^16 + X^5 + X^4 + X^3 + 1.
2020 0x5 = lfsr15 = X^15 + X^14 + 1.
2021 0x6 = lfsr11 = X^11 + X^9 + 1.
2022 0x7 = lfsr7 = X^7 + X^6 + 1.
2023 0x8 = Fixed word (PAT0).
2024 0x9 = DC-balanced word (PAT0, ~PAT0).
2025 0xA = Fixed Pattern: (000, PAT0, 3ff, ~PAT0).
2026 0xB-F = Reserved. */
2027 #else /* Word 0 - Little Endian */
2028 uint64_t lbert_pm_mode : 4; /**< [ 3: 0](R/W) LBERT pattern matcher mode; when changing modes,
2029 must be disabled first:
2030 0x0 = Disabled.
2031 0x1 = lfsr31 = X^31 + X^28 + 1.
2032 0x2 = lfsr23 = X^23 + X^18 + 1.
2033 0x3 = lfsr23 = X^23 + X^21 + X^16 + X^8 + X^5 + X^2 + 1.
2034 0x4 = lfsr16 = X^16 + X^5 + X^4 + X^3 + 1.
2035 0x5 = lfsr15 = X^15 + X^14 + 1.
2036 0x6 = lfsr11 = X^11 + X^9 + 1.
2037 0x7 = lfsr7 = X^7 + X^6 + 1.
2038 0x8 = Fixed word (PAT0).
2039 0x9 = DC-balanced word (PAT0, ~PAT0).
2040 0xA = Fixed Pattern: (000, PAT0, 3ff, ~PAT0).
2041 0xB-F = Reserved. */
2042 uint64_t lbert_pm_width : 2; /**< [ 5: 4](R/W) LBERT pattern matcher data width.
2043 0x0 = 8-bit data.
2044 0x1 = 10-bit data.
2045 0x2 = 16-bit data.
2046 0x3 = 20-bit data. */
2047 uint64_t lbert_pm_en : 1; /**< [ 6: 6](R/W) Enable LBERT pattern matcher. */
2048 uint64_t lbert_pg_mode : 4; /**< [ 10: 7](R/W) LBERT pattern generator mode; when changing modes,
2049 must be disabled first:
2050 0x0 = Disabled.
2051 0x1 = lfsr31 = X^31 + X^28 + 1.
2052 0x2 = lfsr23 = X^23 + X^18 + 1.
2053 0x3 = lfsr23 = X^23 + X^21 + X^16 + X^8 + X^5 + X^2 + 1.
2054 0x4 = lfsr16 = X^16 + X^5 + X^4 + X^3 + 1.
2055 0x5 = lfsr15 = X^15 + X^14 + 1.
2056 0x6 = lfsr11 = X^11 + X^9 + 1.
2057 0x7 = lfsr7 = X^7 + X^6 + 1.
2058 0x8 = Fixed word (PAT0).
2059 0x9 = DC-balanced word (PAT0, ~PAT0).
2060 0xA = Fixed Pattern (000, PAT0, 3ff, ~PAT0).
2061 0xB-F = Reserved. */
2062 uint64_t lbert_pg_width : 2; /**< [ 12: 11](R/W) LBERT pattern generator data width:
2063 0x0 = 8-bit data.
2064 0x1 = 10-bit data.
2065 0x2 = 16-bit data.
2066 0x3 = 20-bit data. */
2067 uint64_t lbert_pg_en : 1; /**< [ 13: 13](R/W) Enable the LBERT pattern generator. */
2068 uint64_t lbert_pm_sync_start : 1; /**< [ 14: 14](WO/H) Synchronize the pattern matcher LFSR with the incoming
2069 data. Writing this bit resets the error counter and
2070 starts a synchronization of the PM. There is no need
2071 to write this bit back to a zero to run normally. */
2072 uint64_t lbert_pg_err_insert : 1; /**< [ 15: 15](WO/H) Insert one bit error into the LSB of the LBERT generated
2073 stream. A single write to this bit inserts a single bit
2074 error. */
2075 uint64_t reserved_16_63 : 48;
2076 #endif /* Word 0 - End */
2077 } s;
2078 /* struct bdk_gserx_lanex_lbert_cfg_s cn; */
2079 };
2080 typedef union bdk_gserx_lanex_lbert_cfg bdk_gserx_lanex_lbert_cfg_t;
2081
2082 static inline uint64_t BDK_GSERX_LANEX_LBERT_CFG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_LBERT_CFG(unsigned long a,unsigned long b)2083 static inline uint64_t BDK_GSERX_LANEX_LBERT_CFG(unsigned long a, unsigned long b)
2084 {
2085 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2086 return 0x87e0904c0020ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2087 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2088 return 0x87e0904c0020ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2089 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2090 return 0x87e0904c0020ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2091 __bdk_csr_fatal("GSERX_LANEX_LBERT_CFG", 2, a, b, 0, 0);
2092 }
2093
2094 #define typedef_BDK_GSERX_LANEX_LBERT_CFG(a,b) bdk_gserx_lanex_lbert_cfg_t
2095 #define bustype_BDK_GSERX_LANEX_LBERT_CFG(a,b) BDK_CSR_TYPE_RSL
2096 #define basename_BDK_GSERX_LANEX_LBERT_CFG(a,b) "GSERX_LANEX_LBERT_CFG"
2097 #define device_bar_BDK_GSERX_LANEX_LBERT_CFG(a,b) 0x0 /* PF_BAR0 */
2098 #define busnum_BDK_GSERX_LANEX_LBERT_CFG(a,b) (a)
2099 #define arguments_BDK_GSERX_LANEX_LBERT_CFG(a,b) (a),(b),-1,-1
2100
2101 /**
2102 * Register (RSL) gser#_lane#_lbert_ecnt
2103 *
2104 * GSER Lane LBERT Error Counter Registers
2105 * These registers are reset by hardware only during chip cold reset.
2106 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2107 * The error registers are reset on a read-only when the pattern matcher is enabled.
2108 * If the pattern matcher is disabled, the registers return the error count that was
2109 * indicated when the pattern matcher was disabled and never reset.
2110 */
2111 union bdk_gserx_lanex_lbert_ecnt
2112 {
2113 uint64_t u;
2114 struct bdk_gserx_lanex_lbert_ecnt_s
2115 {
2116 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2117 uint64_t reserved_16_63 : 48;
2118 uint64_t lbert_err_ovbit14 : 1; /**< [ 15: 15](RO/H) If this bit is set, multiply [LBERT_ERR_CNT] by 128.
2119 If this bit is set and [LBERT_ERR_CNT] = 2^15-1, signals
2120 overflow of the counter. */
2121 uint64_t lbert_err_cnt : 15; /**< [ 14: 0](RO/H) Current bit error count.
2122 If [LBERT_ERR_OVBIT14] is active, then multiply
2123 count by 128. */
2124 #else /* Word 0 - Little Endian */
2125 uint64_t lbert_err_cnt : 15; /**< [ 14: 0](RO/H) Current bit error count.
2126 If [LBERT_ERR_OVBIT14] is active, then multiply
2127 count by 128. */
2128 uint64_t lbert_err_ovbit14 : 1; /**< [ 15: 15](RO/H) If this bit is set, multiply [LBERT_ERR_CNT] by 128.
2129 If this bit is set and [LBERT_ERR_CNT] = 2^15-1, signals
2130 overflow of the counter. */
2131 uint64_t reserved_16_63 : 48;
2132 #endif /* Word 0 - End */
2133 } s;
2134 /* struct bdk_gserx_lanex_lbert_ecnt_s cn; */
2135 };
2136 typedef union bdk_gserx_lanex_lbert_ecnt bdk_gserx_lanex_lbert_ecnt_t;
2137
2138 static inline uint64_t BDK_GSERX_LANEX_LBERT_ECNT(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_LBERT_ECNT(unsigned long a,unsigned long b)2139 static inline uint64_t BDK_GSERX_LANEX_LBERT_ECNT(unsigned long a, unsigned long b)
2140 {
2141 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2142 return 0x87e0904c0028ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2143 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2144 return 0x87e0904c0028ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2145 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2146 return 0x87e0904c0028ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2147 __bdk_csr_fatal("GSERX_LANEX_LBERT_ECNT", 2, a, b, 0, 0);
2148 }
2149
2150 #define typedef_BDK_GSERX_LANEX_LBERT_ECNT(a,b) bdk_gserx_lanex_lbert_ecnt_t
2151 #define bustype_BDK_GSERX_LANEX_LBERT_ECNT(a,b) BDK_CSR_TYPE_RSL
2152 #define basename_BDK_GSERX_LANEX_LBERT_ECNT(a,b) "GSERX_LANEX_LBERT_ECNT"
2153 #define device_bar_BDK_GSERX_LANEX_LBERT_ECNT(a,b) 0x0 /* PF_BAR0 */
2154 #define busnum_BDK_GSERX_LANEX_LBERT_ECNT(a,b) (a)
2155 #define arguments_BDK_GSERX_LANEX_LBERT_ECNT(a,b) (a),(b),-1,-1
2156
2157 /**
2158 * Register (RSL) gser#_lane#_lbert_pat_cfg
2159 *
2160 * GSER Lane LBERT Pattern Configuration Registers
2161 * These registers are reset by hardware only during chip cold reset.
2162 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2163 */
2164 union bdk_gserx_lanex_lbert_pat_cfg
2165 {
2166 uint64_t u;
2167 struct bdk_gserx_lanex_lbert_pat_cfg_s
2168 {
2169 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2170 uint64_t reserved_10_63 : 54;
2171 uint64_t lbert_pg_pat : 10; /**< [ 9: 0](R/W) Programmable 10-bit pattern to be used in the LBERT pattern mode;
2172 applies when GSER()_LANE()_LBERT_CFG[LBERT_PG_MODE]
2173 is equal to 8, 9, or 10. */
2174 #else /* Word 0 - Little Endian */
2175 uint64_t lbert_pg_pat : 10; /**< [ 9: 0](R/W) Programmable 10-bit pattern to be used in the LBERT pattern mode;
2176 applies when GSER()_LANE()_LBERT_CFG[LBERT_PG_MODE]
2177 is equal to 8, 9, or 10. */
2178 uint64_t reserved_10_63 : 54;
2179 #endif /* Word 0 - End */
2180 } s;
2181 /* struct bdk_gserx_lanex_lbert_pat_cfg_s cn; */
2182 };
2183 typedef union bdk_gserx_lanex_lbert_pat_cfg bdk_gserx_lanex_lbert_pat_cfg_t;
2184
2185 static inline uint64_t BDK_GSERX_LANEX_LBERT_PAT_CFG(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_LBERT_PAT_CFG(unsigned long a,unsigned long b)2186 static inline uint64_t BDK_GSERX_LANEX_LBERT_PAT_CFG(unsigned long a, unsigned long b)
2187 {
2188 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2189 return 0x87e0904c0018ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2190 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2191 return 0x87e0904c0018ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2192 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2193 return 0x87e0904c0018ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2194 __bdk_csr_fatal("GSERX_LANEX_LBERT_PAT_CFG", 2, a, b, 0, 0);
2195 }
2196
2197 #define typedef_BDK_GSERX_LANEX_LBERT_PAT_CFG(a,b) bdk_gserx_lanex_lbert_pat_cfg_t
2198 #define bustype_BDK_GSERX_LANEX_LBERT_PAT_CFG(a,b) BDK_CSR_TYPE_RSL
2199 #define basename_BDK_GSERX_LANEX_LBERT_PAT_CFG(a,b) "GSERX_LANEX_LBERT_PAT_CFG"
2200 #define device_bar_BDK_GSERX_LANEX_LBERT_PAT_CFG(a,b) 0x0 /* PF_BAR0 */
2201 #define busnum_BDK_GSERX_LANEX_LBERT_PAT_CFG(a,b) (a)
2202 #define arguments_BDK_GSERX_LANEX_LBERT_PAT_CFG(a,b) (a),(b),-1,-1
2203
2204 /**
2205 * Register (RSL) gser#_lane#_misc_cfg_0
2206 *
2207 * GSER Lane Miscellaneous Configuration 0 Register
2208 * These registers are for diagnostic use only.
2209 * These registers are reset by hardware only during chip cold reset.
2210 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2211 */
2212 union bdk_gserx_lanex_misc_cfg_0
2213 {
2214 uint64_t u;
2215 struct bdk_gserx_lanex_misc_cfg_0_s
2216 {
2217 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2218 uint64_t reserved_16_63 : 48;
2219 uint64_t use_pma_polarity : 1; /**< [ 15: 15](R/W) If set, the PMA control is used to define the polarity.
2220 If not set, GSER()_LANE()_RX_CFG_0[CFG_RX_POL_INVERT]
2221 is used. */
2222 uint64_t cfg_pcs_loopback : 1; /**< [ 14: 14](R/W) Assert for parallel loopback raw PCS TX to Raw PCS RX. */
2223 uint64_t pcs_tx_mode_ovrrd_en : 1; /**< [ 13: 13](R/W) Override enable for raw PCS TX data width. */
2224 uint64_t pcs_rx_mode_ovrrd_en : 1; /**< [ 12: 12](R/W) Override enable for raw PCS RX data width. */
2225 uint64_t cfg_eie_det_cnt : 4; /**< [ 11: 8](R/W) EIE detect state machine required number of consecutive
2226 PHY EIE status assertions to determine EIE and assert Raw
2227 PCS output pcs_mac_rx_eie_det_sts. */
2228 uint64_t eie_det_stl_on_time : 3; /**< [ 7: 5](R/W) EIE detect state machine "on" delay prior to sampling
2229 PHY EIE status. Software needs to set this field to 0x4 if
2230 in SATA mode (GSER()_CFG[SATA] is set). */
2231 uint64_t eie_det_stl_off_time : 3; /**< [ 4: 2](R/W) EIE detect state machine "off" delay prior to sampling
2232 PHY EIE status. */
2233 uint64_t tx_bit_order : 1; /**< [ 1: 1](R/W) Specify transmit bit order.
2234 0 = Maintain bit order of parallel data to SerDes TX.
2235 1 = Reverse bit order of parallel data to SerDes TX. */
2236 uint64_t rx_bit_order : 1; /**< [ 0: 0](R/W) Specify receive bit order:
2237 0 = Maintain bit order of parallel data to SerDes RX.
2238 1 = Reverse bit order of parallel data to SerDes RX. */
2239 #else /* Word 0 - Little Endian */
2240 uint64_t rx_bit_order : 1; /**< [ 0: 0](R/W) Specify receive bit order:
2241 0 = Maintain bit order of parallel data to SerDes RX.
2242 1 = Reverse bit order of parallel data to SerDes RX. */
2243 uint64_t tx_bit_order : 1; /**< [ 1: 1](R/W) Specify transmit bit order.
2244 0 = Maintain bit order of parallel data to SerDes TX.
2245 1 = Reverse bit order of parallel data to SerDes TX. */
2246 uint64_t eie_det_stl_off_time : 3; /**< [ 4: 2](R/W) EIE detect state machine "off" delay prior to sampling
2247 PHY EIE status. */
2248 uint64_t eie_det_stl_on_time : 3; /**< [ 7: 5](R/W) EIE detect state machine "on" delay prior to sampling
2249 PHY EIE status. Software needs to set this field to 0x4 if
2250 in SATA mode (GSER()_CFG[SATA] is set). */
2251 uint64_t cfg_eie_det_cnt : 4; /**< [ 11: 8](R/W) EIE detect state machine required number of consecutive
2252 PHY EIE status assertions to determine EIE and assert Raw
2253 PCS output pcs_mac_rx_eie_det_sts. */
2254 uint64_t pcs_rx_mode_ovrrd_en : 1; /**< [ 12: 12](R/W) Override enable for raw PCS RX data width. */
2255 uint64_t pcs_tx_mode_ovrrd_en : 1; /**< [ 13: 13](R/W) Override enable for raw PCS TX data width. */
2256 uint64_t cfg_pcs_loopback : 1; /**< [ 14: 14](R/W) Assert for parallel loopback raw PCS TX to Raw PCS RX. */
2257 uint64_t use_pma_polarity : 1; /**< [ 15: 15](R/W) If set, the PMA control is used to define the polarity.
2258 If not set, GSER()_LANE()_RX_CFG_0[CFG_RX_POL_INVERT]
2259 is used. */
2260 uint64_t reserved_16_63 : 48;
2261 #endif /* Word 0 - End */
2262 } s;
2263 /* struct bdk_gserx_lanex_misc_cfg_0_s cn; */
2264 };
2265 typedef union bdk_gserx_lanex_misc_cfg_0 bdk_gserx_lanex_misc_cfg_0_t;
2266
2267 static inline uint64_t BDK_GSERX_LANEX_MISC_CFG_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_MISC_CFG_0(unsigned long a,unsigned long b)2268 static inline uint64_t BDK_GSERX_LANEX_MISC_CFG_0(unsigned long a, unsigned long b)
2269 {
2270 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2271 return 0x87e0904c0000ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2272 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2273 return 0x87e0904c0000ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2274 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2275 return 0x87e0904c0000ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2276 __bdk_csr_fatal("GSERX_LANEX_MISC_CFG_0", 2, a, b, 0, 0);
2277 }
2278
2279 #define typedef_BDK_GSERX_LANEX_MISC_CFG_0(a,b) bdk_gserx_lanex_misc_cfg_0_t
2280 #define bustype_BDK_GSERX_LANEX_MISC_CFG_0(a,b) BDK_CSR_TYPE_RSL
2281 #define basename_BDK_GSERX_LANEX_MISC_CFG_0(a,b) "GSERX_LANEX_MISC_CFG_0"
2282 #define device_bar_BDK_GSERX_LANEX_MISC_CFG_0(a,b) 0x0 /* PF_BAR0 */
2283 #define busnum_BDK_GSERX_LANEX_MISC_CFG_0(a,b) (a)
2284 #define arguments_BDK_GSERX_LANEX_MISC_CFG_0(a,b) (a),(b),-1,-1
2285
2286 /**
2287 * Register (RSL) gser#_lane#_misc_cfg_1
2288 *
2289 * GSER Lane Miscellaneous Configuration 1 Register
2290 * These registers are for diagnostic use only.
2291 * These registers are reset by hardware only during chip cold reset.
2292 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2293 */
2294 union bdk_gserx_lanex_misc_cfg_1
2295 {
2296 uint64_t u;
2297 struct bdk_gserx_lanex_misc_cfg_1_s
2298 {
2299 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2300 uint64_t reserved_13_63 : 51;
2301 uint64_t par_tx_init : 1; /**< [ 12: 12](R/W) Performs parallel initialization of SerDes interface TX
2302 FIFO pointers. */
2303 uint64_t tx_polarity : 1; /**< [ 11: 11](R/W) Invert polarity of transmitted bit stream. Inversion is
2304 performed in the SerDes interface transmit datapath. */
2305 uint64_t rx_polarity_ovrrd_en : 1; /**< [ 10: 10](R/W) Override mac_pcs_rxX_polarity control pin values
2306 When set, RX polarity inversion is specified from
2307 RX_POLARITY_OVRRD_VAL, and mac_pcs_rxX_polarity is ignored. */
2308 uint64_t rx_polarity_ovrrd_val : 1; /**< [ 9: 9](R/W) Controls RX polarity inversion when RX_POLARITY_OVRRD_EN
2309 is set. Inversion is performed in the SerDes interface receive
2310 datapath. */
2311 uint64_t reserved_2_8 : 7;
2312 uint64_t mac_tx_fifo_rd_ptr_ival : 2;/**< [ 1: 0](R/W/H) Initial value for MAC to PCS TX FIFO read pointer. */
2313 #else /* Word 0 - Little Endian */
2314 uint64_t mac_tx_fifo_rd_ptr_ival : 2;/**< [ 1: 0](R/W/H) Initial value for MAC to PCS TX FIFO read pointer. */
2315 uint64_t reserved_2_8 : 7;
2316 uint64_t rx_polarity_ovrrd_val : 1; /**< [ 9: 9](R/W) Controls RX polarity inversion when RX_POLARITY_OVRRD_EN
2317 is set. Inversion is performed in the SerDes interface receive
2318 datapath. */
2319 uint64_t rx_polarity_ovrrd_en : 1; /**< [ 10: 10](R/W) Override mac_pcs_rxX_polarity control pin values
2320 When set, RX polarity inversion is specified from
2321 RX_POLARITY_OVRRD_VAL, and mac_pcs_rxX_polarity is ignored. */
2322 uint64_t tx_polarity : 1; /**< [ 11: 11](R/W) Invert polarity of transmitted bit stream. Inversion is
2323 performed in the SerDes interface transmit datapath. */
2324 uint64_t par_tx_init : 1; /**< [ 12: 12](R/W) Performs parallel initialization of SerDes interface TX
2325 FIFO pointers. */
2326 uint64_t reserved_13_63 : 51;
2327 #endif /* Word 0 - End */
2328 } s;
2329 /* struct bdk_gserx_lanex_misc_cfg_1_s cn; */
2330 };
2331 typedef union bdk_gserx_lanex_misc_cfg_1 bdk_gserx_lanex_misc_cfg_1_t;
2332
2333 static inline uint64_t BDK_GSERX_LANEX_MISC_CFG_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_MISC_CFG_1(unsigned long a,unsigned long b)2334 static inline uint64_t BDK_GSERX_LANEX_MISC_CFG_1(unsigned long a, unsigned long b)
2335 {
2336 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2337 return 0x87e0904c0008ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2338 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2339 return 0x87e0904c0008ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2340 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2341 return 0x87e0904c0008ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2342 __bdk_csr_fatal("GSERX_LANEX_MISC_CFG_1", 2, a, b, 0, 0);
2343 }
2344
2345 #define typedef_BDK_GSERX_LANEX_MISC_CFG_1(a,b) bdk_gserx_lanex_misc_cfg_1_t
2346 #define bustype_BDK_GSERX_LANEX_MISC_CFG_1(a,b) BDK_CSR_TYPE_RSL
2347 #define basename_BDK_GSERX_LANEX_MISC_CFG_1(a,b) "GSERX_LANEX_MISC_CFG_1"
2348 #define device_bar_BDK_GSERX_LANEX_MISC_CFG_1(a,b) 0x0 /* PF_BAR0 */
2349 #define busnum_BDK_GSERX_LANEX_MISC_CFG_1(a,b) (a)
2350 #define arguments_BDK_GSERX_LANEX_MISC_CFG_1(a,b) (a),(b),-1,-1
2351
2352 /**
2353 * Register (RSL) gser#_lane#_pcs_ctlifc_0
2354 *
2355 * GSER Lane Raw PCS Control Interface Configuration 0 Register
2356 * These registers are for diagnostic use only.
2357 * These registers are reset by hardware only during chip cold reset.
2358 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2359 */
2360 union bdk_gserx_lanex_pcs_ctlifc_0
2361 {
2362 uint64_t u;
2363 struct bdk_gserx_lanex_pcs_ctlifc_0_s
2364 {
2365 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2366 uint64_t reserved_14_63 : 50;
2367 uint64_t cfg_tx_vboost_en_ovrrd_val : 1;/**< [ 13: 13](R/W) Specifies TX VBOOST enable request when its override bit
2368 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_VBOOST_EN_OVRRD_EN]. */
2369 uint64_t cfg_tx_coeff_req_ovrrd_val : 1;/**< [ 12: 12](R/W) Specifies TX coefficient request when its override bit
2370 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_COEFF_REQ_OVRRD_EN].
2371 See GSER()_LANE()_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ]. */
2372 uint64_t cfg_rx_cdr_coast_req_ovrrd_val : 1;/**< [ 11: 11](R/W) Specifies RX CDR coast request when its override bit
2373 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_RX_COAST_REQ_OVRRD_EN]. */
2374 uint64_t cfg_tx_detrx_en_req_ovrrd_val : 1;/**< [ 10: 10](R/W) Specifies TX detect RX request when its override bit
2375 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_DETRX_EN_REQ_OVRRD_EN]. */
2376 uint64_t cfg_soft_reset_req_ovrrd_val : 1;/**< [ 9: 9](R/W) Specifies Soft reset request when its override bit
2377 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_SOFT_RESET_REQ_OVRRD_EN]. */
2378 uint64_t cfg_lane_pwr_off_ovrrd_val : 1;/**< [ 8: 8](R/W) Specifies lane power off reset request when its override bit
2379 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_LANE_PWR_OFF_OVRRD_EN]. */
2380 uint64_t cfg_tx_mode_ovrrd_val : 2; /**< [ 7: 6](R/W) Override PCS TX mode (data width) when its override bit
2381 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_MODE_OVRRD_EN].
2382 0x0 = 8-bit raw data (not supported).
2383 0x1 = 10-bit raw data (not supported).
2384 0x2 = 16-bit raw data (for PCIe Gen3 8Gb only).
2385 0x3 = 20-bit raw data. */
2386 uint64_t cfg_tx_pstate_req_ovrrd_val : 2;/**< [ 5: 4](R/W) Override TX pstate request when its override bit
2387 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_PSTATE_REQ_OVRRD_EN]. */
2388 uint64_t cfg_lane_mode_req_ovrrd_val : 4;/**< [ 3: 0](R/W) Override lane mode request when its override bit
2389 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_LANE_MODE_REQ_OVRRD_EN]. */
2390 #else /* Word 0 - Little Endian */
2391 uint64_t cfg_lane_mode_req_ovrrd_val : 4;/**< [ 3: 0](R/W) Override lane mode request when its override bit
2392 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_LANE_MODE_REQ_OVRRD_EN]. */
2393 uint64_t cfg_tx_pstate_req_ovrrd_val : 2;/**< [ 5: 4](R/W) Override TX pstate request when its override bit
2394 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_PSTATE_REQ_OVRRD_EN]. */
2395 uint64_t cfg_tx_mode_ovrrd_val : 2; /**< [ 7: 6](R/W) Override PCS TX mode (data width) when its override bit
2396 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_MODE_OVRRD_EN].
2397 0x0 = 8-bit raw data (not supported).
2398 0x1 = 10-bit raw data (not supported).
2399 0x2 = 16-bit raw data (for PCIe Gen3 8Gb only).
2400 0x3 = 20-bit raw data. */
2401 uint64_t cfg_lane_pwr_off_ovrrd_val : 1;/**< [ 8: 8](R/W) Specifies lane power off reset request when its override bit
2402 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_LANE_PWR_OFF_OVRRD_EN]. */
2403 uint64_t cfg_soft_reset_req_ovrrd_val : 1;/**< [ 9: 9](R/W) Specifies Soft reset request when its override bit
2404 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_SOFT_RESET_REQ_OVRRD_EN]. */
2405 uint64_t cfg_tx_detrx_en_req_ovrrd_val : 1;/**< [ 10: 10](R/W) Specifies TX detect RX request when its override bit
2406 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_DETRX_EN_REQ_OVRRD_EN]. */
2407 uint64_t cfg_rx_cdr_coast_req_ovrrd_val : 1;/**< [ 11: 11](R/W) Specifies RX CDR coast request when its override bit
2408 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_RX_COAST_REQ_OVRRD_EN]. */
2409 uint64_t cfg_tx_coeff_req_ovrrd_val : 1;/**< [ 12: 12](R/W) Specifies TX coefficient request when its override bit
2410 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_COEFF_REQ_OVRRD_EN].
2411 See GSER()_LANE()_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ]. */
2412 uint64_t cfg_tx_vboost_en_ovrrd_val : 1;/**< [ 13: 13](R/W) Specifies TX VBOOST enable request when its override bit
2413 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_VBOOST_EN_OVRRD_EN]. */
2414 uint64_t reserved_14_63 : 50;
2415 #endif /* Word 0 - End */
2416 } s;
2417 /* struct bdk_gserx_lanex_pcs_ctlifc_0_s cn; */
2418 };
2419 typedef union bdk_gserx_lanex_pcs_ctlifc_0 bdk_gserx_lanex_pcs_ctlifc_0_t;
2420
2421 static inline uint64_t BDK_GSERX_LANEX_PCS_CTLIFC_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_PCS_CTLIFC_0(unsigned long a,unsigned long b)2422 static inline uint64_t BDK_GSERX_LANEX_PCS_CTLIFC_0(unsigned long a, unsigned long b)
2423 {
2424 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2425 return 0x87e0904c0060ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2426 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2427 return 0x87e0904c0060ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2428 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2429 return 0x87e0904c0060ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2430 __bdk_csr_fatal("GSERX_LANEX_PCS_CTLIFC_0", 2, a, b, 0, 0);
2431 }
2432
2433 #define typedef_BDK_GSERX_LANEX_PCS_CTLIFC_0(a,b) bdk_gserx_lanex_pcs_ctlifc_0_t
2434 #define bustype_BDK_GSERX_LANEX_PCS_CTLIFC_0(a,b) BDK_CSR_TYPE_RSL
2435 #define basename_BDK_GSERX_LANEX_PCS_CTLIFC_0(a,b) "GSERX_LANEX_PCS_CTLIFC_0"
2436 #define device_bar_BDK_GSERX_LANEX_PCS_CTLIFC_0(a,b) 0x0 /* PF_BAR0 */
2437 #define busnum_BDK_GSERX_LANEX_PCS_CTLIFC_0(a,b) (a)
2438 #define arguments_BDK_GSERX_LANEX_PCS_CTLIFC_0(a,b) (a),(b),-1,-1
2439
2440 /**
2441 * Register (RSL) gser#_lane#_pcs_ctlifc_1
2442 *
2443 * GSER Lane Raw PCS Control Interface Configuration 1 Register
2444 * These registers are for diagnostic use only.
2445 * These registers are reset by hardware only during chip cold reset.
2446 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2447 */
2448 union bdk_gserx_lanex_pcs_ctlifc_1
2449 {
2450 uint64_t u;
2451 struct bdk_gserx_lanex_pcs_ctlifc_1_s
2452 {
2453 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2454 uint64_t reserved_9_63 : 55;
2455 uint64_t cfg_rx_pstate_req_ovrrd_val : 2;/**< [ 8: 7](R/W) Override RX pstate request when its override bit
2456 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_PSTATE_REQ_OVRRD_EN]. */
2457 uint64_t reserved_2_6 : 5;
2458 uint64_t cfg_rx_mode_ovrrd_val : 2; /**< [ 1: 0](R/W) Override PCS RX mode (data width) when its override bit
2459 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_RX_MODE_OVRRD_EN].
2460 0x0 = 8-bit raw data (not supported).
2461 0x1 = 10-bit raw data (not supported).
2462 0x2 = 16-bit raw data (not supported).
2463 0x3 = 20-bit raw data. */
2464 #else /* Word 0 - Little Endian */
2465 uint64_t cfg_rx_mode_ovrrd_val : 2; /**< [ 1: 0](R/W) Override PCS RX mode (data width) when its override bit
2466 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_RX_MODE_OVRRD_EN].
2467 0x0 = 8-bit raw data (not supported).
2468 0x1 = 10-bit raw data (not supported).
2469 0x2 = 16-bit raw data (not supported).
2470 0x3 = 20-bit raw data. */
2471 uint64_t reserved_2_6 : 5;
2472 uint64_t cfg_rx_pstate_req_ovrrd_val : 2;/**< [ 8: 7](R/W) Override RX pstate request when its override bit
2473 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_PSTATE_REQ_OVRRD_EN]. */
2474 uint64_t reserved_9_63 : 55;
2475 #endif /* Word 0 - End */
2476 } s;
2477 /* struct bdk_gserx_lanex_pcs_ctlifc_1_s cn; */
2478 };
2479 typedef union bdk_gserx_lanex_pcs_ctlifc_1 bdk_gserx_lanex_pcs_ctlifc_1_t;
2480
2481 static inline uint64_t BDK_GSERX_LANEX_PCS_CTLIFC_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_PCS_CTLIFC_1(unsigned long a,unsigned long b)2482 static inline uint64_t BDK_GSERX_LANEX_PCS_CTLIFC_1(unsigned long a, unsigned long b)
2483 {
2484 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2485 return 0x87e0904c0068ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2486 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2487 return 0x87e0904c0068ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2488 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2489 return 0x87e0904c0068ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2490 __bdk_csr_fatal("GSERX_LANEX_PCS_CTLIFC_1", 2, a, b, 0, 0);
2491 }
2492
2493 #define typedef_BDK_GSERX_LANEX_PCS_CTLIFC_1(a,b) bdk_gserx_lanex_pcs_ctlifc_1_t
2494 #define bustype_BDK_GSERX_LANEX_PCS_CTLIFC_1(a,b) BDK_CSR_TYPE_RSL
2495 #define basename_BDK_GSERX_LANEX_PCS_CTLIFC_1(a,b) "GSERX_LANEX_PCS_CTLIFC_1"
2496 #define device_bar_BDK_GSERX_LANEX_PCS_CTLIFC_1(a,b) 0x0 /* PF_BAR0 */
2497 #define busnum_BDK_GSERX_LANEX_PCS_CTLIFC_1(a,b) (a)
2498 #define arguments_BDK_GSERX_LANEX_PCS_CTLIFC_1(a,b) (a),(b),-1,-1
2499
2500 /**
2501 * Register (RSL) gser#_lane#_pcs_ctlifc_2
2502 *
2503 * GSER Lane Raw PCS Control Interface Configuration 2 Register
2504 * These registers are for diagnostic use only.
2505 * These registers are reset by hardware only during chip cold reset.
2506 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2507 */
2508 union bdk_gserx_lanex_pcs_ctlifc_2
2509 {
2510 uint64_t u;
2511 struct bdk_gserx_lanex_pcs_ctlifc_2_s
2512 {
2513 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2514 uint64_t reserved_16_63 : 48;
2515 uint64_t ctlifc_ovrrd_req : 1; /**< [ 15: 15](WO) Writing to set this bit initiates a state machine interface request
2516 for GSER()_LANE()_PCS_CTLIFC_0 and GSER()_LANE()_PCS_CTLIFC_1
2517 override values.
2518
2519 [CTLIFC_OVRRD_REQ] should be written with a one (with
2520 [CFG_TX_COEFF_REQ_OVRRD_EN]=1 and
2521 GSER()_LANE()_PCS_CTLIFC_0[CFG_TX_COEFF_REQ_OVRRD_VAL]=1) to initiate
2522 a control interface configuration over-ride after manually programming
2523 transmitter settings. See GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP]
2524 and GSER()_LANE()_TX_CFG_0[CFG_TX_SWING]. */
2525 uint64_t reserved_9_14 : 6;
2526 uint64_t cfg_tx_vboost_en_ovrrd_en : 1;/**< [ 8: 8](R/W) Override mac_pcs_txX vboost_en signal with the value specified in
2527 GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_VBOOST_EN_OVRRD_VAL]. */
2528 uint64_t cfg_tx_coeff_req_ovrrd_en : 1;/**< [ 7: 7](R/W) Override mac_pcs_txX_coeff_req signal with the value specified in
2529 GSER()_LANE()_PCS_CTLIFC_0[CFG_TX_COEFF_REQ_OVRRD_VAL]. See
2530 [CTLIFC_OVRRD_REQ]. */
2531 uint64_t cfg_rx_cdr_coast_req_ovrrd_en : 1;/**< [ 6: 6](R/W) Override mac_pcs_rxX_cdr_coast signal with the value specified in
2532 GSER()_LANE()_PCS_CTLIFC_2[CFG_RX_COAST_REQ_OVRRD_VAL]. */
2533 uint64_t cfg_tx_detrx_en_req_ovrrd_en : 1;/**< [ 5: 5](R/W) Override mac_pcs_txX_detrx_en signal with the value specified in
2534 GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_DETRX_EN_REQ_OVRRD_VAL]. */
2535 uint64_t cfg_soft_reset_req_ovrrd_en : 1;/**< [ 4: 4](R/W) Override mac_pcs_laneX_soft_rst signal with the value specified in
2536 GSER()_LANE()_PCS_CTLIFC_2[CFG_SOFT_RESET_REQ_OVRRD_VAL]. */
2537 uint64_t cfg_lane_pwr_off_ovrrd_en : 1;/**< [ 3: 3](R/W) Override mac_pcs_laneX_pwr_off signal with the value specified in
2538 GSER()_LANE()_PCS_CTLIFC_2[CFG_LANE_PWR_OFF_OVRRD_VAL]. */
2539 uint64_t cfg_tx_pstate_req_ovrrd_en : 1;/**< [ 2: 2](R/W) Override mac_pcs_txX_pstate[1:0] signal with the value specified in
2540 GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_PSTATE_REQ_OVRRD_VAL].
2541 When using this field to change the TX power state, you must also set
2542 the override enable bits for the lane_mode, soft_reset and lane_pwr_off
2543 fields. The corresponding orrd_val fields should be programmed so as
2544 not to cause undesired changes. */
2545 uint64_t cfg_rx_pstate_req_ovrrd_en : 1;/**< [ 1: 1](R/W) Override mac_pcs_rxX_pstate[1:0] signal with the value specified in
2546 GSER()_LANE()_PCS_CTLIFC_2[CFG_RX_PSTATE_REQ_OVRRD_VAL].
2547 When using this field to change the RX power state, you must also set
2548 the override enable bits for the lane_mode, soft_reset and lane_pwr_off
2549 fields. The corresponding orrd_val fields should be programmed so as
2550 not to cause undesired changes. */
2551 uint64_t cfg_lane_mode_req_ovrrd_en : 1;/**< [ 0: 0](R/W) Override mac_pcs_laneX_mode[3:0] signal with the value specified in
2552 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_LANE_MODE_REQ_OVRRD_VAL]. */
2553 #else /* Word 0 - Little Endian */
2554 uint64_t cfg_lane_mode_req_ovrrd_en : 1;/**< [ 0: 0](R/W) Override mac_pcs_laneX_mode[3:0] signal with the value specified in
2555 is asserted GSER()_LANE()_PCS_CTLIFC_2[CFG_LANE_MODE_REQ_OVRRD_VAL]. */
2556 uint64_t cfg_rx_pstate_req_ovrrd_en : 1;/**< [ 1: 1](R/W) Override mac_pcs_rxX_pstate[1:0] signal with the value specified in
2557 GSER()_LANE()_PCS_CTLIFC_2[CFG_RX_PSTATE_REQ_OVRRD_VAL].
2558 When using this field to change the RX power state, you must also set
2559 the override enable bits for the lane_mode, soft_reset and lane_pwr_off
2560 fields. The corresponding orrd_val fields should be programmed so as
2561 not to cause undesired changes. */
2562 uint64_t cfg_tx_pstate_req_ovrrd_en : 1;/**< [ 2: 2](R/W) Override mac_pcs_txX_pstate[1:0] signal with the value specified in
2563 GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_PSTATE_REQ_OVRRD_VAL].
2564 When using this field to change the TX power state, you must also set
2565 the override enable bits for the lane_mode, soft_reset and lane_pwr_off
2566 fields. The corresponding orrd_val fields should be programmed so as
2567 not to cause undesired changes. */
2568 uint64_t cfg_lane_pwr_off_ovrrd_en : 1;/**< [ 3: 3](R/W) Override mac_pcs_laneX_pwr_off signal with the value specified in
2569 GSER()_LANE()_PCS_CTLIFC_2[CFG_LANE_PWR_OFF_OVRRD_VAL]. */
2570 uint64_t cfg_soft_reset_req_ovrrd_en : 1;/**< [ 4: 4](R/W) Override mac_pcs_laneX_soft_rst signal with the value specified in
2571 GSER()_LANE()_PCS_CTLIFC_2[CFG_SOFT_RESET_REQ_OVRRD_VAL]. */
2572 uint64_t cfg_tx_detrx_en_req_ovrrd_en : 1;/**< [ 5: 5](R/W) Override mac_pcs_txX_detrx_en signal with the value specified in
2573 GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_DETRX_EN_REQ_OVRRD_VAL]. */
2574 uint64_t cfg_rx_cdr_coast_req_ovrrd_en : 1;/**< [ 6: 6](R/W) Override mac_pcs_rxX_cdr_coast signal with the value specified in
2575 GSER()_LANE()_PCS_CTLIFC_2[CFG_RX_COAST_REQ_OVRRD_VAL]. */
2576 uint64_t cfg_tx_coeff_req_ovrrd_en : 1;/**< [ 7: 7](R/W) Override mac_pcs_txX_coeff_req signal with the value specified in
2577 GSER()_LANE()_PCS_CTLIFC_0[CFG_TX_COEFF_REQ_OVRRD_VAL]. See
2578 [CTLIFC_OVRRD_REQ]. */
2579 uint64_t cfg_tx_vboost_en_ovrrd_en : 1;/**< [ 8: 8](R/W) Override mac_pcs_txX vboost_en signal with the value specified in
2580 GSER()_LANE()_PCS_CTLIFC_2[CFG_TX_VBOOST_EN_OVRRD_VAL]. */
2581 uint64_t reserved_9_14 : 6;
2582 uint64_t ctlifc_ovrrd_req : 1; /**< [ 15: 15](WO) Writing to set this bit initiates a state machine interface request
2583 for GSER()_LANE()_PCS_CTLIFC_0 and GSER()_LANE()_PCS_CTLIFC_1
2584 override values.
2585
2586 [CTLIFC_OVRRD_REQ] should be written with a one (with
2587 [CFG_TX_COEFF_REQ_OVRRD_EN]=1 and
2588 GSER()_LANE()_PCS_CTLIFC_0[CFG_TX_COEFF_REQ_OVRRD_VAL]=1) to initiate
2589 a control interface configuration over-ride after manually programming
2590 transmitter settings. See GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP]
2591 and GSER()_LANE()_TX_CFG_0[CFG_TX_SWING]. */
2592 uint64_t reserved_16_63 : 48;
2593 #endif /* Word 0 - End */
2594 } s;
2595 /* struct bdk_gserx_lanex_pcs_ctlifc_2_s cn; */
2596 };
2597 typedef union bdk_gserx_lanex_pcs_ctlifc_2 bdk_gserx_lanex_pcs_ctlifc_2_t;
2598
2599 static inline uint64_t BDK_GSERX_LANEX_PCS_CTLIFC_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_PCS_CTLIFC_2(unsigned long a,unsigned long b)2600 static inline uint64_t BDK_GSERX_LANEX_PCS_CTLIFC_2(unsigned long a, unsigned long b)
2601 {
2602 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2603 return 0x87e0904c0070ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2604 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2605 return 0x87e0904c0070ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2606 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2607 return 0x87e0904c0070ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2608 __bdk_csr_fatal("GSERX_LANEX_PCS_CTLIFC_2", 2, a, b, 0, 0);
2609 }
2610
2611 #define typedef_BDK_GSERX_LANEX_PCS_CTLIFC_2(a,b) bdk_gserx_lanex_pcs_ctlifc_2_t
2612 #define bustype_BDK_GSERX_LANEX_PCS_CTLIFC_2(a,b) BDK_CSR_TYPE_RSL
2613 #define basename_BDK_GSERX_LANEX_PCS_CTLIFC_2(a,b) "GSERX_LANEX_PCS_CTLIFC_2"
2614 #define device_bar_BDK_GSERX_LANEX_PCS_CTLIFC_2(a,b) 0x0 /* PF_BAR0 */
2615 #define busnum_BDK_GSERX_LANEX_PCS_CTLIFC_2(a,b) (a)
2616 #define arguments_BDK_GSERX_LANEX_PCS_CTLIFC_2(a,b) (a),(b),-1,-1
2617
2618 /**
2619 * Register (RSL) gser#_lane#_pcs_macifc_mon_0
2620 *
2621 * GSER Lane MAC to Raw PCS Interface Monitor 0 Register
2622 * These registers are for diagnostic use only.
2623 * These registers are reset by hardware only during chip cold reset.
2624 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2625 */
2626 union bdk_gserx_lanex_pcs_macifc_mon_0
2627 {
2628 uint64_t u;
2629 struct bdk_gserx_lanex_pcs_macifc_mon_0_s
2630 {
2631 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2632 uint64_t reserved_16_63 : 48;
2633 uint64_t mac_pcs_tx_pstate : 2; /**< [ 15: 14](RO/H) Current state of the MAC to PCS TX power state\<2:0\> input.
2634
2635 Internal:
2636 mac_pcs_txX_pstate[2:0]. */
2637 uint64_t mac_pcs_rx_pstate : 2; /**< [ 13: 12](RO/H) Current state of the MAC to PCS RX power state\<2:0\> input.
2638
2639 Internal:
2640 mac_pcs_rxX_pstate[2:0]. */
2641 uint64_t mac_pcs_lane_pwr_off : 1; /**< [ 11: 11](RO/H) Current state of the MAC to PCS lane power off input.
2642 Internal:
2643 mac_pcs_laneX_pwr_off. */
2644 uint64_t reserved_10 : 1;
2645 uint64_t mac_pcs_lane_soft_reset : 1;/**< [ 9: 9](RO/H) Current state of the MAC to PCS soft reset input.
2646 Internal:
2647 mac_pcs_laneX_soft_reset. */
2648 uint64_t mac_pcs_lane_loopbk_en : 1; /**< [ 8: 8](RO/H) Current state of the MAC to PCS lane loopback enable input.
2649 Internal:
2650 mac_pcs_laneX_loopbk_en. */
2651 uint64_t mac_pcs_rx_eie_det_en : 1; /**< [ 7: 7](RO/H) Current state of the MAC to PCS receiver electrical idle exit
2652 detect enable input.
2653
2654 Internal:
2655 mac_pcs_rxX_eie_det_en. */
2656 uint64_t mac_pcs_rx_cdr_coast : 1; /**< [ 6: 6](RO/H) Current state of the MAC to PCS lane receiver CDR coast input.
2657 Internal:
2658 mac_pcs_rxX_cdr_coast. */
2659 uint64_t mac_pcs_tx_detrx_en : 1; /**< [ 5: 5](RO/H) Current state of the MAC to PCS transmitter receiver detect
2660 enable input.
2661
2662 Internal:
2663 mac_pcs_txX_detrx_en. */
2664 uint64_t mac_pcs_rx_eq_eval : 1; /**< [ 4: 4](RO/H) Current state of the MAC to PCS receiver equalizer evaluation
2665 request input.
2666
2667 Internal:
2668 mac_pcs_rxX_eq_eval. */
2669 uint64_t mac_pcs_lane_mode : 4; /**< [ 3: 0](RO/H) Current state of the MAC to PCS lane mode input.
2670 Internal:
2671 mac_pcs_laneX_mode[3:0]. */
2672 #else /* Word 0 - Little Endian */
2673 uint64_t mac_pcs_lane_mode : 4; /**< [ 3: 0](RO/H) Current state of the MAC to PCS lane mode input.
2674 Internal:
2675 mac_pcs_laneX_mode[3:0]. */
2676 uint64_t mac_pcs_rx_eq_eval : 1; /**< [ 4: 4](RO/H) Current state of the MAC to PCS receiver equalizer evaluation
2677 request input.
2678
2679 Internal:
2680 mac_pcs_rxX_eq_eval. */
2681 uint64_t mac_pcs_tx_detrx_en : 1; /**< [ 5: 5](RO/H) Current state of the MAC to PCS transmitter receiver detect
2682 enable input.
2683
2684 Internal:
2685 mac_pcs_txX_detrx_en. */
2686 uint64_t mac_pcs_rx_cdr_coast : 1; /**< [ 6: 6](RO/H) Current state of the MAC to PCS lane receiver CDR coast input.
2687 Internal:
2688 mac_pcs_rxX_cdr_coast. */
2689 uint64_t mac_pcs_rx_eie_det_en : 1; /**< [ 7: 7](RO/H) Current state of the MAC to PCS receiver electrical idle exit
2690 detect enable input.
2691
2692 Internal:
2693 mac_pcs_rxX_eie_det_en. */
2694 uint64_t mac_pcs_lane_loopbk_en : 1; /**< [ 8: 8](RO/H) Current state of the MAC to PCS lane loopback enable input.
2695 Internal:
2696 mac_pcs_laneX_loopbk_en. */
2697 uint64_t mac_pcs_lane_soft_reset : 1;/**< [ 9: 9](RO/H) Current state of the MAC to PCS soft reset input.
2698 Internal:
2699 mac_pcs_laneX_soft_reset. */
2700 uint64_t reserved_10 : 1;
2701 uint64_t mac_pcs_lane_pwr_off : 1; /**< [ 11: 11](RO/H) Current state of the MAC to PCS lane power off input.
2702 Internal:
2703 mac_pcs_laneX_pwr_off. */
2704 uint64_t mac_pcs_rx_pstate : 2; /**< [ 13: 12](RO/H) Current state of the MAC to PCS RX power state\<2:0\> input.
2705
2706 Internal:
2707 mac_pcs_rxX_pstate[2:0]. */
2708 uint64_t mac_pcs_tx_pstate : 2; /**< [ 15: 14](RO/H) Current state of the MAC to PCS TX power state\<2:0\> input.
2709
2710 Internal:
2711 mac_pcs_txX_pstate[2:0]. */
2712 uint64_t reserved_16_63 : 48;
2713 #endif /* Word 0 - End */
2714 } s;
2715 /* struct bdk_gserx_lanex_pcs_macifc_mon_0_s cn; */
2716 };
2717 typedef union bdk_gserx_lanex_pcs_macifc_mon_0 bdk_gserx_lanex_pcs_macifc_mon_0_t;
2718
2719 static inline uint64_t BDK_GSERX_LANEX_PCS_MACIFC_MON_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_PCS_MACIFC_MON_0(unsigned long a,unsigned long b)2720 static inline uint64_t BDK_GSERX_LANEX_PCS_MACIFC_MON_0(unsigned long a, unsigned long b)
2721 {
2722 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2723 return 0x87e0904c0108ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2724 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2725 return 0x87e0904c0108ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2726 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2727 return 0x87e0904c0108ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2728 __bdk_csr_fatal("GSERX_LANEX_PCS_MACIFC_MON_0", 2, a, b, 0, 0);
2729 }
2730
2731 #define typedef_BDK_GSERX_LANEX_PCS_MACIFC_MON_0(a,b) bdk_gserx_lanex_pcs_macifc_mon_0_t
2732 #define bustype_BDK_GSERX_LANEX_PCS_MACIFC_MON_0(a,b) BDK_CSR_TYPE_RSL
2733 #define basename_BDK_GSERX_LANEX_PCS_MACIFC_MON_0(a,b) "GSERX_LANEX_PCS_MACIFC_MON_0"
2734 #define device_bar_BDK_GSERX_LANEX_PCS_MACIFC_MON_0(a,b) 0x0 /* PF_BAR0 */
2735 #define busnum_BDK_GSERX_LANEX_PCS_MACIFC_MON_0(a,b) (a)
2736 #define arguments_BDK_GSERX_LANEX_PCS_MACIFC_MON_0(a,b) (a),(b),-1,-1
2737
2738 /**
2739 * Register (RSL) gser#_lane#_pcs_macifc_mon_2
2740 *
2741 * GSER Lane MAC to Raw PCS Interface Monitor 2 Register
2742 * These registers are for diagnostic use only.
2743 * These registers are reset by hardware only during chip cold reset.
2744 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2745 */
2746 union bdk_gserx_lanex_pcs_macifc_mon_2
2747 {
2748 uint64_t u;
2749 struct bdk_gserx_lanex_pcs_macifc_mon_2_s
2750 {
2751 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2752 uint64_t reserved_16_63 : 48;
2753 uint64_t tx_coeff_req : 1; /**< [ 15: 15](RO/H) Current state of the MAC to PCS TX coefficient request input.
2754 Internal:
2755 mac_pcs_txX_coeff_req. */
2756 uint64_t tx_vboost_en : 1; /**< [ 14: 14](RO/H) Current state of the MAC to PCS TX Vboost enable input.
2757 Internal:
2758 mac_pcs_txX_vboost_en. */
2759 uint64_t tx_swing : 5; /**< [ 13: 9](RO/H) Current state of the MAC to PCS TX equalizer swing\<4:0\> input.
2760
2761 Internal:
2762 mac_pcs_txX_swing[4:0]. */
2763 uint64_t tx_pre : 4; /**< [ 8: 5](RO/H) Current state of the MAC to PCS TX equalizer preemphasis\<3:0\> input.
2764
2765 Internal:
2766 mac_pcs_txX_pre[3:0]. */
2767 uint64_t tx_post : 5; /**< [ 4: 0](RO/H) Current state of the MAC to PCS TX equalizer postemphasis\<4:0\> input.
2768
2769 Internal:
2770 mac_pcs_txX_post[4:0]. */
2771 #else /* Word 0 - Little Endian */
2772 uint64_t tx_post : 5; /**< [ 4: 0](RO/H) Current state of the MAC to PCS TX equalizer postemphasis\<4:0\> input.
2773
2774 Internal:
2775 mac_pcs_txX_post[4:0]. */
2776 uint64_t tx_pre : 4; /**< [ 8: 5](RO/H) Current state of the MAC to PCS TX equalizer preemphasis\<3:0\> input.
2777
2778 Internal:
2779 mac_pcs_txX_pre[3:0]. */
2780 uint64_t tx_swing : 5; /**< [ 13: 9](RO/H) Current state of the MAC to PCS TX equalizer swing\<4:0\> input.
2781
2782 Internal:
2783 mac_pcs_txX_swing[4:0]. */
2784 uint64_t tx_vboost_en : 1; /**< [ 14: 14](RO/H) Current state of the MAC to PCS TX Vboost enable input.
2785 Internal:
2786 mac_pcs_txX_vboost_en. */
2787 uint64_t tx_coeff_req : 1; /**< [ 15: 15](RO/H) Current state of the MAC to PCS TX coefficient request input.
2788 Internal:
2789 mac_pcs_txX_coeff_req. */
2790 uint64_t reserved_16_63 : 48;
2791 #endif /* Word 0 - End */
2792 } s;
2793 /* struct bdk_gserx_lanex_pcs_macifc_mon_2_s cn; */
2794 };
2795 typedef union bdk_gserx_lanex_pcs_macifc_mon_2 bdk_gserx_lanex_pcs_macifc_mon_2_t;
2796
2797 static inline uint64_t BDK_GSERX_LANEX_PCS_MACIFC_MON_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_PCS_MACIFC_MON_2(unsigned long a,unsigned long b)2798 static inline uint64_t BDK_GSERX_LANEX_PCS_MACIFC_MON_2(unsigned long a, unsigned long b)
2799 {
2800 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2801 return 0x87e0904c0118ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2802 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2803 return 0x87e0904c0118ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2804 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2805 return 0x87e0904c0118ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2806 __bdk_csr_fatal("GSERX_LANEX_PCS_MACIFC_MON_2", 2, a, b, 0, 0);
2807 }
2808
2809 #define typedef_BDK_GSERX_LANEX_PCS_MACIFC_MON_2(a,b) bdk_gserx_lanex_pcs_macifc_mon_2_t
2810 #define bustype_BDK_GSERX_LANEX_PCS_MACIFC_MON_2(a,b) BDK_CSR_TYPE_RSL
2811 #define basename_BDK_GSERX_LANEX_PCS_MACIFC_MON_2(a,b) "GSERX_LANEX_PCS_MACIFC_MON_2"
2812 #define device_bar_BDK_GSERX_LANEX_PCS_MACIFC_MON_2(a,b) 0x0 /* PF_BAR0 */
2813 #define busnum_BDK_GSERX_LANEX_PCS_MACIFC_MON_2(a,b) (a)
2814 #define arguments_BDK_GSERX_LANEX_PCS_MACIFC_MON_2(a,b) (a),(b),-1,-1
2815
2816 /**
2817 * Register (RSL) gser#_lane#_pma_loopback_ctrl
2818 *
2819 * GSER Lane PMA Loopback Control Register
2820 * These registers are for diagnostic use only.
2821 * These registers are reset by hardware only during chip cold reset.
2822 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2823 */
2824 union bdk_gserx_lanex_pma_loopback_ctrl
2825 {
2826 uint64_t u;
2827 struct bdk_gserx_lanex_pma_loopback_ctrl_s
2828 {
2829 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2830 uint64_t reserved_2_63 : 62;
2831 uint64_t cfg_ln_lpbk_mode_ovrrd_en : 1;/**< [ 1: 1](R/W) Enable override mac_pcs_loopbk_mode[3:0] with value of FG_LN_LPBK_MODE. */
2832 uint64_t cfg_ln_lpbk_mode : 1; /**< [ 0: 0](R/W) Override value when CFG_LN_LPBK_MODE_OVRRD_EN is set. */
2833 #else /* Word 0 - Little Endian */
2834 uint64_t cfg_ln_lpbk_mode : 1; /**< [ 0: 0](R/W) Override value when CFG_LN_LPBK_MODE_OVRRD_EN is set. */
2835 uint64_t cfg_ln_lpbk_mode_ovrrd_en : 1;/**< [ 1: 1](R/W) Enable override mac_pcs_loopbk_mode[3:0] with value of FG_LN_LPBK_MODE. */
2836 uint64_t reserved_2_63 : 62;
2837 #endif /* Word 0 - End */
2838 } s;
2839 /* struct bdk_gserx_lanex_pma_loopback_ctrl_s cn; */
2840 };
2841 typedef union bdk_gserx_lanex_pma_loopback_ctrl bdk_gserx_lanex_pma_loopback_ctrl_t;
2842
2843 static inline uint64_t BDK_GSERX_LANEX_PMA_LOOPBACK_CTRL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_PMA_LOOPBACK_CTRL(unsigned long a,unsigned long b)2844 static inline uint64_t BDK_GSERX_LANEX_PMA_LOOPBACK_CTRL(unsigned long a, unsigned long b)
2845 {
2846 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2847 return 0x87e0904400d0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2848 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2849 return 0x87e0904400d0ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2850 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2851 return 0x87e0904400d0ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2852 __bdk_csr_fatal("GSERX_LANEX_PMA_LOOPBACK_CTRL", 2, a, b, 0, 0);
2853 }
2854
2855 #define typedef_BDK_GSERX_LANEX_PMA_LOOPBACK_CTRL(a,b) bdk_gserx_lanex_pma_loopback_ctrl_t
2856 #define bustype_BDK_GSERX_LANEX_PMA_LOOPBACK_CTRL(a,b) BDK_CSR_TYPE_RSL
2857 #define basename_BDK_GSERX_LANEX_PMA_LOOPBACK_CTRL(a,b) "GSERX_LANEX_PMA_LOOPBACK_CTRL"
2858 #define device_bar_BDK_GSERX_LANEX_PMA_LOOPBACK_CTRL(a,b) 0x0 /* PF_BAR0 */
2859 #define busnum_BDK_GSERX_LANEX_PMA_LOOPBACK_CTRL(a,b) (a)
2860 #define arguments_BDK_GSERX_LANEX_PMA_LOOPBACK_CTRL(a,b) (a),(b),-1,-1
2861
2862 /**
2863 * Register (RSL) gser#_lane#_pwr_ctrl
2864 *
2865 * GSER Lane Power Control Register
2866 * These registers are for diagnostic use only.
2867 * These registers are reset by hardware only during chip cold reset.
2868 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2869 */
2870 union bdk_gserx_lanex_pwr_ctrl
2871 {
2872 uint64_t u;
2873 struct bdk_gserx_lanex_pwr_ctrl_s
2874 {
2875 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2876 uint64_t reserved_15_63 : 49;
2877 uint64_t tx_sds_fifo_reset_ovrrd_en : 1;/**< [ 14: 14](R/W) When asserted, TX_SDS_FIFO_RESET_OVRRD_VAL is used to specify the value of the reset
2878 signal for the TX FIFO supplying data to the SerDes p2s interface. */
2879 uint64_t tx_sds_fifo_reset_ovrrd_val : 1;/**< [ 13: 13](R/W) When asserted, TX_SDS_FIFO_RESET_OVRRD_EN is asserted, this field is
2880 used to specify the value of the reset
2881 signal for the TX FIFO supplying data to the SerDes p2s interface. */
2882 uint64_t tx_pcs_reset_ovrrd_val : 1; /**< [ 12: 12](R/W) When TX_PCS_RESET_OVRRD_EN is
2883 asserted, this field is used to specify the value of
2884 the reset signal for PCS TX logic. */
2885 uint64_t rx_pcs_reset_ovrrd_val : 1; /**< [ 11: 11](R/W) When RX_PCS_RESET_OVRRD_EN is
2886 asserted, this field is used to specify the value of
2887 the reset signal for PCS RX logic. */
2888 uint64_t reserved_9_10 : 2;
2889 uint64_t rx_resetn_ovrrd_en : 1; /**< [ 8: 8](R/W) Override RX power state machine rx_resetn
2890 control signal. When set, the rx_resetn control signal is taken
2891 from the GSER()_LANE()_RX_CFG_0[RX_RESETN_OVRRD_VAL]
2892 control bit. */
2893 uint64_t rx_resetn_ovrrd_val : 1; /**< [ 7: 7](R/W) Override RX power state machine reset control
2894 signal. When set, reset control signals are specified in
2895 [RX_PCS_RESET_OVRRD_VAL]. */
2896 uint64_t rx_lctrl_ovrrd_en : 1; /**< [ 6: 6](R/W) Override RX power state machine loop control
2897 signals. When set, the loop control settings are
2898 specified in the GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL] field. */
2899 uint64_t rx_lctrl_ovrrd_val : 1; /**< [ 5: 5](R/W) Override RX power state machine power down
2900 control signal. When set, the power down control signal is
2901 specified by GSER()_LANE()_RX_CFG_1[RX_CHPD_OVRRD_VAL]. */
2902 uint64_t tx_tristate_en_ovrrd_en : 1;/**< [ 4: 4](R/W) Override TX power state machine TX tristate
2903 control signal. When set, TX tristate control signal is specified
2904 in GSER()_LANE()_TX_CFG_0[TX_TRISTATE_EN_OVRRD_VAL]. */
2905 uint64_t tx_pcs_reset_ovrrd_en : 1; /**< [ 3: 3](R/W) Override TX power state machine reset control
2906 signal. When set, reset control signals is specified in
2907 [TX_PCS_RESET_OVRRD_VAL]. */
2908 uint64_t tx_elec_idle_ovrrd_en : 1; /**< [ 2: 2](R/W) Override mac_pcs_txX_elec_idle signal
2909 When set, TX electrical idle is controlled from
2910 GSER()_LANE()_TX_CFG_1[TX_ELEC_IDLE_OVRRD_VAL]
2911 mac_pcs_txX_elec_idle signal is ignored. */
2912 uint64_t tx_pd_ovrrd_en : 1; /**< [ 1: 1](R/W) Override TX power state machine TX lane
2913 power-down control signal
2914 When set, TX lane power down is controlled by
2915 GSER()_LANE()_TX_CFG_0[TX_CHPD_OVRRD_VAL]. */
2916 uint64_t tx_p2s_resetn_ovrrd_en : 1; /**< [ 0: 0](R/W) Override TX power state machine TX reset
2917 control signal
2918 When set, TX reset is controlled by
2919 GSER()_LANE()_TX_CFG_0[TX_RESETN_OVRRD_VAL]. */
2920 #else /* Word 0 - Little Endian */
2921 uint64_t tx_p2s_resetn_ovrrd_en : 1; /**< [ 0: 0](R/W) Override TX power state machine TX reset
2922 control signal
2923 When set, TX reset is controlled by
2924 GSER()_LANE()_TX_CFG_0[TX_RESETN_OVRRD_VAL]. */
2925 uint64_t tx_pd_ovrrd_en : 1; /**< [ 1: 1](R/W) Override TX power state machine TX lane
2926 power-down control signal
2927 When set, TX lane power down is controlled by
2928 GSER()_LANE()_TX_CFG_0[TX_CHPD_OVRRD_VAL]. */
2929 uint64_t tx_elec_idle_ovrrd_en : 1; /**< [ 2: 2](R/W) Override mac_pcs_txX_elec_idle signal
2930 When set, TX electrical idle is controlled from
2931 GSER()_LANE()_TX_CFG_1[TX_ELEC_IDLE_OVRRD_VAL]
2932 mac_pcs_txX_elec_idle signal is ignored. */
2933 uint64_t tx_pcs_reset_ovrrd_en : 1; /**< [ 3: 3](R/W) Override TX power state machine reset control
2934 signal. When set, reset control signals is specified in
2935 [TX_PCS_RESET_OVRRD_VAL]. */
2936 uint64_t tx_tristate_en_ovrrd_en : 1;/**< [ 4: 4](R/W) Override TX power state machine TX tristate
2937 control signal. When set, TX tristate control signal is specified
2938 in GSER()_LANE()_TX_CFG_0[TX_TRISTATE_EN_OVRRD_VAL]. */
2939 uint64_t rx_lctrl_ovrrd_val : 1; /**< [ 5: 5](R/W) Override RX power state machine power down
2940 control signal. When set, the power down control signal is
2941 specified by GSER()_LANE()_RX_CFG_1[RX_CHPD_OVRRD_VAL]. */
2942 uint64_t rx_lctrl_ovrrd_en : 1; /**< [ 6: 6](R/W) Override RX power state machine loop control
2943 signals. When set, the loop control settings are
2944 specified in the GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL] field. */
2945 uint64_t rx_resetn_ovrrd_val : 1; /**< [ 7: 7](R/W) Override RX power state machine reset control
2946 signal. When set, reset control signals are specified in
2947 [RX_PCS_RESET_OVRRD_VAL]. */
2948 uint64_t rx_resetn_ovrrd_en : 1; /**< [ 8: 8](R/W) Override RX power state machine rx_resetn
2949 control signal. When set, the rx_resetn control signal is taken
2950 from the GSER()_LANE()_RX_CFG_0[RX_RESETN_OVRRD_VAL]
2951 control bit. */
2952 uint64_t reserved_9_10 : 2;
2953 uint64_t rx_pcs_reset_ovrrd_val : 1; /**< [ 11: 11](R/W) When RX_PCS_RESET_OVRRD_EN is
2954 asserted, this field is used to specify the value of
2955 the reset signal for PCS RX logic. */
2956 uint64_t tx_pcs_reset_ovrrd_val : 1; /**< [ 12: 12](R/W) When TX_PCS_RESET_OVRRD_EN is
2957 asserted, this field is used to specify the value of
2958 the reset signal for PCS TX logic. */
2959 uint64_t tx_sds_fifo_reset_ovrrd_val : 1;/**< [ 13: 13](R/W) When asserted, TX_SDS_FIFO_RESET_OVRRD_EN is asserted, this field is
2960 used to specify the value of the reset
2961 signal for the TX FIFO supplying data to the SerDes p2s interface. */
2962 uint64_t tx_sds_fifo_reset_ovrrd_en : 1;/**< [ 14: 14](R/W) When asserted, TX_SDS_FIFO_RESET_OVRRD_VAL is used to specify the value of the reset
2963 signal for the TX FIFO supplying data to the SerDes p2s interface. */
2964 uint64_t reserved_15_63 : 49;
2965 #endif /* Word 0 - End */
2966 } s;
2967 /* struct bdk_gserx_lanex_pwr_ctrl_s cn; */
2968 };
2969 typedef union bdk_gserx_lanex_pwr_ctrl bdk_gserx_lanex_pwr_ctrl_t;
2970
2971 static inline uint64_t BDK_GSERX_LANEX_PWR_CTRL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_PWR_CTRL(unsigned long a,unsigned long b)2972 static inline uint64_t BDK_GSERX_LANEX_PWR_CTRL(unsigned long a, unsigned long b)
2973 {
2974 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
2975 return 0x87e0904400d8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
2976 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
2977 return 0x87e0904400d8ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
2978 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
2979 return 0x87e0904400d8ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
2980 __bdk_csr_fatal("GSERX_LANEX_PWR_CTRL", 2, a, b, 0, 0);
2981 }
2982
2983 #define typedef_BDK_GSERX_LANEX_PWR_CTRL(a,b) bdk_gserx_lanex_pwr_ctrl_t
2984 #define bustype_BDK_GSERX_LANEX_PWR_CTRL(a,b) BDK_CSR_TYPE_RSL
2985 #define basename_BDK_GSERX_LANEX_PWR_CTRL(a,b) "GSERX_LANEX_PWR_CTRL"
2986 #define device_bar_BDK_GSERX_LANEX_PWR_CTRL(a,b) 0x0 /* PF_BAR0 */
2987 #define busnum_BDK_GSERX_LANEX_PWR_CTRL(a,b) (a)
2988 #define arguments_BDK_GSERX_LANEX_PWR_CTRL(a,b) (a),(b),-1,-1
2989
2990 /**
2991 * Register (RSL) gser#_lane#_rx_aeq_out_0
2992 *
2993 * GSER Lane SerDes RX Adaptive Equalizer 0 Register
2994 * These registers are for diagnostic use only.
2995 * These registers are reset by hardware only during chip cold reset.
2996 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
2997 */
2998 union bdk_gserx_lanex_rx_aeq_out_0
2999 {
3000 uint64_t u;
3001 struct bdk_gserx_lanex_rx_aeq_out_0_s
3002 {
3003 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3004 uint64_t reserved_10_63 : 54;
3005 uint64_t sds_pcs_rx_aeq_out : 10; /**< [ 9: 0](RO/H) \<9:5\>: DFE TAP5.
3006 \<4:0\>: DFE TAP4. */
3007 #else /* Word 0 - Little Endian */
3008 uint64_t sds_pcs_rx_aeq_out : 10; /**< [ 9: 0](RO/H) \<9:5\>: DFE TAP5.
3009 \<4:0\>: DFE TAP4. */
3010 uint64_t reserved_10_63 : 54;
3011 #endif /* Word 0 - End */
3012 } s;
3013 /* struct bdk_gserx_lanex_rx_aeq_out_0_s cn; */
3014 };
3015 typedef union bdk_gserx_lanex_rx_aeq_out_0 bdk_gserx_lanex_rx_aeq_out_0_t;
3016
3017 static inline uint64_t BDK_GSERX_LANEX_RX_AEQ_OUT_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_AEQ_OUT_0(unsigned long a,unsigned long b)3018 static inline uint64_t BDK_GSERX_LANEX_RX_AEQ_OUT_0(unsigned long a, unsigned long b)
3019 {
3020 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3021 return 0x87e090440280ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3022 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3023 return 0x87e090440280ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3024 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3025 return 0x87e090440280ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3026 __bdk_csr_fatal("GSERX_LANEX_RX_AEQ_OUT_0", 2, a, b, 0, 0);
3027 }
3028
3029 #define typedef_BDK_GSERX_LANEX_RX_AEQ_OUT_0(a,b) bdk_gserx_lanex_rx_aeq_out_0_t
3030 #define bustype_BDK_GSERX_LANEX_RX_AEQ_OUT_0(a,b) BDK_CSR_TYPE_RSL
3031 #define basename_BDK_GSERX_LANEX_RX_AEQ_OUT_0(a,b) "GSERX_LANEX_RX_AEQ_OUT_0"
3032 #define device_bar_BDK_GSERX_LANEX_RX_AEQ_OUT_0(a,b) 0x0 /* PF_BAR0 */
3033 #define busnum_BDK_GSERX_LANEX_RX_AEQ_OUT_0(a,b) (a)
3034 #define arguments_BDK_GSERX_LANEX_RX_AEQ_OUT_0(a,b) (a),(b),-1,-1
3035
3036 /**
3037 * Register (RSL) gser#_lane#_rx_aeq_out_1
3038 *
3039 * GSER Lane SerDes RX Adaptive Equalizer 1 Register
3040 * These registers are for diagnostic use only.
3041 * These registers are reset by hardware only during chip cold reset.
3042 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3043 */
3044 union bdk_gserx_lanex_rx_aeq_out_1
3045 {
3046 uint64_t u;
3047 struct bdk_gserx_lanex_rx_aeq_out_1_s
3048 {
3049 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3050 uint64_t reserved_15_63 : 49;
3051 uint64_t sds_pcs_rx_aeq_out : 15; /**< [ 14: 0](RO/H) \<14:10\> = DFE TAP3.
3052 \<9:5\> = DFE TAP2.
3053 \<4:0\> = DFE TAP1. */
3054 #else /* Word 0 - Little Endian */
3055 uint64_t sds_pcs_rx_aeq_out : 15; /**< [ 14: 0](RO/H) \<14:10\> = DFE TAP3.
3056 \<9:5\> = DFE TAP2.
3057 \<4:0\> = DFE TAP1. */
3058 uint64_t reserved_15_63 : 49;
3059 #endif /* Word 0 - End */
3060 } s;
3061 /* struct bdk_gserx_lanex_rx_aeq_out_1_s cn; */
3062 };
3063 typedef union bdk_gserx_lanex_rx_aeq_out_1 bdk_gserx_lanex_rx_aeq_out_1_t;
3064
3065 static inline uint64_t BDK_GSERX_LANEX_RX_AEQ_OUT_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_AEQ_OUT_1(unsigned long a,unsigned long b)3066 static inline uint64_t BDK_GSERX_LANEX_RX_AEQ_OUT_1(unsigned long a, unsigned long b)
3067 {
3068 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3069 return 0x87e090440288ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3070 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3071 return 0x87e090440288ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3072 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3073 return 0x87e090440288ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3074 __bdk_csr_fatal("GSERX_LANEX_RX_AEQ_OUT_1", 2, a, b, 0, 0);
3075 }
3076
3077 #define typedef_BDK_GSERX_LANEX_RX_AEQ_OUT_1(a,b) bdk_gserx_lanex_rx_aeq_out_1_t
3078 #define bustype_BDK_GSERX_LANEX_RX_AEQ_OUT_1(a,b) BDK_CSR_TYPE_RSL
3079 #define basename_BDK_GSERX_LANEX_RX_AEQ_OUT_1(a,b) "GSERX_LANEX_RX_AEQ_OUT_1"
3080 #define device_bar_BDK_GSERX_LANEX_RX_AEQ_OUT_1(a,b) 0x0 /* PF_BAR0 */
3081 #define busnum_BDK_GSERX_LANEX_RX_AEQ_OUT_1(a,b) (a)
3082 #define arguments_BDK_GSERX_LANEX_RX_AEQ_OUT_1(a,b) (a),(b),-1,-1
3083
3084 /**
3085 * Register (RSL) gser#_lane#_rx_aeq_out_2
3086 *
3087 * GSER Lane SerDes RX Adaptive Equalizer 2 Register
3088 * These registers are for diagnostic use only.
3089 * These registers are reset by hardware only during chip cold reset.
3090 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3091 */
3092 union bdk_gserx_lanex_rx_aeq_out_2
3093 {
3094 uint64_t u;
3095 struct bdk_gserx_lanex_rx_aeq_out_2_s
3096 {
3097 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3098 uint64_t reserved_15_63 : 49;
3099 uint64_t sds_pcs_rx_aeq_out : 15; /**< [ 14: 0](RO/H) \<9:8\> = Reserved.
3100 \<7:4\> = Pre-CTLE gain.
3101 \<3:0\> = Post-CTLE gain. */
3102 #else /* Word 0 - Little Endian */
3103 uint64_t sds_pcs_rx_aeq_out : 15; /**< [ 14: 0](RO/H) \<9:8\> = Reserved.
3104 \<7:4\> = Pre-CTLE gain.
3105 \<3:0\> = Post-CTLE gain. */
3106 uint64_t reserved_15_63 : 49;
3107 #endif /* Word 0 - End */
3108 } s;
3109 /* struct bdk_gserx_lanex_rx_aeq_out_2_s cn; */
3110 };
3111 typedef union bdk_gserx_lanex_rx_aeq_out_2 bdk_gserx_lanex_rx_aeq_out_2_t;
3112
3113 static inline uint64_t BDK_GSERX_LANEX_RX_AEQ_OUT_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_AEQ_OUT_2(unsigned long a,unsigned long b)3114 static inline uint64_t BDK_GSERX_LANEX_RX_AEQ_OUT_2(unsigned long a, unsigned long b)
3115 {
3116 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3117 return 0x87e090440290ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3118 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3119 return 0x87e090440290ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3120 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3121 return 0x87e090440290ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3122 __bdk_csr_fatal("GSERX_LANEX_RX_AEQ_OUT_2", 2, a, b, 0, 0);
3123 }
3124
3125 #define typedef_BDK_GSERX_LANEX_RX_AEQ_OUT_2(a,b) bdk_gserx_lanex_rx_aeq_out_2_t
3126 #define bustype_BDK_GSERX_LANEX_RX_AEQ_OUT_2(a,b) BDK_CSR_TYPE_RSL
3127 #define basename_BDK_GSERX_LANEX_RX_AEQ_OUT_2(a,b) "GSERX_LANEX_RX_AEQ_OUT_2"
3128 #define device_bar_BDK_GSERX_LANEX_RX_AEQ_OUT_2(a,b) 0x0 /* PF_BAR0 */
3129 #define busnum_BDK_GSERX_LANEX_RX_AEQ_OUT_2(a,b) (a)
3130 #define arguments_BDK_GSERX_LANEX_RX_AEQ_OUT_2(a,b) (a),(b),-1,-1
3131
3132 /**
3133 * Register (RSL) gser#_lane#_rx_cdr_ctrl_1
3134 *
3135 * GSER Lane SerDes RX CDR Control 1 Register
3136 * These registers are for diagnostic use only.
3137 * These registers are reset by hardware only during chip cold reset.
3138 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3139 */
3140 union bdk_gserx_lanex_rx_cdr_ctrl_1
3141 {
3142 uint64_t u;
3143 struct bdk_gserx_lanex_rx_cdr_ctrl_1_s
3144 {
3145 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3146 uint64_t reserved_16_63 : 48;
3147 uint64_t cfg_rx_cdr_ctrl_ovrrd_val : 16;/**< [ 15: 0](R/W) Set CFG_RX_CDR_CTRL_OVRRD_EN in register
3148 GSER()_LANE()_RX_MISC_OVRRD to override pcs_sds_rx_cdr_ctrl.
3149 \<15:13\> = CDR frequency gain.
3150 \<12\> = Frequency accumulator manual enable.
3151 \<11:5\> = Frequency accumulator manual value.
3152 \<4\> = CDR phase offset override enable.
3153 \<3:0\> = CDR phase offset override, DLL IQ. */
3154 #else /* Word 0 - Little Endian */
3155 uint64_t cfg_rx_cdr_ctrl_ovrrd_val : 16;/**< [ 15: 0](R/W) Set CFG_RX_CDR_CTRL_OVRRD_EN in register
3156 GSER()_LANE()_RX_MISC_OVRRD to override pcs_sds_rx_cdr_ctrl.
3157 \<15:13\> = CDR frequency gain.
3158 \<12\> = Frequency accumulator manual enable.
3159 \<11:5\> = Frequency accumulator manual value.
3160 \<4\> = CDR phase offset override enable.
3161 \<3:0\> = CDR phase offset override, DLL IQ. */
3162 uint64_t reserved_16_63 : 48;
3163 #endif /* Word 0 - End */
3164 } s;
3165 /* struct bdk_gserx_lanex_rx_cdr_ctrl_1_s cn; */
3166 };
3167 typedef union bdk_gserx_lanex_rx_cdr_ctrl_1 bdk_gserx_lanex_rx_cdr_ctrl_1_t;
3168
3169 static inline uint64_t BDK_GSERX_LANEX_RX_CDR_CTRL_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CDR_CTRL_1(unsigned long a,unsigned long b)3170 static inline uint64_t BDK_GSERX_LANEX_RX_CDR_CTRL_1(unsigned long a, unsigned long b)
3171 {
3172 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3173 return 0x87e090440038ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3174 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3175 return 0x87e090440038ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3176 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3177 return 0x87e090440038ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3178 __bdk_csr_fatal("GSERX_LANEX_RX_CDR_CTRL_1", 2, a, b, 0, 0);
3179 }
3180
3181 #define typedef_BDK_GSERX_LANEX_RX_CDR_CTRL_1(a,b) bdk_gserx_lanex_rx_cdr_ctrl_1_t
3182 #define bustype_BDK_GSERX_LANEX_RX_CDR_CTRL_1(a,b) BDK_CSR_TYPE_RSL
3183 #define basename_BDK_GSERX_LANEX_RX_CDR_CTRL_1(a,b) "GSERX_LANEX_RX_CDR_CTRL_1"
3184 #define device_bar_BDK_GSERX_LANEX_RX_CDR_CTRL_1(a,b) 0x0 /* PF_BAR0 */
3185 #define busnum_BDK_GSERX_LANEX_RX_CDR_CTRL_1(a,b) (a)
3186 #define arguments_BDK_GSERX_LANEX_RX_CDR_CTRL_1(a,b) (a),(b),-1,-1
3187
3188 /**
3189 * Register (RSL) gser#_lane#_rx_cdr_ctrl_2
3190 *
3191 * GSER Lane SerDes RX CDR Control 2 Register
3192 * These registers are for diagnostic use only.
3193 * These registers are reset by hardware only during chip cold reset.
3194 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3195 */
3196 union bdk_gserx_lanex_rx_cdr_ctrl_2
3197 {
3198 uint64_t u;
3199 struct bdk_gserx_lanex_rx_cdr_ctrl_2_s
3200 {
3201 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3202 uint64_t reserved_16_63 : 48;
3203 uint64_t cfg_rx_cdr_ctrl_ovrrd_val : 16;/**< [ 15: 0](R/W) Set CFG_RX_CDR_CTRL_OVRRD_EN in register
3204 GSER()_LANE()_RX_MISC_OVRRD to override pcs_sds_rx_cdr_ctrl.
3205 \<15\> = Shadow PI phase enable.
3206 \<14:8\> = Shadow PI phase value.
3207 \<7\> = CDR manual phase enable.
3208 \<6:0\> = CDR manual phase value. */
3209 #else /* Word 0 - Little Endian */
3210 uint64_t cfg_rx_cdr_ctrl_ovrrd_val : 16;/**< [ 15: 0](R/W) Set CFG_RX_CDR_CTRL_OVRRD_EN in register
3211 GSER()_LANE()_RX_MISC_OVRRD to override pcs_sds_rx_cdr_ctrl.
3212 \<15\> = Shadow PI phase enable.
3213 \<14:8\> = Shadow PI phase value.
3214 \<7\> = CDR manual phase enable.
3215 \<6:0\> = CDR manual phase value. */
3216 uint64_t reserved_16_63 : 48;
3217 #endif /* Word 0 - End */
3218 } s;
3219 /* struct bdk_gserx_lanex_rx_cdr_ctrl_2_s cn; */
3220 };
3221 typedef union bdk_gserx_lanex_rx_cdr_ctrl_2 bdk_gserx_lanex_rx_cdr_ctrl_2_t;
3222
3223 static inline uint64_t BDK_GSERX_LANEX_RX_CDR_CTRL_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CDR_CTRL_2(unsigned long a,unsigned long b)3224 static inline uint64_t BDK_GSERX_LANEX_RX_CDR_CTRL_2(unsigned long a, unsigned long b)
3225 {
3226 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3227 return 0x87e090440040ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3228 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3229 return 0x87e090440040ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3230 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3231 return 0x87e090440040ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3232 __bdk_csr_fatal("GSERX_LANEX_RX_CDR_CTRL_2", 2, a, b, 0, 0);
3233 }
3234
3235 #define typedef_BDK_GSERX_LANEX_RX_CDR_CTRL_2(a,b) bdk_gserx_lanex_rx_cdr_ctrl_2_t
3236 #define bustype_BDK_GSERX_LANEX_RX_CDR_CTRL_2(a,b) BDK_CSR_TYPE_RSL
3237 #define basename_BDK_GSERX_LANEX_RX_CDR_CTRL_2(a,b) "GSERX_LANEX_RX_CDR_CTRL_2"
3238 #define device_bar_BDK_GSERX_LANEX_RX_CDR_CTRL_2(a,b) 0x0 /* PF_BAR0 */
3239 #define busnum_BDK_GSERX_LANEX_RX_CDR_CTRL_2(a,b) (a)
3240 #define arguments_BDK_GSERX_LANEX_RX_CDR_CTRL_2(a,b) (a),(b),-1,-1
3241
3242 /**
3243 * Register (RSL) gser#_lane#_rx_cdr_misc_ctrl_0
3244 *
3245 * GSER Lane SerDes RX CDR Miscellaneous Control 0 Register
3246 * These registers are for diagnostic use only.
3247 * These registers are reset by hardware only during chip cold reset.
3248 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3249 */
3250 union bdk_gserx_lanex_rx_cdr_misc_ctrl_0
3251 {
3252 uint64_t u;
3253 struct bdk_gserx_lanex_rx_cdr_misc_ctrl_0_s
3254 {
3255 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3256 uint64_t reserved_8_63 : 56;
3257 uint64_t pcs_sds_rx_cdr_misc_ctrl : 8;/**< [ 7: 0](R/W) Per lane RX miscellaneous CDR control:
3258 \<7\> = RT-Eyemon counter enable, will start counting 5.4e9 bits.
3259 \<6\> = RT-Eyemon shadow PI control enable.
3260 \<5:4\> = RT-Eyemon error counter byte selection observable on
3261 SDS_OCS_RX_CDR_STATUS[14:7] in register GSER_LANE_RX_CDR_STATUS_1.
3262 \<3:0\> = LBW adjustment thresholds. */
3263 #else /* Word 0 - Little Endian */
3264 uint64_t pcs_sds_rx_cdr_misc_ctrl : 8;/**< [ 7: 0](R/W) Per lane RX miscellaneous CDR control:
3265 \<7\> = RT-Eyemon counter enable, will start counting 5.4e9 bits.
3266 \<6\> = RT-Eyemon shadow PI control enable.
3267 \<5:4\> = RT-Eyemon error counter byte selection observable on
3268 SDS_OCS_RX_CDR_STATUS[14:7] in register GSER_LANE_RX_CDR_STATUS_1.
3269 \<3:0\> = LBW adjustment thresholds. */
3270 uint64_t reserved_8_63 : 56;
3271 #endif /* Word 0 - End */
3272 } s;
3273 struct bdk_gserx_lanex_rx_cdr_misc_ctrl_0_cn
3274 {
3275 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3276 uint64_t reserved_16_63 : 48;
3277 uint64_t reserved_8_15 : 8;
3278 uint64_t pcs_sds_rx_cdr_misc_ctrl : 8;/**< [ 7: 0](R/W) Per lane RX miscellaneous CDR control:
3279 \<7\> = RT-Eyemon counter enable, will start counting 5.4e9 bits.
3280 \<6\> = RT-Eyemon shadow PI control enable.
3281 \<5:4\> = RT-Eyemon error counter byte selection observable on
3282 SDS_OCS_RX_CDR_STATUS[14:7] in register GSER_LANE_RX_CDR_STATUS_1.
3283 \<3:0\> = LBW adjustment thresholds. */
3284 #else /* Word 0 - Little Endian */
3285 uint64_t pcs_sds_rx_cdr_misc_ctrl : 8;/**< [ 7: 0](R/W) Per lane RX miscellaneous CDR control:
3286 \<7\> = RT-Eyemon counter enable, will start counting 5.4e9 bits.
3287 \<6\> = RT-Eyemon shadow PI control enable.
3288 \<5:4\> = RT-Eyemon error counter byte selection observable on
3289 SDS_OCS_RX_CDR_STATUS[14:7] in register GSER_LANE_RX_CDR_STATUS_1.
3290 \<3:0\> = LBW adjustment thresholds. */
3291 uint64_t reserved_8_15 : 8;
3292 uint64_t reserved_16_63 : 48;
3293 #endif /* Word 0 - End */
3294 } cn;
3295 };
3296 typedef union bdk_gserx_lanex_rx_cdr_misc_ctrl_0 bdk_gserx_lanex_rx_cdr_misc_ctrl_0_t;
3297
3298 static inline uint64_t BDK_GSERX_LANEX_RX_CDR_MISC_CTRL_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CDR_MISC_CTRL_0(unsigned long a,unsigned long b)3299 static inline uint64_t BDK_GSERX_LANEX_RX_CDR_MISC_CTRL_0(unsigned long a, unsigned long b)
3300 {
3301 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3302 return 0x87e090440208ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3303 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3304 return 0x87e090440208ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3305 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3306 return 0x87e090440208ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3307 __bdk_csr_fatal("GSERX_LANEX_RX_CDR_MISC_CTRL_0", 2, a, b, 0, 0);
3308 }
3309
3310 #define typedef_BDK_GSERX_LANEX_RX_CDR_MISC_CTRL_0(a,b) bdk_gserx_lanex_rx_cdr_misc_ctrl_0_t
3311 #define bustype_BDK_GSERX_LANEX_RX_CDR_MISC_CTRL_0(a,b) BDK_CSR_TYPE_RSL
3312 #define basename_BDK_GSERX_LANEX_RX_CDR_MISC_CTRL_0(a,b) "GSERX_LANEX_RX_CDR_MISC_CTRL_0"
3313 #define device_bar_BDK_GSERX_LANEX_RX_CDR_MISC_CTRL_0(a,b) 0x0 /* PF_BAR0 */
3314 #define busnum_BDK_GSERX_LANEX_RX_CDR_MISC_CTRL_0(a,b) (a)
3315 #define arguments_BDK_GSERX_LANEX_RX_CDR_MISC_CTRL_0(a,b) (a),(b),-1,-1
3316
3317 /**
3318 * Register (RSL) gser#_lane#_rx_cdr_status_1
3319 *
3320 * GSER Lane SerDes RX CDR Status 1 Register
3321 * These registers are for diagnostic use only.
3322 * These registers are reset by hardware only during chip cold reset.
3323 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3324 */
3325 union bdk_gserx_lanex_rx_cdr_status_1
3326 {
3327 uint64_t u;
3328 struct bdk_gserx_lanex_rx_cdr_status_1_s
3329 {
3330 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3331 uint64_t reserved_15_63 : 49;
3332 uint64_t sds_pcs_rx_cdr_status : 15; /**< [ 14: 0](RO/H) Per lane RX CDR status:
3333 \<14:7\> = RT-Eyemon error counter.
3334 \<6:4\> = LBW adjustment value.
3335 \<3:0\> = LBW adjustment state. */
3336 #else /* Word 0 - Little Endian */
3337 uint64_t sds_pcs_rx_cdr_status : 15; /**< [ 14: 0](RO/H) Per lane RX CDR status:
3338 \<14:7\> = RT-Eyemon error counter.
3339 \<6:4\> = LBW adjustment value.
3340 \<3:0\> = LBW adjustment state. */
3341 uint64_t reserved_15_63 : 49;
3342 #endif /* Word 0 - End */
3343 } s;
3344 struct bdk_gserx_lanex_rx_cdr_status_1_cn
3345 {
3346 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3347 uint64_t reserved_16_63 : 48;
3348 uint64_t reserved_15 : 1;
3349 uint64_t sds_pcs_rx_cdr_status : 15; /**< [ 14: 0](RO/H) Per lane RX CDR status:
3350 \<14:7\> = RT-Eyemon error counter.
3351 \<6:4\> = LBW adjustment value.
3352 \<3:0\> = LBW adjustment state. */
3353 #else /* Word 0 - Little Endian */
3354 uint64_t sds_pcs_rx_cdr_status : 15; /**< [ 14: 0](RO/H) Per lane RX CDR status:
3355 \<14:7\> = RT-Eyemon error counter.
3356 \<6:4\> = LBW adjustment value.
3357 \<3:0\> = LBW adjustment state. */
3358 uint64_t reserved_15 : 1;
3359 uint64_t reserved_16_63 : 48;
3360 #endif /* Word 0 - End */
3361 } cn;
3362 };
3363 typedef union bdk_gserx_lanex_rx_cdr_status_1 bdk_gserx_lanex_rx_cdr_status_1_t;
3364
3365 static inline uint64_t BDK_GSERX_LANEX_RX_CDR_STATUS_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CDR_STATUS_1(unsigned long a,unsigned long b)3366 static inline uint64_t BDK_GSERX_LANEX_RX_CDR_STATUS_1(unsigned long a, unsigned long b)
3367 {
3368 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3369 return 0x87e0904402d0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3370 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3371 return 0x87e0904402d0ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3372 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3373 return 0x87e0904402d0ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3374 __bdk_csr_fatal("GSERX_LANEX_RX_CDR_STATUS_1", 2, a, b, 0, 0);
3375 }
3376
3377 #define typedef_BDK_GSERX_LANEX_RX_CDR_STATUS_1(a,b) bdk_gserx_lanex_rx_cdr_status_1_t
3378 #define bustype_BDK_GSERX_LANEX_RX_CDR_STATUS_1(a,b) BDK_CSR_TYPE_RSL
3379 #define basename_BDK_GSERX_LANEX_RX_CDR_STATUS_1(a,b) "GSERX_LANEX_RX_CDR_STATUS_1"
3380 #define device_bar_BDK_GSERX_LANEX_RX_CDR_STATUS_1(a,b) 0x0 /* PF_BAR0 */
3381 #define busnum_BDK_GSERX_LANEX_RX_CDR_STATUS_1(a,b) (a)
3382 #define arguments_BDK_GSERX_LANEX_RX_CDR_STATUS_1(a,b) (a),(b),-1,-1
3383
3384 /**
3385 * Register (RSL) gser#_lane#_rx_cdr_status_2
3386 *
3387 * GSER Lane SerDes RX CDR Status 2 Register
3388 * These registers are for diagnostic use only.
3389 * These registers are reset by hardware only during chip cold reset.
3390 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3391 */
3392 union bdk_gserx_lanex_rx_cdr_status_2
3393 {
3394 uint64_t u;
3395 struct bdk_gserx_lanex_rx_cdr_status_2_s
3396 {
3397 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3398 uint64_t reserved_14_63 : 50;
3399 uint64_t sds_pcs_rx_cdr_status : 14; /**< [ 13: 0](RO/H) CDR status.
3400 \<13:7\> = CDR phase control output.
3401 \<6:0\> = CDR frequency accumulator output. */
3402 #else /* Word 0 - Little Endian */
3403 uint64_t sds_pcs_rx_cdr_status : 14; /**< [ 13: 0](RO/H) CDR status.
3404 \<13:7\> = CDR phase control output.
3405 \<6:0\> = CDR frequency accumulator output. */
3406 uint64_t reserved_14_63 : 50;
3407 #endif /* Word 0 - End */
3408 } s;
3409 /* struct bdk_gserx_lanex_rx_cdr_status_2_s cn; */
3410 };
3411 typedef union bdk_gserx_lanex_rx_cdr_status_2 bdk_gserx_lanex_rx_cdr_status_2_t;
3412
3413 static inline uint64_t BDK_GSERX_LANEX_RX_CDR_STATUS_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CDR_STATUS_2(unsigned long a,unsigned long b)3414 static inline uint64_t BDK_GSERX_LANEX_RX_CDR_STATUS_2(unsigned long a, unsigned long b)
3415 {
3416 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3417 return 0x87e0904402d8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3418 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3419 return 0x87e0904402d8ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3420 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3421 return 0x87e0904402d8ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3422 __bdk_csr_fatal("GSERX_LANEX_RX_CDR_STATUS_2", 2, a, b, 0, 0);
3423 }
3424
3425 #define typedef_BDK_GSERX_LANEX_RX_CDR_STATUS_2(a,b) bdk_gserx_lanex_rx_cdr_status_2_t
3426 #define bustype_BDK_GSERX_LANEX_RX_CDR_STATUS_2(a,b) BDK_CSR_TYPE_RSL
3427 #define basename_BDK_GSERX_LANEX_RX_CDR_STATUS_2(a,b) "GSERX_LANEX_RX_CDR_STATUS_2"
3428 #define device_bar_BDK_GSERX_LANEX_RX_CDR_STATUS_2(a,b) 0x0 /* PF_BAR0 */
3429 #define busnum_BDK_GSERX_LANEX_RX_CDR_STATUS_2(a,b) (a)
3430 #define arguments_BDK_GSERX_LANEX_RX_CDR_STATUS_2(a,b) (a),(b),-1,-1
3431
3432 /**
3433 * Register (RSL) gser#_lane#_rx_cfg_0
3434 *
3435 * GSER Lane SerDes RX Configuration 0 Register
3436 * These registers are for diagnostic use only.
3437 * These registers are reset by hardware only during chip cold reset.
3438 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3439 */
3440 union bdk_gserx_lanex_rx_cfg_0
3441 {
3442 uint64_t u;
3443 struct bdk_gserx_lanex_rx_cfg_0_s
3444 {
3445 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3446 uint64_t reserved_16_63 : 48;
3447 uint64_t rx_datarate_ovrrd_en : 1; /**< [ 15: 15](R/W) Override enable for RX power state machine data rate signal. */
3448 uint64_t pcs_sds_rx_tristate_enable : 1;/**< [ 14: 14](R/W) RX termination high-Z enable. */
3449 uint64_t rx_resetn_ovrrd_val : 1; /**< [ 13: 13](R/W) This value overrides the RX power state machine rx_resetn control
3450 signal when GSER()_LANE()_PWR_CTRL[RX_RESETN_OVRRD_EN] is set. */
3451 uint64_t pcs_sds_rx_eyemon_en : 1; /**< [ 12: 12](R/W) RX eyemon test enable. */
3452 uint64_t pcs_sds_rx_pcm_ctrl : 4; /**< [ 11: 8](R/W) \<11\>: Reserved.
3453 \<10-8\>:
3454 0x0 = 540mV.
3455 0x1 = 540mV + 20mV.
3456 0x2-0x3 = Reserved.
3457 0x4 = 100-620mV (default).
3458 0x5-0x7 = Reserved. */
3459 uint64_t rx_datarate_ovrrd_val : 2; /**< [ 7: 6](R/W) Specifies the data rate when RX_DATARATE_OVRRD_EN is asserted:
3460 0x0 = Full rate.
3461 0x1 = 1/2 data rate.
3462 0x2 = 1/4 data rate.
3463 0x3 = 1/8 data rate. */
3464 uint64_t cfg_rx_pol_invert : 1; /**< [ 5: 5](R/W) Invert the receive data. Allies with GSER()_LANE()_MISC_CFG_0[USE_PMA_POLARITY]
3465 is deasserted. */
3466 uint64_t rx_subblk_pd_ovrrd_val : 5; /**< [ 4: 0](R/W) Not supported. */
3467 #else /* Word 0 - Little Endian */
3468 uint64_t rx_subblk_pd_ovrrd_val : 5; /**< [ 4: 0](R/W) Not supported. */
3469 uint64_t cfg_rx_pol_invert : 1; /**< [ 5: 5](R/W) Invert the receive data. Allies with GSER()_LANE()_MISC_CFG_0[USE_PMA_POLARITY]
3470 is deasserted. */
3471 uint64_t rx_datarate_ovrrd_val : 2; /**< [ 7: 6](R/W) Specifies the data rate when RX_DATARATE_OVRRD_EN is asserted:
3472 0x0 = Full rate.
3473 0x1 = 1/2 data rate.
3474 0x2 = 1/4 data rate.
3475 0x3 = 1/8 data rate. */
3476 uint64_t pcs_sds_rx_pcm_ctrl : 4; /**< [ 11: 8](R/W) \<11\>: Reserved.
3477 \<10-8\>:
3478 0x0 = 540mV.
3479 0x1 = 540mV + 20mV.
3480 0x2-0x3 = Reserved.
3481 0x4 = 100-620mV (default).
3482 0x5-0x7 = Reserved. */
3483 uint64_t pcs_sds_rx_eyemon_en : 1; /**< [ 12: 12](R/W) RX eyemon test enable. */
3484 uint64_t rx_resetn_ovrrd_val : 1; /**< [ 13: 13](R/W) This value overrides the RX power state machine rx_resetn control
3485 signal when GSER()_LANE()_PWR_CTRL[RX_RESETN_OVRRD_EN] is set. */
3486 uint64_t pcs_sds_rx_tristate_enable : 1;/**< [ 14: 14](R/W) RX termination high-Z enable. */
3487 uint64_t rx_datarate_ovrrd_en : 1; /**< [ 15: 15](R/W) Override enable for RX power state machine data rate signal. */
3488 uint64_t reserved_16_63 : 48;
3489 #endif /* Word 0 - End */
3490 } s;
3491 /* struct bdk_gserx_lanex_rx_cfg_0_s cn; */
3492 };
3493 typedef union bdk_gserx_lanex_rx_cfg_0 bdk_gserx_lanex_rx_cfg_0_t;
3494
3495 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CFG_0(unsigned long a,unsigned long b)3496 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_0(unsigned long a, unsigned long b)
3497 {
3498 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3499 return 0x87e090440000ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3500 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3501 return 0x87e090440000ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3502 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3503 return 0x87e090440000ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3504 __bdk_csr_fatal("GSERX_LANEX_RX_CFG_0", 2, a, b, 0, 0);
3505 }
3506
3507 #define typedef_BDK_GSERX_LANEX_RX_CFG_0(a,b) bdk_gserx_lanex_rx_cfg_0_t
3508 #define bustype_BDK_GSERX_LANEX_RX_CFG_0(a,b) BDK_CSR_TYPE_RSL
3509 #define basename_BDK_GSERX_LANEX_RX_CFG_0(a,b) "GSERX_LANEX_RX_CFG_0"
3510 #define device_bar_BDK_GSERX_LANEX_RX_CFG_0(a,b) 0x0 /* PF_BAR0 */
3511 #define busnum_BDK_GSERX_LANEX_RX_CFG_0(a,b) (a)
3512 #define arguments_BDK_GSERX_LANEX_RX_CFG_0(a,b) (a),(b),-1,-1
3513
3514 /**
3515 * Register (RSL) gser#_lane#_rx_cfg_1
3516 *
3517 * GSER Lane SerDes RX Configuration 1 Register
3518 * These registers are for diagnostic use only.
3519 * These registers are reset by hardware only during chip cold reset.
3520 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3521 */
3522 union bdk_gserx_lanex_rx_cfg_1
3523 {
3524 uint64_t u;
3525 struct bdk_gserx_lanex_rx_cfg_1_s
3526 {
3527 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3528 uint64_t reserved_16_63 : 48;
3529 uint64_t rx_chpd_ovrrd_val : 1; /**< [ 15: 15](R/W) Not supported. */
3530 uint64_t pcs_sds_rx_os_men : 1; /**< [ 14: 14](R/W) RX offset manual enable. */
3531 uint64_t eie_en_ovrrd_en : 1; /**< [ 13: 13](R/W) Override enable for electrical-idle-exit circuit. */
3532 uint64_t eie_en_ovrrd_val : 1; /**< [ 12: 12](R/W) Override value for electrical-idle-exit circuit. */
3533 uint64_t reserved_11 : 1;
3534 uint64_t rx_pcie_mode_ovrrd_en : 1; /**< [ 10: 10](R/W) Override enable for RX_PCIE_MODE_OVRRD_VAL. */
3535 uint64_t rx_pcie_mode_ovrrd_val : 1; /**< [ 9: 9](R/W) Override value for RX_PCIE_MODE_OVRRD_VAL;
3536 selects between RX terminations.
3537 0x0 = pcs_sds_rx_terminate_to_vdda.
3538 0x1 = VDDA. */
3539 uint64_t cfg_rx_dll_locken : 1; /**< [ 8: 8](R/W) Enable DLL lock when GSER()_LANE()_RX_MISC_OVRRD[CFG_RX_DLL_LOCKEN_OVRRD_EN] is asserted. */
3540 uint64_t pcs_sds_rx_cdr_ssc_mode : 8;/**< [ 7: 0](R/W) Per-lane RX CDR SSC control:
3541 \<7:4\> = Reserved.
3542 \<3\> = Clean SSC error flag.
3543 \<2\> = Disable SSC filter.
3544 \<1\> = Enable SSC value usage.
3545 \<0\> = Reserved. */
3546 #else /* Word 0 - Little Endian */
3547 uint64_t pcs_sds_rx_cdr_ssc_mode : 8;/**< [ 7: 0](R/W) Per-lane RX CDR SSC control:
3548 \<7:4\> = Reserved.
3549 \<3\> = Clean SSC error flag.
3550 \<2\> = Disable SSC filter.
3551 \<1\> = Enable SSC value usage.
3552 \<0\> = Reserved. */
3553 uint64_t cfg_rx_dll_locken : 1; /**< [ 8: 8](R/W) Enable DLL lock when GSER()_LANE()_RX_MISC_OVRRD[CFG_RX_DLL_LOCKEN_OVRRD_EN] is asserted. */
3554 uint64_t rx_pcie_mode_ovrrd_val : 1; /**< [ 9: 9](R/W) Override value for RX_PCIE_MODE_OVRRD_VAL;
3555 selects between RX terminations.
3556 0x0 = pcs_sds_rx_terminate_to_vdda.
3557 0x1 = VDDA. */
3558 uint64_t rx_pcie_mode_ovrrd_en : 1; /**< [ 10: 10](R/W) Override enable for RX_PCIE_MODE_OVRRD_VAL. */
3559 uint64_t reserved_11 : 1;
3560 uint64_t eie_en_ovrrd_val : 1; /**< [ 12: 12](R/W) Override value for electrical-idle-exit circuit. */
3561 uint64_t eie_en_ovrrd_en : 1; /**< [ 13: 13](R/W) Override enable for electrical-idle-exit circuit. */
3562 uint64_t pcs_sds_rx_os_men : 1; /**< [ 14: 14](R/W) RX offset manual enable. */
3563 uint64_t rx_chpd_ovrrd_val : 1; /**< [ 15: 15](R/W) Not supported. */
3564 uint64_t reserved_16_63 : 48;
3565 #endif /* Word 0 - End */
3566 } s;
3567 /* struct bdk_gserx_lanex_rx_cfg_1_s cn; */
3568 };
3569 typedef union bdk_gserx_lanex_rx_cfg_1 bdk_gserx_lanex_rx_cfg_1_t;
3570
3571 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CFG_1(unsigned long a,unsigned long b)3572 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_1(unsigned long a, unsigned long b)
3573 {
3574 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3575 return 0x87e090440008ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3576 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3577 return 0x87e090440008ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3578 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3579 return 0x87e090440008ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3580 __bdk_csr_fatal("GSERX_LANEX_RX_CFG_1", 2, a, b, 0, 0);
3581 }
3582
3583 #define typedef_BDK_GSERX_LANEX_RX_CFG_1(a,b) bdk_gserx_lanex_rx_cfg_1_t
3584 #define bustype_BDK_GSERX_LANEX_RX_CFG_1(a,b) BDK_CSR_TYPE_RSL
3585 #define basename_BDK_GSERX_LANEX_RX_CFG_1(a,b) "GSERX_LANEX_RX_CFG_1"
3586 #define device_bar_BDK_GSERX_LANEX_RX_CFG_1(a,b) 0x0 /* PF_BAR0 */
3587 #define busnum_BDK_GSERX_LANEX_RX_CFG_1(a,b) (a)
3588 #define arguments_BDK_GSERX_LANEX_RX_CFG_1(a,b) (a),(b),-1,-1
3589
3590 /**
3591 * Register (RSL) gser#_lane#_rx_cfg_2
3592 *
3593 * GSER Lane SerDes RX Configuration 2 Register
3594 * These registers are for diagnostic use only.
3595 * These registers are reset by hardware only during chip cold reset.
3596 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3597 */
3598 union bdk_gserx_lanex_rx_cfg_2
3599 {
3600 uint64_t u;
3601 struct bdk_gserx_lanex_rx_cfg_2_s
3602 {
3603 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3604 uint64_t reserved_15_63 : 49;
3605 uint64_t pcs_sds_rx_terminate_to_vdda : 1;/**< [ 14: 14](R/W) RX termination control:
3606 0 = Floating.
3607 1 = Terminate to sds_vdda. */
3608 uint64_t pcs_sds_rx_sampler_boost : 2;/**< [ 13: 12](R/W) Controls amount of boost.
3609 Note that this control can negatively impact reliability. */
3610 uint64_t pcs_sds_rx_sampler_boost_en : 1;/**< [ 11: 11](R/W) Faster sampler c2q.
3611 For diagnostic use only. */
3612 uint64_t reserved_10 : 1;
3613 uint64_t rx_sds_rx_agc_mval : 10; /**< [ 9: 0](R/W) AGC manual value used when
3614 GSER()_LANE()_RX_CFG_5[RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL]
3615 are set.
3616
3617 \<9:8\>: Reserved.
3618
3619 \<7:4\>: Pre-CTLE (continuous time linear equalizer) gain (steps of approximately 0.75dB):
3620 _ 0x0 = -6dB.
3621 _ 0x1 = -5dB.
3622 _ 0xF = +5dB.
3623
3624 \<3:0\>: Post-CTLE gain (steps of 0.0875):
3625 _ 0x0 = lowest.
3626 _ 0xF = lowest * 2.3125.
3627
3628 Recommended settings:
3629
3630 When auto-negotiated link training is not present (e.g. BGX) and link speed \<
3631 5 Gbaud, pre-CTLE, post-CTLE, and peaking control settings should be manually
3632 configured. GSER()_LANE()_RX_CFG_5[RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL]
3633 should both be set, [RX_SDS_RX_AGC_MVAL] has the pre and post settings,
3634 and GSER()_LANE()_RX_CTLE_CTRL[PCS_SDS_RX_CTLE_ZERO] controls equalizer
3635 peaking.
3636
3637 The [RX_SDS_RX_AGC_MVAL] settings should be derived from signal integrity
3638 simulations with the IBIS-AMI model supplied by Cavium when
3639 GSER()_LANE()_RX_CFG_5[RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL] are set.
3640
3641 Internal:
3642 reset value may be reasonable default settings. */
3643 #else /* Word 0 - Little Endian */
3644 uint64_t rx_sds_rx_agc_mval : 10; /**< [ 9: 0](R/W) AGC manual value used when
3645 GSER()_LANE()_RX_CFG_5[RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL]
3646 are set.
3647
3648 \<9:8\>: Reserved.
3649
3650 \<7:4\>: Pre-CTLE (continuous time linear equalizer) gain (steps of approximately 0.75dB):
3651 _ 0x0 = -6dB.
3652 _ 0x1 = -5dB.
3653 _ 0xF = +5dB.
3654
3655 \<3:0\>: Post-CTLE gain (steps of 0.0875):
3656 _ 0x0 = lowest.
3657 _ 0xF = lowest * 2.3125.
3658
3659 Recommended settings:
3660
3661 When auto-negotiated link training is not present (e.g. BGX) and link speed \<
3662 5 Gbaud, pre-CTLE, post-CTLE, and peaking control settings should be manually
3663 configured. GSER()_LANE()_RX_CFG_5[RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL]
3664 should both be set, [RX_SDS_RX_AGC_MVAL] has the pre and post settings,
3665 and GSER()_LANE()_RX_CTLE_CTRL[PCS_SDS_RX_CTLE_ZERO] controls equalizer
3666 peaking.
3667
3668 The [RX_SDS_RX_AGC_MVAL] settings should be derived from signal integrity
3669 simulations with the IBIS-AMI model supplied by Cavium when
3670 GSER()_LANE()_RX_CFG_5[RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL] are set.
3671
3672 Internal:
3673 reset value may be reasonable default settings. */
3674 uint64_t reserved_10 : 1;
3675 uint64_t pcs_sds_rx_sampler_boost_en : 1;/**< [ 11: 11](R/W) Faster sampler c2q.
3676 For diagnostic use only. */
3677 uint64_t pcs_sds_rx_sampler_boost : 2;/**< [ 13: 12](R/W) Controls amount of boost.
3678 Note that this control can negatively impact reliability. */
3679 uint64_t pcs_sds_rx_terminate_to_vdda : 1;/**< [ 14: 14](R/W) RX termination control:
3680 0 = Floating.
3681 1 = Terminate to sds_vdda. */
3682 uint64_t reserved_15_63 : 49;
3683 #endif /* Word 0 - End */
3684 } s;
3685 /* struct bdk_gserx_lanex_rx_cfg_2_s cn; */
3686 };
3687 typedef union bdk_gserx_lanex_rx_cfg_2 bdk_gserx_lanex_rx_cfg_2_t;
3688
3689 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CFG_2(unsigned long a,unsigned long b)3690 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_2(unsigned long a, unsigned long b)
3691 {
3692 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3693 return 0x87e090440010ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3694 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3695 return 0x87e090440010ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3696 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3697 return 0x87e090440010ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3698 __bdk_csr_fatal("GSERX_LANEX_RX_CFG_2", 2, a, b, 0, 0);
3699 }
3700
3701 #define typedef_BDK_GSERX_LANEX_RX_CFG_2(a,b) bdk_gserx_lanex_rx_cfg_2_t
3702 #define bustype_BDK_GSERX_LANEX_RX_CFG_2(a,b) BDK_CSR_TYPE_RSL
3703 #define basename_BDK_GSERX_LANEX_RX_CFG_2(a,b) "GSERX_LANEX_RX_CFG_2"
3704 #define device_bar_BDK_GSERX_LANEX_RX_CFG_2(a,b) 0x0 /* PF_BAR0 */
3705 #define busnum_BDK_GSERX_LANEX_RX_CFG_2(a,b) (a)
3706 #define arguments_BDK_GSERX_LANEX_RX_CFG_2(a,b) (a),(b),-1,-1
3707
3708 /**
3709 * Register (RSL) gser#_lane#_rx_cfg_3
3710 *
3711 * GSER Lane SerDes RX Configuration 3 Register
3712 * These registers are for diagnostic use only.
3713 * These registers are reset by hardware only during chip cold reset.
3714 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3715 */
3716 union bdk_gserx_lanex_rx_cfg_3
3717 {
3718 uint64_t u;
3719 struct bdk_gserx_lanex_rx_cfg_3_s
3720 {
3721 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3722 uint64_t reserved_16_63 : 48;
3723 uint64_t cfg_rx_errdet_ctrl : 16; /**< [ 15: 0](R/W) RX adaptive equalizer control.
3724 Value of pcs_sds_rx_err_det_ctrl when
3725 GSER()_LANE()_RX_MISC_OVRRD[CFG_RS_ERRDET_CTRL_OVRRD_EN}
3726 is set.
3727
3728 \<15:13\>: Starting delta (6.7mV/step, 13.4mV + 6.7mV*N).
3729
3730 \<12:10\>: Minimum delta to adapt to (6.7mV/step, 13.4mV + 6.7mV*N).
3731
3732 \<9:7\>: Window mode (PM) delta (6.7mV/step, 13.4mV + 6.7mV*N).
3733
3734 \<6\>: Enable DFE for edge samplers.
3735
3736 \<5:4\>: Edge sampler DEF alpha:
3737 0x0 = 1/4.
3738 0x1 = 1/2.
3739 0x2 = 3/4.
3740 0x3 = 1.
3741
3742 \<3:0\>: Q/QB error sampler 1 threshold, 6.7mV/step. */
3743 #else /* Word 0 - Little Endian */
3744 uint64_t cfg_rx_errdet_ctrl : 16; /**< [ 15: 0](R/W) RX adaptive equalizer control.
3745 Value of pcs_sds_rx_err_det_ctrl when
3746 GSER()_LANE()_RX_MISC_OVRRD[CFG_RS_ERRDET_CTRL_OVRRD_EN}
3747 is set.
3748
3749 \<15:13\>: Starting delta (6.7mV/step, 13.4mV + 6.7mV*N).
3750
3751 \<12:10\>: Minimum delta to adapt to (6.7mV/step, 13.4mV + 6.7mV*N).
3752
3753 \<9:7\>: Window mode (PM) delta (6.7mV/step, 13.4mV + 6.7mV*N).
3754
3755 \<6\>: Enable DFE for edge samplers.
3756
3757 \<5:4\>: Edge sampler DEF alpha:
3758 0x0 = 1/4.
3759 0x1 = 1/2.
3760 0x2 = 3/4.
3761 0x3 = 1.
3762
3763 \<3:0\>: Q/QB error sampler 1 threshold, 6.7mV/step. */
3764 uint64_t reserved_16_63 : 48;
3765 #endif /* Word 0 - End */
3766 } s;
3767 /* struct bdk_gserx_lanex_rx_cfg_3_s cn; */
3768 };
3769 typedef union bdk_gserx_lanex_rx_cfg_3 bdk_gserx_lanex_rx_cfg_3_t;
3770
3771 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_3(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CFG_3(unsigned long a,unsigned long b)3772 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_3(unsigned long a, unsigned long b)
3773 {
3774 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3775 return 0x87e090440018ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3776 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3777 return 0x87e090440018ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3778 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3779 return 0x87e090440018ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3780 __bdk_csr_fatal("GSERX_LANEX_RX_CFG_3", 2, a, b, 0, 0);
3781 }
3782
3783 #define typedef_BDK_GSERX_LANEX_RX_CFG_3(a,b) bdk_gserx_lanex_rx_cfg_3_t
3784 #define bustype_BDK_GSERX_LANEX_RX_CFG_3(a,b) BDK_CSR_TYPE_RSL
3785 #define basename_BDK_GSERX_LANEX_RX_CFG_3(a,b) "GSERX_LANEX_RX_CFG_3"
3786 #define device_bar_BDK_GSERX_LANEX_RX_CFG_3(a,b) 0x0 /* PF_BAR0 */
3787 #define busnum_BDK_GSERX_LANEX_RX_CFG_3(a,b) (a)
3788 #define arguments_BDK_GSERX_LANEX_RX_CFG_3(a,b) (a),(b),-1,-1
3789
3790 /**
3791 * Register (RSL) gser#_lane#_rx_cfg_4
3792 *
3793 * GSER Lane SerDes RX Configuration 4 Register
3794 * These registers are for diagnostic use only.
3795 * These registers are reset by hardware only during chip cold reset.
3796 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3797 */
3798 union bdk_gserx_lanex_rx_cfg_4
3799 {
3800 uint64_t u;
3801 struct bdk_gserx_lanex_rx_cfg_4_s
3802 {
3803 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3804 uint64_t reserved_16_63 : 48;
3805 uint64_t cfg_rx_errdet_ctrl : 16; /**< [ 15: 0](R/W) RX adaptive equalizer control.
3806 Value of pcs_sds_rx_err_det_ctrl when
3807 GSER()_LANE()_RX_MISC_OVRRD[CFG_RS_ERRDET_CTRL_OVRRD_EN] is set.
3808
3809 \<15:14\>: Reserved.
3810
3811 \<13:8\>: Q/QB error sampler 0 threshold, 6.7mV/step, used for training/LMS.
3812
3813 \<7\>: Enable Window mode, after training has finished.
3814
3815 \<6:5\>: Control sds_pcs_rx_vma_status[15:8].
3816
3817 0x0 = window counter[19:12] (FOM).
3818 0x1 = window counter[11:4].
3819 0x2 = CTLE pole, SDLL_IQ.
3820 0x3 = pre-CTLE gain, CTLE peak.
3821
3822 \<4\>: Offset cancellation enable.
3823
3824 \<3:0\>: Max CTLE peak setting during training when pcs_sds_rx_vma_ctl[7] is set in
3825 GSER()_LANE()_RX_VMA_CTRL. */
3826 #else /* Word 0 - Little Endian */
3827 uint64_t cfg_rx_errdet_ctrl : 16; /**< [ 15: 0](R/W) RX adaptive equalizer control.
3828 Value of pcs_sds_rx_err_det_ctrl when
3829 GSER()_LANE()_RX_MISC_OVRRD[CFG_RS_ERRDET_CTRL_OVRRD_EN] is set.
3830
3831 \<15:14\>: Reserved.
3832
3833 \<13:8\>: Q/QB error sampler 0 threshold, 6.7mV/step, used for training/LMS.
3834
3835 \<7\>: Enable Window mode, after training has finished.
3836
3837 \<6:5\>: Control sds_pcs_rx_vma_status[15:8].
3838
3839 0x0 = window counter[19:12] (FOM).
3840 0x1 = window counter[11:4].
3841 0x2 = CTLE pole, SDLL_IQ.
3842 0x3 = pre-CTLE gain, CTLE peak.
3843
3844 \<4\>: Offset cancellation enable.
3845
3846 \<3:0\>: Max CTLE peak setting during training when pcs_sds_rx_vma_ctl[7] is set in
3847 GSER()_LANE()_RX_VMA_CTRL. */
3848 uint64_t reserved_16_63 : 48;
3849 #endif /* Word 0 - End */
3850 } s;
3851 /* struct bdk_gserx_lanex_rx_cfg_4_s cn; */
3852 };
3853 typedef union bdk_gserx_lanex_rx_cfg_4 bdk_gserx_lanex_rx_cfg_4_t;
3854
3855 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_4(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CFG_4(unsigned long a,unsigned long b)3856 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_4(unsigned long a, unsigned long b)
3857 {
3858 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3859 return 0x87e090440020ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3860 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3861 return 0x87e090440020ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3862 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3863 return 0x87e090440020ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3864 __bdk_csr_fatal("GSERX_LANEX_RX_CFG_4", 2, a, b, 0, 0);
3865 }
3866
3867 #define typedef_BDK_GSERX_LANEX_RX_CFG_4(a,b) bdk_gserx_lanex_rx_cfg_4_t
3868 #define bustype_BDK_GSERX_LANEX_RX_CFG_4(a,b) BDK_CSR_TYPE_RSL
3869 #define basename_BDK_GSERX_LANEX_RX_CFG_4(a,b) "GSERX_LANEX_RX_CFG_4"
3870 #define device_bar_BDK_GSERX_LANEX_RX_CFG_4(a,b) 0x0 /* PF_BAR0 */
3871 #define busnum_BDK_GSERX_LANEX_RX_CFG_4(a,b) (a)
3872 #define arguments_BDK_GSERX_LANEX_RX_CFG_4(a,b) (a),(b),-1,-1
3873
3874 /**
3875 * Register (RSL) gser#_lane#_rx_cfg_5
3876 *
3877 * GSER Lane SerDes RX Configuration 5 Register
3878 * These registers are for diagnostic use only.
3879 * These registers are reset by hardware only during chip cold reset.
3880 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
3881 */
3882 union bdk_gserx_lanex_rx_cfg_5
3883 {
3884 uint64_t u;
3885 struct bdk_gserx_lanex_rx_cfg_5_s
3886 {
3887 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3888 uint64_t reserved_5_63 : 59;
3889 uint64_t rx_agc_men_ovrrd_en : 1; /**< [ 4: 4](R/W) Override enable for AGC manual mode.
3890
3891 Recommended settings:
3892
3893 When auto-negotiated link training is not present (e.g. BGX) and link speed \<
3894 5 Gbaud, pre-CTLE, post-CTLE, and peaking control settings should be manually
3895 configured. [RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL] should both be set,
3896 GSER()_LANE()_RX_CFG_2[RX_SDS_RX_AGC_MVAL] has the pre and post settings,
3897 and GSER()_LANE()_RX_CTLE_CTRL[PCS_SDS_RX_CTLE_ZERO] controls equalizer
3898 peaking. */
3899 uint64_t rx_agc_men_ovrrd_val : 1; /**< [ 3: 3](R/W) Override value for AGC manual mode.
3900
3901 Recommended settings:
3902
3903 When auto-negotiated link training is not present (e.g. BGX) and link speed \<
3904 5 Gbaud, pre-CTLE, post-CTLE, and peaking control settings should be manually
3905 configured. [RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL] should both be set,
3906 GSER()_LANE()_RX_CFG_2[RX_SDS_RX_AGC_MVAL] has the pre and post settings,
3907 and GSER()_LANE()_RX_CTLE_CTRL[PCS_SDS_RX_CTLE_ZERO] controls equalizer
3908 peaking. */
3909 uint64_t rx_widthsel_ovrrd_en : 1; /**< [ 2: 2](R/W) Override enable for RX width select to the SerDes pcs_sds_rx_widthsel. */
3910 uint64_t rx_widthsel_ovrrd_val : 2; /**< [ 1: 0](R/W) Override value for RX width select to the SerDes pcs_sds_rx_widthsel.
3911 0x0 = 8-bit raw data.
3912 0x1 = 10-bit raw data.
3913 0x2 = 16-bit raw data.
3914 0x3 = 20-bit raw data. */
3915 #else /* Word 0 - Little Endian */
3916 uint64_t rx_widthsel_ovrrd_val : 2; /**< [ 1: 0](R/W) Override value for RX width select to the SerDes pcs_sds_rx_widthsel.
3917 0x0 = 8-bit raw data.
3918 0x1 = 10-bit raw data.
3919 0x2 = 16-bit raw data.
3920 0x3 = 20-bit raw data. */
3921 uint64_t rx_widthsel_ovrrd_en : 1; /**< [ 2: 2](R/W) Override enable for RX width select to the SerDes pcs_sds_rx_widthsel. */
3922 uint64_t rx_agc_men_ovrrd_val : 1; /**< [ 3: 3](R/W) Override value for AGC manual mode.
3923
3924 Recommended settings:
3925
3926 When auto-negotiated link training is not present (e.g. BGX) and link speed \<
3927 5 Gbaud, pre-CTLE, post-CTLE, and peaking control settings should be manually
3928 configured. [RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL] should both be set,
3929 GSER()_LANE()_RX_CFG_2[RX_SDS_RX_AGC_MVAL] has the pre and post settings,
3930 and GSER()_LANE()_RX_CTLE_CTRL[PCS_SDS_RX_CTLE_ZERO] controls equalizer
3931 peaking. */
3932 uint64_t rx_agc_men_ovrrd_en : 1; /**< [ 4: 4](R/W) Override enable for AGC manual mode.
3933
3934 Recommended settings:
3935
3936 When auto-negotiated link training is not present (e.g. BGX) and link speed \<
3937 5 Gbaud, pre-CTLE, post-CTLE, and peaking control settings should be manually
3938 configured. [RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL] should both be set,
3939 GSER()_LANE()_RX_CFG_2[RX_SDS_RX_AGC_MVAL] has the pre and post settings,
3940 and GSER()_LANE()_RX_CTLE_CTRL[PCS_SDS_RX_CTLE_ZERO] controls equalizer
3941 peaking. */
3942 uint64_t reserved_5_63 : 59;
3943 #endif /* Word 0 - End */
3944 } s;
3945 /* struct bdk_gserx_lanex_rx_cfg_5_s cn; */
3946 };
3947 typedef union bdk_gserx_lanex_rx_cfg_5 bdk_gserx_lanex_rx_cfg_5_t;
3948
3949 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_5(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CFG_5(unsigned long a,unsigned long b)3950 static inline uint64_t BDK_GSERX_LANEX_RX_CFG_5(unsigned long a, unsigned long b)
3951 {
3952 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
3953 return 0x87e090440028ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
3954 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
3955 return 0x87e090440028ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
3956 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
3957 return 0x87e090440028ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
3958 __bdk_csr_fatal("GSERX_LANEX_RX_CFG_5", 2, a, b, 0, 0);
3959 }
3960
3961 #define typedef_BDK_GSERX_LANEX_RX_CFG_5(a,b) bdk_gserx_lanex_rx_cfg_5_t
3962 #define bustype_BDK_GSERX_LANEX_RX_CFG_5(a,b) BDK_CSR_TYPE_RSL
3963 #define basename_BDK_GSERX_LANEX_RX_CFG_5(a,b) "GSERX_LANEX_RX_CFG_5"
3964 #define device_bar_BDK_GSERX_LANEX_RX_CFG_5(a,b) 0x0 /* PF_BAR0 */
3965 #define busnum_BDK_GSERX_LANEX_RX_CFG_5(a,b) (a)
3966 #define arguments_BDK_GSERX_LANEX_RX_CFG_5(a,b) (a),(b),-1,-1
3967
3968 /**
3969 * Register (RSL) gser#_lane#_rx_ctle_ctrl
3970 *
3971 * GSER Lane RX Precorrelation Control Register
3972 * These are the RAW PCS per-lane RX CTLE control registers.
3973 * These registers are reset by hardware only during chip cold reset. The values of the CSR
3974 * fields in these registers do not change during chip warm or soft resets.
3975 */
3976 union bdk_gserx_lanex_rx_ctle_ctrl
3977 {
3978 uint64_t u;
3979 struct bdk_gserx_lanex_rx_ctle_ctrl_s
3980 {
3981 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3982 uint64_t reserved_16_63 : 48;
3983 uint64_t pcs_sds_rx_ctle_bias_ctrl : 2;/**< [ 15: 14](R/W) CTLE bias trim bits.
3984 0x0 = -10%.
3985 0x1 = 0%.
3986 0x2 = +5%.
3987 0x3 = +10%. */
3988 uint64_t pcs_sds_rx_ctle_zero : 4; /**< [ 13: 10](R/W) Equalizer peaking control.
3989
3990 Recommended settings:
3991
3992 When auto-negotiated link training is not present (e.g. BGX) and link speed \<
3993 5 Gbaud,
3994 pre-CTLE, post-CTLE, and peaking control settings should be manually
3995 configured. GSER()_LANE()_RX_CFG_5[RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL]
3996 should both be set, GSER()_LANE()_RX_CFG_2[RX_SDS_RX_AGC_MVAL] has the
3997 pre and post settings, and [PCS_SDS_RX_CTLE_ZERO] controls equalizer
3998 peaking.
3999
4000 The [PCS_SDS_RX_CTLE_ZERO] setting should be derived from signal integrity
4001 simulations with the IBIS-AMI model supplied by Cavium when auto-negotiated
4002 link training is not present and link speed \< 5 Gbaud. */
4003 uint64_t rx_ctle_pole_ovrrd_en : 1; /**< [ 9: 9](R/W) Equalizer pole adjustment override enable. */
4004 uint64_t rx_ctle_pole_ovrrd_val : 4; /**< [ 8: 5](R/W) Equalizer pole adjustment override value.
4005 RX precorrelation sample counter control
4006 bit 3: Optimize CTLE during training.
4007 bit 2: Turn off DFE1 for edge samplers.
4008 bits 1:0:
4009 0x0 = ~ 5dB of peaking at 4.0 GHz.
4010 0x1 = ~10dB of peaking at 5.0 GHz.
4011 0x2 = ~15dB of peaking at 5.5 GHz.
4012 0x3 = ~20dB of peaking at 6.0 GHz. */
4013 uint64_t pcs_sds_rx_ctle_pole_max : 2;/**< [ 4: 3](R/W) Maximum pole value (for VMA adaption, not applicable in manual mode). */
4014 uint64_t pcs_sds_rx_ctle_pole_min : 2;/**< [ 2: 1](R/W) Minimum pole value (for VMA adaption, not applicable in manual mode). */
4015 uint64_t pcs_sds_rx_ctle_pole_step : 1;/**< [ 0: 0](R/W) Step pole value (for VMA adaption, not applicable in manual mode). */
4016 #else /* Word 0 - Little Endian */
4017 uint64_t pcs_sds_rx_ctle_pole_step : 1;/**< [ 0: 0](R/W) Step pole value (for VMA adaption, not applicable in manual mode). */
4018 uint64_t pcs_sds_rx_ctle_pole_min : 2;/**< [ 2: 1](R/W) Minimum pole value (for VMA adaption, not applicable in manual mode). */
4019 uint64_t pcs_sds_rx_ctle_pole_max : 2;/**< [ 4: 3](R/W) Maximum pole value (for VMA adaption, not applicable in manual mode). */
4020 uint64_t rx_ctle_pole_ovrrd_val : 4; /**< [ 8: 5](R/W) Equalizer pole adjustment override value.
4021 RX precorrelation sample counter control
4022 bit 3: Optimize CTLE during training.
4023 bit 2: Turn off DFE1 for edge samplers.
4024 bits 1:0:
4025 0x0 = ~ 5dB of peaking at 4.0 GHz.
4026 0x1 = ~10dB of peaking at 5.0 GHz.
4027 0x2 = ~15dB of peaking at 5.5 GHz.
4028 0x3 = ~20dB of peaking at 6.0 GHz. */
4029 uint64_t rx_ctle_pole_ovrrd_en : 1; /**< [ 9: 9](R/W) Equalizer pole adjustment override enable. */
4030 uint64_t pcs_sds_rx_ctle_zero : 4; /**< [ 13: 10](R/W) Equalizer peaking control.
4031
4032 Recommended settings:
4033
4034 When auto-negotiated link training is not present (e.g. BGX) and link speed \<
4035 5 Gbaud,
4036 pre-CTLE, post-CTLE, and peaking control settings should be manually
4037 configured. GSER()_LANE()_RX_CFG_5[RX_AGC_MEN_OVRRD_EN,RX_AGC_MEN_OVRRD_VAL]
4038 should both be set, GSER()_LANE()_RX_CFG_2[RX_SDS_RX_AGC_MVAL] has the
4039 pre and post settings, and [PCS_SDS_RX_CTLE_ZERO] controls equalizer
4040 peaking.
4041
4042 The [PCS_SDS_RX_CTLE_ZERO] setting should be derived from signal integrity
4043 simulations with the IBIS-AMI model supplied by Cavium when auto-negotiated
4044 link training is not present and link speed \< 5 Gbaud. */
4045 uint64_t pcs_sds_rx_ctle_bias_ctrl : 2;/**< [ 15: 14](R/W) CTLE bias trim bits.
4046 0x0 = -10%.
4047 0x1 = 0%.
4048 0x2 = +5%.
4049 0x3 = +10%. */
4050 uint64_t reserved_16_63 : 48;
4051 #endif /* Word 0 - End */
4052 } s;
4053 /* struct bdk_gserx_lanex_rx_ctle_ctrl_s cn; */
4054 };
4055 typedef union bdk_gserx_lanex_rx_ctle_ctrl bdk_gserx_lanex_rx_ctle_ctrl_t;
4056
4057 static inline uint64_t BDK_GSERX_LANEX_RX_CTLE_CTRL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_CTLE_CTRL(unsigned long a,unsigned long b)4058 static inline uint64_t BDK_GSERX_LANEX_RX_CTLE_CTRL(unsigned long a, unsigned long b)
4059 {
4060 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4061 return 0x87e090440058ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4062 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4063 return 0x87e090440058ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4064 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4065 return 0x87e090440058ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4066 __bdk_csr_fatal("GSERX_LANEX_RX_CTLE_CTRL", 2, a, b, 0, 0);
4067 }
4068
4069 #define typedef_BDK_GSERX_LANEX_RX_CTLE_CTRL(a,b) bdk_gserx_lanex_rx_ctle_ctrl_t
4070 #define bustype_BDK_GSERX_LANEX_RX_CTLE_CTRL(a,b) BDK_CSR_TYPE_RSL
4071 #define basename_BDK_GSERX_LANEX_RX_CTLE_CTRL(a,b) "GSERX_LANEX_RX_CTLE_CTRL"
4072 #define device_bar_BDK_GSERX_LANEX_RX_CTLE_CTRL(a,b) 0x0 /* PF_BAR0 */
4073 #define busnum_BDK_GSERX_LANEX_RX_CTLE_CTRL(a,b) (a)
4074 #define arguments_BDK_GSERX_LANEX_RX_CTLE_CTRL(a,b) (a),(b),-1,-1
4075
4076 /**
4077 * Register (RSL) gser#_lane#_rx_loop_ctrl
4078 *
4079 * GSER Lane RX Loop Control Registers
4080 * These registers are for diagnostic use only.
4081 * These registers are reset by hardware only during chip cold reset.
4082 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
4083 */
4084 union bdk_gserx_lanex_rx_loop_ctrl
4085 {
4086 uint64_t u;
4087 struct bdk_gserx_lanex_rx_loop_ctrl_s
4088 {
4089 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4090 uint64_t reserved_12_63 : 52;
4091 uint64_t fast_dll_lock : 1; /**< [ 11: 11](R/W/H) Assert to enable fast DLL lock (for simulation purposes only). */
4092 uint64_t fast_ofst_cncl : 1; /**< [ 10: 10](R/W/H) Assert to enable fast Offset cancellation (for simulation purposes only). */
4093 uint64_t cfg_rx_lctrl : 10; /**< [ 9: 0](R/W) Loop control settings.
4094
4095 \<0\> = cdr_en_byp.
4096 \<1\> = dfe_en_byp.
4097 \<2\> = agc_en_byp.
4098 \<3\> = ofst_cncl_en_byp.
4099 \<4\> = CDR resetn.
4100 \<5\> = CTLE resetn.
4101 \<6\> = VMA resetn.
4102 \<7\> = ofst_cncl_rstn_byp.
4103 \<8\> = lctrl_men.
4104 \<9\> = Reserved.
4105
4106 GSER()_LANE()_PWR_CTRL[RX_LCTRL_OVRRD_EN] controls \<9:7\> and \<3:0\>.
4107
4108 Recommended settings:
4109
4110 When auto-negotiated link training is not present, non-SATA/PCIe, and link speed \<=
4111 5 Gbaud, the DFE should be completely disabled by setting all of
4112 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4113 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL],
4114 setting [CFG_RX_LCTRL\<8\>], clearing [CFG_RX_LCTRL\<1\>], clearing all of
4115 GSER(0..6)_LANE(0..1)_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,
4116 DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4117 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4118 DFE_C1_MVAL,DFE_C1_MSGN]. */
4119 #else /* Word 0 - Little Endian */
4120 uint64_t cfg_rx_lctrl : 10; /**< [ 9: 0](R/W) Loop control settings.
4121
4122 \<0\> = cdr_en_byp.
4123 \<1\> = dfe_en_byp.
4124 \<2\> = agc_en_byp.
4125 \<3\> = ofst_cncl_en_byp.
4126 \<4\> = CDR resetn.
4127 \<5\> = CTLE resetn.
4128 \<6\> = VMA resetn.
4129 \<7\> = ofst_cncl_rstn_byp.
4130 \<8\> = lctrl_men.
4131 \<9\> = Reserved.
4132
4133 GSER()_LANE()_PWR_CTRL[RX_LCTRL_OVRRD_EN] controls \<9:7\> and \<3:0\>.
4134
4135 Recommended settings:
4136
4137 When auto-negotiated link training is not present, non-SATA/PCIe, and link speed \<=
4138 5 Gbaud, the DFE should be completely disabled by setting all of
4139 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4140 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL],
4141 setting [CFG_RX_LCTRL\<8\>], clearing [CFG_RX_LCTRL\<1\>], clearing all of
4142 GSER(0..6)_LANE(0..1)_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,
4143 DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4144 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4145 DFE_C1_MVAL,DFE_C1_MSGN]. */
4146 uint64_t fast_ofst_cncl : 1; /**< [ 10: 10](R/W/H) Assert to enable fast Offset cancellation (for simulation purposes only). */
4147 uint64_t fast_dll_lock : 1; /**< [ 11: 11](R/W/H) Assert to enable fast DLL lock (for simulation purposes only). */
4148 uint64_t reserved_12_63 : 52;
4149 #endif /* Word 0 - End */
4150 } s;
4151 /* struct bdk_gserx_lanex_rx_loop_ctrl_s cn81xx; */
4152 struct bdk_gserx_lanex_rx_loop_ctrl_cn88xx
4153 {
4154 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4155 uint64_t reserved_12_63 : 52;
4156 uint64_t fast_dll_lock : 1; /**< [ 11: 11](R/W/H) Assert to enable fast DLL lock (for simulation purposes only). */
4157 uint64_t fast_ofst_cncl : 1; /**< [ 10: 10](R/W/H) Assert to enable fast Offset cancellation (for simulation purposes only). */
4158 uint64_t cfg_rx_lctrl : 10; /**< [ 9: 0](R/W) Loop control settings.
4159
4160 \<0\> = cdr_en_byp.
4161 \<1\> = dfe_en_byp.
4162 \<2\> = agc_en_byp.
4163 \<3\> = ofst_cncl_en_byp.
4164 \<4\> = CDR resetn.
4165 \<5\> = CTLE resetn.
4166 \<6\> = VMA resetn.
4167 \<7\> = ofst_cncl_rstn_byp.
4168 \<8\> = lctrl_men.
4169 \<9\> = Reserved.
4170
4171 GSER()_LANE()_PWR_CTRL[RX_LCTRL_OVRRD_EN] controls \<9:7\> and \<3:0\>.
4172
4173 Recommended settings:
4174
4175 When auto-negotiated link training is not present, non-SATA/PCIe, and link speed \<=
4176 5 Gbaud, the DFE should be completely disabled by setting all of
4177 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4178 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL],
4179 setting [CFG_RX_LCTRL\<8\>], clearing [CFG_RX_LCTRL\<1\>], clearing all of
4180 GSER(0..6)_LANE(0..3)_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,
4181 DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4182 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4183 DFE_C1_MVAL,DFE_C1_MSGN]. */
4184 #else /* Word 0 - Little Endian */
4185 uint64_t cfg_rx_lctrl : 10; /**< [ 9: 0](R/W) Loop control settings.
4186
4187 \<0\> = cdr_en_byp.
4188 \<1\> = dfe_en_byp.
4189 \<2\> = agc_en_byp.
4190 \<3\> = ofst_cncl_en_byp.
4191 \<4\> = CDR resetn.
4192 \<5\> = CTLE resetn.
4193 \<6\> = VMA resetn.
4194 \<7\> = ofst_cncl_rstn_byp.
4195 \<8\> = lctrl_men.
4196 \<9\> = Reserved.
4197
4198 GSER()_LANE()_PWR_CTRL[RX_LCTRL_OVRRD_EN] controls \<9:7\> and \<3:0\>.
4199
4200 Recommended settings:
4201
4202 When auto-negotiated link training is not present, non-SATA/PCIe, and link speed \<=
4203 5 Gbaud, the DFE should be completely disabled by setting all of
4204 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4205 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL],
4206 setting [CFG_RX_LCTRL\<8\>], clearing [CFG_RX_LCTRL\<1\>], clearing all of
4207 GSER(0..6)_LANE(0..3)_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,
4208 DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4209 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4210 DFE_C1_MVAL,DFE_C1_MSGN]. */
4211 uint64_t fast_ofst_cncl : 1; /**< [ 10: 10](R/W/H) Assert to enable fast Offset cancellation (for simulation purposes only). */
4212 uint64_t fast_dll_lock : 1; /**< [ 11: 11](R/W/H) Assert to enable fast DLL lock (for simulation purposes only). */
4213 uint64_t reserved_12_63 : 52;
4214 #endif /* Word 0 - End */
4215 } cn88xx;
4216 /* struct bdk_gserx_lanex_rx_loop_ctrl_cn88xx cn83xx; */
4217 };
4218 typedef union bdk_gserx_lanex_rx_loop_ctrl bdk_gserx_lanex_rx_loop_ctrl_t;
4219
4220 static inline uint64_t BDK_GSERX_LANEX_RX_LOOP_CTRL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_LOOP_CTRL(unsigned long a,unsigned long b)4221 static inline uint64_t BDK_GSERX_LANEX_RX_LOOP_CTRL(unsigned long a, unsigned long b)
4222 {
4223 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4224 return 0x87e090440048ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4225 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4226 return 0x87e090440048ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4227 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4228 return 0x87e090440048ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4229 __bdk_csr_fatal("GSERX_LANEX_RX_LOOP_CTRL", 2, a, b, 0, 0);
4230 }
4231
4232 #define typedef_BDK_GSERX_LANEX_RX_LOOP_CTRL(a,b) bdk_gserx_lanex_rx_loop_ctrl_t
4233 #define bustype_BDK_GSERX_LANEX_RX_LOOP_CTRL(a,b) BDK_CSR_TYPE_RSL
4234 #define basename_BDK_GSERX_LANEX_RX_LOOP_CTRL(a,b) "GSERX_LANEX_RX_LOOP_CTRL"
4235 #define device_bar_BDK_GSERX_LANEX_RX_LOOP_CTRL(a,b) 0x0 /* PF_BAR0 */
4236 #define busnum_BDK_GSERX_LANEX_RX_LOOP_CTRL(a,b) (a)
4237 #define arguments_BDK_GSERX_LANEX_RX_LOOP_CTRL(a,b) (a),(b),-1,-1
4238
4239 /**
4240 * Register (RSL) gser#_lane#_rx_misc_ctrl
4241 *
4242 * GSER Lane RX Miscellaneous Control Register
4243 * These registers are for diagnostic use only.
4244 * These registers are reset by hardware only during chip cold reset.
4245 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
4246 */
4247 union bdk_gserx_lanex_rx_misc_ctrl
4248 {
4249 uint64_t u;
4250 struct bdk_gserx_lanex_rx_misc_ctrl_s
4251 {
4252 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4253 uint64_t reserved_8_63 : 56;
4254 uint64_t pcs_sds_rx_misc_ctrl : 8; /**< [ 7: 0](R/W/H) Miscellaneous receive control settings.
4255
4256 \<0\> = Shadow PI control. Must set when using the RX internal eye monitor.
4257 \<1\> = Reserved.
4258 \<3:2\> = Offset cal.
4259 \<4\> = Reserved.
4260 \<5\> = Reserved.
4261 \<6\> = 1149 hysteresis control.
4262 \<7\> = Reserved. */
4263 #else /* Word 0 - Little Endian */
4264 uint64_t pcs_sds_rx_misc_ctrl : 8; /**< [ 7: 0](R/W/H) Miscellaneous receive control settings.
4265
4266 \<0\> = Shadow PI control. Must set when using the RX internal eye monitor.
4267 \<1\> = Reserved.
4268 \<3:2\> = Offset cal.
4269 \<4\> = Reserved.
4270 \<5\> = Reserved.
4271 \<6\> = 1149 hysteresis control.
4272 \<7\> = Reserved. */
4273 uint64_t reserved_8_63 : 56;
4274 #endif /* Word 0 - End */
4275 } s;
4276 /* struct bdk_gserx_lanex_rx_misc_ctrl_s cn; */
4277 };
4278 typedef union bdk_gserx_lanex_rx_misc_ctrl bdk_gserx_lanex_rx_misc_ctrl_t;
4279
4280 static inline uint64_t BDK_GSERX_LANEX_RX_MISC_CTRL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_MISC_CTRL(unsigned long a,unsigned long b)4281 static inline uint64_t BDK_GSERX_LANEX_RX_MISC_CTRL(unsigned long a, unsigned long b)
4282 {
4283 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4284 return 0x87e090440050ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4285 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4286 return 0x87e090440050ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4287 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4288 return 0x87e090440050ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4289 __bdk_csr_fatal("GSERX_LANEX_RX_MISC_CTRL", 2, a, b, 0, 0);
4290 }
4291
4292 #define typedef_BDK_GSERX_LANEX_RX_MISC_CTRL(a,b) bdk_gserx_lanex_rx_misc_ctrl_t
4293 #define bustype_BDK_GSERX_LANEX_RX_MISC_CTRL(a,b) BDK_CSR_TYPE_RSL
4294 #define basename_BDK_GSERX_LANEX_RX_MISC_CTRL(a,b) "GSERX_LANEX_RX_MISC_CTRL"
4295 #define device_bar_BDK_GSERX_LANEX_RX_MISC_CTRL(a,b) 0x0 /* PF_BAR0 */
4296 #define busnum_BDK_GSERX_LANEX_RX_MISC_CTRL(a,b) (a)
4297 #define arguments_BDK_GSERX_LANEX_RX_MISC_CTRL(a,b) (a),(b),-1,-1
4298
4299 /**
4300 * Register (RSL) gser#_lane#_rx_misc_ovrrd
4301 *
4302 * GSER Lane RX Miscellaneous Override Register
4303 * These registers are for diagnostic use only.
4304 * These registers are reset by hardware only during chip cold reset.
4305 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
4306 */
4307 union bdk_gserx_lanex_rx_misc_ovrrd
4308 {
4309 uint64_t u;
4310 struct bdk_gserx_lanex_rx_misc_ovrrd_s
4311 {
4312 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4313 uint64_t reserved_14_63 : 50;
4314 uint64_t cfg_rx_oob_clk_en_ovrrd_val : 1;/**< [ 13: 13](R/W) Override value for RX OOB clock enable. */
4315 uint64_t cfg_rx_oob_clk_en_ovrrd_en : 1;/**< [ 12: 12](R/W) Override enable for RX OOB clock enable. */
4316 uint64_t cfg_rx_eie_det_ovrrd_val : 1;/**< [ 11: 11](R/W) Override value for RX electrical-idle-exit
4317 detect enable. */
4318 uint64_t cfg_rx_eie_det_ovrrd_en : 1;/**< [ 10: 10](R/W) Override enable for RX electrical-idle-exit
4319 detect enable. */
4320 uint64_t cfg_rx_cdr_ctrl_ovrrd_en : 1;/**< [ 9: 9](R/W) Not supported. */
4321 uint64_t cfg_rx_eq_eval_ovrrd_val : 1;/**< [ 8: 8](R/W) Training mode control in override mode. */
4322 uint64_t cfg_rx_eq_eval_ovrrd_en : 1;/**< [ 7: 7](R/W) Override enable for RX-EQ eval.
4323 When asserted, training mode is controlled by
4324 CFG_RX_EQ_EVAL_OVRRD_VAL. */
4325 uint64_t reserved_6 : 1;
4326 uint64_t cfg_rx_dll_locken_ovrrd_en : 1;/**< [ 5: 5](R/W) When asserted, override DLL lock enable
4327 signal from the RX power state machine with
4328 CFG_RX_DLL_LOCKEN in register
4329 GSER()_LANE()_RX_CFG_1. */
4330 uint64_t cfg_rx_errdet_ctrl_ovrrd_en : 1;/**< [ 4: 4](R/W) When asserted, pcs_sds_rx_err_det_ctrl is set
4331 to cfg_rx_errdet_ctrl in registers
4332 GSER()_LANE()_RX_CFG_3 and GSER()_LANE()_RX_CFG_4. */
4333 uint64_t reserved_1_3 : 3;
4334 uint64_t cfg_rxeq_eval_restore_en : 1;/**< [ 0: 0](R/W) When asserted, AGC and CTLE use the RX EQ settings determined from RX EQ
4335 evaluation process when VMA is not in manual mode. Otherwise, default settings are used. */
4336 #else /* Word 0 - Little Endian */
4337 uint64_t cfg_rxeq_eval_restore_en : 1;/**< [ 0: 0](R/W) When asserted, AGC and CTLE use the RX EQ settings determined from RX EQ
4338 evaluation process when VMA is not in manual mode. Otherwise, default settings are used. */
4339 uint64_t reserved_1_3 : 3;
4340 uint64_t cfg_rx_errdet_ctrl_ovrrd_en : 1;/**< [ 4: 4](R/W) When asserted, pcs_sds_rx_err_det_ctrl is set
4341 to cfg_rx_errdet_ctrl in registers
4342 GSER()_LANE()_RX_CFG_3 and GSER()_LANE()_RX_CFG_4. */
4343 uint64_t cfg_rx_dll_locken_ovrrd_en : 1;/**< [ 5: 5](R/W) When asserted, override DLL lock enable
4344 signal from the RX power state machine with
4345 CFG_RX_DLL_LOCKEN in register
4346 GSER()_LANE()_RX_CFG_1. */
4347 uint64_t reserved_6 : 1;
4348 uint64_t cfg_rx_eq_eval_ovrrd_en : 1;/**< [ 7: 7](R/W) Override enable for RX-EQ eval.
4349 When asserted, training mode is controlled by
4350 CFG_RX_EQ_EVAL_OVRRD_VAL. */
4351 uint64_t cfg_rx_eq_eval_ovrrd_val : 1;/**< [ 8: 8](R/W) Training mode control in override mode. */
4352 uint64_t cfg_rx_cdr_ctrl_ovrrd_en : 1;/**< [ 9: 9](R/W) Not supported. */
4353 uint64_t cfg_rx_eie_det_ovrrd_en : 1;/**< [ 10: 10](R/W) Override enable for RX electrical-idle-exit
4354 detect enable. */
4355 uint64_t cfg_rx_eie_det_ovrrd_val : 1;/**< [ 11: 11](R/W) Override value for RX electrical-idle-exit
4356 detect enable. */
4357 uint64_t cfg_rx_oob_clk_en_ovrrd_en : 1;/**< [ 12: 12](R/W) Override enable for RX OOB clock enable. */
4358 uint64_t cfg_rx_oob_clk_en_ovrrd_val : 1;/**< [ 13: 13](R/W) Override value for RX OOB clock enable. */
4359 uint64_t reserved_14_63 : 50;
4360 #endif /* Word 0 - End */
4361 } s;
4362 struct bdk_gserx_lanex_rx_misc_ovrrd_cn88xxp1
4363 {
4364 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4365 uint64_t reserved_14_63 : 50;
4366 uint64_t cfg_rx_oob_clk_en_ovrrd_val : 1;/**< [ 13: 13](R/W) Override value for RX OOB clock enable. */
4367 uint64_t cfg_rx_oob_clk_en_ovrrd_en : 1;/**< [ 12: 12](R/W) Override enable for RX OOB clock enable. */
4368 uint64_t cfg_rx_eie_det_ovrrd_val : 1;/**< [ 11: 11](R/W) Override value for RX electrical-idle-exit
4369 detect enable. */
4370 uint64_t cfg_rx_eie_det_ovrrd_en : 1;/**< [ 10: 10](R/W) Override enable for RX electrical-idle-exit
4371 detect enable. */
4372 uint64_t cfg_rx_cdr_ctrl_ovrrd_en : 1;/**< [ 9: 9](R/W) Not supported. */
4373 uint64_t cfg_rx_eq_eval_ovrrd_val : 1;/**< [ 8: 8](R/W) Training mode control in override mode. */
4374 uint64_t cfg_rx_eq_eval_ovrrd_en : 1;/**< [ 7: 7](R/W) Override enable for RX-EQ eval.
4375 When asserted, training mode is controlled by
4376 CFG_RX_EQ_EVAL_OVRRD_VAL. */
4377 uint64_t reserved_6 : 1;
4378 uint64_t cfg_rx_dll_locken_ovrrd_en : 1;/**< [ 5: 5](R/W) When asserted, override DLL lock enable
4379 signal from the RX power state machine with
4380 CFG_RX_DLL_LOCKEN in register
4381 GSER()_LANE()_RX_CFG_1. */
4382 uint64_t cfg_rx_errdet_ctrl_ovrrd_en : 1;/**< [ 4: 4](R/W) When asserted, pcs_sds_rx_err_det_ctrl is set
4383 to cfg_rx_errdet_ctrl in registers
4384 GSER()_LANE()_RX_CFG_3 and GSER()_LANE()_RX_CFG_4. */
4385 uint64_t reserved_0_3 : 4;
4386 #else /* Word 0 - Little Endian */
4387 uint64_t reserved_0_3 : 4;
4388 uint64_t cfg_rx_errdet_ctrl_ovrrd_en : 1;/**< [ 4: 4](R/W) When asserted, pcs_sds_rx_err_det_ctrl is set
4389 to cfg_rx_errdet_ctrl in registers
4390 GSER()_LANE()_RX_CFG_3 and GSER()_LANE()_RX_CFG_4. */
4391 uint64_t cfg_rx_dll_locken_ovrrd_en : 1;/**< [ 5: 5](R/W) When asserted, override DLL lock enable
4392 signal from the RX power state machine with
4393 CFG_RX_DLL_LOCKEN in register
4394 GSER()_LANE()_RX_CFG_1. */
4395 uint64_t reserved_6 : 1;
4396 uint64_t cfg_rx_eq_eval_ovrrd_en : 1;/**< [ 7: 7](R/W) Override enable for RX-EQ eval.
4397 When asserted, training mode is controlled by
4398 CFG_RX_EQ_EVAL_OVRRD_VAL. */
4399 uint64_t cfg_rx_eq_eval_ovrrd_val : 1;/**< [ 8: 8](R/W) Training mode control in override mode. */
4400 uint64_t cfg_rx_cdr_ctrl_ovrrd_en : 1;/**< [ 9: 9](R/W) Not supported. */
4401 uint64_t cfg_rx_eie_det_ovrrd_en : 1;/**< [ 10: 10](R/W) Override enable for RX electrical-idle-exit
4402 detect enable. */
4403 uint64_t cfg_rx_eie_det_ovrrd_val : 1;/**< [ 11: 11](R/W) Override value for RX electrical-idle-exit
4404 detect enable. */
4405 uint64_t cfg_rx_oob_clk_en_ovrrd_en : 1;/**< [ 12: 12](R/W) Override enable for RX OOB clock enable. */
4406 uint64_t cfg_rx_oob_clk_en_ovrrd_val : 1;/**< [ 13: 13](R/W) Override value for RX OOB clock enable. */
4407 uint64_t reserved_14_63 : 50;
4408 #endif /* Word 0 - End */
4409 } cn88xxp1;
4410 /* struct bdk_gserx_lanex_rx_misc_ovrrd_s cn81xx; */
4411 /* struct bdk_gserx_lanex_rx_misc_ovrrd_s cn83xx; */
4412 /* struct bdk_gserx_lanex_rx_misc_ovrrd_s cn88xxp2; */
4413 };
4414 typedef union bdk_gserx_lanex_rx_misc_ovrrd bdk_gserx_lanex_rx_misc_ovrrd_t;
4415
4416 static inline uint64_t BDK_GSERX_LANEX_RX_MISC_OVRRD(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_MISC_OVRRD(unsigned long a,unsigned long b)4417 static inline uint64_t BDK_GSERX_LANEX_RX_MISC_OVRRD(unsigned long a, unsigned long b)
4418 {
4419 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4420 return 0x87e090440258ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4421 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4422 return 0x87e090440258ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4423 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4424 return 0x87e090440258ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4425 __bdk_csr_fatal("GSERX_LANEX_RX_MISC_OVRRD", 2, a, b, 0, 0);
4426 }
4427
4428 #define typedef_BDK_GSERX_LANEX_RX_MISC_OVRRD(a,b) bdk_gserx_lanex_rx_misc_ovrrd_t
4429 #define bustype_BDK_GSERX_LANEX_RX_MISC_OVRRD(a,b) BDK_CSR_TYPE_RSL
4430 #define basename_BDK_GSERX_LANEX_RX_MISC_OVRRD(a,b) "GSERX_LANEX_RX_MISC_OVRRD"
4431 #define device_bar_BDK_GSERX_LANEX_RX_MISC_OVRRD(a,b) 0x0 /* PF_BAR0 */
4432 #define busnum_BDK_GSERX_LANEX_RX_MISC_OVRRD(a,b) (a)
4433 #define arguments_BDK_GSERX_LANEX_RX_MISC_OVRRD(a,b) (a),(b),-1,-1
4434
4435 /**
4436 * Register (RSL) gser#_lane#_rx_os_mvalbbd_1
4437 *
4438 * GSER Lane SerDes RX Offset Calibration Manual Control 1 Register
4439 * These registers are for diagnostic use only.
4440 * These registers are reset by hardware only during chip cold reset.
4441 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
4442 */
4443 union bdk_gserx_lanex_rx_os_mvalbbd_1
4444 {
4445 uint64_t u;
4446 struct bdk_gserx_lanex_rx_os_mvalbbd_1_s
4447 {
4448 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4449 uint64_t reserved_16_63 : 48;
4450 uint64_t pcs_sds_rx_os_mval : 16; /**< [ 15: 0](R/W/H) Offset calibration override value when GSER()_LANE()_RX_CFG_1[PCS_SDS_RX_OS_MEN] is set.
4451 Requires SIGN-MAG format.
4452 \<15:14\> = Not used.
4453 \<13:8\> = Qerr0.
4454 \<7:2\> = I.
4455 \<3:0\> = Ib. */
4456 #else /* Word 0 - Little Endian */
4457 uint64_t pcs_sds_rx_os_mval : 16; /**< [ 15: 0](R/W/H) Offset calibration override value when GSER()_LANE()_RX_CFG_1[PCS_SDS_RX_OS_MEN] is set.
4458 Requires SIGN-MAG format.
4459 \<15:14\> = Not used.
4460 \<13:8\> = Qerr0.
4461 \<7:2\> = I.
4462 \<3:0\> = Ib. */
4463 uint64_t reserved_16_63 : 48;
4464 #endif /* Word 0 - End */
4465 } s;
4466 /* struct bdk_gserx_lanex_rx_os_mvalbbd_1_s cn; */
4467 };
4468 typedef union bdk_gserx_lanex_rx_os_mvalbbd_1 bdk_gserx_lanex_rx_os_mvalbbd_1_t;
4469
4470 static inline uint64_t BDK_GSERX_LANEX_RX_OS_MVALBBD_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_OS_MVALBBD_1(unsigned long a,unsigned long b)4471 static inline uint64_t BDK_GSERX_LANEX_RX_OS_MVALBBD_1(unsigned long a, unsigned long b)
4472 {
4473 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4474 return 0x87e090440230ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4475 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4476 return 0x87e090440230ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4477 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4478 return 0x87e090440230ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4479 __bdk_csr_fatal("GSERX_LANEX_RX_OS_MVALBBD_1", 2, a, b, 0, 0);
4480 }
4481
4482 #define typedef_BDK_GSERX_LANEX_RX_OS_MVALBBD_1(a,b) bdk_gserx_lanex_rx_os_mvalbbd_1_t
4483 #define bustype_BDK_GSERX_LANEX_RX_OS_MVALBBD_1(a,b) BDK_CSR_TYPE_RSL
4484 #define basename_BDK_GSERX_LANEX_RX_OS_MVALBBD_1(a,b) "GSERX_LANEX_RX_OS_MVALBBD_1"
4485 #define device_bar_BDK_GSERX_LANEX_RX_OS_MVALBBD_1(a,b) 0x0 /* PF_BAR0 */
4486 #define busnum_BDK_GSERX_LANEX_RX_OS_MVALBBD_1(a,b) (a)
4487 #define arguments_BDK_GSERX_LANEX_RX_OS_MVALBBD_1(a,b) (a),(b),-1,-1
4488
4489 /**
4490 * Register (RSL) gser#_lane#_rx_os_mvalbbd_2
4491 *
4492 * GSER Lane SerDes RX Offset Calibration Manual Control 1 Register
4493 * These registers are for diagnostic use only.
4494 * These registers are reset by hardware only during chip cold reset.
4495 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
4496 */
4497 union bdk_gserx_lanex_rx_os_mvalbbd_2
4498 {
4499 uint64_t u;
4500 struct bdk_gserx_lanex_rx_os_mvalbbd_2_s
4501 {
4502 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4503 uint64_t reserved_16_63 : 48;
4504 uint64_t pcs_sds_rx_os_mval : 16; /**< [ 15: 0](R/W/H) Offset calibration override value when GSER()_LANE()_RX_CFG_1[PCS_SDS_RX_OS_MEN] is set.
4505 Requires SIGN-MAG format.
4506 \<15:12\> = Ib.
4507 \<11:6\> = Q.
4508 \<5:0\> = Qb. */
4509 #else /* Word 0 - Little Endian */
4510 uint64_t pcs_sds_rx_os_mval : 16; /**< [ 15: 0](R/W/H) Offset calibration override value when GSER()_LANE()_RX_CFG_1[PCS_SDS_RX_OS_MEN] is set.
4511 Requires SIGN-MAG format.
4512 \<15:12\> = Ib.
4513 \<11:6\> = Q.
4514 \<5:0\> = Qb. */
4515 uint64_t reserved_16_63 : 48;
4516 #endif /* Word 0 - End */
4517 } s;
4518 /* struct bdk_gserx_lanex_rx_os_mvalbbd_2_s cn; */
4519 };
4520 typedef union bdk_gserx_lanex_rx_os_mvalbbd_2 bdk_gserx_lanex_rx_os_mvalbbd_2_t;
4521
4522 static inline uint64_t BDK_GSERX_LANEX_RX_OS_MVALBBD_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_OS_MVALBBD_2(unsigned long a,unsigned long b)4523 static inline uint64_t BDK_GSERX_LANEX_RX_OS_MVALBBD_2(unsigned long a, unsigned long b)
4524 {
4525 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4526 return 0x87e090440238ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4527 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4528 return 0x87e090440238ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4529 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4530 return 0x87e090440238ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4531 __bdk_csr_fatal("GSERX_LANEX_RX_OS_MVALBBD_2", 2, a, b, 0, 0);
4532 }
4533
4534 #define typedef_BDK_GSERX_LANEX_RX_OS_MVALBBD_2(a,b) bdk_gserx_lanex_rx_os_mvalbbd_2_t
4535 #define bustype_BDK_GSERX_LANEX_RX_OS_MVALBBD_2(a,b) BDK_CSR_TYPE_RSL
4536 #define basename_BDK_GSERX_LANEX_RX_OS_MVALBBD_2(a,b) "GSERX_LANEX_RX_OS_MVALBBD_2"
4537 #define device_bar_BDK_GSERX_LANEX_RX_OS_MVALBBD_2(a,b) 0x0 /* PF_BAR0 */
4538 #define busnum_BDK_GSERX_LANEX_RX_OS_MVALBBD_2(a,b) (a)
4539 #define arguments_BDK_GSERX_LANEX_RX_OS_MVALBBD_2(a,b) (a),(b),-1,-1
4540
4541 /**
4542 * Register (RSL) gser#_lane#_rx_os_out_1
4543 *
4544 * GSER Lane SerDes RX Calibration Status 1 Register
4545 * These registers are for diagnostic use only.
4546 * These registers are reset by hardware only during chip cold reset.
4547 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
4548 */
4549 union bdk_gserx_lanex_rx_os_out_1
4550 {
4551 uint64_t u;
4552 struct bdk_gserx_lanex_rx_os_out_1_s
4553 {
4554 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4555 uint64_t reserved_12_63 : 52;
4556 uint64_t sds_pcs_rx_os_out : 12; /**< [ 11: 0](RO/H) Offset calibration code for readout, 2's complement.
4557 \<11:6\> = Not used.
4558 \<5:0\> = Qerr0. */
4559 #else /* Word 0 - Little Endian */
4560 uint64_t sds_pcs_rx_os_out : 12; /**< [ 11: 0](RO/H) Offset calibration code for readout, 2's complement.
4561 \<11:6\> = Not used.
4562 \<5:0\> = Qerr0. */
4563 uint64_t reserved_12_63 : 52;
4564 #endif /* Word 0 - End */
4565 } s;
4566 /* struct bdk_gserx_lanex_rx_os_out_1_s cn; */
4567 };
4568 typedef union bdk_gserx_lanex_rx_os_out_1 bdk_gserx_lanex_rx_os_out_1_t;
4569
4570 static inline uint64_t BDK_GSERX_LANEX_RX_OS_OUT_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_OS_OUT_1(unsigned long a,unsigned long b)4571 static inline uint64_t BDK_GSERX_LANEX_RX_OS_OUT_1(unsigned long a, unsigned long b)
4572 {
4573 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4574 return 0x87e0904402a0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4575 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4576 return 0x87e0904402a0ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4577 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4578 return 0x87e0904402a0ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4579 __bdk_csr_fatal("GSERX_LANEX_RX_OS_OUT_1", 2, a, b, 0, 0);
4580 }
4581
4582 #define typedef_BDK_GSERX_LANEX_RX_OS_OUT_1(a,b) bdk_gserx_lanex_rx_os_out_1_t
4583 #define bustype_BDK_GSERX_LANEX_RX_OS_OUT_1(a,b) BDK_CSR_TYPE_RSL
4584 #define basename_BDK_GSERX_LANEX_RX_OS_OUT_1(a,b) "GSERX_LANEX_RX_OS_OUT_1"
4585 #define device_bar_BDK_GSERX_LANEX_RX_OS_OUT_1(a,b) 0x0 /* PF_BAR0 */
4586 #define busnum_BDK_GSERX_LANEX_RX_OS_OUT_1(a,b) (a)
4587 #define arguments_BDK_GSERX_LANEX_RX_OS_OUT_1(a,b) (a),(b),-1,-1
4588
4589 /**
4590 * Register (RSL) gser#_lane#_rx_os_out_2
4591 *
4592 * GSER Lane SerDes RX Calibration Status 2 Register
4593 * These registers are for diagnostic use only.
4594 * These registers are reset by hardware only during chip cold reset.
4595 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
4596 */
4597 union bdk_gserx_lanex_rx_os_out_2
4598 {
4599 uint64_t u;
4600 struct bdk_gserx_lanex_rx_os_out_2_s
4601 {
4602 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4603 uint64_t reserved_12_63 : 52;
4604 uint64_t sds_pcs_rx_os_out : 12; /**< [ 11: 0](RO/H) Offset calibration code for readout, 2's complement.
4605 \<11:6\> = I.
4606 \<5:0\> = Ib. */
4607 #else /* Word 0 - Little Endian */
4608 uint64_t sds_pcs_rx_os_out : 12; /**< [ 11: 0](RO/H) Offset calibration code for readout, 2's complement.
4609 \<11:6\> = I.
4610 \<5:0\> = Ib. */
4611 uint64_t reserved_12_63 : 52;
4612 #endif /* Word 0 - End */
4613 } s;
4614 /* struct bdk_gserx_lanex_rx_os_out_2_s cn; */
4615 };
4616 typedef union bdk_gserx_lanex_rx_os_out_2 bdk_gserx_lanex_rx_os_out_2_t;
4617
4618 static inline uint64_t BDK_GSERX_LANEX_RX_OS_OUT_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_OS_OUT_2(unsigned long a,unsigned long b)4619 static inline uint64_t BDK_GSERX_LANEX_RX_OS_OUT_2(unsigned long a, unsigned long b)
4620 {
4621 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4622 return 0x87e0904402a8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4623 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4624 return 0x87e0904402a8ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4625 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4626 return 0x87e0904402a8ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4627 __bdk_csr_fatal("GSERX_LANEX_RX_OS_OUT_2", 2, a, b, 0, 0);
4628 }
4629
4630 #define typedef_BDK_GSERX_LANEX_RX_OS_OUT_2(a,b) bdk_gserx_lanex_rx_os_out_2_t
4631 #define bustype_BDK_GSERX_LANEX_RX_OS_OUT_2(a,b) BDK_CSR_TYPE_RSL
4632 #define basename_BDK_GSERX_LANEX_RX_OS_OUT_2(a,b) "GSERX_LANEX_RX_OS_OUT_2"
4633 #define device_bar_BDK_GSERX_LANEX_RX_OS_OUT_2(a,b) 0x0 /* PF_BAR0 */
4634 #define busnum_BDK_GSERX_LANEX_RX_OS_OUT_2(a,b) (a)
4635 #define arguments_BDK_GSERX_LANEX_RX_OS_OUT_2(a,b) (a),(b),-1,-1
4636
4637 /**
4638 * Register (RSL) gser#_lane#_rx_os_out_3
4639 *
4640 * GSER Lane SerDes RX Calibration Status 3 Register
4641 * These registers are for diagnostic use only.
4642 * These registers are reset by hardware only during chip cold reset.
4643 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
4644 */
4645 union bdk_gserx_lanex_rx_os_out_3
4646 {
4647 uint64_t u;
4648 struct bdk_gserx_lanex_rx_os_out_3_s
4649 {
4650 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4651 uint64_t reserved_12_63 : 52;
4652 uint64_t sds_pcs_rx_os_out : 12; /**< [ 11: 0](RO/H) Offset calibration code for readout, 2's complement.
4653 \<11:6\> = Q.
4654 \<5:0\> = Qb. */
4655 #else /* Word 0 - Little Endian */
4656 uint64_t sds_pcs_rx_os_out : 12; /**< [ 11: 0](RO/H) Offset calibration code for readout, 2's complement.
4657 \<11:6\> = Q.
4658 \<5:0\> = Qb. */
4659 uint64_t reserved_12_63 : 52;
4660 #endif /* Word 0 - End */
4661 } s;
4662 /* struct bdk_gserx_lanex_rx_os_out_3_s cn; */
4663 };
4664 typedef union bdk_gserx_lanex_rx_os_out_3 bdk_gserx_lanex_rx_os_out_3_t;
4665
4666 static inline uint64_t BDK_GSERX_LANEX_RX_OS_OUT_3(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_OS_OUT_3(unsigned long a,unsigned long b)4667 static inline uint64_t BDK_GSERX_LANEX_RX_OS_OUT_3(unsigned long a, unsigned long b)
4668 {
4669 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4670 return 0x87e0904402b0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4671 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4672 return 0x87e0904402b0ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4673 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4674 return 0x87e0904402b0ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4675 __bdk_csr_fatal("GSERX_LANEX_RX_OS_OUT_3", 2, a, b, 0, 0);
4676 }
4677
4678 #define typedef_BDK_GSERX_LANEX_RX_OS_OUT_3(a,b) bdk_gserx_lanex_rx_os_out_3_t
4679 #define bustype_BDK_GSERX_LANEX_RX_OS_OUT_3(a,b) BDK_CSR_TYPE_RSL
4680 #define basename_BDK_GSERX_LANEX_RX_OS_OUT_3(a,b) "GSERX_LANEX_RX_OS_OUT_3"
4681 #define device_bar_BDK_GSERX_LANEX_RX_OS_OUT_3(a,b) 0x0 /* PF_BAR0 */
4682 #define busnum_BDK_GSERX_LANEX_RX_OS_OUT_3(a,b) (a)
4683 #define arguments_BDK_GSERX_LANEX_RX_OS_OUT_3(a,b) (a),(b),-1,-1
4684
4685 /**
4686 * Register (RSL) gser#_lane#_rx_precorr_ctrl
4687 *
4688 * GSER Lane RX Precorrelation Control Register
4689 * These are the RAW PCS per-lane RX precorrelation control registers. These registers are for
4690 * diagnostic use only.
4691 * These registers are reset by hardware only during chip cold reset. The values of the CSR
4692 * fields in these registers do not change during chip warm or soft resets.
4693 */
4694 union bdk_gserx_lanex_rx_precorr_ctrl
4695 {
4696 uint64_t u;
4697 struct bdk_gserx_lanex_rx_precorr_ctrl_s
4698 {
4699 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4700 uint64_t reserved_5_63 : 59;
4701 uint64_t rx_precorr_disable : 1; /**< [ 4: 4](R/W) Disable RX precorrelation calculation. */
4702 uint64_t rx_precorr_en_ovrrd_en : 1; /**< [ 3: 3](R/W) Override enable for RX precorrelation calculation enable. */
4703 uint64_t rx_precorr_en_ovrrd_val : 1;/**< [ 2: 2](R/W) Override value for RX precorrelation calculation enable. */
4704 uint64_t pcs_sds_rx_precorr_scnt_ctrl : 2;/**< [ 1: 0](R/W) RX precorrelation sample counter control.
4705 0x0 = Load max sample counter with 0x1FF.
4706 0x1 = Load max sample counter with 0x3FF.
4707 0x2 = Load max sample counter with 0x7FF.
4708 0x3 = Load max sample counter with 0xFFF. */
4709 #else /* Word 0 - Little Endian */
4710 uint64_t pcs_sds_rx_precorr_scnt_ctrl : 2;/**< [ 1: 0](R/W) RX precorrelation sample counter control.
4711 0x0 = Load max sample counter with 0x1FF.
4712 0x1 = Load max sample counter with 0x3FF.
4713 0x2 = Load max sample counter with 0x7FF.
4714 0x3 = Load max sample counter with 0xFFF. */
4715 uint64_t rx_precorr_en_ovrrd_val : 1;/**< [ 2: 2](R/W) Override value for RX precorrelation calculation enable. */
4716 uint64_t rx_precorr_en_ovrrd_en : 1; /**< [ 3: 3](R/W) Override enable for RX precorrelation calculation enable. */
4717 uint64_t rx_precorr_disable : 1; /**< [ 4: 4](R/W) Disable RX precorrelation calculation. */
4718 uint64_t reserved_5_63 : 59;
4719 #endif /* Word 0 - End */
4720 } s;
4721 /* struct bdk_gserx_lanex_rx_precorr_ctrl_s cn; */
4722 };
4723 typedef union bdk_gserx_lanex_rx_precorr_ctrl bdk_gserx_lanex_rx_precorr_ctrl_t;
4724
4725 static inline uint64_t BDK_GSERX_LANEX_RX_PRECORR_CTRL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_PRECORR_CTRL(unsigned long a,unsigned long b)4726 static inline uint64_t BDK_GSERX_LANEX_RX_PRECORR_CTRL(unsigned long a, unsigned long b)
4727 {
4728 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4729 return 0x87e090440060ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4730 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4731 return 0x87e090440060ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4732 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4733 return 0x87e090440060ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4734 __bdk_csr_fatal("GSERX_LANEX_RX_PRECORR_CTRL", 2, a, b, 0, 0);
4735 }
4736
4737 #define typedef_BDK_GSERX_LANEX_RX_PRECORR_CTRL(a,b) bdk_gserx_lanex_rx_precorr_ctrl_t
4738 #define bustype_BDK_GSERX_LANEX_RX_PRECORR_CTRL(a,b) BDK_CSR_TYPE_RSL
4739 #define basename_BDK_GSERX_LANEX_RX_PRECORR_CTRL(a,b) "GSERX_LANEX_RX_PRECORR_CTRL"
4740 #define device_bar_BDK_GSERX_LANEX_RX_PRECORR_CTRL(a,b) 0x0 /* PF_BAR0 */
4741 #define busnum_BDK_GSERX_LANEX_RX_PRECORR_CTRL(a,b) (a)
4742 #define arguments_BDK_GSERX_LANEX_RX_PRECORR_CTRL(a,b) (a),(b),-1,-1
4743
4744 /**
4745 * Register (RSL) gser#_lane#_rx_precorr_val
4746 *
4747 * GSER Lane RX Precorrelation Count Register
4748 * These are the RAW PCS per-lane RX precorrelation control registers. These registers are for
4749 * diagnostic use only.
4750 * These registers are reset by hardware only during chip cold reset. The values of the CSR
4751 * fields in these registers do not change during chip warm or soft resets.
4752 */
4753 union bdk_gserx_lanex_rx_precorr_val
4754 {
4755 uint64_t u;
4756 struct bdk_gserx_lanex_rx_precorr_val_s
4757 {
4758 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4759 uint64_t reserved_13_63 : 51;
4760 uint64_t sds_pcs_rx_precorr_vld : 1; /**< [ 12: 12](RO/H) RX precorrelation count is valid. */
4761 uint64_t sds_pcs_rx_precorr_cnt : 12;/**< [ 11: 0](RO/H) RX precorrelation count. */
4762 #else /* Word 0 - Little Endian */
4763 uint64_t sds_pcs_rx_precorr_cnt : 12;/**< [ 11: 0](RO/H) RX precorrelation count. */
4764 uint64_t sds_pcs_rx_precorr_vld : 1; /**< [ 12: 12](RO/H) RX precorrelation count is valid. */
4765 uint64_t reserved_13_63 : 51;
4766 #endif /* Word 0 - End */
4767 } s;
4768 /* struct bdk_gserx_lanex_rx_precorr_val_s cn; */
4769 };
4770 typedef union bdk_gserx_lanex_rx_precorr_val bdk_gserx_lanex_rx_precorr_val_t;
4771
4772 static inline uint64_t BDK_GSERX_LANEX_RX_PRECORR_VAL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_PRECORR_VAL(unsigned long a,unsigned long b)4773 static inline uint64_t BDK_GSERX_LANEX_RX_PRECORR_VAL(unsigned long a, unsigned long b)
4774 {
4775 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4776 return 0x87e090440078ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4777 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4778 return 0x87e090440078ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4779 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4780 return 0x87e090440078ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4781 __bdk_csr_fatal("GSERX_LANEX_RX_PRECORR_VAL", 2, a, b, 0, 0);
4782 }
4783
4784 #define typedef_BDK_GSERX_LANEX_RX_PRECORR_VAL(a,b) bdk_gserx_lanex_rx_precorr_val_t
4785 #define bustype_BDK_GSERX_LANEX_RX_PRECORR_VAL(a,b) BDK_CSR_TYPE_RSL
4786 #define basename_BDK_GSERX_LANEX_RX_PRECORR_VAL(a,b) "GSERX_LANEX_RX_PRECORR_VAL"
4787 #define device_bar_BDK_GSERX_LANEX_RX_PRECORR_VAL(a,b) 0x0 /* PF_BAR0 */
4788 #define busnum_BDK_GSERX_LANEX_RX_PRECORR_VAL(a,b) (a)
4789 #define arguments_BDK_GSERX_LANEX_RX_PRECORR_VAL(a,b) (a),(b),-1,-1
4790
4791 /**
4792 * Register (RSL) gser#_lane#_rx_valbbd_ctrl_0
4793 *
4794 * GSER Lane RX Adaptive Equalizer Control Register 0
4795 * These registers are reset by hardware only during chip cold reset. The values of the CSR
4796 * fields in these registers do not change during chip warm or soft resets.
4797 */
4798 union bdk_gserx_lanex_rx_valbbd_ctrl_0
4799 {
4800 uint64_t u;
4801 struct bdk_gserx_lanex_rx_valbbd_ctrl_0_s
4802 {
4803 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4804 uint64_t reserved_14_63 : 50;
4805 uint64_t agc_gain : 2; /**< [ 13: 12](R/W) AGC gain. */
4806 uint64_t dfe_gain : 2; /**< [ 11: 10](R/W) DFE gain. */
4807 uint64_t dfe_c5_mval : 4; /**< [ 9: 6](R/W) DFE Tap5 manual value when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4808 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4809
4810 Recommended settings:
4811
4812 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4813 5 Gbaud, the DFE should be completely disabled by setting all of
4814 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4815 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4816 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
4817 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
4818 [DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4819 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4820 DFE_C1_MVAL,DFE_C1_MSGN]. */
4821 uint64_t dfe_c5_msgn : 1; /**< [ 5: 5](R/W) DFE Tap5 manual sign when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4822 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4823
4824 Recommended settings:
4825
4826 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4827 5 Gbaud, the DFE should be completely disabled by setting all of
4828 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4829 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4830 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
4831 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
4832 [DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4833 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4834 DFE_C1_MVAL,DFE_C1_MSGN]. */
4835 uint64_t dfe_c4_mval : 4; /**< [ 4: 1](R/W) DFE Tap4 manual value when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4836 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4837
4838 Recommended settings:
4839
4840 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4841 5 Gbaud, the DFE should be completely disabled by setting all of
4842 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4843 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4844 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
4845 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
4846 [DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4847 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4848 DFE_C1_MVAL,DFE_C1_MSGN]. */
4849 uint64_t dfe_c4_msgn : 1; /**< [ 0: 0](R/W) DFE Tap4 manual sign when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4850 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4851
4852 Recommended settings:
4853
4854 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4855 5 Gbaud, the DFE should be completely disabled by setting all of
4856 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4857 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4858 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
4859 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
4860 [DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4861 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4862 DFE_C1_MVAL,DFE_C1_MSGN]. */
4863 #else /* Word 0 - Little Endian */
4864 uint64_t dfe_c4_msgn : 1; /**< [ 0: 0](R/W) DFE Tap4 manual sign when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4865 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4866
4867 Recommended settings:
4868
4869 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4870 5 Gbaud, the DFE should be completely disabled by setting all of
4871 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4872 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4873 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
4874 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
4875 [DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4876 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4877 DFE_C1_MVAL,DFE_C1_MSGN]. */
4878 uint64_t dfe_c4_mval : 4; /**< [ 4: 1](R/W) DFE Tap4 manual value when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4879 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4880
4881 Recommended settings:
4882
4883 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4884 5 Gbaud, the DFE should be completely disabled by setting all of
4885 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4886 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4887 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
4888 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
4889 [DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4890 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4891 DFE_C1_MVAL,DFE_C1_MSGN]. */
4892 uint64_t dfe_c5_msgn : 1; /**< [ 5: 5](R/W) DFE Tap5 manual sign when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4893 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4894
4895 Recommended settings:
4896
4897 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4898 5 Gbaud, the DFE should be completely disabled by setting all of
4899 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4900 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4901 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
4902 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
4903 [DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4904 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4905 DFE_C1_MVAL,DFE_C1_MSGN]. */
4906 uint64_t dfe_c5_mval : 4; /**< [ 9: 6](R/W) DFE Tap5 manual value when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4907 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4908
4909 Recommended settings:
4910
4911 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4912 5 Gbaud, the DFE should be completely disabled by setting all of
4913 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4914 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4915 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
4916 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
4917 [DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,DFE_C4_MSGN], and clearing all of
4918 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4919 DFE_C1_MVAL,DFE_C1_MSGN]. */
4920 uint64_t dfe_gain : 2; /**< [ 11: 10](R/W) DFE gain. */
4921 uint64_t agc_gain : 2; /**< [ 13: 12](R/W) AGC gain. */
4922 uint64_t reserved_14_63 : 50;
4923 #endif /* Word 0 - End */
4924 } s;
4925 /* struct bdk_gserx_lanex_rx_valbbd_ctrl_0_s cn; */
4926 };
4927 typedef union bdk_gserx_lanex_rx_valbbd_ctrl_0 bdk_gserx_lanex_rx_valbbd_ctrl_0_t;
4928
4929 static inline uint64_t BDK_GSERX_LANEX_RX_VALBBD_CTRL_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_VALBBD_CTRL_0(unsigned long a,unsigned long b)4930 static inline uint64_t BDK_GSERX_LANEX_RX_VALBBD_CTRL_0(unsigned long a, unsigned long b)
4931 {
4932 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
4933 return 0x87e090440240ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
4934 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
4935 return 0x87e090440240ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
4936 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
4937 return 0x87e090440240ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
4938 __bdk_csr_fatal("GSERX_LANEX_RX_VALBBD_CTRL_0", 2, a, b, 0, 0);
4939 }
4940
4941 #define typedef_BDK_GSERX_LANEX_RX_VALBBD_CTRL_0(a,b) bdk_gserx_lanex_rx_valbbd_ctrl_0_t
4942 #define bustype_BDK_GSERX_LANEX_RX_VALBBD_CTRL_0(a,b) BDK_CSR_TYPE_RSL
4943 #define basename_BDK_GSERX_LANEX_RX_VALBBD_CTRL_0(a,b) "GSERX_LANEX_RX_VALBBD_CTRL_0"
4944 #define device_bar_BDK_GSERX_LANEX_RX_VALBBD_CTRL_0(a,b) 0x0 /* PF_BAR0 */
4945 #define busnum_BDK_GSERX_LANEX_RX_VALBBD_CTRL_0(a,b) (a)
4946 #define arguments_BDK_GSERX_LANEX_RX_VALBBD_CTRL_0(a,b) (a),(b),-1,-1
4947
4948 /**
4949 * Register (RSL) gser#_lane#_rx_valbbd_ctrl_1
4950 *
4951 * GSER Lane RX Adaptive Equalizer Control Register 1
4952 * These registers are reset by hardware only during chip cold reset. The values of the CSR
4953 * fields in these registers do not change during chip warm or soft resets.
4954 */
4955 union bdk_gserx_lanex_rx_valbbd_ctrl_1
4956 {
4957 uint64_t u;
4958 struct bdk_gserx_lanex_rx_valbbd_ctrl_1_s
4959 {
4960 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4961 uint64_t reserved_15_63 : 49;
4962 uint64_t dfe_c3_mval : 4; /**< [ 14: 11](R/W) DFE Tap3 manual value when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4963 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4964
4965 Recommended settings:
4966
4967 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4968 5 Gbaud, the DFE should be completely disabled by setting all of
4969 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4970 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4971 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
4972 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
4973 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
4974 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4975 DFE_C1_MVAL,DFE_C1_MSGN]. */
4976 uint64_t dfe_c3_msgn : 1; /**< [ 10: 10](R/W) DFE Tap3 manual sign when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4977 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4978
4979 Recommended settings:
4980
4981 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4982 5 Gbaud, the DFE should be completely disabled by setting all of
4983 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4984 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4985 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
4986 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
4987 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
4988 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
4989 DFE_C1_MVAL,DFE_C1_MSGN]. */
4990 uint64_t dfe_c2_mval : 4; /**< [ 9: 6](R/W) DFE Tap2 manual value when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
4991 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
4992
4993 Recommended settings:
4994
4995 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
4996 5 Gbaud, the DFE should be completely disabled by setting all of
4997 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
4998 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
4999 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5000 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5001 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
5002 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5003 DFE_C1_MVAL,DFE_C1_MSGN]. */
5004 uint64_t dfe_c2_msgn : 1; /**< [ 5: 5](R/W) DFE Tap2 manual sign when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
5005 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
5006
5007 Recommended settings:
5008
5009 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5010 5 Gbaud, the DFE should be completely disabled by setting all of
5011 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
5012 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
5013 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5014 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5015 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
5016 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5017 DFE_C1_MVAL,DFE_C1_MSGN]. */
5018 uint64_t dfe_c1_mval : 4; /**< [ 4: 1](R/W) DFE Tap1 manual value when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
5019 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
5020
5021 Recommended settings:
5022
5023 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5024 5 Gbaud, the DFE should be completely disabled by setting all of
5025 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
5026 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
5027 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5028 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5029 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
5030 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5031 DFE_C1_MVAL,DFE_C1_MSGN]. */
5032 uint64_t dfe_c1_msgn : 1; /**< [ 0: 0](R/W) DFE Tap1 manual sign when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
5033 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
5034
5035 Recommended settings:
5036
5037 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5038 5 Gbaud, the DFE should be completely disabled by setting all of
5039 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
5040 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
5041 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5042 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5043 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
5044 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5045 DFE_C1_MVAL,DFE_C1_MSGN]. */
5046 #else /* Word 0 - Little Endian */
5047 uint64_t dfe_c1_msgn : 1; /**< [ 0: 0](R/W) DFE Tap1 manual sign when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
5048 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
5049
5050 Recommended settings:
5051
5052 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5053 5 Gbaud, the DFE should be completely disabled by setting all of
5054 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
5055 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
5056 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5057 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5058 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
5059 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5060 DFE_C1_MVAL,DFE_C1_MSGN]. */
5061 uint64_t dfe_c1_mval : 4; /**< [ 4: 1](R/W) DFE Tap1 manual value when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
5062 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
5063
5064 Recommended settings:
5065
5066 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5067 5 Gbaud, the DFE should be completely disabled by setting all of
5068 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
5069 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
5070 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5071 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5072 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
5073 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5074 DFE_C1_MVAL,DFE_C1_MSGN]. */
5075 uint64_t dfe_c2_msgn : 1; /**< [ 5: 5](R/W) DFE Tap2 manual sign when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
5076 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
5077
5078 Recommended settings:
5079
5080 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5081 5 Gbaud, the DFE should be completely disabled by setting all of
5082 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
5083 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
5084 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5085 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5086 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
5087 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5088 DFE_C1_MVAL,DFE_C1_MSGN]. */
5089 uint64_t dfe_c2_mval : 4; /**< [ 9: 6](R/W) DFE Tap2 manual value when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
5090 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
5091
5092 Recommended settings:
5093
5094 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5095 5 Gbaud, the DFE should be completely disabled by setting all of
5096 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
5097 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
5098 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5099 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5100 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
5101 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5102 DFE_C1_MVAL,DFE_C1_MSGN]. */
5103 uint64_t dfe_c3_msgn : 1; /**< [ 10: 10](R/W) DFE Tap3 manual sign when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
5104 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
5105
5106 Recommended settings:
5107
5108 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5109 5 Gbaud, the DFE should be completely disabled by setting all of
5110 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
5111 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
5112 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5113 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5114 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
5115 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5116 DFE_C1_MVAL,DFE_C1_MSGN]. */
5117 uint64_t dfe_c3_mval : 4; /**< [ 14: 11](R/W) DFE Tap3 manual value when GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN] and
5118 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_C5_OVRD_VAL] are both set.
5119
5120 Recommended settings:
5121
5122 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5123 5 Gbaud, the DFE should be completely disabled by setting all of
5124 GSER()_LANE()_RX_VALBBD_CTRL_2[DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,
5125 DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,DFE_C1_OVRD_VAL], setting
5126 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5127 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5128 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL,FE_C4_MSGN],
5129 and clearing all of [DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5130 DFE_C1_MVAL,DFE_C1_MSGN]. */
5131 uint64_t reserved_15_63 : 49;
5132 #endif /* Word 0 - End */
5133 } s;
5134 /* struct bdk_gserx_lanex_rx_valbbd_ctrl_1_s cn; */
5135 };
5136 typedef union bdk_gserx_lanex_rx_valbbd_ctrl_1 bdk_gserx_lanex_rx_valbbd_ctrl_1_t;
5137
5138 static inline uint64_t BDK_GSERX_LANEX_RX_VALBBD_CTRL_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_VALBBD_CTRL_1(unsigned long a,unsigned long b)5139 static inline uint64_t BDK_GSERX_LANEX_RX_VALBBD_CTRL_1(unsigned long a, unsigned long b)
5140 {
5141 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
5142 return 0x87e090440248ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
5143 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
5144 return 0x87e090440248ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
5145 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
5146 return 0x87e090440248ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
5147 __bdk_csr_fatal("GSERX_LANEX_RX_VALBBD_CTRL_1", 2, a, b, 0, 0);
5148 }
5149
5150 #define typedef_BDK_GSERX_LANEX_RX_VALBBD_CTRL_1(a,b) bdk_gserx_lanex_rx_valbbd_ctrl_1_t
5151 #define bustype_BDK_GSERX_LANEX_RX_VALBBD_CTRL_1(a,b) BDK_CSR_TYPE_RSL
5152 #define basename_BDK_GSERX_LANEX_RX_VALBBD_CTRL_1(a,b) "GSERX_LANEX_RX_VALBBD_CTRL_1"
5153 #define device_bar_BDK_GSERX_LANEX_RX_VALBBD_CTRL_1(a,b) 0x0 /* PF_BAR0 */
5154 #define busnum_BDK_GSERX_LANEX_RX_VALBBD_CTRL_1(a,b) (a)
5155 #define arguments_BDK_GSERX_LANEX_RX_VALBBD_CTRL_1(a,b) (a),(b),-1,-1
5156
5157 /**
5158 * Register (RSL) gser#_lane#_rx_valbbd_ctrl_2
5159 *
5160 * GSER Lane RX Adaptive Equalizer Control Register 2
5161 * These registers are reset by hardware only during chip cold reset. The values of the CSR
5162 * fields in these registers do not change during chip warm or soft resets.
5163 */
5164 union bdk_gserx_lanex_rx_valbbd_ctrl_2
5165 {
5166 uint64_t u;
5167 struct bdk_gserx_lanex_rx_valbbd_ctrl_2_s
5168 {
5169 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5170 uint64_t reserved_6_63 : 58;
5171 uint64_t dfe_ovrd_en : 1; /**< [ 5: 5](R/W) Override enable for DFE tap controls. When asserted, the register bits in
5172 GSER()_LANE()_RX_VALBBD_CTRL_0 and GSER()_LANE()_RX_VALBBD_CTRL_1 are
5173 used for controlling the DFE tap manual mode, instead the manual mode signal indexed by
5174 GSER()_LANE_MODE[LMODE].
5175
5176 Recommended settings:
5177
5178 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5179 5 Gbaud, the DFE should be completely disabled by setting all of
5180 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5181 DFE_C1_OVRD_VAL], setting
5182 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5183 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5184 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5185 and clearing all of
5186 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5187 DFE_C1_MVAL,DFE_C1_MSGN]. */
5188 uint64_t dfe_c5_ovrd_val : 1; /**< [ 4: 4](R/W) Override value for DFE Tap5 manual enable. Used when [DFE_OVRD_EN] is set.
5189
5190 Recommended settings:
5191
5192 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5193 5 Gbaud, the DFE should be completely disabled by setting all of
5194 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5195 DFE_C1_OVRD_VAL], setting
5196 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5197 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5198 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5199 and clearing all of
5200 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5201 DFE_C1_MVAL,DFE_C1_MSGN]. */
5202 uint64_t dfe_c4_ovrd_val : 1; /**< [ 3: 3](R/W) Override value for DFE Tap4 manual enable. Used when [DFE_OVRD_EN] is set.
5203
5204 Recommended settings:
5205
5206 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5207 5 Gbaud, the DFE should be completely disabled by setting all of
5208 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5209 DFE_C1_OVRD_VAL], setting
5210 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5211 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5212 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5213 and clearing all of
5214 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5215 DFE_C1_MVAL,DFE_C1_MSGN]. */
5216 uint64_t dfe_c3_ovrd_val : 1; /**< [ 2: 2](R/W) Override value for DFE Tap3 manual enable. Used when [DFE_OVRD_EN] is set.
5217
5218 Recommended settings:
5219
5220 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5221 5 Gbaud, the DFE should be completely disabled by setting all of
5222 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5223 DFE_C1_OVRD_VAL], setting
5224 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5225 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5226 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5227 and clearing all of
5228 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5229 DFE_C1_MVAL,DFE_C1_MSGN]. */
5230 uint64_t dfe_c2_ovrd_val : 1; /**< [ 1: 1](R/W) Override value for DFE Tap2 manual enable. Used when [DFE_OVRD_EN] is set.
5231
5232 Recommended settings:
5233
5234 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5235 5 Gbaud, the DFE should be completely disabled by setting all of
5236 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5237 DFE_C1_OVRD_VAL], setting
5238 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5239 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5240 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5241 and clearing all of
5242 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5243 DFE_C1_MVAL,DFE_C1_MSGN]. */
5244 uint64_t dfe_c1_ovrd_val : 1; /**< [ 0: 0](R/W) Override value for DFE Tap1 manual enable. Used when [DFE_OVRD_EN] is set.
5245
5246 Recommended settings:
5247
5248 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5249 5 Gbaud, the DFE should be completely disabled by setting all of
5250 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5251 DFE_C1_OVRD_VAL], setting
5252 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5253 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5254 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5255 and clearing all of
5256 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5257 DFE_C1_MVAL,DFE_C1_MSGN]. */
5258 #else /* Word 0 - Little Endian */
5259 uint64_t dfe_c1_ovrd_val : 1; /**< [ 0: 0](R/W) Override value for DFE Tap1 manual enable. Used when [DFE_OVRD_EN] is set.
5260
5261 Recommended settings:
5262
5263 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5264 5 Gbaud, the DFE should be completely disabled by setting all of
5265 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5266 DFE_C1_OVRD_VAL], setting
5267 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5268 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5269 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5270 and clearing all of
5271 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5272 DFE_C1_MVAL,DFE_C1_MSGN]. */
5273 uint64_t dfe_c2_ovrd_val : 1; /**< [ 1: 1](R/W) Override value for DFE Tap2 manual enable. Used when [DFE_OVRD_EN] is set.
5274
5275 Recommended settings:
5276
5277 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5278 5 Gbaud, the DFE should be completely disabled by setting all of
5279 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5280 DFE_C1_OVRD_VAL], setting
5281 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5282 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5283 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5284 and clearing all of
5285 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5286 DFE_C1_MVAL,DFE_C1_MSGN]. */
5287 uint64_t dfe_c3_ovrd_val : 1; /**< [ 2: 2](R/W) Override value for DFE Tap3 manual enable. Used when [DFE_OVRD_EN] is set.
5288
5289 Recommended settings:
5290
5291 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5292 5 Gbaud, the DFE should be completely disabled by setting all of
5293 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5294 DFE_C1_OVRD_VAL], setting
5295 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5296 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5297 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5298 and clearing all of
5299 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5300 DFE_C1_MVAL,DFE_C1_MSGN]. */
5301 uint64_t dfe_c4_ovrd_val : 1; /**< [ 3: 3](R/W) Override value for DFE Tap4 manual enable. Used when [DFE_OVRD_EN] is set.
5302
5303 Recommended settings:
5304
5305 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5306 5 Gbaud, the DFE should be completely disabled by setting all of
5307 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5308 DFE_C1_OVRD_VAL], setting
5309 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5310 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5311 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5312 and clearing all of
5313 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5314 DFE_C1_MVAL,DFE_C1_MSGN]. */
5315 uint64_t dfe_c5_ovrd_val : 1; /**< [ 4: 4](R/W) Override value for DFE Tap5 manual enable. Used when [DFE_OVRD_EN] is set.
5316
5317 Recommended settings:
5318
5319 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5320 5 Gbaud, the DFE should be completely disabled by setting all of
5321 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5322 DFE_C1_OVRD_VAL], setting
5323 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5324 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5325 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5326 and clearing all of
5327 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5328 DFE_C1_MVAL,DFE_C1_MSGN]. */
5329 uint64_t dfe_ovrd_en : 1; /**< [ 5: 5](R/W) Override enable for DFE tap controls. When asserted, the register bits in
5330 GSER()_LANE()_RX_VALBBD_CTRL_0 and GSER()_LANE()_RX_VALBBD_CTRL_1 are
5331 used for controlling the DFE tap manual mode, instead the manual mode signal indexed by
5332 GSER()_LANE_MODE[LMODE].
5333
5334 Recommended settings:
5335
5336 When auto-negotiated link training is not present (e.g. BGX) and link speed \<=
5337 5 Gbaud, the DFE should be completely disabled by setting all of
5338 [DFE_OVRD_EN,DFE_C5_OVRD_VAL,DFE_C4_OVRD_VAL,DFE_C3_OVRD_VAL,DFE_C2_OVRD_VAL,
5339 DFE_C1_OVRD_VAL], setting
5340 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<8\>], clearing
5341 GSER()_LANE()_RX_LOOP_CTRL[CFG_RX_LCTRL\<1\>], clearing all of
5342 GSER()_LANE()_RX_VALBBD_CTRL_0[DFE_C5_MVAL,DFE_C5_MSGN,DFE_C4_MVAL, FE_C4_MSGN],
5343 and clearing all of
5344 GSER()_LANE()_RX_VALBBD_CTRL_1[DFE_C3_MVAL,DFE_C3_MSGN,DFE_C2_MVAL,DFE_C2_MSGN,
5345 DFE_C1_MVAL,DFE_C1_MSGN]. */
5346 uint64_t reserved_6_63 : 58;
5347 #endif /* Word 0 - End */
5348 } s;
5349 /* struct bdk_gserx_lanex_rx_valbbd_ctrl_2_s cn; */
5350 };
5351 typedef union bdk_gserx_lanex_rx_valbbd_ctrl_2 bdk_gserx_lanex_rx_valbbd_ctrl_2_t;
5352
5353 static inline uint64_t BDK_GSERX_LANEX_RX_VALBBD_CTRL_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_VALBBD_CTRL_2(unsigned long a,unsigned long b)5354 static inline uint64_t BDK_GSERX_LANEX_RX_VALBBD_CTRL_2(unsigned long a, unsigned long b)
5355 {
5356 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
5357 return 0x87e090440250ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
5358 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
5359 return 0x87e090440250ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
5360 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
5361 return 0x87e090440250ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
5362 __bdk_csr_fatal("GSERX_LANEX_RX_VALBBD_CTRL_2", 2, a, b, 0, 0);
5363 }
5364
5365 #define typedef_BDK_GSERX_LANEX_RX_VALBBD_CTRL_2(a,b) bdk_gserx_lanex_rx_valbbd_ctrl_2_t
5366 #define bustype_BDK_GSERX_LANEX_RX_VALBBD_CTRL_2(a,b) BDK_CSR_TYPE_RSL
5367 #define basename_BDK_GSERX_LANEX_RX_VALBBD_CTRL_2(a,b) "GSERX_LANEX_RX_VALBBD_CTRL_2"
5368 #define device_bar_BDK_GSERX_LANEX_RX_VALBBD_CTRL_2(a,b) 0x0 /* PF_BAR0 */
5369 #define busnum_BDK_GSERX_LANEX_RX_VALBBD_CTRL_2(a,b) (a)
5370 #define arguments_BDK_GSERX_LANEX_RX_VALBBD_CTRL_2(a,b) (a),(b),-1,-1
5371
5372 /**
5373 * Register (RSL) gser#_lane#_rx_vma_ctrl
5374 *
5375 * GSER Lane RX VMA Control Register
5376 * These are the RAW PCS per-lane RX VMA control registers. These registers are for diagnostic
5377 * use only.
5378 * These registers are reset by hardware only during chip cold reset. The values of the CSR
5379 * fields in these registers do not change during chip warm or soft resets.
5380 */
5381 union bdk_gserx_lanex_rx_vma_ctrl
5382 {
5383 uint64_t u;
5384 struct bdk_gserx_lanex_rx_vma_ctrl_s
5385 {
5386 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5387 uint64_t reserved_16_63 : 48;
5388 uint64_t vma_fine_cfg_sel_ovrrd_en : 1;/**< [ 15: 15](R/W) Enable override of VMA fine configuration selection. */
5389 uint64_t vma_fine_cfg_sel_ovrrd_val : 1;/**< [ 14: 14](R/W) Override value of VMA fine configuration selection.
5390 0 = Coarse mode.
5391 1 = Fine mode. */
5392 uint64_t rx_fom_div_delta : 1; /**< [ 13: 13](R/W) TX figure of merit delta division-mode enable. */
5393 uint64_t rx_vna_ctrl_18_16 : 3; /**< [ 12: 10](R/W) RX VMA loop control. */
5394 uint64_t rx_vna_ctrl_9_0 : 10; /**< [ 9: 0](R/W) RX VMA loop control.
5395 \<9:8\> = Parameter settling wait time.
5396 \<7\> = Limit CTLE peak to max value.
5397 \<6\> = Long reach enabled.
5398 \<5\> = Short reach enabled.
5399 \<4\> = Training done override enable.
5400 \<3\> = Training done override value.
5401 \<2:0\> = VMA clock modulation. */
5402 #else /* Word 0 - Little Endian */
5403 uint64_t rx_vna_ctrl_9_0 : 10; /**< [ 9: 0](R/W) RX VMA loop control.
5404 \<9:8\> = Parameter settling wait time.
5405 \<7\> = Limit CTLE peak to max value.
5406 \<6\> = Long reach enabled.
5407 \<5\> = Short reach enabled.
5408 \<4\> = Training done override enable.
5409 \<3\> = Training done override value.
5410 \<2:0\> = VMA clock modulation. */
5411 uint64_t rx_vna_ctrl_18_16 : 3; /**< [ 12: 10](R/W) RX VMA loop control. */
5412 uint64_t rx_fom_div_delta : 1; /**< [ 13: 13](R/W) TX figure of merit delta division-mode enable. */
5413 uint64_t vma_fine_cfg_sel_ovrrd_val : 1;/**< [ 14: 14](R/W) Override value of VMA fine configuration selection.
5414 0 = Coarse mode.
5415 1 = Fine mode. */
5416 uint64_t vma_fine_cfg_sel_ovrrd_en : 1;/**< [ 15: 15](R/W) Enable override of VMA fine configuration selection. */
5417 uint64_t reserved_16_63 : 48;
5418 #endif /* Word 0 - End */
5419 } s;
5420 /* struct bdk_gserx_lanex_rx_vma_ctrl_s cn; */
5421 };
5422 typedef union bdk_gserx_lanex_rx_vma_ctrl bdk_gserx_lanex_rx_vma_ctrl_t;
5423
5424 static inline uint64_t BDK_GSERX_LANEX_RX_VMA_CTRL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_VMA_CTRL(unsigned long a,unsigned long b)5425 static inline uint64_t BDK_GSERX_LANEX_RX_VMA_CTRL(unsigned long a, unsigned long b)
5426 {
5427 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
5428 return 0x87e090440200ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
5429 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
5430 return 0x87e090440200ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
5431 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
5432 return 0x87e090440200ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
5433 __bdk_csr_fatal("GSERX_LANEX_RX_VMA_CTRL", 2, a, b, 0, 0);
5434 }
5435
5436 #define typedef_BDK_GSERX_LANEX_RX_VMA_CTRL(a,b) bdk_gserx_lanex_rx_vma_ctrl_t
5437 #define bustype_BDK_GSERX_LANEX_RX_VMA_CTRL(a,b) BDK_CSR_TYPE_RSL
5438 #define basename_BDK_GSERX_LANEX_RX_VMA_CTRL(a,b) "GSERX_LANEX_RX_VMA_CTRL"
5439 #define device_bar_BDK_GSERX_LANEX_RX_VMA_CTRL(a,b) 0x0 /* PF_BAR0 */
5440 #define busnum_BDK_GSERX_LANEX_RX_VMA_CTRL(a,b) (a)
5441 #define arguments_BDK_GSERX_LANEX_RX_VMA_CTRL(a,b) (a),(b),-1,-1
5442
5443 /**
5444 * Register (RSL) gser#_lane#_rx_vma_status_0
5445 *
5446 * GSER Lane SerDes RX CDR Status 0 Register
5447 * These registers are for diagnostic use only.
5448 * These registers are reset by hardware only during chip cold reset.
5449 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
5450 */
5451 union bdk_gserx_lanex_rx_vma_status_0
5452 {
5453 uint64_t u;
5454 struct bdk_gserx_lanex_rx_vma_status_0_s
5455 {
5456 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5457 uint64_t reserved_8_63 : 56;
5458 uint64_t sds_pcs_rx_vma_status : 8; /**< [ 7: 0](RO/H) \<7\> = DFE powerdown.
5459 \<6\> = Reserved.
5460 \<5:2\> = CTLE Peak.
5461 \<1:0\> = CTLE Pole. */
5462 #else /* Word 0 - Little Endian */
5463 uint64_t sds_pcs_rx_vma_status : 8; /**< [ 7: 0](RO/H) \<7\> = DFE powerdown.
5464 \<6\> = Reserved.
5465 \<5:2\> = CTLE Peak.
5466 \<1:0\> = CTLE Pole. */
5467 uint64_t reserved_8_63 : 56;
5468 #endif /* Word 0 - End */
5469 } s;
5470 /* struct bdk_gserx_lanex_rx_vma_status_0_s cn; */
5471 };
5472 typedef union bdk_gserx_lanex_rx_vma_status_0 bdk_gserx_lanex_rx_vma_status_0_t;
5473
5474 static inline uint64_t BDK_GSERX_LANEX_RX_VMA_STATUS_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_VMA_STATUS_0(unsigned long a,unsigned long b)5475 static inline uint64_t BDK_GSERX_LANEX_RX_VMA_STATUS_0(unsigned long a, unsigned long b)
5476 {
5477 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
5478 return 0x87e0904402b8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
5479 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
5480 return 0x87e0904402b8ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
5481 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
5482 return 0x87e0904402b8ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
5483 __bdk_csr_fatal("GSERX_LANEX_RX_VMA_STATUS_0", 2, a, b, 0, 0);
5484 }
5485
5486 #define typedef_BDK_GSERX_LANEX_RX_VMA_STATUS_0(a,b) bdk_gserx_lanex_rx_vma_status_0_t
5487 #define bustype_BDK_GSERX_LANEX_RX_VMA_STATUS_0(a,b) BDK_CSR_TYPE_RSL
5488 #define basename_BDK_GSERX_LANEX_RX_VMA_STATUS_0(a,b) "GSERX_LANEX_RX_VMA_STATUS_0"
5489 #define device_bar_BDK_GSERX_LANEX_RX_VMA_STATUS_0(a,b) 0x0 /* PF_BAR0 */
5490 #define busnum_BDK_GSERX_LANEX_RX_VMA_STATUS_0(a,b) (a)
5491 #define arguments_BDK_GSERX_LANEX_RX_VMA_STATUS_0(a,b) (a),(b),-1,-1
5492
5493 /**
5494 * Register (RSL) gser#_lane#_rx_vma_status_1
5495 *
5496 * GSER Lane SerDes RX CDR Status 1 Register
5497 * These registers are for diagnostic use only.
5498 * These registers are reset by hardware only during chip cold reset.
5499 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
5500 */
5501 union bdk_gserx_lanex_rx_vma_status_1
5502 {
5503 uint64_t u;
5504 struct bdk_gserx_lanex_rx_vma_status_1_s
5505 {
5506 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5507 uint64_t reserved_16_63 : 48;
5508 uint64_t sds_pcs_rx_vma_status : 16; /**< [ 15: 0](RO/H) \<15:8\>: Output is controlled by GSER()_LANE()_RX_CFG_4[CFG_RX_ERRDET_CTRL]\<6:5\>:
5509 0x0 = Window counter\<19:12\> (VMA RAW FOM).
5510 0x1 = Window counter\<11:4\>.
5511 0x2 = CTLE (continuous time linear equalizer) pole, SDLL_IQ.
5512 0x3 = Pre-CTLE gain, CTLE Peak.
5513
5514 \<7\>: Training done.
5515
5516 \<6:4\>: Internal state machine delta.
5517
5518 \<3:0\>: Output is controlled by GSER()_LANE()_RX_CDR_CTRL_1[CDR phase offset override
5519 enable]\<4\>:
5520 0x0 = DLL IQ Training value.
5521 0x1 = CDR Phase Offset. */
5522 #else /* Word 0 - Little Endian */
5523 uint64_t sds_pcs_rx_vma_status : 16; /**< [ 15: 0](RO/H) \<15:8\>: Output is controlled by GSER()_LANE()_RX_CFG_4[CFG_RX_ERRDET_CTRL]\<6:5\>:
5524 0x0 = Window counter\<19:12\> (VMA RAW FOM).
5525 0x1 = Window counter\<11:4\>.
5526 0x2 = CTLE (continuous time linear equalizer) pole, SDLL_IQ.
5527 0x3 = Pre-CTLE gain, CTLE Peak.
5528
5529 \<7\>: Training done.
5530
5531 \<6:4\>: Internal state machine delta.
5532
5533 \<3:0\>: Output is controlled by GSER()_LANE()_RX_CDR_CTRL_1[CDR phase offset override
5534 enable]\<4\>:
5535 0x0 = DLL IQ Training value.
5536 0x1 = CDR Phase Offset. */
5537 uint64_t reserved_16_63 : 48;
5538 #endif /* Word 0 - End */
5539 } s;
5540 /* struct bdk_gserx_lanex_rx_vma_status_1_s cn; */
5541 };
5542 typedef union bdk_gserx_lanex_rx_vma_status_1 bdk_gserx_lanex_rx_vma_status_1_t;
5543
5544 static inline uint64_t BDK_GSERX_LANEX_RX_VMA_STATUS_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_RX_VMA_STATUS_1(unsigned long a,unsigned long b)5545 static inline uint64_t BDK_GSERX_LANEX_RX_VMA_STATUS_1(unsigned long a, unsigned long b)
5546 {
5547 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
5548 return 0x87e0904402c0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
5549 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
5550 return 0x87e0904402c0ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
5551 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
5552 return 0x87e0904402c0ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
5553 __bdk_csr_fatal("GSERX_LANEX_RX_VMA_STATUS_1", 2, a, b, 0, 0);
5554 }
5555
5556 #define typedef_BDK_GSERX_LANEX_RX_VMA_STATUS_1(a,b) bdk_gserx_lanex_rx_vma_status_1_t
5557 #define bustype_BDK_GSERX_LANEX_RX_VMA_STATUS_1(a,b) BDK_CSR_TYPE_RSL
5558 #define basename_BDK_GSERX_LANEX_RX_VMA_STATUS_1(a,b) "GSERX_LANEX_RX_VMA_STATUS_1"
5559 #define device_bar_BDK_GSERX_LANEX_RX_VMA_STATUS_1(a,b) 0x0 /* PF_BAR0 */
5560 #define busnum_BDK_GSERX_LANEX_RX_VMA_STATUS_1(a,b) (a)
5561 #define arguments_BDK_GSERX_LANEX_RX_VMA_STATUS_1(a,b) (a),(b),-1,-1
5562
5563 /**
5564 * Register (RSL) gser#_lane#_sds_pin_mon_0
5565 *
5566 * GSER Lane SerDes Pin Monitor 1 Register
5567 * These registers are for diagnostic use only.
5568 * These registers are reset by hardware only during chip cold reset.
5569 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
5570 */
5571 union bdk_gserx_lanex_sds_pin_mon_0
5572 {
5573 uint64_t u;
5574 struct bdk_gserx_lanex_sds_pin_mon_0_s
5575 {
5576 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5577 uint64_t reserved_10_63 : 54;
5578 uint64_t pcs_sds_tx_widthsel : 2; /**< [ 9: 8](RO/H) TX parallel interface width settings (RAW PCS to
5579 SerDes TX).
5580 0x0 = 8-bit raw data (not supported).
5581 0x1 = 10-bit raw data (not supported).
5582 0x2 = 16-bit raw data (not supported).
5583 0x3 = 20-bit raw data. */
5584 uint64_t pcs_sds_rx_pcie_mode : 1; /**< [ 7: 7](RO/H) Selects between RX terminations:
5585 0x0 = pcs_sds_rx_terminate_to_vdda.
5586 0x1 = VSS. */
5587 uint64_t reserved_5_6 : 2;
5588 uint64_t pcs_sds_rx_misc_ctrl_5 : 1; /**< [ 4: 4](RO/H) Not used. */
5589 uint64_t tx_detrx_state : 2; /**< [ 3: 2](RO/H) RX detection state:
5590 0x0 = IDLE.
5591 0x1 = Charge Up.
5592 0x2 = Detection.
5593 0x3 = Restore common mode. */
5594 uint64_t pcs_sds_tx_rx_detect_dis : 1;/**< [ 1: 1](RO/H) TX detect RX, mode disable. */
5595 uint64_t pcs_sds_tx_detect_pulsen : 1;/**< [ 0: 0](RO/H) TX detect RX, pulse enable. */
5596 #else /* Word 0 - Little Endian */
5597 uint64_t pcs_sds_tx_detect_pulsen : 1;/**< [ 0: 0](RO/H) TX detect RX, pulse enable. */
5598 uint64_t pcs_sds_tx_rx_detect_dis : 1;/**< [ 1: 1](RO/H) TX detect RX, mode disable. */
5599 uint64_t tx_detrx_state : 2; /**< [ 3: 2](RO/H) RX detection state:
5600 0x0 = IDLE.
5601 0x1 = Charge Up.
5602 0x2 = Detection.
5603 0x3 = Restore common mode. */
5604 uint64_t pcs_sds_rx_misc_ctrl_5 : 1; /**< [ 4: 4](RO/H) Not used. */
5605 uint64_t reserved_5_6 : 2;
5606 uint64_t pcs_sds_rx_pcie_mode : 1; /**< [ 7: 7](RO/H) Selects between RX terminations:
5607 0x0 = pcs_sds_rx_terminate_to_vdda.
5608 0x1 = VSS. */
5609 uint64_t pcs_sds_tx_widthsel : 2; /**< [ 9: 8](RO/H) TX parallel interface width settings (RAW PCS to
5610 SerDes TX).
5611 0x0 = 8-bit raw data (not supported).
5612 0x1 = 10-bit raw data (not supported).
5613 0x2 = 16-bit raw data (not supported).
5614 0x3 = 20-bit raw data. */
5615 uint64_t reserved_10_63 : 54;
5616 #endif /* Word 0 - End */
5617 } s;
5618 /* struct bdk_gserx_lanex_sds_pin_mon_0_s cn; */
5619 };
5620 typedef union bdk_gserx_lanex_sds_pin_mon_0 bdk_gserx_lanex_sds_pin_mon_0_t;
5621
5622 static inline uint64_t BDK_GSERX_LANEX_SDS_PIN_MON_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_SDS_PIN_MON_0(unsigned long a,unsigned long b)5623 static inline uint64_t BDK_GSERX_LANEX_SDS_PIN_MON_0(unsigned long a, unsigned long b)
5624 {
5625 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
5626 return 0x87e090440130ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
5627 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
5628 return 0x87e090440130ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
5629 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
5630 return 0x87e090440130ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
5631 __bdk_csr_fatal("GSERX_LANEX_SDS_PIN_MON_0", 2, a, b, 0, 0);
5632 }
5633
5634 #define typedef_BDK_GSERX_LANEX_SDS_PIN_MON_0(a,b) bdk_gserx_lanex_sds_pin_mon_0_t
5635 #define bustype_BDK_GSERX_LANEX_SDS_PIN_MON_0(a,b) BDK_CSR_TYPE_RSL
5636 #define basename_BDK_GSERX_LANEX_SDS_PIN_MON_0(a,b) "GSERX_LANEX_SDS_PIN_MON_0"
5637 #define device_bar_BDK_GSERX_LANEX_SDS_PIN_MON_0(a,b) 0x0 /* PF_BAR0 */
5638 #define busnum_BDK_GSERX_LANEX_SDS_PIN_MON_0(a,b) (a)
5639 #define arguments_BDK_GSERX_LANEX_SDS_PIN_MON_0(a,b) (a),(b),-1,-1
5640
5641 /**
5642 * Register (RSL) gser#_lane#_sds_pin_mon_1
5643 *
5644 * GSER Lane SerDes Pin Monitor 1 Register
5645 * These registers are for diagnostic use only.
5646 * These registers are reset by hardware only during chip cold reset.
5647 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
5648 */
5649 union bdk_gserx_lanex_sds_pin_mon_1
5650 {
5651 uint64_t u;
5652 struct bdk_gserx_lanex_sds_pin_mon_1_s
5653 {
5654 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5655 uint64_t reserved_16_63 : 48;
5656 uint64_t pcs_sds_rx_chpd : 1; /**< [ 15: 15](RO/H) RX channel powerdown signal. */
5657 uint64_t pcs_sds_rx_eie_en : 1; /**< [ 14: 14](RO/H) Enable for electrical idle detection circuit
5658 in SerDes RX. */
5659 uint64_t reserved_13 : 1;
5660 uint64_t pcs_sds_ln_loopback_mode : 1;/**< [ 12: 12](RO/H) TX to RX on chip loopback control signal. */
5661 uint64_t pcs_sds_tx_chpd : 1; /**< [ 11: 11](RO/H) TX channel powerdown signal. */
5662 uint64_t pcs_sds_rx_widthsel : 2; /**< [ 10: 9](RO/H) Width select.
5663 0x0 = 8-bit raw data.
5664 0x1 = 10-bit raw data.
5665 0x2 = 16-bit raw data.
5666 0x3 = 20-bit raw data. */
5667 uint64_t reserved_8 : 1;
5668 uint64_t pcs_sds_tx_resetn : 1; /**< [ 7: 7](RO/H) TX reset, active low (RAW PCS output to lane TX). */
5669 uint64_t pcs_sds_tx_tristate_en : 1; /**< [ 6: 6](RO/H) TX driver tristate enable (RAW PCS output to lane TX). */
5670 uint64_t pcs_sds_tx_swing : 5; /**< [ 5: 1](RO/H) TX swing (RAW PCS output to lane TX). */
5671 uint64_t pcs_sds_tx_elec_idle : 1; /**< [ 0: 0](RO/H) TX electrical idle control (RAW PCS output to lane TX). */
5672 #else /* Word 0 - Little Endian */
5673 uint64_t pcs_sds_tx_elec_idle : 1; /**< [ 0: 0](RO/H) TX electrical idle control (RAW PCS output to lane TX). */
5674 uint64_t pcs_sds_tx_swing : 5; /**< [ 5: 1](RO/H) TX swing (RAW PCS output to lane TX). */
5675 uint64_t pcs_sds_tx_tristate_en : 1; /**< [ 6: 6](RO/H) TX driver tristate enable (RAW PCS output to lane TX). */
5676 uint64_t pcs_sds_tx_resetn : 1; /**< [ 7: 7](RO/H) TX reset, active low (RAW PCS output to lane TX). */
5677 uint64_t reserved_8 : 1;
5678 uint64_t pcs_sds_rx_widthsel : 2; /**< [ 10: 9](RO/H) Width select.
5679 0x0 = 8-bit raw data.
5680 0x1 = 10-bit raw data.
5681 0x2 = 16-bit raw data.
5682 0x3 = 20-bit raw data. */
5683 uint64_t pcs_sds_tx_chpd : 1; /**< [ 11: 11](RO/H) TX channel powerdown signal. */
5684 uint64_t pcs_sds_ln_loopback_mode : 1;/**< [ 12: 12](RO/H) TX to RX on chip loopback control signal. */
5685 uint64_t reserved_13 : 1;
5686 uint64_t pcs_sds_rx_eie_en : 1; /**< [ 14: 14](RO/H) Enable for electrical idle detection circuit
5687 in SerDes RX. */
5688 uint64_t pcs_sds_rx_chpd : 1; /**< [ 15: 15](RO/H) RX channel powerdown signal. */
5689 uint64_t reserved_16_63 : 48;
5690 #endif /* Word 0 - End */
5691 } s;
5692 /* struct bdk_gserx_lanex_sds_pin_mon_1_s cn; */
5693 };
5694 typedef union bdk_gserx_lanex_sds_pin_mon_1 bdk_gserx_lanex_sds_pin_mon_1_t;
5695
5696 static inline uint64_t BDK_GSERX_LANEX_SDS_PIN_MON_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_SDS_PIN_MON_1(unsigned long a,unsigned long b)5697 static inline uint64_t BDK_GSERX_LANEX_SDS_PIN_MON_1(unsigned long a, unsigned long b)
5698 {
5699 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
5700 return 0x87e090440138ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
5701 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
5702 return 0x87e090440138ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
5703 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
5704 return 0x87e090440138ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
5705 __bdk_csr_fatal("GSERX_LANEX_SDS_PIN_MON_1", 2, a, b, 0, 0);
5706 }
5707
5708 #define typedef_BDK_GSERX_LANEX_SDS_PIN_MON_1(a,b) bdk_gserx_lanex_sds_pin_mon_1_t
5709 #define bustype_BDK_GSERX_LANEX_SDS_PIN_MON_1(a,b) BDK_CSR_TYPE_RSL
5710 #define basename_BDK_GSERX_LANEX_SDS_PIN_MON_1(a,b) "GSERX_LANEX_SDS_PIN_MON_1"
5711 #define device_bar_BDK_GSERX_LANEX_SDS_PIN_MON_1(a,b) 0x0 /* PF_BAR0 */
5712 #define busnum_BDK_GSERX_LANEX_SDS_PIN_MON_1(a,b) (a)
5713 #define arguments_BDK_GSERX_LANEX_SDS_PIN_MON_1(a,b) (a),(b),-1,-1
5714
5715 /**
5716 * Register (RSL) gser#_lane#_sds_pin_mon_2
5717 *
5718 * GSER Lane SerDes Pin Monitor 1 Register
5719 * These registers are for diagnostic use only.
5720 * These registers are reset by hardware only during chip cold reset.
5721 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
5722 */
5723 union bdk_gserx_lanex_sds_pin_mon_2
5724 {
5725 uint64_t u;
5726 struct bdk_gserx_lanex_sds_pin_mon_2_s
5727 {
5728 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5729 uint64_t reserved_11_63 : 53;
5730 uint64_t pcs_sds_tx_vboost_en : 1; /**< [ 10: 10](RO/H) TX boost enable. */
5731 uint64_t pcs_sds_tx_turbos_en : 1; /**< [ 9: 9](RO/H) TX turbo mode enable signal, increases swing of TX
5732 through current mode. */
5733 uint64_t pcs_sds_premptap : 9; /**< [ 8: 0](RO/H) Preemphasis control.
5734 \<8:4\> = Postcursor.
5735 \<3:0\> = Precursor. */
5736 #else /* Word 0 - Little Endian */
5737 uint64_t pcs_sds_premptap : 9; /**< [ 8: 0](RO/H) Preemphasis control.
5738 \<8:4\> = Postcursor.
5739 \<3:0\> = Precursor. */
5740 uint64_t pcs_sds_tx_turbos_en : 1; /**< [ 9: 9](RO/H) TX turbo mode enable signal, increases swing of TX
5741 through current mode. */
5742 uint64_t pcs_sds_tx_vboost_en : 1; /**< [ 10: 10](RO/H) TX boost enable. */
5743 uint64_t reserved_11_63 : 53;
5744 #endif /* Word 0 - End */
5745 } s;
5746 /* struct bdk_gserx_lanex_sds_pin_mon_2_s cn; */
5747 };
5748 typedef union bdk_gserx_lanex_sds_pin_mon_2 bdk_gserx_lanex_sds_pin_mon_2_t;
5749
5750 static inline uint64_t BDK_GSERX_LANEX_SDS_PIN_MON_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_SDS_PIN_MON_2(unsigned long a,unsigned long b)5751 static inline uint64_t BDK_GSERX_LANEX_SDS_PIN_MON_2(unsigned long a, unsigned long b)
5752 {
5753 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
5754 return 0x87e090440140ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
5755 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
5756 return 0x87e090440140ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
5757 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
5758 return 0x87e090440140ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
5759 __bdk_csr_fatal("GSERX_LANEX_SDS_PIN_MON_2", 2, a, b, 0, 0);
5760 }
5761
5762 #define typedef_BDK_GSERX_LANEX_SDS_PIN_MON_2(a,b) bdk_gserx_lanex_sds_pin_mon_2_t
5763 #define bustype_BDK_GSERX_LANEX_SDS_PIN_MON_2(a,b) BDK_CSR_TYPE_RSL
5764 #define basename_BDK_GSERX_LANEX_SDS_PIN_MON_2(a,b) "GSERX_LANEX_SDS_PIN_MON_2"
5765 #define device_bar_BDK_GSERX_LANEX_SDS_PIN_MON_2(a,b) 0x0 /* PF_BAR0 */
5766 #define busnum_BDK_GSERX_LANEX_SDS_PIN_MON_2(a,b) (a)
5767 #define arguments_BDK_GSERX_LANEX_SDS_PIN_MON_2(a,b) (a),(b),-1,-1
5768
5769 /**
5770 * Register (RSL) gser#_lane#_tx_cfg_0
5771 *
5772 * GSER Lane TX Configuration 0 Register
5773 * These registers are reset by hardware only during chip cold reset. The
5774 * values of the CSR fields in these registers do not change during chip
5775 * warm or soft resets.
5776 */
5777 union bdk_gserx_lanex_tx_cfg_0
5778 {
5779 uint64_t u;
5780 struct bdk_gserx_lanex_tx_cfg_0_s
5781 {
5782 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5783 uint64_t reserved_16_63 : 48;
5784 uint64_t tx_tristate_en_ovrrd_val : 1;/**< [ 15: 15](R/W) TX termination high-Z enable. Override value when
5785 GSER()_LANE()_PWR_CTRL[TX_TRISTATE_EN_OVRRD_EN] is set. */
5786 uint64_t tx_chpd_ovrrd_val : 1; /**< [ 14: 14](R/W) TX lane power down. Active high. Override value when
5787 GSER()_LANE()_PWR_CTRL[TX_PD_OVRRD_EN] is set. */
5788 uint64_t reserved_10_13 : 4;
5789 uint64_t tx_resetn_ovrrd_val : 1; /**< [ 9: 9](R/W) TX P2S reset. Active high. Override value when
5790 GSER()_LANE()_PWR_CTRL[TX_P2S_RESET_OVRRD_EN] is set. */
5791 uint64_t tx_cm_mode : 1; /**< [ 8: 8](R/W/H) Assert to enable fast common-mode charge up. For simulation purposes only. */
5792 uint64_t cfg_tx_swing : 5; /**< [ 7: 3](R/W) TX output swing control.
5793 Default swing encoding when GSER()_LANE()_TX_CFG_1[TX_SWING_OVRRD_EN] is
5794 asserted.
5795
5796 It is recommended to not use the GSER()_LANE()_TX_CFG_0[CFG_TX_SWING],
5797 GSER()_LANE()_TX_CFG_1[TX_SWING_OVRRD_EN,TX_PREMPTAP_OVRRD_VAL], or
5798 GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP] override registers for 10BASE-KR
5799 or PCIe links in which the transmitter is adapted by the respective
5800 hardware-controlled link training protocols.
5801
5802 The [CFG_TX_SWING] value for transmitter swing should be derived from
5803 signal integrity simulations with IBIS-AMI models supplied by Cavium.
5804
5805 A transmit swing change should be followed by a control interface configuration
5806 over-ride to force the new setting - see
5807 GSER()_LANE()_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ]. */
5808 uint64_t fast_rdet_mode : 1; /**< [ 2: 2](R/W/H) Assert to enable fast RX detection. For simulation purposes only. */
5809 uint64_t fast_tristate_mode : 1; /**< [ 1: 1](R/W/H) Assert to enable fast tristate power up. For simulation purposes only. */
5810 uint64_t reserved_0 : 1;
5811 #else /* Word 0 - Little Endian */
5812 uint64_t reserved_0 : 1;
5813 uint64_t fast_tristate_mode : 1; /**< [ 1: 1](R/W/H) Assert to enable fast tristate power up. For simulation purposes only. */
5814 uint64_t fast_rdet_mode : 1; /**< [ 2: 2](R/W/H) Assert to enable fast RX detection. For simulation purposes only. */
5815 uint64_t cfg_tx_swing : 5; /**< [ 7: 3](R/W) TX output swing control.
5816 Default swing encoding when GSER()_LANE()_TX_CFG_1[TX_SWING_OVRRD_EN] is
5817 asserted.
5818
5819 It is recommended to not use the GSER()_LANE()_TX_CFG_0[CFG_TX_SWING],
5820 GSER()_LANE()_TX_CFG_1[TX_SWING_OVRRD_EN,TX_PREMPTAP_OVRRD_VAL], or
5821 GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP] override registers for 10BASE-KR
5822 or PCIe links in which the transmitter is adapted by the respective
5823 hardware-controlled link training protocols.
5824
5825 The [CFG_TX_SWING] value for transmitter swing should be derived from
5826 signal integrity simulations with IBIS-AMI models supplied by Cavium.
5827
5828 A transmit swing change should be followed by a control interface configuration
5829 over-ride to force the new setting - see
5830 GSER()_LANE()_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ]. */
5831 uint64_t tx_cm_mode : 1; /**< [ 8: 8](R/W/H) Assert to enable fast common-mode charge up. For simulation purposes only. */
5832 uint64_t tx_resetn_ovrrd_val : 1; /**< [ 9: 9](R/W) TX P2S reset. Active high. Override value when
5833 GSER()_LANE()_PWR_CTRL[TX_P2S_RESET_OVRRD_EN] is set. */
5834 uint64_t reserved_10_13 : 4;
5835 uint64_t tx_chpd_ovrrd_val : 1; /**< [ 14: 14](R/W) TX lane power down. Active high. Override value when
5836 GSER()_LANE()_PWR_CTRL[TX_PD_OVRRD_EN] is set. */
5837 uint64_t tx_tristate_en_ovrrd_val : 1;/**< [ 15: 15](R/W) TX termination high-Z enable. Override value when
5838 GSER()_LANE()_PWR_CTRL[TX_TRISTATE_EN_OVRRD_EN] is set. */
5839 uint64_t reserved_16_63 : 48;
5840 #endif /* Word 0 - End */
5841 } s;
5842 /* struct bdk_gserx_lanex_tx_cfg_0_s cn; */
5843 };
5844 typedef union bdk_gserx_lanex_tx_cfg_0 bdk_gserx_lanex_tx_cfg_0_t;
5845
5846 static inline uint64_t BDK_GSERX_LANEX_TX_CFG_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_TX_CFG_0(unsigned long a,unsigned long b)5847 static inline uint64_t BDK_GSERX_LANEX_TX_CFG_0(unsigned long a, unsigned long b)
5848 {
5849 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
5850 return 0x87e0904400a8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
5851 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
5852 return 0x87e0904400a8ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
5853 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
5854 return 0x87e0904400a8ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
5855 __bdk_csr_fatal("GSERX_LANEX_TX_CFG_0", 2, a, b, 0, 0);
5856 }
5857
5858 #define typedef_BDK_GSERX_LANEX_TX_CFG_0(a,b) bdk_gserx_lanex_tx_cfg_0_t
5859 #define bustype_BDK_GSERX_LANEX_TX_CFG_0(a,b) BDK_CSR_TYPE_RSL
5860 #define basename_BDK_GSERX_LANEX_TX_CFG_0(a,b) "GSERX_LANEX_TX_CFG_0"
5861 #define device_bar_BDK_GSERX_LANEX_TX_CFG_0(a,b) 0x0 /* PF_BAR0 */
5862 #define busnum_BDK_GSERX_LANEX_TX_CFG_0(a,b) (a)
5863 #define arguments_BDK_GSERX_LANEX_TX_CFG_0(a,b) (a),(b),-1,-1
5864
5865 /**
5866 * Register (RSL) gser#_lane#_tx_cfg_1
5867 *
5868 * GSER Lane TX Configuration 1 Register
5869 * These registers are reset by hardware only during chip cold reset. The
5870 * values of the CSR fields in these registers do not change during chip
5871 * warm or soft resets.
5872 */
5873 union bdk_gserx_lanex_tx_cfg_1
5874 {
5875 uint64_t u;
5876 struct bdk_gserx_lanex_tx_cfg_1_s
5877 {
5878 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5879 uint64_t reserved_15_63 : 49;
5880 uint64_t tx_widthsel_ovrrd_en : 1; /**< [ 14: 14](R/W) Override enable for pcs_sds_txX_widthsel, TX parallel interface width setting. */
5881 uint64_t tx_widthsel_ovrrd_val : 2; /**< [ 13: 12](R/W) Override value for pcs_sds_widthsel, TX parallel interface width setting.
5882 0x0 = 8-bit (not supported).
5883 0x1 = 10-bit (not supported).
5884 0x2 = 16-bit (for PCIe Gen3 8Gb only).
5885 0x3 = 20-bit. */
5886 uint64_t tx_vboost_en_ovrrd_en : 1; /**< [ 11: 11](R/W) Override enable for pcs_sds_txX_vboost_en, TX vboost mode enable. */
5887 uint64_t tx_turbo_en_ovrrd_en : 1; /**< [ 10: 10](R/W) Override enable for pcs_sds_txX_turbo_en, Turbo mode enable. */
5888 uint64_t tx_swing_ovrrd_en : 1; /**< [ 9: 9](R/W) Override enable for pcs_sds_txX_swing, TX swing. See
5889 GSER()_LANE()_TX_CFG_0[CFG_TX_SWING].
5890
5891 It is recommended to not use the GSER()_LANE()_TX_CFG_0[CFG_TX_SWING],
5892 GSER()_LANE()_TX_CFG_1[TX_SWING_OVRRD_EN,TX_PREMPTAP_OVRRD_VAL], or
5893 GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP] override registers for 10BASE-KR
5894 or PCIe links in which the transmitter is adapted by the respective
5895 hardware-controlled link training protocols.
5896
5897 A transmit swing change should be followed by a control interface
5898 configuration over-ride to force the new setting - see
5899 GSER()_LANE()_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ]. */
5900 uint64_t tx_premptap_ovrrd_val : 1; /**< [ 8: 8](R/W) Override enable for pcs_sds_txX_preemptap, preemphasis control. When
5901 over-riding, [TX_PREMPTAP_OVRRD_VAL] should be set and
5902 GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP] has the precursor and
5903 postcursor values.
5904
5905 It is recommended to not use the GSER()_LANE()_TX_CFG_0[CFG_TX_SWING],
5906 GSER()_LANE()_TX_CFG_1[TX_SWING_OVRRD_EN,TX_PREMPTAP_OVRRD_VAL], or
5907 GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP] override registers for 10BASE-KR
5908 or PCIe links in which the transmitter is adapted by the respective
5909 hardware-controlled link training protocols.
5910
5911 A preemphasis control change should be followed by a control
5912 interface configuration override to force the new setting - see
5913 GSER()_LANE()_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ]. */
5914 uint64_t tx_elec_idle_ovrrd_en : 1; /**< [ 7: 7](R/W) Override enable for pcs_sds_txX_elec_idle, TX electrical idle. */
5915 uint64_t smpl_rate_ovrrd_en : 1; /**< [ 6: 6](R/W) Override enable for TX power state machine sample rate. When asserted, the TX sample is
5916 specified from SMPL_RATE_OVRRD_VAL and the TX Power state machine control signal is
5917 ignored. */
5918 uint64_t smpl_rate_ovrrd_val : 3; /**< [ 5: 3](R/W) Specifies the sample rate (strobe assertion) relative to mac_pcs_txX_clk when
5919 SMPL_RATE_OVRRD_EN is asserted.
5920 0x0 = full rate.
5921 0x1 = 1/2 data rate.
5922 0x2 = 1/4 data rate.
5923 0x3 = 1/8 data rate.
5924 0x4 = 1/16 data rate.
5925 0x5-7 = Reserved. */
5926 uint64_t tx_datarate_ovrrd_en : 1; /**< [ 2: 2](R/W) Override enable for RX power state machine data rate signal. When set, rx_datarate is
5927 specified from [TX_DATARATE_OVRRD_VAL] and the RX power state machine control signal is
5928 ignored. */
5929 uint64_t tx_datarate_ovrrd_val : 2; /**< [ 1: 0](R/W) Specifies the TX data rate when TX_DATARATE_OVRRD_EN is asserted.
5930 0x0 = full rate.
5931 0x1 = 1/2 data rate.
5932 0x2 = 1/4 data rate.
5933 0x3 = 1/8 data rate. */
5934 #else /* Word 0 - Little Endian */
5935 uint64_t tx_datarate_ovrrd_val : 2; /**< [ 1: 0](R/W) Specifies the TX data rate when TX_DATARATE_OVRRD_EN is asserted.
5936 0x0 = full rate.
5937 0x1 = 1/2 data rate.
5938 0x2 = 1/4 data rate.
5939 0x3 = 1/8 data rate. */
5940 uint64_t tx_datarate_ovrrd_en : 1; /**< [ 2: 2](R/W) Override enable for RX power state machine data rate signal. When set, rx_datarate is
5941 specified from [TX_DATARATE_OVRRD_VAL] and the RX power state machine control signal is
5942 ignored. */
5943 uint64_t smpl_rate_ovrrd_val : 3; /**< [ 5: 3](R/W) Specifies the sample rate (strobe assertion) relative to mac_pcs_txX_clk when
5944 SMPL_RATE_OVRRD_EN is asserted.
5945 0x0 = full rate.
5946 0x1 = 1/2 data rate.
5947 0x2 = 1/4 data rate.
5948 0x3 = 1/8 data rate.
5949 0x4 = 1/16 data rate.
5950 0x5-7 = Reserved. */
5951 uint64_t smpl_rate_ovrrd_en : 1; /**< [ 6: 6](R/W) Override enable for TX power state machine sample rate. When asserted, the TX sample is
5952 specified from SMPL_RATE_OVRRD_VAL and the TX Power state machine control signal is
5953 ignored. */
5954 uint64_t tx_elec_idle_ovrrd_en : 1; /**< [ 7: 7](R/W) Override enable for pcs_sds_txX_elec_idle, TX electrical idle. */
5955 uint64_t tx_premptap_ovrrd_val : 1; /**< [ 8: 8](R/W) Override enable for pcs_sds_txX_preemptap, preemphasis control. When
5956 over-riding, [TX_PREMPTAP_OVRRD_VAL] should be set and
5957 GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP] has the precursor and
5958 postcursor values.
5959
5960 It is recommended to not use the GSER()_LANE()_TX_CFG_0[CFG_TX_SWING],
5961 GSER()_LANE()_TX_CFG_1[TX_SWING_OVRRD_EN,TX_PREMPTAP_OVRRD_VAL], or
5962 GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP] override registers for 10BASE-KR
5963 or PCIe links in which the transmitter is adapted by the respective
5964 hardware-controlled link training protocols.
5965
5966 A preemphasis control change should be followed by a control
5967 interface configuration override to force the new setting - see
5968 GSER()_LANE()_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ]. */
5969 uint64_t tx_swing_ovrrd_en : 1; /**< [ 9: 9](R/W) Override enable for pcs_sds_txX_swing, TX swing. See
5970 GSER()_LANE()_TX_CFG_0[CFG_TX_SWING].
5971
5972 It is recommended to not use the GSER()_LANE()_TX_CFG_0[CFG_TX_SWING],
5973 GSER()_LANE()_TX_CFG_1[TX_SWING_OVRRD_EN,TX_PREMPTAP_OVRRD_VAL], or
5974 GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP] override registers for 10BASE-KR
5975 or PCIe links in which the transmitter is adapted by the respective
5976 hardware-controlled link training protocols.
5977
5978 A transmit swing change should be followed by a control interface
5979 configuration over-ride to force the new setting - see
5980 GSER()_LANE()_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ]. */
5981 uint64_t tx_turbo_en_ovrrd_en : 1; /**< [ 10: 10](R/W) Override enable for pcs_sds_txX_turbo_en, Turbo mode enable. */
5982 uint64_t tx_vboost_en_ovrrd_en : 1; /**< [ 11: 11](R/W) Override enable for pcs_sds_txX_vboost_en, TX vboost mode enable. */
5983 uint64_t tx_widthsel_ovrrd_val : 2; /**< [ 13: 12](R/W) Override value for pcs_sds_widthsel, TX parallel interface width setting.
5984 0x0 = 8-bit (not supported).
5985 0x1 = 10-bit (not supported).
5986 0x2 = 16-bit (for PCIe Gen3 8Gb only).
5987 0x3 = 20-bit. */
5988 uint64_t tx_widthsel_ovrrd_en : 1; /**< [ 14: 14](R/W) Override enable for pcs_sds_txX_widthsel, TX parallel interface width setting. */
5989 uint64_t reserved_15_63 : 49;
5990 #endif /* Word 0 - End */
5991 } s;
5992 /* struct bdk_gserx_lanex_tx_cfg_1_s cn; */
5993 };
5994 typedef union bdk_gserx_lanex_tx_cfg_1 bdk_gserx_lanex_tx_cfg_1_t;
5995
5996 static inline uint64_t BDK_GSERX_LANEX_TX_CFG_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_TX_CFG_1(unsigned long a,unsigned long b)5997 static inline uint64_t BDK_GSERX_LANEX_TX_CFG_1(unsigned long a, unsigned long b)
5998 {
5999 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
6000 return 0x87e0904400b0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
6001 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
6002 return 0x87e0904400b0ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
6003 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
6004 return 0x87e0904400b0ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
6005 __bdk_csr_fatal("GSERX_LANEX_TX_CFG_1", 2, a, b, 0, 0);
6006 }
6007
6008 #define typedef_BDK_GSERX_LANEX_TX_CFG_1(a,b) bdk_gserx_lanex_tx_cfg_1_t
6009 #define bustype_BDK_GSERX_LANEX_TX_CFG_1(a,b) BDK_CSR_TYPE_RSL
6010 #define basename_BDK_GSERX_LANEX_TX_CFG_1(a,b) "GSERX_LANEX_TX_CFG_1"
6011 #define device_bar_BDK_GSERX_LANEX_TX_CFG_1(a,b) 0x0 /* PF_BAR0 */
6012 #define busnum_BDK_GSERX_LANEX_TX_CFG_1(a,b) (a)
6013 #define arguments_BDK_GSERX_LANEX_TX_CFG_1(a,b) (a),(b),-1,-1
6014
6015 /**
6016 * Register (RSL) gser#_lane#_tx_cfg_2
6017 *
6018 * GSER Lane TX Configuration 2 Register
6019 * These registers are for diagnostic use only. These registers are reset by hardware only during
6020 * chip cold reset. The values of the CSR fields in these registers do not change during chip
6021 * warm or soft resets.
6022 */
6023 union bdk_gserx_lanex_tx_cfg_2
6024 {
6025 uint64_t u;
6026 struct bdk_gserx_lanex_tx_cfg_2_s
6027 {
6028 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6029 uint64_t reserved_16_63 : 48;
6030 uint64_t pcs_sds_tx_dcc_en : 1; /**< [ 15: 15](R/W) DCC enable. */
6031 uint64_t reserved_3_14 : 12;
6032 uint64_t rcvr_test_ovrrd_en : 1; /**< [ 2: 2](R/W) Override RX detect disable and test pulse. */
6033 uint64_t rcvr_test_ovrrd_val : 1; /**< [ 1: 1](R/W) Override value for RX detect test pulse; used to create a pulse during which the receiver
6034 detect test operation is performed. */
6035 uint64_t tx_rx_detect_dis_ovrrd_val : 1;/**< [ 0: 0](R/W) Override value of RX detect disable. */
6036 #else /* Word 0 - Little Endian */
6037 uint64_t tx_rx_detect_dis_ovrrd_val : 1;/**< [ 0: 0](R/W) Override value of RX detect disable. */
6038 uint64_t rcvr_test_ovrrd_val : 1; /**< [ 1: 1](R/W) Override value for RX detect test pulse; used to create a pulse during which the receiver
6039 detect test operation is performed. */
6040 uint64_t rcvr_test_ovrrd_en : 1; /**< [ 2: 2](R/W) Override RX detect disable and test pulse. */
6041 uint64_t reserved_3_14 : 12;
6042 uint64_t pcs_sds_tx_dcc_en : 1; /**< [ 15: 15](R/W) DCC enable. */
6043 uint64_t reserved_16_63 : 48;
6044 #endif /* Word 0 - End */
6045 } s;
6046 /* struct bdk_gserx_lanex_tx_cfg_2_s cn; */
6047 };
6048 typedef union bdk_gserx_lanex_tx_cfg_2 bdk_gserx_lanex_tx_cfg_2_t;
6049
6050 static inline uint64_t BDK_GSERX_LANEX_TX_CFG_2(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_TX_CFG_2(unsigned long a,unsigned long b)6051 static inline uint64_t BDK_GSERX_LANEX_TX_CFG_2(unsigned long a, unsigned long b)
6052 {
6053 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
6054 return 0x87e0904400b8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
6055 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
6056 return 0x87e0904400b8ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
6057 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
6058 return 0x87e0904400b8ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
6059 __bdk_csr_fatal("GSERX_LANEX_TX_CFG_2", 2, a, b, 0, 0);
6060 }
6061
6062 #define typedef_BDK_GSERX_LANEX_TX_CFG_2(a,b) bdk_gserx_lanex_tx_cfg_2_t
6063 #define bustype_BDK_GSERX_LANEX_TX_CFG_2(a,b) BDK_CSR_TYPE_RSL
6064 #define basename_BDK_GSERX_LANEX_TX_CFG_2(a,b) "GSERX_LANEX_TX_CFG_2"
6065 #define device_bar_BDK_GSERX_LANEX_TX_CFG_2(a,b) 0x0 /* PF_BAR0 */
6066 #define busnum_BDK_GSERX_LANEX_TX_CFG_2(a,b) (a)
6067 #define arguments_BDK_GSERX_LANEX_TX_CFG_2(a,b) (a),(b),-1,-1
6068
6069 /**
6070 * Register (RSL) gser#_lane#_tx_cfg_3
6071 *
6072 * GSER Lane TX Configuration 3 Register
6073 * These registers are for diagnostic use only. These registers are reset by hardware only during
6074 * chip cold reset. The values of the CSR fields in these registers do not change during chip
6075 * warm or soft resets.
6076 */
6077 union bdk_gserx_lanex_tx_cfg_3
6078 {
6079 uint64_t u;
6080 struct bdk_gserx_lanex_tx_cfg_3_s
6081 {
6082 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6083 uint64_t reserved_15_63 : 49;
6084 uint64_t cfg_tx_vboost_en : 1; /**< [ 14: 14](R/W) Specifies the value of TX VBoost enable when
6085 GSER()_LANE()_TX_CFG_1[TX_VBOOST_EN_OVRRD_EN] is asserted. */
6086 uint64_t reserved_7_13 : 7;
6087 uint64_t pcs_sds_tx_gain : 3; /**< [ 6: 4](R/W/H) TX gain. For debug use only. */
6088 uint64_t pcs_sds_tx_srate_sel : 3; /**< [ 3: 1](R/W/H) Reserved. */
6089 uint64_t cfg_tx_turbo_en : 1; /**< [ 0: 0](R/W) Specifies value of TX turbo enable when GSER()_LANE()_TX_CFG_1[TX_TURBO_EN] is set. */
6090 #else /* Word 0 - Little Endian */
6091 uint64_t cfg_tx_turbo_en : 1; /**< [ 0: 0](R/W) Specifies value of TX turbo enable when GSER()_LANE()_TX_CFG_1[TX_TURBO_EN] is set. */
6092 uint64_t pcs_sds_tx_srate_sel : 3; /**< [ 3: 1](R/W/H) Reserved. */
6093 uint64_t pcs_sds_tx_gain : 3; /**< [ 6: 4](R/W/H) TX gain. For debug use only. */
6094 uint64_t reserved_7_13 : 7;
6095 uint64_t cfg_tx_vboost_en : 1; /**< [ 14: 14](R/W) Specifies the value of TX VBoost enable when
6096 GSER()_LANE()_TX_CFG_1[TX_VBOOST_EN_OVRRD_EN] is asserted. */
6097 uint64_t reserved_15_63 : 49;
6098 #endif /* Word 0 - End */
6099 } s;
6100 /* struct bdk_gserx_lanex_tx_cfg_3_s cn; */
6101 };
6102 typedef union bdk_gserx_lanex_tx_cfg_3 bdk_gserx_lanex_tx_cfg_3_t;
6103
6104 static inline uint64_t BDK_GSERX_LANEX_TX_CFG_3(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_TX_CFG_3(unsigned long a,unsigned long b)6105 static inline uint64_t BDK_GSERX_LANEX_TX_CFG_3(unsigned long a, unsigned long b)
6106 {
6107 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
6108 return 0x87e0904400c0ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
6109 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
6110 return 0x87e0904400c0ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
6111 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
6112 return 0x87e0904400c0ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
6113 __bdk_csr_fatal("GSERX_LANEX_TX_CFG_3", 2, a, b, 0, 0);
6114 }
6115
6116 #define typedef_BDK_GSERX_LANEX_TX_CFG_3(a,b) bdk_gserx_lanex_tx_cfg_3_t
6117 #define bustype_BDK_GSERX_LANEX_TX_CFG_3(a,b) BDK_CSR_TYPE_RSL
6118 #define basename_BDK_GSERX_LANEX_TX_CFG_3(a,b) "GSERX_LANEX_TX_CFG_3"
6119 #define device_bar_BDK_GSERX_LANEX_TX_CFG_3(a,b) 0x0 /* PF_BAR0 */
6120 #define busnum_BDK_GSERX_LANEX_TX_CFG_3(a,b) (a)
6121 #define arguments_BDK_GSERX_LANEX_TX_CFG_3(a,b) (a),(b),-1,-1
6122
6123 /**
6124 * Register (RSL) gser#_lane#_tx_pre_emphasis
6125 *
6126 * GSER Lane TX Configuration Preemphasis Register
6127 * These registers are reset by hardware only during chip cold reset. The
6128 * values of the CSR fields in these registers do not change during chip
6129 * warm or soft resets.
6130 */
6131 union bdk_gserx_lanex_tx_pre_emphasis
6132 {
6133 uint64_t u;
6134 struct bdk_gserx_lanex_tx_pre_emphasis_s
6135 {
6136 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6137 uint64_t reserved_9_63 : 55;
6138 uint64_t cfg_tx_premptap : 9; /**< [ 8: 0](R/W) Override preemphasis control. Applies when
6139 GSER()_LANE()_TX_CFG_1[TX_PREMPTAP_OVRRD_VAL] is asserted.
6140 \<8:4\> = Postcursor.
6141 \<3:0\> = Precursor.
6142
6143 It is recommended to not use the GSER()_LANE()_TX_CFG_0[CFG_TX_SWING],
6144 GSER()_LANE()_TX_CFG_1[TX_SWING_OVRRD_EN,TX_PREMPTAP_OVRRD_VAL], or
6145 GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP] override registers for 10BASE-KR
6146 or PCIe links in which the transmitter is adapted by the respective
6147 hardware-controlled link training protocols.
6148
6149 The [CFG_TX_PREEMPTAP] value for transmitter preemphasis and
6150 postemphasis should be derived from signal integrity simulations
6151 with IBIS-AMI models supplied by Cavium.
6152
6153 A preemphasis control change should be followed by a control interface
6154 configuration over-ride to force the new setting - see
6155 GSER()_LANE()_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ]. */
6156 #else /* Word 0 - Little Endian */
6157 uint64_t cfg_tx_premptap : 9; /**< [ 8: 0](R/W) Override preemphasis control. Applies when
6158 GSER()_LANE()_TX_CFG_1[TX_PREMPTAP_OVRRD_VAL] is asserted.
6159 \<8:4\> = Postcursor.
6160 \<3:0\> = Precursor.
6161
6162 It is recommended to not use the GSER()_LANE()_TX_CFG_0[CFG_TX_SWING],
6163 GSER()_LANE()_TX_CFG_1[TX_SWING_OVRRD_EN,TX_PREMPTAP_OVRRD_VAL], or
6164 GSER()_LANE()_TX_PRE_EMPHASIS[CFG_TX_PREMPTAP] override registers for 10BASE-KR
6165 or PCIe links in which the transmitter is adapted by the respective
6166 hardware-controlled link training protocols.
6167
6168 The [CFG_TX_PREEMPTAP] value for transmitter preemphasis and
6169 postemphasis should be derived from signal integrity simulations
6170 with IBIS-AMI models supplied by Cavium.
6171
6172 A preemphasis control change should be followed by a control interface
6173 configuration over-ride to force the new setting - see
6174 GSER()_LANE()_PCS_CTLIFC_2[CTLIFC_OVRRD_REQ]. */
6175 uint64_t reserved_9_63 : 55;
6176 #endif /* Word 0 - End */
6177 } s;
6178 /* struct bdk_gserx_lanex_tx_pre_emphasis_s cn; */
6179 };
6180 typedef union bdk_gserx_lanex_tx_pre_emphasis bdk_gserx_lanex_tx_pre_emphasis_t;
6181
6182 static inline uint64_t BDK_GSERX_LANEX_TX_PRE_EMPHASIS(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANEX_TX_PRE_EMPHASIS(unsigned long a,unsigned long b)6183 static inline uint64_t BDK_GSERX_LANEX_TX_PRE_EMPHASIS(unsigned long a, unsigned long b)
6184 {
6185 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
6186 return 0x87e0904400c8ll + 0x1000000ll * ((a) & 0x3) + 0x100000ll * ((b) & 0x1);
6187 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3)))
6188 return 0x87e0904400c8ll + 0x1000000ll * ((a) & 0x7) + 0x100000ll * ((b) & 0x3);
6189 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3)))
6190 return 0x87e0904400c8ll + 0x1000000ll * ((a) & 0xf) + 0x100000ll * ((b) & 0x3);
6191 __bdk_csr_fatal("GSERX_LANEX_TX_PRE_EMPHASIS", 2, a, b, 0, 0);
6192 }
6193
6194 #define typedef_BDK_GSERX_LANEX_TX_PRE_EMPHASIS(a,b) bdk_gserx_lanex_tx_pre_emphasis_t
6195 #define bustype_BDK_GSERX_LANEX_TX_PRE_EMPHASIS(a,b) BDK_CSR_TYPE_RSL
6196 #define basename_BDK_GSERX_LANEX_TX_PRE_EMPHASIS(a,b) "GSERX_LANEX_TX_PRE_EMPHASIS"
6197 #define device_bar_BDK_GSERX_LANEX_TX_PRE_EMPHASIS(a,b) 0x0 /* PF_BAR0 */
6198 #define busnum_BDK_GSERX_LANEX_TX_PRE_EMPHASIS(a,b) (a)
6199 #define arguments_BDK_GSERX_LANEX_TX_PRE_EMPHASIS(a,b) (a),(b),-1,-1
6200
6201 /**
6202 * Register (RSL) gser#_lane_lpbken
6203 *
6204 * GSER Lane Loopback Enable Register
6205 * These registers are reset by hardware only during chip cold reset. The values of the CSR
6206 * fields in these registers do not change during chip warm or soft resets.
6207 */
6208 union bdk_gserx_lane_lpbken
6209 {
6210 uint64_t u;
6211 struct bdk_gserx_lane_lpbken_s
6212 {
6213 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6214 uint64_t reserved_4_63 : 60;
6215 uint64_t lpbken : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode. When asserted in P0 state,
6216 allows per-lane TX-to-RX serial loopback activation.
6217 \<3\>: Lane 3. Reserved.
6218 \<2\>: Lane 2. Reserved.
6219 \<1\>: Lane 1.
6220 \<0\>: Lane 0. */
6221 #else /* Word 0 - Little Endian */
6222 uint64_t lpbken : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode. When asserted in P0 state,
6223 allows per-lane TX-to-RX serial loopback activation.
6224 \<3\>: Lane 3. Reserved.
6225 \<2\>: Lane 2. Reserved.
6226 \<1\>: Lane 1.
6227 \<0\>: Lane 0. */
6228 uint64_t reserved_4_63 : 60;
6229 #endif /* Word 0 - End */
6230 } s;
6231 /* struct bdk_gserx_lane_lpbken_s cn81xx; */
6232 struct bdk_gserx_lane_lpbken_cn88xx
6233 {
6234 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6235 uint64_t reserved_4_63 : 60;
6236 uint64_t lpbken : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode (including all CCPI links). When asserted in
6237 P0
6238 state,
6239 allows per-lane TX-to-RX serial loopback activation.
6240 \<3\>: Lane 3.
6241 \<2\>: Lane 2.
6242 \<1\>: Lane 1.
6243 \<0\>: Lane 0. */
6244 #else /* Word 0 - Little Endian */
6245 uint64_t lpbken : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode (including all CCPI links). When asserted in
6246 P0
6247 state,
6248 allows per-lane TX-to-RX serial loopback activation.
6249 \<3\>: Lane 3.
6250 \<2\>: Lane 2.
6251 \<1\>: Lane 1.
6252 \<0\>: Lane 0. */
6253 uint64_t reserved_4_63 : 60;
6254 #endif /* Word 0 - End */
6255 } cn88xx;
6256 struct bdk_gserx_lane_lpbken_cn83xx
6257 {
6258 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6259 uint64_t reserved_4_63 : 60;
6260 uint64_t lpbken : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode. When asserted in
6261 P0 state, allows per lane TX-to-RX serial loopback activation.
6262 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
6263 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
6264 \<1\>: Lane 1.
6265 \<0\>: Lane 0. */
6266 #else /* Word 0 - Little Endian */
6267 uint64_t lpbken : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode. When asserted in
6268 P0 state, allows per lane TX-to-RX serial loopback activation.
6269 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
6270 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
6271 \<1\>: Lane 1.
6272 \<0\>: Lane 0. */
6273 uint64_t reserved_4_63 : 60;
6274 #endif /* Word 0 - End */
6275 } cn83xx;
6276 };
6277 typedef union bdk_gserx_lane_lpbken bdk_gserx_lane_lpbken_t;
6278
6279 static inline uint64_t BDK_GSERX_LANE_LPBKEN(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_LPBKEN(unsigned long a)6280 static inline uint64_t BDK_GSERX_LANE_LPBKEN(unsigned long a)
6281 {
6282 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
6283 return 0x87e090000110ll + 0x1000000ll * ((a) & 0x3);
6284 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
6285 return 0x87e090000110ll + 0x1000000ll * ((a) & 0x7);
6286 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
6287 return 0x87e090000110ll + 0x1000000ll * ((a) & 0xf);
6288 __bdk_csr_fatal("GSERX_LANE_LPBKEN", 1, a, 0, 0, 0);
6289 }
6290
6291 #define typedef_BDK_GSERX_LANE_LPBKEN(a) bdk_gserx_lane_lpbken_t
6292 #define bustype_BDK_GSERX_LANE_LPBKEN(a) BDK_CSR_TYPE_RSL
6293 #define basename_BDK_GSERX_LANE_LPBKEN(a) "GSERX_LANE_LPBKEN"
6294 #define device_bar_BDK_GSERX_LANE_LPBKEN(a) 0x0 /* PF_BAR0 */
6295 #define busnum_BDK_GSERX_LANE_LPBKEN(a) (a)
6296 #define arguments_BDK_GSERX_LANE_LPBKEN(a) (a),-1,-1,-1
6297
6298 /**
6299 * Register (RSL) gser#_lane_mode
6300 *
6301 * GSER Lane Mode Register
6302 * These registers are reset by hardware only during chip cold reset. The values of the CSR
6303 * fields in these registers do not change during chip warm or soft resets.
6304 */
6305 union bdk_gserx_lane_mode
6306 {
6307 uint64_t u;
6308 struct bdk_gserx_lane_mode_s
6309 {
6310 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6311 uint64_t reserved_4_63 : 60;
6312 uint64_t lmode : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode, used to index into the PHY
6313 table to select electrical specs and link rate. Note that the PHY table can be modified
6314 such that any supported link rate can be derived regardless of the configured LMODE.
6315
6316 0x0: R_25G_REFCLK100.
6317 0x1: R_5G_REFCLK100.
6318 0x2: R_8G_REFCLK100.
6319 0x3: R_125G_REFCLK15625_KX (not supported).
6320 0x4: R_3125G_REFCLK15625_XAUI.
6321 0x5: R_103125G_REFCLK15625_KR.
6322 0x6: R_125G_REFCLK15625_SGMII.
6323 0x7: R_5G_REFCLK15625_QSGMII.
6324 0x8: R_625G_REFCLK15625_RXAUI.
6325 0x9: R_25G_REFCLK125.
6326 0xA: R_5G_REFCLK125.
6327 0xB: R_8G_REFCLK125.
6328 0xC - 0xF: Reserved.
6329
6330 This register is not used for PCIE configurations. For BGX links, this register
6331 defaults to R_625G_REFCLK15625_RXAUI.
6332
6333 It is recommended that the PHY be in reset when reconfiguring the [LMODE]
6334 (GSER()_PHY_CTL[PHY_RESET] is set).
6335
6336 Once the [LMODE] has been configured, and the PHY is out of reset, the table entries for
6337 the
6338 selected [LMODE] must be updated to reflect the reference clock speed. Refer to the
6339 register
6340 description and index into the table using the rate and reference speed to obtain the
6341 recommended values.
6342
6343 _ Write GSER()_PLL_P()_MODE_0.
6344 _ Write GSER()_PLL_P()_MODE_1.
6345 _ Write GSER()_LANE_P()_MODE_0.
6346 _ Write GSER()_LANE_P()_MODE_1.
6347
6348 where in "P(z)", z equals [LMODE]. */
6349 #else /* Word 0 - Little Endian */
6350 uint64_t lmode : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode, used to index into the PHY
6351 table to select electrical specs and link rate. Note that the PHY table can be modified
6352 such that any supported link rate can be derived regardless of the configured LMODE.
6353
6354 0x0: R_25G_REFCLK100.
6355 0x1: R_5G_REFCLK100.
6356 0x2: R_8G_REFCLK100.
6357 0x3: R_125G_REFCLK15625_KX (not supported).
6358 0x4: R_3125G_REFCLK15625_XAUI.
6359 0x5: R_103125G_REFCLK15625_KR.
6360 0x6: R_125G_REFCLK15625_SGMII.
6361 0x7: R_5G_REFCLK15625_QSGMII.
6362 0x8: R_625G_REFCLK15625_RXAUI.
6363 0x9: R_25G_REFCLK125.
6364 0xA: R_5G_REFCLK125.
6365 0xB: R_8G_REFCLK125.
6366 0xC - 0xF: Reserved.
6367
6368 This register is not used for PCIE configurations. For BGX links, this register
6369 defaults to R_625G_REFCLK15625_RXAUI.
6370
6371 It is recommended that the PHY be in reset when reconfiguring the [LMODE]
6372 (GSER()_PHY_CTL[PHY_RESET] is set).
6373
6374 Once the [LMODE] has been configured, and the PHY is out of reset, the table entries for
6375 the
6376 selected [LMODE] must be updated to reflect the reference clock speed. Refer to the
6377 register
6378 description and index into the table using the rate and reference speed to obtain the
6379 recommended values.
6380
6381 _ Write GSER()_PLL_P()_MODE_0.
6382 _ Write GSER()_PLL_P()_MODE_1.
6383 _ Write GSER()_LANE_P()_MODE_0.
6384 _ Write GSER()_LANE_P()_MODE_1.
6385
6386 where in "P(z)", z equals [LMODE]. */
6387 uint64_t reserved_4_63 : 60;
6388 #endif /* Word 0 - End */
6389 } s;
6390 /* struct bdk_gserx_lane_mode_s cn81xx; */
6391 struct bdk_gserx_lane_mode_cn88xx
6392 {
6393 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6394 uint64_t reserved_4_63 : 60;
6395 uint64_t lmode : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode (including all CCPI links), used to index into
6396 the PHY
6397 table to select electrical specs and link rate. Note that the PHY table can be modified
6398 such that any supported link rate can be derived regardless of the configured LMODE.
6399
6400 0x0: R_25G_REFCLK100.
6401 0x1: R_5G_REFCLK100.
6402 0x2: R_8G_REFCLK100.
6403 0x3: R_125G_REFCLK15625_KX (not supported).
6404 0x4: R_3125G_REFCLK15625_XAUI.
6405 0x5: R_103125G_REFCLK15625_KR.
6406 0x6: R_125G_REFCLK15625_SGMII.
6407 0x7: R_5G_REFCLK15625_QSGMII (not supported).
6408 0x8: R_625G_REFCLK15625_RXAUI.
6409 0x9: R_25G_REFCLK125.
6410 0xA: R_5G_REFCLK125.
6411 0xB: R_8G_REFCLK125.
6412 0xC - 0xF: Reserved.
6413
6414 This register is not used for PCIE configurations. For non-CCPI links, this register
6415 defaults to R_625G_REFCLK15625_RXAUI. For CCPI links, the value is mapped at reset from
6416 the
6417 GSER()_SPD and the appropriate table updates are performed so the rate is obtained for the
6418 particular reference clock.
6419
6420 It is recommended that the PHY be in reset when reconfiguring the [LMODE]
6421 (GSER()_PHY_CTL[PHY_RESET] is set).
6422
6423 Once the [LMODE] has been configured, and the PHY is out of reset, the table entries for
6424 the
6425 selected [LMODE] must be updated to reflect the reference clock speed. Refer to the
6426 register
6427 description and index into the table using the rate and reference speed to obtain the
6428 recommended values.
6429
6430 _ Write GSER()_PLL_P()_MODE_0.
6431 _ Write GSER()_PLL_P()_MODE_1.
6432 _ Write GSER()_LANE_P()_MODE_0.
6433 _ Write GSER()_LANE_P()_MODE_1.
6434
6435 where in "P(z)", z equals [LMODE]. */
6436 #else /* Word 0 - Little Endian */
6437 uint64_t lmode : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode (including all CCPI links), used to index into
6438 the PHY
6439 table to select electrical specs and link rate. Note that the PHY table can be modified
6440 such that any supported link rate can be derived regardless of the configured LMODE.
6441
6442 0x0: R_25G_REFCLK100.
6443 0x1: R_5G_REFCLK100.
6444 0x2: R_8G_REFCLK100.
6445 0x3: R_125G_REFCLK15625_KX (not supported).
6446 0x4: R_3125G_REFCLK15625_XAUI.
6447 0x5: R_103125G_REFCLK15625_KR.
6448 0x6: R_125G_REFCLK15625_SGMII.
6449 0x7: R_5G_REFCLK15625_QSGMII (not supported).
6450 0x8: R_625G_REFCLK15625_RXAUI.
6451 0x9: R_25G_REFCLK125.
6452 0xA: R_5G_REFCLK125.
6453 0xB: R_8G_REFCLK125.
6454 0xC - 0xF: Reserved.
6455
6456 This register is not used for PCIE configurations. For non-CCPI links, this register
6457 defaults to R_625G_REFCLK15625_RXAUI. For CCPI links, the value is mapped at reset from
6458 the
6459 GSER()_SPD and the appropriate table updates are performed so the rate is obtained for the
6460 particular reference clock.
6461
6462 It is recommended that the PHY be in reset when reconfiguring the [LMODE]
6463 (GSER()_PHY_CTL[PHY_RESET] is set).
6464
6465 Once the [LMODE] has been configured, and the PHY is out of reset, the table entries for
6466 the
6467 selected [LMODE] must be updated to reflect the reference clock speed. Refer to the
6468 register
6469 description and index into the table using the rate and reference speed to obtain the
6470 recommended values.
6471
6472 _ Write GSER()_PLL_P()_MODE_0.
6473 _ Write GSER()_PLL_P()_MODE_1.
6474 _ Write GSER()_LANE_P()_MODE_0.
6475 _ Write GSER()_LANE_P()_MODE_1.
6476
6477 where in "P(z)", z equals [LMODE]. */
6478 uint64_t reserved_4_63 : 60;
6479 #endif /* Word 0 - End */
6480 } cn88xx;
6481 struct bdk_gserx_lane_mode_cn83xx
6482 {
6483 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6484 uint64_t reserved_4_63 : 60;
6485 uint64_t lmode : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode, used to index into the PHY
6486 table to select electrical specs and link rate. Note that the PHY table can be modified
6487 such that any supported link rate can be derived regardless of the configured LMODE.
6488
6489 0x0: R_25G_REFCLK100.
6490 0x1: R_5G_REFCLK100.
6491 0x2: R_8G_REFCLK100.
6492 0x3: R_125G_REFCLK15625_KX (not supported).
6493 0x4: R_3125G_REFCLK15625_XAUI.
6494 0x5: R_103125G_REFCLK15625_KR.
6495 0x6: R_125G_REFCLK15625_SGMII.
6496 0x7: R_5G_REFCLK15625_QSGMII.
6497 0x8: R_625G_REFCLK15625_RXAUI.
6498 0x9: R_25G_REFCLK125.
6499 0xA: R_5G_REFCLK125.
6500 0xB: R_8G_REFCLK125.
6501 0xC - 0xF: Reserved.
6502
6503 This register is not used for PCIE configurations. This register
6504 defaults to R_625G_REFCLK15625_RXAUI.
6505
6506 It is recommended that the PHY be in reset when reconfiguring the [LMODE]
6507 (GSER()_PHY_CTL[PHY_RESET] is set).
6508
6509 Once the [LMODE] has been configured, and the PHY is out of reset, the table entries for
6510 the
6511 selected [LMODE] must be updated to reflect the reference clock speed. Refer to the
6512 register
6513 description and index into the table using the rate and reference speed to obtain the
6514 recommended values.
6515
6516 _ Write GSER()_PLL_P()_MODE_0.
6517 _ Write GSER()_PLL_P()_MODE_1.
6518 _ Write GSER()_LANE_P()_MODE_0.
6519 _ Write GSER()_LANE_P()_MODE_1.
6520
6521 where in "P(z)", z equals [LMODE]. */
6522 #else /* Word 0 - Little Endian */
6523 uint64_t lmode : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode, used to index into the PHY
6524 table to select electrical specs and link rate. Note that the PHY table can be modified
6525 such that any supported link rate can be derived regardless of the configured LMODE.
6526
6527 0x0: R_25G_REFCLK100.
6528 0x1: R_5G_REFCLK100.
6529 0x2: R_8G_REFCLK100.
6530 0x3: R_125G_REFCLK15625_KX (not supported).
6531 0x4: R_3125G_REFCLK15625_XAUI.
6532 0x5: R_103125G_REFCLK15625_KR.
6533 0x6: R_125G_REFCLK15625_SGMII.
6534 0x7: R_5G_REFCLK15625_QSGMII.
6535 0x8: R_625G_REFCLK15625_RXAUI.
6536 0x9: R_25G_REFCLK125.
6537 0xA: R_5G_REFCLK125.
6538 0xB: R_8G_REFCLK125.
6539 0xC - 0xF: Reserved.
6540
6541 This register is not used for PCIE configurations. This register
6542 defaults to R_625G_REFCLK15625_RXAUI.
6543
6544 It is recommended that the PHY be in reset when reconfiguring the [LMODE]
6545 (GSER()_PHY_CTL[PHY_RESET] is set).
6546
6547 Once the [LMODE] has been configured, and the PHY is out of reset, the table entries for
6548 the
6549 selected [LMODE] must be updated to reflect the reference clock speed. Refer to the
6550 register
6551 description and index into the table using the rate and reference speed to obtain the
6552 recommended values.
6553
6554 _ Write GSER()_PLL_P()_MODE_0.
6555 _ Write GSER()_PLL_P()_MODE_1.
6556 _ Write GSER()_LANE_P()_MODE_0.
6557 _ Write GSER()_LANE_P()_MODE_1.
6558
6559 where in "P(z)", z equals [LMODE]. */
6560 uint64_t reserved_4_63 : 60;
6561 #endif /* Word 0 - End */
6562 } cn83xx;
6563 };
6564 typedef union bdk_gserx_lane_mode bdk_gserx_lane_mode_t;
6565
6566 static inline uint64_t BDK_GSERX_LANE_MODE(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_MODE(unsigned long a)6567 static inline uint64_t BDK_GSERX_LANE_MODE(unsigned long a)
6568 {
6569 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
6570 return 0x87e090000118ll + 0x1000000ll * ((a) & 0x3);
6571 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
6572 return 0x87e090000118ll + 0x1000000ll * ((a) & 0x7);
6573 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
6574 return 0x87e090000118ll + 0x1000000ll * ((a) & 0xf);
6575 __bdk_csr_fatal("GSERX_LANE_MODE", 1, a, 0, 0, 0);
6576 }
6577
6578 #define typedef_BDK_GSERX_LANE_MODE(a) bdk_gserx_lane_mode_t
6579 #define bustype_BDK_GSERX_LANE_MODE(a) BDK_CSR_TYPE_RSL
6580 #define basename_BDK_GSERX_LANE_MODE(a) "GSERX_LANE_MODE"
6581 #define device_bar_BDK_GSERX_LANE_MODE(a) 0x0 /* PF_BAR0 */
6582 #define busnum_BDK_GSERX_LANE_MODE(a) (a)
6583 #define arguments_BDK_GSERX_LANE_MODE(a) (a),-1,-1,-1
6584
6585 /**
6586 * Register (RSL) gser#_lane_p#_mode_0
6587 *
6588 * GSER Lane Protocol Mode 0 Register
6589 * These are the RAW PCS lane settings mode 0 registers. There is one register per
6590 * 4 lanes per GSER per GSER_LMODE_E value (0..11). Only one entry is used at any given time in a
6591 * given GSER lane - the one selected by the corresponding GSER()_LANE_MODE[LMODE].
6592 * These registers are reset by hardware only during chip cold reset.
6593 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
6594 */
6595 union bdk_gserx_lane_px_mode_0
6596 {
6597 uint64_t u;
6598 struct bdk_gserx_lane_px_mode_0_s
6599 {
6600 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6601 uint64_t reserved_15_63 : 49;
6602 uint64_t ctle : 2; /**< [ 14: 13](R/W/H) Continuous time linear equalizer pole configuration.
6603 0x0 = ~5dB of peaking at 4 GHz (Minimum bandwidth).
6604 0x1 =~10dB of peaking at 5 GHz.
6605 0x2 = ~15dB of peaking at 5.5 GHz.
6606 0x3 = ~20dB of peaking at 6 GHz (Maximum bandwidth).
6607
6608 Recommended settings:
6609
6610 \<pre\>
6611 _ R_25G_REFCLK100: 0x0
6612 _ R_5G_REFCLK100: 0x0
6613 _ R_8G_REFCLK100: 0x3
6614 _ R_125G_REFCLK15625_KX: 0x0
6615 _ R_3125G_REFCLK15625_XAUI: 0x0
6616 _ R_103125G_REFCLK15625_KR: 0x3
6617 _ R_125G_REFCLK15625_SGMII: 0x0
6618 _ R_5G_REFCLK15625_QSGMII: 0x0
6619 _ R_625G_REFCLK15625_RXAUI: 0x0
6620 _ R_25G_REFCLK125: 0x0
6621 _ R_5G_REFCLK125: 0x0
6622 _ R_8G_REFCLK125: 0x3
6623 \</pre\>
6624
6625 For SATA, [CTLE] should always be 0. */
6626 uint64_t pcie : 1; /**< [ 12: 12](R/W/H) Selects between RX terminations.
6627 0 = Differential termination.
6628 1 = Termination between pad and SDS_VDDS.
6629
6630 Recommended settings:
6631
6632 \<pre\>
6633 _ R_25G_REFCLK100: 0x1
6634 _ R_5G_REFCLK100: 0x1
6635 _ R_8G_REFCLK100: 0x0
6636 _ R_125G_REFCLK15625_KX: 0x0
6637 _ R_3125G_REFCLK15625_XAUI: 0x0
6638 _ R_103125G_REFCLK15625_KR: 0x0
6639 _ R_125G_REFCLK15625_SGMII: 0x0
6640 _ R_5G_REFCLK15625_QSGMII: 0x0
6641 _ R_625G_REFCLK15625_RXAUI: 0x0
6642 _ R_25G_REFCLK125: 0x1
6643 _ R_5G_REFCLK125: 0x1
6644 _ R_8G_REFCLK125: 0x0
6645 \</pre\>
6646
6647 For SATA, [PCIE] should always be 0. */
6648 uint64_t tx_ldiv : 2; /**< [ 11: 10](R/W/H) Configures clock divider used to determine the receive rate.
6649 0x0 = full data rate.
6650 0x1 = 1/2 data rate.
6651 0x2 = 1/4 data rate.
6652 0x3 = 1/8 data rate.
6653
6654 Recommended settings:
6655
6656 \<pre\>
6657 _ R_25G_REFCLK100: 0x1
6658 _ R_5G_REFCLK100: 0x0
6659 _ R_8G_REFCLK100: 0x0
6660 _ R_125G_REFCLK15625_KX: 0x2
6661 _ R_3125G_REFCLK15625_XAUI: 0x1
6662 _ R_103125G_REFCLK15625_KR: 0x0
6663 _ R_125G_REFCLK15625_SGMII: 0x2
6664 _ R_5G_REFCLK15625_QSGMII: 0x0
6665 _ R_625G_REFCLK15625_RXAUI: 0x0
6666 _ R_25G_REFCLK125: 0x1
6667 _ R_5G_REFCLK125: 0x0
6668 _ R_8G_REFCLK125: 0x0
6669 \</pre\>
6670
6671 For SATA, [TX_LDIV] should always be 0. */
6672 uint64_t rx_ldiv : 2; /**< [ 9: 8](R/W/H) Configures clock divider used to determine the receive rate.
6673 0x0 = full data rate.
6674 0x1 = 1/2 data rate.
6675 0x2 = 1/4 data rate.
6676 0x3 = 1/8 data rate.
6677
6678 Recommended settings:
6679
6680 \<pre\>
6681 _ R_25G_REFCLK100: 0x1
6682 _ R_5G_REFCLK100: 0x0
6683 _ R_8G_REFCLK100: 0x0
6684 _ R_125G_REFCLK15625_KX: 0x2
6685 _ R_3125G_REFCLK15625_XAUI: 0x1
6686 _ R_103125G_REFCLK15625_KR: 0x0
6687 _ R_125G_REFCLK15625_SGMII: 0x2
6688 _ R_5G_REFCLK15625_QSGMII: 0x0
6689 _ R_625G_REFCLK15625_RXAUI: 0x0
6690 _ R_25G_REFCLK125: 0x1
6691 _ R_5G_REFCLK125: 0x0
6692 _ R_8G_REFCLK125: 0x0
6693 \</pre\>
6694
6695 For SATA, [RX_LDIV] should be 2 for R_25G_REFCLK100 (position 0, 1.5 Gbaud),
6696 1 for R_5G_REFCLK100 (position 1, 3 Gbaud), and 0 for R_8G_REFCLK100
6697 (position 2, 6 Gbaud). */
6698 uint64_t srate : 3; /**< [ 7: 5](R/W) Sample rate, used to generate strobe to effectively divide the clock down to a slower
6699 rate.
6700
6701 0x0 = Full rate.
6702 0x1 = 1/2 data rate.
6703 0x2 = 1/4 data rate.
6704 0x3 = 1/8 data rate.
6705 0x4 = 1/16 data rate.
6706 else = Reserved.
6707
6708 This field should always be cleared to zero (i.e. full rate selected). */
6709 uint64_t reserved_4 : 1;
6710 uint64_t tx_mode : 2; /**< [ 3: 2](R/W/H) TX data width:
6711 0x0 = 8-bit raw data (not supported).
6712 0x1 = 10-bit raw data (not supported).
6713 0x2 = 16-bit raw data (for PCIe Gen3 8 Gb only - software should normally not select
6714 this).
6715 0x3 = 20-bit raw data (anything software-configured). */
6716 uint64_t rx_mode : 2; /**< [ 1: 0](R/W/H) RX data width:
6717 0x0 = 8-bit raw data (not supported).
6718 0x1 = 10-bit raw data (not supported).
6719 0x2 = 16-bit raw data (for PCIe Gen3 8 Gb only - software should normally not select
6720 this).
6721 0x3 = 20-bit raw data (anything software-configured). */
6722 #else /* Word 0 - Little Endian */
6723 uint64_t rx_mode : 2; /**< [ 1: 0](R/W/H) RX data width:
6724 0x0 = 8-bit raw data (not supported).
6725 0x1 = 10-bit raw data (not supported).
6726 0x2 = 16-bit raw data (for PCIe Gen3 8 Gb only - software should normally not select
6727 this).
6728 0x3 = 20-bit raw data (anything software-configured). */
6729 uint64_t tx_mode : 2; /**< [ 3: 2](R/W/H) TX data width:
6730 0x0 = 8-bit raw data (not supported).
6731 0x1 = 10-bit raw data (not supported).
6732 0x2 = 16-bit raw data (for PCIe Gen3 8 Gb only - software should normally not select
6733 this).
6734 0x3 = 20-bit raw data (anything software-configured). */
6735 uint64_t reserved_4 : 1;
6736 uint64_t srate : 3; /**< [ 7: 5](R/W) Sample rate, used to generate strobe to effectively divide the clock down to a slower
6737 rate.
6738
6739 0x0 = Full rate.
6740 0x1 = 1/2 data rate.
6741 0x2 = 1/4 data rate.
6742 0x3 = 1/8 data rate.
6743 0x4 = 1/16 data rate.
6744 else = Reserved.
6745
6746 This field should always be cleared to zero (i.e. full rate selected). */
6747 uint64_t rx_ldiv : 2; /**< [ 9: 8](R/W/H) Configures clock divider used to determine the receive rate.
6748 0x0 = full data rate.
6749 0x1 = 1/2 data rate.
6750 0x2 = 1/4 data rate.
6751 0x3 = 1/8 data rate.
6752
6753 Recommended settings:
6754
6755 \<pre\>
6756 _ R_25G_REFCLK100: 0x1
6757 _ R_5G_REFCLK100: 0x0
6758 _ R_8G_REFCLK100: 0x0
6759 _ R_125G_REFCLK15625_KX: 0x2
6760 _ R_3125G_REFCLK15625_XAUI: 0x1
6761 _ R_103125G_REFCLK15625_KR: 0x0
6762 _ R_125G_REFCLK15625_SGMII: 0x2
6763 _ R_5G_REFCLK15625_QSGMII: 0x0
6764 _ R_625G_REFCLK15625_RXAUI: 0x0
6765 _ R_25G_REFCLK125: 0x1
6766 _ R_5G_REFCLK125: 0x0
6767 _ R_8G_REFCLK125: 0x0
6768 \</pre\>
6769
6770 For SATA, [RX_LDIV] should be 2 for R_25G_REFCLK100 (position 0, 1.5 Gbaud),
6771 1 for R_5G_REFCLK100 (position 1, 3 Gbaud), and 0 for R_8G_REFCLK100
6772 (position 2, 6 Gbaud). */
6773 uint64_t tx_ldiv : 2; /**< [ 11: 10](R/W/H) Configures clock divider used to determine the receive rate.
6774 0x0 = full data rate.
6775 0x1 = 1/2 data rate.
6776 0x2 = 1/4 data rate.
6777 0x3 = 1/8 data rate.
6778
6779 Recommended settings:
6780
6781 \<pre\>
6782 _ R_25G_REFCLK100: 0x1
6783 _ R_5G_REFCLK100: 0x0
6784 _ R_8G_REFCLK100: 0x0
6785 _ R_125G_REFCLK15625_KX: 0x2
6786 _ R_3125G_REFCLK15625_XAUI: 0x1
6787 _ R_103125G_REFCLK15625_KR: 0x0
6788 _ R_125G_REFCLK15625_SGMII: 0x2
6789 _ R_5G_REFCLK15625_QSGMII: 0x0
6790 _ R_625G_REFCLK15625_RXAUI: 0x0
6791 _ R_25G_REFCLK125: 0x1
6792 _ R_5G_REFCLK125: 0x0
6793 _ R_8G_REFCLK125: 0x0
6794 \</pre\>
6795
6796 For SATA, [TX_LDIV] should always be 0. */
6797 uint64_t pcie : 1; /**< [ 12: 12](R/W/H) Selects between RX terminations.
6798 0 = Differential termination.
6799 1 = Termination between pad and SDS_VDDS.
6800
6801 Recommended settings:
6802
6803 \<pre\>
6804 _ R_25G_REFCLK100: 0x1
6805 _ R_5G_REFCLK100: 0x1
6806 _ R_8G_REFCLK100: 0x0
6807 _ R_125G_REFCLK15625_KX: 0x0
6808 _ R_3125G_REFCLK15625_XAUI: 0x0
6809 _ R_103125G_REFCLK15625_KR: 0x0
6810 _ R_125G_REFCLK15625_SGMII: 0x0
6811 _ R_5G_REFCLK15625_QSGMII: 0x0
6812 _ R_625G_REFCLK15625_RXAUI: 0x0
6813 _ R_25G_REFCLK125: 0x1
6814 _ R_5G_REFCLK125: 0x1
6815 _ R_8G_REFCLK125: 0x0
6816 \</pre\>
6817
6818 For SATA, [PCIE] should always be 0. */
6819 uint64_t ctle : 2; /**< [ 14: 13](R/W/H) Continuous time linear equalizer pole configuration.
6820 0x0 = ~5dB of peaking at 4 GHz (Minimum bandwidth).
6821 0x1 =~10dB of peaking at 5 GHz.
6822 0x2 = ~15dB of peaking at 5.5 GHz.
6823 0x3 = ~20dB of peaking at 6 GHz (Maximum bandwidth).
6824
6825 Recommended settings:
6826
6827 \<pre\>
6828 _ R_25G_REFCLK100: 0x0
6829 _ R_5G_REFCLK100: 0x0
6830 _ R_8G_REFCLK100: 0x3
6831 _ R_125G_REFCLK15625_KX: 0x0
6832 _ R_3125G_REFCLK15625_XAUI: 0x0
6833 _ R_103125G_REFCLK15625_KR: 0x3
6834 _ R_125G_REFCLK15625_SGMII: 0x0
6835 _ R_5G_REFCLK15625_QSGMII: 0x0
6836 _ R_625G_REFCLK15625_RXAUI: 0x0
6837 _ R_25G_REFCLK125: 0x0
6838 _ R_5G_REFCLK125: 0x0
6839 _ R_8G_REFCLK125: 0x3
6840 \</pre\>
6841
6842 For SATA, [CTLE] should always be 0. */
6843 uint64_t reserved_15_63 : 49;
6844 #endif /* Word 0 - End */
6845 } s;
6846 /* struct bdk_gserx_lane_px_mode_0_s cn; */
6847 };
6848 typedef union bdk_gserx_lane_px_mode_0 bdk_gserx_lane_px_mode_0_t;
6849
6850 static inline uint64_t BDK_GSERX_LANE_PX_MODE_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_PX_MODE_0(unsigned long a,unsigned long b)6851 static inline uint64_t BDK_GSERX_LANE_PX_MODE_0(unsigned long a, unsigned long b)
6852 {
6853 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=11)))
6854 return 0x87e0904e0040ll + 0x1000000ll * ((a) & 0x3) + 0x20ll * ((b) & 0xf);
6855 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=11)))
6856 return 0x87e0904e0040ll + 0x1000000ll * ((a) & 0x7) + 0x20ll * ((b) & 0xf);
6857 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=11)))
6858 return 0x87e0904e0040ll + 0x1000000ll * ((a) & 0xf) + 0x20ll * ((b) & 0xf);
6859 __bdk_csr_fatal("GSERX_LANE_PX_MODE_0", 2, a, b, 0, 0);
6860 }
6861
6862 #define typedef_BDK_GSERX_LANE_PX_MODE_0(a,b) bdk_gserx_lane_px_mode_0_t
6863 #define bustype_BDK_GSERX_LANE_PX_MODE_0(a,b) BDK_CSR_TYPE_RSL
6864 #define basename_BDK_GSERX_LANE_PX_MODE_0(a,b) "GSERX_LANE_PX_MODE_0"
6865 #define device_bar_BDK_GSERX_LANE_PX_MODE_0(a,b) 0x0 /* PF_BAR0 */
6866 #define busnum_BDK_GSERX_LANE_PX_MODE_0(a,b) (a)
6867 #define arguments_BDK_GSERX_LANE_PX_MODE_0(a,b) (a),(b),-1,-1
6868
6869 /**
6870 * Register (RSL) gser#_lane_p#_mode_1
6871 *
6872 * GSER Lane Protocol Mode 1 Register
6873 * These are the RAW PCS lane settings mode 1 registers. There is one register per 4 lanes,
6874 * (0..3) per GSER per GSER_LMODE_E value (0..11). Only one entry is used at any given time in a
6875 * given
6876 * GSER lane - the one selected by the corresponding GSER()_LANE_MODE[LMODE].
6877 * These registers are reset by hardware only during chip cold reset.
6878 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
6879 */
6880 union bdk_gserx_lane_px_mode_1
6881 {
6882 uint64_t u;
6883 struct bdk_gserx_lane_px_mode_1_s
6884 {
6885 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6886 uint64_t reserved_16_63 : 48;
6887 uint64_t vma_fine_cfg_sel : 1; /**< [ 15: 15](R/W/H) Recommended settings:
6888 0 = Disabled. Coarse step adaptation selected (rates lower than 10.3125 Gbaud).
6889 1 = Enabled. Fine step adaptation selected (10.3125 Gbaud rate).
6890
6891 For SATA, [VMA_FINE_CFG_SEL] should always be 0. */
6892 uint64_t vma_mm : 1; /**< [ 14: 14](R/W/H) Manual DFE verses adaptive DFE mode.
6893
6894 Recommended settings:
6895 0 = Adaptive DFE (5 Gbaud and higher).
6896 1 = Manual DFE, fixed tap (3.125 Gbaud and lower).
6897
6898 For SATA, [VMA_MM] should always be 1. */
6899 uint64_t cdr_fgain : 4; /**< [ 13: 10](R/W/H) CDR frequency gain.
6900
6901 Recommended settings:
6902
6903 \<pre\>
6904 _ R_25G_REFCLK100: 0xA
6905 _ R_5G_REFCLK100: 0xA
6906 _ R_8G_REFCLK100: 0xB
6907 _ R_125G_REFCLK15625_KX: 0xC
6908 _ R_3125G_REFCLK15625_XAUI: 0xC
6909 _ R_103125G_REFCLK15625_KR: 0xA
6910 _ R_125G_REFCLK15625_SGMII: 0xC
6911 _ R_5G_REFCLK15625_QSGMII: 0xC
6912 _ R_625G_REFCLK15625_RXAUI: 0xA
6913 _ R_25G_REFCLK125: 0xA
6914 _ R_5G_REFCLK125: 0xA
6915 _ R_8G_REFCLK125: 0xB
6916 \</pre\>
6917
6918 For SATA, [CDR_FGAIN] should always be 0xA. */
6919 uint64_t ph_acc_adj : 10; /**< [ 9: 0](R/W/H) Phase accumulator adjust.
6920
6921 Recommended settings:
6922
6923 \<pre\>
6924 _ R_25G_REFCLK100: 0x14
6925 _ R_5G_REFCLK100: 0x14
6926 _ R_8G_REFCLK100: 0x23
6927 _ R_125G_REFCLK15625_KX: 0x1E
6928 _ R_3125G_REFCLK15625_XAUI: 0x1E
6929 _ R_103125G_REFCLK15625_KR: 0xF
6930 _ R_125G_REFCLK15625_SGMII: 0x1E
6931 _ R_5G_REFCLK15625_QSGMII: 0x1E
6932 _ R_625G_REFCLK15625_RXAUI: 0x14
6933 _ R_25G_REFCLK125: 0x14
6934 _ R_5G_REFCLK125: 0x14
6935 _ R_8G_REFCLK125: 0x23
6936 \</pre\>
6937
6938 For SATA, [PH_ACC_ADJ] should always be 0x15.
6939
6940 A 'NS' indicates that the rate is not supported at the specified reference clock. */
6941 #else /* Word 0 - Little Endian */
6942 uint64_t ph_acc_adj : 10; /**< [ 9: 0](R/W/H) Phase accumulator adjust.
6943
6944 Recommended settings:
6945
6946 \<pre\>
6947 _ R_25G_REFCLK100: 0x14
6948 _ R_5G_REFCLK100: 0x14
6949 _ R_8G_REFCLK100: 0x23
6950 _ R_125G_REFCLK15625_KX: 0x1E
6951 _ R_3125G_REFCLK15625_XAUI: 0x1E
6952 _ R_103125G_REFCLK15625_KR: 0xF
6953 _ R_125G_REFCLK15625_SGMII: 0x1E
6954 _ R_5G_REFCLK15625_QSGMII: 0x1E
6955 _ R_625G_REFCLK15625_RXAUI: 0x14
6956 _ R_25G_REFCLK125: 0x14
6957 _ R_5G_REFCLK125: 0x14
6958 _ R_8G_REFCLK125: 0x23
6959 \</pre\>
6960
6961 For SATA, [PH_ACC_ADJ] should always be 0x15.
6962
6963 A 'NS' indicates that the rate is not supported at the specified reference clock. */
6964 uint64_t cdr_fgain : 4; /**< [ 13: 10](R/W/H) CDR frequency gain.
6965
6966 Recommended settings:
6967
6968 \<pre\>
6969 _ R_25G_REFCLK100: 0xA
6970 _ R_5G_REFCLK100: 0xA
6971 _ R_8G_REFCLK100: 0xB
6972 _ R_125G_REFCLK15625_KX: 0xC
6973 _ R_3125G_REFCLK15625_XAUI: 0xC
6974 _ R_103125G_REFCLK15625_KR: 0xA
6975 _ R_125G_REFCLK15625_SGMII: 0xC
6976 _ R_5G_REFCLK15625_QSGMII: 0xC
6977 _ R_625G_REFCLK15625_RXAUI: 0xA
6978 _ R_25G_REFCLK125: 0xA
6979 _ R_5G_REFCLK125: 0xA
6980 _ R_8G_REFCLK125: 0xB
6981 \</pre\>
6982
6983 For SATA, [CDR_FGAIN] should always be 0xA. */
6984 uint64_t vma_mm : 1; /**< [ 14: 14](R/W/H) Manual DFE verses adaptive DFE mode.
6985
6986 Recommended settings:
6987 0 = Adaptive DFE (5 Gbaud and higher).
6988 1 = Manual DFE, fixed tap (3.125 Gbaud and lower).
6989
6990 For SATA, [VMA_MM] should always be 1. */
6991 uint64_t vma_fine_cfg_sel : 1; /**< [ 15: 15](R/W/H) Recommended settings:
6992 0 = Disabled. Coarse step adaptation selected (rates lower than 10.3125 Gbaud).
6993 1 = Enabled. Fine step adaptation selected (10.3125 Gbaud rate).
6994
6995 For SATA, [VMA_FINE_CFG_SEL] should always be 0. */
6996 uint64_t reserved_16_63 : 48;
6997 #endif /* Word 0 - End */
6998 } s;
6999 /* struct bdk_gserx_lane_px_mode_1_s cn; */
7000 };
7001 typedef union bdk_gserx_lane_px_mode_1 bdk_gserx_lane_px_mode_1_t;
7002
7003 static inline uint64_t BDK_GSERX_LANE_PX_MODE_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_PX_MODE_1(unsigned long a,unsigned long b)7004 static inline uint64_t BDK_GSERX_LANE_PX_MODE_1(unsigned long a, unsigned long b)
7005 {
7006 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=11)))
7007 return 0x87e0904e0048ll + 0x1000000ll * ((a) & 0x3) + 0x20ll * ((b) & 0xf);
7008 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=11)))
7009 return 0x87e0904e0048ll + 0x1000000ll * ((a) & 0x7) + 0x20ll * ((b) & 0xf);
7010 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=11)))
7011 return 0x87e0904e0048ll + 0x1000000ll * ((a) & 0xf) + 0x20ll * ((b) & 0xf);
7012 __bdk_csr_fatal("GSERX_LANE_PX_MODE_1", 2, a, b, 0, 0);
7013 }
7014
7015 #define typedef_BDK_GSERX_LANE_PX_MODE_1(a,b) bdk_gserx_lane_px_mode_1_t
7016 #define bustype_BDK_GSERX_LANE_PX_MODE_1(a,b) BDK_CSR_TYPE_RSL
7017 #define basename_BDK_GSERX_LANE_PX_MODE_1(a,b) "GSERX_LANE_PX_MODE_1"
7018 #define device_bar_BDK_GSERX_LANE_PX_MODE_1(a,b) 0x0 /* PF_BAR0 */
7019 #define busnum_BDK_GSERX_LANE_PX_MODE_1(a,b) (a)
7020 #define arguments_BDK_GSERX_LANE_PX_MODE_1(a,b) (a),(b),-1,-1
7021
7022 /**
7023 * Register (RSL) gser#_lane_poff
7024 *
7025 * GSER Lane Power Off Register
7026 * These registers are reset by hardware only during chip cold reset. The values of the CSR
7027 * fields in these registers do not change during chip warm or soft resets.
7028 */
7029 union bdk_gserx_lane_poff
7030 {
7031 uint64_t u;
7032 struct bdk_gserx_lane_poff_s
7033 {
7034 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7035 uint64_t reserved_4_63 : 60;
7036 uint64_t lpoff : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, allows for per lane power down.
7037 \<3\>: Lane 3. Reserved.
7038 \<2\>: Lane 2. Reserved.
7039 \<1\>: Lane 1.
7040 \<0\>: Lane 0. */
7041 #else /* Word 0 - Little Endian */
7042 uint64_t lpoff : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, allows for per lane power down.
7043 \<3\>: Lane 3. Reserved.
7044 \<2\>: Lane 2. Reserved.
7045 \<1\>: Lane 1.
7046 \<0\>: Lane 0. */
7047 uint64_t reserved_4_63 : 60;
7048 #endif /* Word 0 - End */
7049 } s;
7050 /* struct bdk_gserx_lane_poff_s cn81xx; */
7051 struct bdk_gserx_lane_poff_cn88xx
7052 {
7053 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7054 uint64_t reserved_4_63 : 60;
7055 uint64_t lpoff : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode (including all CCPI links), allows for per-lane power
7056 down.
7057 \<3\>: Lane 3.
7058 \<2\>: Lane 2.
7059 \<1\>: Lane 1.
7060 \<0\>: Lane 0. */
7061 #else /* Word 0 - Little Endian */
7062 uint64_t lpoff : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode (including all CCPI links), allows for per-lane power
7063 down.
7064 \<3\>: Lane 3.
7065 \<2\>: Lane 2.
7066 \<1\>: Lane 1.
7067 \<0\>: Lane 0. */
7068 uint64_t reserved_4_63 : 60;
7069 #endif /* Word 0 - End */
7070 } cn88xx;
7071 struct bdk_gserx_lane_poff_cn83xx
7072 {
7073 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7074 uint64_t reserved_4_63 : 60;
7075 uint64_t lpoff : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, allows for per lane power
7076 down.
7077 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
7078 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
7079 \<1\>: Lane 1.
7080 \<0\>: Lane 0. */
7081 #else /* Word 0 - Little Endian */
7082 uint64_t lpoff : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, allows for per lane power
7083 down.
7084 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
7085 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
7086 \<1\>: Lane 1.
7087 \<0\>: Lane 0. */
7088 uint64_t reserved_4_63 : 60;
7089 #endif /* Word 0 - End */
7090 } cn83xx;
7091 };
7092 typedef union bdk_gserx_lane_poff bdk_gserx_lane_poff_t;
7093
7094 static inline uint64_t BDK_GSERX_LANE_POFF(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_POFF(unsigned long a)7095 static inline uint64_t BDK_GSERX_LANE_POFF(unsigned long a)
7096 {
7097 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
7098 return 0x87e090000108ll + 0x1000000ll * ((a) & 0x3);
7099 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
7100 return 0x87e090000108ll + 0x1000000ll * ((a) & 0x7);
7101 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
7102 return 0x87e090000108ll + 0x1000000ll * ((a) & 0xf);
7103 __bdk_csr_fatal("GSERX_LANE_POFF", 1, a, 0, 0, 0);
7104 }
7105
7106 #define typedef_BDK_GSERX_LANE_POFF(a) bdk_gserx_lane_poff_t
7107 #define bustype_BDK_GSERX_LANE_POFF(a) BDK_CSR_TYPE_RSL
7108 #define basename_BDK_GSERX_LANE_POFF(a) "GSERX_LANE_POFF"
7109 #define device_bar_BDK_GSERX_LANE_POFF(a) 0x0 /* PF_BAR0 */
7110 #define busnum_BDK_GSERX_LANE_POFF(a) (a)
7111 #define arguments_BDK_GSERX_LANE_POFF(a) (a),-1,-1,-1
7112
7113 /**
7114 * Register (RSL) gser#_lane_srst
7115 *
7116 * GSER Lane Soft Reset Register
7117 * These registers are reset by hardware only during chip cold reset. The values of the CSR
7118 * fields in these registers do not change during chip warm or soft resets.
7119 */
7120 union bdk_gserx_lane_srst
7121 {
7122 uint64_t u;
7123 struct bdk_gserx_lane_srst_s
7124 {
7125 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7126 uint64_t reserved_1_63 : 63;
7127 uint64_t lsrst : 1; /**< [ 0: 0](R/W) For links that are not in PCIE or SATA mode, resets all lanes
7128 (equivalent to the P2 power state) after any pending requests (power state change, rate
7129 change) are complete. The lanes remain in reset state while this signal is asserted. When
7130 the signal deasserts, the lanes exit the reset state and the PHY returns to the power
7131 state the PHY was in prior. For diagnostic use only. */
7132 #else /* Word 0 - Little Endian */
7133 uint64_t lsrst : 1; /**< [ 0: 0](R/W) For links that are not in PCIE or SATA mode, resets all lanes
7134 (equivalent to the P2 power state) after any pending requests (power state change, rate
7135 change) are complete. The lanes remain in reset state while this signal is asserted. When
7136 the signal deasserts, the lanes exit the reset state and the PHY returns to the power
7137 state the PHY was in prior. For diagnostic use only. */
7138 uint64_t reserved_1_63 : 63;
7139 #endif /* Word 0 - End */
7140 } s;
7141 /* struct bdk_gserx_lane_srst_s cn81xx; */
7142 struct bdk_gserx_lane_srst_cn88xx
7143 {
7144 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7145 uint64_t reserved_1_63 : 63;
7146 uint64_t lsrst : 1; /**< [ 0: 0](R/W) For links that are not in PCIE or SATA mode (including all CCPI links), resets all lanes
7147 (equivalent to the P2 power state) after any pending requests (power state change, rate
7148 change) are complete. The lanes remain in reset state while this signal is asserted. When
7149 the signal deasserts, the lanes exit the reset state and the PHY returns to the power
7150 state the PHY was in prior. For diagnostic use only. */
7151 #else /* Word 0 - Little Endian */
7152 uint64_t lsrst : 1; /**< [ 0: 0](R/W) For links that are not in PCIE or SATA mode (including all CCPI links), resets all lanes
7153 (equivalent to the P2 power state) after any pending requests (power state change, rate
7154 change) are complete. The lanes remain in reset state while this signal is asserted. When
7155 the signal deasserts, the lanes exit the reset state and the PHY returns to the power
7156 state the PHY was in prior. For diagnostic use only. */
7157 uint64_t reserved_1_63 : 63;
7158 #endif /* Word 0 - End */
7159 } cn88xx;
7160 /* struct bdk_gserx_lane_srst_s cn83xx; */
7161 };
7162 typedef union bdk_gserx_lane_srst bdk_gserx_lane_srst_t;
7163
7164 static inline uint64_t BDK_GSERX_LANE_SRST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_SRST(unsigned long a)7165 static inline uint64_t BDK_GSERX_LANE_SRST(unsigned long a)
7166 {
7167 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
7168 return 0x87e090000100ll + 0x1000000ll * ((a) & 0x3);
7169 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
7170 return 0x87e090000100ll + 0x1000000ll * ((a) & 0x7);
7171 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
7172 return 0x87e090000100ll + 0x1000000ll * ((a) & 0xf);
7173 __bdk_csr_fatal("GSERX_LANE_SRST", 1, a, 0, 0, 0);
7174 }
7175
7176 #define typedef_BDK_GSERX_LANE_SRST(a) bdk_gserx_lane_srst_t
7177 #define bustype_BDK_GSERX_LANE_SRST(a) BDK_CSR_TYPE_RSL
7178 #define basename_BDK_GSERX_LANE_SRST(a) "GSERX_LANE_SRST"
7179 #define device_bar_BDK_GSERX_LANE_SRST(a) 0x0 /* PF_BAR0 */
7180 #define busnum_BDK_GSERX_LANE_SRST(a) (a)
7181 #define arguments_BDK_GSERX_LANE_SRST(a) (a),-1,-1,-1
7182
7183 /**
7184 * Register (RSL) gser#_lane_vma_coarse_ctrl_0
7185 *
7186 * GSER Lane VMA Coarse Control 0 Register
7187 * These registers are for diagnostic use only.
7188 * These registers are reset by hardware only during chip cold reset.
7189 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
7190 */
7191 union bdk_gserx_lane_vma_coarse_ctrl_0
7192 {
7193 uint64_t u;
7194 struct bdk_gserx_lane_vma_coarse_ctrl_0_s
7195 {
7196 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7197 uint64_t reserved_16_63 : 48;
7198 uint64_t iq_max : 4; /**< [ 15: 12](R/W) Slice DLL IQ maximum value in VMA coarse mode. */
7199 uint64_t iq_min : 4; /**< [ 11: 8](R/W) Slice DLL IQ minimum value in VMA coarse mode. */
7200 uint64_t iq_step : 2; /**< [ 7: 6](R/W) Slice DLL IQ step size in VMA coarse mode. */
7201 uint64_t window_wait : 3; /**< [ 5: 3](R/W) Adaptation window wait setting in VMA coarse mode. */
7202 uint64_t lms_wait : 3; /**< [ 2: 0](R/W/H) LMS wait time setting used to control the number of samples taken during the collection of
7203 statistics in VMA coarse mode. */
7204 #else /* Word 0 - Little Endian */
7205 uint64_t lms_wait : 3; /**< [ 2: 0](R/W/H) LMS wait time setting used to control the number of samples taken during the collection of
7206 statistics in VMA coarse mode. */
7207 uint64_t window_wait : 3; /**< [ 5: 3](R/W) Adaptation window wait setting in VMA coarse mode. */
7208 uint64_t iq_step : 2; /**< [ 7: 6](R/W) Slice DLL IQ step size in VMA coarse mode. */
7209 uint64_t iq_min : 4; /**< [ 11: 8](R/W) Slice DLL IQ minimum value in VMA coarse mode. */
7210 uint64_t iq_max : 4; /**< [ 15: 12](R/W) Slice DLL IQ maximum value in VMA coarse mode. */
7211 uint64_t reserved_16_63 : 48;
7212 #endif /* Word 0 - End */
7213 } s;
7214 /* struct bdk_gserx_lane_vma_coarse_ctrl_0_s cn; */
7215 };
7216 typedef union bdk_gserx_lane_vma_coarse_ctrl_0 bdk_gserx_lane_vma_coarse_ctrl_0_t;
7217
7218 static inline uint64_t BDK_GSERX_LANE_VMA_COARSE_CTRL_0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_VMA_COARSE_CTRL_0(unsigned long a)7219 static inline uint64_t BDK_GSERX_LANE_VMA_COARSE_CTRL_0(unsigned long a)
7220 {
7221 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
7222 return 0x87e0904e01b0ll + 0x1000000ll * ((a) & 0x3);
7223 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
7224 return 0x87e0904e01b0ll + 0x1000000ll * ((a) & 0x7);
7225 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
7226 return 0x87e0904e01b0ll + 0x1000000ll * ((a) & 0xf);
7227 __bdk_csr_fatal("GSERX_LANE_VMA_COARSE_CTRL_0", 1, a, 0, 0, 0);
7228 }
7229
7230 #define typedef_BDK_GSERX_LANE_VMA_COARSE_CTRL_0(a) bdk_gserx_lane_vma_coarse_ctrl_0_t
7231 #define bustype_BDK_GSERX_LANE_VMA_COARSE_CTRL_0(a) BDK_CSR_TYPE_RSL
7232 #define basename_BDK_GSERX_LANE_VMA_COARSE_CTRL_0(a) "GSERX_LANE_VMA_COARSE_CTRL_0"
7233 #define device_bar_BDK_GSERX_LANE_VMA_COARSE_CTRL_0(a) 0x0 /* PF_BAR0 */
7234 #define busnum_BDK_GSERX_LANE_VMA_COARSE_CTRL_0(a) (a)
7235 #define arguments_BDK_GSERX_LANE_VMA_COARSE_CTRL_0(a) (a),-1,-1,-1
7236
7237 /**
7238 * Register (RSL) gser#_lane_vma_coarse_ctrl_1
7239 *
7240 * GSER Lane VMA Coarse Control 1 Register
7241 * These registers are for diagnostic use only.
7242 * These registers are reset by hardware only during chip cold reset.
7243 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
7244 */
7245 union bdk_gserx_lane_vma_coarse_ctrl_1
7246 {
7247 uint64_t u;
7248 struct bdk_gserx_lane_vma_coarse_ctrl_1_s
7249 {
7250 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7251 uint64_t reserved_10_63 : 54;
7252 uint64_t ctle_pmax : 4; /**< [ 9: 6](R/W) RX CTLE peak maximum value in VMA coarse mode. */
7253 uint64_t ctle_pmin : 4; /**< [ 5: 2](R/W) RX CTLE peak minimum value in VMA coarse mode. */
7254 uint64_t ctle_pstep : 2; /**< [ 1: 0](R/W) CTLE peak step size in VMA coarse mode. */
7255 #else /* Word 0 - Little Endian */
7256 uint64_t ctle_pstep : 2; /**< [ 1: 0](R/W) CTLE peak step size in VMA coarse mode. */
7257 uint64_t ctle_pmin : 4; /**< [ 5: 2](R/W) RX CTLE peak minimum value in VMA coarse mode. */
7258 uint64_t ctle_pmax : 4; /**< [ 9: 6](R/W) RX CTLE peak maximum value in VMA coarse mode. */
7259 uint64_t reserved_10_63 : 54;
7260 #endif /* Word 0 - End */
7261 } s;
7262 /* struct bdk_gserx_lane_vma_coarse_ctrl_1_s cn; */
7263 };
7264 typedef union bdk_gserx_lane_vma_coarse_ctrl_1 bdk_gserx_lane_vma_coarse_ctrl_1_t;
7265
7266 static inline uint64_t BDK_GSERX_LANE_VMA_COARSE_CTRL_1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_VMA_COARSE_CTRL_1(unsigned long a)7267 static inline uint64_t BDK_GSERX_LANE_VMA_COARSE_CTRL_1(unsigned long a)
7268 {
7269 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
7270 return 0x87e0904e01b8ll + 0x1000000ll * ((a) & 0x3);
7271 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
7272 return 0x87e0904e01b8ll + 0x1000000ll * ((a) & 0x7);
7273 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
7274 return 0x87e0904e01b8ll + 0x1000000ll * ((a) & 0xf);
7275 __bdk_csr_fatal("GSERX_LANE_VMA_COARSE_CTRL_1", 1, a, 0, 0, 0);
7276 }
7277
7278 #define typedef_BDK_GSERX_LANE_VMA_COARSE_CTRL_1(a) bdk_gserx_lane_vma_coarse_ctrl_1_t
7279 #define bustype_BDK_GSERX_LANE_VMA_COARSE_CTRL_1(a) BDK_CSR_TYPE_RSL
7280 #define basename_BDK_GSERX_LANE_VMA_COARSE_CTRL_1(a) "GSERX_LANE_VMA_COARSE_CTRL_1"
7281 #define device_bar_BDK_GSERX_LANE_VMA_COARSE_CTRL_1(a) 0x0 /* PF_BAR0 */
7282 #define busnum_BDK_GSERX_LANE_VMA_COARSE_CTRL_1(a) (a)
7283 #define arguments_BDK_GSERX_LANE_VMA_COARSE_CTRL_1(a) (a),-1,-1,-1
7284
7285 /**
7286 * Register (RSL) gser#_lane_vma_coarse_ctrl_2
7287 *
7288 * GSER Lane VMA Fine Control 2 Register
7289 * These registers are for diagnostic use only.
7290 * These registers are reset by hardware only during chip cold reset.
7291 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
7292 */
7293 union bdk_gserx_lane_vma_coarse_ctrl_2
7294 {
7295 uint64_t u;
7296 struct bdk_gserx_lane_vma_coarse_ctrl_2_s
7297 {
7298 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7299 uint64_t reserved_10_63 : 54;
7300 uint64_t pctle_gmax : 4; /**< [ 9: 6](R/W) RX PRE-CTLE gain maximum value in VMA coarse mode. */
7301 uint64_t pctle_gmin : 4; /**< [ 5: 2](R/W) RX PRE-CTLE gain minimum value in VMA coarse mode. */
7302 uint64_t pctle_gstep : 2; /**< [ 1: 0](R/W) CTLE PRE-peak gain step size in VMA coarse mode. */
7303 #else /* Word 0 - Little Endian */
7304 uint64_t pctle_gstep : 2; /**< [ 1: 0](R/W) CTLE PRE-peak gain step size in VMA coarse mode. */
7305 uint64_t pctle_gmin : 4; /**< [ 5: 2](R/W) RX PRE-CTLE gain minimum value in VMA coarse mode. */
7306 uint64_t pctle_gmax : 4; /**< [ 9: 6](R/W) RX PRE-CTLE gain maximum value in VMA coarse mode. */
7307 uint64_t reserved_10_63 : 54;
7308 #endif /* Word 0 - End */
7309 } s;
7310 /* struct bdk_gserx_lane_vma_coarse_ctrl_2_s cn; */
7311 };
7312 typedef union bdk_gserx_lane_vma_coarse_ctrl_2 bdk_gserx_lane_vma_coarse_ctrl_2_t;
7313
7314 static inline uint64_t BDK_GSERX_LANE_VMA_COARSE_CTRL_2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_VMA_COARSE_CTRL_2(unsigned long a)7315 static inline uint64_t BDK_GSERX_LANE_VMA_COARSE_CTRL_2(unsigned long a)
7316 {
7317 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
7318 return 0x87e0904e01c0ll + 0x1000000ll * ((a) & 0x3);
7319 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
7320 return 0x87e0904e01c0ll + 0x1000000ll * ((a) & 0x7);
7321 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
7322 return 0x87e0904e01c0ll + 0x1000000ll * ((a) & 0xf);
7323 __bdk_csr_fatal("GSERX_LANE_VMA_COARSE_CTRL_2", 1, a, 0, 0, 0);
7324 }
7325
7326 #define typedef_BDK_GSERX_LANE_VMA_COARSE_CTRL_2(a) bdk_gserx_lane_vma_coarse_ctrl_2_t
7327 #define bustype_BDK_GSERX_LANE_VMA_COARSE_CTRL_2(a) BDK_CSR_TYPE_RSL
7328 #define basename_BDK_GSERX_LANE_VMA_COARSE_CTRL_2(a) "GSERX_LANE_VMA_COARSE_CTRL_2"
7329 #define device_bar_BDK_GSERX_LANE_VMA_COARSE_CTRL_2(a) 0x0 /* PF_BAR0 */
7330 #define busnum_BDK_GSERX_LANE_VMA_COARSE_CTRL_2(a) (a)
7331 #define arguments_BDK_GSERX_LANE_VMA_COARSE_CTRL_2(a) (a),-1,-1,-1
7332
7333 /**
7334 * Register (RSL) gser#_lane_vma_fine_ctrl_0
7335 *
7336 * GSER Lane VMA Fine Control 0 Register
7337 * These registers are for diagnostic use only.
7338 * These registers are reset by hardware only during chip cold reset.
7339 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
7340 */
7341 union bdk_gserx_lane_vma_fine_ctrl_0
7342 {
7343 uint64_t u;
7344 struct bdk_gserx_lane_vma_fine_ctrl_0_s
7345 {
7346 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7347 uint64_t reserved_16_63 : 48;
7348 uint64_t rx_sdll_iq_max_fine : 4; /**< [ 15: 12](R/W) RX slice DLL IQ maximum value in VMA fine mode (valid when
7349 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and
7350 GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7351 uint64_t rx_sdll_iq_min_fine : 4; /**< [ 11: 8](R/W) RX slice DLL IQ minimum value in VMA fine mode (valid when
7352 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and
7353 GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7354 uint64_t rx_sdll_iq_step_fine : 2; /**< [ 7: 6](R/W) RX slice DLL IQ step size in VMA fine mode (valid when
7355 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and
7356 GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7357 uint64_t vma_window_wait_fine : 3; /**< [ 5: 3](R/W) Adaptation window wait setting (in VMA fine mode); used to control the number of samples
7358 taken during the collection of statistics (valid when
7359 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7360 uint64_t lms_wait_time_fine : 3; /**< [ 2: 0](R/W) LMS wait time setting (in VMA fine mode); used to control the number of samples taken
7361 during the collection of statistics (valid when
7362 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7363 #else /* Word 0 - Little Endian */
7364 uint64_t lms_wait_time_fine : 3; /**< [ 2: 0](R/W) LMS wait time setting (in VMA fine mode); used to control the number of samples taken
7365 during the collection of statistics (valid when
7366 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7367 uint64_t vma_window_wait_fine : 3; /**< [ 5: 3](R/W) Adaptation window wait setting (in VMA fine mode); used to control the number of samples
7368 taken during the collection of statistics (valid when
7369 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7370 uint64_t rx_sdll_iq_step_fine : 2; /**< [ 7: 6](R/W) RX slice DLL IQ step size in VMA fine mode (valid when
7371 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and
7372 GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7373 uint64_t rx_sdll_iq_min_fine : 4; /**< [ 11: 8](R/W) RX slice DLL IQ minimum value in VMA fine mode (valid when
7374 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and
7375 GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7376 uint64_t rx_sdll_iq_max_fine : 4; /**< [ 15: 12](R/W) RX slice DLL IQ maximum value in VMA fine mode (valid when
7377 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and
7378 GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7379 uint64_t reserved_16_63 : 48;
7380 #endif /* Word 0 - End */
7381 } s;
7382 /* struct bdk_gserx_lane_vma_fine_ctrl_0_s cn; */
7383 };
7384 typedef union bdk_gserx_lane_vma_fine_ctrl_0 bdk_gserx_lane_vma_fine_ctrl_0_t;
7385
7386 static inline uint64_t BDK_GSERX_LANE_VMA_FINE_CTRL_0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_VMA_FINE_CTRL_0(unsigned long a)7387 static inline uint64_t BDK_GSERX_LANE_VMA_FINE_CTRL_0(unsigned long a)
7388 {
7389 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
7390 return 0x87e0904e01c8ll + 0x1000000ll * ((a) & 0x3);
7391 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
7392 return 0x87e0904e01c8ll + 0x1000000ll * ((a) & 0x7);
7393 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
7394 return 0x87e0904e01c8ll + 0x1000000ll * ((a) & 0xf);
7395 __bdk_csr_fatal("GSERX_LANE_VMA_FINE_CTRL_0", 1, a, 0, 0, 0);
7396 }
7397
7398 #define typedef_BDK_GSERX_LANE_VMA_FINE_CTRL_0(a) bdk_gserx_lane_vma_fine_ctrl_0_t
7399 #define bustype_BDK_GSERX_LANE_VMA_FINE_CTRL_0(a) BDK_CSR_TYPE_RSL
7400 #define basename_BDK_GSERX_LANE_VMA_FINE_CTRL_0(a) "GSERX_LANE_VMA_FINE_CTRL_0"
7401 #define device_bar_BDK_GSERX_LANE_VMA_FINE_CTRL_0(a) 0x0 /* PF_BAR0 */
7402 #define busnum_BDK_GSERX_LANE_VMA_FINE_CTRL_0(a) (a)
7403 #define arguments_BDK_GSERX_LANE_VMA_FINE_CTRL_0(a) (a),-1,-1,-1
7404
7405 /**
7406 * Register (RSL) gser#_lane_vma_fine_ctrl_1
7407 *
7408 * GSER Lane VMA Fine Control 1 Register
7409 * These registers are for diagnostic use only.
7410 * These registers are reset by hardware only during chip cold reset.
7411 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
7412 */
7413 union bdk_gserx_lane_vma_fine_ctrl_1
7414 {
7415 uint64_t u;
7416 struct bdk_gserx_lane_vma_fine_ctrl_1_s
7417 {
7418 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7419 uint64_t reserved_10_63 : 54;
7420 uint64_t rx_ctle_peak_max_fine : 4; /**< [ 9: 6](R/W) RX CTLE peak maximum value in VMA fine mode (valid when
7421 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7422 uint64_t rx_ctle_peak_min_fine : 4; /**< [ 5: 2](R/W) RX CTLE peak minimum value in VMA fine mode (valid when
7423 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7424 uint64_t rx_ctle_peak_step_fine : 2; /**< [ 1: 0](R/W) RX CTLE Peak step size in VMA Fine mode (valid when
7425 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7426 #else /* Word 0 - Little Endian */
7427 uint64_t rx_ctle_peak_step_fine : 2; /**< [ 1: 0](R/W) RX CTLE Peak step size in VMA Fine mode (valid when
7428 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7429 uint64_t rx_ctle_peak_min_fine : 4; /**< [ 5: 2](R/W) RX CTLE peak minimum value in VMA fine mode (valid when
7430 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7431 uint64_t rx_ctle_peak_max_fine : 4; /**< [ 9: 6](R/W) RX CTLE peak maximum value in VMA fine mode (valid when
7432 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7433 uint64_t reserved_10_63 : 54;
7434 #endif /* Word 0 - End */
7435 } s;
7436 /* struct bdk_gserx_lane_vma_fine_ctrl_1_s cn; */
7437 };
7438 typedef union bdk_gserx_lane_vma_fine_ctrl_1 bdk_gserx_lane_vma_fine_ctrl_1_t;
7439
7440 static inline uint64_t BDK_GSERX_LANE_VMA_FINE_CTRL_1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_VMA_FINE_CTRL_1(unsigned long a)7441 static inline uint64_t BDK_GSERX_LANE_VMA_FINE_CTRL_1(unsigned long a)
7442 {
7443 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
7444 return 0x87e0904e01d0ll + 0x1000000ll * ((a) & 0x3);
7445 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
7446 return 0x87e0904e01d0ll + 0x1000000ll * ((a) & 0x7);
7447 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
7448 return 0x87e0904e01d0ll + 0x1000000ll * ((a) & 0xf);
7449 __bdk_csr_fatal("GSERX_LANE_VMA_FINE_CTRL_1", 1, a, 0, 0, 0);
7450 }
7451
7452 #define typedef_BDK_GSERX_LANE_VMA_FINE_CTRL_1(a) bdk_gserx_lane_vma_fine_ctrl_1_t
7453 #define bustype_BDK_GSERX_LANE_VMA_FINE_CTRL_1(a) BDK_CSR_TYPE_RSL
7454 #define basename_BDK_GSERX_LANE_VMA_FINE_CTRL_1(a) "GSERX_LANE_VMA_FINE_CTRL_1"
7455 #define device_bar_BDK_GSERX_LANE_VMA_FINE_CTRL_1(a) 0x0 /* PF_BAR0 */
7456 #define busnum_BDK_GSERX_LANE_VMA_FINE_CTRL_1(a) (a)
7457 #define arguments_BDK_GSERX_LANE_VMA_FINE_CTRL_1(a) (a),-1,-1,-1
7458
7459 /**
7460 * Register (RSL) gser#_lane_vma_fine_ctrl_2
7461 *
7462 * GSER Lane VMA Fine Control 2 Register
7463 * These registers are for diagnostic use only.
7464 * These registers are reset by hardware only during chip cold reset.
7465 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
7466 */
7467 union bdk_gserx_lane_vma_fine_ctrl_2
7468 {
7469 uint64_t u;
7470 struct bdk_gserx_lane_vma_fine_ctrl_2_s
7471 {
7472 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7473 uint64_t reserved_10_63 : 54;
7474 uint64_t rx_prectle_gain_max_fine : 4;/**< [ 9: 6](R/W) RX PRE-CTLE gain maximum value in VMA fine mode (valid when
7475 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7476 uint64_t rx_prectle_gain_min_fine : 4;/**< [ 5: 2](R/W) RX PRE-CTLE gain minimum value in VMA fine mode (valid when
7477 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7478 uint64_t rx_prectle_gain_step_fine : 2;/**< [ 1: 0](R/W) RX PRE-CTLE gain step size in VMA fine mode (valid when
7479 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7480 #else /* Word 0 - Little Endian */
7481 uint64_t rx_prectle_gain_step_fine : 2;/**< [ 1: 0](R/W) RX PRE-CTLE gain step size in VMA fine mode (valid when
7482 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7483 uint64_t rx_prectle_gain_min_fine : 4;/**< [ 5: 2](R/W) RX PRE-CTLE gain minimum value in VMA fine mode (valid when
7484 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7485 uint64_t rx_prectle_gain_max_fine : 4;/**< [ 9: 6](R/W) RX PRE-CTLE gain maximum value in VMA fine mode (valid when
7486 GSER()_LANE_P()_MODE_1[VMA_FINE_CFG_SEL]=1 and GSER()_LANE_P()_MODE_1[VMA_MM]=0). */
7487 uint64_t reserved_10_63 : 54;
7488 #endif /* Word 0 - End */
7489 } s;
7490 /* struct bdk_gserx_lane_vma_fine_ctrl_2_s cn; */
7491 };
7492 typedef union bdk_gserx_lane_vma_fine_ctrl_2 bdk_gserx_lane_vma_fine_ctrl_2_t;
7493
7494 static inline uint64_t BDK_GSERX_LANE_VMA_FINE_CTRL_2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_LANE_VMA_FINE_CTRL_2(unsigned long a)7495 static inline uint64_t BDK_GSERX_LANE_VMA_FINE_CTRL_2(unsigned long a)
7496 {
7497 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
7498 return 0x87e0904e01d8ll + 0x1000000ll * ((a) & 0x3);
7499 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
7500 return 0x87e0904e01d8ll + 0x1000000ll * ((a) & 0x7);
7501 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
7502 return 0x87e0904e01d8ll + 0x1000000ll * ((a) & 0xf);
7503 __bdk_csr_fatal("GSERX_LANE_VMA_FINE_CTRL_2", 1, a, 0, 0, 0);
7504 }
7505
7506 #define typedef_BDK_GSERX_LANE_VMA_FINE_CTRL_2(a) bdk_gserx_lane_vma_fine_ctrl_2_t
7507 #define bustype_BDK_GSERX_LANE_VMA_FINE_CTRL_2(a) BDK_CSR_TYPE_RSL
7508 #define basename_BDK_GSERX_LANE_VMA_FINE_CTRL_2(a) "GSERX_LANE_VMA_FINE_CTRL_2"
7509 #define device_bar_BDK_GSERX_LANE_VMA_FINE_CTRL_2(a) 0x0 /* PF_BAR0 */
7510 #define busnum_BDK_GSERX_LANE_VMA_FINE_CTRL_2(a) (a)
7511 #define arguments_BDK_GSERX_LANE_VMA_FINE_CTRL_2(a) (a),-1,-1,-1
7512
7513 /**
7514 * Register (RSL) gser#_phy_ctl
7515 *
7516 * GSER PHY Control Register
7517 * This register contains general PHY/PLL control of the RAW PCS.
7518 * These registers are reset by hardware only during chip cold reset. The values of the CSR
7519 * fields in these registers do not change during chip warm or soft resets.
7520 */
7521 union bdk_gserx_phy_ctl
7522 {
7523 uint64_t u;
7524 struct bdk_gserx_phy_ctl_s
7525 {
7526 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7527 uint64_t reserved_2_63 : 62;
7528 uint64_t phy_reset : 1; /**< [ 1: 1](R/W/H) When asserted, the PHY is held in reset. This bit is initialized as follows:
7529 0 = (not reset) = Bootable PCIe.
7530 1 = (reset) = Non-bootable PCIe, BGX, or SATA. */
7531 uint64_t phy_pd : 1; /**< [ 0: 0](R/W) When asserted, the PHY is powered down. */
7532 #else /* Word 0 - Little Endian */
7533 uint64_t phy_pd : 1; /**< [ 0: 0](R/W) When asserted, the PHY is powered down. */
7534 uint64_t phy_reset : 1; /**< [ 1: 1](R/W/H) When asserted, the PHY is held in reset. This bit is initialized as follows:
7535 0 = (not reset) = Bootable PCIe.
7536 1 = (reset) = Non-bootable PCIe, BGX, or SATA. */
7537 uint64_t reserved_2_63 : 62;
7538 #endif /* Word 0 - End */
7539 } s;
7540 /* struct bdk_gserx_phy_ctl_s cn81xx; */
7541 struct bdk_gserx_phy_ctl_cn88xx
7542 {
7543 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7544 uint64_t reserved_2_63 : 62;
7545 uint64_t phy_reset : 1; /**< [ 1: 1](R/W/H) When asserted, the PHY is held in reset. This bit is initialized as follows:
7546 0 = (not reset) = Bootable PCIe, or CCPI when GSER(8..13)_SPD[SPD] comes up in a bootable
7547 mode.
7548 1 = (reset) = Non-bootable PCIe, BGX, SATA or CCPI when GSER(8..13)_SPD[SPD] comes up in
7549 SW_MODE. */
7550 uint64_t phy_pd : 1; /**< [ 0: 0](R/W) When asserted, the PHY is powered down. */
7551 #else /* Word 0 - Little Endian */
7552 uint64_t phy_pd : 1; /**< [ 0: 0](R/W) When asserted, the PHY is powered down. */
7553 uint64_t phy_reset : 1; /**< [ 1: 1](R/W/H) When asserted, the PHY is held in reset. This bit is initialized as follows:
7554 0 = (not reset) = Bootable PCIe, or CCPI when GSER(8..13)_SPD[SPD] comes up in a bootable
7555 mode.
7556 1 = (reset) = Non-bootable PCIe, BGX, SATA or CCPI when GSER(8..13)_SPD[SPD] comes up in
7557 SW_MODE. */
7558 uint64_t reserved_2_63 : 62;
7559 #endif /* Word 0 - End */
7560 } cn88xx;
7561 /* struct bdk_gserx_phy_ctl_s cn83xx; */
7562 };
7563 typedef union bdk_gserx_phy_ctl bdk_gserx_phy_ctl_t;
7564
7565 static inline uint64_t BDK_GSERX_PHY_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_PHY_CTL(unsigned long a)7566 static inline uint64_t BDK_GSERX_PHY_CTL(unsigned long a)
7567 {
7568 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
7569 return 0x87e090000000ll + 0x1000000ll * ((a) & 0x3);
7570 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
7571 return 0x87e090000000ll + 0x1000000ll * ((a) & 0x7);
7572 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
7573 return 0x87e090000000ll + 0x1000000ll * ((a) & 0xf);
7574 __bdk_csr_fatal("GSERX_PHY_CTL", 1, a, 0, 0, 0);
7575 }
7576
7577 #define typedef_BDK_GSERX_PHY_CTL(a) bdk_gserx_phy_ctl_t
7578 #define bustype_BDK_GSERX_PHY_CTL(a) BDK_CSR_TYPE_RSL
7579 #define basename_BDK_GSERX_PHY_CTL(a) "GSERX_PHY_CTL"
7580 #define device_bar_BDK_GSERX_PHY_CTL(a) 0x0 /* PF_BAR0 */
7581 #define busnum_BDK_GSERX_PHY_CTL(a) (a)
7582 #define arguments_BDK_GSERX_PHY_CTL(a) (a),-1,-1,-1
7583
7584 /**
7585 * Register (RSL) gser#_pipe_lpbk
7586 *
7587 * GSER PCIE PCS PIPE Lookback Register
7588 */
7589 union bdk_gserx_pipe_lpbk
7590 {
7591 uint64_t u;
7592 struct bdk_gserx_pipe_lpbk_s
7593 {
7594 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7595 uint64_t reserved_1_63 : 63;
7596 uint64_t pcie_lpbk : 1; /**< [ 0: 0](R/W) For links that are in PCIE mode, places the PHY in serial loopback mode, where the
7597 QLMn_TXN/QLMn_TXP data are looped back to the QLMn_RXN/QLMn_RXP.
7598
7599 This register has no meaning for links that don't support PCIe. */
7600 #else /* Word 0 - Little Endian */
7601 uint64_t pcie_lpbk : 1; /**< [ 0: 0](R/W) For links that are in PCIE mode, places the PHY in serial loopback mode, where the
7602 QLMn_TXN/QLMn_TXP data are looped back to the QLMn_RXN/QLMn_RXP.
7603
7604 This register has no meaning for links that don't support PCIe. */
7605 uint64_t reserved_1_63 : 63;
7606 #endif /* Word 0 - End */
7607 } s;
7608 /* struct bdk_gserx_pipe_lpbk_s cn; */
7609 };
7610 typedef union bdk_gserx_pipe_lpbk bdk_gserx_pipe_lpbk_t;
7611
7612 static inline uint64_t BDK_GSERX_PIPE_LPBK(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_PIPE_LPBK(unsigned long a)7613 static inline uint64_t BDK_GSERX_PIPE_LPBK(unsigned long a)
7614 {
7615 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
7616 return 0x87e090000200ll + 0x1000000ll * ((a) & 0x3);
7617 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
7618 return 0x87e090000200ll + 0x1000000ll * ((a) & 0x7);
7619 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
7620 return 0x87e090000200ll + 0x1000000ll * ((a) & 0xf);
7621 __bdk_csr_fatal("GSERX_PIPE_LPBK", 1, a, 0, 0, 0);
7622 }
7623
7624 #define typedef_BDK_GSERX_PIPE_LPBK(a) bdk_gserx_pipe_lpbk_t
7625 #define bustype_BDK_GSERX_PIPE_LPBK(a) BDK_CSR_TYPE_RSL
7626 #define basename_BDK_GSERX_PIPE_LPBK(a) "GSERX_PIPE_LPBK"
7627 #define device_bar_BDK_GSERX_PIPE_LPBK(a) 0x0 /* PF_BAR0 */
7628 #define busnum_BDK_GSERX_PIPE_LPBK(a) (a)
7629 #define arguments_BDK_GSERX_PIPE_LPBK(a) (a),-1,-1,-1
7630
7631 /**
7632 * Register (RSL) gser#_pll_p#_mode_0
7633 *
7634 * GSER PLL Protocol Mode 0 Register
7635 * These are the RAW PCS PLL global settings mode 0 registers. There is one register per GSER per
7636 * GSER_LMODE_E value (0..11). Only one entry is used at any given time in a given GSER - the one
7637 * selected by the corresponding GSER()_LANE_MODE[LMODE].
7638 * These registers are reset by hardware only during chip cold reset.
7639 * The values of the CSR fields in these registers do not change during subsequent chip warm or
7640 * soft resets.
7641 */
7642 union bdk_gserx_pll_px_mode_0
7643 {
7644 uint64_t u;
7645 struct bdk_gserx_pll_px_mode_0_s
7646 {
7647 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7648 uint64_t reserved_16_63 : 48;
7649 uint64_t pll_icp : 4; /**< [ 15: 12](R/W/H) PLL charge pump enable.
7650
7651 Recommended settings, which are based on the reference clock speed:
7652
7653 \<pre\>
7654 100MHz 125MHz 156.25MHz
7655 1.25G: 0x1 0x1 0x1
7656 2.5G: 0x4 0x3 0x3
7657 3.125G: NS 0x1 0x1
7658 5.0G: 0x1 0x1 0x1
7659 6.25G: NS 0x1 0x1
7660 8.0G: 0x3 0x2 NS
7661 10.3125G: NS NS 0x1
7662 \</pre\>
7663
7664 For SATA, [PLL_ICP] should always be 1.
7665 For PCIE 1.1 @100 MHz, [PLL_ICP] should be 4.
7666 For PCIE 2.1 @100 MHz, [PLL_ICP] should be 4.
7667 For PCIE 1.1 @125 MHz, [PLL_ICP] should be 3.
7668 For PCIE 2.1 @125 MHz, [PLL_ICP] should be 3.
7669
7670 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7671 uint64_t pll_rloop : 3; /**< [ 11: 9](R/W/H) Loop resistor tuning.
7672
7673 Recommended settings:
7674
7675 \<pre\>
7676 _ 1.25G: 0x3
7677 _ 2.5G: 0x3
7678 _ 3.125G: 0x3
7679 _ 5.0G: 0x3
7680 _ 6.25G: 0x3
7681 _ 8.0G: 0x5
7682 _ 10.3125G: 0x5
7683 \</pre\>
7684
7685 For SATA with 100 MHz reference clock, [PLL_RLOOP] should always be 3. */
7686 uint64_t pll_pcs_div : 9; /**< [ 8: 0](R/W/H) The divider that generates PCS_MAC_TX_CLK. The frequency of the clock is (pll_frequency /
7687 PLL_PCS_DIV).
7688
7689 Recommended settings:
7690
7691 \<pre\>
7692 PCIE Other
7693 _ 1.25G: NS 0x28
7694 _ 2.5G: 0x5 0x5
7695 _ 3.125G: NS 0x14
7696 _ 5.0G: 0x5 0xA
7697 _ 6.25G: NS 0xA
7698 _ 8.0G: 0x8 0xA
7699 _ 10.3125G: NS 0xA
7700 \</pre\>
7701
7702 For SATA, [PLL_PCS_DIV] should always be 5.
7703
7704 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7705 #else /* Word 0 - Little Endian */
7706 uint64_t pll_pcs_div : 9; /**< [ 8: 0](R/W/H) The divider that generates PCS_MAC_TX_CLK. The frequency of the clock is (pll_frequency /
7707 PLL_PCS_DIV).
7708
7709 Recommended settings:
7710
7711 \<pre\>
7712 PCIE Other
7713 _ 1.25G: NS 0x28
7714 _ 2.5G: 0x5 0x5
7715 _ 3.125G: NS 0x14
7716 _ 5.0G: 0x5 0xA
7717 _ 6.25G: NS 0xA
7718 _ 8.0G: 0x8 0xA
7719 _ 10.3125G: NS 0xA
7720 \</pre\>
7721
7722 For SATA, [PLL_PCS_DIV] should always be 5.
7723
7724 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7725 uint64_t pll_rloop : 3; /**< [ 11: 9](R/W/H) Loop resistor tuning.
7726
7727 Recommended settings:
7728
7729 \<pre\>
7730 _ 1.25G: 0x3
7731 _ 2.5G: 0x3
7732 _ 3.125G: 0x3
7733 _ 5.0G: 0x3
7734 _ 6.25G: 0x3
7735 _ 8.0G: 0x5
7736 _ 10.3125G: 0x5
7737 \</pre\>
7738
7739 For SATA with 100 MHz reference clock, [PLL_RLOOP] should always be 3. */
7740 uint64_t pll_icp : 4; /**< [ 15: 12](R/W/H) PLL charge pump enable.
7741
7742 Recommended settings, which are based on the reference clock speed:
7743
7744 \<pre\>
7745 100MHz 125MHz 156.25MHz
7746 1.25G: 0x1 0x1 0x1
7747 2.5G: 0x4 0x3 0x3
7748 3.125G: NS 0x1 0x1
7749 5.0G: 0x1 0x1 0x1
7750 6.25G: NS 0x1 0x1
7751 8.0G: 0x3 0x2 NS
7752 10.3125G: NS NS 0x1
7753 \</pre\>
7754
7755 For SATA, [PLL_ICP] should always be 1.
7756 For PCIE 1.1 @100 MHz, [PLL_ICP] should be 4.
7757 For PCIE 2.1 @100 MHz, [PLL_ICP] should be 4.
7758 For PCIE 1.1 @125 MHz, [PLL_ICP] should be 3.
7759 For PCIE 2.1 @125 MHz, [PLL_ICP] should be 3.
7760
7761 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7762 uint64_t reserved_16_63 : 48;
7763 #endif /* Word 0 - End */
7764 } s;
7765 /* struct bdk_gserx_pll_px_mode_0_s cn81xx; */
7766 /* struct bdk_gserx_pll_px_mode_0_s cn88xx; */
7767 struct bdk_gserx_pll_px_mode_0_cn83xx
7768 {
7769 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7770 uint64_t reserved_16_63 : 48;
7771 uint64_t pll_icp : 4; /**< [ 15: 12](R/W/H) PLL charge pump enable.
7772
7773 Recommended settings, which are based on the reference clock speed:
7774
7775 \<pre\>
7776 100MHz 125MHz 156.25MHz
7777 1.25G: 0x1 0x1 0x1
7778 2.5G: 0x4 0x3 0x3
7779 3.125G: NS 0x1 0x1
7780 5.0G: 0x1 0x1 0x1
7781 6.25G: NS 0x1 0x1
7782 8.0G: 0x3 0x2 NS
7783 10.3125G: NS NS 0x1
7784 \</pre\>
7785
7786 For SATA, [PLL_ICP] should always be 1.
7787 For PCIE 1.1 @100MHz, [PLL_ICP] should be 4.
7788 For PCIE 2.1 @100MHz, [PLL_ICP] should be 4.
7789 For PCIE 1.1 @125MHz, [PLL_ICP] should be 3.
7790 For PCIE 2.1 @125MHz, [PLL_ICP] should be 3.
7791
7792 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7793 uint64_t pll_rloop : 3; /**< [ 11: 9](R/W/H) Loop resistor tuning.
7794
7795 Recommended settings:
7796
7797 \<pre\>
7798 _ 1.25G: 0x3
7799 _ 2.5G: 0x3
7800 _ 3.125G: 0x3
7801 _ 5.0G: 0x3
7802 _ 6.25G: 0x3
7803 _ 8.0G: 0x5
7804 _ 10.3125G: 0x5
7805 \</pre\>
7806
7807 For SATA with 100 MHz reference clock, [PLL_RLOOP] should always be 3. */
7808 uint64_t pll_pcs_div : 9; /**< [ 8: 0](R/W/H) The divider that generates PCS_MAC_TX_CLK. The frequency of the clock is (pll_frequency /
7809 PLL_PCS_DIV).
7810
7811 Recommended settings:
7812
7813 \<pre\>
7814 PCIE Other
7815 _ 1.25G: NS 0x28
7816 _ 2.5G: 0x5 0x5
7817 _ 3.125G: NS 0x14
7818 _ 5.0G: 0x5 0xA
7819 _ 6.25G: NS 0xA
7820 _ 8.0G: 0x8 0xA
7821 _ 10.3125G: NS 0xA
7822 \</pre\>
7823
7824 For SATA, [PLL_PCS_DIV] should always be 5.
7825
7826 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7827 #else /* Word 0 - Little Endian */
7828 uint64_t pll_pcs_div : 9; /**< [ 8: 0](R/W/H) The divider that generates PCS_MAC_TX_CLK. The frequency of the clock is (pll_frequency /
7829 PLL_PCS_DIV).
7830
7831 Recommended settings:
7832
7833 \<pre\>
7834 PCIE Other
7835 _ 1.25G: NS 0x28
7836 _ 2.5G: 0x5 0x5
7837 _ 3.125G: NS 0x14
7838 _ 5.0G: 0x5 0xA
7839 _ 6.25G: NS 0xA
7840 _ 8.0G: 0x8 0xA
7841 _ 10.3125G: NS 0xA
7842 \</pre\>
7843
7844 For SATA, [PLL_PCS_DIV] should always be 5.
7845
7846 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7847 uint64_t pll_rloop : 3; /**< [ 11: 9](R/W/H) Loop resistor tuning.
7848
7849 Recommended settings:
7850
7851 \<pre\>
7852 _ 1.25G: 0x3
7853 _ 2.5G: 0x3
7854 _ 3.125G: 0x3
7855 _ 5.0G: 0x3
7856 _ 6.25G: 0x3
7857 _ 8.0G: 0x5
7858 _ 10.3125G: 0x5
7859 \</pre\>
7860
7861 For SATA with 100 MHz reference clock, [PLL_RLOOP] should always be 3. */
7862 uint64_t pll_icp : 4; /**< [ 15: 12](R/W/H) PLL charge pump enable.
7863
7864 Recommended settings, which are based on the reference clock speed:
7865
7866 \<pre\>
7867 100MHz 125MHz 156.25MHz
7868 1.25G: 0x1 0x1 0x1
7869 2.5G: 0x4 0x3 0x3
7870 3.125G: NS 0x1 0x1
7871 5.0G: 0x1 0x1 0x1
7872 6.25G: NS 0x1 0x1
7873 8.0G: 0x3 0x2 NS
7874 10.3125G: NS NS 0x1
7875 \</pre\>
7876
7877 For SATA, [PLL_ICP] should always be 1.
7878 For PCIE 1.1 @100MHz, [PLL_ICP] should be 4.
7879 For PCIE 2.1 @100MHz, [PLL_ICP] should be 4.
7880 For PCIE 1.1 @125MHz, [PLL_ICP] should be 3.
7881 For PCIE 2.1 @125MHz, [PLL_ICP] should be 3.
7882
7883 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7884 uint64_t reserved_16_63 : 48;
7885 #endif /* Word 0 - End */
7886 } cn83xx;
7887 };
7888 typedef union bdk_gserx_pll_px_mode_0 bdk_gserx_pll_px_mode_0_t;
7889
7890 static inline uint64_t BDK_GSERX_PLL_PX_MODE_0(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_PLL_PX_MODE_0(unsigned long a,unsigned long b)7891 static inline uint64_t BDK_GSERX_PLL_PX_MODE_0(unsigned long a, unsigned long b)
7892 {
7893 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=11)))
7894 return 0x87e0904e0030ll + 0x1000000ll * ((a) & 0x3) + 0x20ll * ((b) & 0xf);
7895 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=11)))
7896 return 0x87e0904e0030ll + 0x1000000ll * ((a) & 0x7) + 0x20ll * ((b) & 0xf);
7897 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=11)))
7898 return 0x87e0904e0030ll + 0x1000000ll * ((a) & 0xf) + 0x20ll * ((b) & 0xf);
7899 __bdk_csr_fatal("GSERX_PLL_PX_MODE_0", 2, a, b, 0, 0);
7900 }
7901
7902 #define typedef_BDK_GSERX_PLL_PX_MODE_0(a,b) bdk_gserx_pll_px_mode_0_t
7903 #define bustype_BDK_GSERX_PLL_PX_MODE_0(a,b) BDK_CSR_TYPE_RSL
7904 #define basename_BDK_GSERX_PLL_PX_MODE_0(a,b) "GSERX_PLL_PX_MODE_0"
7905 #define device_bar_BDK_GSERX_PLL_PX_MODE_0(a,b) 0x0 /* PF_BAR0 */
7906 #define busnum_BDK_GSERX_PLL_PX_MODE_0(a,b) (a)
7907 #define arguments_BDK_GSERX_PLL_PX_MODE_0(a,b) (a),(b),-1,-1
7908
7909 /**
7910 * Register (RSL) gser#_pll_p#_mode_1
7911 *
7912 * GSER PLL Protocol Mode 1 Register
7913 * These are the RAW PCS PLL global settings mode 1 registers. There is one register per GSER per
7914 * GSER_LMODE_E value (0..11). Only one entry is used at any given time in a given GSER - the one
7915 * selected by the corresponding GSER()_LANE_MODE[LMODE].
7916 * These registers are reset by hardware only during chip cold reset.
7917 * The values of the CSR fields in this register do not change during subsequent chip warm or
7918 * soft resets.
7919 */
7920 union bdk_gserx_pll_px_mode_1
7921 {
7922 uint64_t u;
7923 struct bdk_gserx_pll_px_mode_1_s
7924 {
7925 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7926 uint64_t reserved_14_63 : 50;
7927 uint64_t pll_16p5en : 1; /**< [ 13: 13](R/W/H) Enable for the DIV 16.5 divided down clock.
7928
7929 Recommended settings, based on the reference clock speed:
7930
7931 \<pre\>
7932 100MHz 125MHz 156.25MHz
7933 1.25G: 0x1 0x1 0x1
7934 2.5G: 0x0 0x0 0x0
7935 3.125G: NS 0x1 0x1
7936 5.0G: 0x0 0x0 0x0
7937 6.25G: NS 0x0 0x0
7938 8.0G: 0x0 0x0 NS
7939 10.3125G: NS NS 0x1
7940 \</pre\>
7941
7942 For SATA, [PLL_16P5EN] should always be 0.
7943
7944 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7945 uint64_t pll_cpadj : 2; /**< [ 12: 11](R/W/H) PLL charge adjust.
7946
7947 Recommended settings, based on the reference clock speed:
7948
7949 \<pre\>
7950 100MHz 125MHz 156.25MHz
7951 1.25G: 0x2 0x2 0x3
7952 2.5G: 0x2 0x1 0x2
7953 3.125G: NS 0x2 0x2
7954 5.0G: 0x2 0x2 0x2
7955 6.25G: NS 0x2 0x2
7956 8.0G: 0x2 0x1 NS
7957 10.3125G: NS NS 0x2
7958 \</pre\>
7959
7960 For SATA with 100 MHz reference clock, [PLL_CPADJ] should always be 2.
7961 For PCIE 1.1 @100MHz, [PLL_CPADJ] should be 2.
7962 For PCIE 2.1 @100MHz, [PLL_CPADJ] should be 2.
7963 For PCIE 1.1 @125MHz, [PLL_CPADJ] should be 1.
7964 For PCIE 2.1 @125MHz, [PLL_CPADJ] should be 1.
7965
7966 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7967 uint64_t pll_pcie3en : 1; /**< [ 10: 10](R/W/H) Enable PCIE3 mode.
7968
7969 Recommended settings:
7970 0 = Any rate other than 8 Gbaud.
7971 1 = Rate is equal to 8 Gbaud.
7972
7973 For SATA, [PLL_PCIE3EN] should always be 0. */
7974 uint64_t pll_opr : 1; /**< [ 9: 9](R/W/H) PLL op range:
7975 0 = Use ring oscillator VCO. Recommended for rates 6.25 Gbaud and lower.
7976 1 = Use LC-tank VCO. Recommended for rates 8 Gbaud and higher.
7977
7978 For SATA, [PLL_OPR] should always be 0. */
7979 uint64_t pll_div : 9; /**< [ 8: 0](R/W/H) PLL divider in feedback path which sets the PLL frequency.
7980
7981 Recommended settings:
7982
7983 \<pre\>
7984 100MHz 125MHz 156.25MHz
7985 1.25G: 0x19 0x14 0x10
7986 2.5G: 0x19 0x14 0x10
7987 3.125G: NS 0x19 0x14
7988 5.0G: 0x19 0x14 0x10
7989 6.25G: NS 0x19 0x14
7990 8.0G: 0x28 0x20 NS
7991 10.3125G: NS NS 0x21
7992 \</pre\>
7993
7994 For SATA with 100MHz reference clock, [PLL_DIV] should always be 0x1E.
7995
7996 A 'NS' indicates that the rate is not supported at the specified reference clock. */
7997 #else /* Word 0 - Little Endian */
7998 uint64_t pll_div : 9; /**< [ 8: 0](R/W/H) PLL divider in feedback path which sets the PLL frequency.
7999
8000 Recommended settings:
8001
8002 \<pre\>
8003 100MHz 125MHz 156.25MHz
8004 1.25G: 0x19 0x14 0x10
8005 2.5G: 0x19 0x14 0x10
8006 3.125G: NS 0x19 0x14
8007 5.0G: 0x19 0x14 0x10
8008 6.25G: NS 0x19 0x14
8009 8.0G: 0x28 0x20 NS
8010 10.3125G: NS NS 0x21
8011 \</pre\>
8012
8013 For SATA with 100MHz reference clock, [PLL_DIV] should always be 0x1E.
8014
8015 A 'NS' indicates that the rate is not supported at the specified reference clock. */
8016 uint64_t pll_opr : 1; /**< [ 9: 9](R/W/H) PLL op range:
8017 0 = Use ring oscillator VCO. Recommended for rates 6.25 Gbaud and lower.
8018 1 = Use LC-tank VCO. Recommended for rates 8 Gbaud and higher.
8019
8020 For SATA, [PLL_OPR] should always be 0. */
8021 uint64_t pll_pcie3en : 1; /**< [ 10: 10](R/W/H) Enable PCIE3 mode.
8022
8023 Recommended settings:
8024 0 = Any rate other than 8 Gbaud.
8025 1 = Rate is equal to 8 Gbaud.
8026
8027 For SATA, [PLL_PCIE3EN] should always be 0. */
8028 uint64_t pll_cpadj : 2; /**< [ 12: 11](R/W/H) PLL charge adjust.
8029
8030 Recommended settings, based on the reference clock speed:
8031
8032 \<pre\>
8033 100MHz 125MHz 156.25MHz
8034 1.25G: 0x2 0x2 0x3
8035 2.5G: 0x2 0x1 0x2
8036 3.125G: NS 0x2 0x2
8037 5.0G: 0x2 0x2 0x2
8038 6.25G: NS 0x2 0x2
8039 8.0G: 0x2 0x1 NS
8040 10.3125G: NS NS 0x2
8041 \</pre\>
8042
8043 For SATA with 100 MHz reference clock, [PLL_CPADJ] should always be 2.
8044 For PCIE 1.1 @100MHz, [PLL_CPADJ] should be 2.
8045 For PCIE 2.1 @100MHz, [PLL_CPADJ] should be 2.
8046 For PCIE 1.1 @125MHz, [PLL_CPADJ] should be 1.
8047 For PCIE 2.1 @125MHz, [PLL_CPADJ] should be 1.
8048
8049 A 'NS' indicates that the rate is not supported at the specified reference clock. */
8050 uint64_t pll_16p5en : 1; /**< [ 13: 13](R/W/H) Enable for the DIV 16.5 divided down clock.
8051
8052 Recommended settings, based on the reference clock speed:
8053
8054 \<pre\>
8055 100MHz 125MHz 156.25MHz
8056 1.25G: 0x1 0x1 0x1
8057 2.5G: 0x0 0x0 0x0
8058 3.125G: NS 0x1 0x1
8059 5.0G: 0x0 0x0 0x0
8060 6.25G: NS 0x0 0x0
8061 8.0G: 0x0 0x0 NS
8062 10.3125G: NS NS 0x1
8063 \</pre\>
8064
8065 For SATA, [PLL_16P5EN] should always be 0.
8066
8067 A 'NS' indicates that the rate is not supported at the specified reference clock. */
8068 uint64_t reserved_14_63 : 50;
8069 #endif /* Word 0 - End */
8070 } s;
8071 /* struct bdk_gserx_pll_px_mode_1_s cn81xx; */
8072 /* struct bdk_gserx_pll_px_mode_1_s cn88xx; */
8073 struct bdk_gserx_pll_px_mode_1_cn83xx
8074 {
8075 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8076 uint64_t reserved_14_63 : 50;
8077 uint64_t pll_16p5en : 1; /**< [ 13: 13](R/W/H) Enable for the DIV 16.5 divided down clock.
8078
8079 Recommended settings, based on the reference clock speed:
8080
8081 \<pre\>
8082 100MHz 125MHz 156.25MHz
8083 1.25G: 0x1 0x1 0x1
8084 2.5G: 0x0 0x0 0x0
8085 3.125G: NS 0x1 0x1
8086 5.0G: 0x0 0x0 0x0
8087 6.25G: NS 0x0 0x0
8088 8.0G: 0x0 0x0 NS
8089 10.3125G: NS NS 0x1
8090 \</pre\>
8091
8092 For SATA, [PLL_16P5EN] should always be 0.
8093
8094 A 'NS' indicates that the rate is not supported at the specified reference clock. */
8095 uint64_t pll_cpadj : 2; /**< [ 12: 11](R/W/H) PLL charge adjust.
8096
8097 Recommended settings, based on the reference clock speed:
8098
8099 \<pre\>
8100 100MHz 125MHz 156.25MHz
8101 1.25G: 0x2 0x2 0x3
8102 2.5G: 0x2 0x1 0x2
8103 3.125G: NS 0x2 0x2
8104 5.0G: 0x2 0x2 0x2
8105 6.25G: NS 0x2 0x2
8106 8.0G: 0x2 0x1 NS
8107 10.3125G: NS NS 0x2
8108 \</pre\>
8109
8110 For SATA with 100 MHz reference clock, [PLL_CPADJ] should always be 2.
8111 For PCIE 1.1 @100MHz, [PLL_CPADJ] should be 2.
8112 For PCIE 2.1 @100MHz, [PLL_CPADJ] should be 2.
8113 For PCIE 1.1 @125MHz, [PLL_CPADJ] should be 1.
8114 For PCIE 2.1 @125MHz, [PLL_CPADJ] should be 1.
8115
8116 A 'NS' indicates that the rate is not supported at the specified reference clock. */
8117 uint64_t pll_pcie3en : 1; /**< [ 10: 10](R/W/H) Enable PCIE3 mode.
8118
8119 Recommended settings:
8120 0 = Any rate other than 8 Gbaud.
8121 1 = Rate is equal to 8 Gbaud.
8122
8123 For SATA, [PLL_PCIE3EN] should always be 0. */
8124 uint64_t pll_opr : 1; /**< [ 9: 9](R/W/H) PLL op range:
8125 0 = Use ring oscillator VCO. Recommended for rates 6.25 Gbaud and lower.
8126 1 = Use LC-tank VCO. Recommended for rates 8 Gbaud and higher.
8127
8128 For SATA, [PLL_OPR] should always be 0. */
8129 uint64_t pll_div : 9; /**< [ 8: 0](R/W/H) PLL divider in feedback path which sets the PLL frequency.
8130
8131 Recommended settings:
8132
8133 \<pre\>
8134 100MHz 125MHz 156.25MHz
8135 1.25G: 0x19 0x14 0x10
8136 2.5G: 0x19 0x14 0x10
8137 3.125G: NS 0x19 0x14
8138 5.0G: 0x19 0x14 0x10
8139 6.25G: NS 0x19 0x14
8140 8.0G: 0x28 0x20 NS
8141 10.3125G: NS NS 0x21
8142 \</pre\>
8143
8144 For SATA with 100 MHz reference clock, [PLL_DIV] should always be 0x1E.
8145
8146 A 'NS' indicates that the rate is not supported at the specified reference clock. */
8147 #else /* Word 0 - Little Endian */
8148 uint64_t pll_div : 9; /**< [ 8: 0](R/W/H) PLL divider in feedback path which sets the PLL frequency.
8149
8150 Recommended settings:
8151
8152 \<pre\>
8153 100MHz 125MHz 156.25MHz
8154 1.25G: 0x19 0x14 0x10
8155 2.5G: 0x19 0x14 0x10
8156 3.125G: NS 0x19 0x14
8157 5.0G: 0x19 0x14 0x10
8158 6.25G: NS 0x19 0x14
8159 8.0G: 0x28 0x20 NS
8160 10.3125G: NS NS 0x21
8161 \</pre\>
8162
8163 For SATA with 100 MHz reference clock, [PLL_DIV] should always be 0x1E.
8164
8165 A 'NS' indicates that the rate is not supported at the specified reference clock. */
8166 uint64_t pll_opr : 1; /**< [ 9: 9](R/W/H) PLL op range:
8167 0 = Use ring oscillator VCO. Recommended for rates 6.25 Gbaud and lower.
8168 1 = Use LC-tank VCO. Recommended for rates 8 Gbaud and higher.
8169
8170 For SATA, [PLL_OPR] should always be 0. */
8171 uint64_t pll_pcie3en : 1; /**< [ 10: 10](R/W/H) Enable PCIE3 mode.
8172
8173 Recommended settings:
8174 0 = Any rate other than 8 Gbaud.
8175 1 = Rate is equal to 8 Gbaud.
8176
8177 For SATA, [PLL_PCIE3EN] should always be 0. */
8178 uint64_t pll_cpadj : 2; /**< [ 12: 11](R/W/H) PLL charge adjust.
8179
8180 Recommended settings, based on the reference clock speed:
8181
8182 \<pre\>
8183 100MHz 125MHz 156.25MHz
8184 1.25G: 0x2 0x2 0x3
8185 2.5G: 0x2 0x1 0x2
8186 3.125G: NS 0x2 0x2
8187 5.0G: 0x2 0x2 0x2
8188 6.25G: NS 0x2 0x2
8189 8.0G: 0x2 0x1 NS
8190 10.3125G: NS NS 0x2
8191 \</pre\>
8192
8193 For SATA with 100 MHz reference clock, [PLL_CPADJ] should always be 2.
8194 For PCIE 1.1 @100MHz, [PLL_CPADJ] should be 2.
8195 For PCIE 2.1 @100MHz, [PLL_CPADJ] should be 2.
8196 For PCIE 1.1 @125MHz, [PLL_CPADJ] should be 1.
8197 For PCIE 2.1 @125MHz, [PLL_CPADJ] should be 1.
8198
8199 A 'NS' indicates that the rate is not supported at the specified reference clock. */
8200 uint64_t pll_16p5en : 1; /**< [ 13: 13](R/W/H) Enable for the DIV 16.5 divided down clock.
8201
8202 Recommended settings, based on the reference clock speed:
8203
8204 \<pre\>
8205 100MHz 125MHz 156.25MHz
8206 1.25G: 0x1 0x1 0x1
8207 2.5G: 0x0 0x0 0x0
8208 3.125G: NS 0x1 0x1
8209 5.0G: 0x0 0x0 0x0
8210 6.25G: NS 0x0 0x0
8211 8.0G: 0x0 0x0 NS
8212 10.3125G: NS NS 0x1
8213 \</pre\>
8214
8215 For SATA, [PLL_16P5EN] should always be 0.
8216
8217 A 'NS' indicates that the rate is not supported at the specified reference clock. */
8218 uint64_t reserved_14_63 : 50;
8219 #endif /* Word 0 - End */
8220 } cn83xx;
8221 };
8222 typedef union bdk_gserx_pll_px_mode_1 bdk_gserx_pll_px_mode_1_t;
8223
8224 static inline uint64_t BDK_GSERX_PLL_PX_MODE_1(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_PLL_PX_MODE_1(unsigned long a,unsigned long b)8225 static inline uint64_t BDK_GSERX_PLL_PX_MODE_1(unsigned long a, unsigned long b)
8226 {
8227 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=11)))
8228 return 0x87e0904e0038ll + 0x1000000ll * ((a) & 0x3) + 0x20ll * ((b) & 0xf);
8229 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=11)))
8230 return 0x87e0904e0038ll + 0x1000000ll * ((a) & 0x7) + 0x20ll * ((b) & 0xf);
8231 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=11)))
8232 return 0x87e0904e0038ll + 0x1000000ll * ((a) & 0xf) + 0x20ll * ((b) & 0xf);
8233 __bdk_csr_fatal("GSERX_PLL_PX_MODE_1", 2, a, b, 0, 0);
8234 }
8235
8236 #define typedef_BDK_GSERX_PLL_PX_MODE_1(a,b) bdk_gserx_pll_px_mode_1_t
8237 #define bustype_BDK_GSERX_PLL_PX_MODE_1(a,b) BDK_CSR_TYPE_RSL
8238 #define basename_BDK_GSERX_PLL_PX_MODE_1(a,b) "GSERX_PLL_PX_MODE_1"
8239 #define device_bar_BDK_GSERX_PLL_PX_MODE_1(a,b) 0x0 /* PF_BAR0 */
8240 #define busnum_BDK_GSERX_PLL_PX_MODE_1(a,b) (a)
8241 #define arguments_BDK_GSERX_PLL_PX_MODE_1(a,b) (a),(b),-1,-1
8242
8243 /**
8244 * Register (RSL) gser#_pll_stat
8245 *
8246 * GSER PLL Status Register
8247 */
8248 union bdk_gserx_pll_stat
8249 {
8250 uint64_t u;
8251 struct bdk_gserx_pll_stat_s
8252 {
8253 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8254 uint64_t reserved_1_63 : 63;
8255 uint64_t pll_lock : 1; /**< [ 0: 0](RO/H) When set, indicates that the PHY PLL is locked. */
8256 #else /* Word 0 - Little Endian */
8257 uint64_t pll_lock : 1; /**< [ 0: 0](RO/H) When set, indicates that the PHY PLL is locked. */
8258 uint64_t reserved_1_63 : 63;
8259 #endif /* Word 0 - End */
8260 } s;
8261 /* struct bdk_gserx_pll_stat_s cn; */
8262 };
8263 typedef union bdk_gserx_pll_stat bdk_gserx_pll_stat_t;
8264
8265 static inline uint64_t BDK_GSERX_PLL_STAT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_PLL_STAT(unsigned long a)8266 static inline uint64_t BDK_GSERX_PLL_STAT(unsigned long a)
8267 {
8268 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
8269 return 0x87e090000010ll + 0x1000000ll * ((a) & 0x3);
8270 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
8271 return 0x87e090000010ll + 0x1000000ll * ((a) & 0x7);
8272 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
8273 return 0x87e090000010ll + 0x1000000ll * ((a) & 0xf);
8274 __bdk_csr_fatal("GSERX_PLL_STAT", 1, a, 0, 0, 0);
8275 }
8276
8277 #define typedef_BDK_GSERX_PLL_STAT(a) bdk_gserx_pll_stat_t
8278 #define bustype_BDK_GSERX_PLL_STAT(a) BDK_CSR_TYPE_RSL
8279 #define basename_BDK_GSERX_PLL_STAT(a) "GSERX_PLL_STAT"
8280 #define device_bar_BDK_GSERX_PLL_STAT(a) 0x0 /* PF_BAR0 */
8281 #define busnum_BDK_GSERX_PLL_STAT(a) (a)
8282 #define arguments_BDK_GSERX_PLL_STAT(a) (a),-1,-1,-1
8283
8284 /**
8285 * Register (RSL) gser#_qlm_stat
8286 *
8287 * GSER QLM Status Register
8288 */
8289 union bdk_gserx_qlm_stat
8290 {
8291 uint64_t u;
8292 struct bdk_gserx_qlm_stat_s
8293 {
8294 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8295 uint64_t reserved_2_63 : 62;
8296 uint64_t rst_rdy : 1; /**< [ 1: 1](RO/H) When asserted, the QLM is configured and the PLLs are stable. The GSER
8297 is ready to accept TX traffic from the MAC. */
8298 uint64_t dcok : 1; /**< [ 0: 0](RO) When asserted, there is a PLL reference clock indicating there is power to the QLM. */
8299 #else /* Word 0 - Little Endian */
8300 uint64_t dcok : 1; /**< [ 0: 0](RO) When asserted, there is a PLL reference clock indicating there is power to the QLM. */
8301 uint64_t rst_rdy : 1; /**< [ 1: 1](RO/H) When asserted, the QLM is configured and the PLLs are stable. The GSER
8302 is ready to accept TX traffic from the MAC. */
8303 uint64_t reserved_2_63 : 62;
8304 #endif /* Word 0 - End */
8305 } s;
8306 /* struct bdk_gserx_qlm_stat_s cn; */
8307 };
8308 typedef union bdk_gserx_qlm_stat bdk_gserx_qlm_stat_t;
8309
8310 static inline uint64_t BDK_GSERX_QLM_STAT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_QLM_STAT(unsigned long a)8311 static inline uint64_t BDK_GSERX_QLM_STAT(unsigned long a)
8312 {
8313 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
8314 return 0x87e0900000a0ll + 0x1000000ll * ((a) & 0x3);
8315 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
8316 return 0x87e0900000a0ll + 0x1000000ll * ((a) & 0x7);
8317 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
8318 return 0x87e0900000a0ll + 0x1000000ll * ((a) & 0xf);
8319 __bdk_csr_fatal("GSERX_QLM_STAT", 1, a, 0, 0, 0);
8320 }
8321
8322 #define typedef_BDK_GSERX_QLM_STAT(a) bdk_gserx_qlm_stat_t
8323 #define bustype_BDK_GSERX_QLM_STAT(a) BDK_CSR_TYPE_RSL
8324 #define basename_BDK_GSERX_QLM_STAT(a) "GSERX_QLM_STAT"
8325 #define device_bar_BDK_GSERX_QLM_STAT(a) 0x0 /* PF_BAR0 */
8326 #define busnum_BDK_GSERX_QLM_STAT(a) (a)
8327 #define arguments_BDK_GSERX_QLM_STAT(a) (a),-1,-1,-1
8328
8329 /**
8330 * Register (RSL) gser#_rdet_time
8331 *
8332 * GSER Receiver Detect Wait Times Register
8333 * These registers are for diagnostic use only.
8334 * These registers are reset by hardware only during chip cold reset.
8335 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
8336 */
8337 union bdk_gserx_rdet_time
8338 {
8339 uint64_t u;
8340 struct bdk_gserx_rdet_time_s
8341 {
8342 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8343 uint64_t reserved_16_63 : 48;
8344 uint64_t rdet_time_3 : 4; /**< [ 15: 12](R/W) Determines the time allocated for disabling the RX detect
8345 circuit, and returning to common mode. */
8346 uint64_t rdet_time_2 : 4; /**< [ 11: 8](R/W) Determines the time allocated for the RX detect circuit to
8347 detect a receiver. */
8348 uint64_t rdet_time_1 : 8; /**< [ 7: 0](R/W) Determines the time allocated for enabling the RX detect circuit. */
8349 #else /* Word 0 - Little Endian */
8350 uint64_t rdet_time_1 : 8; /**< [ 7: 0](R/W) Determines the time allocated for enabling the RX detect circuit. */
8351 uint64_t rdet_time_2 : 4; /**< [ 11: 8](R/W) Determines the time allocated for the RX detect circuit to
8352 detect a receiver. */
8353 uint64_t rdet_time_3 : 4; /**< [ 15: 12](R/W) Determines the time allocated for disabling the RX detect
8354 circuit, and returning to common mode. */
8355 uint64_t reserved_16_63 : 48;
8356 #endif /* Word 0 - End */
8357 } s;
8358 /* struct bdk_gserx_rdet_time_s cn; */
8359 };
8360 typedef union bdk_gserx_rdet_time bdk_gserx_rdet_time_t;
8361
8362 static inline uint64_t BDK_GSERX_RDET_TIME(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RDET_TIME(unsigned long a)8363 static inline uint64_t BDK_GSERX_RDET_TIME(unsigned long a)
8364 {
8365 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
8366 return 0x87e0904e0008ll + 0x1000000ll * ((a) & 0x3);
8367 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
8368 return 0x87e0904e0008ll + 0x1000000ll * ((a) & 0x7);
8369 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
8370 return 0x87e0904e0008ll + 0x1000000ll * ((a) & 0xf);
8371 __bdk_csr_fatal("GSERX_RDET_TIME", 1, a, 0, 0, 0);
8372 }
8373
8374 #define typedef_BDK_GSERX_RDET_TIME(a) bdk_gserx_rdet_time_t
8375 #define bustype_BDK_GSERX_RDET_TIME(a) BDK_CSR_TYPE_RSL
8376 #define basename_BDK_GSERX_RDET_TIME(a) "GSERX_RDET_TIME"
8377 #define device_bar_BDK_GSERX_RDET_TIME(a) 0x0 /* PF_BAR0 */
8378 #define busnum_BDK_GSERX_RDET_TIME(a) (a)
8379 #define arguments_BDK_GSERX_RDET_TIME(a) (a),-1,-1,-1
8380
8381 /**
8382 * Register (RSL) gser#_refclk_evt_cntr
8383 *
8384 * GSER QLM Reference Clock Event Counter Register
8385 */
8386 union bdk_gserx_refclk_evt_cntr
8387 {
8388 uint64_t u;
8389 struct bdk_gserx_refclk_evt_cntr_s
8390 {
8391 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8392 uint64_t reserved_32_63 : 32;
8393 uint64_t count : 32; /**< [ 31: 0](RO) This register can only be reliably read when GSER()_REFCLK_EVT_CTRL[ENB]
8394 is clear.
8395
8396 When GSER()_REFCLK_EVT_CTRL[CLR] is set, [COUNT] goes to zero.
8397
8398 When GSER()_REFCLK_EVT_CTRL[ENB] is set, [COUNT] is incremented
8399 in positive edges of the QLM reference clock.
8400
8401 When GSER()_REFCLK_EVT_CTRL[ENB] is not set, [COUNT] is held; this must
8402 be used when [COUNT] is being read for reliable results. */
8403 #else /* Word 0 - Little Endian */
8404 uint64_t count : 32; /**< [ 31: 0](RO) This register can only be reliably read when GSER()_REFCLK_EVT_CTRL[ENB]
8405 is clear.
8406
8407 When GSER()_REFCLK_EVT_CTRL[CLR] is set, [COUNT] goes to zero.
8408
8409 When GSER()_REFCLK_EVT_CTRL[ENB] is set, [COUNT] is incremented
8410 in positive edges of the QLM reference clock.
8411
8412 When GSER()_REFCLK_EVT_CTRL[ENB] is not set, [COUNT] is held; this must
8413 be used when [COUNT] is being read for reliable results. */
8414 uint64_t reserved_32_63 : 32;
8415 #endif /* Word 0 - End */
8416 } s;
8417 /* struct bdk_gserx_refclk_evt_cntr_s cn; */
8418 };
8419 typedef union bdk_gserx_refclk_evt_cntr bdk_gserx_refclk_evt_cntr_t;
8420
8421 static inline uint64_t BDK_GSERX_REFCLK_EVT_CNTR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_REFCLK_EVT_CNTR(unsigned long a)8422 static inline uint64_t BDK_GSERX_REFCLK_EVT_CNTR(unsigned long a)
8423 {
8424 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
8425 return 0x87e090000178ll + 0x1000000ll * ((a) & 0x3);
8426 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
8427 return 0x87e090000178ll + 0x1000000ll * ((a) & 0x7);
8428 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
8429 return 0x87e090000178ll + 0x1000000ll * ((a) & 0xf);
8430 __bdk_csr_fatal("GSERX_REFCLK_EVT_CNTR", 1, a, 0, 0, 0);
8431 }
8432
8433 #define typedef_BDK_GSERX_REFCLK_EVT_CNTR(a) bdk_gserx_refclk_evt_cntr_t
8434 #define bustype_BDK_GSERX_REFCLK_EVT_CNTR(a) BDK_CSR_TYPE_RSL
8435 #define basename_BDK_GSERX_REFCLK_EVT_CNTR(a) "GSERX_REFCLK_EVT_CNTR"
8436 #define device_bar_BDK_GSERX_REFCLK_EVT_CNTR(a) 0x0 /* PF_BAR0 */
8437 #define busnum_BDK_GSERX_REFCLK_EVT_CNTR(a) (a)
8438 #define arguments_BDK_GSERX_REFCLK_EVT_CNTR(a) (a),-1,-1,-1
8439
8440 /**
8441 * Register (RSL) gser#_refclk_evt_ctrl
8442 *
8443 * GSER QLM Reference Clock Event Counter Control Register
8444 */
8445 union bdk_gserx_refclk_evt_ctrl
8446 {
8447 uint64_t u;
8448 struct bdk_gserx_refclk_evt_ctrl_s
8449 {
8450 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8451 uint64_t reserved_2_63 : 62;
8452 uint64_t clr : 1; /**< [ 1: 1](R/W) When set, clears GSER()_REFCLK_EVT_CNTR[COUNT]. */
8453 uint64_t enb : 1; /**< [ 0: 0](R/W) When set, enables the GSER()_REFCLK_EVT_CNTR[COUNT] to increment
8454 on positive edges of the QLM reference clock. */
8455 #else /* Word 0 - Little Endian */
8456 uint64_t enb : 1; /**< [ 0: 0](R/W) When set, enables the GSER()_REFCLK_EVT_CNTR[COUNT] to increment
8457 on positive edges of the QLM reference clock. */
8458 uint64_t clr : 1; /**< [ 1: 1](R/W) When set, clears GSER()_REFCLK_EVT_CNTR[COUNT]. */
8459 uint64_t reserved_2_63 : 62;
8460 #endif /* Word 0 - End */
8461 } s;
8462 /* struct bdk_gserx_refclk_evt_ctrl_s cn; */
8463 };
8464 typedef union bdk_gserx_refclk_evt_ctrl bdk_gserx_refclk_evt_ctrl_t;
8465
8466 static inline uint64_t BDK_GSERX_REFCLK_EVT_CTRL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_REFCLK_EVT_CTRL(unsigned long a)8467 static inline uint64_t BDK_GSERX_REFCLK_EVT_CTRL(unsigned long a)
8468 {
8469 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
8470 return 0x87e090000170ll + 0x1000000ll * ((a) & 0x3);
8471 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
8472 return 0x87e090000170ll + 0x1000000ll * ((a) & 0x7);
8473 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
8474 return 0x87e090000170ll + 0x1000000ll * ((a) & 0xf);
8475 __bdk_csr_fatal("GSERX_REFCLK_EVT_CTRL", 1, a, 0, 0, 0);
8476 }
8477
8478 #define typedef_BDK_GSERX_REFCLK_EVT_CTRL(a) bdk_gserx_refclk_evt_ctrl_t
8479 #define bustype_BDK_GSERX_REFCLK_EVT_CTRL(a) BDK_CSR_TYPE_RSL
8480 #define basename_BDK_GSERX_REFCLK_EVT_CTRL(a) "GSERX_REFCLK_EVT_CTRL"
8481 #define device_bar_BDK_GSERX_REFCLK_EVT_CTRL(a) 0x0 /* PF_BAR0 */
8482 #define busnum_BDK_GSERX_REFCLK_EVT_CTRL(a) (a)
8483 #define arguments_BDK_GSERX_REFCLK_EVT_CTRL(a) (a),-1,-1,-1
8484
8485 /**
8486 * Register (RSL) gser#_refclk_sel
8487 *
8488 * GSER Reference Clock Select Register
8489 * This register selects the reference clock.
8490 * These registers are reset by hardware only during chip cold reset. The values of the CSR
8491 * fields in these registers do not change during chip warm or soft resets.
8492 */
8493 union bdk_gserx_refclk_sel
8494 {
8495 uint64_t u;
8496 struct bdk_gserx_refclk_sel_s
8497 {
8498 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8499 uint64_t reserved_3_63 : 61;
8500 uint64_t pcie_refclk125 : 1; /**< [ 2: 2](R/W/H) For bootable PCIe links, this is loaded with
8501 PCIE0/2_REFCLK_125 at cold reset and indicates a 125 MHz reference clock when set. For
8502 non-bootable PCIe links, this bit is set to zero at cold reset and indicates a 100 MHz
8503 reference clock. It is not used for non-PCIe links. */
8504 uint64_t com_clk_sel : 1; /**< [ 1: 1](R/W/H) When set, the reference clock is sourced from the external clock mux. For bootable PCIe
8505 links, this bit is loaded with the PCIEn_COM0_CLK_EN pin at cold reset.
8506
8507 For CN80XX, this field must be set. */
8508 uint64_t use_com1 : 1; /**< [ 0: 0](R/W) This bit controls the external mux select. When set, DLMC_REF_CLK1_N/P
8509 are selected as the reference clock. When clear, DLMC_REF_CLK0_N/P are selected as the
8510 reference clock. */
8511 #else /* Word 0 - Little Endian */
8512 uint64_t use_com1 : 1; /**< [ 0: 0](R/W) This bit controls the external mux select. When set, DLMC_REF_CLK1_N/P
8513 are selected as the reference clock. When clear, DLMC_REF_CLK0_N/P are selected as the
8514 reference clock. */
8515 uint64_t com_clk_sel : 1; /**< [ 1: 1](R/W/H) When set, the reference clock is sourced from the external clock mux. For bootable PCIe
8516 links, this bit is loaded with the PCIEn_COM0_CLK_EN pin at cold reset.
8517
8518 For CN80XX, this field must be set. */
8519 uint64_t pcie_refclk125 : 1; /**< [ 2: 2](R/W/H) For bootable PCIe links, this is loaded with
8520 PCIE0/2_REFCLK_125 at cold reset and indicates a 125 MHz reference clock when set. For
8521 non-bootable PCIe links, this bit is set to zero at cold reset and indicates a 100 MHz
8522 reference clock. It is not used for non-PCIe links. */
8523 uint64_t reserved_3_63 : 61;
8524 #endif /* Word 0 - End */
8525 } s;
8526 /* struct bdk_gserx_refclk_sel_s cn81xx; */
8527 struct bdk_gserx_refclk_sel_cn88xx
8528 {
8529 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8530 uint64_t reserved_3_63 : 61;
8531 uint64_t pcie_refclk125 : 1; /**< [ 2: 2](R/W/H) For bootable PCIe links, this is loaded with
8532 PCIE0/2_REFCLK_125 at cold reset and indicates a 125 MHz reference clock when set. For
8533 non-bootable PCIe links, this bit is set to zero at cold reset and indicates a 100 MHz
8534 reference clock. It is not used for non-PCIe links. */
8535 uint64_t com_clk_sel : 1; /**< [ 1: 1](R/W/H) When set, the reference clock is sourced from the external clock mux. For bootable PCIe
8536 links, this bit is loaded with the PCIEn_COM0_CLK_EN pin at cold reset. */
8537 uint64_t use_com1 : 1; /**< [ 0: 0](R/W) For non-CCPI links, this bit controls the external mux select. When set, QLMC_REF_CLK1_N/P
8538 are selected as the reference clock. When clear, QLMC_REF_CLK0_N/P are selected as the
8539 reference clock. */
8540 #else /* Word 0 - Little Endian */
8541 uint64_t use_com1 : 1; /**< [ 0: 0](R/W) For non-CCPI links, this bit controls the external mux select. When set, QLMC_REF_CLK1_N/P
8542 are selected as the reference clock. When clear, QLMC_REF_CLK0_N/P are selected as the
8543 reference clock. */
8544 uint64_t com_clk_sel : 1; /**< [ 1: 1](R/W/H) When set, the reference clock is sourced from the external clock mux. For bootable PCIe
8545 links, this bit is loaded with the PCIEn_COM0_CLK_EN pin at cold reset. */
8546 uint64_t pcie_refclk125 : 1; /**< [ 2: 2](R/W/H) For bootable PCIe links, this is loaded with
8547 PCIE0/2_REFCLK_125 at cold reset and indicates a 125 MHz reference clock when set. For
8548 non-bootable PCIe links, this bit is set to zero at cold reset and indicates a 100 MHz
8549 reference clock. It is not used for non-PCIe links. */
8550 uint64_t reserved_3_63 : 61;
8551 #endif /* Word 0 - End */
8552 } cn88xx;
8553 struct bdk_gserx_refclk_sel_cn83xx
8554 {
8555 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8556 uint64_t reserved_3_63 : 61;
8557 uint64_t pcie_refclk125 : 1; /**< [ 2: 2](R/W/H) For bootable PCIe links, this is loaded with
8558 PCIE0/2_REFCLK_125 at cold reset and indicates a 125 MHz reference clock when set. For
8559 non-bootable PCIe links, this bit is set to zero at cold reset and indicates a 100 MHz
8560 reference clock. It is not used for non-PCIe links. */
8561 uint64_t com_clk_sel : 1; /**< [ 1: 1](R/W/H) When set, the reference clock is sourced from the external clock mux. For bootable PCIe
8562 links, this bit is loaded with the PCIEn_COM0_CLK_EN pin at cold reset. */
8563 uint64_t use_com1 : 1; /**< [ 0: 0](R/W) This bit controls the external mux select. When set, QLMC_REF_CLK1_N/P
8564 are selected as the reference clock. When clear, QLMC_REF_CLK0_N/P are selected as the
8565 reference clock. */
8566 #else /* Word 0 - Little Endian */
8567 uint64_t use_com1 : 1; /**< [ 0: 0](R/W) This bit controls the external mux select. When set, QLMC_REF_CLK1_N/P
8568 are selected as the reference clock. When clear, QLMC_REF_CLK0_N/P are selected as the
8569 reference clock. */
8570 uint64_t com_clk_sel : 1; /**< [ 1: 1](R/W/H) When set, the reference clock is sourced from the external clock mux. For bootable PCIe
8571 links, this bit is loaded with the PCIEn_COM0_CLK_EN pin at cold reset. */
8572 uint64_t pcie_refclk125 : 1; /**< [ 2: 2](R/W/H) For bootable PCIe links, this is loaded with
8573 PCIE0/2_REFCLK_125 at cold reset and indicates a 125 MHz reference clock when set. For
8574 non-bootable PCIe links, this bit is set to zero at cold reset and indicates a 100 MHz
8575 reference clock. It is not used for non-PCIe links. */
8576 uint64_t reserved_3_63 : 61;
8577 #endif /* Word 0 - End */
8578 } cn83xx;
8579 };
8580 typedef union bdk_gserx_refclk_sel bdk_gserx_refclk_sel_t;
8581
8582 static inline uint64_t BDK_GSERX_REFCLK_SEL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_REFCLK_SEL(unsigned long a)8583 static inline uint64_t BDK_GSERX_REFCLK_SEL(unsigned long a)
8584 {
8585 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
8586 return 0x87e090000008ll + 0x1000000ll * ((a) & 0x3);
8587 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
8588 return 0x87e090000008ll + 0x1000000ll * ((a) & 0x7);
8589 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
8590 return 0x87e090000008ll + 0x1000000ll * ((a) & 0xf);
8591 __bdk_csr_fatal("GSERX_REFCLK_SEL", 1, a, 0, 0, 0);
8592 }
8593
8594 #define typedef_BDK_GSERX_REFCLK_SEL(a) bdk_gserx_refclk_sel_t
8595 #define bustype_BDK_GSERX_REFCLK_SEL(a) BDK_CSR_TYPE_RSL
8596 #define basename_BDK_GSERX_REFCLK_SEL(a) "GSERX_REFCLK_SEL"
8597 #define device_bar_BDK_GSERX_REFCLK_SEL(a) 0x0 /* PF_BAR0 */
8598 #define busnum_BDK_GSERX_REFCLK_SEL(a) (a)
8599 #define arguments_BDK_GSERX_REFCLK_SEL(a) (a),-1,-1,-1
8600
8601 /**
8602 * Register (RSL) gser#_rx_coast
8603 *
8604 * GSER RX Coast Register
8605 * These registers are reset by hardware only during chip cold reset. The values of the CSR
8606 * fields in these registers do not change during chip warm or soft resets.
8607 */
8608 union bdk_gserx_rx_coast
8609 {
8610 uint64_t u;
8611 struct bdk_gserx_rx_coast_s
8612 {
8613 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8614 uint64_t reserved_4_63 : 60;
8615 uint64_t coast : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode, control signals to freeze
8616 the frequency of the per lane CDR in the PHY. The COAST signals are only valid in P0
8617 state, come up asserted and are deasserted in hardware after detecting the electrical idle
8618 exit (GSER()_RX_EIE_DETSTS[EIESTS]). Once the COAST signal deasserts, the CDR is
8619 allowed to lock. In BGX mode, the BGX MAC can also control the COAST inputs to the PHY to
8620 allow Auto-Negotiation for backplane Ethernet. For diagnostic use only.
8621 \<3\>: Lane 3. Reserved.
8622 \<2\>: Lane 2. Reserved.
8623 \<1\>: Lane 1.
8624 \<0\>: Lane 0. */
8625 #else /* Word 0 - Little Endian */
8626 uint64_t coast : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode, control signals to freeze
8627 the frequency of the per lane CDR in the PHY. The COAST signals are only valid in P0
8628 state, come up asserted and are deasserted in hardware after detecting the electrical idle
8629 exit (GSER()_RX_EIE_DETSTS[EIESTS]). Once the COAST signal deasserts, the CDR is
8630 allowed to lock. In BGX mode, the BGX MAC can also control the COAST inputs to the PHY to
8631 allow Auto-Negotiation for backplane Ethernet. For diagnostic use only.
8632 \<3\>: Lane 3. Reserved.
8633 \<2\>: Lane 2. Reserved.
8634 \<1\>: Lane 1.
8635 \<0\>: Lane 0. */
8636 uint64_t reserved_4_63 : 60;
8637 #endif /* Word 0 - End */
8638 } s;
8639 /* struct bdk_gserx_rx_coast_s cn81xx; */
8640 struct bdk_gserx_rx_coast_cn88xx
8641 {
8642 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8643 uint64_t reserved_4_63 : 60;
8644 uint64_t coast : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode (including all CCPI links), control signals to
8645 freeze
8646 the frequency of the per lane CDR in the PHY. The COAST signals are only valid in P0
8647 state, come up asserted and are deasserted in hardware after detecting the electrical idle
8648 exit (GSER()_RX_EIE_DETSTS[EIESTS]). Once the COAST signal deasserts, the CDR is
8649 allowed to lock. In BGX mode, the BGX MAC can also control the COAST inputs to the PHY to
8650 allow Auto-Negotiation for backplane Ethernet. For diagnostic use only.
8651 \<3\>: Lane 3.
8652 \<2\>: Lane 2.
8653 \<1\>: Lane 1.
8654 \<0\>: Lane 0. */
8655 #else /* Word 0 - Little Endian */
8656 uint64_t coast : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode (including all CCPI links), control signals to
8657 freeze
8658 the frequency of the per lane CDR in the PHY. The COAST signals are only valid in P0
8659 state, come up asserted and are deasserted in hardware after detecting the electrical idle
8660 exit (GSER()_RX_EIE_DETSTS[EIESTS]). Once the COAST signal deasserts, the CDR is
8661 allowed to lock. In BGX mode, the BGX MAC can also control the COAST inputs to the PHY to
8662 allow Auto-Negotiation for backplane Ethernet. For diagnostic use only.
8663 \<3\>: Lane 3.
8664 \<2\>: Lane 2.
8665 \<1\>: Lane 1.
8666 \<0\>: Lane 0. */
8667 uint64_t reserved_4_63 : 60;
8668 #endif /* Word 0 - End */
8669 } cn88xx;
8670 struct bdk_gserx_rx_coast_cn83xx
8671 {
8672 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8673 uint64_t reserved_4_63 : 60;
8674 uint64_t coast : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode, control signals to freeze
8675 the frequency of the per lane CDR in the PHY. The COAST signals are only valid in P0
8676 state, come up asserted and are deasserted in hardware after detecting the electrical idle
8677 exit (GSER()_RX_EIE_DETSTS[EIESTS]). Once the COAST signal deasserts, the CDR is
8678 allowed to lock. In BGX mode, the BGX MAC can also control the COAST inputs to the PHY to
8679 allow Auto-Negotiation for backplane Ethernet. For diagnostic use only.
8680 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
8681 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
8682 \<1\>: Lane 1.
8683 \<0\>: Lane 0. */
8684 #else /* Word 0 - Little Endian */
8685 uint64_t coast : 4; /**< [ 3: 0](R/W/H) For links that are not in PCIE or SATA mode, control signals to freeze
8686 the frequency of the per lane CDR in the PHY. The COAST signals are only valid in P0
8687 state, come up asserted and are deasserted in hardware after detecting the electrical idle
8688 exit (GSER()_RX_EIE_DETSTS[EIESTS]). Once the COAST signal deasserts, the CDR is
8689 allowed to lock. In BGX mode, the BGX MAC can also control the COAST inputs to the PHY to
8690 allow Auto-Negotiation for backplane Ethernet. For diagnostic use only.
8691 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
8692 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
8693 \<1\>: Lane 1.
8694 \<0\>: Lane 0. */
8695 uint64_t reserved_4_63 : 60;
8696 #endif /* Word 0 - End */
8697 } cn83xx;
8698 };
8699 typedef union bdk_gserx_rx_coast bdk_gserx_rx_coast_t;
8700
8701 static inline uint64_t BDK_GSERX_RX_COAST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RX_COAST(unsigned long a)8702 static inline uint64_t BDK_GSERX_RX_COAST(unsigned long a)
8703 {
8704 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
8705 return 0x87e090000138ll + 0x1000000ll * ((a) & 0x3);
8706 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
8707 return 0x87e090000138ll + 0x1000000ll * ((a) & 0x7);
8708 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
8709 return 0x87e090000138ll + 0x1000000ll * ((a) & 0xf);
8710 __bdk_csr_fatal("GSERX_RX_COAST", 1, a, 0, 0, 0);
8711 }
8712
8713 #define typedef_BDK_GSERX_RX_COAST(a) bdk_gserx_rx_coast_t
8714 #define bustype_BDK_GSERX_RX_COAST(a) BDK_CSR_TYPE_RSL
8715 #define basename_BDK_GSERX_RX_COAST(a) "GSERX_RX_COAST"
8716 #define device_bar_BDK_GSERX_RX_COAST(a) 0x0 /* PF_BAR0 */
8717 #define busnum_BDK_GSERX_RX_COAST(a) (a)
8718 #define arguments_BDK_GSERX_RX_COAST(a) (a),-1,-1,-1
8719
8720 /**
8721 * Register (RSL) gser#_rx_eie_deten
8722 *
8723 * GSER RX Electrical Idle Detect Enable Register
8724 * These registers are reset by hardware only during chip cold reset. The values of the CSR
8725 * fields in these registers do not change during chip warm or soft resets.
8726 */
8727 union bdk_gserx_rx_eie_deten
8728 {
8729 uint64_t u;
8730 struct bdk_gserx_rx_eie_deten_s
8731 {
8732 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8733 uint64_t reserved_4_63 : 60;
8734 uint64_t eiede : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode, these bits enable per lane
8735 electrical idle exit (EIE) detection. When EIE is detected,
8736 GSER()_RX_EIE_DETSTS[EIELTCH] is asserted. [EIEDE] defaults to the enabled state. Once
8737 EIE has been detected, [EIEDE] must be disabled, and then enabled again to perform another
8738 EIE detection.
8739 \<3\>: Lane 3. Reserved.
8740 \<2\>: Lane 2. Reserved.
8741 \<1\>: Lane 1.
8742 \<0\>: Lane 0. */
8743 #else /* Word 0 - Little Endian */
8744 uint64_t eiede : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode, these bits enable per lane
8745 electrical idle exit (EIE) detection. When EIE is detected,
8746 GSER()_RX_EIE_DETSTS[EIELTCH] is asserted. [EIEDE] defaults to the enabled state. Once
8747 EIE has been detected, [EIEDE] must be disabled, and then enabled again to perform another
8748 EIE detection.
8749 \<3\>: Lane 3. Reserved.
8750 \<2\>: Lane 2. Reserved.
8751 \<1\>: Lane 1.
8752 \<0\>: Lane 0. */
8753 uint64_t reserved_4_63 : 60;
8754 #endif /* Word 0 - End */
8755 } s;
8756 /* struct bdk_gserx_rx_eie_deten_s cn81xx; */
8757 struct bdk_gserx_rx_eie_deten_cn88xx
8758 {
8759 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8760 uint64_t reserved_4_63 : 60;
8761 uint64_t eiede : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode (including all CCPI links), these bits enable
8762 per lane
8763 electrical idle exit (EIE) detection. When EIE is detected,
8764 GSER()_RX_EIE_DETSTS[EIELTCH] is asserted. [EIEDE] defaults to the enabled state. Once
8765 EIE has been detected, [EIEDE] must be disabled, and then enabled again to perform another
8766 EIE detection.
8767 \<3\>: Lane 3.
8768 \<2\>: Lane 2.
8769 \<1\>: Lane 1.
8770 \<0\>: Lane 0. */
8771 #else /* Word 0 - Little Endian */
8772 uint64_t eiede : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode (including all CCPI links), these bits enable
8773 per lane
8774 electrical idle exit (EIE) detection. When EIE is detected,
8775 GSER()_RX_EIE_DETSTS[EIELTCH] is asserted. [EIEDE] defaults to the enabled state. Once
8776 EIE has been detected, [EIEDE] must be disabled, and then enabled again to perform another
8777 EIE detection.
8778 \<3\>: Lane 3.
8779 \<2\>: Lane 2.
8780 \<1\>: Lane 1.
8781 \<0\>: Lane 0. */
8782 uint64_t reserved_4_63 : 60;
8783 #endif /* Word 0 - End */
8784 } cn88xx;
8785 struct bdk_gserx_rx_eie_deten_cn83xx
8786 {
8787 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8788 uint64_t reserved_4_63 : 60;
8789 uint64_t eiede : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode, these bits enable per lane
8790 electrical idle exit (EIE) detection. When EIE is detected,
8791 GSER()_RX_EIE_DETSTS[EIELTCH] is asserted. [EIEDE] defaults to the enabled state. Once
8792 EIE has been detected, [EIEDE] must be disabled, and then enabled again to perform another
8793 EIE detection.
8794 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
8795 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
8796 \<1\>: Lane 1.
8797 \<0\>: Lane 0. */
8798 #else /* Word 0 - Little Endian */
8799 uint64_t eiede : 4; /**< [ 3: 0](R/W) For links that are not in PCIE or SATA mode, these bits enable per lane
8800 electrical idle exit (EIE) detection. When EIE is detected,
8801 GSER()_RX_EIE_DETSTS[EIELTCH] is asserted. [EIEDE] defaults to the enabled state. Once
8802 EIE has been detected, [EIEDE] must be disabled, and then enabled again to perform another
8803 EIE detection.
8804 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
8805 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
8806 \<1\>: Lane 1.
8807 \<0\>: Lane 0. */
8808 uint64_t reserved_4_63 : 60;
8809 #endif /* Word 0 - End */
8810 } cn83xx;
8811 };
8812 typedef union bdk_gserx_rx_eie_deten bdk_gserx_rx_eie_deten_t;
8813
8814 static inline uint64_t BDK_GSERX_RX_EIE_DETEN(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RX_EIE_DETEN(unsigned long a)8815 static inline uint64_t BDK_GSERX_RX_EIE_DETEN(unsigned long a)
8816 {
8817 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
8818 return 0x87e090000148ll + 0x1000000ll * ((a) & 0x3);
8819 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
8820 return 0x87e090000148ll + 0x1000000ll * ((a) & 0x7);
8821 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
8822 return 0x87e090000148ll + 0x1000000ll * ((a) & 0xf);
8823 __bdk_csr_fatal("GSERX_RX_EIE_DETEN", 1, a, 0, 0, 0);
8824 }
8825
8826 #define typedef_BDK_GSERX_RX_EIE_DETEN(a) bdk_gserx_rx_eie_deten_t
8827 #define bustype_BDK_GSERX_RX_EIE_DETEN(a) BDK_CSR_TYPE_RSL
8828 #define basename_BDK_GSERX_RX_EIE_DETEN(a) "GSERX_RX_EIE_DETEN"
8829 #define device_bar_BDK_GSERX_RX_EIE_DETEN(a) 0x0 /* PF_BAR0 */
8830 #define busnum_BDK_GSERX_RX_EIE_DETEN(a) (a)
8831 #define arguments_BDK_GSERX_RX_EIE_DETEN(a) (a),-1,-1,-1
8832
8833 /**
8834 * Register (RSL) gser#_rx_eie_detsts
8835 *
8836 * GSER RX Electrical Idle Detect Status Register
8837 */
8838 union bdk_gserx_rx_eie_detsts
8839 {
8840 uint64_t u;
8841 struct bdk_gserx_rx_eie_detsts_s
8842 {
8843 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8844 uint64_t reserved_12_63 : 52;
8845 uint64_t cdrlock : 4; /**< [ 11: 8](RO/H) After an electrical idle exit condition (EIE) has been detected, the CDR needs 10000 UI to
8846 lock. During this time, there may be RX bit errors. These bits will set when the CDR is
8847 guaranteed to be locked. Note that link training can't start until the lane CDRLOCK is
8848 set. Software can use CDRLOCK to determine when to expect error free RX data.
8849 \<11\>: Lane 3. Reserved.
8850 \<10\>: Lane 2. Reserved.
8851 \<9\>: Lane 1.
8852 \<8\>: Lane 0. */
8853 uint64_t eiests : 4; /**< [ 7: 4](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
8854 asserted), indicates that an electrical idle exit condition (EIE) was detected. For higher
8855 data rates, the received data needs to have sufficient low frequency content (for example,
8856 idle symbols) for data transitions to be detected and for [EIESTS] to stay set
8857 accordingly.
8858 Under most conditions, [EIESTS]
8859 will stay asserted until GSER()_RX_EIE_DETEN[EIEDE] is deasserted.
8860 \<7\>: Lane 3. Reserved.
8861 \<6\>: Lane 2. Reserved.
8862 \<5\>: Lane 1.
8863 \<4\>: Lane 0. */
8864 uint64_t eieltch : 4; /**< [ 3: 0](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
8865 asserted), indicates that an electrical idle exit condition (EIE) was detected. Once an
8866 EIE condition has been detected, the per-lane [EIELTCH] will stay set until
8867 GSER()_RX_EIE_DETEN[EIEDE] is deasserted. Note that there may be RX bit errors until
8868 CDRLOCK
8869 is set.
8870 \<3\>: Lane 3. Reserved.
8871 \<2\>: Lane 2. Reserved.
8872 \<1\>: Lane 1.
8873 \<0\>: Lane 0. */
8874 #else /* Word 0 - Little Endian */
8875 uint64_t eieltch : 4; /**< [ 3: 0](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
8876 asserted), indicates that an electrical idle exit condition (EIE) was detected. Once an
8877 EIE condition has been detected, the per-lane [EIELTCH] will stay set until
8878 GSER()_RX_EIE_DETEN[EIEDE] is deasserted. Note that there may be RX bit errors until
8879 CDRLOCK
8880 is set.
8881 \<3\>: Lane 3. Reserved.
8882 \<2\>: Lane 2. Reserved.
8883 \<1\>: Lane 1.
8884 \<0\>: Lane 0. */
8885 uint64_t eiests : 4; /**< [ 7: 4](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
8886 asserted), indicates that an electrical idle exit condition (EIE) was detected. For higher
8887 data rates, the received data needs to have sufficient low frequency content (for example,
8888 idle symbols) for data transitions to be detected and for [EIESTS] to stay set
8889 accordingly.
8890 Under most conditions, [EIESTS]
8891 will stay asserted until GSER()_RX_EIE_DETEN[EIEDE] is deasserted.
8892 \<7\>: Lane 3. Reserved.
8893 \<6\>: Lane 2. Reserved.
8894 \<5\>: Lane 1.
8895 \<4\>: Lane 0. */
8896 uint64_t cdrlock : 4; /**< [ 11: 8](RO/H) After an electrical idle exit condition (EIE) has been detected, the CDR needs 10000 UI to
8897 lock. During this time, there may be RX bit errors. These bits will set when the CDR is
8898 guaranteed to be locked. Note that link training can't start until the lane CDRLOCK is
8899 set. Software can use CDRLOCK to determine when to expect error free RX data.
8900 \<11\>: Lane 3. Reserved.
8901 \<10\>: Lane 2. Reserved.
8902 \<9\>: Lane 1.
8903 \<8\>: Lane 0. */
8904 uint64_t reserved_12_63 : 52;
8905 #endif /* Word 0 - End */
8906 } s;
8907 /* struct bdk_gserx_rx_eie_detsts_s cn81xx; */
8908 struct bdk_gserx_rx_eie_detsts_cn88xx
8909 {
8910 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8911 uint64_t reserved_12_63 : 52;
8912 uint64_t cdrlock : 4; /**< [ 11: 8](RO/H) After an electrical idle exit condition (EIE) has been detected, the CDR needs 10000 UI to
8913 lock. During this time, there may be RX bit errors. These bits will set when the CDR is
8914 guaranteed to be locked. Note that link training can't start until the lane CDRLOCK is
8915 set. Software can use CDRLOCK to determine when to expect error free RX data.
8916 \<11\>: Lane 3.
8917 \<10\>: Lane 2.
8918 \<9\>: Lane 1.
8919 \<8\>: Lane 0. */
8920 uint64_t eiests : 4; /**< [ 7: 4](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
8921 asserted), indicates that an electrical idle exit condition (EIE) was detected. For higher
8922 data rates, the received data needs to have sufficient low frequency content (for example,
8923 idle symbols) for data transitions to be detected and for [EIESTS] to stay set
8924 accordingly.
8925 Under most conditions, [EIESTS]
8926 will stay asserted until GSER()_RX_EIE_DETEN[EIEDE] is deasserted.
8927 \<7\>: Lane 3.
8928 \<6\>: Lane 2.
8929 \<5\>: Lane 1.
8930 \<4\>: Lane 0. */
8931 uint64_t eieltch : 4; /**< [ 3: 0](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
8932 asserted), indicates that an electrical idle exit condition (EIE) was detected. Once an
8933 EIE condition has been detected, the per-lane [EIELTCH] will stay set until
8934 GSER()_RX_EIE_DETEN[EIEDE] is deasserted. Note that there may be RX bit errors until
8935 CDRLOCK
8936 is set.
8937 \<3\>: Lane 3.
8938 \<2\>: Lane 2.
8939 \<1\>: Lane 1.
8940 \<0\>: Lane 0. */
8941 #else /* Word 0 - Little Endian */
8942 uint64_t eieltch : 4; /**< [ 3: 0](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
8943 asserted), indicates that an electrical idle exit condition (EIE) was detected. Once an
8944 EIE condition has been detected, the per-lane [EIELTCH] will stay set until
8945 GSER()_RX_EIE_DETEN[EIEDE] is deasserted. Note that there may be RX bit errors until
8946 CDRLOCK
8947 is set.
8948 \<3\>: Lane 3.
8949 \<2\>: Lane 2.
8950 \<1\>: Lane 1.
8951 \<0\>: Lane 0. */
8952 uint64_t eiests : 4; /**< [ 7: 4](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
8953 asserted), indicates that an electrical idle exit condition (EIE) was detected. For higher
8954 data rates, the received data needs to have sufficient low frequency content (for example,
8955 idle symbols) for data transitions to be detected and for [EIESTS] to stay set
8956 accordingly.
8957 Under most conditions, [EIESTS]
8958 will stay asserted until GSER()_RX_EIE_DETEN[EIEDE] is deasserted.
8959 \<7\>: Lane 3.
8960 \<6\>: Lane 2.
8961 \<5\>: Lane 1.
8962 \<4\>: Lane 0. */
8963 uint64_t cdrlock : 4; /**< [ 11: 8](RO/H) After an electrical idle exit condition (EIE) has been detected, the CDR needs 10000 UI to
8964 lock. During this time, there may be RX bit errors. These bits will set when the CDR is
8965 guaranteed to be locked. Note that link training can't start until the lane CDRLOCK is
8966 set. Software can use CDRLOCK to determine when to expect error free RX data.
8967 \<11\>: Lane 3.
8968 \<10\>: Lane 2.
8969 \<9\>: Lane 1.
8970 \<8\>: Lane 0. */
8971 uint64_t reserved_12_63 : 52;
8972 #endif /* Word 0 - End */
8973 } cn88xx;
8974 struct bdk_gserx_rx_eie_detsts_cn83xx
8975 {
8976 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8977 uint64_t reserved_12_63 : 52;
8978 uint64_t cdrlock : 4; /**< [ 11: 8](RO/H) After an electrical idle exit condition (EIE) has been detected, the CDR needs 10000 UI to
8979 lock. During this time, there may be RX bit errors. These bits will set when the CDR is
8980 guaranteed to be locked. Note that link training can't start until the lane CDRLOCK is
8981 set. Software can use CDRLOCK to determine when to expect error free RX data.
8982 \<11\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
8983 \<10\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
8984 \<9\>: Lane 1.
8985 \<8\>: Lane 0. */
8986 uint64_t eiests : 4; /**< [ 7: 4](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
8987 asserted), indicates that an electrical idle exit condition (EIE) was detected. For higher
8988 data rates, the received data needs to have sufficient low frequency content (for example,
8989 idle symbols) for data transitions to be detected and for [EIESTS] to stay set
8990 accordingly.
8991 Under most conditions, [EIESTS]
8992 will stay asserted until GSER()_RX_EIE_DETEN[EIEDE] is deasserted.
8993 \<7\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
8994 \<6\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
8995 \<5\>: Lane 1.
8996 \<4\>: Lane 0. */
8997 uint64_t eieltch : 4; /**< [ 3: 0](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
8998 asserted), indicates that an electrical idle exit condition (EIE) was detected. Once an
8999 EIE condition has been detected, the per-lane [EIELTCH] will stay set until
9000 GSER()_RX_EIE_DETEN[EIEDE] is deasserted. Note that there may be RX bit errors until
9001 CDRLOCK
9002 is set.
9003 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
9004 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
9005 \<1\>: Lane 1.
9006 \<0\>: Lane 0. */
9007 #else /* Word 0 - Little Endian */
9008 uint64_t eieltch : 4; /**< [ 3: 0](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
9009 asserted), indicates that an electrical idle exit condition (EIE) was detected. Once an
9010 EIE condition has been detected, the per-lane [EIELTCH] will stay set until
9011 GSER()_RX_EIE_DETEN[EIEDE] is deasserted. Note that there may be RX bit errors until
9012 CDRLOCK
9013 is set.
9014 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
9015 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
9016 \<1\>: Lane 1.
9017 \<0\>: Lane 0. */
9018 uint64_t eiests : 4; /**< [ 7: 4](RO/H) When electrical idle exit detection is enabled (GSER()_RX_EIE_DETEN[EIEDE] is
9019 asserted), indicates that an electrical idle exit condition (EIE) was detected. For higher
9020 data rates, the received data needs to have sufficient low frequency content (for example,
9021 idle symbols) for data transitions to be detected and for [EIESTS] to stay set
9022 accordingly.
9023 Under most conditions, [EIESTS]
9024 will stay asserted until GSER()_RX_EIE_DETEN[EIEDE] is deasserted.
9025 \<7\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
9026 \<6\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
9027 \<5\>: Lane 1.
9028 \<4\>: Lane 0. */
9029 uint64_t cdrlock : 4; /**< [ 11: 8](RO/H) After an electrical idle exit condition (EIE) has been detected, the CDR needs 10000 UI to
9030 lock. During this time, there may be RX bit errors. These bits will set when the CDR is
9031 guaranteed to be locked. Note that link training can't start until the lane CDRLOCK is
9032 set. Software can use CDRLOCK to determine when to expect error free RX data.
9033 \<11\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
9034 \<10\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
9035 \<9\>: Lane 1.
9036 \<8\>: Lane 0. */
9037 uint64_t reserved_12_63 : 52;
9038 #endif /* Word 0 - End */
9039 } cn83xx;
9040 };
9041 typedef union bdk_gserx_rx_eie_detsts bdk_gserx_rx_eie_detsts_t;
9042
9043 static inline uint64_t BDK_GSERX_RX_EIE_DETSTS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RX_EIE_DETSTS(unsigned long a)9044 static inline uint64_t BDK_GSERX_RX_EIE_DETSTS(unsigned long a)
9045 {
9046 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
9047 return 0x87e090000150ll + 0x1000000ll * ((a) & 0x3);
9048 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
9049 return 0x87e090000150ll + 0x1000000ll * ((a) & 0x7);
9050 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
9051 return 0x87e090000150ll + 0x1000000ll * ((a) & 0xf);
9052 __bdk_csr_fatal("GSERX_RX_EIE_DETSTS", 1, a, 0, 0, 0);
9053 }
9054
9055 #define typedef_BDK_GSERX_RX_EIE_DETSTS(a) bdk_gserx_rx_eie_detsts_t
9056 #define bustype_BDK_GSERX_RX_EIE_DETSTS(a) BDK_CSR_TYPE_RSL
9057 #define basename_BDK_GSERX_RX_EIE_DETSTS(a) "GSERX_RX_EIE_DETSTS"
9058 #define device_bar_BDK_GSERX_RX_EIE_DETSTS(a) 0x0 /* PF_BAR0 */
9059 #define busnum_BDK_GSERX_RX_EIE_DETSTS(a) (a)
9060 #define arguments_BDK_GSERX_RX_EIE_DETSTS(a) (a),-1,-1,-1
9061
9062 /**
9063 * Register (RSL) gser#_rx_eie_filter
9064 *
9065 * GSER RX Electrical Idle Detect Filter Settings Register
9066 */
9067 union bdk_gserx_rx_eie_filter
9068 {
9069 uint64_t u;
9070 struct bdk_gserx_rx_eie_filter_s
9071 {
9072 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9073 uint64_t reserved_16_63 : 48;
9074 uint64_t eii_filt : 16; /**< [ 15: 0](R/W) The GSER uses electrical idle inference to determine when a RX lane has reentered
9075 electrical idle (EI). The PHY electrical idle exit detection supports a minimum pulse
9076 width of 400 ps, therefore configurations that run faster than 2.5 G can indicate EI when
9077 the serial lines are still driven. For rates faster than 2.5 G, it takes 16 K * 8 UI of
9078 consecutive deasserted GSER()_RX_EIE_DETSTS[EIESTS] for the GSER to infer EI. In the
9079 event of electrical idle inference, the following happens:
9080 * GSER()_RX_EIE_DETSTS[CDRLOCK]\<lane\> is zeroed.
9081 * GSER()_RX_EIE_DETSTS[EIELTCH]\<lane\> is zeroed.
9082 * GSER()_RX_EIE_DETSTS[EIESTS]\<lane\> is zeroed.
9083 * GSER()_RX_COAST[COAST]\<lane\> is asserted to prevent the CDR from trying to lock on
9084 the incoming data stream.
9085 * GSER()_RX_EIE_DETEN[EIEDE]\<lane\> deasserts for a short period of time, and then is
9086 asserted to begin looking for the Electrical idle Exit condition.
9087
9088 Writing this register to a nonzero value causes the electrical idle inference to use the
9089 [EII_FILT] count instead of the default settings. Each [EII_FILT] count represents 20 ns
9090 of
9091 incremental EI inference time.
9092
9093 It is not expected that software will need to use the Electrical Idle Inference logic. */
9094 #else /* Word 0 - Little Endian */
9095 uint64_t eii_filt : 16; /**< [ 15: 0](R/W) The GSER uses electrical idle inference to determine when a RX lane has reentered
9096 electrical idle (EI). The PHY electrical idle exit detection supports a minimum pulse
9097 width of 400 ps, therefore configurations that run faster than 2.5 G can indicate EI when
9098 the serial lines are still driven. For rates faster than 2.5 G, it takes 16 K * 8 UI of
9099 consecutive deasserted GSER()_RX_EIE_DETSTS[EIESTS] for the GSER to infer EI. In the
9100 event of electrical idle inference, the following happens:
9101 * GSER()_RX_EIE_DETSTS[CDRLOCK]\<lane\> is zeroed.
9102 * GSER()_RX_EIE_DETSTS[EIELTCH]\<lane\> is zeroed.
9103 * GSER()_RX_EIE_DETSTS[EIESTS]\<lane\> is zeroed.
9104 * GSER()_RX_COAST[COAST]\<lane\> is asserted to prevent the CDR from trying to lock on
9105 the incoming data stream.
9106 * GSER()_RX_EIE_DETEN[EIEDE]\<lane\> deasserts for a short period of time, and then is
9107 asserted to begin looking for the Electrical idle Exit condition.
9108
9109 Writing this register to a nonzero value causes the electrical idle inference to use the
9110 [EII_FILT] count instead of the default settings. Each [EII_FILT] count represents 20 ns
9111 of
9112 incremental EI inference time.
9113
9114 It is not expected that software will need to use the Electrical Idle Inference logic. */
9115 uint64_t reserved_16_63 : 48;
9116 #endif /* Word 0 - End */
9117 } s;
9118 /* struct bdk_gserx_rx_eie_filter_s cn; */
9119 };
9120 typedef union bdk_gserx_rx_eie_filter bdk_gserx_rx_eie_filter_t;
9121
9122 static inline uint64_t BDK_GSERX_RX_EIE_FILTER(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RX_EIE_FILTER(unsigned long a)9123 static inline uint64_t BDK_GSERX_RX_EIE_FILTER(unsigned long a)
9124 {
9125 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
9126 return 0x87e090000158ll + 0x1000000ll * ((a) & 0x3);
9127 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
9128 return 0x87e090000158ll + 0x1000000ll * ((a) & 0x7);
9129 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
9130 return 0x87e090000158ll + 0x1000000ll * ((a) & 0xf);
9131 __bdk_csr_fatal("GSERX_RX_EIE_FILTER", 1, a, 0, 0, 0);
9132 }
9133
9134 #define typedef_BDK_GSERX_RX_EIE_FILTER(a) bdk_gserx_rx_eie_filter_t
9135 #define bustype_BDK_GSERX_RX_EIE_FILTER(a) BDK_CSR_TYPE_RSL
9136 #define basename_BDK_GSERX_RX_EIE_FILTER(a) "GSERX_RX_EIE_FILTER"
9137 #define device_bar_BDK_GSERX_RX_EIE_FILTER(a) 0x0 /* PF_BAR0 */
9138 #define busnum_BDK_GSERX_RX_EIE_FILTER(a) (a)
9139 #define arguments_BDK_GSERX_RX_EIE_FILTER(a) (a),-1,-1,-1
9140
9141 /**
9142 * Register (RSL) gser#_rx_polarity
9143 *
9144 * GSER RX Polarity Register
9145 * These registers are reset by hardware only during chip cold reset. The values of the CSR
9146 * fields in these registers do not change during chip warm or soft resets.
9147 */
9148 union bdk_gserx_rx_polarity
9149 {
9150 uint64_t u;
9151 struct bdk_gserx_rx_polarity_s
9152 {
9153 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9154 uint64_t reserved_4_63 : 60;
9155 uint64_t rx_inv : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, control signal to invert
9156 the polarity of received data. When asserted, the polarity of the received data is
9157 inverted.
9158 \<3\>: Lane 3. Reserved.
9159 \<2\>: Lane 2. Reserved.
9160 \<1\>: Lane 1.
9161 \<0\>: Lane 0. */
9162 #else /* Word 0 - Little Endian */
9163 uint64_t rx_inv : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, control signal to invert
9164 the polarity of received data. When asserted, the polarity of the received data is
9165 inverted.
9166 \<3\>: Lane 3. Reserved.
9167 \<2\>: Lane 2. Reserved.
9168 \<1\>: Lane 1.
9169 \<0\>: Lane 0. */
9170 uint64_t reserved_4_63 : 60;
9171 #endif /* Word 0 - End */
9172 } s;
9173 /* struct bdk_gserx_rx_polarity_s cn81xx; */
9174 struct bdk_gserx_rx_polarity_cn88xx
9175 {
9176 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9177 uint64_t reserved_4_63 : 60;
9178 uint64_t rx_inv : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode (including all CCPI links), control signal to invert
9179 the polarity of received data. When asserted, the polarity of the received data is
9180 inverted.
9181 \<3\>: Lane 3.
9182 \<2\>: Lane 2.
9183 \<1\>: Lane 1.
9184 \<0\>: Lane 0. */
9185 #else /* Word 0 - Little Endian */
9186 uint64_t rx_inv : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode (including all CCPI links), control signal to invert
9187 the polarity of received data. When asserted, the polarity of the received data is
9188 inverted.
9189 \<3\>: Lane 3.
9190 \<2\>: Lane 2.
9191 \<1\>: Lane 1.
9192 \<0\>: Lane 0. */
9193 uint64_t reserved_4_63 : 60;
9194 #endif /* Word 0 - End */
9195 } cn88xx;
9196 struct bdk_gserx_rx_polarity_cn83xx
9197 {
9198 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9199 uint64_t reserved_4_63 : 60;
9200 uint64_t rx_inv : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, control signal to invert
9201 the polarity of received data. When asserted, the polarity of the received data is
9202 inverted.
9203 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
9204 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
9205 \<1\>: Lane 1.
9206 \<0\>: Lane 0. */
9207 #else /* Word 0 - Little Endian */
9208 uint64_t rx_inv : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, control signal to invert
9209 the polarity of received data. When asserted, the polarity of the received data is
9210 inverted.
9211 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
9212 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
9213 \<1\>: Lane 1.
9214 \<0\>: Lane 0. */
9215 uint64_t reserved_4_63 : 60;
9216 #endif /* Word 0 - End */
9217 } cn83xx;
9218 };
9219 typedef union bdk_gserx_rx_polarity bdk_gserx_rx_polarity_t;
9220
9221 static inline uint64_t BDK_GSERX_RX_POLARITY(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RX_POLARITY(unsigned long a)9222 static inline uint64_t BDK_GSERX_RX_POLARITY(unsigned long a)
9223 {
9224 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
9225 return 0x87e090000160ll + 0x1000000ll * ((a) & 0x3);
9226 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
9227 return 0x87e090000160ll + 0x1000000ll * ((a) & 0x7);
9228 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
9229 return 0x87e090000160ll + 0x1000000ll * ((a) & 0xf);
9230 __bdk_csr_fatal("GSERX_RX_POLARITY", 1, a, 0, 0, 0);
9231 }
9232
9233 #define typedef_BDK_GSERX_RX_POLARITY(a) bdk_gserx_rx_polarity_t
9234 #define bustype_BDK_GSERX_RX_POLARITY(a) BDK_CSR_TYPE_RSL
9235 #define basename_BDK_GSERX_RX_POLARITY(a) "GSERX_RX_POLARITY"
9236 #define device_bar_BDK_GSERX_RX_POLARITY(a) 0x0 /* PF_BAR0 */
9237 #define busnum_BDK_GSERX_RX_POLARITY(a) (a)
9238 #define arguments_BDK_GSERX_RX_POLARITY(a) (a),-1,-1,-1
9239
9240 /**
9241 * Register (RSL) gser#_rx_pwr_ctrl_p1
9242 *
9243 * GSER RX Power Control P1 Register
9244 * These registers are for diagnostic use only.
9245 * These registers are reset by hardware only during chip cold reset.
9246 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
9247 */
9248 union bdk_gserx_rx_pwr_ctrl_p1
9249 {
9250 uint64_t u;
9251 struct bdk_gserx_rx_pwr_ctrl_p1_s
9252 {
9253 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9254 uint64_t reserved_14_63 : 50;
9255 uint64_t p1_rx_resetn : 1; /**< [ 13: 13](R/W) Place the receiver in reset (active low). */
9256 uint64_t pq_rx_allow_pll_pd : 1; /**< [ 12: 12](R/W) When asserted, permit PLL powerdown (PLL is powered
9257 down if all other factors permit). */
9258 uint64_t pq_rx_pcs_reset : 1; /**< [ 11: 11](R/W) When asserted, the RX power state machine puts the raw PCS RX logic
9259 in reset state to save power. */
9260 uint64_t p1_rx_agc_en : 1; /**< [ 10: 10](R/W) AGC enable. */
9261 uint64_t p1_rx_dfe_en : 1; /**< [ 9: 9](R/W) DFE enable. */
9262 uint64_t p1_rx_cdr_en : 1; /**< [ 8: 8](R/W) CDR enable. */
9263 uint64_t p1_rx_cdr_coast : 1; /**< [ 7: 7](R/W) CDR coast; freezes the frequency of the CDR. */
9264 uint64_t p1_rx_cdr_clr : 1; /**< [ 6: 6](R/W) CDR clear; clears the frequency of the CDR. */
9265 uint64_t p1_rx_subblk_pd : 5; /**< [ 5: 1](R/W) RX sub-block powerdown controls to RX:
9266 \<4\> = CTLE.
9267 \<3\> = Reserved.
9268 \<2\> = Lane DLL.
9269 \<1\> = DFE/samplers.
9270 \<0\> = Termination. */
9271 uint64_t p1_rx_chpd : 1; /**< [ 0: 0](R/W) RX lane powerdown. */
9272 #else /* Word 0 - Little Endian */
9273 uint64_t p1_rx_chpd : 1; /**< [ 0: 0](R/W) RX lane powerdown. */
9274 uint64_t p1_rx_subblk_pd : 5; /**< [ 5: 1](R/W) RX sub-block powerdown controls to RX:
9275 \<4\> = CTLE.
9276 \<3\> = Reserved.
9277 \<2\> = Lane DLL.
9278 \<1\> = DFE/samplers.
9279 \<0\> = Termination. */
9280 uint64_t p1_rx_cdr_clr : 1; /**< [ 6: 6](R/W) CDR clear; clears the frequency of the CDR. */
9281 uint64_t p1_rx_cdr_coast : 1; /**< [ 7: 7](R/W) CDR coast; freezes the frequency of the CDR. */
9282 uint64_t p1_rx_cdr_en : 1; /**< [ 8: 8](R/W) CDR enable. */
9283 uint64_t p1_rx_dfe_en : 1; /**< [ 9: 9](R/W) DFE enable. */
9284 uint64_t p1_rx_agc_en : 1; /**< [ 10: 10](R/W) AGC enable. */
9285 uint64_t pq_rx_pcs_reset : 1; /**< [ 11: 11](R/W) When asserted, the RX power state machine puts the raw PCS RX logic
9286 in reset state to save power. */
9287 uint64_t pq_rx_allow_pll_pd : 1; /**< [ 12: 12](R/W) When asserted, permit PLL powerdown (PLL is powered
9288 down if all other factors permit). */
9289 uint64_t p1_rx_resetn : 1; /**< [ 13: 13](R/W) Place the receiver in reset (active low). */
9290 uint64_t reserved_14_63 : 50;
9291 #endif /* Word 0 - End */
9292 } s;
9293 /* struct bdk_gserx_rx_pwr_ctrl_p1_s cn; */
9294 };
9295 typedef union bdk_gserx_rx_pwr_ctrl_p1 bdk_gserx_rx_pwr_ctrl_p1_t;
9296
9297 static inline uint64_t BDK_GSERX_RX_PWR_CTRL_P1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RX_PWR_CTRL_P1(unsigned long a)9298 static inline uint64_t BDK_GSERX_RX_PWR_CTRL_P1(unsigned long a)
9299 {
9300 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
9301 return 0x87e0904600b0ll + 0x1000000ll * ((a) & 0x3);
9302 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
9303 return 0x87e0904600b0ll + 0x1000000ll * ((a) & 0x7);
9304 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
9305 return 0x87e0904600b0ll + 0x1000000ll * ((a) & 0xf);
9306 __bdk_csr_fatal("GSERX_RX_PWR_CTRL_P1", 1, a, 0, 0, 0);
9307 }
9308
9309 #define typedef_BDK_GSERX_RX_PWR_CTRL_P1(a) bdk_gserx_rx_pwr_ctrl_p1_t
9310 #define bustype_BDK_GSERX_RX_PWR_CTRL_P1(a) BDK_CSR_TYPE_RSL
9311 #define basename_BDK_GSERX_RX_PWR_CTRL_P1(a) "GSERX_RX_PWR_CTRL_P1"
9312 #define device_bar_BDK_GSERX_RX_PWR_CTRL_P1(a) 0x0 /* PF_BAR0 */
9313 #define busnum_BDK_GSERX_RX_PWR_CTRL_P1(a) (a)
9314 #define arguments_BDK_GSERX_RX_PWR_CTRL_P1(a) (a),-1,-1,-1
9315
9316 /**
9317 * Register (RSL) gser#_rx_pwr_ctrl_p2
9318 *
9319 * GSER RX Power Controls in Power State P2 Register
9320 * These registers are for diagnostic use only.
9321 * These registers are reset by hardware only during chip cold reset.
9322 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
9323 */
9324 union bdk_gserx_rx_pwr_ctrl_p2
9325 {
9326 uint64_t u;
9327 struct bdk_gserx_rx_pwr_ctrl_p2_s
9328 {
9329 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9330 uint64_t reserved_14_63 : 50;
9331 uint64_t p2_rx_resetn : 1; /**< [ 13: 13](R/W) Place the receiver in reset (active low). */
9332 uint64_t p2_rx_allow_pll_pd : 1; /**< [ 12: 12](R/W) When asserted, it permits PLL powerdown (PLL is
9333 powered down if all other factors permit). */
9334 uint64_t p2_rx_pcs_reset : 1; /**< [ 11: 11](R/W) When asserted, the RX Power state machine puts the Raw PCS
9335 RX logic in reset state to save power. */
9336 uint64_t p2_rx_agc_en : 1; /**< [ 10: 10](R/W) AGC enable. */
9337 uint64_t p2_rx_dfe_en : 1; /**< [ 9: 9](R/W) DFE enable. */
9338 uint64_t p2_rx_cdr_en : 1; /**< [ 8: 8](R/W) CDR enable. */
9339 uint64_t p2_rx_cdr_coast : 1; /**< [ 7: 7](R/W) CDR coast; freezes the frequency of the CDR. */
9340 uint64_t p2_rx_cdr_clr : 1; /**< [ 6: 6](R/W) CDR clear; clears the frequency register in the CDR. */
9341 uint64_t p2_rx_subblk_pd : 5; /**< [ 5: 1](R/W) RX sub-block powerdown to RX:
9342 \<4\> = CTLE.
9343 \<3\> = Reserved.
9344 \<2\> = Lane DLL.
9345 \<1\> = DFE/Samplers.
9346 \<0\> = Termination.
9347
9348 Software needs to clear the termination bit in SATA mode
9349 (i.e. when GSER()_CFG[SATA] is set). */
9350 uint64_t p2_rx_chpd : 1; /**< [ 0: 0](R/W) RX lane power down. */
9351 #else /* Word 0 - Little Endian */
9352 uint64_t p2_rx_chpd : 1; /**< [ 0: 0](R/W) RX lane power down. */
9353 uint64_t p2_rx_subblk_pd : 5; /**< [ 5: 1](R/W) RX sub-block powerdown to RX:
9354 \<4\> = CTLE.
9355 \<3\> = Reserved.
9356 \<2\> = Lane DLL.
9357 \<1\> = DFE/Samplers.
9358 \<0\> = Termination.
9359
9360 Software needs to clear the termination bit in SATA mode
9361 (i.e. when GSER()_CFG[SATA] is set). */
9362 uint64_t p2_rx_cdr_clr : 1; /**< [ 6: 6](R/W) CDR clear; clears the frequency register in the CDR. */
9363 uint64_t p2_rx_cdr_coast : 1; /**< [ 7: 7](R/W) CDR coast; freezes the frequency of the CDR. */
9364 uint64_t p2_rx_cdr_en : 1; /**< [ 8: 8](R/W) CDR enable. */
9365 uint64_t p2_rx_dfe_en : 1; /**< [ 9: 9](R/W) DFE enable. */
9366 uint64_t p2_rx_agc_en : 1; /**< [ 10: 10](R/W) AGC enable. */
9367 uint64_t p2_rx_pcs_reset : 1; /**< [ 11: 11](R/W) When asserted, the RX Power state machine puts the Raw PCS
9368 RX logic in reset state to save power. */
9369 uint64_t p2_rx_allow_pll_pd : 1; /**< [ 12: 12](R/W) When asserted, it permits PLL powerdown (PLL is
9370 powered down if all other factors permit). */
9371 uint64_t p2_rx_resetn : 1; /**< [ 13: 13](R/W) Place the receiver in reset (active low). */
9372 uint64_t reserved_14_63 : 50;
9373 #endif /* Word 0 - End */
9374 } s;
9375 /* struct bdk_gserx_rx_pwr_ctrl_p2_s cn; */
9376 };
9377 typedef union bdk_gserx_rx_pwr_ctrl_p2 bdk_gserx_rx_pwr_ctrl_p2_t;
9378
9379 static inline uint64_t BDK_GSERX_RX_PWR_CTRL_P2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RX_PWR_CTRL_P2(unsigned long a)9380 static inline uint64_t BDK_GSERX_RX_PWR_CTRL_P2(unsigned long a)
9381 {
9382 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
9383 return 0x87e0904600b8ll + 0x1000000ll * ((a) & 0x3);
9384 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
9385 return 0x87e0904600b8ll + 0x1000000ll * ((a) & 0x7);
9386 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
9387 return 0x87e0904600b8ll + 0x1000000ll * ((a) & 0xf);
9388 __bdk_csr_fatal("GSERX_RX_PWR_CTRL_P2", 1, a, 0, 0, 0);
9389 }
9390
9391 #define typedef_BDK_GSERX_RX_PWR_CTRL_P2(a) bdk_gserx_rx_pwr_ctrl_p2_t
9392 #define bustype_BDK_GSERX_RX_PWR_CTRL_P2(a) BDK_CSR_TYPE_RSL
9393 #define basename_BDK_GSERX_RX_PWR_CTRL_P2(a) "GSERX_RX_PWR_CTRL_P2"
9394 #define device_bar_BDK_GSERX_RX_PWR_CTRL_P2(a) 0x0 /* PF_BAR0 */
9395 #define busnum_BDK_GSERX_RX_PWR_CTRL_P2(a) (a)
9396 #define arguments_BDK_GSERX_RX_PWR_CTRL_P2(a) (a),-1,-1,-1
9397
9398 /**
9399 * Register (RSL) gser#_rx_txdir_ctrl_0
9400 *
9401 * GSER Far-end TX Direction Control 0 Register
9402 * These registers are for diagnostic use only.
9403 * These registers are reset by hardware only during chip cold reset.
9404 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
9405 */
9406 union bdk_gserx_rx_txdir_ctrl_0
9407 {
9408 uint64_t u;
9409 struct bdk_gserx_rx_txdir_ctrl_0_s
9410 {
9411 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9412 uint64_t reserved_13_63 : 51;
9413 uint64_t rx_boost_hi_thrs : 4; /**< [ 12: 9](R/W/H) The high threshold for RX boost.
9414 The far-end TX POST direction output, pcs_mac_rx_txpost_dir, is set to
9415 increment if the local RX boost value from the VMA (after RX-EQ) is
9416 higher than this value, and the local RX tap1 value is higher than its
9417 high threshold GSER()_RX_TXDIR_CTRL_1[RX_TAP1_HI_THRS].
9418 Note, that if GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9419 the direction is decrement. */
9420 uint64_t rx_boost_lo_thrs : 4; /**< [ 8: 5](R/W/H) The low threshold for RX boost.
9421 The far-end TX POST direction output, pcs_mac_rx_txpost_dir, is set to
9422 decrement if the local RX boost value from the VMA (after RX-EQ) is
9423 lower than this value, and the local RX tap1 value is lower than its
9424 low threshold GSER()_RX_TXDIR_CTRL_1[RX_TAP1_LO_THRS].
9425 Note, that if GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9426 the direction is increment. */
9427 uint64_t rx_boost_hi_val : 5; /**< [ 4: 0](R/W) The far-end TX POST direction output, pcs_mac_rx_txpost_dir,
9428 is set to increment if the local RX boost value from the VMA (after RX-EQ)
9429 equals RX_BOOST_HI_VAL.
9430 Note, that if GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9431 the direction is decrement.
9432 To disable the check against RX_BOOST_HI_VAL, assert RX_BOOST_HI_VAL[4]. */
9433 #else /* Word 0 - Little Endian */
9434 uint64_t rx_boost_hi_val : 5; /**< [ 4: 0](R/W) The far-end TX POST direction output, pcs_mac_rx_txpost_dir,
9435 is set to increment if the local RX boost value from the VMA (after RX-EQ)
9436 equals RX_BOOST_HI_VAL.
9437 Note, that if GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9438 the direction is decrement.
9439 To disable the check against RX_BOOST_HI_VAL, assert RX_BOOST_HI_VAL[4]. */
9440 uint64_t rx_boost_lo_thrs : 4; /**< [ 8: 5](R/W/H) The low threshold for RX boost.
9441 The far-end TX POST direction output, pcs_mac_rx_txpost_dir, is set to
9442 decrement if the local RX boost value from the VMA (after RX-EQ) is
9443 lower than this value, and the local RX tap1 value is lower than its
9444 low threshold GSER()_RX_TXDIR_CTRL_1[RX_TAP1_LO_THRS].
9445 Note, that if GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9446 the direction is increment. */
9447 uint64_t rx_boost_hi_thrs : 4; /**< [ 12: 9](R/W/H) The high threshold for RX boost.
9448 The far-end TX POST direction output, pcs_mac_rx_txpost_dir, is set to
9449 increment if the local RX boost value from the VMA (after RX-EQ) is
9450 higher than this value, and the local RX tap1 value is higher than its
9451 high threshold GSER()_RX_TXDIR_CTRL_1[RX_TAP1_HI_THRS].
9452 Note, that if GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9453 the direction is decrement. */
9454 uint64_t reserved_13_63 : 51;
9455 #endif /* Word 0 - End */
9456 } s;
9457 /* struct bdk_gserx_rx_txdir_ctrl_0_s cn; */
9458 };
9459 typedef union bdk_gserx_rx_txdir_ctrl_0 bdk_gserx_rx_txdir_ctrl_0_t;
9460
9461 static inline uint64_t BDK_GSERX_RX_TXDIR_CTRL_0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RX_TXDIR_CTRL_0(unsigned long a)9462 static inline uint64_t BDK_GSERX_RX_TXDIR_CTRL_0(unsigned long a)
9463 {
9464 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
9465 return 0x87e0904600e8ll + 0x1000000ll * ((a) & 0x3);
9466 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
9467 return 0x87e0904600e8ll + 0x1000000ll * ((a) & 0x7);
9468 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
9469 return 0x87e0904600e8ll + 0x1000000ll * ((a) & 0xf);
9470 __bdk_csr_fatal("GSERX_RX_TXDIR_CTRL_0", 1, a, 0, 0, 0);
9471 }
9472
9473 #define typedef_BDK_GSERX_RX_TXDIR_CTRL_0(a) bdk_gserx_rx_txdir_ctrl_0_t
9474 #define bustype_BDK_GSERX_RX_TXDIR_CTRL_0(a) BDK_CSR_TYPE_RSL
9475 #define basename_BDK_GSERX_RX_TXDIR_CTRL_0(a) "GSERX_RX_TXDIR_CTRL_0"
9476 #define device_bar_BDK_GSERX_RX_TXDIR_CTRL_0(a) 0x0 /* PF_BAR0 */
9477 #define busnum_BDK_GSERX_RX_TXDIR_CTRL_0(a) (a)
9478 #define arguments_BDK_GSERX_RX_TXDIR_CTRL_0(a) (a),-1,-1,-1
9479
9480 /**
9481 * Register (RSL) gser#_rx_txdir_ctrl_1
9482 *
9483 * GSER Far-end TX Direction Control 1 Register
9484 * These registers are for diagnostic use only.
9485 * These registers are reset by hardware only during chip cold reset.
9486 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
9487 */
9488 union bdk_gserx_rx_txdir_ctrl_1
9489 {
9490 uint64_t u;
9491 struct bdk_gserx_rx_txdir_ctrl_1_s
9492 {
9493 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9494 uint64_t reserved_12_63 : 52;
9495 uint64_t rx_precorr_chg_dir : 1; /**< [ 11: 11](R/W/H) When asserted, the default direction output for the far-end TX Pre is reversed. */
9496 uint64_t rx_tap1_chg_dir : 1; /**< [ 10: 10](R/W/H) When asserted, the default direction output for the far-end TX Post is reversed. */
9497 uint64_t rx_tap1_hi_thrs : 5; /**< [ 9: 5](R/W) The high threshold for the local RX Tap1 count.
9498 The far-end TX POST direction output, pcs_mac_rx_txpost_dir,
9499 is set to increment if the local RX tap1 value from the VMA (after RX-EQ)
9500 is higher than this value, and the local RX boost value is higher than
9501 its high threshold GSER()_RX_TXDIR_CTRL_0[RX_BOOST_HI_THRS].
9502 Note that if GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9503 the direction is decrement. */
9504 uint64_t rx_tap1_lo_thrs : 5; /**< [ 4: 0](R/W) The low threshold for the local RX Tap1 count.
9505 The far-end TX POST direction output, pcs_mac_rx_txpost_dir,
9506 is set to decrement if the local RX tap1 value from the VMA (after RX-EQ)
9507 is lower than this value, and the local RX boost value is lower than
9508 its low threshold GSER()_RX_TXDIR_CTRL_0[RX_BOOST_LO_THRS].
9509 Note that if GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9510 the direction is increment. */
9511 #else /* Word 0 - Little Endian */
9512 uint64_t rx_tap1_lo_thrs : 5; /**< [ 4: 0](R/W) The low threshold for the local RX Tap1 count.
9513 The far-end TX POST direction output, pcs_mac_rx_txpost_dir,
9514 is set to decrement if the local RX tap1 value from the VMA (after RX-EQ)
9515 is lower than this value, and the local RX boost value is lower than
9516 its low threshold GSER()_RX_TXDIR_CTRL_0[RX_BOOST_LO_THRS].
9517 Note that if GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9518 the direction is increment. */
9519 uint64_t rx_tap1_hi_thrs : 5; /**< [ 9: 5](R/W) The high threshold for the local RX Tap1 count.
9520 The far-end TX POST direction output, pcs_mac_rx_txpost_dir,
9521 is set to increment if the local RX tap1 value from the VMA (after RX-EQ)
9522 is higher than this value, and the local RX boost value is higher than
9523 its high threshold GSER()_RX_TXDIR_CTRL_0[RX_BOOST_HI_THRS].
9524 Note that if GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9525 the direction is decrement. */
9526 uint64_t rx_tap1_chg_dir : 1; /**< [ 10: 10](R/W/H) When asserted, the default direction output for the far-end TX Post is reversed. */
9527 uint64_t rx_precorr_chg_dir : 1; /**< [ 11: 11](R/W/H) When asserted, the default direction output for the far-end TX Pre is reversed. */
9528 uint64_t reserved_12_63 : 52;
9529 #endif /* Word 0 - End */
9530 } s;
9531 /* struct bdk_gserx_rx_txdir_ctrl_1_s cn81xx; */
9532 struct bdk_gserx_rx_txdir_ctrl_1_cn88xx
9533 {
9534 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9535 uint64_t reserved_12_63 : 52;
9536 uint64_t rx_precorr_chg_dir : 1; /**< [ 11: 11](R/W/H) When asserted, the default direction output for the far-end TX Pre is reversed. */
9537 uint64_t rx_tap1_chg_dir : 1; /**< [ 10: 10](R/W/H) When asserted, the default direction output for the far-end TX Post is reversed. */
9538 uint64_t rx_tap1_hi_thrs : 5; /**< [ 9: 5](R/W) The high threshold for the local RX Tap1 count.
9539 The far-end TX POST direction output, pcs_mac_rx_txpost_dir,
9540 is set to increment if the local RX tap1 value from the VMA (after RX-EQ)
9541 is higher than this value, and the local RX boost value is higher than
9542 its high threshold GSER()_RX_TXDIR_CTRL_0[RX_BOOST_HI_THRS].
9543 If GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9544 the direction is decrement. */
9545 uint64_t rx_tap1_lo_thrs : 5; /**< [ 4: 0](R/W) The low threshold for the local RX Tap1 count.
9546 The far-end TX POST direction output, pcs_mac_rx_txpost_dir,
9547 is set to decrement if the local RX tap1 value from the VMA (after RX-EQ)
9548 is lower than this value, and the local RX boost value is lower than
9549 its low threshold GSER()_RX_TXDIR_CTRL_0[RX_BOOST_LO_THRS].
9550 If GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9551 the direction is increment. */
9552 #else /* Word 0 - Little Endian */
9553 uint64_t rx_tap1_lo_thrs : 5; /**< [ 4: 0](R/W) The low threshold for the local RX Tap1 count.
9554 The far-end TX POST direction output, pcs_mac_rx_txpost_dir,
9555 is set to decrement if the local RX tap1 value from the VMA (after RX-EQ)
9556 is lower than this value, and the local RX boost value is lower than
9557 its low threshold GSER()_RX_TXDIR_CTRL_0[RX_BOOST_LO_THRS].
9558 If GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9559 the direction is increment. */
9560 uint64_t rx_tap1_hi_thrs : 5; /**< [ 9: 5](R/W) The high threshold for the local RX Tap1 count.
9561 The far-end TX POST direction output, pcs_mac_rx_txpost_dir,
9562 is set to increment if the local RX tap1 value from the VMA (after RX-EQ)
9563 is higher than this value, and the local RX boost value is higher than
9564 its high threshold GSER()_RX_TXDIR_CTRL_0[RX_BOOST_HI_THRS].
9565 If GSER()_RX_TXDIR_CTRL_1[RX_TAP1_CHG_DIR]=1 then
9566 the direction is decrement. */
9567 uint64_t rx_tap1_chg_dir : 1; /**< [ 10: 10](R/W/H) When asserted, the default direction output for the far-end TX Post is reversed. */
9568 uint64_t rx_precorr_chg_dir : 1; /**< [ 11: 11](R/W/H) When asserted, the default direction output for the far-end TX Pre is reversed. */
9569 uint64_t reserved_12_63 : 52;
9570 #endif /* Word 0 - End */
9571 } cn88xx;
9572 /* struct bdk_gserx_rx_txdir_ctrl_1_s cn83xx; */
9573 };
9574 typedef union bdk_gserx_rx_txdir_ctrl_1 bdk_gserx_rx_txdir_ctrl_1_t;
9575
9576 static inline uint64_t BDK_GSERX_RX_TXDIR_CTRL_1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RX_TXDIR_CTRL_1(unsigned long a)9577 static inline uint64_t BDK_GSERX_RX_TXDIR_CTRL_1(unsigned long a)
9578 {
9579 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
9580 return 0x87e0904600f0ll + 0x1000000ll * ((a) & 0x3);
9581 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
9582 return 0x87e0904600f0ll + 0x1000000ll * ((a) & 0x7);
9583 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
9584 return 0x87e0904600f0ll + 0x1000000ll * ((a) & 0xf);
9585 __bdk_csr_fatal("GSERX_RX_TXDIR_CTRL_1", 1, a, 0, 0, 0);
9586 }
9587
9588 #define typedef_BDK_GSERX_RX_TXDIR_CTRL_1(a) bdk_gserx_rx_txdir_ctrl_1_t
9589 #define bustype_BDK_GSERX_RX_TXDIR_CTRL_1(a) BDK_CSR_TYPE_RSL
9590 #define basename_BDK_GSERX_RX_TXDIR_CTRL_1(a) "GSERX_RX_TXDIR_CTRL_1"
9591 #define device_bar_BDK_GSERX_RX_TXDIR_CTRL_1(a) 0x0 /* PF_BAR0 */
9592 #define busnum_BDK_GSERX_RX_TXDIR_CTRL_1(a) (a)
9593 #define arguments_BDK_GSERX_RX_TXDIR_CTRL_1(a) (a),-1,-1,-1
9594
9595 /**
9596 * Register (RSL) gser#_rx_txdir_ctrl_2
9597 *
9598 * GSER Far-end TX Direction Control 2 Register
9599 * These registers are for diagnostic use only.
9600 * These registers are reset by hardware only during chip cold reset.
9601 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
9602 */
9603 union bdk_gserx_rx_txdir_ctrl_2
9604 {
9605 uint64_t u;
9606 struct bdk_gserx_rx_txdir_ctrl_2_s
9607 {
9608 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9609 uint64_t reserved_16_63 : 48;
9610 uint64_t rx_precorr_hi_thrs : 8; /**< [ 15: 8](R/W/H) High threshold for RX precursor correlation count.
9611 The far-end TX PRE direction output, pcs_mac_rx_txpre_dir, is set to
9612 decrement if the local RX precursor correlation count from the VMA (after RX-EQ)
9613 is lower than this value.
9614 Note, that if GSER()_RX_TXDIR_CTRL_1[RX_PRECORR_CHG_DIR]=1 then
9615 the direction is increment. */
9616 uint64_t rx_precorr_lo_thrs : 8; /**< [ 7: 0](R/W/H) Low threshold for RX precursor correlation count.
9617 The far-end TX PRE direction output, pcs_mac_rx_txpre_dir, is set to
9618 increment if the local RX precursor correlation count from the VMA (after RX-EQ)
9619 is lower than this value.
9620 Note, that if GSER()_RX_TXDIR_CTRL_1[RX_PRECORR_CHG_DIR]=1 then
9621 the direction is decrement. */
9622 #else /* Word 0 - Little Endian */
9623 uint64_t rx_precorr_lo_thrs : 8; /**< [ 7: 0](R/W/H) Low threshold for RX precursor correlation count.
9624 The far-end TX PRE direction output, pcs_mac_rx_txpre_dir, is set to
9625 increment if the local RX precursor correlation count from the VMA (after RX-EQ)
9626 is lower than this value.
9627 Note, that if GSER()_RX_TXDIR_CTRL_1[RX_PRECORR_CHG_DIR]=1 then
9628 the direction is decrement. */
9629 uint64_t rx_precorr_hi_thrs : 8; /**< [ 15: 8](R/W/H) High threshold for RX precursor correlation count.
9630 The far-end TX PRE direction output, pcs_mac_rx_txpre_dir, is set to
9631 decrement if the local RX precursor correlation count from the VMA (after RX-EQ)
9632 is lower than this value.
9633 Note, that if GSER()_RX_TXDIR_CTRL_1[RX_PRECORR_CHG_DIR]=1 then
9634 the direction is increment. */
9635 uint64_t reserved_16_63 : 48;
9636 #endif /* Word 0 - End */
9637 } s;
9638 /* struct bdk_gserx_rx_txdir_ctrl_2_s cn; */
9639 };
9640 typedef union bdk_gserx_rx_txdir_ctrl_2 bdk_gserx_rx_txdir_ctrl_2_t;
9641
9642 static inline uint64_t BDK_GSERX_RX_TXDIR_CTRL_2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_RX_TXDIR_CTRL_2(unsigned long a)9643 static inline uint64_t BDK_GSERX_RX_TXDIR_CTRL_2(unsigned long a)
9644 {
9645 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
9646 return 0x87e0904600f8ll + 0x1000000ll * ((a) & 0x3);
9647 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
9648 return 0x87e0904600f8ll + 0x1000000ll * ((a) & 0x7);
9649 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
9650 return 0x87e0904600f8ll + 0x1000000ll * ((a) & 0xf);
9651 __bdk_csr_fatal("GSERX_RX_TXDIR_CTRL_2", 1, a, 0, 0, 0);
9652 }
9653
9654 #define typedef_BDK_GSERX_RX_TXDIR_CTRL_2(a) bdk_gserx_rx_txdir_ctrl_2_t
9655 #define bustype_BDK_GSERX_RX_TXDIR_CTRL_2(a) BDK_CSR_TYPE_RSL
9656 #define basename_BDK_GSERX_RX_TXDIR_CTRL_2(a) "GSERX_RX_TXDIR_CTRL_2"
9657 #define device_bar_BDK_GSERX_RX_TXDIR_CTRL_2(a) 0x0 /* PF_BAR0 */
9658 #define busnum_BDK_GSERX_RX_TXDIR_CTRL_2(a) (a)
9659 #define arguments_BDK_GSERX_RX_TXDIR_CTRL_2(a) (a),-1,-1,-1
9660
9661 /**
9662 * Register (RSL) gser#_sata_lane#_tx_amp#
9663 *
9664 * GSER SATA Lane Transmit Amplitude Gen Register
9665 * SATA lane TX launch amplitude at Gen 1, 2 and 3 speeds.
9666 * * AMP(0) is for Gen1.
9667 * * AMP(1) is for Gen2.
9668 * * AMP(2) is for Gen3.
9669 */
9670 union bdk_gserx_sata_lanex_tx_ampx
9671 {
9672 uint64_t u;
9673 struct bdk_gserx_sata_lanex_tx_ampx_s
9674 {
9675 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9676 uint64_t reserved_7_63 : 57;
9677 uint64_t tx_amp : 7; /**< [ 6: 0](R/W) This status value sets the TX driver launch amplitude in the
9678 case where the PHY is running at the Gen1, Gen2, and Gen3
9679 rates. Used for tuning at the board level for RX eye compliance. */
9680 #else /* Word 0 - Little Endian */
9681 uint64_t tx_amp : 7; /**< [ 6: 0](R/W) This status value sets the TX driver launch amplitude in the
9682 case where the PHY is running at the Gen1, Gen2, and Gen3
9683 rates. Used for tuning at the board level for RX eye compliance. */
9684 uint64_t reserved_7_63 : 57;
9685 #endif /* Word 0 - End */
9686 } s;
9687 struct bdk_gserx_sata_lanex_tx_ampx_cn81xx
9688 {
9689 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9690 uint64_t reserved_7_63 : 57;
9691 uint64_t tx_amp : 7; /**< [ 6: 0](R/W) This status value sets the TX driver launch amplitude in the
9692 case where the PHY is running at the Gen1, Gen2, and Gen3
9693 rates. Used for tuning at the board level for RX eye compliance.
9694 This register is used for SATA lanes only for GSER(3). */
9695 #else /* Word 0 - Little Endian */
9696 uint64_t tx_amp : 7; /**< [ 6: 0](R/W) This status value sets the TX driver launch amplitude in the
9697 case where the PHY is running at the Gen1, Gen2, and Gen3
9698 rates. Used for tuning at the board level for RX eye compliance.
9699 This register is used for SATA lanes only for GSER(3). */
9700 uint64_t reserved_7_63 : 57;
9701 #endif /* Word 0 - End */
9702 } cn81xx;
9703 /* struct bdk_gserx_sata_lanex_tx_ampx_s cn88xx; */
9704 struct bdk_gserx_sata_lanex_tx_ampx_cn83xx
9705 {
9706 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9707 uint64_t reserved_7_63 : 57;
9708 uint64_t tx_amp : 7; /**< [ 6: 0](R/W) This status value sets the TX driver launch amplitude in the
9709 case where the PHY is running at the Gen1, Gen2, and Gen3
9710 rates. Used for tuning at the board level for RX eye compliance.
9711 This register is used for SATA lanes only GSER(4..6).
9712
9713 Only SATA lanes 0 and 1 are used. */
9714 #else /* Word 0 - Little Endian */
9715 uint64_t tx_amp : 7; /**< [ 6: 0](R/W) This status value sets the TX driver launch amplitude in the
9716 case where the PHY is running at the Gen1, Gen2, and Gen3
9717 rates. Used for tuning at the board level for RX eye compliance.
9718 This register is used for SATA lanes only GSER(4..6).
9719
9720 Only SATA lanes 0 and 1 are used. */
9721 uint64_t reserved_7_63 : 57;
9722 #endif /* Word 0 - End */
9723 } cn83xx;
9724 };
9725 typedef union bdk_gserx_sata_lanex_tx_ampx bdk_gserx_sata_lanex_tx_ampx_t;
9726
9727 static inline uint64_t BDK_GSERX_SATA_LANEX_TX_AMPX(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_GSERX_SATA_LANEX_TX_AMPX(unsigned long a,unsigned long b,unsigned long c)9728 static inline uint64_t BDK_GSERX_SATA_LANEX_TX_AMPX(unsigned long a, unsigned long b, unsigned long c)
9729 {
9730 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1) && (c<=2)))
9731 return 0x87e090000b00ll + 0x1000000ll * ((a) & 0x3) + 0x20ll * ((b) & 0x1) + 8ll * ((c) & 0x3);
9732 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3) && (c<=2)))
9733 return 0x87e090000b00ll + 0x1000000ll * ((a) & 0x7) + 0x20ll * ((b) & 0x3) + 8ll * ((c) & 0x3);
9734 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3) && (c<=2)))
9735 return 0x87e090000b00ll + 0x1000000ll * ((a) & 0xf) + 0x20ll * ((b) & 0x3) + 8ll * ((c) & 0x3);
9736 __bdk_csr_fatal("GSERX_SATA_LANEX_TX_AMPX", 3, a, b, c, 0);
9737 }
9738
9739 #define typedef_BDK_GSERX_SATA_LANEX_TX_AMPX(a,b,c) bdk_gserx_sata_lanex_tx_ampx_t
9740 #define bustype_BDK_GSERX_SATA_LANEX_TX_AMPX(a,b,c) BDK_CSR_TYPE_RSL
9741 #define basename_BDK_GSERX_SATA_LANEX_TX_AMPX(a,b,c) "GSERX_SATA_LANEX_TX_AMPX"
9742 #define device_bar_BDK_GSERX_SATA_LANEX_TX_AMPX(a,b,c) 0x0 /* PF_BAR0 */
9743 #define busnum_BDK_GSERX_SATA_LANEX_TX_AMPX(a,b,c) (a)
9744 #define arguments_BDK_GSERX_SATA_LANEX_TX_AMPX(a,b,c) (a),(b),(c),-1
9745
9746 /**
9747 * Register (RSL) gser#_sata_lane#_tx_preemph#
9748 *
9749 * GSER SATA Lane Transmit Preemphsis Gen Register
9750 * SATA TX preemphasis at Gen 1, 2 and 3 speeds. The values of the CSR
9751 * fields in these registers do not change during chip warm or soft resets.
9752 * * PREEMPH(0) is for Gen1.
9753 * * PREEMPH(1) is for Gen2.
9754 * * PREEMPH(2) is for Gen3.
9755 */
9756 union bdk_gserx_sata_lanex_tx_preemphx
9757 {
9758 uint64_t u;
9759 struct bdk_gserx_sata_lanex_tx_preemphx_s
9760 {
9761 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9762 uint64_t reserved_7_63 : 57;
9763 uint64_t tx_preemph : 7; /**< [ 6: 0](R/W/H) This static value sets the TX driver deemphasis value in the
9764 case where the PHY is running at the Gen1, Gen2, and Gen3
9765 rates. Used for tuning at the board level for RX eye compliance. */
9766 #else /* Word 0 - Little Endian */
9767 uint64_t tx_preemph : 7; /**< [ 6: 0](R/W/H) This static value sets the TX driver deemphasis value in the
9768 case where the PHY is running at the Gen1, Gen2, and Gen3
9769 rates. Used for tuning at the board level for RX eye compliance. */
9770 uint64_t reserved_7_63 : 57;
9771 #endif /* Word 0 - End */
9772 } s;
9773 struct bdk_gserx_sata_lanex_tx_preemphx_cn81xx
9774 {
9775 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9776 uint64_t reserved_7_63 : 57;
9777 uint64_t tx_preemph : 7; /**< [ 6: 0](R/W/H) This static value sets the TX driver deemphasis value in the
9778 case where the PHY is running at the Gen1, Gen2, and Gen3
9779 rates. Used for tuning at the board level for RX eye compliance.
9780 This register is used for SATA lanes only for GSER(3). */
9781 #else /* Word 0 - Little Endian */
9782 uint64_t tx_preemph : 7; /**< [ 6: 0](R/W/H) This static value sets the TX driver deemphasis value in the
9783 case where the PHY is running at the Gen1, Gen2, and Gen3
9784 rates. Used for tuning at the board level for RX eye compliance.
9785 This register is used for SATA lanes only for GSER(3). */
9786 uint64_t reserved_7_63 : 57;
9787 #endif /* Word 0 - End */
9788 } cn81xx;
9789 /* struct bdk_gserx_sata_lanex_tx_preemphx_s cn88xx; */
9790 struct bdk_gserx_sata_lanex_tx_preemphx_cn83xx
9791 {
9792 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9793 uint64_t reserved_7_63 : 57;
9794 uint64_t tx_preemph : 7; /**< [ 6: 0](R/W/H) This static value sets the TX driver deemphasis value in the
9795 case where the PHY is running at the Gen1, Gen2, and Gen3
9796 rates. Used for tuning at the board level for RX eye compliance.
9797
9798 This register is used for SATA lanes only GSER(4..6).
9799 Only SATA lanes 0 and 1 are used. */
9800 #else /* Word 0 - Little Endian */
9801 uint64_t tx_preemph : 7; /**< [ 6: 0](R/W/H) This static value sets the TX driver deemphasis value in the
9802 case where the PHY is running at the Gen1, Gen2, and Gen3
9803 rates. Used for tuning at the board level for RX eye compliance.
9804
9805 This register is used for SATA lanes only GSER(4..6).
9806 Only SATA lanes 0 and 1 are used. */
9807 uint64_t reserved_7_63 : 57;
9808 #endif /* Word 0 - End */
9809 } cn83xx;
9810 };
9811 typedef union bdk_gserx_sata_lanex_tx_preemphx bdk_gserx_sata_lanex_tx_preemphx_t;
9812
9813 static inline uint64_t BDK_GSERX_SATA_LANEX_TX_PREEMPHX(unsigned long a, unsigned long b, unsigned long c) __attribute__ ((pure, always_inline));
BDK_GSERX_SATA_LANEX_TX_PREEMPHX(unsigned long a,unsigned long b,unsigned long c)9814 static inline uint64_t BDK_GSERX_SATA_LANEX_TX_PREEMPHX(unsigned long a, unsigned long b, unsigned long c)
9815 {
9816 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1) && (c<=2)))
9817 return 0x87e090000a00ll + 0x1000000ll * ((a) & 0x3) + 0x20ll * ((b) & 0x1) + 8ll * ((c) & 0x3);
9818 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=3) && (c<=2)))
9819 return 0x87e090000a00ll + 0x1000000ll * ((a) & 0x7) + 0x20ll * ((b) & 0x3) + 8ll * ((c) & 0x3);
9820 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=3) && (c<=2)))
9821 return 0x87e090000a00ll + 0x1000000ll * ((a) & 0xf) + 0x20ll * ((b) & 0x3) + 8ll * ((c) & 0x3);
9822 __bdk_csr_fatal("GSERX_SATA_LANEX_TX_PREEMPHX", 3, a, b, c, 0);
9823 }
9824
9825 #define typedef_BDK_GSERX_SATA_LANEX_TX_PREEMPHX(a,b,c) bdk_gserx_sata_lanex_tx_preemphx_t
9826 #define bustype_BDK_GSERX_SATA_LANEX_TX_PREEMPHX(a,b,c) BDK_CSR_TYPE_RSL
9827 #define basename_BDK_GSERX_SATA_LANEX_TX_PREEMPHX(a,b,c) "GSERX_SATA_LANEX_TX_PREEMPHX"
9828 #define device_bar_BDK_GSERX_SATA_LANEX_TX_PREEMPHX(a,b,c) 0x0 /* PF_BAR0 */
9829 #define busnum_BDK_GSERX_SATA_LANEX_TX_PREEMPHX(a,b,c) (a)
9830 #define arguments_BDK_GSERX_SATA_LANEX_TX_PREEMPHX(a,b,c) (a),(b),(c),-1
9831
9832 /**
9833 * Register (RSL) gser#_sata_lane_rst
9834 *
9835 * GSER SATA Lane Reset Register
9836 * Lane Reset Control.
9837 */
9838 union bdk_gserx_sata_lane_rst
9839 {
9840 uint64_t u;
9841 struct bdk_gserx_sata_lane_rst_s
9842 {
9843 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9844 uint64_t reserved_4_63 : 60;
9845 uint64_t l3_rst : 1; /**< [ 3: 3](R/W) Independent reset for Lane 3. */
9846 uint64_t l2_rst : 1; /**< [ 2: 2](R/W) Independent reset for Lane 2. */
9847 uint64_t l1_rst : 1; /**< [ 1: 1](R/W) Independent reset for Lane 1. */
9848 uint64_t l0_rst : 1; /**< [ 0: 0](R/W) Independent reset for Lane 0. */
9849 #else /* Word 0 - Little Endian */
9850 uint64_t l0_rst : 1; /**< [ 0: 0](R/W) Independent reset for Lane 0. */
9851 uint64_t l1_rst : 1; /**< [ 1: 1](R/W) Independent reset for Lane 1. */
9852 uint64_t l2_rst : 1; /**< [ 2: 2](R/W) Independent reset for Lane 2. */
9853 uint64_t l3_rst : 1; /**< [ 3: 3](R/W) Independent reset for Lane 3. */
9854 uint64_t reserved_4_63 : 60;
9855 #endif /* Word 0 - End */
9856 } s;
9857 struct bdk_gserx_sata_lane_rst_cn81xx
9858 {
9859 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9860 uint64_t reserved_4_63 : 60;
9861 uint64_t l3_rst : 1; /**< [ 3: 3](RO/H) Reserved. */
9862 uint64_t l2_rst : 1; /**< [ 2: 2](RO/H) Reserved. */
9863 uint64_t l1_rst : 1; /**< [ 1: 1](R/W) Independent reset for lane 1.
9864 This register is used for SATA lanes only for GSER(3). */
9865 uint64_t l0_rst : 1; /**< [ 0: 0](R/W) Independent reset for lane 0.
9866 This register is used for SATA lanes only for GSER(3). */
9867 #else /* Word 0 - Little Endian */
9868 uint64_t l0_rst : 1; /**< [ 0: 0](R/W) Independent reset for lane 0.
9869 This register is used for SATA lanes only for GSER(3). */
9870 uint64_t l1_rst : 1; /**< [ 1: 1](R/W) Independent reset for lane 1.
9871 This register is used for SATA lanes only for GSER(3). */
9872 uint64_t l2_rst : 1; /**< [ 2: 2](RO/H) Reserved. */
9873 uint64_t l3_rst : 1; /**< [ 3: 3](RO/H) Reserved. */
9874 uint64_t reserved_4_63 : 60;
9875 #endif /* Word 0 - End */
9876 } cn81xx;
9877 /* struct bdk_gserx_sata_lane_rst_s cn88xx; */
9878 struct bdk_gserx_sata_lane_rst_cn83xx
9879 {
9880 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9881 uint64_t reserved_4_63 : 60;
9882 uint64_t l3_rst : 1; /**< [ 3: 3](RO/H) Reserved. */
9883 uint64_t l2_rst : 1; /**< [ 2: 2](RO/H) Reserved. */
9884 uint64_t l1_rst : 1; /**< [ 1: 1](R/W) Independent reset for lane 1.
9885 This register is used for SATA lanes only for GSER(4..6). */
9886 uint64_t l0_rst : 1; /**< [ 0: 0](R/W) Independent reset for lane 0.
9887 This register is used for SATA lanes only for GSER(4..6). */
9888 #else /* Word 0 - Little Endian */
9889 uint64_t l0_rst : 1; /**< [ 0: 0](R/W) Independent reset for lane 0.
9890 This register is used for SATA lanes only for GSER(4..6). */
9891 uint64_t l1_rst : 1; /**< [ 1: 1](R/W) Independent reset for lane 1.
9892 This register is used for SATA lanes only for GSER(4..6). */
9893 uint64_t l2_rst : 1; /**< [ 2: 2](RO/H) Reserved. */
9894 uint64_t l3_rst : 1; /**< [ 3: 3](RO/H) Reserved. */
9895 uint64_t reserved_4_63 : 60;
9896 #endif /* Word 0 - End */
9897 } cn83xx;
9898 };
9899 typedef union bdk_gserx_sata_lane_rst bdk_gserx_sata_lane_rst_t;
9900
9901 static inline uint64_t BDK_GSERX_SATA_LANE_RST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_SATA_LANE_RST(unsigned long a)9902 static inline uint64_t BDK_GSERX_SATA_LANE_RST(unsigned long a)
9903 {
9904 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
9905 return 0x87e090000908ll + 0x1000000ll * ((a) & 0x3);
9906 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
9907 return 0x87e090000908ll + 0x1000000ll * ((a) & 0x7);
9908 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
9909 return 0x87e090000908ll + 0x1000000ll * ((a) & 0xf);
9910 __bdk_csr_fatal("GSERX_SATA_LANE_RST", 1, a, 0, 0, 0);
9911 }
9912
9913 #define typedef_BDK_GSERX_SATA_LANE_RST(a) bdk_gserx_sata_lane_rst_t
9914 #define bustype_BDK_GSERX_SATA_LANE_RST(a) BDK_CSR_TYPE_RSL
9915 #define basename_BDK_GSERX_SATA_LANE_RST(a) "GSERX_SATA_LANE_RST"
9916 #define device_bar_BDK_GSERX_SATA_LANE_RST(a) 0x0 /* PF_BAR0 */
9917 #define busnum_BDK_GSERX_SATA_LANE_RST(a) (a)
9918 #define arguments_BDK_GSERX_SATA_LANE_RST(a) (a),-1,-1,-1
9919
9920 /**
9921 * Register (RSL) gser#_sata_status
9922 *
9923 * GSER SATA Status Register
9924 * SATA PHY Ready Status.
9925 */
9926 union bdk_gserx_sata_status
9927 {
9928 uint64_t u;
9929 struct bdk_gserx_sata_status_s
9930 {
9931 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9932 uint64_t reserved_4_63 : 60;
9933 uint64_t p3_rdy : 1; /**< [ 3: 3](RO/H) PHY Lane 3 is ready to send and receive data. */
9934 uint64_t p2_rdy : 1; /**< [ 2: 2](RO/H) PHY Lane 2 is ready to send and receive data. */
9935 uint64_t p1_rdy : 1; /**< [ 1: 1](RO/H) PHY Lane 1 is ready to send and receive data. */
9936 uint64_t p0_rdy : 1; /**< [ 0: 0](RO/H) PHY Lane 0 is ready to send and receive data. */
9937 #else /* Word 0 - Little Endian */
9938 uint64_t p0_rdy : 1; /**< [ 0: 0](RO/H) PHY Lane 0 is ready to send and receive data. */
9939 uint64_t p1_rdy : 1; /**< [ 1: 1](RO/H) PHY Lane 1 is ready to send and receive data. */
9940 uint64_t p2_rdy : 1; /**< [ 2: 2](RO/H) PHY Lane 2 is ready to send and receive data. */
9941 uint64_t p3_rdy : 1; /**< [ 3: 3](RO/H) PHY Lane 3 is ready to send and receive data. */
9942 uint64_t reserved_4_63 : 60;
9943 #endif /* Word 0 - End */
9944 } s;
9945 struct bdk_gserx_sata_status_cn81xx
9946 {
9947 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9948 uint64_t reserved_4_63 : 60;
9949 uint64_t p3_rdy : 1; /**< [ 3: 3](RO/H) Reserved. */
9950 uint64_t p2_rdy : 1; /**< [ 2: 2](RO/H) Reserved. */
9951 uint64_t p1_rdy : 1; /**< [ 1: 1](RO/H) PHY lane 1 is ready to send and receive data.
9952 This register is used for SATA lanes only for GSER(3). */
9953 uint64_t p0_rdy : 1; /**< [ 0: 0](RO/H) PHY lane 0 is ready to send and receive data.
9954 This register is used for SATA lanes only for GSER(3). */
9955 #else /* Word 0 - Little Endian */
9956 uint64_t p0_rdy : 1; /**< [ 0: 0](RO/H) PHY lane 0 is ready to send and receive data.
9957 This register is used for SATA lanes only for GSER(3). */
9958 uint64_t p1_rdy : 1; /**< [ 1: 1](RO/H) PHY lane 1 is ready to send and receive data.
9959 This register is used for SATA lanes only for GSER(3). */
9960 uint64_t p2_rdy : 1; /**< [ 2: 2](RO/H) Reserved. */
9961 uint64_t p3_rdy : 1; /**< [ 3: 3](RO/H) Reserved. */
9962 uint64_t reserved_4_63 : 60;
9963 #endif /* Word 0 - End */
9964 } cn81xx;
9965 /* struct bdk_gserx_sata_status_s cn88xx; */
9966 struct bdk_gserx_sata_status_cn83xx
9967 {
9968 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9969 uint64_t reserved_4_63 : 60;
9970 uint64_t p3_rdy : 1; /**< [ 3: 3](RO/H) Reserved. */
9971 uint64_t p2_rdy : 1; /**< [ 2: 2](RO/H) Reserved. */
9972 uint64_t p1_rdy : 1; /**< [ 1: 1](RO/H) PHY lane 1 is ready to send and receive data.
9973 This register is used for SATA lanes only GSER(4..6). */
9974 uint64_t p0_rdy : 1; /**< [ 0: 0](RO/H) PHY lane 0 is ready to send and receive data.
9975 This register is used for SATA lanes only GSER(4..6). */
9976 #else /* Word 0 - Little Endian */
9977 uint64_t p0_rdy : 1; /**< [ 0: 0](RO/H) PHY lane 0 is ready to send and receive data.
9978 This register is used for SATA lanes only GSER(4..6). */
9979 uint64_t p1_rdy : 1; /**< [ 1: 1](RO/H) PHY lane 1 is ready to send and receive data.
9980 This register is used for SATA lanes only GSER(4..6). */
9981 uint64_t p2_rdy : 1; /**< [ 2: 2](RO/H) Reserved. */
9982 uint64_t p3_rdy : 1; /**< [ 3: 3](RO/H) Reserved. */
9983 uint64_t reserved_4_63 : 60;
9984 #endif /* Word 0 - End */
9985 } cn83xx;
9986 };
9987 typedef union bdk_gserx_sata_status bdk_gserx_sata_status_t;
9988
9989 static inline uint64_t BDK_GSERX_SATA_STATUS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_SATA_STATUS(unsigned long a)9990 static inline uint64_t BDK_GSERX_SATA_STATUS(unsigned long a)
9991 {
9992 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
9993 return 0x87e090100900ll + 0x1000000ll * ((a) & 0x3);
9994 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
9995 return 0x87e090100900ll + 0x1000000ll * ((a) & 0x7);
9996 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
9997 return 0x87e090100900ll + 0x1000000ll * ((a) & 0xf);
9998 __bdk_csr_fatal("GSERX_SATA_STATUS", 1, a, 0, 0, 0);
9999 }
10000
10001 #define typedef_BDK_GSERX_SATA_STATUS(a) bdk_gserx_sata_status_t
10002 #define bustype_BDK_GSERX_SATA_STATUS(a) BDK_CSR_TYPE_RSL
10003 #define basename_BDK_GSERX_SATA_STATUS(a) "GSERX_SATA_STATUS"
10004 #define device_bar_BDK_GSERX_SATA_STATUS(a) 0x0 /* PF_BAR0 */
10005 #define busnum_BDK_GSERX_SATA_STATUS(a) (a)
10006 #define arguments_BDK_GSERX_SATA_STATUS(a) (a),-1,-1,-1
10007
10008 /**
10009 * Register (RSL) gser#_sata_tx_invert
10010 *
10011 * GSER SATA TX Invert Register
10012 * Lane Reset Control.
10013 */
10014 union bdk_gserx_sata_tx_invert
10015 {
10016 uint64_t u;
10017 struct bdk_gserx_sata_tx_invert_s
10018 {
10019 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10020 uint64_t reserved_4_63 : 60;
10021 uint64_t l3_inv : 1; /**< [ 3: 3](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10022 lane 3 transmitted data. */
10023 uint64_t l2_inv : 1; /**< [ 2: 2](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10024 lane 2 transmitted data. */
10025 uint64_t l1_inv : 1; /**< [ 1: 1](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10026 lane 1 transmitted data. */
10027 uint64_t l0_inv : 1; /**< [ 0: 0](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10028 lane 0 transmitted data. */
10029 #else /* Word 0 - Little Endian */
10030 uint64_t l0_inv : 1; /**< [ 0: 0](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10031 lane 0 transmitted data. */
10032 uint64_t l1_inv : 1; /**< [ 1: 1](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10033 lane 1 transmitted data. */
10034 uint64_t l2_inv : 1; /**< [ 2: 2](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10035 lane 2 transmitted data. */
10036 uint64_t l3_inv : 1; /**< [ 3: 3](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10037 lane 3 transmitted data. */
10038 uint64_t reserved_4_63 : 60;
10039 #endif /* Word 0 - End */
10040 } s;
10041 struct bdk_gserx_sata_tx_invert_cn81xx
10042 {
10043 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10044 uint64_t reserved_4_63 : 60;
10045 uint64_t l3_inv : 1; /**< [ 3: 3](RO/H) Reserved. */
10046 uint64_t l2_inv : 1; /**< [ 2: 2](RO/H) Reserved. */
10047 uint64_t l1_inv : 1; /**< [ 1: 1](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10048 lane 1 transmitted data.
10049 This register is used for SATA lanes only for GSER(3). */
10050 uint64_t l0_inv : 1; /**< [ 0: 0](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10051 lane 0 transmitted data.
10052 This register is used for SATA lanes only for GSER(3). */
10053 #else /* Word 0 - Little Endian */
10054 uint64_t l0_inv : 1; /**< [ 0: 0](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10055 lane 0 transmitted data.
10056 This register is used for SATA lanes only for GSER(3). */
10057 uint64_t l1_inv : 1; /**< [ 1: 1](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10058 lane 1 transmitted data.
10059 This register is used for SATA lanes only for GSER(3). */
10060 uint64_t l2_inv : 1; /**< [ 2: 2](RO/H) Reserved. */
10061 uint64_t l3_inv : 1; /**< [ 3: 3](RO/H) Reserved. */
10062 uint64_t reserved_4_63 : 60;
10063 #endif /* Word 0 - End */
10064 } cn81xx;
10065 /* struct bdk_gserx_sata_tx_invert_s cn88xx; */
10066 struct bdk_gserx_sata_tx_invert_cn83xx
10067 {
10068 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10069 uint64_t reserved_4_63 : 60;
10070 uint64_t l3_inv : 1; /**< [ 3: 3](RO/H) Reserved. */
10071 uint64_t l2_inv : 1; /**< [ 2: 2](RO/H) Reserved. */
10072 uint64_t l1_inv : 1; /**< [ 1: 1](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10073 lane 1 transmitted data.
10074 This register is used for SATA lanes only for GSER(4..6). */
10075 uint64_t l0_inv : 1; /**< [ 0: 0](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10076 lane 0 transmitted data.
10077 This register is used for SATA lanes only for GSER(4..6). */
10078 #else /* Word 0 - Little Endian */
10079 uint64_t l0_inv : 1; /**< [ 0: 0](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10080 lane 0 transmitted data.
10081 This register is used for SATA lanes only for GSER(4..6). */
10082 uint64_t l1_inv : 1; /**< [ 1: 1](R/W) Instructs the SATA PCS to perform a polarity inversion on the
10083 lane 1 transmitted data.
10084 This register is used for SATA lanes only for GSER(4..6). */
10085 uint64_t l2_inv : 1; /**< [ 2: 2](RO/H) Reserved. */
10086 uint64_t l3_inv : 1; /**< [ 3: 3](RO/H) Reserved. */
10087 uint64_t reserved_4_63 : 60;
10088 #endif /* Word 0 - End */
10089 } cn83xx;
10090 };
10091 typedef union bdk_gserx_sata_tx_invert bdk_gserx_sata_tx_invert_t;
10092
10093 static inline uint64_t BDK_GSERX_SATA_TX_INVERT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_SATA_TX_INVERT(unsigned long a)10094 static inline uint64_t BDK_GSERX_SATA_TX_INVERT(unsigned long a)
10095 {
10096 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
10097 return 0x87e090000910ll + 0x1000000ll * ((a) & 0x3);
10098 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
10099 return 0x87e090000910ll + 0x1000000ll * ((a) & 0x7);
10100 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
10101 return 0x87e090000910ll + 0x1000000ll * ((a) & 0xf);
10102 __bdk_csr_fatal("GSERX_SATA_TX_INVERT", 1, a, 0, 0, 0);
10103 }
10104
10105 #define typedef_BDK_GSERX_SATA_TX_INVERT(a) bdk_gserx_sata_tx_invert_t
10106 #define bustype_BDK_GSERX_SATA_TX_INVERT(a) BDK_CSR_TYPE_RSL
10107 #define basename_BDK_GSERX_SATA_TX_INVERT(a) "GSERX_SATA_TX_INVERT"
10108 #define device_bar_BDK_GSERX_SATA_TX_INVERT(a) 0x0 /* PF_BAR0 */
10109 #define busnum_BDK_GSERX_SATA_TX_INVERT(a) (a)
10110 #define arguments_BDK_GSERX_SATA_TX_INVERT(a) (a),-1,-1,-1
10111
10112 /**
10113 * Register (RSL) gser#_scratch
10114 *
10115 * GSER General Purpose Scratch Register
10116 * These registers are reset by hardware only during chip cold reset. The values of the CSR
10117 * fields in these registers do not change during chip warm or soft resets.
10118 */
10119 union bdk_gserx_scratch
10120 {
10121 uint64_t u;
10122 struct bdk_gserx_scratch_s
10123 {
10124 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10125 uint64_t reserved_16_63 : 48;
10126 uint64_t scratch : 16; /**< [ 15: 0](R/W) General purpose scratch register. */
10127 #else /* Word 0 - Little Endian */
10128 uint64_t scratch : 16; /**< [ 15: 0](R/W) General purpose scratch register. */
10129 uint64_t reserved_16_63 : 48;
10130 #endif /* Word 0 - End */
10131 } s;
10132 /* struct bdk_gserx_scratch_s cn; */
10133 };
10134 typedef union bdk_gserx_scratch bdk_gserx_scratch_t;
10135
10136 static inline uint64_t BDK_GSERX_SCRATCH(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_SCRATCH(unsigned long a)10137 static inline uint64_t BDK_GSERX_SCRATCH(unsigned long a)
10138 {
10139 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
10140 return 0x87e090000020ll + 0x1000000ll * ((a) & 0x3);
10141 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
10142 return 0x87e090000020ll + 0x1000000ll * ((a) & 0x7);
10143 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
10144 return 0x87e090000020ll + 0x1000000ll * ((a) & 0xf);
10145 __bdk_csr_fatal("GSERX_SCRATCH", 1, a, 0, 0, 0);
10146 }
10147
10148 #define typedef_BDK_GSERX_SCRATCH(a) bdk_gserx_scratch_t
10149 #define bustype_BDK_GSERX_SCRATCH(a) BDK_CSR_TYPE_RSL
10150 #define basename_BDK_GSERX_SCRATCH(a) "GSERX_SCRATCH"
10151 #define device_bar_BDK_GSERX_SCRATCH(a) 0x0 /* PF_BAR0 */
10152 #define busnum_BDK_GSERX_SCRATCH(a) (a)
10153 #define arguments_BDK_GSERX_SCRATCH(a) (a),-1,-1,-1
10154
10155 /**
10156 * Register (RSL) gser#_slice#_cei_6g_sr_mode
10157 *
10158 * GSER Slice CEI_6G_SR MODE Register
10159 * These registers are for diagnostic use only.
10160 * These registers are reset by hardware only during chip cold reset.
10161 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
10162 */
10163 union bdk_gserx_slicex_cei_6g_sr_mode
10164 {
10165 uint64_t u;
10166 struct bdk_gserx_slicex_cei_6g_sr_mode_s
10167 {
10168 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10169 uint64_t reserved_15_63 : 49;
10170 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10171 Bit 13 controls enable for lane 0.
10172 Bit 14 controls enable for lane 1. */
10173 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10174 0x0 = 500 uA.
10175 0x1 = 1000 uA.
10176 0x2 = 250 uA.
10177 0x3 = 330 uA. */
10178 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10179 0x0 = 500 uA.
10180 0x1 = 1000 uA.
10181 0x2 = 250 uA.
10182 0x3 = 330 uA. */
10183 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10184 0x0 = 2.5 GHz.
10185 0x1 = 3.125 GHz.
10186 0x6 = 4 GHz.
10187 0x7 = 5.15625 GHz.
10188
10189 All other values in this field are reserved. */
10190 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10191 based on the PLL clock frequency as follows:
10192 0x0 = 2.5 GHz.
10193 0x1 = 3.125 GHz.
10194 0x3 = 4 GHz.
10195 0x5 = 5.15625 GHz.
10196 0x6 = 5.65 GHz.
10197 0x7 = 6.25 GHz.
10198
10199 All other values in this field are reserved. */
10200 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10201 based on the PLL clock frequency as follows:
10202 0x0 = 2.5 GHz.
10203 0x1 = 3.125 GHz.
10204 0x3 = 4 GHz.
10205 0x5 = 5.15625 GHz.
10206 0x6 = 5.65 GHz.
10207 0x7 = 6.25 GHz.
10208
10209 All other values in this field are reserved. */
10210 #else /* Word 0 - Little Endian */
10211 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10212 based on the PLL clock frequency as follows:
10213 0x0 = 2.5 GHz.
10214 0x1 = 3.125 GHz.
10215 0x3 = 4 GHz.
10216 0x5 = 5.15625 GHz.
10217 0x6 = 5.65 GHz.
10218 0x7 = 6.25 GHz.
10219
10220 All other values in this field are reserved. */
10221 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10222 based on the PLL clock frequency as follows:
10223 0x0 = 2.5 GHz.
10224 0x1 = 3.125 GHz.
10225 0x3 = 4 GHz.
10226 0x5 = 5.15625 GHz.
10227 0x6 = 5.65 GHz.
10228 0x7 = 6.25 GHz.
10229
10230 All other values in this field are reserved. */
10231 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10232 0x0 = 2.5 GHz.
10233 0x1 = 3.125 GHz.
10234 0x6 = 4 GHz.
10235 0x7 = 5.15625 GHz.
10236
10237 All other values in this field are reserved. */
10238 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10239 0x0 = 500 uA.
10240 0x1 = 1000 uA.
10241 0x2 = 250 uA.
10242 0x3 = 330 uA. */
10243 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10244 0x0 = 500 uA.
10245 0x1 = 1000 uA.
10246 0x2 = 250 uA.
10247 0x3 = 330 uA. */
10248 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10249 Bit 13 controls enable for lane 0.
10250 Bit 14 controls enable for lane 1. */
10251 uint64_t reserved_15_63 : 49;
10252 #endif /* Word 0 - End */
10253 } s;
10254 /* struct bdk_gserx_slicex_cei_6g_sr_mode_s cn; */
10255 };
10256 typedef union bdk_gserx_slicex_cei_6g_sr_mode bdk_gserx_slicex_cei_6g_sr_mode_t;
10257
10258 static inline uint64_t BDK_GSERX_SLICEX_CEI_6G_SR_MODE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_CEI_6G_SR_MODE(unsigned long a,unsigned long b)10259 static inline uint64_t BDK_GSERX_SLICEX_CEI_6G_SR_MODE(unsigned long a, unsigned long b)
10260 {
10261 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
10262 return 0x87e090460268ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
10263 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
10264 return 0x87e090460268ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
10265 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
10266 return 0x87e090460268ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
10267 __bdk_csr_fatal("GSERX_SLICEX_CEI_6G_SR_MODE", 2, a, b, 0, 0);
10268 }
10269
10270 #define typedef_BDK_GSERX_SLICEX_CEI_6G_SR_MODE(a,b) bdk_gserx_slicex_cei_6g_sr_mode_t
10271 #define bustype_BDK_GSERX_SLICEX_CEI_6G_SR_MODE(a,b) BDK_CSR_TYPE_RSL
10272 #define basename_BDK_GSERX_SLICEX_CEI_6G_SR_MODE(a,b) "GSERX_SLICEX_CEI_6G_SR_MODE"
10273 #define device_bar_BDK_GSERX_SLICEX_CEI_6G_SR_MODE(a,b) 0x0 /* PF_BAR0 */
10274 #define busnum_BDK_GSERX_SLICEX_CEI_6G_SR_MODE(a,b) (a)
10275 #define arguments_BDK_GSERX_SLICEX_CEI_6G_SR_MODE(a,b) (a),(b),-1,-1
10276
10277 /**
10278 * Register (RSL) gser#_slice#_kr_mode
10279 *
10280 * GSER Slice KR MODE Register
10281 * These registers are for diagnostic use only.
10282 * These registers are reset by hardware only during chip cold reset.
10283 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
10284 */
10285 union bdk_gserx_slicex_kr_mode
10286 {
10287 uint64_t u;
10288 struct bdk_gserx_slicex_kr_mode_s
10289 {
10290 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10291 uint64_t reserved_15_63 : 49;
10292 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10293 Bit 13 controls enable for lane 0.
10294 Bit 14 controls enable for lane 1. */
10295 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10296 0x0 = 500 uA.
10297 0x1 = 1000 uA.
10298 0x2 = 250 uA.
10299 0x3 = 330 uA. */
10300 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10301 0x0 = 500 uA.
10302 0x1 = 1000 uA.
10303 0x2 = 250 uA.
10304 0x3 = 330 uA. */
10305 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10306 0x0 = 2.5 GHz.
10307 0x1 = 3.125 GHz.
10308 0x6 = 4 GHz.
10309 0x7 = 5.15625 GHz.
10310
10311 All other values in this field are reserved. */
10312 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10313 based on the PLL clock frequency as follows:
10314 0x0 = 2.5 GHz.
10315 0x1 = 3.125 GHz.
10316 0x3 = 4 GHz.
10317 0x5 = 5.15625 GHz.
10318 0x6 = 5.65 GHz.
10319 0x7 = 6.25 GHz.
10320
10321 All other values in this field are reserved. */
10322 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10323 based on the PLL clock frequency as follows:
10324 0x0 = 2.5 GHz.
10325 0x1 = 3.125 GHz.
10326 0x3 = 4 GHz.
10327 0x5 = 5.15625 GHz.
10328 0x6 = 5.65 GHz.
10329 0x7 = 6.25 GHz.
10330
10331 All other values in this field are reserved. */
10332 #else /* Word 0 - Little Endian */
10333 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10334 based on the PLL clock frequency as follows:
10335 0x0 = 2.5 GHz.
10336 0x1 = 3.125 GHz.
10337 0x3 = 4 GHz.
10338 0x5 = 5.15625 GHz.
10339 0x6 = 5.65 GHz.
10340 0x7 = 6.25 GHz.
10341
10342 All other values in this field are reserved. */
10343 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10344 based on the PLL clock frequency as follows:
10345 0x0 = 2.5 GHz.
10346 0x1 = 3.125 GHz.
10347 0x3 = 4 GHz.
10348 0x5 = 5.15625 GHz.
10349 0x6 = 5.65 GHz.
10350 0x7 = 6.25 GHz.
10351
10352 All other values in this field are reserved. */
10353 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10354 0x0 = 2.5 GHz.
10355 0x1 = 3.125 GHz.
10356 0x6 = 4 GHz.
10357 0x7 = 5.15625 GHz.
10358
10359 All other values in this field are reserved. */
10360 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10361 0x0 = 500 uA.
10362 0x1 = 1000 uA.
10363 0x2 = 250 uA.
10364 0x3 = 330 uA. */
10365 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10366 0x0 = 500 uA.
10367 0x1 = 1000 uA.
10368 0x2 = 250 uA.
10369 0x3 = 330 uA. */
10370 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10371 Bit 13 controls enable for lane 0.
10372 Bit 14 controls enable for lane 1. */
10373 uint64_t reserved_15_63 : 49;
10374 #endif /* Word 0 - End */
10375 } s;
10376 /* struct bdk_gserx_slicex_kr_mode_s cn; */
10377 };
10378 typedef union bdk_gserx_slicex_kr_mode bdk_gserx_slicex_kr_mode_t;
10379
10380 static inline uint64_t BDK_GSERX_SLICEX_KR_MODE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_KR_MODE(unsigned long a,unsigned long b)10381 static inline uint64_t BDK_GSERX_SLICEX_KR_MODE(unsigned long a, unsigned long b)
10382 {
10383 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
10384 return 0x87e090460250ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
10385 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
10386 return 0x87e090460250ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
10387 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
10388 return 0x87e090460250ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
10389 __bdk_csr_fatal("GSERX_SLICEX_KR_MODE", 2, a, b, 0, 0);
10390 }
10391
10392 #define typedef_BDK_GSERX_SLICEX_KR_MODE(a,b) bdk_gserx_slicex_kr_mode_t
10393 #define bustype_BDK_GSERX_SLICEX_KR_MODE(a,b) BDK_CSR_TYPE_RSL
10394 #define basename_BDK_GSERX_SLICEX_KR_MODE(a,b) "GSERX_SLICEX_KR_MODE"
10395 #define device_bar_BDK_GSERX_SLICEX_KR_MODE(a,b) 0x0 /* PF_BAR0 */
10396 #define busnum_BDK_GSERX_SLICEX_KR_MODE(a,b) (a)
10397 #define arguments_BDK_GSERX_SLICEX_KR_MODE(a,b) (a),(b),-1,-1
10398
10399 /**
10400 * Register (RSL) gser#_slice#_kx4_mode
10401 *
10402 * GSER Slice KX4 MODE Register
10403 * These registers are for diagnostic use only.
10404 * These registers are reset by hardware only during chip cold reset.
10405 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
10406 */
10407 union bdk_gserx_slicex_kx4_mode
10408 {
10409 uint64_t u;
10410 struct bdk_gserx_slicex_kx4_mode_s
10411 {
10412 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10413 uint64_t reserved_15_63 : 49;
10414 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10415 Bit 13 controls enable for lane 0.
10416 Bit 14 controls enable for lane 1. */
10417 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10418 0x0 = 500 uA.
10419 0x1 = 1000 uA.
10420 0x2 = 250 uA.
10421 0x3 = 330 uA. */
10422 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10423 0x0 = 500 uA.
10424 0x1 = 1000 uA.
10425 0x2 = 250 uA.
10426 0x3 = 330 uA. */
10427 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10428 0x0 = 2.5 GHz.
10429 0x1 = 3.125 GHz.
10430 0x6 = 4 GHz.
10431 0x7 = 5.15625 GHz.
10432
10433 All other values in this field are reserved. */
10434 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10435 based on the PLL clock frequency as follows:
10436 0x0 = 2.5 GHz.
10437 0x1 = 3.125 GHz.
10438 0x3 = 4 GHz.
10439 0x5 = 5.15625 GHz.
10440 0x6 = 5.65 GHz.
10441 0x7 = 6.25 GHz.
10442
10443 All other values in this field are reserved. */
10444 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10445 based on the PLL clock frequency as follows:
10446 0x0 = 2.5 GHz.
10447 0x1 = 3.125 GHz.
10448 0x3 = 4 GHz.
10449 0x5 = 5.15625 GHz.
10450 0x6 = 5.65 GHz.
10451 0x7 = 6.25 GHz.
10452
10453 All other values in this field are reserved. */
10454 #else /* Word 0 - Little Endian */
10455 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10456 based on the PLL clock frequency as follows:
10457 0x0 = 2.5 GHz.
10458 0x1 = 3.125 GHz.
10459 0x3 = 4 GHz.
10460 0x5 = 5.15625 GHz.
10461 0x6 = 5.65 GHz.
10462 0x7 = 6.25 GHz.
10463
10464 All other values in this field are reserved. */
10465 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10466 based on the PLL clock frequency as follows:
10467 0x0 = 2.5 GHz.
10468 0x1 = 3.125 GHz.
10469 0x3 = 4 GHz.
10470 0x5 = 5.15625 GHz.
10471 0x6 = 5.65 GHz.
10472 0x7 = 6.25 GHz.
10473
10474 All other values in this field are reserved. */
10475 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10476 0x0 = 2.5 GHz.
10477 0x1 = 3.125 GHz.
10478 0x6 = 4 GHz.
10479 0x7 = 5.15625 GHz.
10480
10481 All other values in this field are reserved. */
10482 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10483 0x0 = 500 uA.
10484 0x1 = 1000 uA.
10485 0x2 = 250 uA.
10486 0x3 = 330 uA. */
10487 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10488 0x0 = 500 uA.
10489 0x1 = 1000 uA.
10490 0x2 = 250 uA.
10491 0x3 = 330 uA. */
10492 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10493 Bit 13 controls enable for lane 0.
10494 Bit 14 controls enable for lane 1. */
10495 uint64_t reserved_15_63 : 49;
10496 #endif /* Word 0 - End */
10497 } s;
10498 /* struct bdk_gserx_slicex_kx4_mode_s cn; */
10499 };
10500 typedef union bdk_gserx_slicex_kx4_mode bdk_gserx_slicex_kx4_mode_t;
10501
10502 static inline uint64_t BDK_GSERX_SLICEX_KX4_MODE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_KX4_MODE(unsigned long a,unsigned long b)10503 static inline uint64_t BDK_GSERX_SLICEX_KX4_MODE(unsigned long a, unsigned long b)
10504 {
10505 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
10506 return 0x87e090460248ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
10507 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
10508 return 0x87e090460248ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
10509 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
10510 return 0x87e090460248ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
10511 __bdk_csr_fatal("GSERX_SLICEX_KX4_MODE", 2, a, b, 0, 0);
10512 }
10513
10514 #define typedef_BDK_GSERX_SLICEX_KX4_MODE(a,b) bdk_gserx_slicex_kx4_mode_t
10515 #define bustype_BDK_GSERX_SLICEX_KX4_MODE(a,b) BDK_CSR_TYPE_RSL
10516 #define basename_BDK_GSERX_SLICEX_KX4_MODE(a,b) "GSERX_SLICEX_KX4_MODE"
10517 #define device_bar_BDK_GSERX_SLICEX_KX4_MODE(a,b) 0x0 /* PF_BAR0 */
10518 #define busnum_BDK_GSERX_SLICEX_KX4_MODE(a,b) (a)
10519 #define arguments_BDK_GSERX_SLICEX_KX4_MODE(a,b) (a),(b),-1,-1
10520
10521 /**
10522 * Register (RSL) gser#_slice#_kx_mode
10523 *
10524 * GSER Slice KX MODE Register
10525 * These registers are for diagnostic use only.
10526 * These registers are reset by hardware only during chip cold reset.
10527 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
10528 */
10529 union bdk_gserx_slicex_kx_mode
10530 {
10531 uint64_t u;
10532 struct bdk_gserx_slicex_kx_mode_s
10533 {
10534 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10535 uint64_t reserved_15_63 : 49;
10536 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10537 Bit 13 controls enable for lane 0.
10538 Bit 14 controls enable for lane 1. */
10539 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10540 0x0 = 500 uA.
10541 0x1 = 1000 uA.
10542 0x2 = 250 uA.
10543 0x3 = 330 uA. */
10544 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10545 0x0 = 500 uA.
10546 0x1 = 1000 uA.
10547 0x2 = 250 uA.
10548 0x3 = 330 uA. */
10549 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10550 0x0 = 2.5 GHz.
10551 0x1 = 3.125 GHz.
10552 0x6 = 4 GHz.
10553 0x7 = 5.15625 GHz.
10554
10555 All other values in this field are reserved. */
10556 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10557 based on the PLL clock frequency as follows:
10558 0x0 = 2.5 GHz.
10559 0x1 = 3.125 GHz.
10560 0x3 = 4 GHz.
10561 0x5 = 5.15625 GHz.
10562 0x6 = 5.65 GHz.
10563 0x7 = 6.25 GHz.
10564
10565 All other values in this field are reserved. */
10566 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10567 based on the PLL clock frequency as follows:
10568 0x0 = 2.5 GHz.
10569 0x1 = 3.125 GHz.
10570 0x3 = 4 GHz.
10571 0x5 = 5.15625 GHz.
10572 0x6 = 5.65 GHz.
10573 0x7 = 6.25 GHz.
10574
10575 All other values in this field are reserved. */
10576 #else /* Word 0 - Little Endian */
10577 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10578 based on the PLL clock frequency as follows:
10579 0x0 = 2.5 GHz.
10580 0x1 = 3.125 GHz.
10581 0x3 = 4 GHz.
10582 0x5 = 5.15625 GHz.
10583 0x6 = 5.65 GHz.
10584 0x7 = 6.25 GHz.
10585
10586 All other values in this field are reserved. */
10587 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10588 based on the PLL clock frequency as follows:
10589 0x0 = 2.5 GHz.
10590 0x1 = 3.125 GHz.
10591 0x3 = 4 GHz.
10592 0x5 = 5.15625 GHz.
10593 0x6 = 5.65 GHz.
10594 0x7 = 6.25 GHz.
10595
10596 All other values in this field are reserved. */
10597 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10598 0x0 = 2.5 GHz.
10599 0x1 = 3.125 GHz.
10600 0x6 = 4 GHz.
10601 0x7 = 5.15625 GHz.
10602
10603 All other values in this field are reserved. */
10604 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10605 0x0 = 500 uA.
10606 0x1 = 1000 uA.
10607 0x2 = 250 uA.
10608 0x3 = 330 uA. */
10609 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10610 0x0 = 500 uA.
10611 0x1 = 1000 uA.
10612 0x2 = 250 uA.
10613 0x3 = 330 uA. */
10614 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10615 Bit 13 controls enable for lane 0.
10616 Bit 14 controls enable for lane 1. */
10617 uint64_t reserved_15_63 : 49;
10618 #endif /* Word 0 - End */
10619 } s;
10620 /* struct bdk_gserx_slicex_kx_mode_s cn; */
10621 };
10622 typedef union bdk_gserx_slicex_kx_mode bdk_gserx_slicex_kx_mode_t;
10623
10624 static inline uint64_t BDK_GSERX_SLICEX_KX_MODE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_KX_MODE(unsigned long a,unsigned long b)10625 static inline uint64_t BDK_GSERX_SLICEX_KX_MODE(unsigned long a, unsigned long b)
10626 {
10627 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
10628 return 0x87e090460240ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
10629 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
10630 return 0x87e090460240ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
10631 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
10632 return 0x87e090460240ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
10633 __bdk_csr_fatal("GSERX_SLICEX_KX_MODE", 2, a, b, 0, 0);
10634 }
10635
10636 #define typedef_BDK_GSERX_SLICEX_KX_MODE(a,b) bdk_gserx_slicex_kx_mode_t
10637 #define bustype_BDK_GSERX_SLICEX_KX_MODE(a,b) BDK_CSR_TYPE_RSL
10638 #define basename_BDK_GSERX_SLICEX_KX_MODE(a,b) "GSERX_SLICEX_KX_MODE"
10639 #define device_bar_BDK_GSERX_SLICEX_KX_MODE(a,b) 0x0 /* PF_BAR0 */
10640 #define busnum_BDK_GSERX_SLICEX_KX_MODE(a,b) (a)
10641 #define arguments_BDK_GSERX_SLICEX_KX_MODE(a,b) (a),(b),-1,-1
10642
10643 /**
10644 * Register (RSL) gser#_slice#_pcie1_mode
10645 *
10646 * GSER Slice PCIE1 MODE Register
10647 * These registers are for diagnostic use only.
10648 * These registers are reset by hardware only during chip cold reset.
10649 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
10650 */
10651 union bdk_gserx_slicex_pcie1_mode
10652 {
10653 uint64_t u;
10654 struct bdk_gserx_slicex_pcie1_mode_s
10655 {
10656 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10657 uint64_t reserved_15_63 : 49;
10658 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10659 Bit 13 controls enable for lane 0.
10660 Bit 14 controls enable for lane 1. */
10661 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10662 0x0 = 500 uA.
10663 0x1 = 1000 uA.
10664 0x2 = 250 uA.
10665 0x3 = 330 uA. */
10666 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10667 0x0 = 500 uA.
10668 0x1 = 1000 uA.
10669 0x2 = 250 uA.
10670 0x3 = 330 uA. */
10671 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10672 0x0 = 2.5 GHz.
10673 0x1 = 3.125 GHz, or SATA mode.
10674 0x6 = 4 GHz.
10675 0x7 = 5.15625 GHz.
10676
10677 All other values in this field are reserved. */
10678 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10679 based on the PLL clock frequency as follows:
10680 0x0 = 2.5 GHz.
10681 0x1 = 3.125 GHz, or SATA mode.
10682 0x3 = 4 GHz.
10683 0x5 = 5.15625 GHz.
10684 0x6 = 5.65 GHz.
10685 0x7 = 6.25 GHz.
10686
10687 All other values in this field are reserved. */
10688 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10689 based on the PLL clock frequency as follows:
10690 0x0 = 2.5 GHz.
10691 0x1 = 3.125 GHz, or SATA mode.
10692 0x3 = 4 GHz.
10693 0x5 = 5.15625 GHz.
10694 0x6 = 5.65 GHz.
10695 0x7 = 6.25 GHz.
10696
10697 All other values in this field are reserved.
10698
10699 In SATA Mode program RX_SDLL_BWSEL = 0x1. */
10700 #else /* Word 0 - Little Endian */
10701 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10702 based on the PLL clock frequency as follows:
10703 0x0 = 2.5 GHz.
10704 0x1 = 3.125 GHz, or SATA mode.
10705 0x3 = 4 GHz.
10706 0x5 = 5.15625 GHz.
10707 0x6 = 5.65 GHz.
10708 0x7 = 6.25 GHz.
10709
10710 All other values in this field are reserved.
10711
10712 In SATA Mode program RX_SDLL_BWSEL = 0x1. */
10713 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10714 based on the PLL clock frequency as follows:
10715 0x0 = 2.5 GHz.
10716 0x1 = 3.125 GHz, or SATA mode.
10717 0x3 = 4 GHz.
10718 0x5 = 5.15625 GHz.
10719 0x6 = 5.65 GHz.
10720 0x7 = 6.25 GHz.
10721
10722 All other values in this field are reserved. */
10723 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10724 0x0 = 2.5 GHz.
10725 0x1 = 3.125 GHz, or SATA mode.
10726 0x6 = 4 GHz.
10727 0x7 = 5.15625 GHz.
10728
10729 All other values in this field are reserved. */
10730 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10731 0x0 = 500 uA.
10732 0x1 = 1000 uA.
10733 0x2 = 250 uA.
10734 0x3 = 330 uA. */
10735 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10736 0x0 = 500 uA.
10737 0x1 = 1000 uA.
10738 0x2 = 250 uA.
10739 0x3 = 330 uA. */
10740 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10741 Bit 13 controls enable for lane 0.
10742 Bit 14 controls enable for lane 1. */
10743 uint64_t reserved_15_63 : 49;
10744 #endif /* Word 0 - End */
10745 } s;
10746 /* struct bdk_gserx_slicex_pcie1_mode_s cn81xx; */
10747 struct bdk_gserx_slicex_pcie1_mode_cn88xx
10748 {
10749 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10750 uint64_t reserved_15_63 : 49;
10751 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10752 Bit 13 controls enable for lane 0.
10753 Bit 14 controls enable for lane 1. */
10754 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10755 0x0 = 500 uA.
10756 0x1 = 1000 uA.
10757 0x2 = 250 uA.
10758 0x3 = 330 uA. */
10759 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10760 0x0 = 500 uA.
10761 0x1 = 1000 uA.
10762 0x2 = 250 uA.
10763 0x3 = 330 uA. */
10764 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10765 0x0 = 2.5 GHz.
10766 0x1 = 3.125 GHz, or SATA mode.
10767 0x6 = 4 GHz.
10768 0x7 = 5.15625 GHz.
10769
10770 All other values in this field are reserved. */
10771 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10772 based on the PLL clock frequency as follows:
10773 0x0 = 2.5 GHz.
10774 0x1 = 3.125 GHz, or SATA mode.
10775 0x3 = 4 GHz.
10776 0x5 = 5.15625 GHz.
10777 0x6 = 5.65 GHz.
10778 0x7 = 6.25 GHz.
10779
10780 All other values in this field are reserved. */
10781 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10782 based on the PLL clock frequency as follows:
10783 0x0 = 2.5 GHz.
10784 0x1 = 3.125 GHz, or SATA mode.
10785 0x3 = 4 GHz.
10786 0x5 = 5.15625 GHz.
10787 0x6 = 5.65 GHz.
10788 0x7 = 6.25 GHz.
10789
10790 All other values in this field are reserved. */
10791 #else /* Word 0 - Little Endian */
10792 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10793 based on the PLL clock frequency as follows:
10794 0x0 = 2.5 GHz.
10795 0x1 = 3.125 GHz, or SATA mode.
10796 0x3 = 4 GHz.
10797 0x5 = 5.15625 GHz.
10798 0x6 = 5.65 GHz.
10799 0x7 = 6.25 GHz.
10800
10801 All other values in this field are reserved. */
10802 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10803 based on the PLL clock frequency as follows:
10804 0x0 = 2.5 GHz.
10805 0x1 = 3.125 GHz, or SATA mode.
10806 0x3 = 4 GHz.
10807 0x5 = 5.15625 GHz.
10808 0x6 = 5.65 GHz.
10809 0x7 = 6.25 GHz.
10810
10811 All other values in this field are reserved. */
10812 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10813 0x0 = 2.5 GHz.
10814 0x1 = 3.125 GHz, or SATA mode.
10815 0x6 = 4 GHz.
10816 0x7 = 5.15625 GHz.
10817
10818 All other values in this field are reserved. */
10819 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10820 0x0 = 500 uA.
10821 0x1 = 1000 uA.
10822 0x2 = 250 uA.
10823 0x3 = 330 uA. */
10824 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10825 0x0 = 500 uA.
10826 0x1 = 1000 uA.
10827 0x2 = 250 uA.
10828 0x3 = 330 uA. */
10829 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10830 Bit 13 controls enable for lane 0.
10831 Bit 14 controls enable for lane 1. */
10832 uint64_t reserved_15_63 : 49;
10833 #endif /* Word 0 - End */
10834 } cn88xx;
10835 /* struct bdk_gserx_slicex_pcie1_mode_cn88xx cn83xx; */
10836 };
10837 typedef union bdk_gserx_slicex_pcie1_mode bdk_gserx_slicex_pcie1_mode_t;
10838
10839 static inline uint64_t BDK_GSERX_SLICEX_PCIE1_MODE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_PCIE1_MODE(unsigned long a,unsigned long b)10840 static inline uint64_t BDK_GSERX_SLICEX_PCIE1_MODE(unsigned long a, unsigned long b)
10841 {
10842 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
10843 return 0x87e090460228ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
10844 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
10845 return 0x87e090460228ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
10846 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
10847 return 0x87e090460228ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
10848 __bdk_csr_fatal("GSERX_SLICEX_PCIE1_MODE", 2, a, b, 0, 0);
10849 }
10850
10851 #define typedef_BDK_GSERX_SLICEX_PCIE1_MODE(a,b) bdk_gserx_slicex_pcie1_mode_t
10852 #define bustype_BDK_GSERX_SLICEX_PCIE1_MODE(a,b) BDK_CSR_TYPE_RSL
10853 #define basename_BDK_GSERX_SLICEX_PCIE1_MODE(a,b) "GSERX_SLICEX_PCIE1_MODE"
10854 #define device_bar_BDK_GSERX_SLICEX_PCIE1_MODE(a,b) 0x0 /* PF_BAR0 */
10855 #define busnum_BDK_GSERX_SLICEX_PCIE1_MODE(a,b) (a)
10856 #define arguments_BDK_GSERX_SLICEX_PCIE1_MODE(a,b) (a),(b),-1,-1
10857
10858 /**
10859 * Register (RSL) gser#_slice#_pcie2_mode
10860 *
10861 * GSER Slice PCIE2 MODE Register
10862 * These registers are for diagnostic use only.
10863 * These registers are reset by hardware only during chip cold reset.
10864 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
10865 */
10866 union bdk_gserx_slicex_pcie2_mode
10867 {
10868 uint64_t u;
10869 struct bdk_gserx_slicex_pcie2_mode_s
10870 {
10871 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10872 uint64_t reserved_15_63 : 49;
10873 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10874 Bit 13 controls enable for lane 0.
10875 Bit 14 controls enable for lane 1. */
10876 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10877 0x0 = 500 uA.
10878 0x1 = 1000 uA.
10879 0x2 = 250 uA.
10880 0x3 = 330 uA. */
10881 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10882 0x0 = 500 uA.
10883 0x1 = 1000 uA.
10884 0x2 = 250 uA.
10885 0x3 = 330 uA. */
10886 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10887 0x0 = 2.5 GHz.
10888 0x1 = 3.125 GHz, or SATA mode.
10889 0x6 = 4 GHz.
10890 0x7 = 5.15625 GHz.
10891
10892 All other values in this field are reserved. */
10893 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10894 based on the PLL clock frequency as follows:
10895 0x0 = 2.5 GHz.
10896 0x1 = 3.125 GHz, or SATA mode.
10897 0x3 = 4 GHz.
10898 0x5 = 5.15625 GHz.
10899 0x6 = 5.65 GHz.
10900 0x7 = 6.25 GHz.
10901
10902 All other values in this field are reserved. */
10903 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10904 based on the PLL clock frequency as follows:
10905 0x0 = 2.5 GHz.
10906 0x1 = 3.125 GHz, or SATA mode.
10907 0x3 = 4 GHz.
10908 0x5 = 5.15625 GHz.
10909 0x6 = 5.65 GHz.
10910 0x7 = 6.25 GHz.
10911
10912 All other values in this field are reserved.
10913
10914 In SATA Mode program RX_SDLL_BWSEL = 0x1. */
10915 #else /* Word 0 - Little Endian */
10916 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10917 based on the PLL clock frequency as follows:
10918 0x0 = 2.5 GHz.
10919 0x1 = 3.125 GHz, or SATA mode.
10920 0x3 = 4 GHz.
10921 0x5 = 5.15625 GHz.
10922 0x6 = 5.65 GHz.
10923 0x7 = 6.25 GHz.
10924
10925 All other values in this field are reserved.
10926
10927 In SATA Mode program RX_SDLL_BWSEL = 0x1. */
10928 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10929 based on the PLL clock frequency as follows:
10930 0x0 = 2.5 GHz.
10931 0x1 = 3.125 GHz, or SATA mode.
10932 0x3 = 4 GHz.
10933 0x5 = 5.15625 GHz.
10934 0x6 = 5.65 GHz.
10935 0x7 = 6.25 GHz.
10936
10937 All other values in this field are reserved. */
10938 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10939 0x0 = 2.5 GHz.
10940 0x1 = 3.125 GHz, or SATA mode.
10941 0x6 = 4 GHz.
10942 0x7 = 5.15625 GHz.
10943
10944 All other values in this field are reserved. */
10945 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10946 0x0 = 500 uA.
10947 0x1 = 1000 uA.
10948 0x2 = 250 uA.
10949 0x3 = 330 uA. */
10950 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10951 0x0 = 500 uA.
10952 0x1 = 1000 uA.
10953 0x2 = 250 uA.
10954 0x3 = 330 uA. */
10955 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10956 Bit 13 controls enable for lane 0.
10957 Bit 14 controls enable for lane 1. */
10958 uint64_t reserved_15_63 : 49;
10959 #endif /* Word 0 - End */
10960 } s;
10961 /* struct bdk_gserx_slicex_pcie2_mode_s cn81xx; */
10962 /* struct bdk_gserx_slicex_pcie2_mode_s cn88xx; */
10963 struct bdk_gserx_slicex_pcie2_mode_cn83xx
10964 {
10965 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10966 uint64_t reserved_15_63 : 49;
10967 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
10968 Bit 13 controls enable for lane 0.
10969 Bit 14 controls enable for lane 1. */
10970 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
10971 0x0 = 500 uA.
10972 0x1 = 1000 uA.
10973 0x2 = 250 uA.
10974 0x3 = 330 uA. */
10975 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
10976 0x0 = 500 uA.
10977 0x1 = 1000 uA.
10978 0x2 = 250 uA.
10979 0x3 = 330 uA. */
10980 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
10981 0x0 = 2.5 GHz.
10982 0x1 = 3.125 GHz, or SATA mode.
10983 0x6 = 4 GHz.
10984 0x7 = 5.15625 GHz.
10985
10986 All other values in this field are reserved. */
10987 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
10988 based on the PLL clock frequency as follows:
10989 0x0 = 2.5 GHz.
10990 0x1 = 3.125 GHz, or SATA mode.
10991 0x3 = 4 GHz.
10992 0x5 = 5.15625 GHz.
10993 0x6 = 5.65 GHz.
10994 0x7 = 6.25 GHz.
10995
10996 All other values in this field are reserved. */
10997 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
10998 based on the PLL clock frequency as follows:
10999 0x0 = 2.5 GHz.
11000 0x1 = 3.125 GHz, or SATA mode.
11001 0x3 = 4 GHz.
11002 0x5 = 5.15625 GHz.
11003 0x6 = 5.65 GHz.
11004 0x7 = 6.25 GHz.
11005
11006 All other values in this field are reserved. */
11007 #else /* Word 0 - Little Endian */
11008 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
11009 based on the PLL clock frequency as follows:
11010 0x0 = 2.5 GHz.
11011 0x1 = 3.125 GHz, or SATA mode.
11012 0x3 = 4 GHz.
11013 0x5 = 5.15625 GHz.
11014 0x6 = 5.65 GHz.
11015 0x7 = 6.25 GHz.
11016
11017 All other values in this field are reserved. */
11018 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
11019 based on the PLL clock frequency as follows:
11020 0x0 = 2.5 GHz.
11021 0x1 = 3.125 GHz, or SATA mode.
11022 0x3 = 4 GHz.
11023 0x5 = 5.15625 GHz.
11024 0x6 = 5.65 GHz.
11025 0x7 = 6.25 GHz.
11026
11027 All other values in this field are reserved. */
11028 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
11029 0x0 = 2.5 GHz.
11030 0x1 = 3.125 GHz, or SATA mode.
11031 0x6 = 4 GHz.
11032 0x7 = 5.15625 GHz.
11033
11034 All other values in this field are reserved. */
11035 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
11036 0x0 = 500 uA.
11037 0x1 = 1000 uA.
11038 0x2 = 250 uA.
11039 0x3 = 330 uA. */
11040 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
11041 0x0 = 500 uA.
11042 0x1 = 1000 uA.
11043 0x2 = 250 uA.
11044 0x3 = 330 uA. */
11045 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
11046 Bit 13 controls enable for lane 0.
11047 Bit 14 controls enable for lane 1. */
11048 uint64_t reserved_15_63 : 49;
11049 #endif /* Word 0 - End */
11050 } cn83xx;
11051 };
11052 typedef union bdk_gserx_slicex_pcie2_mode bdk_gserx_slicex_pcie2_mode_t;
11053
11054 static inline uint64_t BDK_GSERX_SLICEX_PCIE2_MODE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_PCIE2_MODE(unsigned long a,unsigned long b)11055 static inline uint64_t BDK_GSERX_SLICEX_PCIE2_MODE(unsigned long a, unsigned long b)
11056 {
11057 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
11058 return 0x87e090460230ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
11059 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
11060 return 0x87e090460230ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
11061 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
11062 return 0x87e090460230ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
11063 __bdk_csr_fatal("GSERX_SLICEX_PCIE2_MODE", 2, a, b, 0, 0);
11064 }
11065
11066 #define typedef_BDK_GSERX_SLICEX_PCIE2_MODE(a,b) bdk_gserx_slicex_pcie2_mode_t
11067 #define bustype_BDK_GSERX_SLICEX_PCIE2_MODE(a,b) BDK_CSR_TYPE_RSL
11068 #define basename_BDK_GSERX_SLICEX_PCIE2_MODE(a,b) "GSERX_SLICEX_PCIE2_MODE"
11069 #define device_bar_BDK_GSERX_SLICEX_PCIE2_MODE(a,b) 0x0 /* PF_BAR0 */
11070 #define busnum_BDK_GSERX_SLICEX_PCIE2_MODE(a,b) (a)
11071 #define arguments_BDK_GSERX_SLICEX_PCIE2_MODE(a,b) (a),(b),-1,-1
11072
11073 /**
11074 * Register (RSL) gser#_slice#_pcie3_mode
11075 *
11076 * GSER Slice PCIE3 MODE Register
11077 * These registers are for diagnostic use only.
11078 * These registers are reset by hardware only during chip cold reset.
11079 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
11080 */
11081 union bdk_gserx_slicex_pcie3_mode
11082 {
11083 uint64_t u;
11084 struct bdk_gserx_slicex_pcie3_mode_s
11085 {
11086 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11087 uint64_t reserved_15_63 : 49;
11088 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
11089 Bit 13 controls enable for lane 0.
11090 Bit 14 controls enable for lane 1. */
11091 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
11092 0x0 = 500 uA.
11093 0x1 = 1000 uA.
11094 0x2 = 250 uA.
11095 0x3 = 330 uA. */
11096 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
11097 0x0 = 500 uA.
11098 0x1 = 1000 uA.
11099 0x2 = 250 uA.
11100 0x3 = 330 uA. */
11101 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
11102 0x0 = 2.5 GHz.
11103 0x1 = 3.125 GHz, or SATA mode.
11104 0x6 = 4 GHz.
11105 0x7 = 5.15625 GHz.
11106
11107 All other values in this field are reserved. */
11108 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
11109 based on the PLL clock frequency as follows:
11110 0x0 = 2.5 GHz.
11111 0x1 = 3.125 GHz, or SATA mode.
11112 0x3 = 4 GHz.
11113 0x5 = 5.15625 GHz.
11114 0x6 = 5.65 GHz.
11115 0x7 = 6.25 GHz.
11116
11117 All other values in this field are reserved. */
11118 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
11119 based on the PLL clock frequency as follows:
11120 0x0 = 2.5 GHz.
11121 0x1 = 3.125 GHz, or SATA mode.
11122 0x3 = 4 GHz.
11123 0x5 = 5.15625 GHz.
11124 0x6 = 5.65 GHz.
11125 0x7 = 6.25 GHz.
11126
11127 All other values in this field are reserved. */
11128 #else /* Word 0 - Little Endian */
11129 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
11130 based on the PLL clock frequency as follows:
11131 0x0 = 2.5 GHz.
11132 0x1 = 3.125 GHz, or SATA mode.
11133 0x3 = 4 GHz.
11134 0x5 = 5.15625 GHz.
11135 0x6 = 5.65 GHz.
11136 0x7 = 6.25 GHz.
11137
11138 All other values in this field are reserved. */
11139 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
11140 based on the PLL clock frequency as follows:
11141 0x0 = 2.5 GHz.
11142 0x1 = 3.125 GHz, or SATA mode.
11143 0x3 = 4 GHz.
11144 0x5 = 5.15625 GHz.
11145 0x6 = 5.65 GHz.
11146 0x7 = 6.25 GHz.
11147
11148 All other values in this field are reserved. */
11149 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
11150 0x0 = 2.5 GHz.
11151 0x1 = 3.125 GHz, or SATA mode.
11152 0x6 = 4 GHz.
11153 0x7 = 5.15625 GHz.
11154
11155 All other values in this field are reserved. */
11156 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
11157 0x0 = 500 uA.
11158 0x1 = 1000 uA.
11159 0x2 = 250 uA.
11160 0x3 = 330 uA. */
11161 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
11162 0x0 = 500 uA.
11163 0x1 = 1000 uA.
11164 0x2 = 250 uA.
11165 0x3 = 330 uA. */
11166 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
11167 Bit 13 controls enable for lane 0.
11168 Bit 14 controls enable for lane 1. */
11169 uint64_t reserved_15_63 : 49;
11170 #endif /* Word 0 - End */
11171 } s;
11172 /* struct bdk_gserx_slicex_pcie3_mode_s cn81xx; */
11173 struct bdk_gserx_slicex_pcie3_mode_cn88xx
11174 {
11175 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11176 uint64_t reserved_15_63 : 49;
11177 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
11178 Bit 13 controls enable for lane 0.
11179 Bit 14 controls enable for lane 1. */
11180 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
11181 0x0 = 500 uA.
11182 0x1 = 1000 uA.
11183 0x2 = 250 uA.
11184 0x3 = 330 uA. */
11185 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
11186 0x0 = 500 uA.
11187 0x1 = 1000 uA.
11188 0x2 = 250 uA.
11189 0x3 = 330 uA. */
11190 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
11191 0x0 = 2.5 GHz.
11192 0x1 = 3.125 GHz, or SATA mode.
11193 0x6 = 4 GHz.
11194 0x7 = 5.15625 GHz.
11195
11196 All other values in this field are reserved. */
11197 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
11198 based on the PLL clock frequency as follows:
11199 0x0 = 2.5 GHz.
11200 0x1 = 3.125 GHz, or SATA mode.
11201 0x3 = 4 GHz.
11202 0x5 = 5.15625 GHz.
11203 0x6 = 5.65 GHz.
11204 0x7 = 6.25 GHz.
11205
11206 All other values in this field are reserved. */
11207 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
11208 based on the PLL clock frequency as follows:
11209 0x0 = 2.5 GHz.
11210 0x1 = 3.125 GHz, or SATA mode.
11211 0x3 = 4 GHz.
11212 0x5 = 5.15625 GHz.
11213 0x6 = 5.65 GHz.
11214 0x7 = 6.25 GHz.
11215
11216 All other values in this field are reserved.
11217
11218 In SATA Mode program RX_SDLL_BWSEL = 0x1. */
11219 #else /* Word 0 - Little Endian */
11220 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
11221 based on the PLL clock frequency as follows:
11222 0x0 = 2.5 GHz.
11223 0x1 = 3.125 GHz, or SATA mode.
11224 0x3 = 4 GHz.
11225 0x5 = 5.15625 GHz.
11226 0x6 = 5.65 GHz.
11227 0x7 = 6.25 GHz.
11228
11229 All other values in this field are reserved.
11230
11231 In SATA Mode program RX_SDLL_BWSEL = 0x1. */
11232 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
11233 based on the PLL clock frequency as follows:
11234 0x0 = 2.5 GHz.
11235 0x1 = 3.125 GHz, or SATA mode.
11236 0x3 = 4 GHz.
11237 0x5 = 5.15625 GHz.
11238 0x6 = 5.65 GHz.
11239 0x7 = 6.25 GHz.
11240
11241 All other values in this field are reserved. */
11242 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
11243 0x0 = 2.5 GHz.
11244 0x1 = 3.125 GHz, or SATA mode.
11245 0x6 = 4 GHz.
11246 0x7 = 5.15625 GHz.
11247
11248 All other values in this field are reserved. */
11249 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
11250 0x0 = 500 uA.
11251 0x1 = 1000 uA.
11252 0x2 = 250 uA.
11253 0x3 = 330 uA. */
11254 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
11255 0x0 = 500 uA.
11256 0x1 = 1000 uA.
11257 0x2 = 250 uA.
11258 0x3 = 330 uA. */
11259 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
11260 Bit 13 controls enable for lane 0.
11261 Bit 14 controls enable for lane 1. */
11262 uint64_t reserved_15_63 : 49;
11263 #endif /* Word 0 - End */
11264 } cn88xx;
11265 /* struct bdk_gserx_slicex_pcie3_mode_s cn83xx; */
11266 };
11267 typedef union bdk_gserx_slicex_pcie3_mode bdk_gserx_slicex_pcie3_mode_t;
11268
11269 static inline uint64_t BDK_GSERX_SLICEX_PCIE3_MODE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_PCIE3_MODE(unsigned long a,unsigned long b)11270 static inline uint64_t BDK_GSERX_SLICEX_PCIE3_MODE(unsigned long a, unsigned long b)
11271 {
11272 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
11273 return 0x87e090460238ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
11274 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
11275 return 0x87e090460238ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
11276 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
11277 return 0x87e090460238ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
11278 __bdk_csr_fatal("GSERX_SLICEX_PCIE3_MODE", 2, a, b, 0, 0);
11279 }
11280
11281 #define typedef_BDK_GSERX_SLICEX_PCIE3_MODE(a,b) bdk_gserx_slicex_pcie3_mode_t
11282 #define bustype_BDK_GSERX_SLICEX_PCIE3_MODE(a,b) BDK_CSR_TYPE_RSL
11283 #define basename_BDK_GSERX_SLICEX_PCIE3_MODE(a,b) "GSERX_SLICEX_PCIE3_MODE"
11284 #define device_bar_BDK_GSERX_SLICEX_PCIE3_MODE(a,b) 0x0 /* PF_BAR0 */
11285 #define busnum_BDK_GSERX_SLICEX_PCIE3_MODE(a,b) (a)
11286 #define arguments_BDK_GSERX_SLICEX_PCIE3_MODE(a,b) (a),(b),-1,-1
11287
11288 /**
11289 * Register (RSL) gser#_slice#_qsgmii_mode
11290 *
11291 * GSER Slice QSGMII MODE Register
11292 * These registers are for diagnostic use only.
11293 * These registers are reset by hardware only during chip cold reset.
11294 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
11295 */
11296 union bdk_gserx_slicex_qsgmii_mode
11297 {
11298 uint64_t u;
11299 struct bdk_gserx_slicex_qsgmii_mode_s
11300 {
11301 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11302 uint64_t reserved_15_63 : 49;
11303 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
11304 Bit 13 controls enable for lane 0.
11305 Bit 14 controls enable for lane 1. */
11306 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
11307 0x0 = 500 uA.
11308 0x1 = 1000 uA.
11309 0x2 = 250 uA.
11310 0x3 = 330 uA. */
11311 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
11312 0x0 = 500 uA.
11313 0x1 = 1000 uA.
11314 0x2 = 250 uA.
11315 0x3 = 330 uA. */
11316 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
11317 0x0 = 2.5 GHz.
11318 0x1 = 3.125 GHz.
11319 0x6 = 4 GHz.
11320 0x7 = 5.15625 GHz.
11321
11322 All other values in this field are reserved. */
11323 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
11324 based on the PLL clock frequency as follows:
11325 0x0 = 2.5 GHz.
11326 0x1 = 3.125 GHz.
11327 0x3 = 4 GHz.
11328 0x5 = 5.15625 GHz.
11329 0x6 = 5.65 GHz.
11330 0x7 = 6.25 GHz.
11331
11332 All other values in this field are reserved. */
11333 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
11334 based on the PLL clock frequency as follows:
11335 0x0 = 2.5 GHz.
11336 0x1 = 3.125 GHz.
11337 0x3 = 4 GHz.
11338 0x5 = 5.15625 GHz.
11339 0x6 = 5.65 GHz.
11340 0x7 = 6.25 GHz.
11341
11342 All other values in this field are reserved. */
11343 #else /* Word 0 - Little Endian */
11344 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
11345 based on the PLL clock frequency as follows:
11346 0x0 = 2.5 GHz.
11347 0x1 = 3.125 GHz.
11348 0x3 = 4 GHz.
11349 0x5 = 5.15625 GHz.
11350 0x6 = 5.65 GHz.
11351 0x7 = 6.25 GHz.
11352
11353 All other values in this field are reserved. */
11354 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
11355 based on the PLL clock frequency as follows:
11356 0x0 = 2.5 GHz.
11357 0x1 = 3.125 GHz.
11358 0x3 = 4 GHz.
11359 0x5 = 5.15625 GHz.
11360 0x6 = 5.65 GHz.
11361 0x7 = 6.25 GHz.
11362
11363 All other values in this field are reserved. */
11364 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
11365 0x0 = 2.5 GHz.
11366 0x1 = 3.125 GHz.
11367 0x6 = 4 GHz.
11368 0x7 = 5.15625 GHz.
11369
11370 All other values in this field are reserved. */
11371 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
11372 0x0 = 500 uA.
11373 0x1 = 1000 uA.
11374 0x2 = 250 uA.
11375 0x3 = 330 uA. */
11376 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
11377 0x0 = 500 uA.
11378 0x1 = 1000 uA.
11379 0x2 = 250 uA.
11380 0x3 = 330 uA. */
11381 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
11382 Bit 13 controls enable for lane 0.
11383 Bit 14 controls enable for lane 1. */
11384 uint64_t reserved_15_63 : 49;
11385 #endif /* Word 0 - End */
11386 } s;
11387 /* struct bdk_gserx_slicex_qsgmii_mode_s cn; */
11388 };
11389 typedef union bdk_gserx_slicex_qsgmii_mode bdk_gserx_slicex_qsgmii_mode_t;
11390
11391 static inline uint64_t BDK_GSERX_SLICEX_QSGMII_MODE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_QSGMII_MODE(unsigned long a,unsigned long b)11392 static inline uint64_t BDK_GSERX_SLICEX_QSGMII_MODE(unsigned long a, unsigned long b)
11393 {
11394 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
11395 return 0x87e090460260ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
11396 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
11397 return 0x87e090460260ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
11398 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
11399 return 0x87e090460260ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
11400 __bdk_csr_fatal("GSERX_SLICEX_QSGMII_MODE", 2, a, b, 0, 0);
11401 }
11402
11403 #define typedef_BDK_GSERX_SLICEX_QSGMII_MODE(a,b) bdk_gserx_slicex_qsgmii_mode_t
11404 #define bustype_BDK_GSERX_SLICEX_QSGMII_MODE(a,b) BDK_CSR_TYPE_RSL
11405 #define basename_BDK_GSERX_SLICEX_QSGMII_MODE(a,b) "GSERX_SLICEX_QSGMII_MODE"
11406 #define device_bar_BDK_GSERX_SLICEX_QSGMII_MODE(a,b) 0x0 /* PF_BAR0 */
11407 #define busnum_BDK_GSERX_SLICEX_QSGMII_MODE(a,b) (a)
11408 #define arguments_BDK_GSERX_SLICEX_QSGMII_MODE(a,b) (a),(b),-1,-1
11409
11410 /**
11411 * Register (RSL) gser#_slice#_rx_ldll_ctrl
11412 *
11413 * GSER Slice RX LDLL Register
11414 * These registers are for diagnostic use only.
11415 * These registers are reset by hardware only during chip cold reset.
11416 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
11417 */
11418 union bdk_gserx_slicex_rx_ldll_ctrl
11419 {
11420 uint64_t u;
11421 struct bdk_gserx_slicex_rx_ldll_ctrl_s
11422 {
11423 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11424 uint64_t reserved_8_63 : 56;
11425 uint64_t pcs_sds_rx_ldll_tune : 3; /**< [ 7: 5](R/W/H) Tuning bits for the regulator and loop filter.
11426 Bit 7 controls the initial value of the regulator output,
11427 0 for 0.9V and 1 for 0.925V.
11428 Bits 6:5 are connected to the loop filter, to reduce
11429 its corner frequency (for testing purposes).
11430
11431 This parameter is for debugging purposes and should not
11432 be written in normal operation. */
11433 uint64_t pcs_sds_rx_ldll_swsel : 4; /**< [ 4: 1](R/W/H) DMON control, selects which signal is passed to the output
11434 of DMON:
11435 0x8 = vdda_int
11436 0x4 = pi clock (output of the PI)
11437 0x2 = dllout[1] (second output clock phase, out of 4 phases,
11438 of the Lane DLL)
11439 0x1 = dllout[0] (first output clock phase, out of 4 phases,
11440 of the Lane DLL). Ensure that
11441 GSER()_SLICE_RX_SDLL_CTRL[PCS_SDS_RX_SDLL_SWSEL]=0x0 during
11442 this test.
11443
11444 This parameter is for debugging purposes and should not
11445 be written in normal operation. */
11446 uint64_t reserved_0 : 1;
11447 #else /* Word 0 - Little Endian */
11448 uint64_t reserved_0 : 1;
11449 uint64_t pcs_sds_rx_ldll_swsel : 4; /**< [ 4: 1](R/W/H) DMON control, selects which signal is passed to the output
11450 of DMON:
11451 0x8 = vdda_int
11452 0x4 = pi clock (output of the PI)
11453 0x2 = dllout[1] (second output clock phase, out of 4 phases,
11454 of the Lane DLL)
11455 0x1 = dllout[0] (first output clock phase, out of 4 phases,
11456 of the Lane DLL). Ensure that
11457 GSER()_SLICE_RX_SDLL_CTRL[PCS_SDS_RX_SDLL_SWSEL]=0x0 during
11458 this test.
11459
11460 This parameter is for debugging purposes and should not
11461 be written in normal operation. */
11462 uint64_t pcs_sds_rx_ldll_tune : 3; /**< [ 7: 5](R/W/H) Tuning bits for the regulator and loop filter.
11463 Bit 7 controls the initial value of the regulator output,
11464 0 for 0.9V and 1 for 0.925V.
11465 Bits 6:5 are connected to the loop filter, to reduce
11466 its corner frequency (for testing purposes).
11467
11468 This parameter is for debugging purposes and should not
11469 be written in normal operation. */
11470 uint64_t reserved_8_63 : 56;
11471 #endif /* Word 0 - End */
11472 } s;
11473 /* struct bdk_gserx_slicex_rx_ldll_ctrl_s cn; */
11474 };
11475 typedef union bdk_gserx_slicex_rx_ldll_ctrl bdk_gserx_slicex_rx_ldll_ctrl_t;
11476
11477 static inline uint64_t BDK_GSERX_SLICEX_RX_LDLL_CTRL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_RX_LDLL_CTRL(unsigned long a,unsigned long b)11478 static inline uint64_t BDK_GSERX_SLICEX_RX_LDLL_CTRL(unsigned long a, unsigned long b)
11479 {
11480 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
11481 return 0x87e090460218ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
11482 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
11483 return 0x87e090460218ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
11484 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
11485 return 0x87e090460218ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
11486 __bdk_csr_fatal("GSERX_SLICEX_RX_LDLL_CTRL", 2, a, b, 0, 0);
11487 }
11488
11489 #define typedef_BDK_GSERX_SLICEX_RX_LDLL_CTRL(a,b) bdk_gserx_slicex_rx_ldll_ctrl_t
11490 #define bustype_BDK_GSERX_SLICEX_RX_LDLL_CTRL(a,b) BDK_CSR_TYPE_RSL
11491 #define basename_BDK_GSERX_SLICEX_RX_LDLL_CTRL(a,b) "GSERX_SLICEX_RX_LDLL_CTRL"
11492 #define device_bar_BDK_GSERX_SLICEX_RX_LDLL_CTRL(a,b) 0x0 /* PF_BAR0 */
11493 #define busnum_BDK_GSERX_SLICEX_RX_LDLL_CTRL(a,b) (a)
11494 #define arguments_BDK_GSERX_SLICEX_RX_LDLL_CTRL(a,b) (a),(b),-1,-1
11495
11496 /**
11497 * Register (RSL) gser#_slice#_rx_sdll_ctrl
11498 *
11499 * GSER Slice RX SDLL Register
11500 * These registers are for diagnostic use only.
11501 * These registers are reset by hardware only during chip cold reset.
11502 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
11503 */
11504 union bdk_gserx_slicex_rx_sdll_ctrl
11505 {
11506 uint64_t u;
11507 struct bdk_gserx_slicex_rx_sdll_ctrl_s
11508 {
11509 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11510 uint64_t reserved_16_63 : 48;
11511 uint64_t pcs_sds_oob_clk_ctrl : 2; /**< [ 15: 14](R/W/H) OOB clock oscillator output frequency selection:
11512 0x0 = 506 MHz (min) 682 MHz (typ) 782 MHz (max).
11513 0x1 = 439 MHz (min) 554 MHz (typ) 595 MHz (max).
11514 0x2 = 379 MHz (min) 453 MHz (typ) 482 MHz (max).
11515 0x3 = 303 MHz (min) 378 MHz (typ) 414 MHz (max).
11516
11517 This parameter is for debugging purposes and should not
11518 be written in normal operation. */
11519 uint64_t reserved_7_13 : 7;
11520 uint64_t pcs_sds_rx_sdll_tune : 3; /**< [ 6: 4](R/W) Tuning bits for the regulator and the loop filter. */
11521 uint64_t pcs_sds_rx_sdll_swsel : 4; /**< [ 3: 0](R/W) DMON control; selects which signal is passed to the output
11522 of DMON.
11523 0x1 = dllout[0] (first output clock phase, out of 8 phases,
11524 of the Slice DLL).
11525 0x2 = dllout[1] (second output clock phase, out of 8 phases,
11526 of the Slice DLL).
11527 0x4 = piclk (output clock of the PI).
11528 0x8 = vdda_int.
11529
11530 All other values in this field are reserved. */
11531 #else /* Word 0 - Little Endian */
11532 uint64_t pcs_sds_rx_sdll_swsel : 4; /**< [ 3: 0](R/W) DMON control; selects which signal is passed to the output
11533 of DMON.
11534 0x1 = dllout[0] (first output clock phase, out of 8 phases,
11535 of the Slice DLL).
11536 0x2 = dllout[1] (second output clock phase, out of 8 phases,
11537 of the Slice DLL).
11538 0x4 = piclk (output clock of the PI).
11539 0x8 = vdda_int.
11540
11541 All other values in this field are reserved. */
11542 uint64_t pcs_sds_rx_sdll_tune : 3; /**< [ 6: 4](R/W) Tuning bits for the regulator and the loop filter. */
11543 uint64_t reserved_7_13 : 7;
11544 uint64_t pcs_sds_oob_clk_ctrl : 2; /**< [ 15: 14](R/W/H) OOB clock oscillator output frequency selection:
11545 0x0 = 506 MHz (min) 682 MHz (typ) 782 MHz (max).
11546 0x1 = 439 MHz (min) 554 MHz (typ) 595 MHz (max).
11547 0x2 = 379 MHz (min) 453 MHz (typ) 482 MHz (max).
11548 0x3 = 303 MHz (min) 378 MHz (typ) 414 MHz (max).
11549
11550 This parameter is for debugging purposes and should not
11551 be written in normal operation. */
11552 uint64_t reserved_16_63 : 48;
11553 #endif /* Word 0 - End */
11554 } s;
11555 /* struct bdk_gserx_slicex_rx_sdll_ctrl_s cn; */
11556 };
11557 typedef union bdk_gserx_slicex_rx_sdll_ctrl bdk_gserx_slicex_rx_sdll_ctrl_t;
11558
11559 static inline uint64_t BDK_GSERX_SLICEX_RX_SDLL_CTRL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_RX_SDLL_CTRL(unsigned long a,unsigned long b)11560 static inline uint64_t BDK_GSERX_SLICEX_RX_SDLL_CTRL(unsigned long a, unsigned long b)
11561 {
11562 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
11563 return 0x87e090460220ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
11564 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
11565 return 0x87e090460220ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
11566 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
11567 return 0x87e090460220ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
11568 __bdk_csr_fatal("GSERX_SLICEX_RX_SDLL_CTRL", 2, a, b, 0, 0);
11569 }
11570
11571 #define typedef_BDK_GSERX_SLICEX_RX_SDLL_CTRL(a,b) bdk_gserx_slicex_rx_sdll_ctrl_t
11572 #define bustype_BDK_GSERX_SLICEX_RX_SDLL_CTRL(a,b) BDK_CSR_TYPE_RSL
11573 #define basename_BDK_GSERX_SLICEX_RX_SDLL_CTRL(a,b) "GSERX_SLICEX_RX_SDLL_CTRL"
11574 #define device_bar_BDK_GSERX_SLICEX_RX_SDLL_CTRL(a,b) 0x0 /* PF_BAR0 */
11575 #define busnum_BDK_GSERX_SLICEX_RX_SDLL_CTRL(a,b) (a)
11576 #define arguments_BDK_GSERX_SLICEX_RX_SDLL_CTRL(a,b) (a),(b),-1,-1
11577
11578 /**
11579 * Register (RSL) gser#_slice#_sgmii_mode
11580 *
11581 * GSER Slice SGMII MODE Register
11582 * These registers are for diagnostic use only.
11583 * These registers are reset by hardware only during chip cold reset.
11584 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
11585 */
11586 union bdk_gserx_slicex_sgmii_mode
11587 {
11588 uint64_t u;
11589 struct bdk_gserx_slicex_sgmii_mode_s
11590 {
11591 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11592 uint64_t reserved_15_63 : 49;
11593 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
11594 Bit 13 controls enable for lane 0.
11595 Bit 14 controls enable for lane 1. */
11596 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
11597 0x0 = 500 uA.
11598 0x1 = 1000 uA.
11599 0x2 = 250 uA.
11600 0x3 = 330 uA. */
11601 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
11602 0x0 = 500 uA.
11603 0x1 = 1000 uA.
11604 0x2 = 250 uA.
11605 0x3 = 330 uA. */
11606 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
11607 0x0 = 2.5 GHz.
11608 0x1 = 3.125 GHz.
11609 0x6 = 4 GHz.
11610 0x7 = 5.15625 GHz.
11611
11612 All other values in this field are reserved. */
11613 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
11614 based on the PLL clock frequency as follows:
11615 0x0 = 2.5 GHz.
11616 0x1 = 3.125 GHz.
11617 0x3 = 4 GHz.
11618 0x5 = 5.15625 GHz.
11619 0x6 = 5.65 GHz.
11620 0x7 = 6.25 GHz.
11621
11622 All other values in this field are reserved. */
11623 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
11624 based on the PLL clock frequency as follows:
11625 0x0 = 2.5 GHz.
11626 0x1 = 3.125 GHz.
11627 0x3 = 4 GHz.
11628 0x5 = 5.15625 GHz.
11629 0x6 = 5.65 GHz.
11630 0x7 = 6.25 GHz.
11631
11632 All other values in this field are reserved. */
11633 #else /* Word 0 - Little Endian */
11634 uint64_t rx_sdll_bwsel : 3; /**< [ 2: 0](R/W/H) Controls capacitors in delay line for different data rates; should be set
11635 based on the PLL clock frequency as follows:
11636 0x0 = 2.5 GHz.
11637 0x1 = 3.125 GHz.
11638 0x3 = 4 GHz.
11639 0x5 = 5.15625 GHz.
11640 0x6 = 5.65 GHz.
11641 0x7 = 6.25 GHz.
11642
11643 All other values in this field are reserved. */
11644 uint64_t rx_ldll_bwsel : 3; /**< [ 5: 3](R/W/H) Controls capacitors in delay line for different data rates; should be set
11645 based on the PLL clock frequency as follows:
11646 0x0 = 2.5 GHz.
11647 0x1 = 3.125 GHz.
11648 0x3 = 4 GHz.
11649 0x5 = 5.15625 GHz.
11650 0x6 = 5.65 GHz.
11651 0x7 = 6.25 GHz.
11652
11653 All other values in this field are reserved. */
11654 uint64_t rx_pi_bwsel : 3; /**< [ 8: 6](R/W/H) Controls PI different data rates:
11655 0x0 = 2.5 GHz.
11656 0x1 = 3.125 GHz.
11657 0x6 = 4 GHz.
11658 0x7 = 5.15625 GHz.
11659
11660 All other values in this field are reserved. */
11661 uint64_t rx_sdll_isel : 2; /**< [ 10: 9](R/W/H) Controls charge pump current for slice DLL:
11662 0x0 = 500 uA.
11663 0x1 = 1000 uA.
11664 0x2 = 250 uA.
11665 0x3 = 330 uA. */
11666 uint64_t rx_ldll_isel : 2; /**< [ 12: 11](R/W/H) Controls charge pump current for lane DLL:
11667 0x0 = 500 uA.
11668 0x1 = 1000 uA.
11669 0x2 = 250 uA.
11670 0x3 = 330 uA. */
11671 uint64_t slice_spare_1_0 : 2; /**< [ 14: 13](R/W/H) Controls enable of pcs_sds_rx_div33 for lane 0 and 1 in the slice:
11672 Bit 13 controls enable for lane 0.
11673 Bit 14 controls enable for lane 1. */
11674 uint64_t reserved_15_63 : 49;
11675 #endif /* Word 0 - End */
11676 } s;
11677 /* struct bdk_gserx_slicex_sgmii_mode_s cn; */
11678 };
11679 typedef union bdk_gserx_slicex_sgmii_mode bdk_gserx_slicex_sgmii_mode_t;
11680
11681 static inline uint64_t BDK_GSERX_SLICEX_SGMII_MODE(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICEX_SGMII_MODE(unsigned long a,unsigned long b)11682 static inline uint64_t BDK_GSERX_SLICEX_SGMII_MODE(unsigned long a, unsigned long b)
11683 {
11684 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a<=3) && (b<=1)))
11685 return 0x87e090460258ll + 0x1000000ll * ((a) & 0x3) + 0x200000ll * ((b) & 0x1);
11686 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=6) && (b<=1)))
11687 return 0x87e090460258ll + 0x1000000ll * ((a) & 0x7) + 0x200000ll * ((b) & 0x1);
11688 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=13) && (b<=1)))
11689 return 0x87e090460258ll + 0x1000000ll * ((a) & 0xf) + 0x200000ll * ((b) & 0x1);
11690 __bdk_csr_fatal("GSERX_SLICEX_SGMII_MODE", 2, a, b, 0, 0);
11691 }
11692
11693 #define typedef_BDK_GSERX_SLICEX_SGMII_MODE(a,b) bdk_gserx_slicex_sgmii_mode_t
11694 #define bustype_BDK_GSERX_SLICEX_SGMII_MODE(a,b) BDK_CSR_TYPE_RSL
11695 #define basename_BDK_GSERX_SLICEX_SGMII_MODE(a,b) "GSERX_SLICEX_SGMII_MODE"
11696 #define device_bar_BDK_GSERX_SLICEX_SGMII_MODE(a,b) 0x0 /* PF_BAR0 */
11697 #define busnum_BDK_GSERX_SLICEX_SGMII_MODE(a,b) (a)
11698 #define arguments_BDK_GSERX_SLICEX_SGMII_MODE(a,b) (a),(b),-1,-1
11699
11700 /**
11701 * Register (RSL) gser#_slice_cfg
11702 *
11703 * GSER Slice Configuration Register
11704 * These registers are for diagnostic use only.
11705 * These registers are reset by hardware only during chip cold reset.
11706 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
11707 */
11708 union bdk_gserx_slice_cfg
11709 {
11710 uint64_t u;
11711 struct bdk_gserx_slice_cfg_s
11712 {
11713 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11714 uint64_t reserved_12_63 : 52;
11715 uint64_t tx_rx_detect_lvl_enc : 4; /**< [ 11: 8](R/W) Determines the RX detect level, pcs_sds_tx_rx_detect_lvl[9:0],
11716 (which is a 1-hot signal), where the level is equal to
11717 2^TX_RX_DETECT_LVL_ENC. */
11718 uint64_t reserved_6_7 : 2;
11719 uint64_t pcs_sds_rx_pcie_pterm : 2; /**< [ 5: 4](R/W) Reserved. */
11720 uint64_t pcs_sds_rx_pcie_nterm : 2; /**< [ 3: 2](R/W) Reserved. */
11721 uint64_t pcs_sds_tx_stress_eye : 2; /**< [ 1: 0](R/W) Controls TX stress eye. */
11722 #else /* Word 0 - Little Endian */
11723 uint64_t pcs_sds_tx_stress_eye : 2; /**< [ 1: 0](R/W) Controls TX stress eye. */
11724 uint64_t pcs_sds_rx_pcie_nterm : 2; /**< [ 3: 2](R/W) Reserved. */
11725 uint64_t pcs_sds_rx_pcie_pterm : 2; /**< [ 5: 4](R/W) Reserved. */
11726 uint64_t reserved_6_7 : 2;
11727 uint64_t tx_rx_detect_lvl_enc : 4; /**< [ 11: 8](R/W) Determines the RX detect level, pcs_sds_tx_rx_detect_lvl[9:0],
11728 (which is a 1-hot signal), where the level is equal to
11729 2^TX_RX_DETECT_LVL_ENC. */
11730 uint64_t reserved_12_63 : 52;
11731 #endif /* Word 0 - End */
11732 } s;
11733 /* struct bdk_gserx_slice_cfg_s cn; */
11734 };
11735 typedef union bdk_gserx_slice_cfg bdk_gserx_slice_cfg_t;
11736
11737 static inline uint64_t BDK_GSERX_SLICE_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_SLICE_CFG(unsigned long a)11738 static inline uint64_t BDK_GSERX_SLICE_CFG(unsigned long a)
11739 {
11740 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
11741 return 0x87e090460060ll + 0x1000000ll * ((a) & 0x3);
11742 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
11743 return 0x87e090460060ll + 0x1000000ll * ((a) & 0x7);
11744 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
11745 return 0x87e090460060ll + 0x1000000ll * ((a) & 0xf);
11746 __bdk_csr_fatal("GSERX_SLICE_CFG", 1, a, 0, 0, 0);
11747 }
11748
11749 #define typedef_BDK_GSERX_SLICE_CFG(a) bdk_gserx_slice_cfg_t
11750 #define bustype_BDK_GSERX_SLICE_CFG(a) BDK_CSR_TYPE_RSL
11751 #define basename_BDK_GSERX_SLICE_CFG(a) "GSERX_SLICE_CFG"
11752 #define device_bar_BDK_GSERX_SLICE_CFG(a) 0x0 /* PF_BAR0 */
11753 #define busnum_BDK_GSERX_SLICE_CFG(a) (a)
11754 #define arguments_BDK_GSERX_SLICE_CFG(a) (a),-1,-1,-1
11755
11756 /**
11757 * Register (RSL) gser#_spd
11758 *
11759 * GSER Speed Bits Register
11760 * These registers are reset by hardware only during chip cold reset. The values of the CSR
11761 * fields in these registers do not change during chip warm or soft resets.
11762 */
11763 union bdk_gserx_spd
11764 {
11765 uint64_t u;
11766 struct bdk_gserx_spd_s
11767 {
11768 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11769 uint64_t reserved_4_63 : 60;
11770 uint64_t spd : 4; /**< [ 3: 0](R/W/H) For CCPI links (i.e. GSER8..13), the hardware loads this CSR field from the OCI_SPD\<3:0\>
11771 pins during chip cold reset. For non-CCPI links, this field is not used.
11772 For SPD settings that configure a non-default reference clock, hardware updates the PLL
11773 settings of the specific lane mode (LMODE) table entry to derive the correct link rate.
11774
11775 \<pre\>
11776 REFCLK Link Rate
11777 SPD (MHz) (Gb) LMODE
11778 ---- ------ ------ -----------------------
11779 0x0: 100 1.25 R_125G_REFCLK15625_KX
11780 0x1: 100 2.5 R_25G_REFCLK100
11781 0x2: 100 5 R_5G_REFCLK100
11782 0x3: 100 8 R_8G_REFCLK100
11783 0x4: 125 1.25 R_125G_REFCLK15625_KX
11784 0x5: 125 2.5 R_25G_REFCLK125
11785 0x6: 125 3.125 R_3125G_REFCLK15625_XAUI
11786 0x7: 125 5 R_5G_REFCLK125
11787 0x8: 125 6.25 R_625G_REFCLK15625_RXAUI
11788 0x9: 125 8 R_8G_REFCLK125
11789 0xA: 156.25 2.5 R_25G_REFCLK100
11790 0xB: 156.25 3.125 R_3125G_REFCLK15625_XAUI
11791 0xC: 156.25 5 R_5G_REFCLK125
11792 0xD: 156.25 6.25 R_625G_REFCLK15625_RXAUI
11793 0xE: 156.25 10.3125 R_103125G_REFCLK15625_KR
11794 0xF: SW_MODE
11795 \</pre\>
11796
11797 Note that a value of 0xF is called SW_MODE. The CCPI link does not come up configured in
11798 SW_MODE.
11799 (Software must do all the CCPI GSER configuration to use CCPI in the case of SW_MODE.)
11800 When SPD!=SW_MODE after a chip cold reset, the hardware has initialized the following
11801 registers (based on the OCI_SPD selection):
11802
11803 * GSER()_LANE_MODE[LMODE]=Z.
11804 * GSER()_PLL_P()_MODE_0.
11805 * GSER()_PLL_P()_MODE_1.
11806 * GSER()_LANE_P()_MODE_0.
11807 * GSER()_LANE_P()_MODE_1.
11808 * GSER()_LANE()_RX_VALBBD_CTRL_0.
11809 * GSER()_LANE()_RX_VALBBD_CTRL_1.
11810 * GSER()_LANE()_RX_VALBBD_CTRL_2.
11811
11812 where in "GSER(x)", x is 8..13, and in "P(z)", z equals LMODE. */
11813 #else /* Word 0 - Little Endian */
11814 uint64_t spd : 4; /**< [ 3: 0](R/W/H) For CCPI links (i.e. GSER8..13), the hardware loads this CSR field from the OCI_SPD\<3:0\>
11815 pins during chip cold reset. For non-CCPI links, this field is not used.
11816 For SPD settings that configure a non-default reference clock, hardware updates the PLL
11817 settings of the specific lane mode (LMODE) table entry to derive the correct link rate.
11818
11819 \<pre\>
11820 REFCLK Link Rate
11821 SPD (MHz) (Gb) LMODE
11822 ---- ------ ------ -----------------------
11823 0x0: 100 1.25 R_125G_REFCLK15625_KX
11824 0x1: 100 2.5 R_25G_REFCLK100
11825 0x2: 100 5 R_5G_REFCLK100
11826 0x3: 100 8 R_8G_REFCLK100
11827 0x4: 125 1.25 R_125G_REFCLK15625_KX
11828 0x5: 125 2.5 R_25G_REFCLK125
11829 0x6: 125 3.125 R_3125G_REFCLK15625_XAUI
11830 0x7: 125 5 R_5G_REFCLK125
11831 0x8: 125 6.25 R_625G_REFCLK15625_RXAUI
11832 0x9: 125 8 R_8G_REFCLK125
11833 0xA: 156.25 2.5 R_25G_REFCLK100
11834 0xB: 156.25 3.125 R_3125G_REFCLK15625_XAUI
11835 0xC: 156.25 5 R_5G_REFCLK125
11836 0xD: 156.25 6.25 R_625G_REFCLK15625_RXAUI
11837 0xE: 156.25 10.3125 R_103125G_REFCLK15625_KR
11838 0xF: SW_MODE
11839 \</pre\>
11840
11841 Note that a value of 0xF is called SW_MODE. The CCPI link does not come up configured in
11842 SW_MODE.
11843 (Software must do all the CCPI GSER configuration to use CCPI in the case of SW_MODE.)
11844 When SPD!=SW_MODE after a chip cold reset, the hardware has initialized the following
11845 registers (based on the OCI_SPD selection):
11846
11847 * GSER()_LANE_MODE[LMODE]=Z.
11848 * GSER()_PLL_P()_MODE_0.
11849 * GSER()_PLL_P()_MODE_1.
11850 * GSER()_LANE_P()_MODE_0.
11851 * GSER()_LANE_P()_MODE_1.
11852 * GSER()_LANE()_RX_VALBBD_CTRL_0.
11853 * GSER()_LANE()_RX_VALBBD_CTRL_1.
11854 * GSER()_LANE()_RX_VALBBD_CTRL_2.
11855
11856 where in "GSER(x)", x is 8..13, and in "P(z)", z equals LMODE. */
11857 uint64_t reserved_4_63 : 60;
11858 #endif /* Word 0 - End */
11859 } s;
11860 /* struct bdk_gserx_spd_s cn88xxp1; */
11861 struct bdk_gserx_spd_cn81xx
11862 {
11863 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11864 uint64_t reserved_4_63 : 60;
11865 uint64_t spd : 4; /**< [ 3: 0](R/W/H) Not used. */
11866 #else /* Word 0 - Little Endian */
11867 uint64_t spd : 4; /**< [ 3: 0](R/W/H) Not used. */
11868 uint64_t reserved_4_63 : 60;
11869 #endif /* Word 0 - End */
11870 } cn81xx;
11871 /* struct bdk_gserx_spd_cn81xx cn83xx; */
11872 struct bdk_gserx_spd_cn88xxp2
11873 {
11874 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11875 uint64_t reserved_4_63 : 60;
11876 uint64_t spd : 4; /**< [ 3: 0](R/W/H) For CCPI links (i.e. GSER8..13), the hardware loads this CSR field from the OCI_SPD\<3:0\>
11877 pins during chip cold reset. For non-CCPI links, this field is not used.
11878 For SPD settings that configure a non-default reference clock, hardware updates the PLL
11879 settings of the specific lane mode (LMODE) table entry to derive the correct link rate.
11880
11881 \<pre\>
11882 REFCLK Link Rate
11883 SPD (MHz) (Gb) Train LMODE
11884 ---- ------ ------ ----- -----------------------
11885 0x0: 100 5 TS R_5G_REFCLK100
11886 0x1: 100 2.5 -- R_25G_REFCLK100
11887 0x2: 100 5 -- R_5G_REFCLK100
11888 0x3: 100 8 -- R_8G_REFCLK100
11889 0x4: 100 8 TS R_8G_REFCLK100
11890 0x5: 100 8 KR R_8G_REFCLK100
11891 0x6: 125 3.125 -- R_3125G_REFCLK15625_XAUI
11892 0x7: 125 5 -- R_5G_REFCLK125
11893 0x8: 125 6.25 -- R_625G_REFCLK15625_RXAUI
11894 0x9: 125 8 -- R_8G_REFCLK125
11895 0xA: 156.25 10.3125 TS R_103125G_REFCLK15625_KR
11896 0xB: 156.25 3.125 -- R_3125G_REFCLK15625_XAUI
11897 0xC: 156.25 5 TS R_5G_REFCLK125
11898 0xD: 156.25 6.25 TS R_625G_REFCLK15625_RXAUI
11899 0xE: 156.25 10.3125 KR R_103125G_REFCLK15625_KR
11900 0xF: SW_MODE
11901 \</pre\>
11902
11903 Train column indicates training method. TS indicates short training, i.e., local RX
11904 equalization only. KR indicates KR training, i.e., local RX equalization and link
11905 partner TX equalizer adaptation. -- indicates not applicable.
11906 Note that a value of 0xF is called SW_MODE. The CCPI link does not come up configured in
11907 SW_MODE.
11908 (Software must do all the CCPI GSER configuration to use CCPI in the case of SW_MODE.)
11909 When SPD!=SW_MODE after a chip cold reset, the hardware has initialized the following
11910 registers (based on the OCI_SPD selection):
11911
11912 * GSER()_LANE_MODE[LMODE]=Z.
11913 * GSER()_PLL_P()_MODE_0.
11914 * GSER()_PLL_P()_MODE_1.
11915 * GSER()_LANE_P()_MODE_0.
11916 * GSER()_LANE_P()_MODE_1.
11917 * GSER()_LANE()_RX_VALBBD_CTRL_0.
11918 * GSER()_LANE()_RX_VALBBD_CTRL_1.
11919 * GSER()_LANE()_RX_VALBBD_CTRL_2.
11920
11921 where in "GSER(x)", x is 8..13, and in "P(z)", z equals LMODE. */
11922 #else /* Word 0 - Little Endian */
11923 uint64_t spd : 4; /**< [ 3: 0](R/W/H) For CCPI links (i.e. GSER8..13), the hardware loads this CSR field from the OCI_SPD\<3:0\>
11924 pins during chip cold reset. For non-CCPI links, this field is not used.
11925 For SPD settings that configure a non-default reference clock, hardware updates the PLL
11926 settings of the specific lane mode (LMODE) table entry to derive the correct link rate.
11927
11928 \<pre\>
11929 REFCLK Link Rate
11930 SPD (MHz) (Gb) Train LMODE
11931 ---- ------ ------ ----- -----------------------
11932 0x0: 100 5 TS R_5G_REFCLK100
11933 0x1: 100 2.5 -- R_25G_REFCLK100
11934 0x2: 100 5 -- R_5G_REFCLK100
11935 0x3: 100 8 -- R_8G_REFCLK100
11936 0x4: 100 8 TS R_8G_REFCLK100
11937 0x5: 100 8 KR R_8G_REFCLK100
11938 0x6: 125 3.125 -- R_3125G_REFCLK15625_XAUI
11939 0x7: 125 5 -- R_5G_REFCLK125
11940 0x8: 125 6.25 -- R_625G_REFCLK15625_RXAUI
11941 0x9: 125 8 -- R_8G_REFCLK125
11942 0xA: 156.25 10.3125 TS R_103125G_REFCLK15625_KR
11943 0xB: 156.25 3.125 -- R_3125G_REFCLK15625_XAUI
11944 0xC: 156.25 5 TS R_5G_REFCLK125
11945 0xD: 156.25 6.25 TS R_625G_REFCLK15625_RXAUI
11946 0xE: 156.25 10.3125 KR R_103125G_REFCLK15625_KR
11947 0xF: SW_MODE
11948 \</pre\>
11949
11950 Train column indicates training method. TS indicates short training, i.e., local RX
11951 equalization only. KR indicates KR training, i.e., local RX equalization and link
11952 partner TX equalizer adaptation. -- indicates not applicable.
11953 Note that a value of 0xF is called SW_MODE. The CCPI link does not come up configured in
11954 SW_MODE.
11955 (Software must do all the CCPI GSER configuration to use CCPI in the case of SW_MODE.)
11956 When SPD!=SW_MODE after a chip cold reset, the hardware has initialized the following
11957 registers (based on the OCI_SPD selection):
11958
11959 * GSER()_LANE_MODE[LMODE]=Z.
11960 * GSER()_PLL_P()_MODE_0.
11961 * GSER()_PLL_P()_MODE_1.
11962 * GSER()_LANE_P()_MODE_0.
11963 * GSER()_LANE_P()_MODE_1.
11964 * GSER()_LANE()_RX_VALBBD_CTRL_0.
11965 * GSER()_LANE()_RX_VALBBD_CTRL_1.
11966 * GSER()_LANE()_RX_VALBBD_CTRL_2.
11967
11968 where in "GSER(x)", x is 8..13, and in "P(z)", z equals LMODE. */
11969 uint64_t reserved_4_63 : 60;
11970 #endif /* Word 0 - End */
11971 } cn88xxp2;
11972 };
11973 typedef union bdk_gserx_spd bdk_gserx_spd_t;
11974
11975 static inline uint64_t BDK_GSERX_SPD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_SPD(unsigned long a)11976 static inline uint64_t BDK_GSERX_SPD(unsigned long a)
11977 {
11978 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
11979 return 0x87e090000088ll + 0x1000000ll * ((a) & 0x3);
11980 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
11981 return 0x87e090000088ll + 0x1000000ll * ((a) & 0x7);
11982 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
11983 return 0x87e090000088ll + 0x1000000ll * ((a) & 0xf);
11984 __bdk_csr_fatal("GSERX_SPD", 1, a, 0, 0, 0);
11985 }
11986
11987 #define typedef_BDK_GSERX_SPD(a) bdk_gserx_spd_t
11988 #define bustype_BDK_GSERX_SPD(a) BDK_CSR_TYPE_RSL
11989 #define basename_BDK_GSERX_SPD(a) "GSERX_SPD"
11990 #define device_bar_BDK_GSERX_SPD(a) 0x0 /* PF_BAR0 */
11991 #define busnum_BDK_GSERX_SPD(a) (a)
11992 #define arguments_BDK_GSERX_SPD(a) (a),-1,-1,-1
11993
11994 /**
11995 * Register (RSL) gser#_srst
11996 *
11997 * GSER Soft Reset Register
11998 * These registers are reset by hardware only during chip cold reset. The values of the CSR
11999 * fields in these registers do not change during chip warm or soft resets.
12000 */
12001 union bdk_gserx_srst
12002 {
12003 uint64_t u;
12004 struct bdk_gserx_srst_s
12005 {
12006 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12007 uint64_t reserved_1_63 : 63;
12008 uint64_t srst : 1; /**< [ 0: 0](R/W) When asserted, resets all per-lane state in the GSER with the exception of the PHY and the
12009 GSER()_CFG. For diagnostic use only. */
12010 #else /* Word 0 - Little Endian */
12011 uint64_t srst : 1; /**< [ 0: 0](R/W) When asserted, resets all per-lane state in the GSER with the exception of the PHY and the
12012 GSER()_CFG. For diagnostic use only. */
12013 uint64_t reserved_1_63 : 63;
12014 #endif /* Word 0 - End */
12015 } s;
12016 /* struct bdk_gserx_srst_s cn; */
12017 };
12018 typedef union bdk_gserx_srst bdk_gserx_srst_t;
12019
12020 static inline uint64_t BDK_GSERX_SRST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_SRST(unsigned long a)12021 static inline uint64_t BDK_GSERX_SRST(unsigned long a)
12022 {
12023 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
12024 return 0x87e090000090ll + 0x1000000ll * ((a) & 0x3);
12025 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
12026 return 0x87e090000090ll + 0x1000000ll * ((a) & 0x7);
12027 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
12028 return 0x87e090000090ll + 0x1000000ll * ((a) & 0xf);
12029 __bdk_csr_fatal("GSERX_SRST", 1, a, 0, 0, 0);
12030 }
12031
12032 #define typedef_BDK_GSERX_SRST(a) bdk_gserx_srst_t
12033 #define bustype_BDK_GSERX_SRST(a) BDK_CSR_TYPE_RSL
12034 #define basename_BDK_GSERX_SRST(a) "GSERX_SRST"
12035 #define device_bar_BDK_GSERX_SRST(a) 0x0 /* PF_BAR0 */
12036 #define busnum_BDK_GSERX_SRST(a) (a)
12037 #define arguments_BDK_GSERX_SRST(a) (a),-1,-1,-1
12038
12039 /**
12040 * Register (RSL) gser#_term_cfg
12041 *
12042 * GSER Termination Calibration Configuration Register
12043 * These registers are for diagnostic use only.
12044 * These registers are reset by hardware only during chip cold reset.
12045 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
12046 */
12047 union bdk_gserx_term_cfg
12048 {
12049 uint64_t u;
12050 struct bdk_gserx_term_cfg_s
12051 {
12052 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12053 uint64_t reserved_9_63 : 55;
12054 uint64_t fast_term_cal : 1; /**< [ 8: 8](R/W/H) Set to enable fast termination calibration.
12055 For simulation use only. */
12056 uint64_t reserved_7 : 1;
12057 uint64_t cal_start_ovrd_en : 1; /**< [ 6: 6](R/W/H) When set, calibration start is defined by
12058 GSER()_TERM_CFG[CAL_START_OVRD_VAL]. */
12059 uint64_t cal_start_ovrd_val : 1; /**< [ 5: 5](R/W/H) Override calibration start value. */
12060 uint64_t cal_code_ovrd_en : 1; /**< [ 4: 4](R/W/H) When set, calibration code is defined by
12061 GSER()_TERM_CFG[CAL_CODE_OVRD]. */
12062 uint64_t cal_code_ovrd : 4; /**< [ 3: 0](R/W/H) Override calibration code value. */
12063 #else /* Word 0 - Little Endian */
12064 uint64_t cal_code_ovrd : 4; /**< [ 3: 0](R/W/H) Override calibration code value. */
12065 uint64_t cal_code_ovrd_en : 1; /**< [ 4: 4](R/W/H) When set, calibration code is defined by
12066 GSER()_TERM_CFG[CAL_CODE_OVRD]. */
12067 uint64_t cal_start_ovrd_val : 1; /**< [ 5: 5](R/W/H) Override calibration start value. */
12068 uint64_t cal_start_ovrd_en : 1; /**< [ 6: 6](R/W/H) When set, calibration start is defined by
12069 GSER()_TERM_CFG[CAL_START_OVRD_VAL]. */
12070 uint64_t reserved_7 : 1;
12071 uint64_t fast_term_cal : 1; /**< [ 8: 8](R/W/H) Set to enable fast termination calibration.
12072 For simulation use only. */
12073 uint64_t reserved_9_63 : 55;
12074 #endif /* Word 0 - End */
12075 } s;
12076 /* struct bdk_gserx_term_cfg_s cn; */
12077 };
12078 typedef union bdk_gserx_term_cfg bdk_gserx_term_cfg_t;
12079
12080 static inline uint64_t BDK_GSERX_TERM_CFG(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_TERM_CFG(unsigned long a)12081 static inline uint64_t BDK_GSERX_TERM_CFG(unsigned long a)
12082 {
12083 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
12084 return 0x87e090460070ll + 0x1000000ll * ((a) & 0x3);
12085 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
12086 return 0x87e090460070ll + 0x1000000ll * ((a) & 0x7);
12087 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
12088 return 0x87e090460070ll + 0x1000000ll * ((a) & 0xf);
12089 __bdk_csr_fatal("GSERX_TERM_CFG", 1, a, 0, 0, 0);
12090 }
12091
12092 #define typedef_BDK_GSERX_TERM_CFG(a) bdk_gserx_term_cfg_t
12093 #define bustype_BDK_GSERX_TERM_CFG(a) BDK_CSR_TYPE_RSL
12094 #define basename_BDK_GSERX_TERM_CFG(a) "GSERX_TERM_CFG"
12095 #define device_bar_BDK_GSERX_TERM_CFG(a) 0x0 /* PF_BAR0 */
12096 #define busnum_BDK_GSERX_TERM_CFG(a) (a)
12097 #define arguments_BDK_GSERX_TERM_CFG(a) (a),-1,-1,-1
12098
12099 /**
12100 * Register (RSL) gser#_term_mon_1
12101 *
12102 * GSER Termination Cal Code Monitor Register
12103 * These registers are for diagnostic use only.
12104 * These registers are reset by hardware only during chip cold reset.
12105 * The values of the CSR fields in these registers do not change during chip warm or soft resets.
12106 */
12107 union bdk_gserx_term_mon_1
12108 {
12109 uint64_t u;
12110 struct bdk_gserx_term_mon_1_s
12111 {
12112 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12113 uint64_t reserved_4_63 : 60;
12114 uint64_t cal_code_mgmt : 4; /**< [ 3: 0](RO/H) RX and TX termination resistance calibration code. */
12115 #else /* Word 0 - Little Endian */
12116 uint64_t cal_code_mgmt : 4; /**< [ 3: 0](RO/H) RX and TX termination resistance calibration code. */
12117 uint64_t reserved_4_63 : 60;
12118 #endif /* Word 0 - End */
12119 } s;
12120 /* struct bdk_gserx_term_mon_1_s cn; */
12121 };
12122 typedef union bdk_gserx_term_mon_1 bdk_gserx_term_mon_1_t;
12123
12124 static inline uint64_t BDK_GSERX_TERM_MON_1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_TERM_MON_1(unsigned long a)12125 static inline uint64_t BDK_GSERX_TERM_MON_1(unsigned long a)
12126 {
12127 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
12128 return 0x87e090460110ll + 0x1000000ll * ((a) & 0x3);
12129 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
12130 return 0x87e090460110ll + 0x1000000ll * ((a) & 0x7);
12131 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
12132 return 0x87e090460110ll + 0x1000000ll * ((a) & 0xf);
12133 __bdk_csr_fatal("GSERX_TERM_MON_1", 1, a, 0, 0, 0);
12134 }
12135
12136 #define typedef_BDK_GSERX_TERM_MON_1(a) bdk_gserx_term_mon_1_t
12137 #define bustype_BDK_GSERX_TERM_MON_1(a) BDK_CSR_TYPE_RSL
12138 #define basename_BDK_GSERX_TERM_MON_1(a) "GSERX_TERM_MON_1"
12139 #define device_bar_BDK_GSERX_TERM_MON_1(a) 0x0 /* PF_BAR0 */
12140 #define busnum_BDK_GSERX_TERM_MON_1(a) (a)
12141 #define arguments_BDK_GSERX_TERM_MON_1(a) (a),-1,-1,-1
12142
12143 /**
12144 * Register (RSL) gser#_tx_vboost
12145 *
12146 * GSER TX Voltage Boost Enable Register
12147 * These registers are reset by hardware only during chip cold reset. The values of the CSR
12148 * fields in these registers do not change during chip warm or soft resets.
12149 */
12150 union bdk_gserx_tx_vboost
12151 {
12152 uint64_t u;
12153 struct bdk_gserx_tx_vboost_s
12154 {
12155 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12156 uint64_t reserved_4_63 : 60;
12157 uint64_t vboost : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, boosts the TX Vswing from
12158 VDD to 1.0 VPPD.
12159 \<3\>: Lane 3. Reserved.
12160 \<2\>: Lane 2. Reserved.
12161 \<1\>: Lane 1.
12162 \<0\>: Lane 0. */
12163 #else /* Word 0 - Little Endian */
12164 uint64_t vboost : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, boosts the TX Vswing from
12165 VDD to 1.0 VPPD.
12166 \<3\>: Lane 3. Reserved.
12167 \<2\>: Lane 2. Reserved.
12168 \<1\>: Lane 1.
12169 \<0\>: Lane 0. */
12170 uint64_t reserved_4_63 : 60;
12171 #endif /* Word 0 - End */
12172 } s;
12173 /* struct bdk_gserx_tx_vboost_s cn81xx; */
12174 struct bdk_gserx_tx_vboost_cn88xx
12175 {
12176 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12177 uint64_t reserved_4_63 : 60;
12178 uint64_t vboost : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode (including all CCPI links), boosts the TX Vswing from
12179 VDD to 1.0 VPPD.
12180 \<3\>: Lane 3.
12181 \<2\>: Lane 2.
12182 \<1\>: Lane 1.
12183 \<0\>: Lane 0. */
12184 #else /* Word 0 - Little Endian */
12185 uint64_t vboost : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode (including all CCPI links), boosts the TX Vswing from
12186 VDD to 1.0 VPPD.
12187 \<3\>: Lane 3.
12188 \<2\>: Lane 2.
12189 \<1\>: Lane 1.
12190 \<0\>: Lane 0. */
12191 uint64_t reserved_4_63 : 60;
12192 #endif /* Word 0 - End */
12193 } cn88xx;
12194 struct bdk_gserx_tx_vboost_cn83xx
12195 {
12196 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12197 uint64_t reserved_4_63 : 60;
12198 uint64_t vboost : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, boosts the TX Vswing from
12199 VDD to 1.0 VPPD.
12200 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
12201 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
12202 \<1\>: Lane 1.
12203 \<0\>: Lane 0. */
12204 #else /* Word 0 - Little Endian */
12205 uint64_t vboost : 4; /**< [ 3: 0](R/W) For links that are not in PCIE mode, boosts the TX Vswing from
12206 VDD to 1.0 VPPD.
12207 \<3\>: Lane 3. Not supported in GSER4, GSER5, or GSER6.
12208 \<2\>: Lane 2. Not supported in GSER4, GSER5, or GSER6.
12209 \<1\>: Lane 1.
12210 \<0\>: Lane 0. */
12211 uint64_t reserved_4_63 : 60;
12212 #endif /* Word 0 - End */
12213 } cn83xx;
12214 };
12215 typedef union bdk_gserx_tx_vboost bdk_gserx_tx_vboost_t;
12216
12217 static inline uint64_t BDK_GSERX_TX_VBOOST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_TX_VBOOST(unsigned long a)12218 static inline uint64_t BDK_GSERX_TX_VBOOST(unsigned long a)
12219 {
12220 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
12221 return 0x87e090000130ll + 0x1000000ll * ((a) & 0x3);
12222 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
12223 return 0x87e090000130ll + 0x1000000ll * ((a) & 0x7);
12224 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
12225 return 0x87e090000130ll + 0x1000000ll * ((a) & 0xf);
12226 __bdk_csr_fatal("GSERX_TX_VBOOST", 1, a, 0, 0, 0);
12227 }
12228
12229 #define typedef_BDK_GSERX_TX_VBOOST(a) bdk_gserx_tx_vboost_t
12230 #define bustype_BDK_GSERX_TX_VBOOST(a) BDK_CSR_TYPE_RSL
12231 #define basename_BDK_GSERX_TX_VBOOST(a) "GSERX_TX_VBOOST"
12232 #define device_bar_BDK_GSERX_TX_VBOOST(a) 0x0 /* PF_BAR0 */
12233 #define busnum_BDK_GSERX_TX_VBOOST(a) (a)
12234 #define arguments_BDK_GSERX_TX_VBOOST(a) (a),-1,-1,-1
12235
12236 /**
12237 * Register (RSL) gser#_txclk_evt_cntr
12238 *
12239 * GSER QLM Transmit Clock Event Counter Register
12240 */
12241 union bdk_gserx_txclk_evt_cntr
12242 {
12243 uint64_t u;
12244 struct bdk_gserx_txclk_evt_cntr_s
12245 {
12246 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12247 uint64_t reserved_32_63 : 32;
12248 uint64_t count : 32; /**< [ 31: 0](RO) This register can only be reliably read when GSER()_TXCLK_EVT_CTRL[ENB]
12249 is clear.
12250
12251 When GSER()_TXCLK_EVT_CTRL[CLR] is set, [COUNT] goes to zero.
12252
12253 When GSER()_TXCLK_EVT_CTRL[ENB] is set, [COUNT] is incremented
12254 in positive edges of the QLM reference clock.
12255
12256 When GSER()_TXCLK_EVT_CTRL[ENB] is not set, [COUNT] value is held;
12257 this must be used when [COUNT] is being read for reliable results. */
12258 #else /* Word 0 - Little Endian */
12259 uint64_t count : 32; /**< [ 31: 0](RO) This register can only be reliably read when GSER()_TXCLK_EVT_CTRL[ENB]
12260 is clear.
12261
12262 When GSER()_TXCLK_EVT_CTRL[CLR] is set, [COUNT] goes to zero.
12263
12264 When GSER()_TXCLK_EVT_CTRL[ENB] is set, [COUNT] is incremented
12265 in positive edges of the QLM reference clock.
12266
12267 When GSER()_TXCLK_EVT_CTRL[ENB] is not set, [COUNT] value is held;
12268 this must be used when [COUNT] is being read for reliable results. */
12269 uint64_t reserved_32_63 : 32;
12270 #endif /* Word 0 - End */
12271 } s;
12272 /* struct bdk_gserx_txclk_evt_cntr_s cn; */
12273 };
12274 typedef union bdk_gserx_txclk_evt_cntr bdk_gserx_txclk_evt_cntr_t;
12275
12276 static inline uint64_t BDK_GSERX_TXCLK_EVT_CNTR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_TXCLK_EVT_CNTR(unsigned long a)12277 static inline uint64_t BDK_GSERX_TXCLK_EVT_CNTR(unsigned long a)
12278 {
12279 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
12280 return 0x87e090000188ll + 0x1000000ll * ((a) & 0x3);
12281 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
12282 return 0x87e090000188ll + 0x1000000ll * ((a) & 0x7);
12283 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
12284 return 0x87e090000188ll + 0x1000000ll * ((a) & 0xf);
12285 __bdk_csr_fatal("GSERX_TXCLK_EVT_CNTR", 1, a, 0, 0, 0);
12286 }
12287
12288 #define typedef_BDK_GSERX_TXCLK_EVT_CNTR(a) bdk_gserx_txclk_evt_cntr_t
12289 #define bustype_BDK_GSERX_TXCLK_EVT_CNTR(a) BDK_CSR_TYPE_RSL
12290 #define basename_BDK_GSERX_TXCLK_EVT_CNTR(a) "GSERX_TXCLK_EVT_CNTR"
12291 #define device_bar_BDK_GSERX_TXCLK_EVT_CNTR(a) 0x0 /* PF_BAR0 */
12292 #define busnum_BDK_GSERX_TXCLK_EVT_CNTR(a) (a)
12293 #define arguments_BDK_GSERX_TXCLK_EVT_CNTR(a) (a),-1,-1,-1
12294
12295 /**
12296 * Register (RSL) gser#_txclk_evt_ctrl
12297 *
12298 * GSER QLM Transmit Clock Event Counter Control Register
12299 */
12300 union bdk_gserx_txclk_evt_ctrl
12301 {
12302 uint64_t u;
12303 struct bdk_gserx_txclk_evt_ctrl_s
12304 {
12305 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12306 uint64_t reserved_2_63 : 62;
12307 uint64_t clr : 1; /**< [ 1: 1](R/W) When set, clears GSER()_TXCLK_EVT_CNTR[COUNT]. */
12308 uint64_t enb : 1; /**< [ 0: 0](R/W) When set, enables the GSER()_TXCLK_EVT_CNTR[COUNT] to increment
12309 on positive edges of the QLM reference clock. */
12310 #else /* Word 0 - Little Endian */
12311 uint64_t enb : 1; /**< [ 0: 0](R/W) When set, enables the GSER()_TXCLK_EVT_CNTR[COUNT] to increment
12312 on positive edges of the QLM reference clock. */
12313 uint64_t clr : 1; /**< [ 1: 1](R/W) When set, clears GSER()_TXCLK_EVT_CNTR[COUNT]. */
12314 uint64_t reserved_2_63 : 62;
12315 #endif /* Word 0 - End */
12316 } s;
12317 /* struct bdk_gserx_txclk_evt_ctrl_s cn; */
12318 };
12319 typedef union bdk_gserx_txclk_evt_ctrl bdk_gserx_txclk_evt_ctrl_t;
12320
12321 static inline uint64_t BDK_GSERX_TXCLK_EVT_CTRL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GSERX_TXCLK_EVT_CTRL(unsigned long a)12322 static inline uint64_t BDK_GSERX_TXCLK_EVT_CTRL(unsigned long a)
12323 {
12324 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=3))
12325 return 0x87e090000180ll + 0x1000000ll * ((a) & 0x3);
12326 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=6))
12327 return 0x87e090000180ll + 0x1000000ll * ((a) & 0x7);
12328 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=13))
12329 return 0x87e090000180ll + 0x1000000ll * ((a) & 0xf);
12330 __bdk_csr_fatal("GSERX_TXCLK_EVT_CTRL", 1, a, 0, 0, 0);
12331 }
12332
12333 #define typedef_BDK_GSERX_TXCLK_EVT_CTRL(a) bdk_gserx_txclk_evt_ctrl_t
12334 #define bustype_BDK_GSERX_TXCLK_EVT_CTRL(a) BDK_CSR_TYPE_RSL
12335 #define basename_BDK_GSERX_TXCLK_EVT_CTRL(a) "GSERX_TXCLK_EVT_CTRL"
12336 #define device_bar_BDK_GSERX_TXCLK_EVT_CTRL(a) 0x0 /* PF_BAR0 */
12337 #define busnum_BDK_GSERX_TXCLK_EVT_CTRL(a) (a)
12338 #define arguments_BDK_GSERX_TXCLK_EVT_CTRL(a) (a),-1,-1,-1
12339
12340 #endif /* __BDK_CSRS_GSER_H__ */
12341