1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_CHIP_H_ 4 #define _SOC_CHIP_H_ 5 6 #include <drivers/i2c/designware/dw_i2c.h> 7 #include <device/pci_ids.h> 8 #include <gpio.h> 9 #include <intelblocks/cfg.h> 10 #include <intelblocks/gspi.h> 11 #include <intelblocks/power_limit.h> 12 #include <intelblocks/pcie_rp.h> 13 #include <intelblocks/tcss.h> 14 #include <soc/gpe.h> 15 #include <soc/pci_devs.h> 16 #include <soc/pmc.h> 17 #include <soc/serialio.h> 18 #include <soc/usb.h> 19 #include <stdint.h> 20 21 /* Define config parameters for In-Band ECC (IBECC). */ 22 #define MAX_IBECC_REGIONS 8 23 24 #define MAX_SAGV_POINTS 4 25 #define MAX_HD_AUDIO_SDI_LINKS 2 26 27 /* In-Band ECC Operation Mode */ 28 enum ibecc_mode { 29 IBECC_MODE_PER_REGION, 30 IBECC_MODE_NONE, 31 IBECC_MODE_ALL 32 }; 33 34 struct ibecc_config { 35 bool enable; 36 bool parity_en; 37 enum ibecc_mode mode; 38 bool region_enable[MAX_IBECC_REGIONS]; 39 uint16_t region_base[MAX_IBECC_REGIONS]; 40 uint16_t region_mask[MAX_IBECC_REGIONS]; 41 }; 42 43 /* Types of different SKUs */ 44 enum soc_intel_meteorlake_power_limits { 45 MTL_P_282_242_CORE, 46 MTL_P_682_482_CORE, 47 MTL_POWER_LIMITS_COUNT 48 }; 49 50 /* TDP values for different SKUs */ 51 enum soc_intel_meteorlake_cpu_tdps { 52 TDP_15W = 15, 53 TDP_28W = 28 54 }; 55 56 /* Mapping of different SKUs based on CPU ID and TDP values */ 57 static const struct { 58 unsigned int cpu_id; 59 enum soc_intel_meteorlake_power_limits limits; 60 enum soc_intel_meteorlake_cpu_tdps cpu_tdp; 61 } cpuid_to_mtl[] = { 62 { PCI_DID_INTEL_MTL_P_ID_5, MTL_P_282_242_CORE, TDP_15W }, 63 { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W }, 64 { PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W }, 65 { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W }, 66 }; 67 68 /* Types of display ports */ 69 enum ddi_ports { 70 DDI_PORT_A, 71 DDI_PORT_B, 72 DDI_PORT_C, 73 DDI_PORT_1, 74 DDI_PORT_2, 75 DDI_PORT_3, 76 DDI_PORT_4, 77 DDI_PORT_COUNT, 78 }; 79 80 enum ddi_port_flags { 81 DDI_ENABLE_DDC = 1 << 0, // Display Data Channel 82 DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect 83 }; 84 85 /* 86 * The Max Pkg Cstate 87 * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 88 * 254 - CPU Default , 255 - Auto. 89 */ 90 enum pkgcstate_limit { 91 LIMIT_C0_C1 = 0, 92 LIMIT_C2 = 1, 93 LIMIT_C3 = 2, 94 LIMIT_C6 = 3, 95 LIMIT_C7 = 4, 96 LIMIT_C7S = 5, 97 LIMIT_C8 = 6, 98 LIMIT_C9 = 7, 99 LIMIT_C10 = 8, 100 LIMIT_CPUDEFAULT = 254, 101 LIMIT_AUTO = 255, 102 }; 103 104 /* Bit values for use in LpmStateEnableMask. */ 105 enum lpm_state_mask { 106 LPM_S0i2_0 = BIT(0), 107 LPM_S0i2_1 = BIT(1), 108 LPM_S0i2_2 = BIT(2), 109 LPM_S0i3_0 = BIT(3), 110 LPM_S0i3_1 = BIT(4), 111 LPM_S0i3_2 = BIT(5), 112 LPM_S0i3_3 = BIT(6), 113 LPM_S0i3_4 = BIT(7), 114 LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 115 | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, 116 }; 117 118 /* 119 * As per definition from FSP header: 120 * - [0] for IA 121 * - [1] for GT 122 * - [2] for SA 123 * - [3] through [5] are reserved 124 */ 125 enum vr_domain { 126 VR_DOMAIN_IA, 127 VR_DOMAIN_GT, 128 VR_DOMAIN_SA, 129 NUM_VR_DOMAINS 130 }; 131 132 /* 133 * Slew Rate configuration for Deep Package C States for VR domain. 134 * They are fast time divided by 2. 135 * 0 - Fast/2 136 * 1 - Fast/4 137 * 2 - Fast/8 138 * 3 - Fast/16 139 */ 140 enum slew_rate { 141 SLEW_FAST_2, 142 SLEW_FAST_4, 143 SLEW_FAST_8, 144 SLEW_FAST_16, 145 SLEW_IGNORE = 0xff, 146 }; 147 148 struct soc_intel_meteorlake_config { 149 /* Common struct containing soc config data required by common code */ 150 struct soc_intel_common_config common_soc_config; 151 152 /* Common struct containing power limits configuration information */ 153 struct soc_power_limits_config power_limits_config[MTL_POWER_LIMITS_COUNT]; 154 155 /* Gpio group routed to each dword of the GPE0 block. Values are 156 * of the form PMC_GPP_[A:U] or GPD. */ 157 uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ 158 uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ 159 uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ 160 161 /* Generic IO decode ranges */ 162 uint32_t gen1_dec; 163 uint32_t gen2_dec; 164 uint32_t gen3_dec; 165 uint32_t gen4_dec; 166 167 /* Enable S0iX support */ 168 int s0ix_enable; 169 /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ 170 uint8_t tcss_d3_hot_disable; 171 /* Enable DPTF support */ 172 int dptf_enable; 173 174 /* Deep SX enable for both AC and DC */ 175 int deep_s3_enable_ac; 176 int deep_s3_enable_dc; 177 int deep_s5_enable_ac; 178 int deep_s5_enable_dc; 179 180 /* Deep Sx Configuration 181 * DSX_EN_WAKE_PIN - Enable WAKE# pin 182 * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin 183 * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ 184 uint32_t deep_sx_config; 185 186 /* TCC activation offset */ 187 uint32_t tcc_offset; 188 189 /* In-Band ECC (IBECC) configuration */ 190 struct ibecc_config ibecc; 191 192 /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. 193 * When enabled memory will be training at two different frequencies. 194 * 0:Disabled, 1:Enabled 195 */ 196 enum { 197 SAGV_DISABLED, 198 SAGV_ENABLED, 199 } sagv; 200 201 /* System Agent dynamic frequency work points that memory will be training 202 * at the enabled frequencies. Possible work points are: 203 * 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3 204 */ 205 enum { 206 SAGV_POINTS_0_1 = 0x03, 207 SAGV_POINTS_0_1_2 = 0x07, 208 SAGV_POINTS_0_1_2_3 = 0x0f, 209 } sagv_wp_bitmap; 210 211 /* Rank Margin Tool. 1:Enable, 0:Disable */ 212 uint8_t rmt; 213 214 /* USB related */ 215 struct usb2_port_config usb2_ports[CONFIG_SOC_INTEL_USB2_DEV_MAX]; 216 struct usb3_port_config usb3_ports[CONFIG_SOC_INTEL_USB3_DEV_MAX]; 217 /* Wake Enable Bitmap for USB2 ports */ 218 uint16_t usb2_wake_enable_bitmap; 219 /* Wake Enable Bitmap for USB3 ports */ 220 uint16_t usb3_wake_enable_bitmap; 221 /* Program OC pins for TCSS */ 222 struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; 223 /* Validate TBT firmware authenticated and loaded into IMR */ 224 bool tbt_authentication; 225 226 /* SATA related */ 227 uint8_t sata_mode; 228 uint8_t sata_salp_support; 229 uint8_t sata_ports_enable[8]; 230 uint8_t sata_ports_dev_slp[8]; 231 232 /* 233 * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. 234 * Default 0. Setting this to 1 disables the SATA Power Optimizer. 235 */ 236 uint8_t sata_pwr_optimize_disable; 237 238 /* 239 * SATA Port Enable Dito Config. 240 * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). 241 */ 242 uint8_t sata_ports_enable_dito_config[8]; 243 244 /* SataPortsDmVal is the DITO multiplier. Default is 15. */ 245 uint8_t sata_ports_dm_val[8]; 246 /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ 247 uint16_t sata_ports_dito_val[8]; 248 249 /* Audio related */ 250 uint8_t pch_hda_audio_link_hda_enable; 251 uint8_t pch_hda_dsp_enable; 252 253 bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS]; 254 255 /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ 256 enum { 257 HDA_TMODE_2T = 0, 258 HDA_TMODE_4T = 2, 259 HDA_TMODE_8T = 3, 260 HDA_TMODE_16T = 4, 261 } pch_hda_idisp_link_tmode; 262 263 /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */ 264 enum { 265 HDA_LINKFREQ_48MHZ = 3, 266 HDA_LINKFREQ_96MHZ = 4, 267 } pch_hda_idisp_link_frequency; 268 269 bool pch_hda_idisp_codec_enable; 270 271 struct pcie_rp_config pcie_rp[CONFIG_MAX_ROOT_PORTS]; 272 uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC]; 273 274 /* Gfx related */ 275 enum { 276 IGD_SM_0MB = 0x00, 277 IGD_SM_32MB = 0x01, 278 IGD_SM_64MB = 0x02, 279 IGD_SM_96MB = 0x03, 280 IGD_SM_128MB = 0x04, 281 IGD_SM_160MB = 0x05, 282 IGD_SM_4MB = 0xF0, 283 IGD_SM_8MB = 0xF1, 284 IGD_SM_12MB = 0xF2, 285 IGD_SM_16MB = 0xF3, 286 IGD_SM_20MB = 0xF4, 287 IGD_SM_24MB = 0xF5, 288 IGD_SM_28MB = 0xF6, 289 IGD_SM_36MB = 0xF8, 290 IGD_SM_40MB = 0xF9, 291 IGD_SM_44MB = 0xFA, 292 IGD_SM_48MB = 0xFB, 293 IGD_SM_52MB = 0xFC, 294 IGD_SM_56MB = 0xFD, 295 IGD_SM_60MB = 0xFE, 296 } igd_dvmt50_pre_alloc; 297 uint8_t skip_ext_gfx_scan; 298 299 /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ 300 uint8_t eist_enable; 301 302 /* 303 * When enabled, this feature makes the SoC throttle when the power 304 * consumption exceeds the I_TRIP threshold. 305 * 306 * FSPs sets a by default I_TRIP threshold adapted to the current SoC 307 * and assuming a Voltage Regulator error accuracy of 6.5%. 308 */ 309 bool enable_fast_vmode[NUM_VR_DOMAINS]; 310 311 /* 312 * Current Excursion Protection needs to be set for each VR domain 313 * in order to be able to enable fast Vmode. 314 */ 315 bool cep_enable[NUM_VR_DOMAINS]; 316 317 /* 318 * VR Fast Vmode I_TRIP threshold. 319 * 0-255A in 1/4 A units. Example: 400 = 100A 320 * This setting overrides the default value set by FSPs when Fast VMode 321 * is enabled. 322 */ 323 uint16_t fast_vmode_i_trip[NUM_VR_DOMAINS]; 324 325 /* 326 * Power state current threshold 1. 327 * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, 328 * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for 329 * SA, [3] through [5] are Reserved. 330 */ 331 uint16_t ps_cur_1_threshold[NUM_VR_DOMAINS]; 332 333 /* 334 * Power state current threshold 2. 335 * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, 336 * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for 337 * SA, [3] through [5] are Reserved. 338 */ 339 uint16_t ps_cur_2_threshold[NUM_VR_DOMAINS]; 340 341 /* 342 * Power state current threshold 3. 343 * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, 344 * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for 345 * SA, [3] through [5] are Reserved. 346 */ 347 uint16_t ps_cur_3_threshold[NUM_VR_DOMAINS]; 348 349 uint8_t PmTimerDisabled; 350 /* 351 * SerialIO device mode selection: 352 * PchSerialIoDisabled, 353 * PchSerialIoPci, 354 * PchSerialIoHidden, 355 * PchSerialIoLegacyUart, 356 * PchSerialIoSkipInit 357 */ 358 uint8_t serial_io_i2c_mode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; 359 uint8_t serial_io_gspi_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; 360 uint8_t serial_io_uart_mode[CONFIG_SOC_INTEL_UART_DEV_MAX]; 361 /* 362 * GSPIn Default Chip Select Mode: 363 * 0:Hardware Mode, 364 * 1:Software Mode 365 */ 366 uint8_t serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; 367 /* 368 * GSPIn Default Chip Select State: 369 * 0: Low, 370 * 1: High 371 */ 372 uint8_t serial_io_gspi_cs_state[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; 373 374 /* CNVi WiFi Core Enable/Disable */ 375 bool cnvi_wifi_core; 376 377 /* CNVi BT Core Enable/Disable */ 378 bool cnvi_bt_core; 379 380 /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ 381 bool cnvi_bt_audio_offload; 382 383 /* 384 * These GPIOs will be programmed by the IOM to handle biasing of the 385 * Type-C aux (SBU) signals when certain alternate modes are used. 386 * `pad_auxn_dc` should be assigned to the GPIO pad providing negative 387 * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, 388 * `pad_auxp_dc` should be assigned to the GPIO providing positive bias 389 * (name often contains `AUXP_DC` or `_AUX_P`). 390 */ 391 struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; 392 393 /* 394 * SOC Aux orientation override: 395 * This is a bitfield that corresponds to up to 4 TCSS ports on MTL. 396 * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. 397 * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines 398 * on the motherboard. 399 */ 400 uint16_t tcss_aux_ori; 401 402 /* Connect Topology Command timeout value */ 403 uint16_t itbt_connect_topology_timeout_in_ms; 404 405 /* 406 * Override GPIO PM configuration: 407 * 0: Use FSP default GPIO PM program, 408 * 1: coreboot to override GPIO PM program 409 */ 410 uint8_t gpio_override_pm; 411 412 /* 413 * GPIO PM configuration: 0 to disable, 1 to enable power gating 414 * Bit 6-7: Reserved 415 * Bit 5: MISCCFG_GPSIDEDPCGEN 416 * Bit 4: MISCCFG_GPRCOMPCDLCGEN 417 * Bit 3: MISCCFG_GPRTCDLCGEN 418 * Bit 2: MISCCFG_GSXLCGEN 419 * Bit 1: MISCCFG_GPDPCGEN 420 * Bit 0: MISCCFG_GPDLCGEN 421 */ 422 uint8_t gpio_pm[TOTAL_GPIO_COMM]; 423 424 /* DP config */ 425 /* 426 * Port config 427 * 0:Disabled, 1:eDP, 2:MIPI DSI 428 */ 429 uint8_t ddi_port_A_config; 430 uint8_t ddi_port_B_config; 431 432 /* Enable(1)/Disable(0) HPD/DDC */ 433 uint8_t ddi_ports_config[DDI_PORT_COUNT]; 434 435 /* 436 * Override CPU flex ratio value: 437 * CPU ratio value controls the maximum processor non-turbo ratio. 438 * Valid Range 0 to 63. 439 * 440 * In general descriptor provides option to set default cpu flex ratio. 441 * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. 442 * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. 443 * 444 * Only override CPU flex ratio if don't want to boot with non-turbo max. 445 */ 446 uint8_t cpu_ratio_override; 447 448 /* 449 * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. 450 * Default 0. Setting this to 1 disables the DMI Power Optimizer. 451 */ 452 uint8_t dmi_pwr_optimize_disable; 453 454 /* 455 * Enable(1)/Disable(0) CPU Replacement check. 456 * Default 0. Setting this to 1 to check CPU replacement. 457 */ 458 uint8_t cpu_replacement_check; 459 460 /* ISA Serial Base selection. */ 461 enum { 462 ISA_SERIAL_BASE_ADDR_3F8, 463 ISA_SERIAL_BASE_ADDR_2F8, 464 } isa_serial_uart_base; 465 466 /* 467 * Assign clock source port for GbE. 0: Disable, N-1: port number 468 * Default 0. 469 */ 470 uint8_t lan_clk; 471 472 /* 473 * Enable or Disable C1 C-state Auto Demotion & un-demotion 474 * The algorithm looks at the behavior of the wake up tracker, how 475 * often it is waking up, and based on that it demote the c-state. 476 * Default 0. Set this to 1 in order to disable C1-state auto demotion. 477 * NOTE: Un-Demotion from Demoted C1 needs to be disabled when 478 * C1 C-state Auto Demotion is disabled. 479 */ 480 bool disable_c1_state_auto_demotion; 481 482 /* 483 * Enable or Disable Package C-state Demotion. 484 * Default is set to 0. 485 * Set this to 1 in order to disable Package C-state demotion. 486 * NOTE: Un-Demotion from demoted Package C-state needs to be disabled 487 * when auto demotion is disabled. 488 */ 489 bool disable_package_c_state_demotion; 490 491 /* Enable PCH to CPU energy report feature. */ 492 bool pch_pm_energy_report_enable; 493 494 /* Energy-Performance Preference (HWP feature) */ 495 bool enable_energy_perf_pref; 496 uint8_t energy_perf_pref_value; 497 498 bool disable_vmx; 499 500 /* 501 * SAGV Frequency per point in Mhz. 0 is Auto, otherwise holds the 502 * frequency value expressed as an integer. For example: 1867 503 */ 504 uint16_t sagv_freq_mhz[MAX_SAGV_POINTS]; 505 506 /* Gear Selection for SAGV points. 0: Auto, 1: Gear 1, 2: Gear 2, 4: Gear 4 */ 507 uint8_t sagv_gear[MAX_SAGV_POINTS]; 508 509 /* 510 * Enable or Disable Reduced BasicMemoryTest size. 511 * Default is set to 0. 512 * Set this to 1 in order to reduce BasicMemoryTest size 513 */ 514 bool lower_basic_mem_test_size; 515 516 /* Platform Power Pmax in Watts. Zero means automatic. */ 517 uint16_t psys_pmax_watts; 518 519 /* Platform Power Limit 2 in Watts. */ 520 uint16_t psys_pl2_watts; 521 522 /* Enable or Disable Acoustic Noise Mitigation feature */ 523 uint8_t enable_acoustic_noise_mitigation; 524 /* Disable Fast Slew Rate for Deep Package C States for VR domains */ 525 uint8_t disable_fast_pkgc_ramp[NUM_VR_DOMAINS]; 526 /* 527 * Slew Rate configuration for Deep Package C States for VR domains 528 * as per `enum slew_rate` data type. 529 */ 530 uint8_t slow_slew_rate_config[NUM_VR_DOMAINS]; 531 }; 532 533 typedef struct soc_intel_meteorlake_config config_t; 534 535 #endif 536