1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_NVIDIA_TEGRA210_CHIP_H__ 4 #define __SOC_NVIDIA_TEGRA210_CHIP_H__ 5 #include <soc/addressmap.h> 6 #include <stdint.h> 7 #include <soc/nvidia/tegra/dc.h> 8 9 struct soc_nvidia_tegra210_config { 10 /* 11 * panel resolution 12 * The two parameters below provides dc about panel spec. 13 */ 14 u32 xres; /* the width of H display active area */ 15 u32 yres; /* the height of V display active area */ 16 u32 framebuffer_bits_per_pixel; 17 u32 color_depth; /* color format */ 18 19 u64 display_controller; /* dc block base address */ 20 u32 framebuffer_base; 21 22 /* 23 * Technically, we can compute this. At the same time, some platforms 24 * might want to specify a specific size for their own reasons. If it 25 * is zero the soc code will compute it as 26 * xres*yres*framebuffer_bits_per_pixel/8 27 */ 28 u32 framebuffer_size; 29 30 /* 31 * Framebuffer resolution 32 * The two parameters below provides dc about framebuffer's sdram size. 33 * When they are not the same as panel resolution, we need to program 34 * dc's DDA_INCREMENT and some other registers to resize dc output. 35 */ 36 u32 display_xres; 37 u32 display_yres; 38 39 int href_to_sync; /* HSYNC position with respect to line start */ 40 int hsync_width; /* the width of HSYNC pulses */ 41 int hback_porch; /* the distance between HSYNC trailing edge to 42 beginning of H display active area */ 43 int hfront_porch; /* the distance between end of H display active 44 area to the leading edge of HSYNC */ 45 int vref_to_sync; 46 int vsync_width; 47 int vback_porch; 48 int vfront_porch; 49 int refresh; /* display refresh rate */ 50 51 int pixel_clock; /* dc pixel clock source rate */ 52 53 u32 panel_bits_per_pixel; 54 55 /* dp specific fields */ 56 struct { 57 /* pwm to use to set display contrast */ 58 int pwm; 59 60 /* HPD related timing */ 61 int vdd_to_hpd_delay_ms; 62 int hpd_unplug_min_us; 63 int hpd_plug_min_us; 64 int hpd_irq_min_us; 65 66 /* The minimum link configuration settings */ 67 u32 lane_count; 68 u32 enhanced_framing; 69 u32 link_bw; 70 u32 drive_current; 71 u32 preemphasis; 72 u32 postcursor; 73 } dp; 74 75 int win_opt; 76 void *dc_data; 77 }; 78 79 #endif /* __SOC_NVIDIA_TEGRA210_CHIP_H__ */ 80