xref: /aosp_15_r20/external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-ap.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1 #ifndef __BDK_CSRS_AP_H__
2 #define __BDK_CSRS_AP_H__
3 /* This file is auto-generated. Do not edit */
4 
5 /***********************license start***************
6  * Copyright (c) 2003-2017  Cavium Inc. ([email protected]). All rights
7  * reserved.
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9  *
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18  *     copyright notice, this list of conditions and the following
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20  *     with the distribution.
21 
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26 
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31 
32  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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41  * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42  ***********************license end**************************************/
43 
44 
45 /**
46  * @file
47  *
48  * Configuration and status register (CSR) address and type definitions for
49  * Cavium AP.
50  *
51  * This file is auto generated. Do not edit.
52  *
53  */
54 
55 /**
56  * Enumeration ap_clidr_el1_ctype_e
57  *
58  * Cache Type Field Enumeration
59  * Enumerates the CTYPEn fields of AP_CLIDR_EL1. All other values are reserved.
60  */
61 #define BDK_AP_CLIDR_EL1_CTYPE_E_DATA (2)
62 #define BDK_AP_CLIDR_EL1_CTYPE_E_INSTRUCTION (1)
63 #define BDK_AP_CLIDR_EL1_CTYPE_E_NONE (0)
64 #define BDK_AP_CLIDR_EL1_CTYPE_E_SEPARATE (3)
65 #define BDK_AP_CLIDR_EL1_CTYPE_E_UNIFIED (4)
66 
67 /**
68  * Enumeration ap_psb_accum_sel_e
69  *
70  * AP Power Serial Bus Accumulator Selection Enumeration
71  * Enumerates the AP accumulator events used by PSBS_AP()_ACCUM()_SEL.
72  */
73 #define BDK_AP_PSB_ACCUM_SEL_E_TBD0 (0)
74 
75 /**
76  * Enumeration ap_psb_event_e
77  *
78  * AP Power Serial Bus Event Enumeration
79  * Enumerates the event numbers for AP slaves, which correspond to index {b} of PSBS_AP()_EVENT()_CFG.
80  */
81 #define BDK_AP_PSB_EVENT_E_TBD0 (0)
82 
83 /**
84  * Register (SYSREG) ap_actlr_el#
85  *
86  * AP Auxiliary Control Register
87  * These registers are implementation defined for implementation specific control functionality
88  * while executing at the associated execution level, or, in the case of ACTLR_EL1, while
89  * executing at EL0.
90  */
91 union bdk_ap_actlr_elx
92 {
93     uint64_t u;
94     struct bdk_ap_actlr_elx_s
95     {
96 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
97         uint64_t reserved_0_63         : 64;
98 #else /* Word 0 - Little Endian */
99         uint64_t reserved_0_63         : 64;
100 #endif /* Word 0 - End */
101     } s;
102     /* struct bdk_ap_actlr_elx_s cn; */
103 };
104 typedef union bdk_ap_actlr_elx bdk_ap_actlr_elx_t;
105 
106 static inline uint64_t BDK_AP_ACTLR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ACTLR_ELX(unsigned long a)107 static inline uint64_t BDK_AP_ACTLR_ELX(unsigned long a)
108 {
109     if ((a>=1)&&(a<=3))
110         return 0x30001000100ll + 0ll * ((a) & 0x3);
111     __bdk_csr_fatal("AP_ACTLR_ELX", 1, a, 0, 0, 0);
112 }
113 
114 #define typedef_BDK_AP_ACTLR_ELX(a) bdk_ap_actlr_elx_t
115 #define bustype_BDK_AP_ACTLR_ELX(a) BDK_CSR_TYPE_SYSREG
116 #define basename_BDK_AP_ACTLR_ELX(a) "AP_ACTLR_ELX"
117 #define busnum_BDK_AP_ACTLR_ELX(a) (a)
118 #define arguments_BDK_AP_ACTLR_ELX(a) (a),-1,-1,-1
119 
120 /**
121  * Register (SYSREG) ap_afsr#_el#
122  *
123  * AP Auxiliary Fault Status 0 and 1 Registers
124  * Provides additional implementation defined fault status
125  *     information for exceptions taken to EL*.
126  */
127 union bdk_ap_afsrx_elx
128 {
129     uint32_t u;
130     struct bdk_ap_afsrx_elx_s
131     {
132 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
133         uint32_t reserved_0_31         : 32;
134 #else /* Word 0 - Little Endian */
135         uint32_t reserved_0_31         : 32;
136 #endif /* Word 0 - End */
137     } s;
138     /* struct bdk_ap_afsrx_elx_s cn; */
139 };
140 typedef union bdk_ap_afsrx_elx bdk_ap_afsrx_elx_t;
141 
142 static inline uint64_t BDK_AP_AFSRX_ELX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_AP_AFSRX_ELX(unsigned long a,unsigned long b)143 static inline uint64_t BDK_AP_AFSRX_ELX(unsigned long a, unsigned long b)
144 {
145     if ((a<=1) && ((b>=1)&&(b<=3)))
146         return 0x30005010000ll + 0x100ll * ((a) & 0x1) + 0ll * ((b) & 0x3);
147     __bdk_csr_fatal("AP_AFSRX_ELX", 2, a, b, 0, 0);
148 }
149 
150 #define typedef_BDK_AP_AFSRX_ELX(a,b) bdk_ap_afsrx_elx_t
151 #define bustype_BDK_AP_AFSRX_ELX(a,b) BDK_CSR_TYPE_SYSREG
152 #define basename_BDK_AP_AFSRX_ELX(a,b) "AP_AFSRX_ELX"
153 #define busnum_BDK_AP_AFSRX_ELX(a,b) (a)
154 #define arguments_BDK_AP_AFSRX_ELX(a,b) (a),(b),-1,-1
155 
156 /**
157  * Register (SYSREG) ap_afsr#_el12
158  *
159  * AP Auxiliary Fault Status 0 and 1 Alias Registers
160  * Alias of AFSR(n)_EL1 when accessed from EL2 and AP_HCR_EL2[E2H] is set.
161  */
162 union bdk_ap_afsrx_el12
163 {
164     uint32_t u;
165     struct bdk_ap_afsrx_el12_s
166     {
167 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
168         uint32_t reserved_0_31         : 32;
169 #else /* Word 0 - Little Endian */
170         uint32_t reserved_0_31         : 32;
171 #endif /* Word 0 - End */
172     } s;
173     /* struct bdk_ap_afsrx_el12_s cn; */
174 };
175 typedef union bdk_ap_afsrx_el12 bdk_ap_afsrx_el12_t;
176 
177 static inline uint64_t BDK_AP_AFSRX_EL12(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_AFSRX_EL12(unsigned long a)178 static inline uint64_t BDK_AP_AFSRX_EL12(unsigned long a)
179 {
180     if (a<=1)
181         return 0x30505010000ll + 0x100ll * ((a) & 0x1);
182     __bdk_csr_fatal("AP_AFSRX_EL12", 1, a, 0, 0, 0);
183 }
184 
185 #define typedef_BDK_AP_AFSRX_EL12(a) bdk_ap_afsrx_el12_t
186 #define bustype_BDK_AP_AFSRX_EL12(a) BDK_CSR_TYPE_SYSREG
187 #define basename_BDK_AP_AFSRX_EL12(a) "AP_AFSRX_EL12"
188 #define busnum_BDK_AP_AFSRX_EL12(a) (a)
189 #define arguments_BDK_AP_AFSRX_EL12(a) (a),-1,-1,-1
190 
191 /**
192  * Register (SYSREG) ap_aidr_el1
193  *
194  * AP Auxiliary ID Register
195  * Provides implementation defined identification information.
196  */
197 union bdk_ap_aidr_el1
198 {
199     uint64_t u;
200     struct bdk_ap_aidr_el1_s
201     {
202 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
203         uint64_t reserved_0_63         : 64;
204 #else /* Word 0 - Little Endian */
205         uint64_t reserved_0_63         : 64;
206 #endif /* Word 0 - End */
207     } s;
208     /* struct bdk_ap_aidr_el1_s cn; */
209 };
210 typedef union bdk_ap_aidr_el1 bdk_ap_aidr_el1_t;
211 
212 #define BDK_AP_AIDR_EL1 BDK_AP_AIDR_EL1_FUNC()
213 static inline uint64_t BDK_AP_AIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_AIDR_EL1_FUNC(void)214 static inline uint64_t BDK_AP_AIDR_EL1_FUNC(void)
215 {
216     return 0x30100000700ll;
217 }
218 
219 #define typedef_BDK_AP_AIDR_EL1 bdk_ap_aidr_el1_t
220 #define bustype_BDK_AP_AIDR_EL1 BDK_CSR_TYPE_SYSREG
221 #define basename_BDK_AP_AIDR_EL1 "AP_AIDR_EL1"
222 #define busnum_BDK_AP_AIDR_EL1 0
223 #define arguments_BDK_AP_AIDR_EL1 -1,-1,-1,-1
224 
225 /**
226  * Register (SYSREG) ap_amair_el#
227  *
228  * AP Auxiliary Memory Attribute Indirection Register
229  * Provides implementation defined memory attributes for the
230  *     memory regions specified by MAIR_EL*.
231  */
232 union bdk_ap_amair_elx
233 {
234     uint64_t u;
235     struct bdk_ap_amair_elx_s
236     {
237 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
238         uint64_t reserved_0_63         : 64;
239 #else /* Word 0 - Little Endian */
240         uint64_t reserved_0_63         : 64;
241 #endif /* Word 0 - End */
242     } s;
243     /* struct bdk_ap_amair_elx_s cn; */
244 };
245 typedef union bdk_ap_amair_elx bdk_ap_amair_elx_t;
246 
247 static inline uint64_t BDK_AP_AMAIR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_AMAIR_ELX(unsigned long a)248 static inline uint64_t BDK_AP_AMAIR_ELX(unsigned long a)
249 {
250     if ((a>=1)&&(a<=3))
251         return 0x3000a030000ll + 0ll * ((a) & 0x3);
252     __bdk_csr_fatal("AP_AMAIR_ELX", 1, a, 0, 0, 0);
253 }
254 
255 #define typedef_BDK_AP_AMAIR_ELX(a) bdk_ap_amair_elx_t
256 #define bustype_BDK_AP_AMAIR_ELX(a) BDK_CSR_TYPE_SYSREG
257 #define basename_BDK_AP_AMAIR_ELX(a) "AP_AMAIR_ELX"
258 #define busnum_BDK_AP_AMAIR_ELX(a) (a)
259 #define arguments_BDK_AP_AMAIR_ELX(a) (a),-1,-1,-1
260 
261 /**
262  * Register (SYSREG) ap_amair_el12
263  *
264  * AP Auxiliary Memory Attribute Indirection Register
265  * Alias of AMAIR_EL1 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
266  */
267 union bdk_ap_amair_el12
268 {
269     uint64_t u;
270     struct bdk_ap_amair_el12_s
271     {
272 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
273         uint64_t reserved_0_63         : 64;
274 #else /* Word 0 - Little Endian */
275         uint64_t reserved_0_63         : 64;
276 #endif /* Word 0 - End */
277     } s;
278     /* struct bdk_ap_amair_el12_s cn; */
279 };
280 typedef union bdk_ap_amair_el12 bdk_ap_amair_el12_t;
281 
282 #define BDK_AP_AMAIR_EL12 BDK_AP_AMAIR_EL12_FUNC()
283 static inline uint64_t BDK_AP_AMAIR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_AMAIR_EL12_FUNC(void)284 static inline uint64_t BDK_AP_AMAIR_EL12_FUNC(void)
285 {
286     return 0x3050a030000ll;
287 }
288 
289 #define typedef_BDK_AP_AMAIR_EL12 bdk_ap_amair_el12_t
290 #define bustype_BDK_AP_AMAIR_EL12 BDK_CSR_TYPE_SYSREG
291 #define basename_BDK_AP_AMAIR_EL12 "AP_AMAIR_EL12"
292 #define busnum_BDK_AP_AMAIR_EL12 0
293 #define arguments_BDK_AP_AMAIR_EL12 -1,-1,-1,-1
294 
295 /**
296  * Register (SYSREG) ap_ccsidr_el1
297  *
298  * AP Current Cache Size ID Register
299  * This register provides information about the architecture of the currently selected
300  * cache. AP_CSSELR_EL1 selects which Cache Size ID Register is accessible.
301  */
302 union bdk_ap_ccsidr_el1
303 {
304     uint32_t u;
305     struct bdk_ap_ccsidr_el1_s
306     {
307 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
308         uint32_t wt                    : 1;  /**< [ 31: 31](RO) Indicates whether the selected cache level supports write-through.
309                                                                  0 = Write-through not supported.
310                                                                  1 = Write-through supported.
311 
312                                                                  For CNXXXX does not apply as hardware managed coherence. */
313         uint32_t wb                    : 1;  /**< [ 30: 30](RO) Indicates whether the selected cache level supports write-back.
314                                                                  0 = Write-back not supported.
315                                                                  1 = Write-back supported.
316 
317                                                                  For CNXXXX does not apply as hardware managed coherence. */
318         uint32_t ra                    : 1;  /**< [ 29: 29](RO) Indicates whether the selected cache level supports read-allocation.
319                                                                  0 = Read-allocation not supported.
320                                                                  1 = Read-allocation supported.
321 
322                                                                  For CNXXXX does not apply as hardware managed coherence. */
323         uint32_t wa                    : 1;  /**< [ 28: 28](RO) Indicates whether the selected cache level supports write-allocation.
324                                                                  0 = Write-allocation not supported.
325                                                                  1 = Write-allocation supported.
326 
327                                                                  For CNXXXX does not apply as hardware managed coherence. */
328         uint32_t numsets               : 15; /**< [ 27: 13](RO) Number of sets in cache minus 1, therefore a value of 0
329                                                                  indicates 1 set in the cache. The number of sets does not have
330                                                                  to be a power of 2.
331 
332                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 7.
333 
334                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 15.
335 
336                                                                  For CN88XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 8191. */
337         uint32_t associativity         : 10; /**< [ 12:  3](RO) Associativity of cache minus 1, therefore a value of 0 indicates
338                                                                  an associativity of 1. The associativity does not have to be a
339                                                                  power of 2.
340 
341                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 31.
342 
343                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 38.
344 
345                                                                  For CN88XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 15. */
346         uint32_t linesize              : 3;  /**< [  2:  0](RO) Cache-line size, in (Log2(Number of bytes in cache line)) - 4.
347 
348                                                                  For CNXXXX, 128 bytes. */
349 #else /* Word 0 - Little Endian */
350         uint32_t linesize              : 3;  /**< [  2:  0](RO) Cache-line size, in (Log2(Number of bytes in cache line)) - 4.
351 
352                                                                  For CNXXXX, 128 bytes. */
353         uint32_t associativity         : 10; /**< [ 12:  3](RO) Associativity of cache minus 1, therefore a value of 0 indicates
354                                                                  an associativity of 1. The associativity does not have to be a
355                                                                  power of 2.
356 
357                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 31.
358 
359                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 38.
360 
361                                                                  For CN88XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 15. */
362         uint32_t numsets               : 15; /**< [ 27: 13](RO) Number of sets in cache minus 1, therefore a value of 0
363                                                                  indicates 1 set in the cache. The number of sets does not have
364                                                                  to be a power of 2.
365 
366                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 7.
367 
368                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 15.
369 
370                                                                  For CN88XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 8191. */
371         uint32_t wa                    : 1;  /**< [ 28: 28](RO) Indicates whether the selected cache level supports write-allocation.
372                                                                  0 = Write-allocation not supported.
373                                                                  1 = Write-allocation supported.
374 
375                                                                  For CNXXXX does not apply as hardware managed coherence. */
376         uint32_t ra                    : 1;  /**< [ 29: 29](RO) Indicates whether the selected cache level supports read-allocation.
377                                                                  0 = Read-allocation not supported.
378                                                                  1 = Read-allocation supported.
379 
380                                                                  For CNXXXX does not apply as hardware managed coherence. */
381         uint32_t wb                    : 1;  /**< [ 30: 30](RO) Indicates whether the selected cache level supports write-back.
382                                                                  0 = Write-back not supported.
383                                                                  1 = Write-back supported.
384 
385                                                                  For CNXXXX does not apply as hardware managed coherence. */
386         uint32_t wt                    : 1;  /**< [ 31: 31](RO) Indicates whether the selected cache level supports write-through.
387                                                                  0 = Write-through not supported.
388                                                                  1 = Write-through supported.
389 
390                                                                  For CNXXXX does not apply as hardware managed coherence. */
391 #endif /* Word 0 - End */
392     } s;
393     struct bdk_ap_ccsidr_el1_cn9
394     {
395 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
396         uint32_t wt                    : 1;  /**< [ 31: 31](RO) Indicates whether the selected cache level supports write-through.
397                                                                  0 = Write-through not supported.
398                                                                  1 = Write-through supported.
399 
400                                                                  For CNXXXX does not apply as hardware managed coherence. */
401         uint32_t wb                    : 1;  /**< [ 30: 30](RO) Indicates whether the selected cache level supports write-back.
402                                                                  0 = Write-back not supported.
403                                                                  1 = Write-back supported.
404 
405                                                                  For CNXXXX does not apply as hardware managed coherence. */
406         uint32_t ra                    : 1;  /**< [ 29: 29](RO) Indicates whether the selected cache level supports read-allocation.
407                                                                  0 = Read-allocation not supported.
408                                                                  1 = Read-allocation supported.
409 
410                                                                  For CNXXXX does not apply as hardware managed coherence. */
411         uint32_t wa                    : 1;  /**< [ 28: 28](RO) Indicates whether the selected cache level supports write-allocation.
412                                                                  0 = Write-allocation not supported.
413                                                                  1 = Write-allocation supported.
414 
415                                                                  For CNXXXX does not apply as hardware managed coherence. */
416         uint32_t numsets               : 15; /**< [ 27: 13](RO) Number of sets in cache minus 1, therefore a value of 0
417                                                                  indicates 1 set in the cache. The number of sets does not have
418                                                                  to be a power of 2.
419 
420                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is TBD.
421 
422                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is TBD.
423 
424                                                                  For CN98XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is TBD.
425 
426                                                                  For CN98XX L3 (AP_CSSELR_EL1[LEVEL] = 0x2, AP_CSSELR_EL1[IND] = 0), is TBD. */
427         uint32_t associativity         : 10; /**< [ 12:  3](RO) Associativity of cache minus 1, therefore a value of 0 indicates
428                                                                  an associativity of 1. The associativity does not have to be a
429                                                                  power of 2.
430 
431                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is TBD.
432 
433                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is TBD.
434 
435                                                                  For CN98XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is TBD.
436 
437                                                                  For CN98XX L3 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is TBD. */
438         uint32_t linesize              : 3;  /**< [  2:  0](RO) Cache-line size, in (Log2(Number of bytes in cache line)) - 4.
439 
440                                                                  For CNXXXX, 128 bytes. */
441 #else /* Word 0 - Little Endian */
442         uint32_t linesize              : 3;  /**< [  2:  0](RO) Cache-line size, in (Log2(Number of bytes in cache line)) - 4.
443 
444                                                                  For CNXXXX, 128 bytes. */
445         uint32_t associativity         : 10; /**< [ 12:  3](RO) Associativity of cache minus 1, therefore a value of 0 indicates
446                                                                  an associativity of 1. The associativity does not have to be a
447                                                                  power of 2.
448 
449                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is TBD.
450 
451                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is TBD.
452 
453                                                                  For CN98XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is TBD.
454 
455                                                                  For CN98XX L3 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is TBD. */
456         uint32_t numsets               : 15; /**< [ 27: 13](RO) Number of sets in cache minus 1, therefore a value of 0
457                                                                  indicates 1 set in the cache. The number of sets does not have
458                                                                  to be a power of 2.
459 
460                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is TBD.
461 
462                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is TBD.
463 
464                                                                  For CN98XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is TBD.
465 
466                                                                  For CN98XX L3 (AP_CSSELR_EL1[LEVEL] = 0x2, AP_CSSELR_EL1[IND] = 0), is TBD. */
467         uint32_t wa                    : 1;  /**< [ 28: 28](RO) Indicates whether the selected cache level supports write-allocation.
468                                                                  0 = Write-allocation not supported.
469                                                                  1 = Write-allocation supported.
470 
471                                                                  For CNXXXX does not apply as hardware managed coherence. */
472         uint32_t ra                    : 1;  /**< [ 29: 29](RO) Indicates whether the selected cache level supports read-allocation.
473                                                                  0 = Read-allocation not supported.
474                                                                  1 = Read-allocation supported.
475 
476                                                                  For CNXXXX does not apply as hardware managed coherence. */
477         uint32_t wb                    : 1;  /**< [ 30: 30](RO) Indicates whether the selected cache level supports write-back.
478                                                                  0 = Write-back not supported.
479                                                                  1 = Write-back supported.
480 
481                                                                  For CNXXXX does not apply as hardware managed coherence. */
482         uint32_t wt                    : 1;  /**< [ 31: 31](RO) Indicates whether the selected cache level supports write-through.
483                                                                  0 = Write-through not supported.
484                                                                  1 = Write-through supported.
485 
486                                                                  For CNXXXX does not apply as hardware managed coherence. */
487 #endif /* Word 0 - End */
488     } cn9;
489     struct bdk_ap_ccsidr_el1_cn81xx
490     {
491 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
492         uint32_t wt                    : 1;  /**< [ 31: 31](RO) Indicates whether the selected cache level supports write-through.
493                                                                  0 = Write-through not supported.
494                                                                  1 = Write-through supported.
495 
496                                                                  For CNXXXX does not apply as hardware managed coherence. */
497         uint32_t wb                    : 1;  /**< [ 30: 30](RO) Indicates whether the selected cache level supports write-back.
498                                                                  0 = Write-back not supported.
499                                                                  1 = Write-back supported.
500 
501                                                                  For CNXXXX does not apply as hardware managed coherence. */
502         uint32_t ra                    : 1;  /**< [ 29: 29](RO) Indicates whether the selected cache level supports read-allocation.
503                                                                  0 = Read-allocation not supported.
504                                                                  1 = Read-allocation supported.
505 
506                                                                  For CNXXXX does not apply as hardware managed coherence. */
507         uint32_t wa                    : 1;  /**< [ 28: 28](RO) Indicates whether the selected cache level supports write-allocation.
508                                                                  0 = Write-allocation not supported.
509                                                                  1 = Write-allocation supported.
510 
511                                                                  For CNXXXX does not apply as hardware managed coherence. */
512         uint32_t numsets               : 15; /**< [ 27: 13](RO) Number of sets in cache minus 1, therefore a value of 0
513                                                                  indicates 1 set in the cache. The number of sets does not have
514                                                                  to be a power of 2.
515 
516                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 7.
517 
518                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 15.
519 
520                                                                  For CN81XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 1023.
521 
522                                                                  For CN80XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 1023. */
523         uint32_t associativity         : 10; /**< [ 12:  3](RO) Associativity of cache minus 1, therefore a value of 0 indicates
524                                                                  an associativity of 1. The associativity does not have to be a
525                                                                  power of 2.
526 
527                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 31.
528 
529                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 38.
530 
531                                                                  For CN81XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 15.
532 
533                                                                  For CN80XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 7. */
534         uint32_t linesize              : 3;  /**< [  2:  0](RO) Cache-line size, in (Log2(Number of bytes in cache line)) - 4.
535 
536                                                                  For CNXXXX, 128 bytes. */
537 #else /* Word 0 - Little Endian */
538         uint32_t linesize              : 3;  /**< [  2:  0](RO) Cache-line size, in (Log2(Number of bytes in cache line)) - 4.
539 
540                                                                  For CNXXXX, 128 bytes. */
541         uint32_t associativity         : 10; /**< [ 12:  3](RO) Associativity of cache minus 1, therefore a value of 0 indicates
542                                                                  an associativity of 1. The associativity does not have to be a
543                                                                  power of 2.
544 
545                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 31.
546 
547                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 38.
548 
549                                                                  For CN81XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 15.
550 
551                                                                  For CN80XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 7. */
552         uint32_t numsets               : 15; /**< [ 27: 13](RO) Number of sets in cache minus 1, therefore a value of 0
553                                                                  indicates 1 set in the cache. The number of sets does not have
554                                                                  to be a power of 2.
555 
556                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 7.
557 
558                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 15.
559 
560                                                                  For CN81XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 1023.
561 
562                                                                  For CN80XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 1023. */
563         uint32_t wa                    : 1;  /**< [ 28: 28](RO) Indicates whether the selected cache level supports write-allocation.
564                                                                  0 = Write-allocation not supported.
565                                                                  1 = Write-allocation supported.
566 
567                                                                  For CNXXXX does not apply as hardware managed coherence. */
568         uint32_t ra                    : 1;  /**< [ 29: 29](RO) Indicates whether the selected cache level supports read-allocation.
569                                                                  0 = Read-allocation not supported.
570                                                                  1 = Read-allocation supported.
571 
572                                                                  For CNXXXX does not apply as hardware managed coherence. */
573         uint32_t wb                    : 1;  /**< [ 30: 30](RO) Indicates whether the selected cache level supports write-back.
574                                                                  0 = Write-back not supported.
575                                                                  1 = Write-back supported.
576 
577                                                                  For CNXXXX does not apply as hardware managed coherence. */
578         uint32_t wt                    : 1;  /**< [ 31: 31](RO) Indicates whether the selected cache level supports write-through.
579                                                                  0 = Write-through not supported.
580                                                                  1 = Write-through supported.
581 
582                                                                  For CNXXXX does not apply as hardware managed coherence. */
583 #endif /* Word 0 - End */
584     } cn81xx;
585     /* struct bdk_ap_ccsidr_el1_s cn88xx; */
586     struct bdk_ap_ccsidr_el1_cn83xx
587     {
588 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
589         uint32_t wt                    : 1;  /**< [ 31: 31](RO) Indicates whether the selected cache level supports write-through.
590                                                                  0 = Write-through not supported.
591                                                                  1 = Write-through supported.
592 
593                                                                  For CNXXXX does not apply as hardware managed coherence. */
594         uint32_t wb                    : 1;  /**< [ 30: 30](RO) Indicates whether the selected cache level supports write-back.
595                                                                  0 = Write-back not supported.
596                                                                  1 = Write-back supported.
597 
598                                                                  For CNXXXX does not apply as hardware managed coherence. */
599         uint32_t ra                    : 1;  /**< [ 29: 29](RO) Indicates whether the selected cache level supports read-allocation.
600                                                                  0 = Read-allocation not supported.
601                                                                  1 = Read-allocation supported.
602 
603                                                                  For CNXXXX does not apply as hardware managed coherence. */
604         uint32_t wa                    : 1;  /**< [ 28: 28](RO) Indicates whether the selected cache level supports write-allocation.
605                                                                  0 = Write-allocation not supported.
606                                                                  1 = Write-allocation supported.
607 
608                                                                  For CNXXXX does not apply as hardware managed coherence. */
609         uint32_t numsets               : 15; /**< [ 27: 13](RO) Number of sets in cache minus 1, therefore a value of 0
610                                                                  indicates 1 set in the cache. The number of sets does not have
611                                                                  to be a power of 2.
612 
613                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 7.
614 
615                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 15.
616 
617                                                                  For CN83XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 4095. */
618         uint32_t associativity         : 10; /**< [ 12:  3](RO) Associativity of cache minus 1, therefore a value of 0 indicates
619                                                                  an associativity of 1. The associativity does not have to be a
620                                                                  power of 2.
621 
622                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 31.
623 
624                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 38.
625 
626                                                                  For CN83XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 15. */
627         uint32_t linesize              : 3;  /**< [  2:  0](RO) Cache-line size, in (Log2(Number of bytes in cache line)) - 4.
628 
629                                                                  For CNXXXX, 128 bytes. */
630 #else /* Word 0 - Little Endian */
631         uint32_t linesize              : 3;  /**< [  2:  0](RO) Cache-line size, in (Log2(Number of bytes in cache line)) - 4.
632 
633                                                                  For CNXXXX, 128 bytes. */
634         uint32_t associativity         : 10; /**< [ 12:  3](RO) Associativity of cache minus 1, therefore a value of 0 indicates
635                                                                  an associativity of 1. The associativity does not have to be a
636                                                                  power of 2.
637 
638                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 31.
639 
640                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 38.
641 
642                                                                  For CN83XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 15. */
643         uint32_t numsets               : 15; /**< [ 27: 13](RO) Number of sets in cache minus 1, therefore a value of 0
644                                                                  indicates 1 set in the cache. The number of sets does not have
645                                                                  to be a power of 2.
646 
647                                                                  For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 7.
648 
649                                                                  For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 15.
650 
651                                                                  For CN83XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 4095. */
652         uint32_t wa                    : 1;  /**< [ 28: 28](RO) Indicates whether the selected cache level supports write-allocation.
653                                                                  0 = Write-allocation not supported.
654                                                                  1 = Write-allocation supported.
655 
656                                                                  For CNXXXX does not apply as hardware managed coherence. */
657         uint32_t ra                    : 1;  /**< [ 29: 29](RO) Indicates whether the selected cache level supports read-allocation.
658                                                                  0 = Read-allocation not supported.
659                                                                  1 = Read-allocation supported.
660 
661                                                                  For CNXXXX does not apply as hardware managed coherence. */
662         uint32_t wb                    : 1;  /**< [ 30: 30](RO) Indicates whether the selected cache level supports write-back.
663                                                                  0 = Write-back not supported.
664                                                                  1 = Write-back supported.
665 
666                                                                  For CNXXXX does not apply as hardware managed coherence. */
667         uint32_t wt                    : 1;  /**< [ 31: 31](RO) Indicates whether the selected cache level supports write-through.
668                                                                  0 = Write-through not supported.
669                                                                  1 = Write-through supported.
670 
671                                                                  For CNXXXX does not apply as hardware managed coherence. */
672 #endif /* Word 0 - End */
673     } cn83xx;
674 };
675 typedef union bdk_ap_ccsidr_el1 bdk_ap_ccsidr_el1_t;
676 
677 #define BDK_AP_CCSIDR_EL1 BDK_AP_CCSIDR_EL1_FUNC()
678 static inline uint64_t BDK_AP_CCSIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CCSIDR_EL1_FUNC(void)679 static inline uint64_t BDK_AP_CCSIDR_EL1_FUNC(void)
680 {
681     return 0x30100000000ll;
682 }
683 
684 #define typedef_BDK_AP_CCSIDR_EL1 bdk_ap_ccsidr_el1_t
685 #define bustype_BDK_AP_CCSIDR_EL1 BDK_CSR_TYPE_SYSREG
686 #define basename_BDK_AP_CCSIDR_EL1 "AP_CCSIDR_EL1"
687 #define busnum_BDK_AP_CCSIDR_EL1 0
688 #define arguments_BDK_AP_CCSIDR_EL1 -1,-1,-1,-1
689 
690 /**
691  * Register (SYSREG) ap_clidr_el1
692  *
693  * AP Cache Level ID Register
694  * This register identifies the type of cache, or caches, implemented at each level, up
695  * to a maximum of seven levels. Also identifies the Level of Coherence (LoC) and Level
696  * of Unification (LoU) for the cache hierarchy.
697  */
698 union bdk_ap_clidr_el1
699 {
700     uint32_t u;
701     struct bdk_ap_clidr_el1_s
702     {
703 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
704         uint32_t reserved_30_31        : 2;
705         uint32_t louu                  : 3;  /**< [ 29: 27](RO) Level of unification uniprocessor for the cache hierarchy. */
706         uint32_t loc                   : 3;  /**< [ 26: 24](RO) Level of coherence for the cache hierarchy.
707 
708                                                                  For CN88XX, 0x1 for pass 1, 0x0 for pass 2 and subsequent chips. */
709         uint32_t louis                 : 3;  /**< [ 23: 21](RO) Level of unification inner shareable for the cache hierarchy. */
710         uint32_t ctype7                : 3;  /**< [ 20: 18](RO) Cache type fields. Indicate the type of cache implemented at
711                                                                      each level, from Level 1 up to a maximum of seven levels of
712                                                                      cache hierarchy.
713                                                                  0x0 = No cache.
714                                                                  0x1 = Instruction cache only.
715                                                                  0x2 = Data cache only.
716                                                                  0x3 = Separate instruction and data caches.
717                                                                  0x4 = Unified cache.
718 
719                                                                  All other values are reserved.
720 
721                                                                  For CNXXXX, no L7 cache. */
722         uint32_t ctype6                : 3;  /**< [ 17: 15](RO) Cache type fields. Indicate the type of cache implemented at
723                                                                      each level, from Level 1 up to a maximum of seven levels of
724                                                                      cache hierarchy.
725                                                                  0x0 = No cache.
726                                                                  0x1 = Instruction cache only.
727                                                                  0x2 = Data cache only.
728                                                                  0x3 = Separate instruction and data caches.
729                                                                  0x4 = Unified cache.
730 
731                                                                  For CNXXXX, no L6 cache. */
732         uint32_t ctype5                : 3;  /**< [ 14: 12](RO) Cache type fields. Indicate the type of cache implemented at
733                                                                      each level, from Level 1 up to a maximum of seven levels of
734                                                                      cache hierarchy.
735                                                                  0x0 = No cache.
736                                                                  0x1 = Instruction cache only.
737                                                                  0x2 = Data cache only.
738                                                                  0x3 = Separate instruction and data caches.
739                                                                  0x4 = Unified cache.
740 
741                                                                  For CNXXXX, no L5 cache. */
742         uint32_t ctype4                : 3;  /**< [ 11:  9](RO) Cache type fields. Indicate the type of cache implemented at
743                                                                      each level, from Level 1 up to a maximum of seven levels of
744                                                                      cache hierarchy.
745                                                                  0x0 = No cache.
746                                                                  0x1 = Instruction cache only.
747                                                                  0x2 = Data cache only.
748                                                                  0x3 = Separate instruction and data caches.
749                                                                  0x4 = Unified cache.
750 
751                                                                  For CNXXXX, no L4 cache. */
752         uint32_t ctype3                : 3;  /**< [  8:  6](RO) Cache type fields. Indicate the type of cache implemented at
753                                                                      each level, from Level 1 up to a maximum of seven levels of
754                                                                      cache hierarchy.
755                                                                  0x0 = No cache.
756                                                                  0x1 = Instruction cache only.
757                                                                  0x2 = Data cache only.
758                                                                  0x3 = Separate instruction and data caches.
759                                                                  0x4 = Unified cache.
760 
761                                                                  For CNXXXX, no L3 cache. */
762         uint32_t ctype2                : 3;  /**< [  5:  3](RO) Cache type fields. Indicate the type of cache implemented at
763                                                                      each level, from Level 1 up to a maximum of seven levels of
764                                                                      cache hierarchy.
765                                                                  0x0 = No cache.
766                                                                  0x1 = Instruction cache only.
767                                                                  0x2 = Data cache only.
768                                                                  0x3 = Separate instruction and data caches.
769                                                                  0x4 = Unified cache.
770 
771                                                                  For CNXXXX, L2 cache is unified. */
772         uint32_t ctype1                : 3;  /**< [  2:  0](RO) Cache type fields. Indicate the type of cache implemented at
773                                                                      each level, from Level 1 up to a maximum of seven levels of
774                                                                      cache hierarchy.
775                                                                  0x0 = No cache.
776                                                                  0x1 = Instruction cache only.
777                                                                  0x2 = Data cache only.
778                                                                  0x3 = Separate instruction and data caches.
779                                                                  0x4 = Unified cache.
780 
781                                                                  For CNXXXX, L1 Dcache and Icache are independent. */
782 #else /* Word 0 - Little Endian */
783         uint32_t ctype1                : 3;  /**< [  2:  0](RO) Cache type fields. Indicate the type of cache implemented at
784                                                                      each level, from Level 1 up to a maximum of seven levels of
785                                                                      cache hierarchy.
786                                                                  0x0 = No cache.
787                                                                  0x1 = Instruction cache only.
788                                                                  0x2 = Data cache only.
789                                                                  0x3 = Separate instruction and data caches.
790                                                                  0x4 = Unified cache.
791 
792                                                                  For CNXXXX, L1 Dcache and Icache are independent. */
793         uint32_t ctype2                : 3;  /**< [  5:  3](RO) Cache type fields. Indicate the type of cache implemented at
794                                                                      each level, from Level 1 up to a maximum of seven levels of
795                                                                      cache hierarchy.
796                                                                  0x0 = No cache.
797                                                                  0x1 = Instruction cache only.
798                                                                  0x2 = Data cache only.
799                                                                  0x3 = Separate instruction and data caches.
800                                                                  0x4 = Unified cache.
801 
802                                                                  For CNXXXX, L2 cache is unified. */
803         uint32_t ctype3                : 3;  /**< [  8:  6](RO) Cache type fields. Indicate the type of cache implemented at
804                                                                      each level, from Level 1 up to a maximum of seven levels of
805                                                                      cache hierarchy.
806                                                                  0x0 = No cache.
807                                                                  0x1 = Instruction cache only.
808                                                                  0x2 = Data cache only.
809                                                                  0x3 = Separate instruction and data caches.
810                                                                  0x4 = Unified cache.
811 
812                                                                  For CNXXXX, no L3 cache. */
813         uint32_t ctype4                : 3;  /**< [ 11:  9](RO) Cache type fields. Indicate the type of cache implemented at
814                                                                      each level, from Level 1 up to a maximum of seven levels of
815                                                                      cache hierarchy.
816                                                                  0x0 = No cache.
817                                                                  0x1 = Instruction cache only.
818                                                                  0x2 = Data cache only.
819                                                                  0x3 = Separate instruction and data caches.
820                                                                  0x4 = Unified cache.
821 
822                                                                  For CNXXXX, no L4 cache. */
823         uint32_t ctype5                : 3;  /**< [ 14: 12](RO) Cache type fields. Indicate the type of cache implemented at
824                                                                      each level, from Level 1 up to a maximum of seven levels of
825                                                                      cache hierarchy.
826                                                                  0x0 = No cache.
827                                                                  0x1 = Instruction cache only.
828                                                                  0x2 = Data cache only.
829                                                                  0x3 = Separate instruction and data caches.
830                                                                  0x4 = Unified cache.
831 
832                                                                  For CNXXXX, no L5 cache. */
833         uint32_t ctype6                : 3;  /**< [ 17: 15](RO) Cache type fields. Indicate the type of cache implemented at
834                                                                      each level, from Level 1 up to a maximum of seven levels of
835                                                                      cache hierarchy.
836                                                                  0x0 = No cache.
837                                                                  0x1 = Instruction cache only.
838                                                                  0x2 = Data cache only.
839                                                                  0x3 = Separate instruction and data caches.
840                                                                  0x4 = Unified cache.
841 
842                                                                  For CNXXXX, no L6 cache. */
843         uint32_t ctype7                : 3;  /**< [ 20: 18](RO) Cache type fields. Indicate the type of cache implemented at
844                                                                      each level, from Level 1 up to a maximum of seven levels of
845                                                                      cache hierarchy.
846                                                                  0x0 = No cache.
847                                                                  0x1 = Instruction cache only.
848                                                                  0x2 = Data cache only.
849                                                                  0x3 = Separate instruction and data caches.
850                                                                  0x4 = Unified cache.
851 
852                                                                  All other values are reserved.
853 
854                                                                  For CNXXXX, no L7 cache. */
855         uint32_t louis                 : 3;  /**< [ 23: 21](RO) Level of unification inner shareable for the cache hierarchy. */
856         uint32_t loc                   : 3;  /**< [ 26: 24](RO) Level of coherence for the cache hierarchy.
857 
858                                                                  For CN88XX, 0x1 for pass 1, 0x0 for pass 2 and subsequent chips. */
859         uint32_t louu                  : 3;  /**< [ 29: 27](RO) Level of unification uniprocessor for the cache hierarchy. */
860         uint32_t reserved_30_31        : 2;
861 #endif /* Word 0 - End */
862     } s;
863     struct bdk_ap_clidr_el1_cn9
864     {
865 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
866         uint32_t reserved_30_31        : 2;
867         uint32_t louu                  : 3;  /**< [ 29: 27](RO) Level of unification uniprocessor for the cache hierarchy. */
868         uint32_t loc                   : 3;  /**< [ 26: 24](RO) Level of coherence for the cache hierarchy.
869 
870                                                                  For CNXXXX, 0x0. */
871         uint32_t louis                 : 3;  /**< [ 23: 21](RO) Level of unification inner shareable for the cache hierarchy. */
872         uint32_t ctype7                : 3;  /**< [ 20: 18](RO) Cache type fields. Indicate the type of cache implemented at
873                                                                      each level, from Level 1 up to a maximum of seven levels of
874                                                                      cache hierarchy.
875 
876                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
877 
878                                                                  For CNXXXX, no L7 cache. */
879         uint32_t ctype6                : 3;  /**< [ 17: 15](RO) Cache type fields. Indicate the type of cache implemented at
880                                                                      each level, from Level 1 up to a maximum of seven levels of
881                                                                      cache hierarchy.
882 
883                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
884 
885                                                                  For CNXXXX, no L6 cache. */
886         uint32_t ctype5                : 3;  /**< [ 14: 12](RO) Cache type fields. Indicate the type of cache implemented at
887                                                                      each level, from Level 1 up to a maximum of seven levels of
888                                                                      cache hierarchy.
889 
890                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
891 
892                                                                  For CNXXXX, no L5 cache. */
893         uint32_t ctype4                : 3;  /**< [ 11:  9](RO) Cache type fields. Indicate the type of cache implemented at
894                                                                      each level, from Level 1 up to a maximum of seven levels of
895                                                                      cache hierarchy.
896 
897                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
898 
899                                                                  For CNXXXX, no L4 cache. */
900         uint32_t ctype3                : 3;  /**< [  8:  6](RO) Cache type fields. Indicate the type of cache implemented at
901                                                                      each level, from Level 1 up to a maximum of seven levels of
902                                                                      cache hierarchy.
903 
904                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
905 
906                                                                  For CNXXXX, L3 cache is unified. */
907         uint32_t ctype2                : 3;  /**< [  5:  3](RO) Cache type fields. Indicate the type of cache implemented at
908                                                                      each level, from Level 1 up to a maximum of seven levels of
909                                                                      cache hierarchy.
910 
911                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
912 
913                                                                  For CNXXXX, L2 cache is an instruction cache only.
914 
915                                                                  Internal:
916                                                                  L2 can be NONE if fused-off. */
917         uint32_t ctype1                : 3;  /**< [  2:  0](RO) Cache type fields. Indicate the type of cache implemented at
918                                                                      each level, from Level 1 up to a maximum of seven levels of
919                                                                      cache hierarchy.
920 
921                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
922 
923                                                                  For CNXXXX, L1 Dcache and Icache are independent. */
924 #else /* Word 0 - Little Endian */
925         uint32_t ctype1                : 3;  /**< [  2:  0](RO) Cache type fields. Indicate the type of cache implemented at
926                                                                      each level, from Level 1 up to a maximum of seven levels of
927                                                                      cache hierarchy.
928 
929                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
930 
931                                                                  For CNXXXX, L1 Dcache and Icache are independent. */
932         uint32_t ctype2                : 3;  /**< [  5:  3](RO) Cache type fields. Indicate the type of cache implemented at
933                                                                      each level, from Level 1 up to a maximum of seven levels of
934                                                                      cache hierarchy.
935 
936                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
937 
938                                                                  For CNXXXX, L2 cache is an instruction cache only.
939 
940                                                                  Internal:
941                                                                  L2 can be NONE if fused-off. */
942         uint32_t ctype3                : 3;  /**< [  8:  6](RO) Cache type fields. Indicate the type of cache implemented at
943                                                                      each level, from Level 1 up to a maximum of seven levels of
944                                                                      cache hierarchy.
945 
946                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
947 
948                                                                  For CNXXXX, L3 cache is unified. */
949         uint32_t ctype4                : 3;  /**< [ 11:  9](RO) Cache type fields. Indicate the type of cache implemented at
950                                                                      each level, from Level 1 up to a maximum of seven levels of
951                                                                      cache hierarchy.
952 
953                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
954 
955                                                                  For CNXXXX, no L4 cache. */
956         uint32_t ctype5                : 3;  /**< [ 14: 12](RO) Cache type fields. Indicate the type of cache implemented at
957                                                                      each level, from Level 1 up to a maximum of seven levels of
958                                                                      cache hierarchy.
959 
960                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
961 
962                                                                  For CNXXXX, no L5 cache. */
963         uint32_t ctype6                : 3;  /**< [ 17: 15](RO) Cache type fields. Indicate the type of cache implemented at
964                                                                      each level, from Level 1 up to a maximum of seven levels of
965                                                                      cache hierarchy.
966 
967                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
968 
969                                                                  For CNXXXX, no L6 cache. */
970         uint32_t ctype7                : 3;  /**< [ 20: 18](RO) Cache type fields. Indicate the type of cache implemented at
971                                                                      each level, from Level 1 up to a maximum of seven levels of
972                                                                      cache hierarchy.
973 
974                                                                  Enumerated by AP_CLIDR_EL1_CTYPE_E.
975 
976                                                                  For CNXXXX, no L7 cache. */
977         uint32_t louis                 : 3;  /**< [ 23: 21](RO) Level of unification inner shareable for the cache hierarchy. */
978         uint32_t loc                   : 3;  /**< [ 26: 24](RO) Level of coherence for the cache hierarchy.
979 
980                                                                  For CNXXXX, 0x0. */
981         uint32_t louu                  : 3;  /**< [ 29: 27](RO) Level of unification uniprocessor for the cache hierarchy. */
982         uint32_t reserved_30_31        : 2;
983 #endif /* Word 0 - End */
984     } cn9;
985     struct bdk_ap_clidr_el1_cn81xx
986     {
987 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
988         uint32_t reserved_30_31        : 2;
989         uint32_t louu                  : 3;  /**< [ 29: 27](RO) Level of unification uniprocessor for the cache hierarchy. */
990         uint32_t loc                   : 3;  /**< [ 26: 24](RO) Level of coherence for the cache hierarchy.
991 
992                                                                  For CNXXXX, 0x0. */
993         uint32_t louis                 : 3;  /**< [ 23: 21](RO) Level of unification inner shareable for the cache hierarchy. */
994         uint32_t ctype7                : 3;  /**< [ 20: 18](RO) Cache type fields. Indicate the type of cache implemented at
995                                                                      each level, from Level 1 up to a maximum of seven levels of
996                                                                      cache hierarchy.
997                                                                  0x0 = No cache.
998                                                                  0x1 = Instruction cache only.
999                                                                  0x2 = Data cache only.
1000                                                                  0x3 = Separate instruction and data caches.
1001                                                                  0x4 = Unified cache.
1002 
1003                                                                  All other values are reserved.
1004 
1005                                                                  For CNXXXX, no L7 cache. */
1006         uint32_t ctype6                : 3;  /**< [ 17: 15](RO) Cache type fields. Indicate the type of cache implemented at
1007                                                                      each level, from Level 1 up to a maximum of seven levels of
1008                                                                      cache hierarchy.
1009                                                                  0x0 = No cache.
1010                                                                  0x1 = Instruction cache only.
1011                                                                  0x2 = Data cache only.
1012                                                                  0x3 = Separate instruction and data caches.
1013                                                                  0x4 = Unified cache.
1014 
1015                                                                  For CNXXXX, no L6 cache. */
1016         uint32_t ctype5                : 3;  /**< [ 14: 12](RO) Cache type fields. Indicate the type of cache implemented at
1017                                                                      each level, from Level 1 up to a maximum of seven levels of
1018                                                                      cache hierarchy.
1019                                                                  0x0 = No cache.
1020                                                                  0x1 = Instruction cache only.
1021                                                                  0x2 = Data cache only.
1022                                                                  0x3 = Separate instruction and data caches.
1023                                                                  0x4 = Unified cache.
1024 
1025                                                                  For CNXXXX, no L5 cache. */
1026         uint32_t ctype4                : 3;  /**< [ 11:  9](RO) Cache type fields. Indicate the type of cache implemented at
1027                                                                      each level, from Level 1 up to a maximum of seven levels of
1028                                                                      cache hierarchy.
1029                                                                  0x0 = No cache.
1030                                                                  0x1 = Instruction cache only.
1031                                                                  0x2 = Data cache only.
1032                                                                  0x3 = Separate instruction and data caches.
1033                                                                  0x4 = Unified cache.
1034 
1035                                                                  For CNXXXX, no L4 cache. */
1036         uint32_t ctype3                : 3;  /**< [  8:  6](RO) Cache type fields. Indicate the type of cache implemented at
1037                                                                      each level, from Level 1 up to a maximum of seven levels of
1038                                                                      cache hierarchy.
1039                                                                  0x0 = No cache.
1040                                                                  0x1 = Instruction cache only.
1041                                                                  0x2 = Data cache only.
1042                                                                  0x3 = Separate instruction and data caches.
1043                                                                  0x4 = Unified cache.
1044 
1045                                                                  For CNXXXX, no L3 cache. */
1046         uint32_t ctype2                : 3;  /**< [  5:  3](RO) Cache type fields. Indicate the type of cache implemented at
1047                                                                      each level, from Level 1 up to a maximum of seven levels of
1048                                                                      cache hierarchy.
1049                                                                  0x0 = No cache.
1050                                                                  0x1 = Instruction cache only.
1051                                                                  0x2 = Data cache only.
1052                                                                  0x3 = Separate instruction and data caches.
1053                                                                  0x4 = Unified cache.
1054 
1055                                                                  For CNXXXX, L2 cache is unified. */
1056         uint32_t ctype1                : 3;  /**< [  2:  0](RO) Cache type fields. Indicate the type of cache implemented at
1057                                                                      each level, from Level 1 up to a maximum of seven levels of
1058                                                                      cache hierarchy.
1059                                                                  0x0 = No cache.
1060                                                                  0x1 = Instruction cache only.
1061                                                                  0x2 = Data cache only.
1062                                                                  0x3 = Separate instruction and data caches.
1063                                                                  0x4 = Unified cache.
1064 
1065                                                                  For CNXXXX, L1 Dcache and Icache are independent. */
1066 #else /* Word 0 - Little Endian */
1067         uint32_t ctype1                : 3;  /**< [  2:  0](RO) Cache type fields. Indicate the type of cache implemented at
1068                                                                      each level, from Level 1 up to a maximum of seven levels of
1069                                                                      cache hierarchy.
1070                                                                  0x0 = No cache.
1071                                                                  0x1 = Instruction cache only.
1072                                                                  0x2 = Data cache only.
1073                                                                  0x3 = Separate instruction and data caches.
1074                                                                  0x4 = Unified cache.
1075 
1076                                                                  For CNXXXX, L1 Dcache and Icache are independent. */
1077         uint32_t ctype2                : 3;  /**< [  5:  3](RO) Cache type fields. Indicate the type of cache implemented at
1078                                                                      each level, from Level 1 up to a maximum of seven levels of
1079                                                                      cache hierarchy.
1080                                                                  0x0 = No cache.
1081                                                                  0x1 = Instruction cache only.
1082                                                                  0x2 = Data cache only.
1083                                                                  0x3 = Separate instruction and data caches.
1084                                                                  0x4 = Unified cache.
1085 
1086                                                                  For CNXXXX, L2 cache is unified. */
1087         uint32_t ctype3                : 3;  /**< [  8:  6](RO) Cache type fields. Indicate the type of cache implemented at
1088                                                                      each level, from Level 1 up to a maximum of seven levels of
1089                                                                      cache hierarchy.
1090                                                                  0x0 = No cache.
1091                                                                  0x1 = Instruction cache only.
1092                                                                  0x2 = Data cache only.
1093                                                                  0x3 = Separate instruction and data caches.
1094                                                                  0x4 = Unified cache.
1095 
1096                                                                  For CNXXXX, no L3 cache. */
1097         uint32_t ctype4                : 3;  /**< [ 11:  9](RO) Cache type fields. Indicate the type of cache implemented at
1098                                                                      each level, from Level 1 up to a maximum of seven levels of
1099                                                                      cache hierarchy.
1100                                                                  0x0 = No cache.
1101                                                                  0x1 = Instruction cache only.
1102                                                                  0x2 = Data cache only.
1103                                                                  0x3 = Separate instruction and data caches.
1104                                                                  0x4 = Unified cache.
1105 
1106                                                                  For CNXXXX, no L4 cache. */
1107         uint32_t ctype5                : 3;  /**< [ 14: 12](RO) Cache type fields. Indicate the type of cache implemented at
1108                                                                      each level, from Level 1 up to a maximum of seven levels of
1109                                                                      cache hierarchy.
1110                                                                  0x0 = No cache.
1111                                                                  0x1 = Instruction cache only.
1112                                                                  0x2 = Data cache only.
1113                                                                  0x3 = Separate instruction and data caches.
1114                                                                  0x4 = Unified cache.
1115 
1116                                                                  For CNXXXX, no L5 cache. */
1117         uint32_t ctype6                : 3;  /**< [ 17: 15](RO) Cache type fields. Indicate the type of cache implemented at
1118                                                                      each level, from Level 1 up to a maximum of seven levels of
1119                                                                      cache hierarchy.
1120                                                                  0x0 = No cache.
1121                                                                  0x1 = Instruction cache only.
1122                                                                  0x2 = Data cache only.
1123                                                                  0x3 = Separate instruction and data caches.
1124                                                                  0x4 = Unified cache.
1125 
1126                                                                  For CNXXXX, no L6 cache. */
1127         uint32_t ctype7                : 3;  /**< [ 20: 18](RO) Cache type fields. Indicate the type of cache implemented at
1128                                                                      each level, from Level 1 up to a maximum of seven levels of
1129                                                                      cache hierarchy.
1130                                                                  0x0 = No cache.
1131                                                                  0x1 = Instruction cache only.
1132                                                                  0x2 = Data cache only.
1133                                                                  0x3 = Separate instruction and data caches.
1134                                                                  0x4 = Unified cache.
1135 
1136                                                                  All other values are reserved.
1137 
1138                                                                  For CNXXXX, no L7 cache. */
1139         uint32_t louis                 : 3;  /**< [ 23: 21](RO) Level of unification inner shareable for the cache hierarchy. */
1140         uint32_t loc                   : 3;  /**< [ 26: 24](RO) Level of coherence for the cache hierarchy.
1141 
1142                                                                  For CNXXXX, 0x0. */
1143         uint32_t louu                  : 3;  /**< [ 29: 27](RO) Level of unification uniprocessor for the cache hierarchy. */
1144         uint32_t reserved_30_31        : 2;
1145 #endif /* Word 0 - End */
1146     } cn81xx;
1147     /* struct bdk_ap_clidr_el1_s cn88xx; */
1148     /* struct bdk_ap_clidr_el1_cn81xx cn83xx; */
1149 };
1150 typedef union bdk_ap_clidr_el1 bdk_ap_clidr_el1_t;
1151 
1152 #define BDK_AP_CLIDR_EL1 BDK_AP_CLIDR_EL1_FUNC()
1153 static inline uint64_t BDK_AP_CLIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CLIDR_EL1_FUNC(void)1154 static inline uint64_t BDK_AP_CLIDR_EL1_FUNC(void)
1155 {
1156     return 0x30100000100ll;
1157 }
1158 
1159 #define typedef_BDK_AP_CLIDR_EL1 bdk_ap_clidr_el1_t
1160 #define bustype_BDK_AP_CLIDR_EL1 BDK_CSR_TYPE_SYSREG
1161 #define basename_BDK_AP_CLIDR_EL1 "AP_CLIDR_EL1"
1162 #define busnum_BDK_AP_CLIDR_EL1 0
1163 #define arguments_BDK_AP_CLIDR_EL1 -1,-1,-1,-1
1164 
1165 /**
1166  * Register (SYSREG) ap_cntfrq_el0
1167  *
1168  * AP Counter-timer Frequency Register
1169  * Holds the clock frequency of the system counter.
1170  */
1171 union bdk_ap_cntfrq_el0
1172 {
1173     uint32_t u;
1174     struct bdk_ap_cntfrq_el0_s
1175     {
1176 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1177         uint32_t data                  : 32; /**< [ 31:  0](R/W) Clock frequency. Indicates the system counter clock frequency,
1178                                                                      in Hz. */
1179 #else /* Word 0 - Little Endian */
1180         uint32_t data                  : 32; /**< [ 31:  0](R/W) Clock frequency. Indicates the system counter clock frequency,
1181                                                                      in Hz. */
1182 #endif /* Word 0 - End */
1183     } s;
1184     /* struct bdk_ap_cntfrq_el0_s cn; */
1185 };
1186 typedef union bdk_ap_cntfrq_el0 bdk_ap_cntfrq_el0_t;
1187 
1188 #define BDK_AP_CNTFRQ_EL0 BDK_AP_CNTFRQ_EL0_FUNC()
1189 static inline uint64_t BDK_AP_CNTFRQ_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTFRQ_EL0_FUNC(void)1190 static inline uint64_t BDK_AP_CNTFRQ_EL0_FUNC(void)
1191 {
1192     return 0x3030e000000ll;
1193 }
1194 
1195 #define typedef_BDK_AP_CNTFRQ_EL0 bdk_ap_cntfrq_el0_t
1196 #define bustype_BDK_AP_CNTFRQ_EL0 BDK_CSR_TYPE_SYSREG
1197 #define basename_BDK_AP_CNTFRQ_EL0 "AP_CNTFRQ_EL0"
1198 #define busnum_BDK_AP_CNTFRQ_EL0 0
1199 #define arguments_BDK_AP_CNTFRQ_EL0 -1,-1,-1,-1
1200 
1201 /**
1202  * Register (SYSREG) ap_cnthctl_el2
1203  *
1204  * AP Counter-timer Hypervisor Control Non-E2H Register
1205  * Controls the generation of an event stream from the physical
1206  *     counter, and access from nonsecure EL1 to the physical
1207  *     counter and the nonsecure EL1 physical timer.
1208  *
1209  * This register is at the same select as AP_CNTHCTL_EL2_E2H and is used when E2H=0.
1210  */
1211 union bdk_ap_cnthctl_el2
1212 {
1213     uint32_t u;
1214     struct bdk_ap_cnthctl_el2_s
1215     {
1216 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1217         uint32_t reserved_8_31         : 24;
1218         uint32_t evnti                 : 4;  /**< [  7:  4](R/W) Selects which bit (0 to 15) of the corresponding counter
1219                                                                      register ( AP_CNTPCT_EL0 or AP_CNTVCT_EL0) is the trigger for the
1220                                                                      event stream generated from that counter, when that stream is
1221                                                                      enabled. */
1222         uint32_t evntdir               : 1;  /**< [  3:  3](R/W) Controls which transition of the counter register ( AP_CNTPCT_EL0
1223                                                                      or AP_CNTVCT_EL0) trigger bit, defined by EVNTI, generates an
1224                                                                      event when the event stream is enabled:
1225                                                                  0 = A 0 to 1 transition of the trigger bit triggers an event.
1226                                                                  1 = A 1 to 0 transition of the trigger bit triggers an event. */
1227         uint32_t evnten                : 1;  /**< [  2:  2](R/W) Enables the generation of an event stream from the
1228                                                                      corresponding counter:
1229                                                                  0 = Disables the event stream.
1230                                                                  1 = Enables the event stream. */
1231         uint32_t el1pcen               : 1;  /**< [  1:  1](R/W) Controls whether the physical timer registers are accessible
1232                                                                      from nonsecure EL1 and EL0 modes:
1233                                                                  If EL3 is implemented and EL2 is not implemented, this bit is
1234                                                                      treated as if it is 1 for all purposes other than reading the
1235                                                                      register.
1236                                                                  0 = The AP_CNTP_CVAL_EL0, AP_CNTP_TVAL_EL0, and AP_CNTP_CTL_EL0 registers
1237                                                                      are not accessible from nonsecure EL1 and EL0 modes.
1238                                                                  1 = The AP_CNTP_CVAL_EL0, AP_CNTP_TVAL_EL0, and AP_CNTP_CTL_EL0 registers
1239                                                                      are accessible from nonsecure EL1 and EL0 modes. */
1240         uint32_t el1pcten              : 1;  /**< [  0:  0](R/W) Controls whether the physical counter, AP_CNTPCT_EL0, is
1241                                                                      accessible from nonsecure EL1 and EL0 modes:
1242                                                                  If EL3 is implemented and EL2 is not implemented, this bit is
1243                                                                      treated as if it is 1 for all purposes other than reading the
1244                                                                      register.
1245                                                                  0 = The AP_CNTPCT_EL0 register is not accessible from nonsecure EL1
1246                                                                      and EL0 modes.
1247                                                                  1 = The AP_CNTPCT_EL0 register is accessible from nonsecure EL1 and
1248                                                                      EL0 modes. */
1249 #else /* Word 0 - Little Endian */
1250         uint32_t el1pcten              : 1;  /**< [  0:  0](R/W) Controls whether the physical counter, AP_CNTPCT_EL0, is
1251                                                                      accessible from nonsecure EL1 and EL0 modes:
1252                                                                  If EL3 is implemented and EL2 is not implemented, this bit is
1253                                                                      treated as if it is 1 for all purposes other than reading the
1254                                                                      register.
1255                                                                  0 = The AP_CNTPCT_EL0 register is not accessible from nonsecure EL1
1256                                                                      and EL0 modes.
1257                                                                  1 = The AP_CNTPCT_EL0 register is accessible from nonsecure EL1 and
1258                                                                      EL0 modes. */
1259         uint32_t el1pcen               : 1;  /**< [  1:  1](R/W) Controls whether the physical timer registers are accessible
1260                                                                      from nonsecure EL1 and EL0 modes:
1261                                                                  If EL3 is implemented and EL2 is not implemented, this bit is
1262                                                                      treated as if it is 1 for all purposes other than reading the
1263                                                                      register.
1264                                                                  0 = The AP_CNTP_CVAL_EL0, AP_CNTP_TVAL_EL0, and AP_CNTP_CTL_EL0 registers
1265                                                                      are not accessible from nonsecure EL1 and EL0 modes.
1266                                                                  1 = The AP_CNTP_CVAL_EL0, AP_CNTP_TVAL_EL0, and AP_CNTP_CTL_EL0 registers
1267                                                                      are accessible from nonsecure EL1 and EL0 modes. */
1268         uint32_t evnten                : 1;  /**< [  2:  2](R/W) Enables the generation of an event stream from the
1269                                                                      corresponding counter:
1270                                                                  0 = Disables the event stream.
1271                                                                  1 = Enables the event stream. */
1272         uint32_t evntdir               : 1;  /**< [  3:  3](R/W) Controls which transition of the counter register ( AP_CNTPCT_EL0
1273                                                                      or AP_CNTVCT_EL0) trigger bit, defined by EVNTI, generates an
1274                                                                      event when the event stream is enabled:
1275                                                                  0 = A 0 to 1 transition of the trigger bit triggers an event.
1276                                                                  1 = A 1 to 0 transition of the trigger bit triggers an event. */
1277         uint32_t evnti                 : 4;  /**< [  7:  4](R/W) Selects which bit (0 to 15) of the corresponding counter
1278                                                                      register ( AP_CNTPCT_EL0 or AP_CNTVCT_EL0) is the trigger for the
1279                                                                      event stream generated from that counter, when that stream is
1280                                                                      enabled. */
1281         uint32_t reserved_8_31         : 24;
1282 #endif /* Word 0 - End */
1283     } s;
1284     /* struct bdk_ap_cnthctl_el2_s cn; */
1285 };
1286 typedef union bdk_ap_cnthctl_el2 bdk_ap_cnthctl_el2_t;
1287 
1288 #define BDK_AP_CNTHCTL_EL2 BDK_AP_CNTHCTL_EL2_FUNC()
1289 static inline uint64_t BDK_AP_CNTHCTL_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTHCTL_EL2_FUNC(void)1290 static inline uint64_t BDK_AP_CNTHCTL_EL2_FUNC(void)
1291 {
1292     return 0x3040e010000ll;
1293 }
1294 
1295 #define typedef_BDK_AP_CNTHCTL_EL2 bdk_ap_cnthctl_el2_t
1296 #define bustype_BDK_AP_CNTHCTL_EL2 BDK_CSR_TYPE_SYSREG
1297 #define basename_BDK_AP_CNTHCTL_EL2 "AP_CNTHCTL_EL2"
1298 #define busnum_BDK_AP_CNTHCTL_EL2 0
1299 #define arguments_BDK_AP_CNTHCTL_EL2 -1,-1,-1,-1
1300 
1301 /**
1302  * Register (SYSREG) ap_cnthctl_el2_e2h
1303  *
1304  * AP Counter-timer Hypervisor Control E2H Register
1305  * This register is at the same select as AP_CNTHCTL_EL2 and is used when E2H=1.
1306  */
1307 union bdk_ap_cnthctl_el2_e2h
1308 {
1309     uint32_t u;
1310     struct bdk_ap_cnthctl_el2_e2h_s
1311     {
1312 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1313         uint32_t reserved_12_31        : 20;
1314         uint32_t el1pcen               : 1;  /**< [ 11: 11](R/W) Controls whether physical timer register accessing instuctions
1315                                                                  are accessible from nonsecure EL1 and EL0:
1316                                                                  0 = The following system register accessing instructions in AARCH64,
1317                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1318                                                                      when AP_HCR_EL2[TGE] == 0 and the instructions are executed at
1319                                                                      nonsecure EL1, or nonsecure EL0 unless trapped to EL1 as a
1320                                                                      result of controls in the AP_CNTKCTL_EL1
1321                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=0   AP_CNTP_TVAL_EL0
1322                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=1   AP_CNTP_CTL_EL0
1323                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=2   AP_CNTP_CVAL_EL0
1324                                                                      This bit does not cause any instructions to be trapped to EL2
1325                                                                      when AP_HCR_EL2[TGE]==1.
1326 
1327                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1328         uint32_t el1pten               : 1;  /**< [ 10: 10](R/W) Controls whether the physical counter is accessible from nonsecure
1329                                                                  EL1 and EL0.
1330                                                                  0 = The following system register accessing instructions in AARCH64,
1331                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1332                                                                      when AP_HCR_EL2[TGE] == 0 and the instructions are executed at nonsecure
1333                                                                      EL1, or nonsecure EL0 unless trapped to EL1 as a result of controls
1334                                                                      in AP_CNTKCTL_EL1.
1335                                                                        Op0=3, op1=3, CRn=14, CRm=0, Op2=1   AP_CNTPCT_EL0
1336                                                                      This bit does not cause any instructions to be trapped to EL2
1337                                                                      when AP_HCR_EL2[TGE] == 1.
1338 
1339                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1340         uint32_t el0pten               : 1;  /**< [  9:  9](R/W) Controls whether the physical timer register accessing instructions are
1341                                                                  accessible from nonsecure EL0 when AP_HCR_EL2[TGE]==1.
1342                                                                  0 = The following system register accessing instructions in AARCH64,
1343                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1344                                                                      when AP_HCR_EL2[TGE] == 1 and the instructions are executed at nonsecure
1345                                                                      EL0.
1346                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=0   AP_CNTP_TVAL_EL0
1347                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=1   AP_CNTP_CTL_EL0
1348                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=2   AP_CNTP_CVAL_EL0
1349                                                                      This bit does not cause any instructions to be trapped to EL2
1350                                                                      when AP_HCR_EL2[TGE]==0.
1351 
1352                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1353         uint32_t el0vten               : 1;  /**< [  8:  8](R/W) Controls whether the virtual timer register accessing instructions are
1354                                                                  accessible from nonsecure EL0 when AP_HCR_EL2[TGE]==1.
1355                                                                  0 = The following system register accessing instructions in AARCH64,
1356                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1357                                                                      when AP_HCR_EL2[TGE] == 1 and the instructions are executed at nonsecure
1358                                                                      EL0.
1359                                                                        Op0=3, op1=3, CRn=14, CRm=3, Op2=0   AP_CNTV_TVAL_EL0
1360                                                                        Op0=3, op1=3, CRn=14, CRm=3, Op2=1   AP_CNTV_CTL_EL0
1361                                                                        Op0=3, op1=3, CRn=14, CRm=3, Op2=2   AP_CNTV_CVAL_EL0
1362                                                                      This bit does not cause any instructions to be trapped to EL2
1363                                                                      when AP_HCR_EL2[TGE]==0.
1364 
1365                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1366         uint32_t evnti                 : 4;  /**< [  7:  4](R/W) Selects which bit (0 to 15) of the corresponding counter
1367                                                                      register ( AP_CNTPCT_EL0 or AP_CNTVCT_EL0) is the trigger for the
1368                                                                      event stream generated from that counter, when that stream is
1369                                                                      enabled. */
1370         uint32_t evntdir               : 1;  /**< [  3:  3](R/W) Controls which transition of the counter register ( AP_CNTPCT_EL0
1371                                                                      or AP_CNTVCT_EL0) trigger bit, defined by EVNTI, generates an
1372                                                                      event when the event stream is enabled:
1373                                                                  0 = A 0 to 1 transition of the trigger bit triggers an event.
1374                                                                  1 = A 1 to 0 transition of the trigger bit triggers an event. */
1375         uint32_t evnten                : 1;  /**< [  2:  2](R/W) Enables the generation of an event stream from the
1376                                                                      corresponding counter:
1377                                                                  0 = Disables the event stream.
1378                                                                  1 = Enables the event stream. */
1379         uint32_t el0vcten              : 1;  /**< [  1:  1](R/W) Controls whether the virtual counter registers are accessible
1380                                                                      from nonsecure EL1 and EL0 when AP_HCR_EL2[TGE]==1:
1381                                                                  0 = The following system register accessing instructions in AARCH64,
1382                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1383                                                                      when AP_HCR_EL2[TGE] == 1 and the instructions are executed at nonsecure
1384                                                                      EL0.
1385                                                                        Op0=3, op1=3, CRn=14, CRm=0, Op2=2   AP_CNTVCT_EL0
1386                                                                      In addition, if EL0PCTEN == 0, then the following System Register
1387                                                                      accessing instructions in AARCH64, and their equivalent instructions
1388                                                                      in AARCH32, are trapped to EL2 when executed at nonsecure EL0 when
1389                                                                      AP_HCR_EL2[TGE]==1.
1390                                                                        Op0=3, op1=3, CRn=14, CRm=0, Op2=0   AP_CNTFRQ_EL0
1391                                                                      This bit does not cause any instructions to be trapped to EL2
1392                                                                      when AP_HCR_EL2[TGE]==0.
1393 
1394                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1395         uint32_t el0pcten              : 1;  /**< [  0:  0](R/W) Controls whether physical counter register accessing instructions
1396                                                                  are accessible from nonsecure EL0 when AP_HCR_EL2[TGE]==1:
1397                                                                  0 = The following system register accessing instructions in AARCH64,
1398                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1399                                                                      when AP_HCR_EL2[TGE] == 1 and the instructions are executed at nonsecure
1400                                                                      EL0.
1401                                                                        Op0=3, op1=3, CRn=14, CRm=0, Op2=1   AP_CNTPCT_EL0
1402                                                                      In addition, if EL0PCTEN == 0, then the following System Register
1403                                                                      accessing instructions in AARCH64, and their equivalent instructions
1404                                                                      in AARCH32, are trapped to EL2 when executed at nonsecure EL0 when
1405                                                                      AP_HCR_EL2[TGE]==1.
1406                                                                        Op0=3, op1=3, CRn=14, CRm=0, Op2=0   AP_CNTFRQ_EL0
1407                                                                      This bit does not cause any instructions to be trapped to EL2
1408                                                                      when AP_HCR_EL2[TGE]==0.
1409 
1410                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1411 #else /* Word 0 - Little Endian */
1412         uint32_t el0pcten              : 1;  /**< [  0:  0](R/W) Controls whether physical counter register accessing instructions
1413                                                                  are accessible from nonsecure EL0 when AP_HCR_EL2[TGE]==1:
1414                                                                  0 = The following system register accessing instructions in AARCH64,
1415                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1416                                                                      when AP_HCR_EL2[TGE] == 1 and the instructions are executed at nonsecure
1417                                                                      EL0.
1418                                                                        Op0=3, op1=3, CRn=14, CRm=0, Op2=1   AP_CNTPCT_EL0
1419                                                                      In addition, if EL0PCTEN == 0, then the following System Register
1420                                                                      accessing instructions in AARCH64, and their equivalent instructions
1421                                                                      in AARCH32, are trapped to EL2 when executed at nonsecure EL0 when
1422                                                                      AP_HCR_EL2[TGE]==1.
1423                                                                        Op0=3, op1=3, CRn=14, CRm=0, Op2=0   AP_CNTFRQ_EL0
1424                                                                      This bit does not cause any instructions to be trapped to EL2
1425                                                                      when AP_HCR_EL2[TGE]==0.
1426 
1427                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1428         uint32_t el0vcten              : 1;  /**< [  1:  1](R/W) Controls whether the virtual counter registers are accessible
1429                                                                      from nonsecure EL1 and EL0 when AP_HCR_EL2[TGE]==1:
1430                                                                  0 = The following system register accessing instructions in AARCH64,
1431                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1432                                                                      when AP_HCR_EL2[TGE] == 1 and the instructions are executed at nonsecure
1433                                                                      EL0.
1434                                                                        Op0=3, op1=3, CRn=14, CRm=0, Op2=2   AP_CNTVCT_EL0
1435                                                                      In addition, if EL0PCTEN == 0, then the following System Register
1436                                                                      accessing instructions in AARCH64, and their equivalent instructions
1437                                                                      in AARCH32, are trapped to EL2 when executed at nonsecure EL0 when
1438                                                                      AP_HCR_EL2[TGE]==1.
1439                                                                        Op0=3, op1=3, CRn=14, CRm=0, Op2=0   AP_CNTFRQ_EL0
1440                                                                      This bit does not cause any instructions to be trapped to EL2
1441                                                                      when AP_HCR_EL2[TGE]==0.
1442 
1443                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1444         uint32_t evnten                : 1;  /**< [  2:  2](R/W) Enables the generation of an event stream from the
1445                                                                      corresponding counter:
1446                                                                  0 = Disables the event stream.
1447                                                                  1 = Enables the event stream. */
1448         uint32_t evntdir               : 1;  /**< [  3:  3](R/W) Controls which transition of the counter register ( AP_CNTPCT_EL0
1449                                                                      or AP_CNTVCT_EL0) trigger bit, defined by EVNTI, generates an
1450                                                                      event when the event stream is enabled:
1451                                                                  0 = A 0 to 1 transition of the trigger bit triggers an event.
1452                                                                  1 = A 1 to 0 transition of the trigger bit triggers an event. */
1453         uint32_t evnti                 : 4;  /**< [  7:  4](R/W) Selects which bit (0 to 15) of the corresponding counter
1454                                                                      register ( AP_CNTPCT_EL0 or AP_CNTVCT_EL0) is the trigger for the
1455                                                                      event stream generated from that counter, when that stream is
1456                                                                      enabled. */
1457         uint32_t el0vten               : 1;  /**< [  8:  8](R/W) Controls whether the virtual timer register accessing instructions are
1458                                                                  accessible from nonsecure EL0 when AP_HCR_EL2[TGE]==1.
1459                                                                  0 = The following system register accessing instructions in AARCH64,
1460                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1461                                                                      when AP_HCR_EL2[TGE] == 1 and the instructions are executed at nonsecure
1462                                                                      EL0.
1463                                                                        Op0=3, op1=3, CRn=14, CRm=3, Op2=0   AP_CNTV_TVAL_EL0
1464                                                                        Op0=3, op1=3, CRn=14, CRm=3, Op2=1   AP_CNTV_CTL_EL0
1465                                                                        Op0=3, op1=3, CRn=14, CRm=3, Op2=2   AP_CNTV_CVAL_EL0
1466                                                                      This bit does not cause any instructions to be trapped to EL2
1467                                                                      when AP_HCR_EL2[TGE]==0.
1468 
1469                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1470         uint32_t el0pten               : 1;  /**< [  9:  9](R/W) Controls whether the physical timer register accessing instructions are
1471                                                                  accessible from nonsecure EL0 when AP_HCR_EL2[TGE]==1.
1472                                                                  0 = The following system register accessing instructions in AARCH64,
1473                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1474                                                                      when AP_HCR_EL2[TGE] == 1 and the instructions are executed at nonsecure
1475                                                                      EL0.
1476                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=0   AP_CNTP_TVAL_EL0
1477                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=1   AP_CNTP_CTL_EL0
1478                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=2   AP_CNTP_CVAL_EL0
1479                                                                      This bit does not cause any instructions to be trapped to EL2
1480                                                                      when AP_HCR_EL2[TGE]==0.
1481 
1482                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1483         uint32_t el1pten               : 1;  /**< [ 10: 10](R/W) Controls whether the physical counter is accessible from nonsecure
1484                                                                  EL1 and EL0.
1485                                                                  0 = The following system register accessing instructions in AARCH64,
1486                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1487                                                                      when AP_HCR_EL2[TGE] == 0 and the instructions are executed at nonsecure
1488                                                                      EL1, or nonsecure EL0 unless trapped to EL1 as a result of controls
1489                                                                      in AP_CNTKCTL_EL1.
1490                                                                        Op0=3, op1=3, CRn=14, CRm=0, Op2=1   AP_CNTPCT_EL0
1491                                                                      This bit does not cause any instructions to be trapped to EL2
1492                                                                      when AP_HCR_EL2[TGE] == 1.
1493 
1494                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1495         uint32_t el1pcen               : 1;  /**< [ 11: 11](R/W) Controls whether physical timer register accessing instuctions
1496                                                                  are accessible from nonsecure EL1 and EL0:
1497                                                                  0 = The following system register accessing instructions in AARCH64,
1498                                                                      and their equivalent instructions in AARCH32, are trapped to EL2
1499                                                                      when AP_HCR_EL2[TGE] == 0 and the instructions are executed at
1500                                                                      nonsecure EL1, or nonsecure EL0 unless trapped to EL1 as a
1501                                                                      result of controls in the AP_CNTKCTL_EL1
1502                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=0   AP_CNTP_TVAL_EL0
1503                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=1   AP_CNTP_CTL_EL0
1504                                                                        Op0=3, op1=3, CRn=14, CRm=2, Op2=2   AP_CNTP_CVAL_EL0
1505                                                                      This bit does not cause any instructions to be trapped to EL2
1506                                                                      when AP_HCR_EL2[TGE]==1.
1507 
1508                                                                  1 = This bit does not cause any instructions to be trapped to EL2. */
1509         uint32_t reserved_12_31        : 20;
1510 #endif /* Word 0 - End */
1511     } s;
1512     /* struct bdk_ap_cnthctl_el2_e2h_s cn; */
1513 };
1514 typedef union bdk_ap_cnthctl_el2_e2h bdk_ap_cnthctl_el2_e2h_t;
1515 
1516 #define BDK_AP_CNTHCTL_EL2_E2H BDK_AP_CNTHCTL_EL2_E2H_FUNC()
1517 static inline uint64_t BDK_AP_CNTHCTL_EL2_E2H_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTHCTL_EL2_E2H_FUNC(void)1518 static inline uint64_t BDK_AP_CNTHCTL_EL2_E2H_FUNC(void)
1519 {
1520     return 0x3040e010010ll;
1521 }
1522 
1523 #define typedef_BDK_AP_CNTHCTL_EL2_E2H bdk_ap_cnthctl_el2_e2h_t
1524 #define bustype_BDK_AP_CNTHCTL_EL2_E2H BDK_CSR_TYPE_SYSREG
1525 #define basename_BDK_AP_CNTHCTL_EL2_E2H "AP_CNTHCTL_EL2_E2H"
1526 #define busnum_BDK_AP_CNTHCTL_EL2_E2H 0
1527 #define arguments_BDK_AP_CNTHCTL_EL2_E2H -1,-1,-1,-1
1528 
1529 /**
1530  * Register (SYSREG) ap_cnthp_ctl_el2
1531  *
1532  * AP Counter-timer Hypervisor Physical Timer Control Register
1533  * Control register for the EL2 physical timer.
1534  */
1535 union bdk_ap_cnthp_ctl_el2
1536 {
1537     uint32_t u;
1538     struct bdk_ap_cnthp_ctl_el2_s
1539     {
1540 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1541         uint32_t reserved_3_31         : 29;
1542         uint32_t istatus               : 1;  /**< [  2:  2](RO) The status of the timer interrupt. This bit is read-only.
1543                                                                  A register write that sets IMASK to 1 latches this bit to
1544                                                                      reflect the status of the interrupt immediately before that
1545                                                                      write.
1546                                                                  0 = Interrupt not asserted.
1547                                                                  1 = Interrupt asserted. */
1548         uint32_t imask                 : 1;  /**< [  1:  1](R/W) Timer interrupt mask bit.
1549                                                                  0 = Timer interrupt is not masked.
1550                                                                  1 = Timer interrupt is masked. */
1551         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables the timer.
1552                                                                  Disabling the timer masks the timer interrupt, but the timer
1553                                                                      value continues to count down.
1554                                                                  0 = Timer disabled.
1555                                                                  1 = Timer enabled. */
1556 #else /* Word 0 - Little Endian */
1557         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables the timer.
1558                                                                  Disabling the timer masks the timer interrupt, but the timer
1559                                                                      value continues to count down.
1560                                                                  0 = Timer disabled.
1561                                                                  1 = Timer enabled. */
1562         uint32_t imask                 : 1;  /**< [  1:  1](R/W) Timer interrupt mask bit.
1563                                                                  0 = Timer interrupt is not masked.
1564                                                                  1 = Timer interrupt is masked. */
1565         uint32_t istatus               : 1;  /**< [  2:  2](RO) The status of the timer interrupt. This bit is read-only.
1566                                                                  A register write that sets IMASK to 1 latches this bit to
1567                                                                      reflect the status of the interrupt immediately before that
1568                                                                      write.
1569                                                                  0 = Interrupt not asserted.
1570                                                                  1 = Interrupt asserted. */
1571         uint32_t reserved_3_31         : 29;
1572 #endif /* Word 0 - End */
1573     } s;
1574     /* struct bdk_ap_cnthp_ctl_el2_s cn; */
1575 };
1576 typedef union bdk_ap_cnthp_ctl_el2 bdk_ap_cnthp_ctl_el2_t;
1577 
1578 #define BDK_AP_CNTHP_CTL_EL2 BDK_AP_CNTHP_CTL_EL2_FUNC()
1579 static inline uint64_t BDK_AP_CNTHP_CTL_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTHP_CTL_EL2_FUNC(void)1580 static inline uint64_t BDK_AP_CNTHP_CTL_EL2_FUNC(void)
1581 {
1582     return 0x3040e020100ll;
1583 }
1584 
1585 #define typedef_BDK_AP_CNTHP_CTL_EL2 bdk_ap_cnthp_ctl_el2_t
1586 #define bustype_BDK_AP_CNTHP_CTL_EL2 BDK_CSR_TYPE_SYSREG
1587 #define basename_BDK_AP_CNTHP_CTL_EL2 "AP_CNTHP_CTL_EL2"
1588 #define busnum_BDK_AP_CNTHP_CTL_EL2 0
1589 #define arguments_BDK_AP_CNTHP_CTL_EL2 -1,-1,-1,-1
1590 
1591 /**
1592  * Register (SYSREG) ap_cnthp_cval_el2
1593  *
1594  * AP Counter-timer Hypervisor Physical Timer Compare Value Register
1595  * Holds the compare value for the EL2 physical timer.
1596  */
1597 union bdk_ap_cnthp_cval_el2
1598 {
1599     uint64_t u;
1600     struct bdk_ap_cnthp_cval_el2_s
1601     {
1602 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1603         uint64_t data                  : 64; /**< [ 63:  0](R/W) EL2 physical timer compare value. */
1604 #else /* Word 0 - Little Endian */
1605         uint64_t data                  : 64; /**< [ 63:  0](R/W) EL2 physical timer compare value. */
1606 #endif /* Word 0 - End */
1607     } s;
1608     /* struct bdk_ap_cnthp_cval_el2_s cn; */
1609 };
1610 typedef union bdk_ap_cnthp_cval_el2 bdk_ap_cnthp_cval_el2_t;
1611 
1612 #define BDK_AP_CNTHP_CVAL_EL2 BDK_AP_CNTHP_CVAL_EL2_FUNC()
1613 static inline uint64_t BDK_AP_CNTHP_CVAL_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTHP_CVAL_EL2_FUNC(void)1614 static inline uint64_t BDK_AP_CNTHP_CVAL_EL2_FUNC(void)
1615 {
1616     return 0x3040e020200ll;
1617 }
1618 
1619 #define typedef_BDK_AP_CNTHP_CVAL_EL2 bdk_ap_cnthp_cval_el2_t
1620 #define bustype_BDK_AP_CNTHP_CVAL_EL2 BDK_CSR_TYPE_SYSREG
1621 #define basename_BDK_AP_CNTHP_CVAL_EL2 "AP_CNTHP_CVAL_EL2"
1622 #define busnum_BDK_AP_CNTHP_CVAL_EL2 0
1623 #define arguments_BDK_AP_CNTHP_CVAL_EL2 -1,-1,-1,-1
1624 
1625 /**
1626  * Register (SYSREG) ap_cnthp_tval_el2
1627  *
1628  * AP Counter-timer Hypervisor Physical Timer Value Register
1629  * Holds the timer value for the EL2 physical timer.
1630  */
1631 union bdk_ap_cnthp_tval_el2
1632 {
1633     uint32_t u;
1634     struct bdk_ap_cnthp_tval_el2_s
1635     {
1636 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1637         uint32_t data                  : 32; /**< [ 31:  0](R/W) EL2 physical timer value. */
1638 #else /* Word 0 - Little Endian */
1639         uint32_t data                  : 32; /**< [ 31:  0](R/W) EL2 physical timer value. */
1640 #endif /* Word 0 - End */
1641     } s;
1642     /* struct bdk_ap_cnthp_tval_el2_s cn; */
1643 };
1644 typedef union bdk_ap_cnthp_tval_el2 bdk_ap_cnthp_tval_el2_t;
1645 
1646 #define BDK_AP_CNTHP_TVAL_EL2 BDK_AP_CNTHP_TVAL_EL2_FUNC()
1647 static inline uint64_t BDK_AP_CNTHP_TVAL_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTHP_TVAL_EL2_FUNC(void)1648 static inline uint64_t BDK_AP_CNTHP_TVAL_EL2_FUNC(void)
1649 {
1650     return 0x3040e020000ll;
1651 }
1652 
1653 #define typedef_BDK_AP_CNTHP_TVAL_EL2 bdk_ap_cnthp_tval_el2_t
1654 #define bustype_BDK_AP_CNTHP_TVAL_EL2 BDK_CSR_TYPE_SYSREG
1655 #define basename_BDK_AP_CNTHP_TVAL_EL2 "AP_CNTHP_TVAL_EL2"
1656 #define busnum_BDK_AP_CNTHP_TVAL_EL2 0
1657 #define arguments_BDK_AP_CNTHP_TVAL_EL2 -1,-1,-1,-1
1658 
1659 /**
1660  * Register (SYSREG) ap_cnthv_ctl_el2
1661  *
1662  * AP v8.1 Counter-timer Hypervisor Virtual Timer Control Register
1663  * v8.1 Control register for the EL2 virtual timer.
1664  */
1665 union bdk_ap_cnthv_ctl_el2
1666 {
1667     uint32_t u;
1668     struct bdk_ap_cnthv_ctl_el2_s
1669     {
1670 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1671         uint32_t reserved_3_31         : 29;
1672         uint32_t istatus               : 1;  /**< [  2:  2](RO) The status of the timer interrupt. This bit is read-only.
1673                                                                  A register write that sets IMASK to 1 latches this bit to
1674                                                                      reflect the status of the interrupt immediately before that
1675                                                                      write.
1676                                                                  0 = Interrupt not asserted.
1677                                                                  1 = Interrupt asserted. */
1678         uint32_t imask                 : 1;  /**< [  1:  1](R/W) Timer interrupt mask bit.
1679                                                                  0 = Timer interrupt is not masked.
1680                                                                  1 = Timer interrupt is masked. */
1681         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables the timer.
1682                                                                  Disabling the timer masks the timer interrupt, but the timer
1683                                                                      value continues to count down.
1684                                                                  0 = Timer disabled.
1685                                                                  1 = Timer enabled. */
1686 #else /* Word 0 - Little Endian */
1687         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables the timer.
1688                                                                  Disabling the timer masks the timer interrupt, but the timer
1689                                                                      value continues to count down.
1690                                                                  0 = Timer disabled.
1691                                                                  1 = Timer enabled. */
1692         uint32_t imask                 : 1;  /**< [  1:  1](R/W) Timer interrupt mask bit.
1693                                                                  0 = Timer interrupt is not masked.
1694                                                                  1 = Timer interrupt is masked. */
1695         uint32_t istatus               : 1;  /**< [  2:  2](RO) The status of the timer interrupt. This bit is read-only.
1696                                                                  A register write that sets IMASK to 1 latches this bit to
1697                                                                      reflect the status of the interrupt immediately before that
1698                                                                      write.
1699                                                                  0 = Interrupt not asserted.
1700                                                                  1 = Interrupt asserted. */
1701         uint32_t reserved_3_31         : 29;
1702 #endif /* Word 0 - End */
1703     } s;
1704     /* struct bdk_ap_cnthv_ctl_el2_s cn; */
1705 };
1706 typedef union bdk_ap_cnthv_ctl_el2 bdk_ap_cnthv_ctl_el2_t;
1707 
1708 #define BDK_AP_CNTHV_CTL_EL2 BDK_AP_CNTHV_CTL_EL2_FUNC()
1709 static inline uint64_t BDK_AP_CNTHV_CTL_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTHV_CTL_EL2_FUNC(void)1710 static inline uint64_t BDK_AP_CNTHV_CTL_EL2_FUNC(void)
1711 {
1712     return 0x3040e030100ll;
1713 }
1714 
1715 #define typedef_BDK_AP_CNTHV_CTL_EL2 bdk_ap_cnthv_ctl_el2_t
1716 #define bustype_BDK_AP_CNTHV_CTL_EL2 BDK_CSR_TYPE_SYSREG
1717 #define basename_BDK_AP_CNTHV_CTL_EL2 "AP_CNTHV_CTL_EL2"
1718 #define busnum_BDK_AP_CNTHV_CTL_EL2 0
1719 #define arguments_BDK_AP_CNTHV_CTL_EL2 -1,-1,-1,-1
1720 
1721 /**
1722  * Register (SYSREG) ap_cnthv_cval_el2
1723  *
1724  * AP v8.1 Counter-timer Hypervisor Virtual Timer Compare Value Register
1725  * v8.1 Holds the compare value for the EL2 virtual timer.
1726  */
1727 union bdk_ap_cnthv_cval_el2
1728 {
1729     uint64_t u;
1730     struct bdk_ap_cnthv_cval_el2_s
1731     {
1732 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1733         uint64_t data                  : 64; /**< [ 63:  0](R/W) EL2 physical timer compare value. */
1734 #else /* Word 0 - Little Endian */
1735         uint64_t data                  : 64; /**< [ 63:  0](R/W) EL2 physical timer compare value. */
1736 #endif /* Word 0 - End */
1737     } s;
1738     /* struct bdk_ap_cnthv_cval_el2_s cn; */
1739 };
1740 typedef union bdk_ap_cnthv_cval_el2 bdk_ap_cnthv_cval_el2_t;
1741 
1742 #define BDK_AP_CNTHV_CVAL_EL2 BDK_AP_CNTHV_CVAL_EL2_FUNC()
1743 static inline uint64_t BDK_AP_CNTHV_CVAL_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTHV_CVAL_EL2_FUNC(void)1744 static inline uint64_t BDK_AP_CNTHV_CVAL_EL2_FUNC(void)
1745 {
1746     return 0x3040e030200ll;
1747 }
1748 
1749 #define typedef_BDK_AP_CNTHV_CVAL_EL2 bdk_ap_cnthv_cval_el2_t
1750 #define bustype_BDK_AP_CNTHV_CVAL_EL2 BDK_CSR_TYPE_SYSREG
1751 #define basename_BDK_AP_CNTHV_CVAL_EL2 "AP_CNTHV_CVAL_EL2"
1752 #define busnum_BDK_AP_CNTHV_CVAL_EL2 0
1753 #define arguments_BDK_AP_CNTHV_CVAL_EL2 -1,-1,-1,-1
1754 
1755 /**
1756  * Register (SYSREG) ap_cnthv_tval_el2
1757  *
1758  * AP v8.1 Counter-timer Hypervisor Virtual Timer Value Register
1759  * v8.1 Holds the timer value for the EL2 virtual timer.
1760  */
1761 union bdk_ap_cnthv_tval_el2
1762 {
1763     uint32_t u;
1764     struct bdk_ap_cnthv_tval_el2_s
1765     {
1766 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1767         uint32_t data                  : 32; /**< [ 31:  0](R/W) EL2 virtual timer value. */
1768 #else /* Word 0 - Little Endian */
1769         uint32_t data                  : 32; /**< [ 31:  0](R/W) EL2 virtual timer value. */
1770 #endif /* Word 0 - End */
1771     } s;
1772     /* struct bdk_ap_cnthv_tval_el2_s cn; */
1773 };
1774 typedef union bdk_ap_cnthv_tval_el2 bdk_ap_cnthv_tval_el2_t;
1775 
1776 #define BDK_AP_CNTHV_TVAL_EL2 BDK_AP_CNTHV_TVAL_EL2_FUNC()
1777 static inline uint64_t BDK_AP_CNTHV_TVAL_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTHV_TVAL_EL2_FUNC(void)1778 static inline uint64_t BDK_AP_CNTHV_TVAL_EL2_FUNC(void)
1779 {
1780     return 0x3040e030000ll;
1781 }
1782 
1783 #define typedef_BDK_AP_CNTHV_TVAL_EL2 bdk_ap_cnthv_tval_el2_t
1784 #define bustype_BDK_AP_CNTHV_TVAL_EL2 BDK_CSR_TYPE_SYSREG
1785 #define basename_BDK_AP_CNTHV_TVAL_EL2 "AP_CNTHV_TVAL_EL2"
1786 #define busnum_BDK_AP_CNTHV_TVAL_EL2 0
1787 #define arguments_BDK_AP_CNTHV_TVAL_EL2 -1,-1,-1,-1
1788 
1789 /**
1790  * Register (SYSREG) ap_cntkctl_el1
1791  *
1792  * AP Counter-timer Kernel Control Register
1793  * Controls the generation of an event stream from the virtual
1794  *     counter, and access from EL0 to the physical counter, virtual
1795  *     counter, EL1 physical timers, and the virtual timer.
1796  */
1797 union bdk_ap_cntkctl_el1
1798 {
1799     uint32_t u;
1800     struct bdk_ap_cntkctl_el1_s
1801     {
1802 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1803         uint32_t reserved_10_31        : 22;
1804         uint32_t el0pten               : 1;  /**< [  9:  9](R/W) Controls whether the physical timer registers are accessible
1805                                                                      from EL0 modes:
1806                                                                  0 = The AP_CNTP_CVAL_EL0, AP_CNTP_CTL_EL0, and AP_CNTP_TVAL_EL0 registers
1807                                                                      are not accessible from EL0.
1808                                                                  1 = The AP_CNTP_CVAL_EL0, AP_CNTP_CTL_EL0, and AP_CNTP_TVAL_EL0 registers
1809                                                                      are accessible from EL0. */
1810         uint32_t el0vten               : 1;  /**< [  8:  8](R/W) Controls whether the virtual timer registers are accessible
1811                                                                      from EL0 modes:
1812                                                                  0 = The AP_CNTV_CVAL_EL0, AP_CNTV_CTL_EL0, and AP_CNTV_TVAL_EL0 registers
1813                                                                      are not accessible from EL0.
1814                                                                  1 = The AP_CNTV_CVAL_EL0, AP_CNTV_CTL_EL0, and AP_CNTV_TVAL_EL0 registers
1815                                                                      are accessible from EL0. */
1816         uint32_t evnti                 : 4;  /**< [  7:  4](R/W) Selects which bit (0 to 15) of the corresponding counter
1817                                                                      register ( AP_CNTPCT_EL0 or AP_CNTVCT_EL0) is the trigger for the
1818                                                                      event stream generated from that counter, when that stream is
1819                                                                      enabled. */
1820         uint32_t evntdir               : 1;  /**< [  3:  3](R/W) Controls which transition of the counter register ( AP_CNTPCT_EL0
1821                                                                      or AP_CNTVCT_EL0) trigger bit, defined by EVNTI, generates an
1822                                                                      event when the event stream is enabled:
1823                                                                  0 = A 0 to 1 transition of the trigger bit triggers an event.
1824                                                                  1 = A 1 to 0 transition of the trigger bit triggers an event. */
1825         uint32_t evnten                : 1;  /**< [  2:  2](R/W) Enables the generation of an event stream from the
1826                                                                      corresponding counter:
1827                                                                  0 = Disables the event stream.
1828                                                                  1 = Enables the event stream. */
1829         uint32_t el0vcten              : 1;  /**< [  1:  1](R/W) Controls whether the virtual counter, AP_CNTVCT_EL0, and the
1830                                                                      frequency register AP_CNTFRQ_EL0, are accessible from EL0 modes:
1831                                                                  0 =  AP_CNTVCT_EL0 is not accessible from EL0. If EL0PCTEN is set to
1832                                                                      0, AP_CNTFRQ_EL0 is not accessible from EL0.
1833                                                                  1 =  AP_CNTVCT_EL0 and AP_CNTFRQ_EL0 are accessible from EL0. */
1834         uint32_t el0pcten              : 1;  /**< [  0:  0](R/W) Controls whether the physical counter, AP_CNTPCT_EL0, and the
1835                                                                      frequency register AP_CNTFRQ_EL0, are accessible from EL0 modes:
1836                                                                  0 =  AP_CNTPCT_EL0 is not accessible from EL0 modes. If EL0VCTEN is
1837                                                                      set to 0, AP_CNTFRQ_EL0 is not accessible from EL0.
1838                                                                  1 =  AP_CNTPCT_EL0 and AP_CNTFRQ_EL0 are accessible from EL0. */
1839 #else /* Word 0 - Little Endian */
1840         uint32_t el0pcten              : 1;  /**< [  0:  0](R/W) Controls whether the physical counter, AP_CNTPCT_EL0, and the
1841                                                                      frequency register AP_CNTFRQ_EL0, are accessible from EL0 modes:
1842                                                                  0 =  AP_CNTPCT_EL0 is not accessible from EL0 modes. If EL0VCTEN is
1843                                                                      set to 0, AP_CNTFRQ_EL0 is not accessible from EL0.
1844                                                                  1 =  AP_CNTPCT_EL0 and AP_CNTFRQ_EL0 are accessible from EL0. */
1845         uint32_t el0vcten              : 1;  /**< [  1:  1](R/W) Controls whether the virtual counter, AP_CNTVCT_EL0, and the
1846                                                                      frequency register AP_CNTFRQ_EL0, are accessible from EL0 modes:
1847                                                                  0 =  AP_CNTVCT_EL0 is not accessible from EL0. If EL0PCTEN is set to
1848                                                                      0, AP_CNTFRQ_EL0 is not accessible from EL0.
1849                                                                  1 =  AP_CNTVCT_EL0 and AP_CNTFRQ_EL0 are accessible from EL0. */
1850         uint32_t evnten                : 1;  /**< [  2:  2](R/W) Enables the generation of an event stream from the
1851                                                                      corresponding counter:
1852                                                                  0 = Disables the event stream.
1853                                                                  1 = Enables the event stream. */
1854         uint32_t evntdir               : 1;  /**< [  3:  3](R/W) Controls which transition of the counter register ( AP_CNTPCT_EL0
1855                                                                      or AP_CNTVCT_EL0) trigger bit, defined by EVNTI, generates an
1856                                                                      event when the event stream is enabled:
1857                                                                  0 = A 0 to 1 transition of the trigger bit triggers an event.
1858                                                                  1 = A 1 to 0 transition of the trigger bit triggers an event. */
1859         uint32_t evnti                 : 4;  /**< [  7:  4](R/W) Selects which bit (0 to 15) of the corresponding counter
1860                                                                      register ( AP_CNTPCT_EL0 or AP_CNTVCT_EL0) is the trigger for the
1861                                                                      event stream generated from that counter, when that stream is
1862                                                                      enabled. */
1863         uint32_t el0vten               : 1;  /**< [  8:  8](R/W) Controls whether the virtual timer registers are accessible
1864                                                                      from EL0 modes:
1865                                                                  0 = The AP_CNTV_CVAL_EL0, AP_CNTV_CTL_EL0, and AP_CNTV_TVAL_EL0 registers
1866                                                                      are not accessible from EL0.
1867                                                                  1 = The AP_CNTV_CVAL_EL0, AP_CNTV_CTL_EL0, and AP_CNTV_TVAL_EL0 registers
1868                                                                      are accessible from EL0. */
1869         uint32_t el0pten               : 1;  /**< [  9:  9](R/W) Controls whether the physical timer registers are accessible
1870                                                                      from EL0 modes:
1871                                                                  0 = The AP_CNTP_CVAL_EL0, AP_CNTP_CTL_EL0, and AP_CNTP_TVAL_EL0 registers
1872                                                                      are not accessible from EL0.
1873                                                                  1 = The AP_CNTP_CVAL_EL0, AP_CNTP_CTL_EL0, and AP_CNTP_TVAL_EL0 registers
1874                                                                      are accessible from EL0. */
1875         uint32_t reserved_10_31        : 22;
1876 #endif /* Word 0 - End */
1877     } s;
1878     /* struct bdk_ap_cntkctl_el1_s cn; */
1879 };
1880 typedef union bdk_ap_cntkctl_el1 bdk_ap_cntkctl_el1_t;
1881 
1882 #define BDK_AP_CNTKCTL_EL1 BDK_AP_CNTKCTL_EL1_FUNC()
1883 static inline uint64_t BDK_AP_CNTKCTL_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTKCTL_EL1_FUNC(void)1884 static inline uint64_t BDK_AP_CNTKCTL_EL1_FUNC(void)
1885 {
1886     return 0x3000e010000ll;
1887 }
1888 
1889 #define typedef_BDK_AP_CNTKCTL_EL1 bdk_ap_cntkctl_el1_t
1890 #define bustype_BDK_AP_CNTKCTL_EL1 BDK_CSR_TYPE_SYSREG
1891 #define basename_BDK_AP_CNTKCTL_EL1 "AP_CNTKCTL_EL1"
1892 #define busnum_BDK_AP_CNTKCTL_EL1 0
1893 #define arguments_BDK_AP_CNTKCTL_EL1 -1,-1,-1,-1
1894 
1895 /**
1896  * Register (SYSREG) ap_cntkctl_el12
1897  *
1898  * AP Counter-timer Kernel Control Register
1899  * Alias of AP_CNTKCTL_EL1 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
1900  */
1901 union bdk_ap_cntkctl_el12
1902 {
1903     uint32_t u;
1904     struct bdk_ap_cntkctl_el12_s
1905     {
1906 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1907         uint32_t reserved_0_31         : 32;
1908 #else /* Word 0 - Little Endian */
1909         uint32_t reserved_0_31         : 32;
1910 #endif /* Word 0 - End */
1911     } s;
1912     /* struct bdk_ap_cntkctl_el12_s cn; */
1913 };
1914 typedef union bdk_ap_cntkctl_el12 bdk_ap_cntkctl_el12_t;
1915 
1916 #define BDK_AP_CNTKCTL_EL12 BDK_AP_CNTKCTL_EL12_FUNC()
1917 static inline uint64_t BDK_AP_CNTKCTL_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTKCTL_EL12_FUNC(void)1918 static inline uint64_t BDK_AP_CNTKCTL_EL12_FUNC(void)
1919 {
1920     return 0x3050e010000ll;
1921 }
1922 
1923 #define typedef_BDK_AP_CNTKCTL_EL12 bdk_ap_cntkctl_el12_t
1924 #define bustype_BDK_AP_CNTKCTL_EL12 BDK_CSR_TYPE_SYSREG
1925 #define basename_BDK_AP_CNTKCTL_EL12 "AP_CNTKCTL_EL12"
1926 #define busnum_BDK_AP_CNTKCTL_EL12 0
1927 #define arguments_BDK_AP_CNTKCTL_EL12 -1,-1,-1,-1
1928 
1929 /**
1930  * Register (SYSREG) ap_cntp_ctl_el0
1931  *
1932  * AP Counter-timer Physical Timer Control Register
1933  * Control register for the EL1 physical timer.
1934  */
1935 union bdk_ap_cntp_ctl_el0
1936 {
1937     uint32_t u;
1938     struct bdk_ap_cntp_ctl_el0_s
1939     {
1940 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1941         uint32_t reserved_3_31         : 29;
1942         uint32_t istatus               : 1;  /**< [  2:  2](RO) The status of the timer interrupt. This bit is read-only.
1943                                                                  A register write that sets IMASK to 1 latches this bit to
1944                                                                      reflect the status of the interrupt immediately before that
1945                                                                      write.
1946                                                                  0 = Interrupt not asserted.
1947                                                                  1 = Interrupt asserted. */
1948         uint32_t imask                 : 1;  /**< [  1:  1](R/W) Timer interrupt mask bit.
1949                                                                  0 = Timer interrupt is not masked.
1950                                                                  1 = Timer interrupt is masked. */
1951         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables the timer.
1952                                                                  Disabling the timer masks the timer interrupt, but the timer
1953                                                                      value continues to count down.
1954                                                                  0 = Timer disabled.
1955                                                                  1 = Timer enabled. */
1956 #else /* Word 0 - Little Endian */
1957         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables the timer.
1958                                                                  Disabling the timer masks the timer interrupt, but the timer
1959                                                                      value continues to count down.
1960                                                                  0 = Timer disabled.
1961                                                                  1 = Timer enabled. */
1962         uint32_t imask                 : 1;  /**< [  1:  1](R/W) Timer interrupt mask bit.
1963                                                                  0 = Timer interrupt is not masked.
1964                                                                  1 = Timer interrupt is masked. */
1965         uint32_t istatus               : 1;  /**< [  2:  2](RO) The status of the timer interrupt. This bit is read-only.
1966                                                                  A register write that sets IMASK to 1 latches this bit to
1967                                                                      reflect the status of the interrupt immediately before that
1968                                                                      write.
1969                                                                  0 = Interrupt not asserted.
1970                                                                  1 = Interrupt asserted. */
1971         uint32_t reserved_3_31         : 29;
1972 #endif /* Word 0 - End */
1973     } s;
1974     /* struct bdk_ap_cntp_ctl_el0_s cn; */
1975 };
1976 typedef union bdk_ap_cntp_ctl_el0 bdk_ap_cntp_ctl_el0_t;
1977 
1978 #define BDK_AP_CNTP_CTL_EL0 BDK_AP_CNTP_CTL_EL0_FUNC()
1979 static inline uint64_t BDK_AP_CNTP_CTL_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTP_CTL_EL0_FUNC(void)1980 static inline uint64_t BDK_AP_CNTP_CTL_EL0_FUNC(void)
1981 {
1982     return 0x3030e020100ll;
1983 }
1984 
1985 #define typedef_BDK_AP_CNTP_CTL_EL0 bdk_ap_cntp_ctl_el0_t
1986 #define bustype_BDK_AP_CNTP_CTL_EL0 BDK_CSR_TYPE_SYSREG
1987 #define basename_BDK_AP_CNTP_CTL_EL0 "AP_CNTP_CTL_EL0"
1988 #define busnum_BDK_AP_CNTP_CTL_EL0 0
1989 #define arguments_BDK_AP_CNTP_CTL_EL0 -1,-1,-1,-1
1990 
1991 /**
1992  * Register (SYSREG) ap_cntp_ctl_el02
1993  *
1994  * AP Counter-timer Physical Timer Control Register
1995  * Alias of AP_CNTP_CTL_EL0 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
1996  */
1997 union bdk_ap_cntp_ctl_el02
1998 {
1999     uint32_t u;
2000     struct bdk_ap_cntp_ctl_el02_s
2001     {
2002 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2003         uint32_t reserved_0_31         : 32;
2004 #else /* Word 0 - Little Endian */
2005         uint32_t reserved_0_31         : 32;
2006 #endif /* Word 0 - End */
2007     } s;
2008     /* struct bdk_ap_cntp_ctl_el02_s cn; */
2009 };
2010 typedef union bdk_ap_cntp_ctl_el02 bdk_ap_cntp_ctl_el02_t;
2011 
2012 #define BDK_AP_CNTP_CTL_EL02 BDK_AP_CNTP_CTL_EL02_FUNC()
2013 static inline uint64_t BDK_AP_CNTP_CTL_EL02_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTP_CTL_EL02_FUNC(void)2014 static inline uint64_t BDK_AP_CNTP_CTL_EL02_FUNC(void)
2015 {
2016     return 0x3050e020100ll;
2017 }
2018 
2019 #define typedef_BDK_AP_CNTP_CTL_EL02 bdk_ap_cntp_ctl_el02_t
2020 #define bustype_BDK_AP_CNTP_CTL_EL02 BDK_CSR_TYPE_SYSREG
2021 #define basename_BDK_AP_CNTP_CTL_EL02 "AP_CNTP_CTL_EL02"
2022 #define busnum_BDK_AP_CNTP_CTL_EL02 0
2023 #define arguments_BDK_AP_CNTP_CTL_EL02 -1,-1,-1,-1
2024 
2025 /**
2026  * Register (SYSREG) ap_cntp_cval_el0
2027  *
2028  * AP Counter-timer Physical Timer Compare Value Register
2029  * Holds the compare value for the EL1 physical timer.
2030  */
2031 union bdk_ap_cntp_cval_el0
2032 {
2033     uint64_t u;
2034     struct bdk_ap_cntp_cval_el0_s
2035     {
2036 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2037         uint64_t data                  : 64; /**< [ 63:  0](R/W) EL1 physical timer compare value. */
2038 #else /* Word 0 - Little Endian */
2039         uint64_t data                  : 64; /**< [ 63:  0](R/W) EL1 physical timer compare value. */
2040 #endif /* Word 0 - End */
2041     } s;
2042     /* struct bdk_ap_cntp_cval_el0_s cn; */
2043 };
2044 typedef union bdk_ap_cntp_cval_el0 bdk_ap_cntp_cval_el0_t;
2045 
2046 #define BDK_AP_CNTP_CVAL_EL0 BDK_AP_CNTP_CVAL_EL0_FUNC()
2047 static inline uint64_t BDK_AP_CNTP_CVAL_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTP_CVAL_EL0_FUNC(void)2048 static inline uint64_t BDK_AP_CNTP_CVAL_EL0_FUNC(void)
2049 {
2050     return 0x3030e020200ll;
2051 }
2052 
2053 #define typedef_BDK_AP_CNTP_CVAL_EL0 bdk_ap_cntp_cval_el0_t
2054 #define bustype_BDK_AP_CNTP_CVAL_EL0 BDK_CSR_TYPE_SYSREG
2055 #define basename_BDK_AP_CNTP_CVAL_EL0 "AP_CNTP_CVAL_EL0"
2056 #define busnum_BDK_AP_CNTP_CVAL_EL0 0
2057 #define arguments_BDK_AP_CNTP_CVAL_EL0 -1,-1,-1,-1
2058 
2059 /**
2060  * Register (SYSREG) ap_cntp_cval_el02
2061  *
2062  * AP Counter-timer Physical Timer Compare Value Register
2063  * Alias of AP_CNTP_CVAL_EL0 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
2064  */
2065 union bdk_ap_cntp_cval_el02
2066 {
2067     uint64_t u;
2068     struct bdk_ap_cntp_cval_el02_s
2069     {
2070 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2071         uint64_t reserved_0_63         : 64;
2072 #else /* Word 0 - Little Endian */
2073         uint64_t reserved_0_63         : 64;
2074 #endif /* Word 0 - End */
2075     } s;
2076     /* struct bdk_ap_cntp_cval_el02_s cn; */
2077 };
2078 typedef union bdk_ap_cntp_cval_el02 bdk_ap_cntp_cval_el02_t;
2079 
2080 #define BDK_AP_CNTP_CVAL_EL02 BDK_AP_CNTP_CVAL_EL02_FUNC()
2081 static inline uint64_t BDK_AP_CNTP_CVAL_EL02_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTP_CVAL_EL02_FUNC(void)2082 static inline uint64_t BDK_AP_CNTP_CVAL_EL02_FUNC(void)
2083 {
2084     return 0x3050e020200ll;
2085 }
2086 
2087 #define typedef_BDK_AP_CNTP_CVAL_EL02 bdk_ap_cntp_cval_el02_t
2088 #define bustype_BDK_AP_CNTP_CVAL_EL02 BDK_CSR_TYPE_SYSREG
2089 #define basename_BDK_AP_CNTP_CVAL_EL02 "AP_CNTP_CVAL_EL02"
2090 #define busnum_BDK_AP_CNTP_CVAL_EL02 0
2091 #define arguments_BDK_AP_CNTP_CVAL_EL02 -1,-1,-1,-1
2092 
2093 /**
2094  * Register (SYSREG) ap_cntp_tval_el0
2095  *
2096  * AP Counter-timer Physical Timer Value Register
2097  * Holds the timer value for the EL1 physical timer.
2098  */
2099 union bdk_ap_cntp_tval_el0
2100 {
2101     uint32_t u;
2102     struct bdk_ap_cntp_tval_el0_s
2103     {
2104 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2105         uint32_t data                  : 32; /**< [ 31:  0](R/W) EL1 physical timer value. */
2106 #else /* Word 0 - Little Endian */
2107         uint32_t data                  : 32; /**< [ 31:  0](R/W) EL1 physical timer value. */
2108 #endif /* Word 0 - End */
2109     } s;
2110     /* struct bdk_ap_cntp_tval_el0_s cn; */
2111 };
2112 typedef union bdk_ap_cntp_tval_el0 bdk_ap_cntp_tval_el0_t;
2113 
2114 #define BDK_AP_CNTP_TVAL_EL0 BDK_AP_CNTP_TVAL_EL0_FUNC()
2115 static inline uint64_t BDK_AP_CNTP_TVAL_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTP_TVAL_EL0_FUNC(void)2116 static inline uint64_t BDK_AP_CNTP_TVAL_EL0_FUNC(void)
2117 {
2118     return 0x3030e020000ll;
2119 }
2120 
2121 #define typedef_BDK_AP_CNTP_TVAL_EL0 bdk_ap_cntp_tval_el0_t
2122 #define bustype_BDK_AP_CNTP_TVAL_EL0 BDK_CSR_TYPE_SYSREG
2123 #define basename_BDK_AP_CNTP_TVAL_EL0 "AP_CNTP_TVAL_EL0"
2124 #define busnum_BDK_AP_CNTP_TVAL_EL0 0
2125 #define arguments_BDK_AP_CNTP_TVAL_EL0 -1,-1,-1,-1
2126 
2127 /**
2128  * Register (SYSREG) ap_cntp_tval_el02
2129  *
2130  * AP Counter-timer Physical Timer Value Register
2131  * Alias of CNTP_TVAL_EL1 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
2132  */
2133 union bdk_ap_cntp_tval_el02
2134 {
2135     uint32_t u;
2136     struct bdk_ap_cntp_tval_el02_s
2137     {
2138 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2139         uint32_t reserved_0_31         : 32;
2140 #else /* Word 0 - Little Endian */
2141         uint32_t reserved_0_31         : 32;
2142 #endif /* Word 0 - End */
2143     } s;
2144     /* struct bdk_ap_cntp_tval_el02_s cn; */
2145 };
2146 typedef union bdk_ap_cntp_tval_el02 bdk_ap_cntp_tval_el02_t;
2147 
2148 #define BDK_AP_CNTP_TVAL_EL02 BDK_AP_CNTP_TVAL_EL02_FUNC()
2149 static inline uint64_t BDK_AP_CNTP_TVAL_EL02_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTP_TVAL_EL02_FUNC(void)2150 static inline uint64_t BDK_AP_CNTP_TVAL_EL02_FUNC(void)
2151 {
2152     return 0x3050e020000ll;
2153 }
2154 
2155 #define typedef_BDK_AP_CNTP_TVAL_EL02 bdk_ap_cntp_tval_el02_t
2156 #define bustype_BDK_AP_CNTP_TVAL_EL02 BDK_CSR_TYPE_SYSREG
2157 #define basename_BDK_AP_CNTP_TVAL_EL02 "AP_CNTP_TVAL_EL02"
2158 #define busnum_BDK_AP_CNTP_TVAL_EL02 0
2159 #define arguments_BDK_AP_CNTP_TVAL_EL02 -1,-1,-1,-1
2160 
2161 /**
2162  * Register (SYSREG) ap_cntpct_el0
2163  *
2164  * AP Counter-timer Physical Count Register
2165  * Holds the 64-bit physical count value.
2166  */
2167 union bdk_ap_cntpct_el0
2168 {
2169     uint64_t u;
2170     struct bdk_ap_cntpct_el0_s
2171     {
2172 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2173         uint64_t data                  : 64; /**< [ 63:  0](RO) Physical count value. */
2174 #else /* Word 0 - Little Endian */
2175         uint64_t data                  : 64; /**< [ 63:  0](RO) Physical count value. */
2176 #endif /* Word 0 - End */
2177     } s;
2178     /* struct bdk_ap_cntpct_el0_s cn; */
2179 };
2180 typedef union bdk_ap_cntpct_el0 bdk_ap_cntpct_el0_t;
2181 
2182 #define BDK_AP_CNTPCT_EL0 BDK_AP_CNTPCT_EL0_FUNC()
2183 static inline uint64_t BDK_AP_CNTPCT_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTPCT_EL0_FUNC(void)2184 static inline uint64_t BDK_AP_CNTPCT_EL0_FUNC(void)
2185 {
2186     return 0x3030e000100ll;
2187 }
2188 
2189 #define typedef_BDK_AP_CNTPCT_EL0 bdk_ap_cntpct_el0_t
2190 #define bustype_BDK_AP_CNTPCT_EL0 BDK_CSR_TYPE_SYSREG
2191 #define basename_BDK_AP_CNTPCT_EL0 "AP_CNTPCT_EL0"
2192 #define busnum_BDK_AP_CNTPCT_EL0 0
2193 #define arguments_BDK_AP_CNTPCT_EL0 -1,-1,-1,-1
2194 
2195 /**
2196  * Register (SYSREG) ap_cntps_ctl_el1
2197  *
2198  * AP Counter-timer Physical Secure Timer Control Register
2199  * Control register for the secure physical timer, usually
2200  *     accessible at EL3 but configurably accessible at EL1 in Secure
2201  *     state.
2202  */
2203 union bdk_ap_cntps_ctl_el1
2204 {
2205     uint32_t u;
2206     struct bdk_ap_cntps_ctl_el1_s
2207     {
2208 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2209         uint32_t reserved_3_31         : 29;
2210         uint32_t istatus               : 1;  /**< [  2:  2](RO) The status of the timer interrupt. This bit is read-only.
2211                                                                  A register write that sets IMASK to 1 latches this bit to
2212                                                                      reflect the status of the interrupt immediately before that
2213                                                                      write.
2214                                                                  0 = Interrupt not asserted.
2215                                                                  1 = Interrupt asserted. */
2216         uint32_t imask                 : 1;  /**< [  1:  1](R/W) Timer interrupt mask bit.
2217                                                                  0 = Timer interrupt is not masked.
2218                                                                  1 = Timer interrupt is masked. */
2219         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables the timer.
2220                                                                  Disabling the timer masks the timer interrupt, but the timer
2221                                                                      value continues to count down.
2222                                                                  0 = Timer disabled.
2223                                                                  1 = Timer enabled. */
2224 #else /* Word 0 - Little Endian */
2225         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables the timer.
2226                                                                  Disabling the timer masks the timer interrupt, but the timer
2227                                                                      value continues to count down.
2228                                                                  0 = Timer disabled.
2229                                                                  1 = Timer enabled. */
2230         uint32_t imask                 : 1;  /**< [  1:  1](R/W) Timer interrupt mask bit.
2231                                                                  0 = Timer interrupt is not masked.
2232                                                                  1 = Timer interrupt is masked. */
2233         uint32_t istatus               : 1;  /**< [  2:  2](RO) The status of the timer interrupt. This bit is read-only.
2234                                                                  A register write that sets IMASK to 1 latches this bit to
2235                                                                      reflect the status of the interrupt immediately before that
2236                                                                      write.
2237                                                                  0 = Interrupt not asserted.
2238                                                                  1 = Interrupt asserted. */
2239         uint32_t reserved_3_31         : 29;
2240 #endif /* Word 0 - End */
2241     } s;
2242     /* struct bdk_ap_cntps_ctl_el1_s cn; */
2243 };
2244 typedef union bdk_ap_cntps_ctl_el1 bdk_ap_cntps_ctl_el1_t;
2245 
2246 #define BDK_AP_CNTPS_CTL_EL1 BDK_AP_CNTPS_CTL_EL1_FUNC()
2247 static inline uint64_t BDK_AP_CNTPS_CTL_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTPS_CTL_EL1_FUNC(void)2248 static inline uint64_t BDK_AP_CNTPS_CTL_EL1_FUNC(void)
2249 {
2250     return 0x3070e020100ll;
2251 }
2252 
2253 #define typedef_BDK_AP_CNTPS_CTL_EL1 bdk_ap_cntps_ctl_el1_t
2254 #define bustype_BDK_AP_CNTPS_CTL_EL1 BDK_CSR_TYPE_SYSREG
2255 #define basename_BDK_AP_CNTPS_CTL_EL1 "AP_CNTPS_CTL_EL1"
2256 #define busnum_BDK_AP_CNTPS_CTL_EL1 0
2257 #define arguments_BDK_AP_CNTPS_CTL_EL1 -1,-1,-1,-1
2258 
2259 /**
2260  * Register (SYSREG) ap_cntps_cval_el1
2261  *
2262  * AP Counter-timer Physical Secure Timer Compare Value Register
2263  * Holds the compare value for the secure physical timer, usually
2264  *     accessible at EL3 but configurably accessible at EL1 in Secure
2265  *     state.
2266  */
2267 union bdk_ap_cntps_cval_el1
2268 {
2269     uint64_t u;
2270     struct bdk_ap_cntps_cval_el1_s
2271     {
2272 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2273         uint64_t data                  : 64; /**< [ 63:  0](R/W) Secure physical timer compare value. */
2274 #else /* Word 0 - Little Endian */
2275         uint64_t data                  : 64; /**< [ 63:  0](R/W) Secure physical timer compare value. */
2276 #endif /* Word 0 - End */
2277     } s;
2278     /* struct bdk_ap_cntps_cval_el1_s cn; */
2279 };
2280 typedef union bdk_ap_cntps_cval_el1 bdk_ap_cntps_cval_el1_t;
2281 
2282 #define BDK_AP_CNTPS_CVAL_EL1 BDK_AP_CNTPS_CVAL_EL1_FUNC()
2283 static inline uint64_t BDK_AP_CNTPS_CVAL_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTPS_CVAL_EL1_FUNC(void)2284 static inline uint64_t BDK_AP_CNTPS_CVAL_EL1_FUNC(void)
2285 {
2286     return 0x3070e020200ll;
2287 }
2288 
2289 #define typedef_BDK_AP_CNTPS_CVAL_EL1 bdk_ap_cntps_cval_el1_t
2290 #define bustype_BDK_AP_CNTPS_CVAL_EL1 BDK_CSR_TYPE_SYSREG
2291 #define basename_BDK_AP_CNTPS_CVAL_EL1 "AP_CNTPS_CVAL_EL1"
2292 #define busnum_BDK_AP_CNTPS_CVAL_EL1 0
2293 #define arguments_BDK_AP_CNTPS_CVAL_EL1 -1,-1,-1,-1
2294 
2295 /**
2296  * Register (SYSREG) ap_cntps_tval_el1
2297  *
2298  * AP Counter-timer Physical Secure Timer Value Register
2299  * This register holds the timer value for the secure physical timer, usually
2300  * accessible at EL3 but configurably accessible at EL1 in the secure state.
2301  */
2302 union bdk_ap_cntps_tval_el1
2303 {
2304     uint32_t u;
2305     struct bdk_ap_cntps_tval_el1_s
2306     {
2307 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2308         uint32_t data                  : 32; /**< [ 31:  0](R/W) Secure physical timer value. */
2309 #else /* Word 0 - Little Endian */
2310         uint32_t data                  : 32; /**< [ 31:  0](R/W) Secure physical timer value. */
2311 #endif /* Word 0 - End */
2312     } s;
2313     /* struct bdk_ap_cntps_tval_el1_s cn; */
2314 };
2315 typedef union bdk_ap_cntps_tval_el1 bdk_ap_cntps_tval_el1_t;
2316 
2317 #define BDK_AP_CNTPS_TVAL_EL1 BDK_AP_CNTPS_TVAL_EL1_FUNC()
2318 static inline uint64_t BDK_AP_CNTPS_TVAL_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTPS_TVAL_EL1_FUNC(void)2319 static inline uint64_t BDK_AP_CNTPS_TVAL_EL1_FUNC(void)
2320 {
2321     return 0x3070e020000ll;
2322 }
2323 
2324 #define typedef_BDK_AP_CNTPS_TVAL_EL1 bdk_ap_cntps_tval_el1_t
2325 #define bustype_BDK_AP_CNTPS_TVAL_EL1 BDK_CSR_TYPE_SYSREG
2326 #define basename_BDK_AP_CNTPS_TVAL_EL1 "AP_CNTPS_TVAL_EL1"
2327 #define busnum_BDK_AP_CNTPS_TVAL_EL1 0
2328 #define arguments_BDK_AP_CNTPS_TVAL_EL1 -1,-1,-1,-1
2329 
2330 /**
2331  * Register (SYSREG) ap_cntv_ctl_el0
2332  *
2333  * AP Counter-timer Virtual Timer Control Register
2334  * Control register for the virtual timer.
2335  */
2336 union bdk_ap_cntv_ctl_el0
2337 {
2338     uint32_t u;
2339     struct bdk_ap_cntv_ctl_el0_s
2340     {
2341 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2342         uint32_t reserved_3_31         : 29;
2343         uint32_t istatus               : 1;  /**< [  2:  2](RO) The status of the timer interrupt. This bit is read-only.
2344                                                                  A register write that sets IMASK to 1 latches this bit to
2345                                                                      reflect the status of the interrupt immediately before that
2346                                                                      write.
2347                                                                  0 = Interrupt not asserted.
2348                                                                  1 = Interrupt asserted. */
2349         uint32_t imask                 : 1;  /**< [  1:  1](R/W) Timer interrupt mask bit.
2350                                                                  0 = Timer interrupt is not masked.
2351                                                                  1 = Timer interrupt is masked. */
2352         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables the timer.
2353                                                                  Disabling the timer masks the timer interrupt, but the timer
2354                                                                      value continues to count down.
2355                                                                  0 = Timer disabled.
2356                                                                  1 = Timer enabled. */
2357 #else /* Word 0 - Little Endian */
2358         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables the timer.
2359                                                                  Disabling the timer masks the timer interrupt, but the timer
2360                                                                      value continues to count down.
2361                                                                  0 = Timer disabled.
2362                                                                  1 = Timer enabled. */
2363         uint32_t imask                 : 1;  /**< [  1:  1](R/W) Timer interrupt mask bit.
2364                                                                  0 = Timer interrupt is not masked.
2365                                                                  1 = Timer interrupt is masked. */
2366         uint32_t istatus               : 1;  /**< [  2:  2](RO) The status of the timer interrupt. This bit is read-only.
2367                                                                  A register write that sets IMASK to 1 latches this bit to
2368                                                                      reflect the status of the interrupt immediately before that
2369                                                                      write.
2370                                                                  0 = Interrupt not asserted.
2371                                                                  1 = Interrupt asserted. */
2372         uint32_t reserved_3_31         : 29;
2373 #endif /* Word 0 - End */
2374     } s;
2375     /* struct bdk_ap_cntv_ctl_el0_s cn; */
2376 };
2377 typedef union bdk_ap_cntv_ctl_el0 bdk_ap_cntv_ctl_el0_t;
2378 
2379 #define BDK_AP_CNTV_CTL_EL0 BDK_AP_CNTV_CTL_EL0_FUNC()
2380 static inline uint64_t BDK_AP_CNTV_CTL_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTV_CTL_EL0_FUNC(void)2381 static inline uint64_t BDK_AP_CNTV_CTL_EL0_FUNC(void)
2382 {
2383     return 0x3030e030100ll;
2384 }
2385 
2386 #define typedef_BDK_AP_CNTV_CTL_EL0 bdk_ap_cntv_ctl_el0_t
2387 #define bustype_BDK_AP_CNTV_CTL_EL0 BDK_CSR_TYPE_SYSREG
2388 #define basename_BDK_AP_CNTV_CTL_EL0 "AP_CNTV_CTL_EL0"
2389 #define busnum_BDK_AP_CNTV_CTL_EL0 0
2390 #define arguments_BDK_AP_CNTV_CTL_EL0 -1,-1,-1,-1
2391 
2392 /**
2393  * Register (SYSREG) ap_cntv_ctl_el02
2394  *
2395  * AP Counter-timer Virtual Timer Control Register
2396  * Alias of AP_CNTV_CTL_EL0 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
2397  */
2398 union bdk_ap_cntv_ctl_el02
2399 {
2400     uint32_t u;
2401     struct bdk_ap_cntv_ctl_el02_s
2402     {
2403 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2404         uint32_t reserved_0_31         : 32;
2405 #else /* Word 0 - Little Endian */
2406         uint32_t reserved_0_31         : 32;
2407 #endif /* Word 0 - End */
2408     } s;
2409     /* struct bdk_ap_cntv_ctl_el02_s cn; */
2410 };
2411 typedef union bdk_ap_cntv_ctl_el02 bdk_ap_cntv_ctl_el02_t;
2412 
2413 #define BDK_AP_CNTV_CTL_EL02 BDK_AP_CNTV_CTL_EL02_FUNC()
2414 static inline uint64_t BDK_AP_CNTV_CTL_EL02_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTV_CTL_EL02_FUNC(void)2415 static inline uint64_t BDK_AP_CNTV_CTL_EL02_FUNC(void)
2416 {
2417     return 0x3050e030100ll;
2418 }
2419 
2420 #define typedef_BDK_AP_CNTV_CTL_EL02 bdk_ap_cntv_ctl_el02_t
2421 #define bustype_BDK_AP_CNTV_CTL_EL02 BDK_CSR_TYPE_SYSREG
2422 #define basename_BDK_AP_CNTV_CTL_EL02 "AP_CNTV_CTL_EL02"
2423 #define busnum_BDK_AP_CNTV_CTL_EL02 0
2424 #define arguments_BDK_AP_CNTV_CTL_EL02 -1,-1,-1,-1
2425 
2426 /**
2427  * Register (SYSREG) ap_cntv_cval_el0
2428  *
2429  * AP Counter-timer Virtual Timer Compare Value Register
2430  * Holds the compare value for the virtual timer.
2431  */
2432 union bdk_ap_cntv_cval_el0
2433 {
2434     uint64_t u;
2435     struct bdk_ap_cntv_cval_el0_s
2436     {
2437 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2438         uint64_t data                  : 64; /**< [ 63:  0](R/W) Virtual timer compare value. */
2439 #else /* Word 0 - Little Endian */
2440         uint64_t data                  : 64; /**< [ 63:  0](R/W) Virtual timer compare value. */
2441 #endif /* Word 0 - End */
2442     } s;
2443     /* struct bdk_ap_cntv_cval_el0_s cn; */
2444 };
2445 typedef union bdk_ap_cntv_cval_el0 bdk_ap_cntv_cval_el0_t;
2446 
2447 #define BDK_AP_CNTV_CVAL_EL0 BDK_AP_CNTV_CVAL_EL0_FUNC()
2448 static inline uint64_t BDK_AP_CNTV_CVAL_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTV_CVAL_EL0_FUNC(void)2449 static inline uint64_t BDK_AP_CNTV_CVAL_EL0_FUNC(void)
2450 {
2451     return 0x3030e030200ll;
2452 }
2453 
2454 #define typedef_BDK_AP_CNTV_CVAL_EL0 bdk_ap_cntv_cval_el0_t
2455 #define bustype_BDK_AP_CNTV_CVAL_EL0 BDK_CSR_TYPE_SYSREG
2456 #define basename_BDK_AP_CNTV_CVAL_EL0 "AP_CNTV_CVAL_EL0"
2457 #define busnum_BDK_AP_CNTV_CVAL_EL0 0
2458 #define arguments_BDK_AP_CNTV_CVAL_EL0 -1,-1,-1,-1
2459 
2460 /**
2461  * Register (SYSREG) ap_cntv_cval_el02
2462  *
2463  * AP Counter-timer Virtual Timer Compare Value Register
2464  * Alias of AP_CNTV_CVAL_EL0 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
2465  */
2466 union bdk_ap_cntv_cval_el02
2467 {
2468     uint64_t u;
2469     struct bdk_ap_cntv_cval_el02_s
2470     {
2471 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2472         uint64_t reserved_0_63         : 64;
2473 #else /* Word 0 - Little Endian */
2474         uint64_t reserved_0_63         : 64;
2475 #endif /* Word 0 - End */
2476     } s;
2477     /* struct bdk_ap_cntv_cval_el02_s cn; */
2478 };
2479 typedef union bdk_ap_cntv_cval_el02 bdk_ap_cntv_cval_el02_t;
2480 
2481 #define BDK_AP_CNTV_CVAL_EL02 BDK_AP_CNTV_CVAL_EL02_FUNC()
2482 static inline uint64_t BDK_AP_CNTV_CVAL_EL02_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTV_CVAL_EL02_FUNC(void)2483 static inline uint64_t BDK_AP_CNTV_CVAL_EL02_FUNC(void)
2484 {
2485     return 0x3050e030200ll;
2486 }
2487 
2488 #define typedef_BDK_AP_CNTV_CVAL_EL02 bdk_ap_cntv_cval_el02_t
2489 #define bustype_BDK_AP_CNTV_CVAL_EL02 BDK_CSR_TYPE_SYSREG
2490 #define basename_BDK_AP_CNTV_CVAL_EL02 "AP_CNTV_CVAL_EL02"
2491 #define busnum_BDK_AP_CNTV_CVAL_EL02 0
2492 #define arguments_BDK_AP_CNTV_CVAL_EL02 -1,-1,-1,-1
2493 
2494 /**
2495  * Register (SYSREG) ap_cntv_tval_el0
2496  *
2497  * AP Counter-timer Virtual Timer Value Register
2498  * Holds the timer value for the virtual timer.
2499  */
2500 union bdk_ap_cntv_tval_el0
2501 {
2502     uint32_t u;
2503     struct bdk_ap_cntv_tval_el0_s
2504     {
2505 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2506         uint32_t data                  : 32; /**< [ 31:  0](R/W) Virtual timer value. */
2507 #else /* Word 0 - Little Endian */
2508         uint32_t data                  : 32; /**< [ 31:  0](R/W) Virtual timer value. */
2509 #endif /* Word 0 - End */
2510     } s;
2511     /* struct bdk_ap_cntv_tval_el0_s cn; */
2512 };
2513 typedef union bdk_ap_cntv_tval_el0 bdk_ap_cntv_tval_el0_t;
2514 
2515 #define BDK_AP_CNTV_TVAL_EL0 BDK_AP_CNTV_TVAL_EL0_FUNC()
2516 static inline uint64_t BDK_AP_CNTV_TVAL_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTV_TVAL_EL0_FUNC(void)2517 static inline uint64_t BDK_AP_CNTV_TVAL_EL0_FUNC(void)
2518 {
2519     return 0x3030e030000ll;
2520 }
2521 
2522 #define typedef_BDK_AP_CNTV_TVAL_EL0 bdk_ap_cntv_tval_el0_t
2523 #define bustype_BDK_AP_CNTV_TVAL_EL0 BDK_CSR_TYPE_SYSREG
2524 #define basename_BDK_AP_CNTV_TVAL_EL0 "AP_CNTV_TVAL_EL0"
2525 #define busnum_BDK_AP_CNTV_TVAL_EL0 0
2526 #define arguments_BDK_AP_CNTV_TVAL_EL0 -1,-1,-1,-1
2527 
2528 /**
2529  * Register (SYSREG) ap_cntv_tval_el02
2530  *
2531  * AP Counter-timer Virtual Timer Value Register
2532  * Alias of AP_CNTV_TVAL_EL0 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
2533  */
2534 union bdk_ap_cntv_tval_el02
2535 {
2536     uint32_t u;
2537     struct bdk_ap_cntv_tval_el02_s
2538     {
2539 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2540         uint32_t reserved_0_31         : 32;
2541 #else /* Word 0 - Little Endian */
2542         uint32_t reserved_0_31         : 32;
2543 #endif /* Word 0 - End */
2544     } s;
2545     /* struct bdk_ap_cntv_tval_el02_s cn; */
2546 };
2547 typedef union bdk_ap_cntv_tval_el02 bdk_ap_cntv_tval_el02_t;
2548 
2549 #define BDK_AP_CNTV_TVAL_EL02 BDK_AP_CNTV_TVAL_EL02_FUNC()
2550 static inline uint64_t BDK_AP_CNTV_TVAL_EL02_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTV_TVAL_EL02_FUNC(void)2551 static inline uint64_t BDK_AP_CNTV_TVAL_EL02_FUNC(void)
2552 {
2553     return 0x3050e030000ll;
2554 }
2555 
2556 #define typedef_BDK_AP_CNTV_TVAL_EL02 bdk_ap_cntv_tval_el02_t
2557 #define bustype_BDK_AP_CNTV_TVAL_EL02 BDK_CSR_TYPE_SYSREG
2558 #define basename_BDK_AP_CNTV_TVAL_EL02 "AP_CNTV_TVAL_EL02"
2559 #define busnum_BDK_AP_CNTV_TVAL_EL02 0
2560 #define arguments_BDK_AP_CNTV_TVAL_EL02 -1,-1,-1,-1
2561 
2562 /**
2563  * Register (SYSREG) ap_cntvct_el0
2564  *
2565  * AP Counter-timer Virtual Count Register
2566  * Holds the 64-bit virtual count value.
2567  */
2568 union bdk_ap_cntvct_el0
2569 {
2570     uint64_t u;
2571     struct bdk_ap_cntvct_el0_s
2572     {
2573 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2574         uint64_t data                  : 64; /**< [ 63:  0](RO) Virtual count value. */
2575 #else /* Word 0 - Little Endian */
2576         uint64_t data                  : 64; /**< [ 63:  0](RO) Virtual count value. */
2577 #endif /* Word 0 - End */
2578     } s;
2579     /* struct bdk_ap_cntvct_el0_s cn; */
2580 };
2581 typedef union bdk_ap_cntvct_el0 bdk_ap_cntvct_el0_t;
2582 
2583 #define BDK_AP_CNTVCT_EL0 BDK_AP_CNTVCT_EL0_FUNC()
2584 static inline uint64_t BDK_AP_CNTVCT_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTVCT_EL0_FUNC(void)2585 static inline uint64_t BDK_AP_CNTVCT_EL0_FUNC(void)
2586 {
2587     return 0x3030e000200ll;
2588 }
2589 
2590 #define typedef_BDK_AP_CNTVCT_EL0 bdk_ap_cntvct_el0_t
2591 #define bustype_BDK_AP_CNTVCT_EL0 BDK_CSR_TYPE_SYSREG
2592 #define basename_BDK_AP_CNTVCT_EL0 "AP_CNTVCT_EL0"
2593 #define busnum_BDK_AP_CNTVCT_EL0 0
2594 #define arguments_BDK_AP_CNTVCT_EL0 -1,-1,-1,-1
2595 
2596 /**
2597  * Register (SYSREG) ap_cntvoff_el2
2598  *
2599  * AP Counter-timer Virtual Offset Register
2600  * Holds the 64-bit virtual offset.
2601  */
2602 union bdk_ap_cntvoff_el2
2603 {
2604     uint64_t u;
2605     struct bdk_ap_cntvoff_el2_s
2606     {
2607 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2608         uint64_t data                  : 64; /**< [ 63:  0](R/W) Virtual offset. */
2609 #else /* Word 0 - Little Endian */
2610         uint64_t data                  : 64; /**< [ 63:  0](R/W) Virtual offset. */
2611 #endif /* Word 0 - End */
2612     } s;
2613     /* struct bdk_ap_cntvoff_el2_s cn; */
2614 };
2615 typedef union bdk_ap_cntvoff_el2 bdk_ap_cntvoff_el2_t;
2616 
2617 #define BDK_AP_CNTVOFF_EL2 BDK_AP_CNTVOFF_EL2_FUNC()
2618 static inline uint64_t BDK_AP_CNTVOFF_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CNTVOFF_EL2_FUNC(void)2619 static inline uint64_t BDK_AP_CNTVOFF_EL2_FUNC(void)
2620 {
2621     return 0x3040e000300ll;
2622 }
2623 
2624 #define typedef_BDK_AP_CNTVOFF_EL2 bdk_ap_cntvoff_el2_t
2625 #define bustype_BDK_AP_CNTVOFF_EL2 BDK_CSR_TYPE_SYSREG
2626 #define basename_BDK_AP_CNTVOFF_EL2 "AP_CNTVOFF_EL2"
2627 #define busnum_BDK_AP_CNTVOFF_EL2 0
2628 #define arguments_BDK_AP_CNTVOFF_EL2 -1,-1,-1,-1
2629 
2630 /**
2631  * Register (SYSREG) ap_contextidr_el1
2632  *
2633  * AP Context ID Register
2634  * Identifies the current Process Identifier.
2635  */
2636 union bdk_ap_contextidr_el1
2637 {
2638     uint32_t u;
2639     struct bdk_ap_contextidr_el1_s
2640     {
2641 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2642         uint32_t procid                : 32; /**< [ 31:  0](R/W) Process Identifier. This field must be programmed with a
2643                                                                      unique value that identifies the current process. The bottom 8
2644                                                                      bits of this register are not used to hold the ASID. */
2645 #else /* Word 0 - Little Endian */
2646         uint32_t procid                : 32; /**< [ 31:  0](R/W) Process Identifier. This field must be programmed with a
2647                                                                      unique value that identifies the current process. The bottom 8
2648                                                                      bits of this register are not used to hold the ASID. */
2649 #endif /* Word 0 - End */
2650     } s;
2651     /* struct bdk_ap_contextidr_el1_s cn; */
2652 };
2653 typedef union bdk_ap_contextidr_el1 bdk_ap_contextidr_el1_t;
2654 
2655 #define BDK_AP_CONTEXTIDR_EL1 BDK_AP_CONTEXTIDR_EL1_FUNC()
2656 static inline uint64_t BDK_AP_CONTEXTIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CONTEXTIDR_EL1_FUNC(void)2657 static inline uint64_t BDK_AP_CONTEXTIDR_EL1_FUNC(void)
2658 {
2659     return 0x3000d000100ll;
2660 }
2661 
2662 #define typedef_BDK_AP_CONTEXTIDR_EL1 bdk_ap_contextidr_el1_t
2663 #define bustype_BDK_AP_CONTEXTIDR_EL1 BDK_CSR_TYPE_SYSREG
2664 #define basename_BDK_AP_CONTEXTIDR_EL1 "AP_CONTEXTIDR_EL1"
2665 #define busnum_BDK_AP_CONTEXTIDR_EL1 0
2666 #define arguments_BDK_AP_CONTEXTIDR_EL1 -1,-1,-1,-1
2667 
2668 /**
2669  * Register (SYSREG) ap_contextidr_el12
2670  *
2671  * AP Context ID Register
2672  * Alias of AP_CONTEXTIDR_EL1 when accessed at EL2/2 and AP_HCR_EL2[E2H] is set.
2673  */
2674 union bdk_ap_contextidr_el12
2675 {
2676     uint32_t u;
2677     struct bdk_ap_contextidr_el12_s
2678     {
2679 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2680         uint32_t reserved_0_31         : 32;
2681 #else /* Word 0 - Little Endian */
2682         uint32_t reserved_0_31         : 32;
2683 #endif /* Word 0 - End */
2684     } s;
2685     /* struct bdk_ap_contextidr_el12_s cn; */
2686 };
2687 typedef union bdk_ap_contextidr_el12 bdk_ap_contextidr_el12_t;
2688 
2689 #define BDK_AP_CONTEXTIDR_EL12 BDK_AP_CONTEXTIDR_EL12_FUNC()
2690 static inline uint64_t BDK_AP_CONTEXTIDR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CONTEXTIDR_EL12_FUNC(void)2691 static inline uint64_t BDK_AP_CONTEXTIDR_EL12_FUNC(void)
2692 {
2693     return 0x3050d000100ll;
2694 }
2695 
2696 #define typedef_BDK_AP_CONTEXTIDR_EL12 bdk_ap_contextidr_el12_t
2697 #define bustype_BDK_AP_CONTEXTIDR_EL12 BDK_CSR_TYPE_SYSREG
2698 #define basename_BDK_AP_CONTEXTIDR_EL12 "AP_CONTEXTIDR_EL12"
2699 #define busnum_BDK_AP_CONTEXTIDR_EL12 0
2700 #define arguments_BDK_AP_CONTEXTIDR_EL12 -1,-1,-1,-1
2701 
2702 /**
2703  * Register (SYSREG) ap_contextidr_el2
2704  *
2705  * AP Context ID EL2 Register
2706  * v8.1: Identifies the current Process Identifier.
2707  */
2708 union bdk_ap_contextidr_el2
2709 {
2710     uint32_t u;
2711     struct bdk_ap_contextidr_el2_s
2712     {
2713 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2714         uint32_t procid                : 32; /**< [ 31:  0](R/W) v8.1: Process Identifier. This field must be programmed with a
2715                                                                      unique value that identifies the current process. The bottom 8
2716                                                                      bits of this register are not used to hold the ASID. */
2717 #else /* Word 0 - Little Endian */
2718         uint32_t procid                : 32; /**< [ 31:  0](R/W) v8.1: Process Identifier. This field must be programmed with a
2719                                                                      unique value that identifies the current process. The bottom 8
2720                                                                      bits of this register are not used to hold the ASID. */
2721 #endif /* Word 0 - End */
2722     } s;
2723     /* struct bdk_ap_contextidr_el2_s cn; */
2724 };
2725 typedef union bdk_ap_contextidr_el2 bdk_ap_contextidr_el2_t;
2726 
2727 #define BDK_AP_CONTEXTIDR_EL2 BDK_AP_CONTEXTIDR_EL2_FUNC()
2728 static inline uint64_t BDK_AP_CONTEXTIDR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CONTEXTIDR_EL2_FUNC(void)2729 static inline uint64_t BDK_AP_CONTEXTIDR_EL2_FUNC(void)
2730 {
2731     return 0x3040d000100ll;
2732 }
2733 
2734 #define typedef_BDK_AP_CONTEXTIDR_EL2 bdk_ap_contextidr_el2_t
2735 #define bustype_BDK_AP_CONTEXTIDR_EL2 BDK_CSR_TYPE_SYSREG
2736 #define basename_BDK_AP_CONTEXTIDR_EL2 "AP_CONTEXTIDR_EL2"
2737 #define busnum_BDK_AP_CONTEXTIDR_EL2 0
2738 #define arguments_BDK_AP_CONTEXTIDR_EL2 -1,-1,-1,-1
2739 
2740 /**
2741  * Register (SYSREG) ap_cpacr_el1
2742  *
2743  * AP Architectural Feature Access Control Register
2744  * Controls access to Trace, Floating-point, and Advanced SIMD
2745  *     functionality.
2746  */
2747 union bdk_ap_cpacr_el1
2748 {
2749     uint32_t u;
2750     struct bdk_ap_cpacr_el1_s
2751     {
2752 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2753         uint32_t reserved_22_31        : 10;
2754         uint32_t fpen                  : 2;  /**< [ 21: 20](R/W) Causes instructions that access the registers associated with
2755                                                                      Floating Point and Advanced SIMD execution to trap to EL1 when
2756                                                                      executed from EL0 or EL1.
2757                                                                  0x0 = Causes any instructions in EL0 or EL1 that use the registers
2758                                                                      associated with Floating Point and Advanced SIMD execution to
2759                                                                      be trapped.
2760                                                                  0x1 = Causes any instructions in EL0 that use the registers
2761                                                                      associated with Floating Point and Advanced SIMD execution to
2762                                                                      be trapped, but does not cause any instruction in EL1 to be
2763                                                                      trapped.
2764                                                                  0x2 = Causes any instructions in EL0 or EL1 that use the registers
2765                                                                      associated with Floating Point and Advanced SIMD execution to
2766                                                                      be trapped.
2767                                                                  0x3 = Does not cause any instruction to be trapped. */
2768         uint32_t reserved_0_19         : 20;
2769 #else /* Word 0 - Little Endian */
2770         uint32_t reserved_0_19         : 20;
2771         uint32_t fpen                  : 2;  /**< [ 21: 20](R/W) Causes instructions that access the registers associated with
2772                                                                      Floating Point and Advanced SIMD execution to trap to EL1 when
2773                                                                      executed from EL0 or EL1.
2774                                                                  0x0 = Causes any instructions in EL0 or EL1 that use the registers
2775                                                                      associated with Floating Point and Advanced SIMD execution to
2776                                                                      be trapped.
2777                                                                  0x1 = Causes any instructions in EL0 that use the registers
2778                                                                      associated with Floating Point and Advanced SIMD execution to
2779                                                                      be trapped, but does not cause any instruction in EL1 to be
2780                                                                      trapped.
2781                                                                  0x2 = Causes any instructions in EL0 or EL1 that use the registers
2782                                                                      associated with Floating Point and Advanced SIMD execution to
2783                                                                      be trapped.
2784                                                                  0x3 = Does not cause any instruction to be trapped. */
2785         uint32_t reserved_22_31        : 10;
2786 #endif /* Word 0 - End */
2787     } s;
2788     struct bdk_ap_cpacr_el1_cn
2789     {
2790 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2791         uint32_t reserved_29_31        : 3;
2792         uint32_t reserved_28           : 1;
2793         uint32_t reserved_22_27        : 6;
2794         uint32_t fpen                  : 2;  /**< [ 21: 20](R/W) Causes instructions that access the registers associated with
2795                                                                      Floating Point and Advanced SIMD execution to trap to EL1 when
2796                                                                      executed from EL0 or EL1.
2797                                                                  0x0 = Causes any instructions in EL0 or EL1 that use the registers
2798                                                                      associated with Floating Point and Advanced SIMD execution to
2799                                                                      be trapped.
2800                                                                  0x1 = Causes any instructions in EL0 that use the registers
2801                                                                      associated with Floating Point and Advanced SIMD execution to
2802                                                                      be trapped, but does not cause any instruction in EL1 to be
2803                                                                      trapped.
2804                                                                  0x2 = Causes any instructions in EL0 or EL1 that use the registers
2805                                                                      associated with Floating Point and Advanced SIMD execution to
2806                                                                      be trapped.
2807                                                                  0x3 = Does not cause any instruction to be trapped. */
2808         uint32_t reserved_0_19         : 20;
2809 #else /* Word 0 - Little Endian */
2810         uint32_t reserved_0_19         : 20;
2811         uint32_t fpen                  : 2;  /**< [ 21: 20](R/W) Causes instructions that access the registers associated with
2812                                                                      Floating Point and Advanced SIMD execution to trap to EL1 when
2813                                                                      executed from EL0 or EL1.
2814                                                                  0x0 = Causes any instructions in EL0 or EL1 that use the registers
2815                                                                      associated with Floating Point and Advanced SIMD execution to
2816                                                                      be trapped.
2817                                                                  0x1 = Causes any instructions in EL0 that use the registers
2818                                                                      associated with Floating Point and Advanced SIMD execution to
2819                                                                      be trapped, but does not cause any instruction in EL1 to be
2820                                                                      trapped.
2821                                                                  0x2 = Causes any instructions in EL0 or EL1 that use the registers
2822                                                                      associated with Floating Point and Advanced SIMD execution to
2823                                                                      be trapped.
2824                                                                  0x3 = Does not cause any instruction to be trapped. */
2825         uint32_t reserved_22_27        : 6;
2826         uint32_t reserved_28           : 1;
2827         uint32_t reserved_29_31        : 3;
2828 #endif /* Word 0 - End */
2829     } cn;
2830 };
2831 typedef union bdk_ap_cpacr_el1 bdk_ap_cpacr_el1_t;
2832 
2833 #define BDK_AP_CPACR_EL1 BDK_AP_CPACR_EL1_FUNC()
2834 static inline uint64_t BDK_AP_CPACR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CPACR_EL1_FUNC(void)2835 static inline uint64_t BDK_AP_CPACR_EL1_FUNC(void)
2836 {
2837     return 0x30001000200ll;
2838 }
2839 
2840 #define typedef_BDK_AP_CPACR_EL1 bdk_ap_cpacr_el1_t
2841 #define bustype_BDK_AP_CPACR_EL1 BDK_CSR_TYPE_SYSREG
2842 #define basename_BDK_AP_CPACR_EL1 "AP_CPACR_EL1"
2843 #define busnum_BDK_AP_CPACR_EL1 0
2844 #define arguments_BDK_AP_CPACR_EL1 -1,-1,-1,-1
2845 
2846 /**
2847  * Register (SYSREG) ap_cpacr_el12
2848  *
2849  * AP Architectural Feature Access Control Register
2850  * Alias of AP_CPACR_EL1 when accessed from EL2 and AP_HCR_EL2[E2H] is set.
2851  */
2852 union bdk_ap_cpacr_el12
2853 {
2854     uint32_t u;
2855     struct bdk_ap_cpacr_el12_s
2856     {
2857 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2858         uint32_t reserved_0_31         : 32;
2859 #else /* Word 0 - Little Endian */
2860         uint32_t reserved_0_31         : 32;
2861 #endif /* Word 0 - End */
2862     } s;
2863     /* struct bdk_ap_cpacr_el12_s cn; */
2864 };
2865 typedef union bdk_ap_cpacr_el12 bdk_ap_cpacr_el12_t;
2866 
2867 #define BDK_AP_CPACR_EL12 BDK_AP_CPACR_EL12_FUNC()
2868 static inline uint64_t BDK_AP_CPACR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CPACR_EL12_FUNC(void)2869 static inline uint64_t BDK_AP_CPACR_EL12_FUNC(void)
2870 {
2871     return 0x30501000200ll;
2872 }
2873 
2874 #define typedef_BDK_AP_CPACR_EL12 bdk_ap_cpacr_el12_t
2875 #define bustype_BDK_AP_CPACR_EL12 BDK_CSR_TYPE_SYSREG
2876 #define basename_BDK_AP_CPACR_EL12 "AP_CPACR_EL12"
2877 #define busnum_BDK_AP_CPACR_EL12 0
2878 #define arguments_BDK_AP_CPACR_EL12 -1,-1,-1,-1
2879 
2880 /**
2881  * Register (SYSREG) ap_cptr_el2
2882  *
2883  * AP Architectural Feature Trap EL2 Non-E2H Register
2884  * Controls trapping to EL2 of access to CPACR, AP_CPACR_EL1, Trace
2885  *     functionality and registers associated with Floating Point and
2886  *     Advanced SIMD execution. Also controls EL2 access to this
2887  *     functionality.
2888  *
2889  * This register is at the same select as AP_CPTR_EL2_E2H and is used when E2H=0.
2890  */
2891 union bdk_ap_cptr_el2
2892 {
2893     uint32_t u;
2894     struct bdk_ap_cptr_el2_s
2895     {
2896 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2897         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to CPACR or AP_CPACR_EL1 from EL1 to
2898                                                                      trap to EL2.
2899                                                                  0 = Does not cause access to CPACR or AP_CPACR_EL1 to be trapped.
2900                                                                  1 = Causes access to CPACR or AP_CPACR_EL1 to be trapped. */
2901         uint32_t reserved_14_30        : 17;
2902         uint32_t rsvd_12_13            : 2;  /**< [ 13: 12](RO) Reserved 1. */
2903         uint32_t reserved_11           : 1;
2904         uint32_t tfp                   : 1;  /**< [ 10: 10](R/W) This causes instructions that access the registers associated
2905                                                                      with Floating Point and Advanced SIMD execution to trap to EL2
2906                                                                      when executed from EL0, EL1, or EL2, unless trapped to EL1.
2907 
2908                                                                  0 = Does not cause any instruction to be trapped.
2909                                                                  1 = Causes any instructions that use the registers associated with
2910                                                                      Floating Point and Advanced SIMD execution to be trapped. */
2911         uint32_t rsvd_0_9              : 10; /**< [  9:  0](RO) Reserved 1. */
2912 #else /* Word 0 - Little Endian */
2913         uint32_t rsvd_0_9              : 10; /**< [  9:  0](RO) Reserved 1. */
2914         uint32_t tfp                   : 1;  /**< [ 10: 10](R/W) This causes instructions that access the registers associated
2915                                                                      with Floating Point and Advanced SIMD execution to trap to EL2
2916                                                                      when executed from EL0, EL1, or EL2, unless trapped to EL1.
2917 
2918                                                                  0 = Does not cause any instruction to be trapped.
2919                                                                  1 = Causes any instructions that use the registers associated with
2920                                                                      Floating Point and Advanced SIMD execution to be trapped. */
2921         uint32_t reserved_11           : 1;
2922         uint32_t rsvd_12_13            : 2;  /**< [ 13: 12](RO) Reserved 1. */
2923         uint32_t reserved_14_30        : 17;
2924         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to CPACR or AP_CPACR_EL1 from EL1 to
2925                                                                      trap to EL2.
2926                                                                  0 = Does not cause access to CPACR or AP_CPACR_EL1 to be trapped.
2927                                                                  1 = Causes access to CPACR or AP_CPACR_EL1 to be trapped. */
2928 #endif /* Word 0 - End */
2929     } s;
2930     struct bdk_ap_cptr_el2_cn
2931     {
2932 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2933         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to CPACR or AP_CPACR_EL1 from EL1 to
2934                                                                      trap to EL2.
2935                                                                  0 = Does not cause access to CPACR or AP_CPACR_EL1 to be trapped.
2936                                                                  1 = Causes access to CPACR or AP_CPACR_EL1 to be trapped. */
2937         uint32_t reserved_29_30        : 2;
2938         uint32_t reserved_28           : 1;
2939         uint32_t reserved_20_27        : 8;
2940         uint32_t reserved_14_19        : 6;
2941         uint32_t rsvd_12_13            : 2;  /**< [ 13: 12](RO) Reserved 1. */
2942         uint32_t reserved_11           : 1;
2943         uint32_t tfp                   : 1;  /**< [ 10: 10](R/W) This causes instructions that access the registers associated
2944                                                                      with Floating Point and Advanced SIMD execution to trap to EL2
2945                                                                      when executed from EL0, EL1, or EL2, unless trapped to EL1.
2946 
2947                                                                  0 = Does not cause any instruction to be trapped.
2948                                                                  1 = Causes any instructions that use the registers associated with
2949                                                                      Floating Point and Advanced SIMD execution to be trapped. */
2950         uint32_t rsvd_0_9              : 10; /**< [  9:  0](RO) Reserved 1. */
2951 #else /* Word 0 - Little Endian */
2952         uint32_t rsvd_0_9              : 10; /**< [  9:  0](RO) Reserved 1. */
2953         uint32_t tfp                   : 1;  /**< [ 10: 10](R/W) This causes instructions that access the registers associated
2954                                                                      with Floating Point and Advanced SIMD execution to trap to EL2
2955                                                                      when executed from EL0, EL1, or EL2, unless trapped to EL1.
2956 
2957                                                                  0 = Does not cause any instruction to be trapped.
2958                                                                  1 = Causes any instructions that use the registers associated with
2959                                                                      Floating Point and Advanced SIMD execution to be trapped. */
2960         uint32_t reserved_11           : 1;
2961         uint32_t rsvd_12_13            : 2;  /**< [ 13: 12](RO) Reserved 1. */
2962         uint32_t reserved_14_19        : 6;
2963         uint32_t reserved_20_27        : 8;
2964         uint32_t reserved_28           : 1;
2965         uint32_t reserved_29_30        : 2;
2966         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to CPACR or AP_CPACR_EL1 from EL1 to
2967                                                                      trap to EL2.
2968                                                                  0 = Does not cause access to CPACR or AP_CPACR_EL1 to be trapped.
2969                                                                  1 = Causes access to CPACR or AP_CPACR_EL1 to be trapped. */
2970 #endif /* Word 0 - End */
2971     } cn;
2972 };
2973 typedef union bdk_ap_cptr_el2 bdk_ap_cptr_el2_t;
2974 
2975 #define BDK_AP_CPTR_EL2 BDK_AP_CPTR_EL2_FUNC()
2976 static inline uint64_t BDK_AP_CPTR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CPTR_EL2_FUNC(void)2977 static inline uint64_t BDK_AP_CPTR_EL2_FUNC(void)
2978 {
2979     return 0x30401010200ll;
2980 }
2981 
2982 #define typedef_BDK_AP_CPTR_EL2 bdk_ap_cptr_el2_t
2983 #define bustype_BDK_AP_CPTR_EL2 BDK_CSR_TYPE_SYSREG
2984 #define basename_BDK_AP_CPTR_EL2 "AP_CPTR_EL2"
2985 #define busnum_BDK_AP_CPTR_EL2 0
2986 #define arguments_BDK_AP_CPTR_EL2 -1,-1,-1,-1
2987 
2988 /**
2989  * Register (SYSREG) ap_cptr_el2_e2h
2990  *
2991  * AP Architectural Feature Trap EL2 E2H Register
2992  * Controls trapping to EL2 of access to CPACR, AP_CPACR_EL1, Trace
2993  *     functionality and registers associated with Floating Point and
2994  *     Advanced SIMD execution. Also controls EL2 access to this
2995  *     functionality.
2996  *
2997  * This register is at the same select as AP_CPTR_EL2 and is used when E2H=1.
2998  */
2999 union bdk_ap_cptr_el2_e2h
3000 {
3001     uint32_t u;
3002     struct bdk_ap_cptr_el2_e2h_s
3003     {
3004 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3005         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to CPACR or AP_CPACR_EL1 from EL1 to
3006                                                                      trap to EL2. When AP_HCR_EL2[TGE] == 0:
3007                                                                  0 = Does not cause access to CPACR or AP_CPACR_EL1 to be trapped.
3008                                                                  1 = Causes access to CPACR or AP_CPACR_EL1 to be trapped.
3009 
3010                                                                  When AP_HCR_EL2[TGE] == 1, this bit is ignored by hardware and
3011                                                                  does not cause access to the AP_CPACR_EL1 to be trapped. */
3012         uint32_t reserved_22_30        : 9;
3013         uint32_t fpen                  : 2;  /**< [ 21: 20](R/W) This causes instructions that access the registers associated with
3014                                                                  Floating Point and Advanced SIMD execution to trap to EL2 when executed
3015                                                                  from EL0 or EL2.
3016                                                                  0x0 = This field value causes any instructions that use the registers
3017                                                                       associated with Floating Point and Advanced SIMD execution to be
3018                                                                       trapped in the following cases:
3019                                                                         * When AP_HCR_EL2[TGE] == 0, when the instruction is executed at
3020                                                                           EL0, EL1 or EL2 unless the instruction is trapped to EL1 as
3021                                                                           a result of the AP_CPACR_EL1[FPEN] bit.
3022                                                                         * When AP_HCR_EL2[TGE] == 1, when the instruction is executed at
3023                                                                           EL0 or EL2.
3024 
3025                                                                  0x1 = This field value causes any instructions executed at EL0 that use
3026                                                                       the registerss associated with Floating Point or Advanced SIMD
3027                                                                       execution to be trapped when AP_HCR_EL2[TGE]==1 only.  It does not
3028                                                                       cause any instruction executed at EL1 or EL2 to be trapped and
3029                                                                       it does not cause any instruction to be trapped when AP_HCR_EL2[TGE]==0.
3030 
3031                                                                  0x2 = This field value causes any instructions that use the registers
3032                                                                       associated with Floating Point and Advanced SIMD execution to be
3033                                                                       trapped in the following cases:
3034                                                                         * When AP_HCR_EL2[TGE] == 0, when the instruction is executed at
3035                                                                           EL0, EL1 or EL2 unless the instruction is trapped to EL2 as
3036                                                                           a result of the AP_CPACR_EL1[FPEN] bit.
3037                                                                         * When AP_HCR_EL2[TGE] == 1, when the instruction is executed at
3038                                                                           EL0 or EL2.
3039 
3040                                                                  0x3 = This field value does not cause any instruction to be trapped. */
3041         uint32_t reserved_0_19         : 20;
3042 #else /* Word 0 - Little Endian */
3043         uint32_t reserved_0_19         : 20;
3044         uint32_t fpen                  : 2;  /**< [ 21: 20](R/W) This causes instructions that access the registers associated with
3045                                                                  Floating Point and Advanced SIMD execution to trap to EL2 when executed
3046                                                                  from EL0 or EL2.
3047                                                                  0x0 = This field value causes any instructions that use the registers
3048                                                                       associated with Floating Point and Advanced SIMD execution to be
3049                                                                       trapped in the following cases:
3050                                                                         * When AP_HCR_EL2[TGE] == 0, when the instruction is executed at
3051                                                                           EL0, EL1 or EL2 unless the instruction is trapped to EL1 as
3052                                                                           a result of the AP_CPACR_EL1[FPEN] bit.
3053                                                                         * When AP_HCR_EL2[TGE] == 1, when the instruction is executed at
3054                                                                           EL0 or EL2.
3055 
3056                                                                  0x1 = This field value causes any instructions executed at EL0 that use
3057                                                                       the registerss associated with Floating Point or Advanced SIMD
3058                                                                       execution to be trapped when AP_HCR_EL2[TGE]==1 only.  It does not
3059                                                                       cause any instruction executed at EL1 or EL2 to be trapped and
3060                                                                       it does not cause any instruction to be trapped when AP_HCR_EL2[TGE]==0.
3061 
3062                                                                  0x2 = This field value causes any instructions that use the registers
3063                                                                       associated with Floating Point and Advanced SIMD execution to be
3064                                                                       trapped in the following cases:
3065                                                                         * When AP_HCR_EL2[TGE] == 0, when the instruction is executed at
3066                                                                           EL0, EL1 or EL2 unless the instruction is trapped to EL2 as
3067                                                                           a result of the AP_CPACR_EL1[FPEN] bit.
3068                                                                         * When AP_HCR_EL2[TGE] == 1, when the instruction is executed at
3069                                                                           EL0 or EL2.
3070 
3071                                                                  0x3 = This field value does not cause any instruction to be trapped. */
3072         uint32_t reserved_22_30        : 9;
3073         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to CPACR or AP_CPACR_EL1 from EL1 to
3074                                                                      trap to EL2. When AP_HCR_EL2[TGE] == 0:
3075                                                                  0 = Does not cause access to CPACR or AP_CPACR_EL1 to be trapped.
3076                                                                  1 = Causes access to CPACR or AP_CPACR_EL1 to be trapped.
3077 
3078                                                                  When AP_HCR_EL2[TGE] == 1, this bit is ignored by hardware and
3079                                                                  does not cause access to the AP_CPACR_EL1 to be trapped. */
3080 #endif /* Word 0 - End */
3081     } s;
3082     struct bdk_ap_cptr_el2_e2h_cn
3083     {
3084 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3085         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to CPACR or AP_CPACR_EL1 from EL1 to
3086                                                                      trap to EL2. When AP_HCR_EL2[TGE] == 0:
3087                                                                  0 = Does not cause access to CPACR or AP_CPACR_EL1 to be trapped.
3088                                                                  1 = Causes access to CPACR or AP_CPACR_EL1 to be trapped.
3089 
3090                                                                  When AP_HCR_EL2[TGE] == 1, this bit is ignored by hardware and
3091                                                                  does not cause access to the AP_CPACR_EL1 to be trapped. */
3092         uint32_t reserved_29_30        : 2;
3093         uint32_t reserved_28           : 1;
3094         uint32_t reserved_22_27        : 6;
3095         uint32_t fpen                  : 2;  /**< [ 21: 20](R/W) This causes instructions that access the registers associated with
3096                                                                  Floating Point and Advanced SIMD execution to trap to EL2 when executed
3097                                                                  from EL0 or EL2.
3098                                                                  0x0 = This field value causes any instructions that use the registers
3099                                                                       associated with Floating Point and Advanced SIMD execution to be
3100                                                                       trapped in the following cases:
3101                                                                         * When AP_HCR_EL2[TGE] == 0, when the instruction is executed at
3102                                                                           EL0, EL1 or EL2 unless the instruction is trapped to EL1 as
3103                                                                           a result of the AP_CPACR_EL1[FPEN] bit.
3104                                                                         * When AP_HCR_EL2[TGE] == 1, when the instruction is executed at
3105                                                                           EL0 or EL2.
3106 
3107                                                                  0x1 = This field value causes any instructions executed at EL0 that use
3108                                                                       the registerss associated with Floating Point or Advanced SIMD
3109                                                                       execution to be trapped when AP_HCR_EL2[TGE]==1 only.  It does not
3110                                                                       cause any instruction executed at EL1 or EL2 to be trapped and
3111                                                                       it does not cause any instruction to be trapped when AP_HCR_EL2[TGE]==0.
3112 
3113                                                                  0x2 = This field value causes any instructions that use the registers
3114                                                                       associated with Floating Point and Advanced SIMD execution to be
3115                                                                       trapped in the following cases:
3116                                                                         * When AP_HCR_EL2[TGE] == 0, when the instruction is executed at
3117                                                                           EL0, EL1 or EL2 unless the instruction is trapped to EL2 as
3118                                                                           a result of the AP_CPACR_EL1[FPEN] bit.
3119                                                                         * When AP_HCR_EL2[TGE] == 1, when the instruction is executed at
3120                                                                           EL0 or EL2.
3121 
3122                                                                  0x3 = This field value does not cause any instruction to be trapped. */
3123         uint32_t reserved_0_19         : 20;
3124 #else /* Word 0 - Little Endian */
3125         uint32_t reserved_0_19         : 20;
3126         uint32_t fpen                  : 2;  /**< [ 21: 20](R/W) This causes instructions that access the registers associated with
3127                                                                  Floating Point and Advanced SIMD execution to trap to EL2 when executed
3128                                                                  from EL0 or EL2.
3129                                                                  0x0 = This field value causes any instructions that use the registers
3130                                                                       associated with Floating Point and Advanced SIMD execution to be
3131                                                                       trapped in the following cases:
3132                                                                         * When AP_HCR_EL2[TGE] == 0, when the instruction is executed at
3133                                                                           EL0, EL1 or EL2 unless the instruction is trapped to EL1 as
3134                                                                           a result of the AP_CPACR_EL1[FPEN] bit.
3135                                                                         * When AP_HCR_EL2[TGE] == 1, when the instruction is executed at
3136                                                                           EL0 or EL2.
3137 
3138                                                                  0x1 = This field value causes any instructions executed at EL0 that use
3139                                                                       the registerss associated with Floating Point or Advanced SIMD
3140                                                                       execution to be trapped when AP_HCR_EL2[TGE]==1 only.  It does not
3141                                                                       cause any instruction executed at EL1 or EL2 to be trapped and
3142                                                                       it does not cause any instruction to be trapped when AP_HCR_EL2[TGE]==0.
3143 
3144                                                                  0x2 = This field value causes any instructions that use the registers
3145                                                                       associated with Floating Point and Advanced SIMD execution to be
3146                                                                       trapped in the following cases:
3147                                                                         * When AP_HCR_EL2[TGE] == 0, when the instruction is executed at
3148                                                                           EL0, EL1 or EL2 unless the instruction is trapped to EL2 as
3149                                                                           a result of the AP_CPACR_EL1[FPEN] bit.
3150                                                                         * When AP_HCR_EL2[TGE] == 1, when the instruction is executed at
3151                                                                           EL0 or EL2.
3152 
3153                                                                  0x3 = This field value does not cause any instruction to be trapped. */
3154         uint32_t reserved_22_27        : 6;
3155         uint32_t reserved_28           : 1;
3156         uint32_t reserved_29_30        : 2;
3157         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to CPACR or AP_CPACR_EL1 from EL1 to
3158                                                                      trap to EL2. When AP_HCR_EL2[TGE] == 0:
3159                                                                  0 = Does not cause access to CPACR or AP_CPACR_EL1 to be trapped.
3160                                                                  1 = Causes access to CPACR or AP_CPACR_EL1 to be trapped.
3161 
3162                                                                  When AP_HCR_EL2[TGE] == 1, this bit is ignored by hardware and
3163                                                                  does not cause access to the AP_CPACR_EL1 to be trapped. */
3164 #endif /* Word 0 - End */
3165     } cn;
3166 };
3167 typedef union bdk_ap_cptr_el2_e2h bdk_ap_cptr_el2_e2h_t;
3168 
3169 #define BDK_AP_CPTR_EL2_E2H BDK_AP_CPTR_EL2_E2H_FUNC()
3170 static inline uint64_t BDK_AP_CPTR_EL2_E2H_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CPTR_EL2_E2H_FUNC(void)3171 static inline uint64_t BDK_AP_CPTR_EL2_E2H_FUNC(void)
3172 {
3173     return 0x30401010210ll;
3174 }
3175 
3176 #define typedef_BDK_AP_CPTR_EL2_E2H bdk_ap_cptr_el2_e2h_t
3177 #define bustype_BDK_AP_CPTR_EL2_E2H BDK_CSR_TYPE_SYSREG
3178 #define basename_BDK_AP_CPTR_EL2_E2H "AP_CPTR_EL2_E2H"
3179 #define busnum_BDK_AP_CPTR_EL2_E2H 0
3180 #define arguments_BDK_AP_CPTR_EL2_E2H -1,-1,-1,-1
3181 
3182 /**
3183  * Register (SYSREG) ap_cptr_el3
3184  *
3185  * AP Architectural Feature Trap EL3 Register
3186  * Controls trapping to EL3 of access to AP_CPACR_EL1, Trace
3187  *     functionality and registers associated with Floating Point and
3188  *     Advanced SIMD execution. Also controls EL3 access to this
3189  *     functionality.
3190  */
3191 union bdk_ap_cptr_el3
3192 {
3193     uint32_t u;
3194     struct bdk_ap_cptr_el3_s
3195     {
3196 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3197         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to the AP_CPACR_EL1 from EL1 or the
3198                                                                      AP_CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
3199 
3200                                                                  0 = Does not cause access to the AP_CPACR_EL1 or AP_CPTR_EL2 to be
3201                                                                      trapped.
3202                                                                  1 = Causes access to the AP_CPACR_EL1 or AP_CPTR_EL2 to be trapped. */
3203         uint32_t reserved_11_30        : 20;
3204         uint32_t tfp                   : 1;  /**< [ 10: 10](R/W) This causes instructions that access the registers associated
3205                                                                      with Floating Point and Advanced SIMD execution to trap to EL3
3206                                                                      when executed from any Exception level, unless trapped to EL1
3207                                                                      or EL2.
3208                                                                  0 = Does not cause any instruction to be trapped.
3209                                                                  1 = Causes any instructions that use the registers associated with
3210                                                                      Floating Point and Advanced SIMD execution to be trapped. */
3211         uint32_t reserved_0_9          : 10;
3212 #else /* Word 0 - Little Endian */
3213         uint32_t reserved_0_9          : 10;
3214         uint32_t tfp                   : 1;  /**< [ 10: 10](R/W) This causes instructions that access the registers associated
3215                                                                      with Floating Point and Advanced SIMD execution to trap to EL3
3216                                                                      when executed from any Exception level, unless trapped to EL1
3217                                                                      or EL2.
3218                                                                  0 = Does not cause any instruction to be trapped.
3219                                                                  1 = Causes any instructions that use the registers associated with
3220                                                                      Floating Point and Advanced SIMD execution to be trapped. */
3221         uint32_t reserved_11_30        : 20;
3222         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to the AP_CPACR_EL1 from EL1 or the
3223                                                                      AP_CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
3224 
3225                                                                  0 = Does not cause access to the AP_CPACR_EL1 or AP_CPTR_EL2 to be
3226                                                                      trapped.
3227                                                                  1 = Causes access to the AP_CPACR_EL1 or AP_CPTR_EL2 to be trapped. */
3228 #endif /* Word 0 - End */
3229     } s;
3230     struct bdk_ap_cptr_el3_cn
3231     {
3232 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3233         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to the AP_CPACR_EL1 from EL1 or the
3234                                                                      AP_CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
3235 
3236                                                                  0 = Does not cause access to the AP_CPACR_EL1 or AP_CPTR_EL2 to be
3237                                                                      trapped.
3238                                                                  1 = Causes access to the AP_CPACR_EL1 or AP_CPTR_EL2 to be trapped. */
3239         uint32_t reserved_21_30        : 10;
3240         uint32_t reserved_20           : 1;
3241         uint32_t reserved_11_19        : 9;
3242         uint32_t tfp                   : 1;  /**< [ 10: 10](R/W) This causes instructions that access the registers associated
3243                                                                      with Floating Point and Advanced SIMD execution to trap to EL3
3244                                                                      when executed from any Exception level, unless trapped to EL1
3245                                                                      or EL2.
3246                                                                  0 = Does not cause any instruction to be trapped.
3247                                                                  1 = Causes any instructions that use the registers associated with
3248                                                                      Floating Point and Advanced SIMD execution to be trapped. */
3249         uint32_t reserved_0_9          : 10;
3250 #else /* Word 0 - Little Endian */
3251         uint32_t reserved_0_9          : 10;
3252         uint32_t tfp                   : 1;  /**< [ 10: 10](R/W) This causes instructions that access the registers associated
3253                                                                      with Floating Point and Advanced SIMD execution to trap to EL3
3254                                                                      when executed from any Exception level, unless trapped to EL1
3255                                                                      or EL2.
3256                                                                  0 = Does not cause any instruction to be trapped.
3257                                                                  1 = Causes any instructions that use the registers associated with
3258                                                                      Floating Point and Advanced SIMD execution to be trapped. */
3259         uint32_t reserved_11_19        : 9;
3260         uint32_t reserved_20           : 1;
3261         uint32_t reserved_21_30        : 10;
3262         uint32_t tcpac                 : 1;  /**< [ 31: 31](R/W) This causes a direct access to the AP_CPACR_EL1 from EL1 or the
3263                                                                      AP_CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
3264 
3265                                                                  0 = Does not cause access to the AP_CPACR_EL1 or AP_CPTR_EL2 to be
3266                                                                      trapped.
3267                                                                  1 = Causes access to the AP_CPACR_EL1 or AP_CPTR_EL2 to be trapped. */
3268 #endif /* Word 0 - End */
3269     } cn;
3270 };
3271 typedef union bdk_ap_cptr_el3 bdk_ap_cptr_el3_t;
3272 
3273 #define BDK_AP_CPTR_EL3 BDK_AP_CPTR_EL3_FUNC()
3274 static inline uint64_t BDK_AP_CPTR_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CPTR_EL3_FUNC(void)3275 static inline uint64_t BDK_AP_CPTR_EL3_FUNC(void)
3276 {
3277     return 0x30601010200ll;
3278 }
3279 
3280 #define typedef_BDK_AP_CPTR_EL3 bdk_ap_cptr_el3_t
3281 #define bustype_BDK_AP_CPTR_EL3 BDK_CSR_TYPE_SYSREG
3282 #define basename_BDK_AP_CPTR_EL3 "AP_CPTR_EL3"
3283 #define busnum_BDK_AP_CPTR_EL3 0
3284 #define arguments_BDK_AP_CPTR_EL3 -1,-1,-1,-1
3285 
3286 /**
3287  * Register (SYSREG) ap_csselr_el1
3288  *
3289  * AP Cache Size Selection Register
3290  * Selects the current Cache Size ID Register, AP_CCSIDR_EL1, by
3291  *     specifying the required cache level and the cache type (either
3292  *     instruction or data cache).
3293  */
3294 union bdk_ap_csselr_el1
3295 {
3296     uint32_t u;
3297     struct bdk_ap_csselr_el1_s
3298     {
3299 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3300         uint32_t reserved_4_31         : 28;
3301         uint32_t level                 : 3;  /**< [  3:  1](R/W) Cache level of required cache. */
3302         uint32_t ind                   : 1;  /**< [  0:  0](R/W) Instruction not Data bit.
3303                                                                  0 = Data or unified cache.
3304                                                                  1 = Instruction cache. */
3305 #else /* Word 0 - Little Endian */
3306         uint32_t ind                   : 1;  /**< [  0:  0](R/W) Instruction not Data bit.
3307                                                                  0 = Data or unified cache.
3308                                                                  1 = Instruction cache. */
3309         uint32_t level                 : 3;  /**< [  3:  1](R/W) Cache level of required cache. */
3310         uint32_t reserved_4_31         : 28;
3311 #endif /* Word 0 - End */
3312     } s;
3313     /* struct bdk_ap_csselr_el1_s cn; */
3314 };
3315 typedef union bdk_ap_csselr_el1 bdk_ap_csselr_el1_t;
3316 
3317 #define BDK_AP_CSSELR_EL1 BDK_AP_CSSELR_EL1_FUNC()
3318 static inline uint64_t BDK_AP_CSSELR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CSSELR_EL1_FUNC(void)3319 static inline uint64_t BDK_AP_CSSELR_EL1_FUNC(void)
3320 {
3321     return 0x30200000000ll;
3322 }
3323 
3324 #define typedef_BDK_AP_CSSELR_EL1 bdk_ap_csselr_el1_t
3325 #define bustype_BDK_AP_CSSELR_EL1 BDK_CSR_TYPE_SYSREG
3326 #define basename_BDK_AP_CSSELR_EL1 "AP_CSSELR_EL1"
3327 #define busnum_BDK_AP_CSSELR_EL1 0
3328 #define arguments_BDK_AP_CSSELR_EL1 -1,-1,-1,-1
3329 
3330 /**
3331  * Register (SYSREG) ap_ctr_el0
3332  *
3333  * AP Cache Type Register
3334  * This register provides information about the architecture of the caches.
3335  */
3336 union bdk_ap_ctr_el0
3337 {
3338     uint32_t u;
3339     struct bdk_ap_ctr_el0_s
3340     {
3341 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3342         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
3343         uint32_t reserved_28_30        : 3;
3344         uint32_t cwg                   : 4;  /**< [ 27: 24](RO) Cache writeback granule. Log2 of the number of
3345                                                                      words of the maximum size of memory that can be overwritten as
3346                                                                      a result of the eviction of a cache entry that has had a
3347                                                                      memory location in it modified.
3348 
3349                                                                   The architectural maximum of 512 words (2KB) must be assumed.
3350 
3351                                                                   The cache writeback granule can be determined from maximum
3352                                                                      cache line size encoded in the Cache Size ID Registers. */
3353         uint32_t erg                   : 4;  /**< [ 23: 20](RO) Exclusives reservation granule. Log2 of the number
3354                                                                      of words of the maximum size of the reservation granule that
3355                                                                      has been implemented for the Load-Exclusive and
3356                                                                      Store-Exclusive instructions. */
3357         uint32_t dminline              : 4;  /**< [ 19: 16](RO) Log2 of the number of words in the smallest cache
3358                                                                      line of all the data caches and unified caches that are
3359                                                                      controlled by the PE.
3360 
3361                                                                  For CNXXXX, 128 bytes. */
3362         uint32_t l1ip                  : 2;  /**< [ 15: 14](RO) Level 1 instruction cache policy. Indicates the indexing and
3363                                                                      tagging policy for the L1 instruction cache.
3364 
3365                                                                  0x1 = ASID-tagged virtual index, virtual tag (AIVIVT).
3366                                                                  0x2 = Virtual index, physical tag (VIPT).
3367                                                                  0x3 = Physical index, physical tag (PIPT). */
3368         uint32_t reserved_4_13         : 10;
3369         uint32_t iminline              : 4;  /**< [  3:  0](RO) Log2 of the number of words in the smallest cache line of all the instruction
3370                                                                  caches that are controlled by the PE.
3371 
3372                                                                  For CNXXXX, 128 bytes. */
3373 #else /* Word 0 - Little Endian */
3374         uint32_t iminline              : 4;  /**< [  3:  0](RO) Log2 of the number of words in the smallest cache line of all the instruction
3375                                                                  caches that are controlled by the PE.
3376 
3377                                                                  For CNXXXX, 128 bytes. */
3378         uint32_t reserved_4_13         : 10;
3379         uint32_t l1ip                  : 2;  /**< [ 15: 14](RO) Level 1 instruction cache policy. Indicates the indexing and
3380                                                                      tagging policy for the L1 instruction cache.
3381 
3382                                                                  0x1 = ASID-tagged virtual index, virtual tag (AIVIVT).
3383                                                                  0x2 = Virtual index, physical tag (VIPT).
3384                                                                  0x3 = Physical index, physical tag (PIPT). */
3385         uint32_t dminline              : 4;  /**< [ 19: 16](RO) Log2 of the number of words in the smallest cache
3386                                                                      line of all the data caches and unified caches that are
3387                                                                      controlled by the PE.
3388 
3389                                                                  For CNXXXX, 128 bytes. */
3390         uint32_t erg                   : 4;  /**< [ 23: 20](RO) Exclusives reservation granule. Log2 of the number
3391                                                                      of words of the maximum size of the reservation granule that
3392                                                                      has been implemented for the Load-Exclusive and
3393                                                                      Store-Exclusive instructions. */
3394         uint32_t cwg                   : 4;  /**< [ 27: 24](RO) Cache writeback granule. Log2 of the number of
3395                                                                      words of the maximum size of memory that can be overwritten as
3396                                                                      a result of the eviction of a cache entry that has had a
3397                                                                      memory location in it modified.
3398 
3399                                                                   The architectural maximum of 512 words (2KB) must be assumed.
3400 
3401                                                                   The cache writeback granule can be determined from maximum
3402                                                                      cache line size encoded in the Cache Size ID Registers. */
3403         uint32_t reserved_28_30        : 3;
3404         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
3405 #endif /* Word 0 - End */
3406     } s;
3407     /* struct bdk_ap_ctr_el0_s cn; */
3408 };
3409 typedef union bdk_ap_ctr_el0 bdk_ap_ctr_el0_t;
3410 
3411 #define BDK_AP_CTR_EL0 BDK_AP_CTR_EL0_FUNC()
3412 static inline uint64_t BDK_AP_CTR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CTR_EL0_FUNC(void)3413 static inline uint64_t BDK_AP_CTR_EL0_FUNC(void)
3414 {
3415     return 0x30300000100ll;
3416 }
3417 
3418 #define typedef_BDK_AP_CTR_EL0 bdk_ap_ctr_el0_t
3419 #define bustype_BDK_AP_CTR_EL0 BDK_CSR_TYPE_SYSREG
3420 #define basename_BDK_AP_CTR_EL0 "AP_CTR_EL0"
3421 #define busnum_BDK_AP_CTR_EL0 0
3422 #define arguments_BDK_AP_CTR_EL0 -1,-1,-1,-1
3423 
3424 /**
3425  * Register (SYSREG) ap_currentel
3426  *
3427  * AP Current Exception Level Register
3428  * Holds the current Exception level.
3429  */
3430 union bdk_ap_currentel
3431 {
3432     uint32_t u;
3433     struct bdk_ap_currentel_s
3434     {
3435 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3436         uint32_t reserved_4_31         : 28;
3437         uint32_t el                    : 2;  /**< [  3:  2](RO) Current Exception level.
3438                                                                  0x0 = EL0.
3439                                                                  0x1 = EL1.
3440                                                                  0x2 = EL2.
3441                                                                  0x3 = EL3. */
3442         uint32_t reserved_0_1          : 2;
3443 #else /* Word 0 - Little Endian */
3444         uint32_t reserved_0_1          : 2;
3445         uint32_t el                    : 2;  /**< [  3:  2](RO) Current Exception level.
3446                                                                  0x0 = EL0.
3447                                                                  0x1 = EL1.
3448                                                                  0x2 = EL2.
3449                                                                  0x3 = EL3. */
3450         uint32_t reserved_4_31         : 28;
3451 #endif /* Word 0 - End */
3452     } s;
3453     /* struct bdk_ap_currentel_s cn; */
3454 };
3455 typedef union bdk_ap_currentel bdk_ap_currentel_t;
3456 
3457 #define BDK_AP_CURRENTEL BDK_AP_CURRENTEL_FUNC()
3458 static inline uint64_t BDK_AP_CURRENTEL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CURRENTEL_FUNC(void)3459 static inline uint64_t BDK_AP_CURRENTEL_FUNC(void)
3460 {
3461     return 0x30004020200ll;
3462 }
3463 
3464 #define typedef_BDK_AP_CURRENTEL bdk_ap_currentel_t
3465 #define bustype_BDK_AP_CURRENTEL BDK_CSR_TYPE_SYSREG
3466 #define basename_BDK_AP_CURRENTEL "AP_CURRENTEL"
3467 #define busnum_BDK_AP_CURRENTEL 0
3468 #define arguments_BDK_AP_CURRENTEL -1,-1,-1,-1
3469 
3470 /**
3471  * Register (SYSREG) ap_cvm_access_el1
3472  *
3473  * AP Cavium Access EL1 Register
3474  * This register controls trapping on register accesses.
3475  *
3476  * Read/write access at EL1, EL2 and EL3.
3477  *
3478  * Note that AP_HCR_EL2[TIDCP] can also prevent all CVM* access at EL1
3479  * and below and takes priority over AP_CVM_ACCESS_EL1.
3480  *
3481  * Note that AP_CVM_ACCESS_EL1 can grant access to EL0 for AP_CVM_*_EL1
3482  * registers. This is non standard. A some point AP_CVM_ACCESS_EL1 may be
3483  * depreciated.
3484  *
3485  * A 1 in the appropriate bit in the AP_CVM_ACCESS_ELn register prevents
3486  * any access at lower exception levels.
3487  *
3488  * Internal:
3489  * If access is denied at multiple exception levels then the
3490  * trap occurs at the lowest. This is similar to ARM's
3491  * AP_CPACR_EL1/AP_CPTR_EL2/AP_CPTR_EL3.
3492  */
3493 union bdk_ap_cvm_access_el1
3494 {
3495     uint64_t u;
3496     struct bdk_ap_cvm_access_el1_s
3497     {
3498 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3499         uint64_t reserved_9_63         : 55;
3500         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 1 traps to EL1 unless
3501                                                                  AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3502         uint64_t cvm_pn                : 1;  /**< [  7:  7](R/W) A read or write operation to AP_CVM_PN_EL1 with the exception level lower than 1
3503                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3504         uint64_t cvm_statprof          : 1;  /**< [  6:  6](R/W) A read or write operation to AP_CVM_STATPROFCTL_EL1 or AP_CVM_STATPROFCMP_EL1
3505                                                                  with the exception level lower than 1 traps to EL1 unless
3506                                                                  AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3507         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read operation to AP_CVM_EVATTID with the exception level lower than 1 traps
3508                                                                  to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3509         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_Icache* or AP_CVM_Dcache* with the exception
3510                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then
3511                                                                  EL2. */
3512         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 1
3513                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3514         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 1
3515                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3516         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 1
3517                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3518         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3519                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then
3520                                                                  EL2. */
3521 #else /* Word 0 - Little Endian */
3522         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3523                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then
3524                                                                  EL2. */
3525         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 1
3526                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3527         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 1
3528                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3529         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 1
3530                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3531         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_Icache* or AP_CVM_Dcache* with the exception
3532                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then
3533                                                                  EL2. */
3534         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read operation to AP_CVM_EVATTID with the exception level lower than 1 traps
3535                                                                  to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3536         uint64_t cvm_statprof          : 1;  /**< [  6:  6](R/W) A read or write operation to AP_CVM_STATPROFCTL_EL1 or AP_CVM_STATPROFCMP_EL1
3537                                                                  with the exception level lower than 1 traps to EL1 unless
3538                                                                  AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3539         uint64_t cvm_pn                : 1;  /**< [  7:  7](R/W) A read or write operation to AP_CVM_PN_EL1 with the exception level lower than 1
3540                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3541         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 1 traps to EL1 unless
3542                                                                  AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3543         uint64_t reserved_9_63         : 55;
3544 #endif /* Word 0 - End */
3545     } s;
3546     struct bdk_ap_cvm_access_el1_cn8
3547     {
3548 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3549         uint64_t reserved_9_63         : 55;
3550         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 1 traps to EL1 unless
3551                                                                  AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3552         uint64_t reserved_6_7          : 2;
3553         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read operation to AP_CVM_EVATTID with the exception level lower than 1 traps
3554                                                                  to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3555         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_Icache* or AP_CVM_Dcache* with the exception
3556                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then
3557                                                                  EL2. */
3558         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 1
3559                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3560         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 1
3561                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3562         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 1
3563                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3564         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3565                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then
3566                                                                  EL2. */
3567 #else /* Word 0 - Little Endian */
3568         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3569                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then
3570                                                                  EL2. */
3571         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 1
3572                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3573         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 1
3574                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3575         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 1
3576                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3577         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_Icache* or AP_CVM_Dcache* with the exception
3578                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then
3579                                                                  EL2. */
3580         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read operation to AP_CVM_EVATTID with the exception level lower than 1 traps
3581                                                                  to EL1 unless AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3582         uint64_t reserved_6_7          : 2;
3583         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 1 traps to EL1 unless
3584                                                                  AP_HCR_EL2[TGE] && !AP_SCR_EL3[NS], then EL2. */
3585         uint64_t reserved_9_63         : 55;
3586 #endif /* Word 0 - End */
3587     } cn8;
3588     struct bdk_ap_cvm_access_el1_cn9
3589     {
3590 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3591         uint64_t reserved_9_63         : 55;
3592         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 1 traps to EL1 unless
3593                                                                  AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3594         uint64_t cvm_pn                : 1;  /**< [  7:  7](R/W) A read or write operation to AP_CVM_PN_EL1 with the exception level lower than 1
3595                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3596         uint64_t cvm_statprof          : 1;  /**< [  6:  6](R/W) A read or write operation to AP_CVM_STATPROFCTL_EL1 or AP_CVM_STATPROFCMP_EL1
3597                                                                  with the exception level lower than 1 traps to EL1 unless
3598                                                                  AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3599         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read operation to AP_CVM_EVATTID with the exception level lower than 1 traps
3600                                                                  to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3601         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_Icache* or AP_CVM_Dcache* with the exception
3602                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then
3603                                                                  EL2. */
3604         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 1
3605                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3606         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 1
3607                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3608         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 1
3609                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3610         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3611                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then
3612                                                                  EL2. */
3613 #else /* Word 0 - Little Endian */
3614         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3615                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then
3616                                                                  EL2. */
3617         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 1
3618                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3619         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 1
3620                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3621         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 1
3622                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3623         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_Icache* or AP_CVM_Dcache* with the exception
3624                                                                  level lower than 1 traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then
3625                                                                  EL2. */
3626         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read operation to AP_CVM_EVATTID with the exception level lower than 1 traps
3627                                                                  to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3628         uint64_t cvm_statprof          : 1;  /**< [  6:  6](R/W) A read or write operation to AP_CVM_STATPROFCTL_EL1 or AP_CVM_STATPROFCMP_EL1
3629                                                                  with the exception level lower than 1 traps to EL1 unless
3630                                                                  AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3631         uint64_t cvm_pn                : 1;  /**< [  7:  7](R/W) A read or write operation to AP_CVM_PN_EL1 with the exception level lower than 1
3632                                                                  traps to EL1 unless AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3633         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 1 traps to EL1 unless
3634                                                                  AP_HCR_EL2[TGE] && AP_SCR_EL3[NS], then EL2. */
3635         uint64_t reserved_9_63         : 55;
3636 #endif /* Word 0 - End */
3637     } cn9;
3638 };
3639 typedef union bdk_ap_cvm_access_el1 bdk_ap_cvm_access_el1_t;
3640 
3641 #define BDK_AP_CVM_ACCESS_EL1 BDK_AP_CVM_ACCESS_EL1_FUNC()
3642 static inline uint64_t BDK_AP_CVM_ACCESS_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_ACCESS_EL1_FUNC(void)3643 static inline uint64_t BDK_AP_CVM_ACCESS_EL1_FUNC(void)
3644 {
3645     return 0x3000b000300ll;
3646 }
3647 
3648 #define typedef_BDK_AP_CVM_ACCESS_EL1 bdk_ap_cvm_access_el1_t
3649 #define bustype_BDK_AP_CVM_ACCESS_EL1 BDK_CSR_TYPE_SYSREG
3650 #define basename_BDK_AP_CVM_ACCESS_EL1 "AP_CVM_ACCESS_EL1"
3651 #define busnum_BDK_AP_CVM_ACCESS_EL1 0
3652 #define arguments_BDK_AP_CVM_ACCESS_EL1 -1,-1,-1,-1
3653 
3654 /**
3655  * Register (SYSREG) ap_cvm_access_el2
3656  *
3657  * AP Cavium Access EL2 Register
3658  * This register controls trap/access of Cavium registers. Read/write access at EL2 and EL3.
3659  */
3660 union bdk_ap_cvm_access_el2
3661 {
3662     uint64_t u;
3663     struct bdk_ap_cvm_access_el2_s
3664     {
3665 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3666         uint64_t reserved_9_63         : 55;
3667         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 2 traps to EL2 unless
3668                                                                  prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3669         uint64_t cvm_pn                : 1;  /**< [  7:  7](R/W) A read or write operation to AP_CVM_PN_EL1 with the exception level lower than 2
3670                                                                  traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3671         uint64_t cvm_statprof          : 1;  /**< [  6:  6](R/W) A read or write operation to AP_CVM_STATPROFCTL_EL1 or AP_CVM_STATPROFCMP_EL1
3672                                                                  with the exception level lower than 2 traps to EL2 unless prohibited by
3673                                                                  AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3674         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read operation to AP_CVM_EVATTID with the exception level lower than 2 traps
3675                                                                  to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3676         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_ICACHE* or AP_CVM_DCACHE* with the exception
3677                                                                  level lower than 2 traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or
3678                                                                  AP_SCR_EL3[NS] = 0. */
3679         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 2
3680                                                                  traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3681         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 2
3682                                                                  traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3683         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 2 traps to
3684                                                                  EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3685         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3686                                                                  level lower than 2 traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or
3687                                                                  AP_SCR_EL3[NS] = 0. */
3688 #else /* Word 0 - Little Endian */
3689         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3690                                                                  level lower than 2 traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or
3691                                                                  AP_SCR_EL3[NS] = 0. */
3692         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 2 traps to
3693                                                                  EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3694         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 2
3695                                                                  traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3696         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 2
3697                                                                  traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3698         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_ICACHE* or AP_CVM_DCACHE* with the exception
3699                                                                  level lower than 2 traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or
3700                                                                  AP_SCR_EL3[NS] = 0. */
3701         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read operation to AP_CVM_EVATTID with the exception level lower than 2 traps
3702                                                                  to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3703         uint64_t cvm_statprof          : 1;  /**< [  6:  6](R/W) A read or write operation to AP_CVM_STATPROFCTL_EL1 or AP_CVM_STATPROFCMP_EL1
3704                                                                  with the exception level lower than 2 traps to EL2 unless prohibited by
3705                                                                  AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3706         uint64_t cvm_pn                : 1;  /**< [  7:  7](R/W) A read or write operation to AP_CVM_PN_EL1 with the exception level lower than 2
3707                                                                  traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3708         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 2 traps to EL2 unless
3709                                                                  prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3710         uint64_t reserved_9_63         : 55;
3711 #endif /* Word 0 - End */
3712     } s;
3713     struct bdk_ap_cvm_access_el2_cn8
3714     {
3715 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3716         uint64_t reserved_9_63         : 55;
3717         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 2 traps to EL2 unless
3718                                                                  prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3719         uint64_t reserved_6_7          : 2;
3720         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read operation to AP_CVM_EVATTID with the exception level lower than 2 traps
3721                                                                  to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3722         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_ICACHE* or AP_CVM_DCACHE* with the exception
3723                                                                  level lower than 2 traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or
3724                                                                  AP_SCR_EL3[NS] = 0. */
3725         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 2
3726                                                                  traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3727         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 2
3728                                                                  traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3729         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 2 traps to
3730                                                                  EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3731         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3732                                                                  level lower than 2 traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or
3733                                                                  AP_SCR_EL3[NS] = 0. */
3734 #else /* Word 0 - Little Endian */
3735         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3736                                                                  level lower than 2 traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or
3737                                                                  AP_SCR_EL3[NS] = 0. */
3738         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 2 traps to
3739                                                                  EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3740         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 2
3741                                                                  traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3742         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 2
3743                                                                  traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3744         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_ICACHE* or AP_CVM_DCACHE* with the exception
3745                                                                  level lower than 2 traps to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or
3746                                                                  AP_SCR_EL3[NS] = 0. */
3747         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read operation to AP_CVM_EVATTID with the exception level lower than 2 traps
3748                                                                  to EL2 unless prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3749         uint64_t reserved_6_7          : 2;
3750         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 2 traps to EL2 unless
3751                                                                  prohibited by AP_CVM_ACCESS_EL1 or AP_SCR_EL3[NS] = 0. */
3752         uint64_t reserved_9_63         : 55;
3753 #endif /* Word 0 - End */
3754     } cn8;
3755     /* struct bdk_ap_cvm_access_el2_s cn9; */
3756 };
3757 typedef union bdk_ap_cvm_access_el2 bdk_ap_cvm_access_el2_t;
3758 
3759 #define BDK_AP_CVM_ACCESS_EL2 BDK_AP_CVM_ACCESS_EL2_FUNC()
3760 static inline uint64_t BDK_AP_CVM_ACCESS_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_ACCESS_EL2_FUNC(void)3761 static inline uint64_t BDK_AP_CVM_ACCESS_EL2_FUNC(void)
3762 {
3763     return 0x3040b000300ll;
3764 }
3765 
3766 #define typedef_BDK_AP_CVM_ACCESS_EL2 bdk_ap_cvm_access_el2_t
3767 #define bustype_BDK_AP_CVM_ACCESS_EL2 BDK_CSR_TYPE_SYSREG
3768 #define basename_BDK_AP_CVM_ACCESS_EL2 "AP_CVM_ACCESS_EL2"
3769 #define busnum_BDK_AP_CVM_ACCESS_EL2 0
3770 #define arguments_BDK_AP_CVM_ACCESS_EL2 -1,-1,-1,-1
3771 
3772 /**
3773  * Register (SYSREG) ap_cvm_access_el3
3774  *
3775  * AP Cavium Access EL3 Register
3776  * Internal:
3777  * Software should expose the CvmCACHE instruction to EL2 or
3778  * EL1 with extreme caution. Exposing this instruction to lower
3779  * exception levels may cause nonsecure state to mess with secure
3780  * state, which would cause a security hole.
3781  */
3782 union bdk_ap_cvm_access_el3
3783 {
3784     uint64_t u;
3785     struct bdk_ap_cvm_access_el3_s
3786     {
3787 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3788         uint64_t reserved_9_63         : 55;
3789         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 3 traps to EL3. */
3790         uint64_t cvm_pn                : 1;  /**< [  7:  7](R/W) A read or write operation to AP_CVM_PN_EL1 with the exception level lower than 3
3791                                                                  traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3792                                                                  AP_HCR_EL2[TIDCP]. */
3793         uint64_t cvm_statprof          : 1;  /**< [  6:  6](R/W) A read or write operation to AP_CVM_STATPROFCTL_EL1 or AP_CVM_STATPROFCMP_EL1
3794                                                                  with the exception level lower than 3 traps to EL3 unless prohibited by
3795                                                                  AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3796         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read or write operation to AP_CVM_EVATTID with the exception level lower than 3 traps to
3797                                                                  EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3798         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_ICACHE* or AP_CVM_DCACHE* with the exception level
3799                                                                  lower
3800                                                                  than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3801                                                                  AP_HCR_EL2[TIDCP]. */
3802         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 3 traps to
3803                                                                  EL3
3804                                                                  unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3805         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 3 traps to
3806                                                                  EL3
3807                                                                  unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3808         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 3 traps to
3809                                                                  EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3810         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3811                                                                  level lower than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2,
3812                                                                  AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3813 #else /* Word 0 - Little Endian */
3814         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3815                                                                  level lower than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2,
3816                                                                  AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3817         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 3 traps to
3818                                                                  EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3819         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 3 traps to
3820                                                                  EL3
3821                                                                  unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3822         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 3 traps to
3823                                                                  EL3
3824                                                                  unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3825         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_ICACHE* or AP_CVM_DCACHE* with the exception level
3826                                                                  lower
3827                                                                  than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3828                                                                  AP_HCR_EL2[TIDCP]. */
3829         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read or write operation to AP_CVM_EVATTID with the exception level lower than 3 traps to
3830                                                                  EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3831         uint64_t cvm_statprof          : 1;  /**< [  6:  6](R/W) A read or write operation to AP_CVM_STATPROFCTL_EL1 or AP_CVM_STATPROFCMP_EL1
3832                                                                  with the exception level lower than 3 traps to EL3 unless prohibited by
3833                                                                  AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3834         uint64_t cvm_pn                : 1;  /**< [  7:  7](R/W) A read or write operation to AP_CVM_PN_EL1 with the exception level lower than 3
3835                                                                  traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3836                                                                  AP_HCR_EL2[TIDCP]. */
3837         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 3 traps to EL3. */
3838         uint64_t reserved_9_63         : 55;
3839 #endif /* Word 0 - End */
3840     } s;
3841     struct bdk_ap_cvm_access_el3_cn8
3842     {
3843 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3844         uint64_t reserved_9_63         : 55;
3845         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 3 traps to EL3. */
3846         uint64_t reserved_6_7          : 2;
3847         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read or write operation to AP_CVM_EVATTID with the exception level lower than 3 traps to
3848                                                                  EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3849         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_ICACHE* or AP_CVM_DCACHE* with the exception level
3850                                                                  lower
3851                                                                  than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3852                                                                  AP_HCR_EL2[TIDCP]. */
3853         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 3 traps to
3854                                                                  EL3
3855                                                                  unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3856         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 3 traps to
3857                                                                  EL3
3858                                                                  unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3859         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 3 traps to
3860                                                                  EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3861         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3862                                                                  level lower than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2,
3863                                                                  AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3864 #else /* Word 0 - Little Endian */
3865         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3866                                                                  level lower than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2,
3867                                                                  AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3868         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 3 traps to
3869                                                                  EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3870         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 3 traps to
3871                                                                  EL3
3872                                                                  unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3873         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 3 traps to
3874                                                                  EL3
3875                                                                  unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3876         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_ICACHE* or AP_CVM_DCACHE* with the exception level
3877                                                                  lower
3878                                                                  than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3879                                                                  AP_HCR_EL2[TIDCP]. */
3880         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read or write operation to AP_CVM_EVATTID with the exception level lower than 3 traps to
3881                                                                  EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3882         uint64_t reserved_6_7          : 2;
3883         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 3 traps to EL3. */
3884         uint64_t reserved_9_63         : 55;
3885 #endif /* Word 0 - End */
3886     } cn8;
3887     struct bdk_ap_cvm_access_el3_cn9
3888     {
3889 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3890         uint64_t reserved_9_63         : 55;
3891         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 3 traps to EL3. */
3892         uint64_t cvm_pn                : 1;  /**< [  7:  7](R/W) A read or write operation to AP_CVM_PN_EL1 with the exception level lower than 3
3893                                                                  traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3894                                                                  AP_HCR_EL2[TIDCP]. */
3895         uint64_t cvm_statprof          : 1;  /**< [  6:  6](R/W) A read or write operation to AP_CVM_STATPROFCTL_EL1 or AP_CVM_STATPROFCMP_EL1
3896                                                                  with the exception level lower than 3 traps to EL3 unless prohibited by
3897                                                                  AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3898         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read or write operation to AP_CVM_EVATTID with the exception level lower than
3899                                                                  3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3900                                                                  AP_HCR_EL2[TIDCP]. */
3901         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_ICACHE* or AP_CVM_DCACHE* with the exception
3902                                                                  level lower than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2,
3903                                                                  AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3904         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 3
3905                                                                  traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3906                                                                  AP_HCR_EL2[TIDCP]. */
3907         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 3
3908                                                                  traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3909                                                                  AP_HCR_EL2[TIDCP]. */
3910         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 3
3911                                                                  traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3912                                                                  AP_HCR_EL2[TIDCP]. */
3913         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3914                                                                  level lower than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2,
3915                                                                  AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3916 #else /* Word 0 - Little Endian */
3917         uint64_t cvm_ctl               : 1;  /**< [  0:  0](R/W) A read or write operation to AP_CVM_CTL or AP_CVM_MEMCTL with the exception
3918                                                                  level lower than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2,
3919                                                                  AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3920         uint64_t powthrottle           : 1;  /**< [  1:  1](R/W) A read or write operation to PowThrottle with the exception level lower than 3
3921                                                                  traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3922                                                                  AP_HCR_EL2[TIDCP]. */
3923         uint64_t cvm_bist              : 1;  /**< [  2:  2](R/W) A read or write operation to AP_CVM_BIST* with the exception level lower than 3
3924                                                                  traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3925                                                                  AP_HCR_EL2[TIDCP]. */
3926         uint64_t cvm_err               : 1;  /**< [  3:  3](R/W) A read or write operation to AP_CVM_ERR* with the exception level lower than 3
3927                                                                  traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3928                                                                  AP_HCR_EL2[TIDCP]. */
3929         uint64_t cvm_i_d_cache         : 1;  /**< [  4:  4](R/W) A read or write operation to AP_CVM_ICACHE* or AP_CVM_DCACHE* with the exception
3930                                                                  level lower than 3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2,
3931                                                                  AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3932         uint64_t cvm_evattid           : 1;  /**< [  5:  5](R/W) A read or write operation to AP_CVM_EVATTID with the exception level lower than
3933                                                                  3 traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3934                                                                  AP_HCR_EL2[TIDCP]. */
3935         uint64_t cvm_statprof          : 1;  /**< [  6:  6](R/W) A read or write operation to AP_CVM_STATPROFCTL_EL1 or AP_CVM_STATPROFCMP_EL1
3936                                                                  with the exception level lower than 3 traps to EL3 unless prohibited by
3937                                                                  AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or AP_HCR_EL2[TIDCP]. */
3938         uint64_t cvm_pn                : 1;  /**< [  7:  7](R/W) A read or write operation to AP_CVM_PN_EL1 with the exception level lower than 3
3939                                                                  traps to EL3 unless prohibited by AP_CVM_ACCESS_EL2, AP_CVM_ACCESS_EL1, or
3940                                                                  AP_HCR_EL2[TIDCP]. */
3941         uint64_t cvm_cache             : 1;  /**< [  8:  8](R/W) A Cvm_Cache instruction with the exception level lower than 3 traps to EL3. */
3942         uint64_t reserved_9_63         : 55;
3943 #endif /* Word 0 - End */
3944     } cn9;
3945 };
3946 typedef union bdk_ap_cvm_access_el3 bdk_ap_cvm_access_el3_t;
3947 
3948 #define BDK_AP_CVM_ACCESS_EL3 BDK_AP_CVM_ACCESS_EL3_FUNC()
3949 static inline uint64_t BDK_AP_CVM_ACCESS_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_ACCESS_EL3_FUNC(void)3950 static inline uint64_t BDK_AP_CVM_ACCESS_EL3_FUNC(void)
3951 {
3952     return 0x3060b000300ll;
3953 }
3954 
3955 #define typedef_BDK_AP_CVM_ACCESS_EL3 bdk_ap_cvm_access_el3_t
3956 #define bustype_BDK_AP_CVM_ACCESS_EL3 BDK_CSR_TYPE_SYSREG
3957 #define basename_BDK_AP_CVM_ACCESS_EL3 "AP_CVM_ACCESS_EL3"
3958 #define busnum_BDK_AP_CVM_ACCESS_EL3 0
3959 #define arguments_BDK_AP_CVM_ACCESS_EL3 -1,-1,-1,-1
3960 
3961 /**
3962  * Register (SYSREG) ap_cvm_bist0_el1
3963  *
3964  * AP Cavium BIST0 Register
3965  * This register indicates BIST status, where a 1 in a bit position indicates defective.
3966  */
3967 union bdk_ap_cvm_bist0_el1
3968 {
3969     uint64_t u;
3970     struct bdk_ap_cvm_bist0_el1_s
3971     {
3972 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3973         uint64_t reserved_35_63        : 29;
3974         uint64_t fuse_controller_reports_hard_repair : 1;/**< [ 34: 34](RO) Fuse controller reports hard repair. */
3975         uint64_t clear_bist_was_run    : 1;  /**< [ 33: 33](RO) Clear BIST was run. */
3976         uint64_t manufacturing_mode    : 1;  /**< [ 32: 32](RO) Manufacturing mode. */
3977         uint64_t icache_data_banks_with_unrepairable_defects : 8;/**< [ 31: 24](RO) Icache data banks with unrepairable defects. */
3978         uint64_t icache_data_banks_with_defects : 8;/**< [ 23: 16](RO) Icache data banks with defects. */
3979         uint64_t reserved_8_15         : 8;
3980         uint64_t aes_roms_defective    : 1;  /**< [  7:  7](RO) AES ROMs defective. */
3981         uint64_t fpu_roms_defective    : 1;  /**< [  6:  6](RO) FPU ROMs defective. */
3982         uint64_t fpu_rf_defective      : 1;  /**< [  5:  5](RO) FPU/SIMD RF defective. */
3983         uint64_t integer_rf_defective  : 1;  /**< [  4:  4](RO) Integer RF defective. */
3984         uint64_t jrt_defective         : 1;  /**< [  3:  3](RO) JRT defective. */
3985         uint64_t bht_defective         : 1;  /**< [  2:  2](RO) BHT defective. */
3986         uint64_t icache_tag_defective  : 1;  /**< [  1:  1](RO) Icache tag defective. */
3987         uint64_t icache_data_defective : 1;  /**< [  0:  0](RO) Icache data defective/unrepairable. */
3988 #else /* Word 0 - Little Endian */
3989         uint64_t icache_data_defective : 1;  /**< [  0:  0](RO) Icache data defective/unrepairable. */
3990         uint64_t icache_tag_defective  : 1;  /**< [  1:  1](RO) Icache tag defective. */
3991         uint64_t bht_defective         : 1;  /**< [  2:  2](RO) BHT defective. */
3992         uint64_t jrt_defective         : 1;  /**< [  3:  3](RO) JRT defective. */
3993         uint64_t integer_rf_defective  : 1;  /**< [  4:  4](RO) Integer RF defective. */
3994         uint64_t fpu_rf_defective      : 1;  /**< [  5:  5](RO) FPU/SIMD RF defective. */
3995         uint64_t fpu_roms_defective    : 1;  /**< [  6:  6](RO) FPU ROMs defective. */
3996         uint64_t aes_roms_defective    : 1;  /**< [  7:  7](RO) AES ROMs defective. */
3997         uint64_t reserved_8_15         : 8;
3998         uint64_t icache_data_banks_with_defects : 8;/**< [ 23: 16](RO) Icache data banks with defects. */
3999         uint64_t icache_data_banks_with_unrepairable_defects : 8;/**< [ 31: 24](RO) Icache data banks with unrepairable defects. */
4000         uint64_t manufacturing_mode    : 1;  /**< [ 32: 32](RO) Manufacturing mode. */
4001         uint64_t clear_bist_was_run    : 1;  /**< [ 33: 33](RO) Clear BIST was run. */
4002         uint64_t fuse_controller_reports_hard_repair : 1;/**< [ 34: 34](RO) Fuse controller reports hard repair. */
4003         uint64_t reserved_35_63        : 29;
4004 #endif /* Word 0 - End */
4005     } s;
4006     /* struct bdk_ap_cvm_bist0_el1_s cn8; */
4007     struct bdk_ap_cvm_bist0_el1_cn9
4008     {
4009 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4010         uint64_t reserved_35_63        : 29;
4011         uint64_t fuse_controller_reports_hard_repair : 1;/**< [ 34: 34](RO) Fuse controller reports hard repair. */
4012         uint64_t reserved_33           : 1;
4013         uint64_t manufacturing_mode    : 1;  /**< [ 32: 32](RO) Manufacturing mode. */
4014         uint64_t icache_data_banks_with_unrepairable_defects : 8;/**< [ 31: 24](RO) Icache data banks with unrepairable defects. */
4015         uint64_t icache_data_banks_with_defects : 8;/**< [ 23: 16](RO) Icache data banks with defects. */
4016         uint64_t reserved_8_15         : 8;
4017         uint64_t aes_roms_defective    : 1;  /**< [  7:  7](RO) AES ROMs defective. */
4018         uint64_t fpu_roms_defective    : 1;  /**< [  6:  6](RO) FPU ROMs defective. */
4019         uint64_t fpu_rf_defective      : 1;  /**< [  5:  5](RO) FPU/SIMD RF defective. */
4020         uint64_t integer_rf_defective  : 1;  /**< [  4:  4](RO) Integer RF defective. */
4021         uint64_t jrt_defective         : 1;  /**< [  3:  3](RO) JRT defective. */
4022         uint64_t bht_defective         : 1;  /**< [  2:  2](RO) BHT defective. */
4023         uint64_t icache_tag_defective  : 1;  /**< [  1:  1](RO) Icache tag defective. */
4024         uint64_t icache_data_defective : 1;  /**< [  0:  0](RO) Icache data defective/unrepairable. */
4025 #else /* Word 0 - Little Endian */
4026         uint64_t icache_data_defective : 1;  /**< [  0:  0](RO) Icache data defective/unrepairable. */
4027         uint64_t icache_tag_defective  : 1;  /**< [  1:  1](RO) Icache tag defective. */
4028         uint64_t bht_defective         : 1;  /**< [  2:  2](RO) BHT defective. */
4029         uint64_t jrt_defective         : 1;  /**< [  3:  3](RO) JRT defective. */
4030         uint64_t integer_rf_defective  : 1;  /**< [  4:  4](RO) Integer RF defective. */
4031         uint64_t fpu_rf_defective      : 1;  /**< [  5:  5](RO) FPU/SIMD RF defective. */
4032         uint64_t fpu_roms_defective    : 1;  /**< [  6:  6](RO) FPU ROMs defective. */
4033         uint64_t aes_roms_defective    : 1;  /**< [  7:  7](RO) AES ROMs defective. */
4034         uint64_t reserved_8_15         : 8;
4035         uint64_t icache_data_banks_with_defects : 8;/**< [ 23: 16](RO) Icache data banks with defects. */
4036         uint64_t icache_data_banks_with_unrepairable_defects : 8;/**< [ 31: 24](RO) Icache data banks with unrepairable defects. */
4037         uint64_t manufacturing_mode    : 1;  /**< [ 32: 32](RO) Manufacturing mode. */
4038         uint64_t reserved_33           : 1;
4039         uint64_t fuse_controller_reports_hard_repair : 1;/**< [ 34: 34](RO) Fuse controller reports hard repair. */
4040         uint64_t reserved_35_63        : 29;
4041 #endif /* Word 0 - End */
4042     } cn9;
4043 };
4044 typedef union bdk_ap_cvm_bist0_el1 bdk_ap_cvm_bist0_el1_t;
4045 
4046 #define BDK_AP_CVM_BIST0_EL1 BDK_AP_CVM_BIST0_EL1_FUNC()
4047 static inline uint64_t BDK_AP_CVM_BIST0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_BIST0_EL1_FUNC(void)4048 static inline uint64_t BDK_AP_CVM_BIST0_EL1_FUNC(void)
4049 {
4050     return 0x3000b010000ll;
4051 }
4052 
4053 #define typedef_BDK_AP_CVM_BIST0_EL1 bdk_ap_cvm_bist0_el1_t
4054 #define bustype_BDK_AP_CVM_BIST0_EL1 BDK_CSR_TYPE_SYSREG
4055 #define basename_BDK_AP_CVM_BIST0_EL1 "AP_CVM_BIST0_EL1"
4056 #define busnum_BDK_AP_CVM_BIST0_EL1 0
4057 #define arguments_BDK_AP_CVM_BIST0_EL1 -1,-1,-1,-1
4058 
4059 /**
4060  * Register (SYSREG) ap_cvm_bist1_el1
4061  *
4062  * AP Cavium BIST1 Register
4063  * This register indicates BIST status, where a 1 in a bit position indicates defective.
4064  */
4065 union bdk_ap_cvm_bist1_el1
4066 {
4067     uint64_t u;
4068     struct bdk_ap_cvm_bist1_el1_s
4069     {
4070 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4071         uint64_t reserved_48_63        : 16;
4072         uint64_t icache_bank7          : 6;  /**< [ 47: 42](RO) Icache bank7 bad set, 0x3F means no defect. */
4073         uint64_t icache_bank6          : 6;  /**< [ 41: 36](RO) Icache bank6 bad set, 0x3F means no defect. */
4074         uint64_t icache_bank5          : 6;  /**< [ 35: 30](RO) Icache bank5 bad set, 0x3F means no defect. */
4075         uint64_t icache_bank4          : 6;  /**< [ 29: 24](RO) Icache bank4 bad set, 0x3F means no defect. */
4076         uint64_t icache_bank3          : 6;  /**< [ 23: 18](RO) Icache bank3 bad set, 0x3F means no defect. */
4077         uint64_t icache_bank2          : 6;  /**< [ 17: 12](RO) Icache bank2 bad set, 0x3F means no defect. */
4078         uint64_t icache_bank1          : 6;  /**< [ 11:  6](RO) Icache bank1 bad set, 0x3F means no defect. */
4079         uint64_t icache_bank0          : 6;  /**< [  5:  0](RO) Icache bank0 bad set, 0x3F means no defect. */
4080 #else /* Word 0 - Little Endian */
4081         uint64_t icache_bank0          : 6;  /**< [  5:  0](RO) Icache bank0 bad set, 0x3F means no defect. */
4082         uint64_t icache_bank1          : 6;  /**< [ 11:  6](RO) Icache bank1 bad set, 0x3F means no defect. */
4083         uint64_t icache_bank2          : 6;  /**< [ 17: 12](RO) Icache bank2 bad set, 0x3F means no defect. */
4084         uint64_t icache_bank3          : 6;  /**< [ 23: 18](RO) Icache bank3 bad set, 0x3F means no defect. */
4085         uint64_t icache_bank4          : 6;  /**< [ 29: 24](RO) Icache bank4 bad set, 0x3F means no defect. */
4086         uint64_t icache_bank5          : 6;  /**< [ 35: 30](RO) Icache bank5 bad set, 0x3F means no defect. */
4087         uint64_t icache_bank6          : 6;  /**< [ 41: 36](RO) Icache bank6 bad set, 0x3F means no defect. */
4088         uint64_t icache_bank7          : 6;  /**< [ 47: 42](RO) Icache bank7 bad set, 0x3F means no defect. */
4089         uint64_t reserved_48_63        : 16;
4090 #endif /* Word 0 - End */
4091     } s;
4092     /* struct bdk_ap_cvm_bist1_el1_s cn8; */
4093     struct bdk_ap_cvm_bist1_el1_cn9
4094     {
4095 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4096         uint64_t reserved_0_63         : 64;
4097 #else /* Word 0 - Little Endian */
4098         uint64_t reserved_0_63         : 64;
4099 #endif /* Word 0 - End */
4100     } cn9;
4101 };
4102 typedef union bdk_ap_cvm_bist1_el1 bdk_ap_cvm_bist1_el1_t;
4103 
4104 #define BDK_AP_CVM_BIST1_EL1 BDK_AP_CVM_BIST1_EL1_FUNC()
4105 static inline uint64_t BDK_AP_CVM_BIST1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_BIST1_EL1_FUNC(void)4106 static inline uint64_t BDK_AP_CVM_BIST1_EL1_FUNC(void)
4107 {
4108     return 0x3000b010100ll;
4109 }
4110 
4111 #define typedef_BDK_AP_CVM_BIST1_EL1 bdk_ap_cvm_bist1_el1_t
4112 #define bustype_BDK_AP_CVM_BIST1_EL1 BDK_CSR_TYPE_SYSREG
4113 #define basename_BDK_AP_CVM_BIST1_EL1 "AP_CVM_BIST1_EL1"
4114 #define busnum_BDK_AP_CVM_BIST1_EL1 0
4115 #define arguments_BDK_AP_CVM_BIST1_EL1 -1,-1,-1,-1
4116 
4117 /**
4118  * Register (SYSREG) ap_cvm_bist2_el1
4119  *
4120  * AP Cavium BIST2 Register
4121  * This register indicates BIST status, where a 1 in a bit position indicates defective.
4122  */
4123 union bdk_ap_cvm_bist2_el1
4124 {
4125     uint64_t u;
4126     struct bdk_ap_cvm_bist2_el1_s
4127     {
4128 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4129         uint64_t reserved_9_63         : 55;
4130         uint64_t wcu                   : 1;  /**< [  8:  8](RO) WCU defective. */
4131         uint64_t dut                   : 1;  /**< [  7:  7](RO) DUT defective. */
4132         uint64_t wbf                   : 1;  /**< [  6:  6](RO) WBF defective. */
4133         uint64_t maf                   : 1;  /**< [  5:  5](RO) MAF defective. */
4134         uint64_t utlb                  : 1;  /**< [  4:  4](RO) UTLB defective. */
4135         uint64_t mtlb                  : 1;  /**< [  3:  3](RO) MTLB defective. */
4136         uint64_t l1dp                  : 1;  /**< [  2:  2](RO) Dcache PTAG defective. */
4137         uint64_t l1dv                  : 1;  /**< [  1:  1](RO) Dcache VTAG defective. */
4138         uint64_t l1dd                  : 1;  /**< [  0:  0](RO) Dcache Data defective. */
4139 #else /* Word 0 - Little Endian */
4140         uint64_t l1dd                  : 1;  /**< [  0:  0](RO) Dcache Data defective. */
4141         uint64_t l1dv                  : 1;  /**< [  1:  1](RO) Dcache VTAG defective. */
4142         uint64_t l1dp                  : 1;  /**< [  2:  2](RO) Dcache PTAG defective. */
4143         uint64_t mtlb                  : 1;  /**< [  3:  3](RO) MTLB defective. */
4144         uint64_t utlb                  : 1;  /**< [  4:  4](RO) UTLB defective. */
4145         uint64_t maf                   : 1;  /**< [  5:  5](RO) MAF defective. */
4146         uint64_t wbf                   : 1;  /**< [  6:  6](RO) WBF defective. */
4147         uint64_t dut                   : 1;  /**< [  7:  7](RO) DUT defective. */
4148         uint64_t wcu                   : 1;  /**< [  8:  8](RO) WCU defective. */
4149         uint64_t reserved_9_63         : 55;
4150 #endif /* Word 0 - End */
4151     } s;
4152     /* struct bdk_ap_cvm_bist2_el1_s cn8; */
4153     struct bdk_ap_cvm_bist2_el1_cn9
4154     {
4155 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4156         uint64_t reserved_0_63         : 64;
4157 #else /* Word 0 - Little Endian */
4158         uint64_t reserved_0_63         : 64;
4159 #endif /* Word 0 - End */
4160     } cn9;
4161 };
4162 typedef union bdk_ap_cvm_bist2_el1 bdk_ap_cvm_bist2_el1_t;
4163 
4164 #define BDK_AP_CVM_BIST2_EL1 BDK_AP_CVM_BIST2_EL1_FUNC()
4165 static inline uint64_t BDK_AP_CVM_BIST2_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_BIST2_EL1_FUNC(void)4166 static inline uint64_t BDK_AP_CVM_BIST2_EL1_FUNC(void)
4167 {
4168     return 0x3000b010400ll;
4169 }
4170 
4171 #define typedef_BDK_AP_CVM_BIST2_EL1 bdk_ap_cvm_bist2_el1_t
4172 #define bustype_BDK_AP_CVM_BIST2_EL1 BDK_CSR_TYPE_SYSREG
4173 #define basename_BDK_AP_CVM_BIST2_EL1 "AP_CVM_BIST2_EL1"
4174 #define busnum_BDK_AP_CVM_BIST2_EL1 0
4175 #define arguments_BDK_AP_CVM_BIST2_EL1 -1,-1,-1,-1
4176 
4177 /**
4178  * Register (SYSREG) ap_cvm_bist3_el1
4179  *
4180  * AP Cavium BIST3 Register
4181  * This register indicates BIST status, where a 1 in a bit position indicates defective.
4182  */
4183 union bdk_ap_cvm_bist3_el1
4184 {
4185     uint64_t u;
4186     struct bdk_ap_cvm_bist3_el1_s
4187     {
4188 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4189         uint64_t reserved_48_63        : 16;
4190         uint64_t set7                  : 6;  /**< [ 47: 42](RO) Dcache set7 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4191         uint64_t set6                  : 6;  /**< [ 41: 36](RO) Dcache set6 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4192         uint64_t set5                  : 6;  /**< [ 35: 30](RO) Dcache set5 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4193         uint64_t set4                  : 6;  /**< [ 29: 24](RO) Dcache set4 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4194         uint64_t set3                  : 6;  /**< [ 23: 18](RO) Dcache set3 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4195         uint64_t set2                  : 6;  /**< [ 17: 12](RO) Dcache set2 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4196         uint64_t set1                  : 6;  /**< [ 11:  6](RO) Dcache set1 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4197         uint64_t set0                  : 6;  /**< [  5:  0](RO) Dcache set0 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4198 #else /* Word 0 - Little Endian */
4199         uint64_t set0                  : 6;  /**< [  5:  0](RO) Dcache set0 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4200         uint64_t set1                  : 6;  /**< [ 11:  6](RO) Dcache set1 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4201         uint64_t set2                  : 6;  /**< [ 17: 12](RO) Dcache set2 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4202         uint64_t set3                  : 6;  /**< [ 23: 18](RO) Dcache set3 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4203         uint64_t set4                  : 6;  /**< [ 29: 24](RO) Dcache set4 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4204         uint64_t set5                  : 6;  /**< [ 35: 30](RO) Dcache set5 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4205         uint64_t set6                  : 6;  /**< [ 41: 36](RO) Dcache set6 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4206         uint64_t set7                  : 6;  /**< [ 47: 42](RO) Dcache set7 bad way, 0x3F = no defect, 0x3E = multiple defects. */
4207         uint64_t reserved_48_63        : 16;
4208 #endif /* Word 0 - End */
4209     } s;
4210     /* struct bdk_ap_cvm_bist3_el1_s cn8; */
4211     struct bdk_ap_cvm_bist3_el1_cn9
4212     {
4213 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4214         uint64_t reserved_48_63        : 16;
4215         uint64_t reserved_0_47         : 48;
4216 #else /* Word 0 - Little Endian */
4217         uint64_t reserved_0_47         : 48;
4218         uint64_t reserved_48_63        : 16;
4219 #endif /* Word 0 - End */
4220     } cn9;
4221 };
4222 typedef union bdk_ap_cvm_bist3_el1 bdk_ap_cvm_bist3_el1_t;
4223 
4224 #define BDK_AP_CVM_BIST3_EL1 BDK_AP_CVM_BIST3_EL1_FUNC()
4225 static inline uint64_t BDK_AP_CVM_BIST3_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_BIST3_EL1_FUNC(void)4226 static inline uint64_t BDK_AP_CVM_BIST3_EL1_FUNC(void)
4227 {
4228     return 0x3000b010500ll;
4229 }
4230 
4231 #define typedef_BDK_AP_CVM_BIST3_EL1 bdk_ap_cvm_bist3_el1_t
4232 #define bustype_BDK_AP_CVM_BIST3_EL1 BDK_CSR_TYPE_SYSREG
4233 #define basename_BDK_AP_CVM_BIST3_EL1 "AP_CVM_BIST3_EL1"
4234 #define busnum_BDK_AP_CVM_BIST3_EL1 0
4235 #define arguments_BDK_AP_CVM_BIST3_EL1 -1,-1,-1,-1
4236 
4237 /**
4238  * Register (SYSREG) ap_cvm_cpid_el2
4239  *
4240  * AP Cavium Cache Partitioning EL2 Register
4241  * This register provides Cavium-specific control information.
4242  */
4243 union bdk_ap_cvm_cpid_el2
4244 {
4245     uint64_t u;
4246     struct bdk_ap_cvm_cpid_el2_s
4247     {
4248 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4249         uint64_t reserved_7_63         : 57;
4250         uint64_t cpid                  : 7;  /**< [  6:  0](R/W) Cache partition ID. */
4251 #else /* Word 0 - Little Endian */
4252         uint64_t cpid                  : 7;  /**< [  6:  0](R/W) Cache partition ID. */
4253         uint64_t reserved_7_63         : 57;
4254 #endif /* Word 0 - End */
4255     } s;
4256     /* struct bdk_ap_cvm_cpid_el2_s cn; */
4257 };
4258 typedef union bdk_ap_cvm_cpid_el2 bdk_ap_cvm_cpid_el2_t;
4259 
4260 #define BDK_AP_CVM_CPID_EL2 BDK_AP_CVM_CPID_EL2_FUNC()
4261 static inline uint64_t BDK_AP_CVM_CPID_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_CPID_EL2_FUNC(void)4262 static inline uint64_t BDK_AP_CVM_CPID_EL2_FUNC(void)
4263 {
4264     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
4265         return 0x3040b060400ll;
4266     __bdk_csr_fatal("AP_CVM_CPID_EL2", 0, 0, 0, 0, 0);
4267 }
4268 
4269 #define typedef_BDK_AP_CVM_CPID_EL2 bdk_ap_cvm_cpid_el2_t
4270 #define bustype_BDK_AP_CVM_CPID_EL2 BDK_CSR_TYPE_SYSREG
4271 #define basename_BDK_AP_CVM_CPID_EL2 "AP_CVM_CPID_EL2"
4272 #define busnum_BDK_AP_CVM_CPID_EL2 0
4273 #define arguments_BDK_AP_CVM_CPID_EL2 -1,-1,-1,-1
4274 
4275 /**
4276  * Register (SYSREG) ap_cvm_cpid_el3
4277  *
4278  * AP Cavium Cache Partitioning EL3 Register
4279  * This register provides Cavium-specific control information.
4280  */
4281 union bdk_ap_cvm_cpid_el3
4282 {
4283     uint64_t u;
4284     struct bdk_ap_cvm_cpid_el3_s
4285     {
4286 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4287         uint64_t reserved_7_63         : 57;
4288         uint64_t cpid                  : 7;  /**< [  6:  0](R/W) Cache partition ID. */
4289 #else /* Word 0 - Little Endian */
4290         uint64_t cpid                  : 7;  /**< [  6:  0](R/W) Cache partition ID. */
4291         uint64_t reserved_7_63         : 57;
4292 #endif /* Word 0 - End */
4293     } s;
4294     /* struct bdk_ap_cvm_cpid_el3_s cn; */
4295 };
4296 typedef union bdk_ap_cvm_cpid_el3 bdk_ap_cvm_cpid_el3_t;
4297 
4298 #define BDK_AP_CVM_CPID_EL3 BDK_AP_CVM_CPID_EL3_FUNC()
4299 static inline uint64_t BDK_AP_CVM_CPID_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_CPID_EL3_FUNC(void)4300 static inline uint64_t BDK_AP_CVM_CPID_EL3_FUNC(void)
4301 {
4302     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
4303         return 0x3060b060400ll;
4304     __bdk_csr_fatal("AP_CVM_CPID_EL3", 0, 0, 0, 0, 0);
4305 }
4306 
4307 #define typedef_BDK_AP_CVM_CPID_EL3 bdk_ap_cvm_cpid_el3_t
4308 #define bustype_BDK_AP_CVM_CPID_EL3 BDK_CSR_TYPE_SYSREG
4309 #define basename_BDK_AP_CVM_CPID_EL3 "AP_CVM_CPID_EL3"
4310 #define busnum_BDK_AP_CVM_CPID_EL3 0
4311 #define arguments_BDK_AP_CVM_CPID_EL3 -1,-1,-1,-1
4312 
4313 /**
4314  * Register (SYSREG) ap_cvm_dcachedata0_el1
4315  *
4316  * AP Cavium Dcache Data 0 Register
4317  */
4318 union bdk_ap_cvm_dcachedata0_el1
4319 {
4320     uint64_t u;
4321     struct bdk_ap_cvm_dcachedata0_el1_s
4322     {
4323 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4324         uint64_t data                  : 64; /**< [ 63:  0](RO) Dcache data. */
4325 #else /* Word 0 - Little Endian */
4326         uint64_t data                  : 64; /**< [ 63:  0](RO) Dcache data. */
4327 #endif /* Word 0 - End */
4328     } s;
4329     /* struct bdk_ap_cvm_dcachedata0_el1_s cn; */
4330 };
4331 typedef union bdk_ap_cvm_dcachedata0_el1 bdk_ap_cvm_dcachedata0_el1_t;
4332 
4333 #define BDK_AP_CVM_DCACHEDATA0_EL1 BDK_AP_CVM_DCACHEDATA0_EL1_FUNC()
4334 static inline uint64_t BDK_AP_CVM_DCACHEDATA0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DCACHEDATA0_EL1_FUNC(void)4335 static inline uint64_t BDK_AP_CVM_DCACHEDATA0_EL1_FUNC(void)
4336 {
4337     return 0x3000b030400ll;
4338 }
4339 
4340 #define typedef_BDK_AP_CVM_DCACHEDATA0_EL1 bdk_ap_cvm_dcachedata0_el1_t
4341 #define bustype_BDK_AP_CVM_DCACHEDATA0_EL1 BDK_CSR_TYPE_SYSREG
4342 #define basename_BDK_AP_CVM_DCACHEDATA0_EL1 "AP_CVM_DCACHEDATA0_EL1"
4343 #define busnum_BDK_AP_CVM_DCACHEDATA0_EL1 0
4344 #define arguments_BDK_AP_CVM_DCACHEDATA0_EL1 -1,-1,-1,-1
4345 
4346 /**
4347  * Register (SYSREG) ap_cvm_dcachedata1_el1
4348  *
4349  * AP Cavium Dcache Data 1 Register
4350  */
4351 union bdk_ap_cvm_dcachedata1_el1
4352 {
4353     uint64_t u;
4354     struct bdk_ap_cvm_dcachedata1_el1_s
4355     {
4356 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4357         uint64_t reserved_8_63         : 56;
4358         uint64_t parity                : 8;  /**< [  7:  0](RO) Parity bits. */
4359 #else /* Word 0 - Little Endian */
4360         uint64_t parity                : 8;  /**< [  7:  0](RO) Parity bits. */
4361         uint64_t reserved_8_63         : 56;
4362 #endif /* Word 0 - End */
4363     } s;
4364     /* struct bdk_ap_cvm_dcachedata1_el1_s cn; */
4365 };
4366 typedef union bdk_ap_cvm_dcachedata1_el1 bdk_ap_cvm_dcachedata1_el1_t;
4367 
4368 #define BDK_AP_CVM_DCACHEDATA1_EL1 BDK_AP_CVM_DCACHEDATA1_EL1_FUNC()
4369 static inline uint64_t BDK_AP_CVM_DCACHEDATA1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DCACHEDATA1_EL1_FUNC(void)4370 static inline uint64_t BDK_AP_CVM_DCACHEDATA1_EL1_FUNC(void)
4371 {
4372     return 0x3000b030500ll;
4373 }
4374 
4375 #define typedef_BDK_AP_CVM_DCACHEDATA1_EL1 bdk_ap_cvm_dcachedata1_el1_t
4376 #define bustype_BDK_AP_CVM_DCACHEDATA1_EL1 BDK_CSR_TYPE_SYSREG
4377 #define basename_BDK_AP_CVM_DCACHEDATA1_EL1 "AP_CVM_DCACHEDATA1_EL1"
4378 #define busnum_BDK_AP_CVM_DCACHEDATA1_EL1 0
4379 #define arguments_BDK_AP_CVM_DCACHEDATA1_EL1 -1,-1,-1,-1
4380 
4381 /**
4382  * Register (SYSREG) ap_cvm_dcacheptag0_el1
4383  *
4384  * AP Cavium Dcache Ptag 0 Register
4385  */
4386 union bdk_ap_cvm_dcacheptag0_el1
4387 {
4388     uint64_t u;
4389     struct bdk_ap_cvm_dcacheptag0_el1_s
4390     {
4391 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4392         uint64_t reserved_44_63        : 20;
4393         uint64_t nsec                  : 1;  /**< [ 43: 43](RO) Not-shared. */
4394         uint64_t ptag                  : 33; /**< [ 42: 10](RO) Physical tag \<42:10\>. */
4395         uint64_t reserved_1_9          : 9;
4396         uint64_t valid                 : 1;  /**< [  0:  0](RO) Valid. */
4397 #else /* Word 0 - Little Endian */
4398         uint64_t valid                 : 1;  /**< [  0:  0](RO) Valid. */
4399         uint64_t reserved_1_9          : 9;
4400         uint64_t ptag                  : 33; /**< [ 42: 10](RO) Physical tag \<42:10\>. */
4401         uint64_t nsec                  : 1;  /**< [ 43: 43](RO) Not-shared. */
4402         uint64_t reserved_44_63        : 20;
4403 #endif /* Word 0 - End */
4404     } s;
4405     /* struct bdk_ap_cvm_dcacheptag0_el1_s cn; */
4406 };
4407 typedef union bdk_ap_cvm_dcacheptag0_el1 bdk_ap_cvm_dcacheptag0_el1_t;
4408 
4409 #define BDK_AP_CVM_DCACHEPTAG0_EL1 BDK_AP_CVM_DCACHEPTAG0_EL1_FUNC()
4410 static inline uint64_t BDK_AP_CVM_DCACHEPTAG0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DCACHEPTAG0_EL1_FUNC(void)4411 static inline uint64_t BDK_AP_CVM_DCACHEPTAG0_EL1_FUNC(void)
4412 {
4413     return 0x3000b040400ll;
4414 }
4415 
4416 #define typedef_BDK_AP_CVM_DCACHEPTAG0_EL1 bdk_ap_cvm_dcacheptag0_el1_t
4417 #define bustype_BDK_AP_CVM_DCACHEPTAG0_EL1 BDK_CSR_TYPE_SYSREG
4418 #define basename_BDK_AP_CVM_DCACHEPTAG0_EL1 "AP_CVM_DCACHEPTAG0_EL1"
4419 #define busnum_BDK_AP_CVM_DCACHEPTAG0_EL1 0
4420 #define arguments_BDK_AP_CVM_DCACHEPTAG0_EL1 -1,-1,-1,-1
4421 
4422 /**
4423  * Register (SYSREG) ap_cvm_dcachevtag0_el1
4424  *
4425  * AP Cavium Dcache Vtag 0 Register
4426  */
4427 union bdk_ap_cvm_dcachevtag0_el1
4428 {
4429     uint64_t u;
4430     struct bdk_ap_cvm_dcachevtag0_el1_s
4431     {
4432 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4433         uint64_t reserved_60_63        : 4;
4434         uint64_t eva_vmid              : 4;  /**< [ 59: 56](RO) Entry EVA_VMID. */
4435         uint64_t reserved_49_55        : 7;
4436         uint64_t r                     : 1;  /**< [ 48: 48](RO) Entry R. */
4437         uint64_t vtag                  : 38; /**< [ 47: 10](RO) Entry VTAG\<47:10\>. */
4438         uint64_t eva_asid              : 6;  /**< [  9:  4](RO) Entry EVA_ASID. */
4439         uint64_t ng                    : 1;  /**< [  3:  3](RO) Entry NG. */
4440         uint64_t el_1or0               : 1;  /**< [  2:  2](RO) Entry is EL0 or EL1. */
4441         uint64_t nsec                  : 1;  /**< [  1:  1](RO) Entry is NS. */
4442         uint64_t valid                 : 1;  /**< [  0:  0](RO) Entry valid. */
4443 #else /* Word 0 - Little Endian */
4444         uint64_t valid                 : 1;  /**< [  0:  0](RO) Entry valid. */
4445         uint64_t nsec                  : 1;  /**< [  1:  1](RO) Entry is NS. */
4446         uint64_t el_1or0               : 1;  /**< [  2:  2](RO) Entry is EL0 or EL1. */
4447         uint64_t ng                    : 1;  /**< [  3:  3](RO) Entry NG. */
4448         uint64_t eva_asid              : 6;  /**< [  9:  4](RO) Entry EVA_ASID. */
4449         uint64_t vtag                  : 38; /**< [ 47: 10](RO) Entry VTAG\<47:10\>. */
4450         uint64_t r                     : 1;  /**< [ 48: 48](RO) Entry R. */
4451         uint64_t reserved_49_55        : 7;
4452         uint64_t eva_vmid              : 4;  /**< [ 59: 56](RO) Entry EVA_VMID. */
4453         uint64_t reserved_60_63        : 4;
4454 #endif /* Word 0 - End */
4455     } s;
4456     /* struct bdk_ap_cvm_dcachevtag0_el1_s cn; */
4457 };
4458 typedef union bdk_ap_cvm_dcachevtag0_el1 bdk_ap_cvm_dcachevtag0_el1_t;
4459 
4460 #define BDK_AP_CVM_DCACHEVTAG0_EL1 BDK_AP_CVM_DCACHEVTAG0_EL1_FUNC()
4461 static inline uint64_t BDK_AP_CVM_DCACHEVTAG0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DCACHEVTAG0_EL1_FUNC(void)4462 static inline uint64_t BDK_AP_CVM_DCACHEVTAG0_EL1_FUNC(void)
4463 {
4464     return 0x3000b030600ll;
4465 }
4466 
4467 #define typedef_BDK_AP_CVM_DCACHEVTAG0_EL1 bdk_ap_cvm_dcachevtag0_el1_t
4468 #define bustype_BDK_AP_CVM_DCACHEVTAG0_EL1 BDK_CSR_TYPE_SYSREG
4469 #define basename_BDK_AP_CVM_DCACHEVTAG0_EL1 "AP_CVM_DCACHEVTAG0_EL1"
4470 #define busnum_BDK_AP_CVM_DCACHEVTAG0_EL1 0
4471 #define arguments_BDK_AP_CVM_DCACHEVTAG0_EL1 -1,-1,-1,-1
4472 
4473 /**
4474  * Register (SYSREG) ap_cvm_dcachevtag1_el1
4475  *
4476  * AP Cavium Dcache Vtag 1 Register
4477  */
4478 union bdk_ap_cvm_dcachevtag1_el1
4479 {
4480     uint64_t u;
4481     struct bdk_ap_cvm_dcachevtag1_el1_s
4482     {
4483 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4484         uint64_t reserved_25_63        : 39;
4485         uint64_t ent1                  : 9;  /**< [ 24: 16](RO) ENT1. */
4486         uint64_t reserved_9_15         : 7;
4487         uint64_t ent2                  : 9;  /**< [  8:  0](RO) ENT2. */
4488 #else /* Word 0 - Little Endian */
4489         uint64_t ent2                  : 9;  /**< [  8:  0](RO) ENT2. */
4490         uint64_t reserved_9_15         : 7;
4491         uint64_t ent1                  : 9;  /**< [ 24: 16](RO) ENT1. */
4492         uint64_t reserved_25_63        : 39;
4493 #endif /* Word 0 - End */
4494     } s;
4495     /* struct bdk_ap_cvm_dcachevtag1_el1_s cn; */
4496 };
4497 typedef union bdk_ap_cvm_dcachevtag1_el1 bdk_ap_cvm_dcachevtag1_el1_t;
4498 
4499 #define BDK_AP_CVM_DCACHEVTAG1_EL1 BDK_AP_CVM_DCACHEVTAG1_EL1_FUNC()
4500 static inline uint64_t BDK_AP_CVM_DCACHEVTAG1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DCACHEVTAG1_EL1_FUNC(void)4501 static inline uint64_t BDK_AP_CVM_DCACHEVTAG1_EL1_FUNC(void)
4502 {
4503     return 0x3000b030700ll;
4504 }
4505 
4506 #define typedef_BDK_AP_CVM_DCACHEVTAG1_EL1 bdk_ap_cvm_dcachevtag1_el1_t
4507 #define bustype_BDK_AP_CVM_DCACHEVTAG1_EL1 BDK_CSR_TYPE_SYSREG
4508 #define basename_BDK_AP_CVM_DCACHEVTAG1_EL1 "AP_CVM_DCACHEVTAG1_EL1"
4509 #define busnum_BDK_AP_CVM_DCACHEVTAG1_EL1 0
4510 #define arguments_BDK_AP_CVM_DCACHEVTAG1_EL1 -1,-1,-1,-1
4511 
4512 /**
4513  * Register (SYSREG) ap_cvm_debug0_el3
4514  *
4515  * INTERNAL: AP Cavium Debug 0 Register
4516  *
4517  * This register is for diagnostic use only.
4518  */
4519 union bdk_ap_cvm_debug0_el3
4520 {
4521     uint64_t u;
4522     struct bdk_ap_cvm_debug0_el3_s
4523     {
4524 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4525         uint64_t current_pc            : 64; /**< [ 63:  0](RO) Current PC. */
4526 #else /* Word 0 - Little Endian */
4527         uint64_t current_pc            : 64; /**< [ 63:  0](RO) Current PC. */
4528 #endif /* Word 0 - End */
4529     } s;
4530     /* struct bdk_ap_cvm_debug0_el3_s cn; */
4531 };
4532 typedef union bdk_ap_cvm_debug0_el3 bdk_ap_cvm_debug0_el3_t;
4533 
4534 #define BDK_AP_CVM_DEBUG0_EL3 BDK_AP_CVM_DEBUG0_EL3_FUNC()
4535 static inline uint64_t BDK_AP_CVM_DEBUG0_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DEBUG0_EL3_FUNC(void)4536 static inline uint64_t BDK_AP_CVM_DEBUG0_EL3_FUNC(void)
4537 {
4538     return 0x3060b040000ll;
4539 }
4540 
4541 #define typedef_BDK_AP_CVM_DEBUG0_EL3 bdk_ap_cvm_debug0_el3_t
4542 #define bustype_BDK_AP_CVM_DEBUG0_EL3 BDK_CSR_TYPE_SYSREG
4543 #define basename_BDK_AP_CVM_DEBUG0_EL3 "AP_CVM_DEBUG0_EL3"
4544 #define busnum_BDK_AP_CVM_DEBUG0_EL3 0
4545 #define arguments_BDK_AP_CVM_DEBUG0_EL3 -1,-1,-1,-1
4546 
4547 /**
4548  * Register (SYSREG) ap_cvm_debug1_el3
4549  *
4550  * INTERNAL: AP Cavium Debug 1 Register
4551  *
4552  * This register is for diagnostic use only.
4553  */
4554 union bdk_ap_cvm_debug1_el3
4555 {
4556     uint64_t u;
4557     struct bdk_ap_cvm_debug1_el3_s
4558     {
4559 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4560         uint64_t current_fetch         : 64; /**< [ 63:  0](RO) Current fetcher address. */
4561 #else /* Word 0 - Little Endian */
4562         uint64_t current_fetch         : 64; /**< [ 63:  0](RO) Current fetcher address. */
4563 #endif /* Word 0 - End */
4564     } s;
4565     /* struct bdk_ap_cvm_debug1_el3_s cn; */
4566 };
4567 typedef union bdk_ap_cvm_debug1_el3 bdk_ap_cvm_debug1_el3_t;
4568 
4569 #define BDK_AP_CVM_DEBUG1_EL3 BDK_AP_CVM_DEBUG1_EL3_FUNC()
4570 static inline uint64_t BDK_AP_CVM_DEBUG1_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DEBUG1_EL3_FUNC(void)4571 static inline uint64_t BDK_AP_CVM_DEBUG1_EL3_FUNC(void)
4572 {
4573     return 0x3060b040100ll;
4574 }
4575 
4576 #define typedef_BDK_AP_CVM_DEBUG1_EL3 bdk_ap_cvm_debug1_el3_t
4577 #define bustype_BDK_AP_CVM_DEBUG1_EL3 BDK_CSR_TYPE_SYSREG
4578 #define basename_BDK_AP_CVM_DEBUG1_EL3 "AP_CVM_DEBUG1_EL3"
4579 #define busnum_BDK_AP_CVM_DEBUG1_EL3 0
4580 #define arguments_BDK_AP_CVM_DEBUG1_EL3 -1,-1,-1,-1
4581 
4582 /**
4583  * Register (SYSREG) ap_cvm_debug2_el3
4584  *
4585  * INTERNAL: AP Cavium Debug 2 Register
4586  *
4587  * This register is for diagnostic use only.
4588  */
4589 union bdk_ap_cvm_debug2_el3
4590 {
4591     uint64_t u;
4592     struct bdk_ap_cvm_debug2_el3_s
4593     {
4594 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4595         uint64_t last_ifill            : 64; /**< [ 63:  0](RO) Last ifill address. */
4596 #else /* Word 0 - Little Endian */
4597         uint64_t last_ifill            : 64; /**< [ 63:  0](RO) Last ifill address. */
4598 #endif /* Word 0 - End */
4599     } s;
4600     /* struct bdk_ap_cvm_debug2_el3_s cn; */
4601 };
4602 typedef union bdk_ap_cvm_debug2_el3 bdk_ap_cvm_debug2_el3_t;
4603 
4604 #define BDK_AP_CVM_DEBUG2_EL3 BDK_AP_CVM_DEBUG2_EL3_FUNC()
4605 static inline uint64_t BDK_AP_CVM_DEBUG2_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DEBUG2_EL3_FUNC(void)4606 static inline uint64_t BDK_AP_CVM_DEBUG2_EL3_FUNC(void)
4607 {
4608     return 0x3060b040200ll;
4609 }
4610 
4611 #define typedef_BDK_AP_CVM_DEBUG2_EL3 bdk_ap_cvm_debug2_el3_t
4612 #define bustype_BDK_AP_CVM_DEBUG2_EL3 BDK_CSR_TYPE_SYSREG
4613 #define basename_BDK_AP_CVM_DEBUG2_EL3 "AP_CVM_DEBUG2_EL3"
4614 #define busnum_BDK_AP_CVM_DEBUG2_EL3 0
4615 #define arguments_BDK_AP_CVM_DEBUG2_EL3 -1,-1,-1,-1
4616 
4617 /**
4618  * Register (SYSREG) ap_cvm_debug3_el3
4619  *
4620  * INTERNAL: AP Cavium Debug 3 Register
4621  *
4622  * This register is for diagnostic use only.
4623  */
4624 union bdk_ap_cvm_debug3_el3
4625 {
4626     uint64_t u;
4627     struct bdk_ap_cvm_debug3_el3_s
4628     {
4629 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4630         uint64_t last_committed        : 64; /**< [ 63:  0](RO) Last committed instruction PC. */
4631 #else /* Word 0 - Little Endian */
4632         uint64_t last_committed        : 64; /**< [ 63:  0](RO) Last committed instruction PC. */
4633 #endif /* Word 0 - End */
4634     } s;
4635     /* struct bdk_ap_cvm_debug3_el3_s cn; */
4636 };
4637 typedef union bdk_ap_cvm_debug3_el3 bdk_ap_cvm_debug3_el3_t;
4638 
4639 #define BDK_AP_CVM_DEBUG3_EL3 BDK_AP_CVM_DEBUG3_EL3_FUNC()
4640 static inline uint64_t BDK_AP_CVM_DEBUG3_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DEBUG3_EL3_FUNC(void)4641 static inline uint64_t BDK_AP_CVM_DEBUG3_EL3_FUNC(void)
4642 {
4643     return 0x3060b040300ll;
4644 }
4645 
4646 #define typedef_BDK_AP_CVM_DEBUG3_EL3 bdk_ap_cvm_debug3_el3_t
4647 #define bustype_BDK_AP_CVM_DEBUG3_EL3 BDK_CSR_TYPE_SYSREG
4648 #define basename_BDK_AP_CVM_DEBUG3_EL3 "AP_CVM_DEBUG3_EL3"
4649 #define busnum_BDK_AP_CVM_DEBUG3_EL3 0
4650 #define arguments_BDK_AP_CVM_DEBUG3_EL3 -1,-1,-1,-1
4651 
4652 /**
4653  * Register (SYSREG) ap_cvm_debug4_el3
4654  *
4655  * INTERNAL: AP Cavium Debug 4 Register
4656  *
4657  * This register is for diagnostic use only.
4658  */
4659 union bdk_ap_cvm_debug4_el3
4660 {
4661     uint64_t u;
4662     struct bdk_ap_cvm_debug4_el3_s
4663     {
4664 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4665         uint64_t reserved_24_63        : 40;
4666         uint64_t dual_issue_reason     : 8;  /**< [ 23: 16](RO) Reason dual issue didn't occur. */
4667         uint64_t issue_reason          : 8;  /**< [ 15:  8](RO) Reason issue didn't occur. */
4668         uint64_t reserved_5_7          : 3;
4669         uint64_t mem_stall_4a          : 1;  /**< [  4:  4](RO) Memory Stall stage 4a. */
4670         uint64_t waiting_for_pfill_4a  : 1;  /**< [  3:  3](RO) Waiting for PFILL stage 4a. */
4671         uint64_t waiting_for_ifill_4a  : 1;  /**< [  2:  2](RO) Waiting for IFILL stage 4a. */
4672         uint64_t exception_level       : 2;  /**< [  1:  0](RO) Current exception level. */
4673 #else /* Word 0 - Little Endian */
4674         uint64_t exception_level       : 2;  /**< [  1:  0](RO) Current exception level. */
4675         uint64_t waiting_for_ifill_4a  : 1;  /**< [  2:  2](RO) Waiting for IFILL stage 4a. */
4676         uint64_t waiting_for_pfill_4a  : 1;  /**< [  3:  3](RO) Waiting for PFILL stage 4a. */
4677         uint64_t mem_stall_4a          : 1;  /**< [  4:  4](RO) Memory Stall stage 4a. */
4678         uint64_t reserved_5_7          : 3;
4679         uint64_t issue_reason          : 8;  /**< [ 15:  8](RO) Reason issue didn't occur. */
4680         uint64_t dual_issue_reason     : 8;  /**< [ 23: 16](RO) Reason dual issue didn't occur. */
4681         uint64_t reserved_24_63        : 40;
4682 #endif /* Word 0 - End */
4683     } s;
4684     /* struct bdk_ap_cvm_debug4_el3_s cn; */
4685 };
4686 typedef union bdk_ap_cvm_debug4_el3 bdk_ap_cvm_debug4_el3_t;
4687 
4688 #define BDK_AP_CVM_DEBUG4_EL3 BDK_AP_CVM_DEBUG4_EL3_FUNC()
4689 static inline uint64_t BDK_AP_CVM_DEBUG4_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DEBUG4_EL3_FUNC(void)4690 static inline uint64_t BDK_AP_CVM_DEBUG4_EL3_FUNC(void)
4691 {
4692     return 0x3060b050000ll;
4693 }
4694 
4695 #define typedef_BDK_AP_CVM_DEBUG4_EL3 bdk_ap_cvm_debug4_el3_t
4696 #define bustype_BDK_AP_CVM_DEBUG4_EL3 BDK_CSR_TYPE_SYSREG
4697 #define basename_BDK_AP_CVM_DEBUG4_EL3 "AP_CVM_DEBUG4_EL3"
4698 #define busnum_BDK_AP_CVM_DEBUG4_EL3 0
4699 #define arguments_BDK_AP_CVM_DEBUG4_EL3 -1,-1,-1,-1
4700 
4701 /**
4702  * Register (SYSREG) ap_cvm_debug6_el3
4703  *
4704  * INTERNAL: AP Cavium Debug 6 Register
4705  *
4706  * This register is for diagnostic use only.
4707  */
4708 union bdk_ap_cvm_debug6_el3
4709 {
4710     uint64_t u;
4711     struct bdk_ap_cvm_debug6_el3_s
4712     {
4713 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4714         uint64_t reserved_41_63        : 23;
4715         uint64_t power_off             : 1;  /**< [ 40: 40](RO)  */
4716         uint64_t power_longterm        : 8;  /**< [ 39: 32](RO)  */
4717         uint64_t power_setting         : 8;  /**< [ 31: 24](RO)  */
4718         uint64_t reserved_22_23        : 2;
4719         uint64_t interval_power        : 22; /**< [ 21:  0](RO)  */
4720 #else /* Word 0 - Little Endian */
4721         uint64_t interval_power        : 22; /**< [ 21:  0](RO)  */
4722         uint64_t reserved_22_23        : 2;
4723         uint64_t power_setting         : 8;  /**< [ 31: 24](RO)  */
4724         uint64_t power_longterm        : 8;  /**< [ 39: 32](RO)  */
4725         uint64_t power_off             : 1;  /**< [ 40: 40](RO)  */
4726         uint64_t reserved_41_63        : 23;
4727 #endif /* Word 0 - End */
4728     } s;
4729     /* struct bdk_ap_cvm_debug6_el3_s cn; */
4730 };
4731 typedef union bdk_ap_cvm_debug6_el3 bdk_ap_cvm_debug6_el3_t;
4732 
4733 #define BDK_AP_CVM_DEBUG6_EL3 BDK_AP_CVM_DEBUG6_EL3_FUNC()
4734 static inline uint64_t BDK_AP_CVM_DEBUG6_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DEBUG6_EL3_FUNC(void)4735 static inline uint64_t BDK_AP_CVM_DEBUG6_EL3_FUNC(void)
4736 {
4737     return 0x3060b050200ll;
4738 }
4739 
4740 #define typedef_BDK_AP_CVM_DEBUG6_EL3 bdk_ap_cvm_debug6_el3_t
4741 #define bustype_BDK_AP_CVM_DEBUG6_EL3 BDK_CSR_TYPE_SYSREG
4742 #define basename_BDK_AP_CVM_DEBUG6_EL3 "AP_CVM_DEBUG6_EL3"
4743 #define busnum_BDK_AP_CVM_DEBUG6_EL3 0
4744 #define arguments_BDK_AP_CVM_DEBUG6_EL3 -1,-1,-1,-1
4745 
4746 /**
4747  * Register (SYSREG) ap_cvm_debug7_el3
4748  *
4749  * INTERNAL: AP Cavium Debug 7 Register
4750  *
4751  * This register is for diagnostic use only.
4752  */
4753 union bdk_ap_cvm_debug7_el3
4754 {
4755     uint64_t u;
4756     struct bdk_ap_cvm_debug7_el3_s
4757     {
4758 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4759         uint64_t reserved_0_63         : 64;
4760 #else /* Word 0 - Little Endian */
4761         uint64_t reserved_0_63         : 64;
4762 #endif /* Word 0 - End */
4763     } s;
4764     /* struct bdk_ap_cvm_debug7_el3_s cn; */
4765 };
4766 typedef union bdk_ap_cvm_debug7_el3 bdk_ap_cvm_debug7_el3_t;
4767 
4768 #define BDK_AP_CVM_DEBUG7_EL3 BDK_AP_CVM_DEBUG7_EL3_FUNC()
4769 static inline uint64_t BDK_AP_CVM_DEBUG7_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DEBUG7_EL3_FUNC(void)4770 static inline uint64_t BDK_AP_CVM_DEBUG7_EL3_FUNC(void)
4771 {
4772     return 0x3060b050300ll;
4773 }
4774 
4775 #define typedef_BDK_AP_CVM_DEBUG7_EL3 bdk_ap_cvm_debug7_el3_t
4776 #define bustype_BDK_AP_CVM_DEBUG7_EL3 BDK_CSR_TYPE_SYSREG
4777 #define basename_BDK_AP_CVM_DEBUG7_EL3 "AP_CVM_DEBUG7_EL3"
4778 #define busnum_BDK_AP_CVM_DEBUG7_EL3 0
4779 #define arguments_BDK_AP_CVM_DEBUG7_EL3 -1,-1,-1,-1
4780 
4781 /**
4782  * Register (SYSREG) ap_cvm_debug8_el3
4783  *
4784  * INTERNAL: AP Cavium Debug 8 Register
4785  *
4786  * This register is for diagnostic use only.
4787  */
4788 union bdk_ap_cvm_debug8_el3
4789 {
4790     uint64_t u;
4791     struct bdk_ap_cvm_debug8_el3_s
4792     {
4793 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4794         uint64_t rdb_dsc_set_arry_1    : 18; /**< [ 63: 46](RO) Bits 17..0 of rdb_dsc_set_arry[1]. */
4795         uint64_t rdb_dsc_set_arry_0    : 36; /**< [ 45: 10](RO) Rdb_dsc_set_arry[0]. */
4796         uint64_t uwr_ack_def_cnt       : 2;  /**< [  9:  8](RO) Upstream write message ack count. */
4797         uint64_t sgi_ack_def_cnt       : 2;  /**< [  7:  6](RO) SGI generate message ack count. */
4798         uint64_t dct_ack_def_cnt       : 2;  /**< [  5:  4](RO) Deactivate message ack count. */
4799         uint64_t act_ack_def_cnt       : 2;  /**< [  3:  2](RO) Activate message ack count. */
4800         uint64_t clr_ack_def_cnt       : 2;  /**< [  1:  0](RO) Clear message ack count. */
4801 #else /* Word 0 - Little Endian */
4802         uint64_t clr_ack_def_cnt       : 2;  /**< [  1:  0](RO) Clear message ack count. */
4803         uint64_t act_ack_def_cnt       : 2;  /**< [  3:  2](RO) Activate message ack count. */
4804         uint64_t dct_ack_def_cnt       : 2;  /**< [  5:  4](RO) Deactivate message ack count. */
4805         uint64_t sgi_ack_def_cnt       : 2;  /**< [  7:  6](RO) SGI generate message ack count. */
4806         uint64_t uwr_ack_def_cnt       : 2;  /**< [  9:  8](RO) Upstream write message ack count. */
4807         uint64_t rdb_dsc_set_arry_0    : 36; /**< [ 45: 10](RO) Rdb_dsc_set_arry[0]. */
4808         uint64_t rdb_dsc_set_arry_1    : 18; /**< [ 63: 46](RO) Bits 17..0 of rdb_dsc_set_arry[1]. */
4809 #endif /* Word 0 - End */
4810     } s;
4811     /* struct bdk_ap_cvm_debug8_el3_s cn; */
4812 };
4813 typedef union bdk_ap_cvm_debug8_el3 bdk_ap_cvm_debug8_el3_t;
4814 
4815 #define BDK_AP_CVM_DEBUG8_EL3 BDK_AP_CVM_DEBUG8_EL3_FUNC()
4816 static inline uint64_t BDK_AP_CVM_DEBUG8_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DEBUG8_EL3_FUNC(void)4817 static inline uint64_t BDK_AP_CVM_DEBUG8_EL3_FUNC(void)
4818 {
4819     return 0x3060b070000ll;
4820 }
4821 
4822 #define typedef_BDK_AP_CVM_DEBUG8_EL3 bdk_ap_cvm_debug8_el3_t
4823 #define bustype_BDK_AP_CVM_DEBUG8_EL3 BDK_CSR_TYPE_SYSREG
4824 #define basename_BDK_AP_CVM_DEBUG8_EL3 "AP_CVM_DEBUG8_EL3"
4825 #define busnum_BDK_AP_CVM_DEBUG8_EL3 0
4826 #define arguments_BDK_AP_CVM_DEBUG8_EL3 -1,-1,-1,-1
4827 
4828 /**
4829  * Register (SYSREG) ap_cvm_debug9_el3
4830  *
4831  * INTERNAL: AP Cavium Debug 9 Register
4832  *
4833  * This register is for diagnostic use only.
4834  */
4835 union bdk_ap_cvm_debug9_el3
4836 {
4837     uint64_t u;
4838     struct bdk_ap_cvm_debug9_el3_s
4839     {
4840 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4841         uint64_t reserved_48_63        : 16;
4842         uint64_t dsc_fsm_enc_state_1   : 4;  /**< [ 47: 44](RO) DSC FSM ENC state\<1\>. */
4843         uint64_t dsc_fsm_enc_state_0   : 4;  /**< [ 43: 40](RO) DSC FSM ENC state\<0\>. */
4844         uint64_t clr_fsm_enc_state     : 3;  /**< [ 39: 37](RO) CLR FSM ENC state. */
4845         uint64_t qsc_fsm_enc_state     : 3;  /**< [ 36: 34](RO) QSC FSM ENC state. */
4846         uint64_t dsc_fifo              : 4;  /**< [ 33: 30](RO) DSC FIFO. */
4847         uint64_t ppi_fifo              : 4;  /**< [ 29: 26](RO) PPI FIFO. */
4848         uint64_t cdc_fifo              : 4;  /**< [ 25: 22](RO) CDC FIFO. */
4849         uint64_t eac_fifo              : 4;  /**< [ 21: 18](RO) EAC FIFO. */
4850         uint64_t rdb_dsc_set_arry_1    : 18; /**< [ 17:  0](RO) rdb_dsc_set_arry[1]\<35:18\>. */
4851 #else /* Word 0 - Little Endian */
4852         uint64_t rdb_dsc_set_arry_1    : 18; /**< [ 17:  0](RO) rdb_dsc_set_arry[1]\<35:18\>. */
4853         uint64_t eac_fifo              : 4;  /**< [ 21: 18](RO) EAC FIFO. */
4854         uint64_t cdc_fifo              : 4;  /**< [ 25: 22](RO) CDC FIFO. */
4855         uint64_t ppi_fifo              : 4;  /**< [ 29: 26](RO) PPI FIFO. */
4856         uint64_t dsc_fifo              : 4;  /**< [ 33: 30](RO) DSC FIFO. */
4857         uint64_t qsc_fsm_enc_state     : 3;  /**< [ 36: 34](RO) QSC FSM ENC state. */
4858         uint64_t clr_fsm_enc_state     : 3;  /**< [ 39: 37](RO) CLR FSM ENC state. */
4859         uint64_t dsc_fsm_enc_state_0   : 4;  /**< [ 43: 40](RO) DSC FSM ENC state\<0\>. */
4860         uint64_t dsc_fsm_enc_state_1   : 4;  /**< [ 47: 44](RO) DSC FSM ENC state\<1\>. */
4861         uint64_t reserved_48_63        : 16;
4862 #endif /* Word 0 - End */
4863     } s;
4864     /* struct bdk_ap_cvm_debug9_el3_s cn; */
4865 };
4866 typedef union bdk_ap_cvm_debug9_el3 bdk_ap_cvm_debug9_el3_t;
4867 
4868 #define BDK_AP_CVM_DEBUG9_EL3 BDK_AP_CVM_DEBUG9_EL3_FUNC()
4869 static inline uint64_t BDK_AP_CVM_DEBUG9_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DEBUG9_EL3_FUNC(void)4870 static inline uint64_t BDK_AP_CVM_DEBUG9_EL3_FUNC(void)
4871 {
4872     return 0x3060b070100ll;
4873 }
4874 
4875 #define typedef_BDK_AP_CVM_DEBUG9_EL3 bdk_ap_cvm_debug9_el3_t
4876 #define bustype_BDK_AP_CVM_DEBUG9_EL3 BDK_CSR_TYPE_SYSREG
4877 #define basename_BDK_AP_CVM_DEBUG9_EL3 "AP_CVM_DEBUG9_EL3"
4878 #define busnum_BDK_AP_CVM_DEBUG9_EL3 0
4879 #define arguments_BDK_AP_CVM_DEBUG9_EL3 -1,-1,-1,-1
4880 
4881 /**
4882  * Register (SYSREG) ap_cvm_dll_observabilty_el3
4883  *
4884  * INTERNAL: AP Cavium DLL Observability Register
4885  */
4886 union bdk_ap_cvm_dll_observabilty_el3
4887 {
4888     uint64_t u;
4889     struct bdk_ap_cvm_dll_observabilty_el3_s
4890     {
4891 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4892         uint64_t reserved_60_63        : 4;
4893         uint64_t max_seen              : 12; /**< [ 59: 48](RO) Maximum setting seen. */
4894         uint64_t min_seen              : 12; /**< [ 47: 36](RO) Minimum setting seen. */
4895         uint64_t rclk_dll_lock         : 1;  /**< [ 35: 35](RO) rclk_dll__lock. */
4896         uint64_t dll_state             : 3;  /**< [ 34: 32](RO) dll_state\<2:0\>. */
4897         uint64_t dll_setting           : 12; /**< [ 31: 20](RO) dll_setting\<11:0\>. */
4898         uint64_t raw_dly_elem_enable   : 16; /**< [ 19:  4](RO) raw_dly_elem_enable\<15:0\>. */
4899         uint64_t clk_invert            : 1;  /**< [  3:  3](RO) clk_invert. */
4900         uint64_t pd_pos_rclk_refclk    : 1;  /**< [  2:  2](RO) pd_pos_rclk_refclk. */
4901         uint64_t pdl_rclk_refclk       : 1;  /**< [  1:  1](RO) pdl_rclk_refclk. */
4902         uint64_t pdr_rclk_refclk       : 1;  /**< [  0:  0](RO) pdr_rclk_refclk. */
4903 #else /* Word 0 - Little Endian */
4904         uint64_t pdr_rclk_refclk       : 1;  /**< [  0:  0](RO) pdr_rclk_refclk. */
4905         uint64_t pdl_rclk_refclk       : 1;  /**< [  1:  1](RO) pdl_rclk_refclk. */
4906         uint64_t pd_pos_rclk_refclk    : 1;  /**< [  2:  2](RO) pd_pos_rclk_refclk. */
4907         uint64_t clk_invert            : 1;  /**< [  3:  3](RO) clk_invert. */
4908         uint64_t raw_dly_elem_enable   : 16; /**< [ 19:  4](RO) raw_dly_elem_enable\<15:0\>. */
4909         uint64_t dll_setting           : 12; /**< [ 31: 20](RO) dll_setting\<11:0\>. */
4910         uint64_t dll_state             : 3;  /**< [ 34: 32](RO) dll_state\<2:0\>. */
4911         uint64_t rclk_dll_lock         : 1;  /**< [ 35: 35](RO) rclk_dll__lock. */
4912         uint64_t min_seen              : 12; /**< [ 47: 36](RO) Minimum setting seen. */
4913         uint64_t max_seen              : 12; /**< [ 59: 48](RO) Maximum setting seen. */
4914         uint64_t reserved_60_63        : 4;
4915 #endif /* Word 0 - End */
4916     } s;
4917     /* struct bdk_ap_cvm_dll_observabilty_el3_s cn; */
4918 };
4919 typedef union bdk_ap_cvm_dll_observabilty_el3 bdk_ap_cvm_dll_observabilty_el3_t;
4920 
4921 #define BDK_AP_CVM_DLL_OBSERVABILTY_EL3 BDK_AP_CVM_DLL_OBSERVABILTY_EL3_FUNC()
4922 static inline uint64_t BDK_AP_CVM_DLL_OBSERVABILTY_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_DLL_OBSERVABILTY_EL3_FUNC(void)4923 static inline uint64_t BDK_AP_CVM_DLL_OBSERVABILTY_EL3_FUNC(void)
4924 {
4925     return 0x3060b050100ll;
4926 }
4927 
4928 #define typedef_BDK_AP_CVM_DLL_OBSERVABILTY_EL3 bdk_ap_cvm_dll_observabilty_el3_t
4929 #define bustype_BDK_AP_CVM_DLL_OBSERVABILTY_EL3 BDK_CSR_TYPE_SYSREG
4930 #define basename_BDK_AP_CVM_DLL_OBSERVABILTY_EL3 "AP_CVM_DLL_OBSERVABILTY_EL3"
4931 #define busnum_BDK_AP_CVM_DLL_OBSERVABILTY_EL3 0
4932 #define arguments_BDK_AP_CVM_DLL_OBSERVABILTY_EL3 -1,-1,-1,-1
4933 
4934 /**
4935  * Register (SYSREG) ap_cvm_erricache_el1
4936  *
4937  * AP Cavium Error Icache Register
4938  */
4939 union bdk_ap_cvm_erricache_el1
4940 {
4941     uint64_t u;
4942     struct bdk_ap_cvm_erricache_el1_s
4943     {
4944 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4945         uint64_t reserved_17_63        : 47;
4946         uint64_t set                   : 6;  /**< [ 16: 11](R/W) Set which had the parity error. */
4947         uint64_t va                    : 8;  /**< [ 10:  3](R/W) VA\<10:3\> of address which had the parity error. */
4948         uint64_t reserved_1_2          : 2;
4949         uint64_t icache_data_error     : 1;  /**< [  0:  0](R/W) Icache corrected a data error. */
4950 #else /* Word 0 - Little Endian */
4951         uint64_t icache_data_error     : 1;  /**< [  0:  0](R/W) Icache corrected a data error. */
4952         uint64_t reserved_1_2          : 2;
4953         uint64_t va                    : 8;  /**< [ 10:  3](R/W) VA\<10:3\> of address which had the parity error. */
4954         uint64_t set                   : 6;  /**< [ 16: 11](R/W) Set which had the parity error. */
4955         uint64_t reserved_17_63        : 47;
4956 #endif /* Word 0 - End */
4957     } s;
4958     /* struct bdk_ap_cvm_erricache_el1_s cn; */
4959 };
4960 typedef union bdk_ap_cvm_erricache_el1 bdk_ap_cvm_erricache_el1_t;
4961 
4962 #define BDK_AP_CVM_ERRICACHE_EL1 BDK_AP_CVM_ERRICACHE_EL1_FUNC()
4963 static inline uint64_t BDK_AP_CVM_ERRICACHE_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_ERRICACHE_EL1_FUNC(void)4964 static inline uint64_t BDK_AP_CVM_ERRICACHE_EL1_FUNC(void)
4965 {
4966     return 0x3000b020000ll;
4967 }
4968 
4969 #define typedef_BDK_AP_CVM_ERRICACHE_EL1 bdk_ap_cvm_erricache_el1_t
4970 #define bustype_BDK_AP_CVM_ERRICACHE_EL1 BDK_CSR_TYPE_SYSREG
4971 #define basename_BDK_AP_CVM_ERRICACHE_EL1 "AP_CVM_ERRICACHE_EL1"
4972 #define busnum_BDK_AP_CVM_ERRICACHE_EL1 0
4973 #define arguments_BDK_AP_CVM_ERRICACHE_EL1 -1,-1,-1,-1
4974 
4975 /**
4976  * Register (SYSREG) ap_cvm_errmem_el1
4977  *
4978  * AP Cavium Error Memory Register
4979  */
4980 union bdk_ap_cvm_errmem_el1
4981 {
4982     uint64_t u;
4983     struct bdk_ap_cvm_errmem_el1_s
4984     {
4985 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4986         uint64_t reserved_49_63        : 15;
4987         uint64_t wbfsbeerr             : 1;  /**< [ 48: 48](RO) Reserved. */
4988         uint64_t gsynctonosw           : 1;  /**< [ 47: 47](R/W) Global sync timeout, no report to software. */
4989         uint64_t gsynctodis            : 1;  /**< [ 46: 46](R/W) Global sync timeout disable. */
4990         uint64_t gsyncto               : 1;  /**< [ 45: 45](R/W/H) Global sync timeout. */
4991         uint64_t wcumultdis            : 1;  /**< [ 44: 44](R/W) WCU multiple match error disable. */
4992         uint64_t wcumult               : 1;  /**< [ 43: 43](R/W/H) WCU multiple match error. */
4993         uint64_t mtlbmultdis           : 1;  /**< [ 42: 42](R/W) MTLB multiple match error disable. */
4994         uint64_t mtlbmult              : 1;  /**< [ 41: 41](R/W/H) MTLB multiple match error. */
4995         uint64_t reserved_40           : 1;
4996         uint64_t barriertonosw         : 1;  /**< [ 39: 39](R/W) Barrier timeout, no report to software. */
4997         uint64_t barriertodis          : 1;  /**< [ 38: 38](R/W) Barrier timeout disable. */
4998         uint64_t barrierto             : 1;  /**< [ 37: 37](R/W/H) Barrier timeout. */
4999         uint64_t reserved_36           : 1;
5000         uint64_t rbftonosw             : 1;  /**< [ 35: 35](R/W) Read buffer timeout, no report to software. */
5001         uint64_t rbftodis              : 1;  /**< [ 34: 34](R/W) Read buffer timeout disable. */
5002         uint64_t rbfto                 : 1;  /**< [ 33: 33](R/W/H) Read buffer timeout. */
5003         uint64_t wcuperrforce          : 1;  /**< [ 32: 32](R/W/H) WCU parity error force. Bit is cleared when error is forced on next write operation. */
5004         uint64_t wcuperrnosw           : 1;  /**< [ 31: 31](R/W) WCU parity error, no report to software. */
5005         uint64_t wcuperrdis            : 1;  /**< [ 30: 30](R/W) WCU parity error disable. */
5006         uint64_t wcuperr               : 1;  /**< [ 29: 29](R/W/H) WCU corrected parity error. */
5007         uint64_t wbfdbeforce           : 1;  /**< [ 28: 28](R/W/H) Write-buffer DBE force. Bit is cleared when error is forced on next write operation. */
5008         uint64_t wbfsbeforce           : 1;  /**< [ 27: 27](R/W/H) Write-buffer SBE force. Bit is cleared when error is forced on next write operation. */
5009         uint64_t wbfperrnosw           : 1;  /**< [ 26: 26](R/W) Write-buffer single-bit error, no report to software. */
5010         uint64_t wbfperrdis            : 1;  /**< [ 25: 25](R/W) Write-buffer double-bit error disable. */
5011         uint64_t wbfperr               : 1;  /**< [ 24: 24](R/W/H) Write-buffer double-bit error. */
5012         uint64_t mafperrforce          : 1;  /**< [ 23: 23](R/W/H) MAF parity error force. Bit is cleared when error is forced on next write operation. */
5013         uint64_t mafperrnosw           : 1;  /**< [ 22: 22](R/W) MAF parity error, no report to software. */
5014         uint64_t mafperrdis            : 1;  /**< [ 21: 21](R/W) MAF parity error disable. */
5015         uint64_t mafperr               : 1;  /**< [ 20: 20](R/W/H) MAF parity error. */
5016         uint64_t utlbperrforce         : 1;  /**< [ 19: 19](R/W/H) uTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5017         uint64_t utlbperrnosw          : 1;  /**< [ 18: 18](R/W) uTLB correctable parity error, no report to software. */
5018         uint64_t utlbperrdis           : 1;  /**< [ 17: 17](R/W) uTLB correctable parity error disable. */
5019         uint64_t utlbperr              : 1;  /**< [ 16: 16](R/W/H) uTLB corrected a parity error. */
5020         uint64_t mtlbperrforce         : 1;  /**< [ 15: 15](R/W/H) MTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5021         uint64_t mtlbperrnosw          : 1;  /**< [ 14: 14](R/W) MTLB correctable parity error, no report to software. */
5022         uint64_t mtlbperrdis           : 1;  /**< [ 13: 13](R/W) MTLB correctable parity error disable. */
5023         uint64_t mtlbperr              : 1;  /**< [ 12: 12](R/W/H) MTLB corrected a parity error. */
5024         uint64_t l1dperrforce          : 1;  /**< [ 11: 11](R/W/H) Dcache correctable parity error force. Bit is cleared when error is forced on next write operation. */
5025         uint64_t l1dperrnosw           : 1;  /**< [ 10: 10](R/W) Dcache correctable parity error, no report to software. */
5026         uint64_t l1dperrdis            : 1;  /**< [  9:  9](R/W) Dcache correctable parity error disable. */
5027         uint64_t l1dperr               : 1;  /**< [  8:  8](R/W/H) Dcache corrected a parity error. */
5028         uint64_t l1dway                : 5;  /**< [  7:  3](R/W/H) Indicates Dcache way. */
5029         uint64_t l1dset                : 3;  /**< [  2:  0](R/W/H) Indicates Dcache set. */
5030 #else /* Word 0 - Little Endian */
5031         uint64_t l1dset                : 3;  /**< [  2:  0](R/W/H) Indicates Dcache set. */
5032         uint64_t l1dway                : 5;  /**< [  7:  3](R/W/H) Indicates Dcache way. */
5033         uint64_t l1dperr               : 1;  /**< [  8:  8](R/W/H) Dcache corrected a parity error. */
5034         uint64_t l1dperrdis            : 1;  /**< [  9:  9](R/W) Dcache correctable parity error disable. */
5035         uint64_t l1dperrnosw           : 1;  /**< [ 10: 10](R/W) Dcache correctable parity error, no report to software. */
5036         uint64_t l1dperrforce          : 1;  /**< [ 11: 11](R/W/H) Dcache correctable parity error force. Bit is cleared when error is forced on next write operation. */
5037         uint64_t mtlbperr              : 1;  /**< [ 12: 12](R/W/H) MTLB corrected a parity error. */
5038         uint64_t mtlbperrdis           : 1;  /**< [ 13: 13](R/W) MTLB correctable parity error disable. */
5039         uint64_t mtlbperrnosw          : 1;  /**< [ 14: 14](R/W) MTLB correctable parity error, no report to software. */
5040         uint64_t mtlbperrforce         : 1;  /**< [ 15: 15](R/W/H) MTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5041         uint64_t utlbperr              : 1;  /**< [ 16: 16](R/W/H) uTLB corrected a parity error. */
5042         uint64_t utlbperrdis           : 1;  /**< [ 17: 17](R/W) uTLB correctable parity error disable. */
5043         uint64_t utlbperrnosw          : 1;  /**< [ 18: 18](R/W) uTLB correctable parity error, no report to software. */
5044         uint64_t utlbperrforce         : 1;  /**< [ 19: 19](R/W/H) uTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5045         uint64_t mafperr               : 1;  /**< [ 20: 20](R/W/H) MAF parity error. */
5046         uint64_t mafperrdis            : 1;  /**< [ 21: 21](R/W) MAF parity error disable. */
5047         uint64_t mafperrnosw           : 1;  /**< [ 22: 22](R/W) MAF parity error, no report to software. */
5048         uint64_t mafperrforce          : 1;  /**< [ 23: 23](R/W/H) MAF parity error force. Bit is cleared when error is forced on next write operation. */
5049         uint64_t wbfperr               : 1;  /**< [ 24: 24](R/W/H) Write-buffer double-bit error. */
5050         uint64_t wbfperrdis            : 1;  /**< [ 25: 25](R/W) Write-buffer double-bit error disable. */
5051         uint64_t wbfperrnosw           : 1;  /**< [ 26: 26](R/W) Write-buffer single-bit error, no report to software. */
5052         uint64_t wbfsbeforce           : 1;  /**< [ 27: 27](R/W/H) Write-buffer SBE force. Bit is cleared when error is forced on next write operation. */
5053         uint64_t wbfdbeforce           : 1;  /**< [ 28: 28](R/W/H) Write-buffer DBE force. Bit is cleared when error is forced on next write operation. */
5054         uint64_t wcuperr               : 1;  /**< [ 29: 29](R/W/H) WCU corrected parity error. */
5055         uint64_t wcuperrdis            : 1;  /**< [ 30: 30](R/W) WCU parity error disable. */
5056         uint64_t wcuperrnosw           : 1;  /**< [ 31: 31](R/W) WCU parity error, no report to software. */
5057         uint64_t wcuperrforce          : 1;  /**< [ 32: 32](R/W/H) WCU parity error force. Bit is cleared when error is forced on next write operation. */
5058         uint64_t rbfto                 : 1;  /**< [ 33: 33](R/W/H) Read buffer timeout. */
5059         uint64_t rbftodis              : 1;  /**< [ 34: 34](R/W) Read buffer timeout disable. */
5060         uint64_t rbftonosw             : 1;  /**< [ 35: 35](R/W) Read buffer timeout, no report to software. */
5061         uint64_t reserved_36           : 1;
5062         uint64_t barrierto             : 1;  /**< [ 37: 37](R/W/H) Barrier timeout. */
5063         uint64_t barriertodis          : 1;  /**< [ 38: 38](R/W) Barrier timeout disable. */
5064         uint64_t barriertonosw         : 1;  /**< [ 39: 39](R/W) Barrier timeout, no report to software. */
5065         uint64_t reserved_40           : 1;
5066         uint64_t mtlbmult              : 1;  /**< [ 41: 41](R/W/H) MTLB multiple match error. */
5067         uint64_t mtlbmultdis           : 1;  /**< [ 42: 42](R/W) MTLB multiple match error disable. */
5068         uint64_t wcumult               : 1;  /**< [ 43: 43](R/W/H) WCU multiple match error. */
5069         uint64_t wcumultdis            : 1;  /**< [ 44: 44](R/W) WCU multiple match error disable. */
5070         uint64_t gsyncto               : 1;  /**< [ 45: 45](R/W/H) Global sync timeout. */
5071         uint64_t gsynctodis            : 1;  /**< [ 46: 46](R/W) Global sync timeout disable. */
5072         uint64_t gsynctonosw           : 1;  /**< [ 47: 47](R/W) Global sync timeout, no report to software. */
5073         uint64_t wbfsbeerr             : 1;  /**< [ 48: 48](RO) Reserved. */
5074         uint64_t reserved_49_63        : 15;
5075 #endif /* Word 0 - End */
5076     } s;
5077     struct bdk_ap_cvm_errmem_el1_cn88xxp1
5078     {
5079 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5080         uint64_t reserved_49_63        : 15;
5081         uint64_t wbfsbeerr             : 1;  /**< [ 48: 48](RO) Reserved. */
5082         uint64_t gsynctonosw           : 1;  /**< [ 47: 47](R/W) Global sync timeout, no report to software. */
5083         uint64_t gsynctodis            : 1;  /**< [ 46: 46](R/W) Global sync timeout disable. */
5084         uint64_t gsyncto               : 1;  /**< [ 45: 45](R/W/H) Global sync timeout. */
5085         uint64_t wcumultdis            : 1;  /**< [ 44: 44](R/W) WCU multiple match error disable. */
5086         uint64_t wcumult               : 1;  /**< [ 43: 43](R/W/H) WCU multiple match error. */
5087         uint64_t mtlbmultdis           : 1;  /**< [ 42: 42](R/W) MTLB multiple match error disable. */
5088         uint64_t mtlbmult              : 1;  /**< [ 41: 41](R/W/H) MTLB multiple match error. */
5089         uint64_t barriertoforce        : 1;  /**< [ 40: 40](R/W/H) Barrier timeout force. Bit is cleared when error is forced. */
5090         uint64_t barriertonosw         : 1;  /**< [ 39: 39](R/W) Barrier timeout, no report to software. */
5091         uint64_t barriertodis          : 1;  /**< [ 38: 38](R/W) Barrier timeout disable. */
5092         uint64_t barrierto             : 1;  /**< [ 37: 37](R/W/H) Barrier timeout. */
5093         uint64_t rbftoforce            : 1;  /**< [ 36: 36](R/W/H) Read buffer timeout force. Bit is cleared when error is forced. */
5094         uint64_t rbftonosw             : 1;  /**< [ 35: 35](R/W) Read buffer timeout, no report to software. */
5095         uint64_t rbftodis              : 1;  /**< [ 34: 34](R/W) Read buffer timeout disable. */
5096         uint64_t rbfto                 : 1;  /**< [ 33: 33](R/W/H) Read buffer timeout. */
5097         uint64_t wcuperrforce          : 1;  /**< [ 32: 32](R/W/H) WCU parity error force. Bit is cleared when error is forced on next write operation. */
5098         uint64_t wcuperrnosw           : 1;  /**< [ 31: 31](R/W) WCU parity error, no report to software. */
5099         uint64_t wcuperrdis            : 1;  /**< [ 30: 30](R/W) WCU parity error disable. */
5100         uint64_t wcuperr               : 1;  /**< [ 29: 29](R/W/H) WCU corrected parity error. */
5101         uint64_t wbfdbeforce           : 1;  /**< [ 28: 28](R/W/H) Write-buffer DBE force. Bit is cleared when error is forced on next write operation. */
5102         uint64_t wbfsbeforce           : 1;  /**< [ 27: 27](R/W/H) Write-buffer SBE force. Bit is cleared when error is forced on next write operation. */
5103         uint64_t wbfperrnosw           : 1;  /**< [ 26: 26](R/W) Write-buffer single-bit error, no report to software. */
5104         uint64_t wbfperrdis            : 1;  /**< [ 25: 25](R/W) Write-buffer double-bit error disable. */
5105         uint64_t wbfperr               : 1;  /**< [ 24: 24](R/W/H) Write-buffer double-bit error. */
5106         uint64_t mafperrforce          : 1;  /**< [ 23: 23](R/W/H) MAF parity error force. Bit is cleared when error is forced on next write operation. */
5107         uint64_t mafperrnosw           : 1;  /**< [ 22: 22](R/W) MAF parity error, no report to software. */
5108         uint64_t mafperrdis            : 1;  /**< [ 21: 21](R/W) MAF parity error disable. */
5109         uint64_t mafperr               : 1;  /**< [ 20: 20](R/W/H) MAF parity error. */
5110         uint64_t utlbperrforce         : 1;  /**< [ 19: 19](R/W/H) uTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5111         uint64_t utlbperrnosw          : 1;  /**< [ 18: 18](R/W) uTLB correctable parity error, no report to software. */
5112         uint64_t utlbperrdis           : 1;  /**< [ 17: 17](R/W) uTLB correctable parity error disable. */
5113         uint64_t utlbperr              : 1;  /**< [ 16: 16](R/W/H) uTLB corrected a parity error. */
5114         uint64_t mtlbperrforce         : 1;  /**< [ 15: 15](R/W/H) MTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5115         uint64_t mtlbperrnosw          : 1;  /**< [ 14: 14](R/W) MTLB correctable parity error, no report to software. */
5116         uint64_t mtlbperrdis           : 1;  /**< [ 13: 13](R/W) MTLB correctable parity error disable. */
5117         uint64_t mtlbperr              : 1;  /**< [ 12: 12](R/W/H) MTLB corrected a parity error. */
5118         uint64_t l1dperrforce          : 1;  /**< [ 11: 11](R/W/H) Dcache correctable parity error force. Bit is cleared when error is forced on next write operation. */
5119         uint64_t l1dperrnosw           : 1;  /**< [ 10: 10](R/W) Dcache correctable parity error, no report to software. */
5120         uint64_t l1dperrdis            : 1;  /**< [  9:  9](R/W) Dcache correctable parity error disable. */
5121         uint64_t l1dperr               : 1;  /**< [  8:  8](R/W/H) Dcache corrected a parity error. */
5122         uint64_t l1dway                : 5;  /**< [  7:  3](R/W/H) Indicates Dcache way. */
5123         uint64_t l1dset                : 3;  /**< [  2:  0](R/W/H) Indicates Dcache set. */
5124 #else /* Word 0 - Little Endian */
5125         uint64_t l1dset                : 3;  /**< [  2:  0](R/W/H) Indicates Dcache set. */
5126         uint64_t l1dway                : 5;  /**< [  7:  3](R/W/H) Indicates Dcache way. */
5127         uint64_t l1dperr               : 1;  /**< [  8:  8](R/W/H) Dcache corrected a parity error. */
5128         uint64_t l1dperrdis            : 1;  /**< [  9:  9](R/W) Dcache correctable parity error disable. */
5129         uint64_t l1dperrnosw           : 1;  /**< [ 10: 10](R/W) Dcache correctable parity error, no report to software. */
5130         uint64_t l1dperrforce          : 1;  /**< [ 11: 11](R/W/H) Dcache correctable parity error force. Bit is cleared when error is forced on next write operation. */
5131         uint64_t mtlbperr              : 1;  /**< [ 12: 12](R/W/H) MTLB corrected a parity error. */
5132         uint64_t mtlbperrdis           : 1;  /**< [ 13: 13](R/W) MTLB correctable parity error disable. */
5133         uint64_t mtlbperrnosw          : 1;  /**< [ 14: 14](R/W) MTLB correctable parity error, no report to software. */
5134         uint64_t mtlbperrforce         : 1;  /**< [ 15: 15](R/W/H) MTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5135         uint64_t utlbperr              : 1;  /**< [ 16: 16](R/W/H) uTLB corrected a parity error. */
5136         uint64_t utlbperrdis           : 1;  /**< [ 17: 17](R/W) uTLB correctable parity error disable. */
5137         uint64_t utlbperrnosw          : 1;  /**< [ 18: 18](R/W) uTLB correctable parity error, no report to software. */
5138         uint64_t utlbperrforce         : 1;  /**< [ 19: 19](R/W/H) uTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5139         uint64_t mafperr               : 1;  /**< [ 20: 20](R/W/H) MAF parity error. */
5140         uint64_t mafperrdis            : 1;  /**< [ 21: 21](R/W) MAF parity error disable. */
5141         uint64_t mafperrnosw           : 1;  /**< [ 22: 22](R/W) MAF parity error, no report to software. */
5142         uint64_t mafperrforce          : 1;  /**< [ 23: 23](R/W/H) MAF parity error force. Bit is cleared when error is forced on next write operation. */
5143         uint64_t wbfperr               : 1;  /**< [ 24: 24](R/W/H) Write-buffer double-bit error. */
5144         uint64_t wbfperrdis            : 1;  /**< [ 25: 25](R/W) Write-buffer double-bit error disable. */
5145         uint64_t wbfperrnosw           : 1;  /**< [ 26: 26](R/W) Write-buffer single-bit error, no report to software. */
5146         uint64_t wbfsbeforce           : 1;  /**< [ 27: 27](R/W/H) Write-buffer SBE force. Bit is cleared when error is forced on next write operation. */
5147         uint64_t wbfdbeforce           : 1;  /**< [ 28: 28](R/W/H) Write-buffer DBE force. Bit is cleared when error is forced on next write operation. */
5148         uint64_t wcuperr               : 1;  /**< [ 29: 29](R/W/H) WCU corrected parity error. */
5149         uint64_t wcuperrdis            : 1;  /**< [ 30: 30](R/W) WCU parity error disable. */
5150         uint64_t wcuperrnosw           : 1;  /**< [ 31: 31](R/W) WCU parity error, no report to software. */
5151         uint64_t wcuperrforce          : 1;  /**< [ 32: 32](R/W/H) WCU parity error force. Bit is cleared when error is forced on next write operation. */
5152         uint64_t rbfto                 : 1;  /**< [ 33: 33](R/W/H) Read buffer timeout. */
5153         uint64_t rbftodis              : 1;  /**< [ 34: 34](R/W) Read buffer timeout disable. */
5154         uint64_t rbftonosw             : 1;  /**< [ 35: 35](R/W) Read buffer timeout, no report to software. */
5155         uint64_t rbftoforce            : 1;  /**< [ 36: 36](R/W/H) Read buffer timeout force. Bit is cleared when error is forced. */
5156         uint64_t barrierto             : 1;  /**< [ 37: 37](R/W/H) Barrier timeout. */
5157         uint64_t barriertodis          : 1;  /**< [ 38: 38](R/W) Barrier timeout disable. */
5158         uint64_t barriertonosw         : 1;  /**< [ 39: 39](R/W) Barrier timeout, no report to software. */
5159         uint64_t barriertoforce        : 1;  /**< [ 40: 40](R/W/H) Barrier timeout force. Bit is cleared when error is forced. */
5160         uint64_t mtlbmult              : 1;  /**< [ 41: 41](R/W/H) MTLB multiple match error. */
5161         uint64_t mtlbmultdis           : 1;  /**< [ 42: 42](R/W) MTLB multiple match error disable. */
5162         uint64_t wcumult               : 1;  /**< [ 43: 43](R/W/H) WCU multiple match error. */
5163         uint64_t wcumultdis            : 1;  /**< [ 44: 44](R/W) WCU multiple match error disable. */
5164         uint64_t gsyncto               : 1;  /**< [ 45: 45](R/W/H) Global sync timeout. */
5165         uint64_t gsynctodis            : 1;  /**< [ 46: 46](R/W) Global sync timeout disable. */
5166         uint64_t gsynctonosw           : 1;  /**< [ 47: 47](R/W) Global sync timeout, no report to software. */
5167         uint64_t wbfsbeerr             : 1;  /**< [ 48: 48](RO) Reserved. */
5168         uint64_t reserved_49_63        : 15;
5169 #endif /* Word 0 - End */
5170     } cn88xxp1;
5171     struct bdk_ap_cvm_errmem_el1_cn9
5172     {
5173 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5174         uint64_t reserved_49_63        : 15;
5175         uint64_t reserved_0_48         : 49;
5176 #else /* Word 0 - Little Endian */
5177         uint64_t reserved_0_48         : 49;
5178         uint64_t reserved_49_63        : 15;
5179 #endif /* Word 0 - End */
5180     } cn9;
5181     struct bdk_ap_cvm_errmem_el1_cn81xx
5182     {
5183 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5184         uint64_t reserved_49_63        : 15;
5185         uint64_t wbfsbeerr             : 1;  /**< [ 48: 48](RO) Reserved. */
5186         uint64_t gsynctonosw           : 1;  /**< [ 47: 47](R/W) Global sync timeout, no report to software. */
5187         uint64_t gsynctodis            : 1;  /**< [ 46: 46](R/W) Global sync timeout disable. */
5188         uint64_t gsyncto               : 1;  /**< [ 45: 45](R/W/H) Global sync timeout. */
5189         uint64_t wcumultdis            : 1;  /**< [ 44: 44](R/W) WCU multiple match error disable. */
5190         uint64_t wcumult               : 1;  /**< [ 43: 43](R/W/H) WCU multiple match error. */
5191         uint64_t mtlbmultdis           : 1;  /**< [ 42: 42](R/W) MTLB multiple match error disable. */
5192         uint64_t mtlbmult              : 1;  /**< [ 41: 41](R/W/H) MTLB multiple match error. */
5193         uint64_t spare40               : 1;  /**< [ 40: 40](R/W/H) Reserved. */
5194         uint64_t barriertonosw         : 1;  /**< [ 39: 39](R/W) Barrier timeout, no report to software. */
5195         uint64_t barriertodis          : 1;  /**< [ 38: 38](R/W) Barrier timeout disable. */
5196         uint64_t barrierto             : 1;  /**< [ 37: 37](R/W/H) Barrier timeout. */
5197         uint64_t spare36               : 1;  /**< [ 36: 36](R/W/H) Reserved. */
5198         uint64_t rbftonosw             : 1;  /**< [ 35: 35](R/W) Read buffer timeout, no report to software. */
5199         uint64_t rbftodis              : 1;  /**< [ 34: 34](R/W) Read buffer timeout disable. */
5200         uint64_t rbfto                 : 1;  /**< [ 33: 33](R/W/H) Read buffer timeout. */
5201         uint64_t wcuperrforce          : 1;  /**< [ 32: 32](R/W/H) WCU parity error force. Bit is cleared when error is forced on next write operation. */
5202         uint64_t wcuperrnosw           : 1;  /**< [ 31: 31](R/W) WCU parity error, no report to software. */
5203         uint64_t wcuperrdis            : 1;  /**< [ 30: 30](R/W) WCU parity error disable. */
5204         uint64_t wcuperr               : 1;  /**< [ 29: 29](R/W/H) WCU corrected parity error. */
5205         uint64_t wbfdbeforce           : 1;  /**< [ 28: 28](R/W/H) Write-buffer DBE force. Bit is cleared when error is forced on next write operation. */
5206         uint64_t wbfsbeforce           : 1;  /**< [ 27: 27](R/W/H) Write-buffer SBE force. Bit is cleared when error is forced on next write operation. */
5207         uint64_t wbfperrnosw           : 1;  /**< [ 26: 26](R/W) Write-buffer single-bit error, no report to software. */
5208         uint64_t wbfperrdis            : 1;  /**< [ 25: 25](R/W) Write-buffer double-bit error disable. */
5209         uint64_t wbfperr               : 1;  /**< [ 24: 24](R/W/H) Write-buffer double-bit error. */
5210         uint64_t mafperrforce          : 1;  /**< [ 23: 23](R/W/H) MAF parity error force. Bit is cleared when error is forced on next write operation. */
5211         uint64_t mafperrnosw           : 1;  /**< [ 22: 22](R/W) MAF parity error, no report to software. */
5212         uint64_t mafperrdis            : 1;  /**< [ 21: 21](R/W) MAF parity error disable. */
5213         uint64_t mafperr               : 1;  /**< [ 20: 20](R/W/H) MAF parity error. */
5214         uint64_t utlbperrforce         : 1;  /**< [ 19: 19](R/W/H) uTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5215         uint64_t utlbperrnosw          : 1;  /**< [ 18: 18](R/W) uTLB correctable parity error, no report to software. */
5216         uint64_t utlbperrdis           : 1;  /**< [ 17: 17](R/W) uTLB correctable parity error disable. */
5217         uint64_t utlbperr              : 1;  /**< [ 16: 16](R/W/H) uTLB corrected a parity error. */
5218         uint64_t mtlbperrforce         : 1;  /**< [ 15: 15](R/W/H) MTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5219         uint64_t mtlbperrnosw          : 1;  /**< [ 14: 14](R/W) MTLB correctable parity error, no report to software. */
5220         uint64_t mtlbperrdis           : 1;  /**< [ 13: 13](R/W) MTLB correctable parity error disable. */
5221         uint64_t mtlbperr              : 1;  /**< [ 12: 12](R/W/H) MTLB corrected a parity error. */
5222         uint64_t l1dperrforce          : 1;  /**< [ 11: 11](R/W/H) Dcache correctable parity error force. Bit is cleared when error is forced on next write operation. */
5223         uint64_t l1dperrnosw           : 1;  /**< [ 10: 10](R/W) Dcache correctable parity error, no report to software. */
5224         uint64_t l1dperrdis            : 1;  /**< [  9:  9](R/W) Dcache correctable parity error disable. */
5225         uint64_t l1dperr               : 1;  /**< [  8:  8](R/W/H) Dcache corrected a parity error. */
5226         uint64_t l1dway                : 5;  /**< [  7:  3](R/W/H) Indicates Dcache way. */
5227         uint64_t l1dset                : 3;  /**< [  2:  0](R/W/H) Indicates Dcache set. */
5228 #else /* Word 0 - Little Endian */
5229         uint64_t l1dset                : 3;  /**< [  2:  0](R/W/H) Indicates Dcache set. */
5230         uint64_t l1dway                : 5;  /**< [  7:  3](R/W/H) Indicates Dcache way. */
5231         uint64_t l1dperr               : 1;  /**< [  8:  8](R/W/H) Dcache corrected a parity error. */
5232         uint64_t l1dperrdis            : 1;  /**< [  9:  9](R/W) Dcache correctable parity error disable. */
5233         uint64_t l1dperrnosw           : 1;  /**< [ 10: 10](R/W) Dcache correctable parity error, no report to software. */
5234         uint64_t l1dperrforce          : 1;  /**< [ 11: 11](R/W/H) Dcache correctable parity error force. Bit is cleared when error is forced on next write operation. */
5235         uint64_t mtlbperr              : 1;  /**< [ 12: 12](R/W/H) MTLB corrected a parity error. */
5236         uint64_t mtlbperrdis           : 1;  /**< [ 13: 13](R/W) MTLB correctable parity error disable. */
5237         uint64_t mtlbperrnosw          : 1;  /**< [ 14: 14](R/W) MTLB correctable parity error, no report to software. */
5238         uint64_t mtlbperrforce         : 1;  /**< [ 15: 15](R/W/H) MTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5239         uint64_t utlbperr              : 1;  /**< [ 16: 16](R/W/H) uTLB corrected a parity error. */
5240         uint64_t utlbperrdis           : 1;  /**< [ 17: 17](R/W) uTLB correctable parity error disable. */
5241         uint64_t utlbperrnosw          : 1;  /**< [ 18: 18](R/W) uTLB correctable parity error, no report to software. */
5242         uint64_t utlbperrforce         : 1;  /**< [ 19: 19](R/W/H) uTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5243         uint64_t mafperr               : 1;  /**< [ 20: 20](R/W/H) MAF parity error. */
5244         uint64_t mafperrdis            : 1;  /**< [ 21: 21](R/W) MAF parity error disable. */
5245         uint64_t mafperrnosw           : 1;  /**< [ 22: 22](R/W) MAF parity error, no report to software. */
5246         uint64_t mafperrforce          : 1;  /**< [ 23: 23](R/W/H) MAF parity error force. Bit is cleared when error is forced on next write operation. */
5247         uint64_t wbfperr               : 1;  /**< [ 24: 24](R/W/H) Write-buffer double-bit error. */
5248         uint64_t wbfperrdis            : 1;  /**< [ 25: 25](R/W) Write-buffer double-bit error disable. */
5249         uint64_t wbfperrnosw           : 1;  /**< [ 26: 26](R/W) Write-buffer single-bit error, no report to software. */
5250         uint64_t wbfsbeforce           : 1;  /**< [ 27: 27](R/W/H) Write-buffer SBE force. Bit is cleared when error is forced on next write operation. */
5251         uint64_t wbfdbeforce           : 1;  /**< [ 28: 28](R/W/H) Write-buffer DBE force. Bit is cleared when error is forced on next write operation. */
5252         uint64_t wcuperr               : 1;  /**< [ 29: 29](R/W/H) WCU corrected parity error. */
5253         uint64_t wcuperrdis            : 1;  /**< [ 30: 30](R/W) WCU parity error disable. */
5254         uint64_t wcuperrnosw           : 1;  /**< [ 31: 31](R/W) WCU parity error, no report to software. */
5255         uint64_t wcuperrforce          : 1;  /**< [ 32: 32](R/W/H) WCU parity error force. Bit is cleared when error is forced on next write operation. */
5256         uint64_t rbfto                 : 1;  /**< [ 33: 33](R/W/H) Read buffer timeout. */
5257         uint64_t rbftodis              : 1;  /**< [ 34: 34](R/W) Read buffer timeout disable. */
5258         uint64_t rbftonosw             : 1;  /**< [ 35: 35](R/W) Read buffer timeout, no report to software. */
5259         uint64_t spare36               : 1;  /**< [ 36: 36](R/W/H) Reserved. */
5260         uint64_t barrierto             : 1;  /**< [ 37: 37](R/W/H) Barrier timeout. */
5261         uint64_t barriertodis          : 1;  /**< [ 38: 38](R/W) Barrier timeout disable. */
5262         uint64_t barriertonosw         : 1;  /**< [ 39: 39](R/W) Barrier timeout, no report to software. */
5263         uint64_t spare40               : 1;  /**< [ 40: 40](R/W/H) Reserved. */
5264         uint64_t mtlbmult              : 1;  /**< [ 41: 41](R/W/H) MTLB multiple match error. */
5265         uint64_t mtlbmultdis           : 1;  /**< [ 42: 42](R/W) MTLB multiple match error disable. */
5266         uint64_t wcumult               : 1;  /**< [ 43: 43](R/W/H) WCU multiple match error. */
5267         uint64_t wcumultdis            : 1;  /**< [ 44: 44](R/W) WCU multiple match error disable. */
5268         uint64_t gsyncto               : 1;  /**< [ 45: 45](R/W/H) Global sync timeout. */
5269         uint64_t gsynctodis            : 1;  /**< [ 46: 46](R/W) Global sync timeout disable. */
5270         uint64_t gsynctonosw           : 1;  /**< [ 47: 47](R/W) Global sync timeout, no report to software. */
5271         uint64_t wbfsbeerr             : 1;  /**< [ 48: 48](RO) Reserved. */
5272         uint64_t reserved_49_63        : 15;
5273 #endif /* Word 0 - End */
5274     } cn81xx;
5275     struct bdk_ap_cvm_errmem_el1_cn83xx
5276     {
5277 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5278         uint64_t reserved_49_63        : 15;
5279         uint64_t wbfsbeerr             : 1;  /**< [ 48: 48](R/W/H) Write-buffer single-bit error. */
5280         uint64_t gsynctonosw           : 1;  /**< [ 47: 47](R/W) Global sync timeout, no report to software. */
5281         uint64_t gsynctodis            : 1;  /**< [ 46: 46](R/W) Global sync timeout disable. */
5282         uint64_t gsyncto               : 1;  /**< [ 45: 45](R/W/H) Global sync timeout. */
5283         uint64_t wcumultdis            : 1;  /**< [ 44: 44](R/W) WCU multiple match error disable. */
5284         uint64_t wcumult               : 1;  /**< [ 43: 43](R/W/H) WCU multiple match error. */
5285         uint64_t mtlbmultdis           : 1;  /**< [ 42: 42](R/W) MTLB multiple match error disable. */
5286         uint64_t mtlbmult              : 1;  /**< [ 41: 41](R/W/H) MTLB multiple match error. */
5287         uint64_t spare40               : 1;  /**< [ 40: 40](R/W/H) Reserved. */
5288         uint64_t barriertonosw         : 1;  /**< [ 39: 39](R/W) Barrier timeout, no report to software. */
5289         uint64_t barriertodis          : 1;  /**< [ 38: 38](R/W) Barrier timeout disable. */
5290         uint64_t barrierto             : 1;  /**< [ 37: 37](R/W/H) Barrier timeout. */
5291         uint64_t spare36               : 1;  /**< [ 36: 36](R/W/H) Reserved. */
5292         uint64_t rbftonosw             : 1;  /**< [ 35: 35](R/W) Read buffer timeout, no report to software. */
5293         uint64_t rbftodis              : 1;  /**< [ 34: 34](R/W) Read buffer timeout disable. */
5294         uint64_t rbfto                 : 1;  /**< [ 33: 33](R/W/H) Read buffer timeout. */
5295         uint64_t wcuperrforce          : 1;  /**< [ 32: 32](R/W/H) WCU parity error force. Bit is cleared when error is forced on next write operation. */
5296         uint64_t wcuperrnosw           : 1;  /**< [ 31: 31](R/W) WCU parity error, no report to software. */
5297         uint64_t wcuperrdis            : 1;  /**< [ 30: 30](R/W) WCU parity error disable. */
5298         uint64_t wcuperr               : 1;  /**< [ 29: 29](R/W/H) WCU corrected parity error. */
5299         uint64_t wbfdbeforce           : 1;  /**< [ 28: 28](R/W/H) Write-buffer DBE force. Bit is cleared when error is forced on next write operation. */
5300         uint64_t wbfsbeforce           : 1;  /**< [ 27: 27](R/W/H) Write-buffer SBE force. Bit is cleared when error is forced on next write operation. */
5301         uint64_t wbfperrnosw           : 1;  /**< [ 26: 26](R/W) Write-buffer single-bit error, no report to software. */
5302         uint64_t wbfperrdis            : 1;  /**< [ 25: 25](R/W) Write-buffer double-bit error disable. */
5303         uint64_t wbfperr               : 1;  /**< [ 24: 24](R/W/H) Write-buffer double-bit error. */
5304         uint64_t mafperrforce          : 1;  /**< [ 23: 23](R/W/H) MAF parity error force. Bit is cleared when error is forced on next write operation. */
5305         uint64_t mafperrnosw           : 1;  /**< [ 22: 22](R/W) MAF parity error, no report to software. */
5306         uint64_t mafperrdis            : 1;  /**< [ 21: 21](R/W) MAF parity error disable. */
5307         uint64_t mafperr               : 1;  /**< [ 20: 20](R/W/H) MAF parity error. */
5308         uint64_t utlbperrforce         : 1;  /**< [ 19: 19](R/W/H) uTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5309         uint64_t utlbperrnosw          : 1;  /**< [ 18: 18](R/W) uTLB correctable parity error, no report to software. */
5310         uint64_t utlbperrdis           : 1;  /**< [ 17: 17](R/W) uTLB correctable parity error disable. */
5311         uint64_t utlbperr              : 1;  /**< [ 16: 16](R/W/H) uTLB corrected a parity error. */
5312         uint64_t mtlbperrforce         : 1;  /**< [ 15: 15](R/W/H) MTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5313         uint64_t mtlbperrnosw          : 1;  /**< [ 14: 14](R/W) MTLB correctable parity error, no report to software. */
5314         uint64_t mtlbperrdis           : 1;  /**< [ 13: 13](R/W) MTLB correctable parity error disable. */
5315         uint64_t mtlbperr              : 1;  /**< [ 12: 12](R/W/H) MTLB corrected a parity error. */
5316         uint64_t l1dperrforce          : 1;  /**< [ 11: 11](R/W/H) Dcache correctable parity error force. Bit is cleared when error is forced on next write operation. */
5317         uint64_t l1dperrnosw           : 1;  /**< [ 10: 10](R/W) Dcache correctable parity error, no report to software. */
5318         uint64_t l1dperrdis            : 1;  /**< [  9:  9](R/W) Dcache correctable parity error disable. */
5319         uint64_t l1dperr               : 1;  /**< [  8:  8](R/W/H) Dcache corrected a parity error. */
5320         uint64_t l1dway                : 5;  /**< [  7:  3](R/W/H) Indicates Dcache way. */
5321         uint64_t l1dset                : 3;  /**< [  2:  0](R/W/H) Indicates Dcache set. */
5322 #else /* Word 0 - Little Endian */
5323         uint64_t l1dset                : 3;  /**< [  2:  0](R/W/H) Indicates Dcache set. */
5324         uint64_t l1dway                : 5;  /**< [  7:  3](R/W/H) Indicates Dcache way. */
5325         uint64_t l1dperr               : 1;  /**< [  8:  8](R/W/H) Dcache corrected a parity error. */
5326         uint64_t l1dperrdis            : 1;  /**< [  9:  9](R/W) Dcache correctable parity error disable. */
5327         uint64_t l1dperrnosw           : 1;  /**< [ 10: 10](R/W) Dcache correctable parity error, no report to software. */
5328         uint64_t l1dperrforce          : 1;  /**< [ 11: 11](R/W/H) Dcache correctable parity error force. Bit is cleared when error is forced on next write operation. */
5329         uint64_t mtlbperr              : 1;  /**< [ 12: 12](R/W/H) MTLB corrected a parity error. */
5330         uint64_t mtlbperrdis           : 1;  /**< [ 13: 13](R/W) MTLB correctable parity error disable. */
5331         uint64_t mtlbperrnosw          : 1;  /**< [ 14: 14](R/W) MTLB correctable parity error, no report to software. */
5332         uint64_t mtlbperrforce         : 1;  /**< [ 15: 15](R/W/H) MTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5333         uint64_t utlbperr              : 1;  /**< [ 16: 16](R/W/H) uTLB corrected a parity error. */
5334         uint64_t utlbperrdis           : 1;  /**< [ 17: 17](R/W) uTLB correctable parity error disable. */
5335         uint64_t utlbperrnosw          : 1;  /**< [ 18: 18](R/W) uTLB correctable parity error, no report to software. */
5336         uint64_t utlbperrforce         : 1;  /**< [ 19: 19](R/W/H) uTLB correctable parity error force. Bit is cleared when error is forced on next write operation. */
5337         uint64_t mafperr               : 1;  /**< [ 20: 20](R/W/H) MAF parity error. */
5338         uint64_t mafperrdis            : 1;  /**< [ 21: 21](R/W) MAF parity error disable. */
5339         uint64_t mafperrnosw           : 1;  /**< [ 22: 22](R/W) MAF parity error, no report to software. */
5340         uint64_t mafperrforce          : 1;  /**< [ 23: 23](R/W/H) MAF parity error force. Bit is cleared when error is forced on next write operation. */
5341         uint64_t wbfperr               : 1;  /**< [ 24: 24](R/W/H) Write-buffer double-bit error. */
5342         uint64_t wbfperrdis            : 1;  /**< [ 25: 25](R/W) Write-buffer double-bit error disable. */
5343         uint64_t wbfperrnosw           : 1;  /**< [ 26: 26](R/W) Write-buffer single-bit error, no report to software. */
5344         uint64_t wbfsbeforce           : 1;  /**< [ 27: 27](R/W/H) Write-buffer SBE force. Bit is cleared when error is forced on next write operation. */
5345         uint64_t wbfdbeforce           : 1;  /**< [ 28: 28](R/W/H) Write-buffer DBE force. Bit is cleared when error is forced on next write operation. */
5346         uint64_t wcuperr               : 1;  /**< [ 29: 29](R/W/H) WCU corrected parity error. */
5347         uint64_t wcuperrdis            : 1;  /**< [ 30: 30](R/W) WCU parity error disable. */
5348         uint64_t wcuperrnosw           : 1;  /**< [ 31: 31](R/W) WCU parity error, no report to software. */
5349         uint64_t wcuperrforce          : 1;  /**< [ 32: 32](R/W/H) WCU parity error force. Bit is cleared when error is forced on next write operation. */
5350         uint64_t rbfto                 : 1;  /**< [ 33: 33](R/W/H) Read buffer timeout. */
5351         uint64_t rbftodis              : 1;  /**< [ 34: 34](R/W) Read buffer timeout disable. */
5352         uint64_t rbftonosw             : 1;  /**< [ 35: 35](R/W) Read buffer timeout, no report to software. */
5353         uint64_t spare36               : 1;  /**< [ 36: 36](R/W/H) Reserved. */
5354         uint64_t barrierto             : 1;  /**< [ 37: 37](R/W/H) Barrier timeout. */
5355         uint64_t barriertodis          : 1;  /**< [ 38: 38](R/W) Barrier timeout disable. */
5356         uint64_t barriertonosw         : 1;  /**< [ 39: 39](R/W) Barrier timeout, no report to software. */
5357         uint64_t spare40               : 1;  /**< [ 40: 40](R/W/H) Reserved. */
5358         uint64_t mtlbmult              : 1;  /**< [ 41: 41](R/W/H) MTLB multiple match error. */
5359         uint64_t mtlbmultdis           : 1;  /**< [ 42: 42](R/W) MTLB multiple match error disable. */
5360         uint64_t wcumult               : 1;  /**< [ 43: 43](R/W/H) WCU multiple match error. */
5361         uint64_t wcumultdis            : 1;  /**< [ 44: 44](R/W) WCU multiple match error disable. */
5362         uint64_t gsyncto               : 1;  /**< [ 45: 45](R/W/H) Global sync timeout. */
5363         uint64_t gsynctodis            : 1;  /**< [ 46: 46](R/W) Global sync timeout disable. */
5364         uint64_t gsynctonosw           : 1;  /**< [ 47: 47](R/W) Global sync timeout, no report to software. */
5365         uint64_t wbfsbeerr             : 1;  /**< [ 48: 48](R/W/H) Write-buffer single-bit error. */
5366         uint64_t reserved_49_63        : 15;
5367 #endif /* Word 0 - End */
5368     } cn83xx;
5369     /* struct bdk_ap_cvm_errmem_el1_cn81xx cn88xxp2; */
5370 };
5371 typedef union bdk_ap_cvm_errmem_el1 bdk_ap_cvm_errmem_el1_t;
5372 
5373 #define BDK_AP_CVM_ERRMEM_EL1 BDK_AP_CVM_ERRMEM_EL1_FUNC()
5374 static inline uint64_t BDK_AP_CVM_ERRMEM_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_ERRMEM_EL1_FUNC(void)5375 static inline uint64_t BDK_AP_CVM_ERRMEM_EL1_FUNC(void)
5376 {
5377     return 0x3000b020400ll;
5378 }
5379 
5380 #define typedef_BDK_AP_CVM_ERRMEM_EL1 bdk_ap_cvm_errmem_el1_t
5381 #define bustype_BDK_AP_CVM_ERRMEM_EL1 BDK_CSR_TYPE_SYSREG
5382 #define basename_BDK_AP_CVM_ERRMEM_EL1 "AP_CVM_ERRMEM_EL1"
5383 #define busnum_BDK_AP_CVM_ERRMEM_EL1 0
5384 #define arguments_BDK_AP_CVM_ERRMEM_EL1 -1,-1,-1,-1
5385 
5386 /**
5387  * Register (SYSREG) ap_cvm_evattid_el1
5388  *
5389  * AP Cavium EVATTID Register
5390  * This register is for diagnostic use only.
5391  */
5392 union bdk_ap_cvm_evattid_el1
5393 {
5394     uint64_t u;
5395     struct bdk_ap_cvm_evattid_el1_s
5396     {
5397 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5398         uint64_t reserved_60_63        : 4;
5399         uint64_t el3_vmid              : 4;  /**< [ 59: 56](R/W) Current EL3 EVA VMID. */
5400         uint64_t reserved_55           : 1;
5401         uint64_t el3_asid              : 7;  /**< [ 54: 48](R/W) Current EL3 EVA ASID. */
5402         uint64_t el2_vmid              : 4;  /**< [ 47: 44](R/W) Current EL2 EVA VMID. */
5403         uint64_t reserved_31_43        : 13;
5404         uint64_t el2_asid_e2h          : 7;  /**< [ 30: 24](R/W) Current EL2 E2H EVA ASID. */
5405         uint64_t el1_vmid_s            : 4;  /**< [ 23: 20](R/W) Current EL1 secure EVA VMID. */
5406         uint64_t reserved_12_19        : 8;
5407         uint64_t el1_vmid_ns           : 4;  /**< [ 11:  8](R/W) Current EL1 nonsecure EVA VMID. */
5408         uint64_t reserved_0_7          : 8;
5409 #else /* Word 0 - Little Endian */
5410         uint64_t reserved_0_7          : 8;
5411         uint64_t el1_vmid_ns           : 4;  /**< [ 11:  8](R/W) Current EL1 nonsecure EVA VMID. */
5412         uint64_t reserved_12_19        : 8;
5413         uint64_t el1_vmid_s            : 4;  /**< [ 23: 20](R/W) Current EL1 secure EVA VMID. */
5414         uint64_t el2_asid_e2h          : 7;  /**< [ 30: 24](R/W) Current EL2 E2H EVA ASID. */
5415         uint64_t reserved_31_43        : 13;
5416         uint64_t el2_vmid              : 4;  /**< [ 47: 44](R/W) Current EL2 EVA VMID. */
5417         uint64_t el3_asid              : 7;  /**< [ 54: 48](R/W) Current EL3 EVA ASID. */
5418         uint64_t reserved_55           : 1;
5419         uint64_t el3_vmid              : 4;  /**< [ 59: 56](R/W) Current EL3 EVA VMID. */
5420         uint64_t reserved_60_63        : 4;
5421 #endif /* Word 0 - End */
5422     } s;
5423     struct bdk_ap_cvm_evattid_el1_cn8
5424     {
5425 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5426         uint64_t reserved_38_63        : 26;
5427         uint64_t el2_asid              : 6;  /**< [ 37: 32](R/W) Current EL2 EVA ASID. */
5428         uint64_t reserved_20_31        : 12;
5429         uint64_t el1_vmid              : 4;  /**< [ 19: 16](R/W) Current EL1 EVA VMID. */
5430         uint64_t reserved_6_15         : 10;
5431         uint64_t el1_asid              : 6;  /**< [  5:  0](R/W) Current EL1 EVA ASID. */
5432 #else /* Word 0 - Little Endian */
5433         uint64_t el1_asid              : 6;  /**< [  5:  0](R/W) Current EL1 EVA ASID. */
5434         uint64_t reserved_6_15         : 10;
5435         uint64_t el1_vmid              : 4;  /**< [ 19: 16](R/W) Current EL1 EVA VMID. */
5436         uint64_t reserved_20_31        : 12;
5437         uint64_t el2_asid              : 6;  /**< [ 37: 32](R/W) Current EL2 EVA ASID. */
5438         uint64_t reserved_38_63        : 26;
5439 #endif /* Word 0 - End */
5440     } cn8;
5441     struct bdk_ap_cvm_evattid_el1_cn9
5442     {
5443 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5444         uint64_t reserved_60_63        : 4;
5445         uint64_t el3_vmid              : 4;  /**< [ 59: 56](R/W) Current EL3 EVA VMID. */
5446         uint64_t reserved_55           : 1;
5447         uint64_t el3_asid              : 7;  /**< [ 54: 48](R/W) Current EL3 EVA ASID. */
5448         uint64_t el2_vmid              : 4;  /**< [ 47: 44](R/W) Current EL2 EVA VMID. */
5449         uint64_t reserved_43           : 1;
5450         uint64_t el2_asid              : 7;  /**< [ 42: 36](R/W) Current EL2 EVA ASID. */
5451         uint64_t el2_vmid_e2h          : 4;  /**< [ 35: 32](R/W) Current EL2 E2H EVA VMID. */
5452         uint64_t reserved_31           : 1;
5453         uint64_t el2_asid_e2h          : 7;  /**< [ 30: 24](R/W) Current EL2 E2H EVA ASID. */
5454         uint64_t el1_vmid_s            : 4;  /**< [ 23: 20](R/W) Current EL1 secure EVA VMID. */
5455         uint64_t reserved_19           : 1;
5456         uint64_t el1_asid_s            : 7;  /**< [ 18: 12](R/W) Current EL1 secure EVA ASID. */
5457         uint64_t el1_vmid_ns           : 4;  /**< [ 11:  8](R/W) Current EL1 nonsecure EVA VMID. */
5458         uint64_t reserved_7            : 1;
5459         uint64_t el1_asid_ns           : 7;  /**< [  6:  0](R/W) Current EL1 nonsecure EVA ASID. */
5460 #else /* Word 0 - Little Endian */
5461         uint64_t el1_asid_ns           : 7;  /**< [  6:  0](R/W) Current EL1 nonsecure EVA ASID. */
5462         uint64_t reserved_7            : 1;
5463         uint64_t el1_vmid_ns           : 4;  /**< [ 11:  8](R/W) Current EL1 nonsecure EVA VMID. */
5464         uint64_t el1_asid_s            : 7;  /**< [ 18: 12](R/W) Current EL1 secure EVA ASID. */
5465         uint64_t reserved_19           : 1;
5466         uint64_t el1_vmid_s            : 4;  /**< [ 23: 20](R/W) Current EL1 secure EVA VMID. */
5467         uint64_t el2_asid_e2h          : 7;  /**< [ 30: 24](R/W) Current EL2 E2H EVA ASID. */
5468         uint64_t reserved_31           : 1;
5469         uint64_t el2_vmid_e2h          : 4;  /**< [ 35: 32](R/W) Current EL2 E2H EVA VMID. */
5470         uint64_t el2_asid              : 7;  /**< [ 42: 36](R/W) Current EL2 EVA ASID. */
5471         uint64_t reserved_43           : 1;
5472         uint64_t el2_vmid              : 4;  /**< [ 47: 44](R/W) Current EL2 EVA VMID. */
5473         uint64_t el3_asid              : 7;  /**< [ 54: 48](R/W) Current EL3 EVA ASID. */
5474         uint64_t reserved_55           : 1;
5475         uint64_t el3_vmid              : 4;  /**< [ 59: 56](R/W) Current EL3 EVA VMID. */
5476         uint64_t reserved_60_63        : 4;
5477 #endif /* Word 0 - End */
5478     } cn9;
5479 };
5480 typedef union bdk_ap_cvm_evattid_el1 bdk_ap_cvm_evattid_el1_t;
5481 
5482 #define BDK_AP_CVM_EVATTID_EL1 BDK_AP_CVM_EVATTID_EL1_FUNC()
5483 static inline uint64_t BDK_AP_CVM_EVATTID_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_EVATTID_EL1_FUNC(void)5484 static inline uint64_t BDK_AP_CVM_EVATTID_EL1_FUNC(void)
5485 {
5486     return 0x3000b020500ll;
5487 }
5488 
5489 #define typedef_BDK_AP_CVM_EVATTID_EL1 bdk_ap_cvm_evattid_el1_t
5490 #define bustype_BDK_AP_CVM_EVATTID_EL1 BDK_CSR_TYPE_SYSREG
5491 #define basename_BDK_AP_CVM_EVATTID_EL1 "AP_CVM_EVATTID_EL1"
5492 #define busnum_BDK_AP_CVM_EVATTID_EL1 0
5493 #define arguments_BDK_AP_CVM_EVATTID_EL1 -1,-1,-1,-1
5494 
5495 /**
5496  * Register (SYSREG) ap_cvm_icachedata0_el1
5497  *
5498  * INTERNAL: AP Cavium Icache Data 0 Register
5499  */
5500 union bdk_ap_cvm_icachedata0_el1
5501 {
5502     uint64_t u;
5503     struct bdk_ap_cvm_icachedata0_el1_s
5504     {
5505 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5506         uint64_t data                  : 64; /**< [ 63:  0](RO) Icache data\<63:0\> from an Icache read operation. */
5507 #else /* Word 0 - Little Endian */
5508         uint64_t data                  : 64; /**< [ 63:  0](RO) Icache data\<63:0\> from an Icache read operation. */
5509 #endif /* Word 0 - End */
5510     } s;
5511     /* struct bdk_ap_cvm_icachedata0_el1_s cn; */
5512 };
5513 typedef union bdk_ap_cvm_icachedata0_el1 bdk_ap_cvm_icachedata0_el1_t;
5514 
5515 #define BDK_AP_CVM_ICACHEDATA0_EL1 BDK_AP_CVM_ICACHEDATA0_EL1_FUNC()
5516 static inline uint64_t BDK_AP_CVM_ICACHEDATA0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_ICACHEDATA0_EL1_FUNC(void)5517 static inline uint64_t BDK_AP_CVM_ICACHEDATA0_EL1_FUNC(void)
5518 {
5519     return 0x3000b030000ll;
5520 }
5521 
5522 #define typedef_BDK_AP_CVM_ICACHEDATA0_EL1 bdk_ap_cvm_icachedata0_el1_t
5523 #define bustype_BDK_AP_CVM_ICACHEDATA0_EL1 BDK_CSR_TYPE_SYSREG
5524 #define basename_BDK_AP_CVM_ICACHEDATA0_EL1 "AP_CVM_ICACHEDATA0_EL1"
5525 #define busnum_BDK_AP_CVM_ICACHEDATA0_EL1 0
5526 #define arguments_BDK_AP_CVM_ICACHEDATA0_EL1 -1,-1,-1,-1
5527 
5528 /**
5529  * Register (SYSREG) ap_cvm_icachedata1_el1
5530  *
5531  * INTERNAL: AP Cavium Icache Data 1 Register
5532  */
5533 union bdk_ap_cvm_icachedata1_el1
5534 {
5535     uint64_t u;
5536     struct bdk_ap_cvm_icachedata1_el1_s
5537     {
5538 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5539         uint64_t reserved_2_63         : 62;
5540         uint64_t data                  : 2;  /**< [  1:  0](RO) Icache data\<65:64\> from an Icache read operation. */
5541 #else /* Word 0 - Little Endian */
5542         uint64_t data                  : 2;  /**< [  1:  0](RO) Icache data\<65:64\> from an Icache read operation. */
5543         uint64_t reserved_2_63         : 62;
5544 #endif /* Word 0 - End */
5545     } s;
5546     /* struct bdk_ap_cvm_icachedata1_el1_s cn; */
5547 };
5548 typedef union bdk_ap_cvm_icachedata1_el1 bdk_ap_cvm_icachedata1_el1_t;
5549 
5550 #define BDK_AP_CVM_ICACHEDATA1_EL1 BDK_AP_CVM_ICACHEDATA1_EL1_FUNC()
5551 static inline uint64_t BDK_AP_CVM_ICACHEDATA1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_ICACHEDATA1_EL1_FUNC(void)5552 static inline uint64_t BDK_AP_CVM_ICACHEDATA1_EL1_FUNC(void)
5553 {
5554     return 0x3000b030100ll;
5555 }
5556 
5557 #define typedef_BDK_AP_CVM_ICACHEDATA1_EL1 bdk_ap_cvm_icachedata1_el1_t
5558 #define bustype_BDK_AP_CVM_ICACHEDATA1_EL1 BDK_CSR_TYPE_SYSREG
5559 #define basename_BDK_AP_CVM_ICACHEDATA1_EL1 "AP_CVM_ICACHEDATA1_EL1"
5560 #define busnum_BDK_AP_CVM_ICACHEDATA1_EL1 0
5561 #define arguments_BDK_AP_CVM_ICACHEDATA1_EL1 -1,-1,-1,-1
5562 
5563 /**
5564  * Register (SYSREG) ap_cvm_icachetag0_el1
5565  *
5566  * INTERNAL: AP Cavium Icache Tag 0 Register
5567  */
5568 union bdk_ap_cvm_icachetag0_el1
5569 {
5570     uint64_t u;
5571     struct bdk_ap_cvm_icachetag0_el1_s
5572     {
5573 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5574         uint64_t reserved_52_63        : 12;
5575         uint64_t valid                 : 1;  /**< [ 51: 51](RO) Valid. */
5576         uint64_t va                    : 40; /**< [ 50: 11](RO) VA in tags. */
5577         uint64_t asid_valid_ignored    : 1;  /**< [ 10: 10](RO) ASID valid is ignored. */
5578         uint64_t asid_index            : 6;  /**< [  9:  4](RO) ASID index. */
5579         uint64_t vmid_index            : 4;  /**< [  3:  0](RO) VMID index. */
5580 #else /* Word 0 - Little Endian */
5581         uint64_t vmid_index            : 4;  /**< [  3:  0](RO) VMID index. */
5582         uint64_t asid_index            : 6;  /**< [  9:  4](RO) ASID index. */
5583         uint64_t asid_valid_ignored    : 1;  /**< [ 10: 10](RO) ASID valid is ignored. */
5584         uint64_t va                    : 40; /**< [ 50: 11](RO) VA in tags. */
5585         uint64_t valid                 : 1;  /**< [ 51: 51](RO) Valid. */
5586         uint64_t reserved_52_63        : 12;
5587 #endif /* Word 0 - End */
5588     } s;
5589     /* struct bdk_ap_cvm_icachetag0_el1_s cn; */
5590 };
5591 typedef union bdk_ap_cvm_icachetag0_el1 bdk_ap_cvm_icachetag0_el1_t;
5592 
5593 #define BDK_AP_CVM_ICACHETAG0_EL1 BDK_AP_CVM_ICACHETAG0_EL1_FUNC()
5594 static inline uint64_t BDK_AP_CVM_ICACHETAG0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_ICACHETAG0_EL1_FUNC(void)5595 static inline uint64_t BDK_AP_CVM_ICACHETAG0_EL1_FUNC(void)
5596 {
5597     return 0x3000b030200ll;
5598 }
5599 
5600 #define typedef_BDK_AP_CVM_ICACHETAG0_EL1 bdk_ap_cvm_icachetag0_el1_t
5601 #define bustype_BDK_AP_CVM_ICACHETAG0_EL1 BDK_CSR_TYPE_SYSREG
5602 #define basename_BDK_AP_CVM_ICACHETAG0_EL1 "AP_CVM_ICACHETAG0_EL1"
5603 #define busnum_BDK_AP_CVM_ICACHETAG0_EL1 0
5604 #define arguments_BDK_AP_CVM_ICACHETAG0_EL1 -1,-1,-1,-1
5605 
5606 /**
5607  * Register (SYSREG) ap_cvm_memdebug0_el3
5608  *
5609  * INTERNAL: AP Cavium Memory Debug 0 Register
5610  */
5611 union bdk_ap_cvm_memdebug0_el3
5612 {
5613     uint64_t u;
5614     struct bdk_ap_cvm_memdebug0_el3_s
5615     {
5616 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5617         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5618 #else /* Word 0 - Little Endian */
5619         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5620 #endif /* Word 0 - End */
5621     } s;
5622     /* struct bdk_ap_cvm_memdebug0_el3_s cn; */
5623 };
5624 typedef union bdk_ap_cvm_memdebug0_el3 bdk_ap_cvm_memdebug0_el3_t;
5625 
5626 #define BDK_AP_CVM_MEMDEBUG0_EL3 BDK_AP_CVM_MEMDEBUG0_EL3_FUNC()
5627 static inline uint64_t BDK_AP_CVM_MEMDEBUG0_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_MEMDEBUG0_EL3_FUNC(void)5628 static inline uint64_t BDK_AP_CVM_MEMDEBUG0_EL3_FUNC(void)
5629 {
5630     return 0x3060b040400ll;
5631 }
5632 
5633 #define typedef_BDK_AP_CVM_MEMDEBUG0_EL3 bdk_ap_cvm_memdebug0_el3_t
5634 #define bustype_BDK_AP_CVM_MEMDEBUG0_EL3 BDK_CSR_TYPE_SYSREG
5635 #define basename_BDK_AP_CVM_MEMDEBUG0_EL3 "AP_CVM_MEMDEBUG0_EL3"
5636 #define busnum_BDK_AP_CVM_MEMDEBUG0_EL3 0
5637 #define arguments_BDK_AP_CVM_MEMDEBUG0_EL3 -1,-1,-1,-1
5638 
5639 /**
5640  * Register (SYSREG) ap_cvm_memdebug1_el3
5641  *
5642  * INTERNAL: AP Cavium Memory Debug 1 Register
5643  */
5644 union bdk_ap_cvm_memdebug1_el3
5645 {
5646     uint64_t u;
5647     struct bdk_ap_cvm_memdebug1_el3_s
5648     {
5649 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5650         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5651 #else /* Word 0 - Little Endian */
5652         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5653 #endif /* Word 0 - End */
5654     } s;
5655     /* struct bdk_ap_cvm_memdebug1_el3_s cn; */
5656 };
5657 typedef union bdk_ap_cvm_memdebug1_el3 bdk_ap_cvm_memdebug1_el3_t;
5658 
5659 #define BDK_AP_CVM_MEMDEBUG1_EL3 BDK_AP_CVM_MEMDEBUG1_EL3_FUNC()
5660 static inline uint64_t BDK_AP_CVM_MEMDEBUG1_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_MEMDEBUG1_EL3_FUNC(void)5661 static inline uint64_t BDK_AP_CVM_MEMDEBUG1_EL3_FUNC(void)
5662 {
5663     return 0x3060b040500ll;
5664 }
5665 
5666 #define typedef_BDK_AP_CVM_MEMDEBUG1_EL3 bdk_ap_cvm_memdebug1_el3_t
5667 #define bustype_BDK_AP_CVM_MEMDEBUG1_EL3 BDK_CSR_TYPE_SYSREG
5668 #define basename_BDK_AP_CVM_MEMDEBUG1_EL3 "AP_CVM_MEMDEBUG1_EL3"
5669 #define busnum_BDK_AP_CVM_MEMDEBUG1_EL3 0
5670 #define arguments_BDK_AP_CVM_MEMDEBUG1_EL3 -1,-1,-1,-1
5671 
5672 /**
5673  * Register (SYSREG) ap_cvm_memdebug2_el3
5674  *
5675  * INTERNAL: AP Cavium Memory Debug 2 Register
5676  */
5677 union bdk_ap_cvm_memdebug2_el3
5678 {
5679     uint64_t u;
5680     struct bdk_ap_cvm_memdebug2_el3_s
5681     {
5682 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5683         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5684 #else /* Word 0 - Little Endian */
5685         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5686 #endif /* Word 0 - End */
5687     } s;
5688     /* struct bdk_ap_cvm_memdebug2_el3_s cn; */
5689 };
5690 typedef union bdk_ap_cvm_memdebug2_el3 bdk_ap_cvm_memdebug2_el3_t;
5691 
5692 #define BDK_AP_CVM_MEMDEBUG2_EL3 BDK_AP_CVM_MEMDEBUG2_EL3_FUNC()
5693 static inline uint64_t BDK_AP_CVM_MEMDEBUG2_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_MEMDEBUG2_EL3_FUNC(void)5694 static inline uint64_t BDK_AP_CVM_MEMDEBUG2_EL3_FUNC(void)
5695 {
5696     return 0x3060b040600ll;
5697 }
5698 
5699 #define typedef_BDK_AP_CVM_MEMDEBUG2_EL3 bdk_ap_cvm_memdebug2_el3_t
5700 #define bustype_BDK_AP_CVM_MEMDEBUG2_EL3 BDK_CSR_TYPE_SYSREG
5701 #define basename_BDK_AP_CVM_MEMDEBUG2_EL3 "AP_CVM_MEMDEBUG2_EL3"
5702 #define busnum_BDK_AP_CVM_MEMDEBUG2_EL3 0
5703 #define arguments_BDK_AP_CVM_MEMDEBUG2_EL3 -1,-1,-1,-1
5704 
5705 /**
5706  * Register (SYSREG) ap_cvm_memdebug3_el3
5707  *
5708  * INTERNAL: AP Cavium Memory Debug 3 Register
5709  */
5710 union bdk_ap_cvm_memdebug3_el3
5711 {
5712     uint64_t u;
5713     struct bdk_ap_cvm_memdebug3_el3_s
5714     {
5715 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5716         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5717 #else /* Word 0 - Little Endian */
5718         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5719 #endif /* Word 0 - End */
5720     } s;
5721     /* struct bdk_ap_cvm_memdebug3_el3_s cn; */
5722 };
5723 typedef union bdk_ap_cvm_memdebug3_el3 bdk_ap_cvm_memdebug3_el3_t;
5724 
5725 #define BDK_AP_CVM_MEMDEBUG3_EL3 BDK_AP_CVM_MEMDEBUG3_EL3_FUNC()
5726 static inline uint64_t BDK_AP_CVM_MEMDEBUG3_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_MEMDEBUG3_EL3_FUNC(void)5727 static inline uint64_t BDK_AP_CVM_MEMDEBUG3_EL3_FUNC(void)
5728 {
5729     return 0x3060b040700ll;
5730 }
5731 
5732 #define typedef_BDK_AP_CVM_MEMDEBUG3_EL3 bdk_ap_cvm_memdebug3_el3_t
5733 #define bustype_BDK_AP_CVM_MEMDEBUG3_EL3 BDK_CSR_TYPE_SYSREG
5734 #define basename_BDK_AP_CVM_MEMDEBUG3_EL3 "AP_CVM_MEMDEBUG3_EL3"
5735 #define busnum_BDK_AP_CVM_MEMDEBUG3_EL3 0
5736 #define arguments_BDK_AP_CVM_MEMDEBUG3_EL3 -1,-1,-1,-1
5737 
5738 /**
5739  * Register (SYSREG) ap_cvm_memdebug4_el3
5740  *
5741  * INTERNAL: AP Cavium Memory Debug 4 Register
5742  */
5743 union bdk_ap_cvm_memdebug4_el3
5744 {
5745     uint64_t u;
5746     struct bdk_ap_cvm_memdebug4_el3_s
5747     {
5748 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5749         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5750 #else /* Word 0 - Little Endian */
5751         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5752 #endif /* Word 0 - End */
5753     } s;
5754     /* struct bdk_ap_cvm_memdebug4_el3_s cn; */
5755 };
5756 typedef union bdk_ap_cvm_memdebug4_el3 bdk_ap_cvm_memdebug4_el3_t;
5757 
5758 #define BDK_AP_CVM_MEMDEBUG4_EL3 BDK_AP_CVM_MEMDEBUG4_EL3_FUNC()
5759 static inline uint64_t BDK_AP_CVM_MEMDEBUG4_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_MEMDEBUG4_EL3_FUNC(void)5760 static inline uint64_t BDK_AP_CVM_MEMDEBUG4_EL3_FUNC(void)
5761 {
5762     return 0x3060b050400ll;
5763 }
5764 
5765 #define typedef_BDK_AP_CVM_MEMDEBUG4_EL3 bdk_ap_cvm_memdebug4_el3_t
5766 #define bustype_BDK_AP_CVM_MEMDEBUG4_EL3 BDK_CSR_TYPE_SYSREG
5767 #define basename_BDK_AP_CVM_MEMDEBUG4_EL3 "AP_CVM_MEMDEBUG4_EL3"
5768 #define busnum_BDK_AP_CVM_MEMDEBUG4_EL3 0
5769 #define arguments_BDK_AP_CVM_MEMDEBUG4_EL3 -1,-1,-1,-1
5770 
5771 /**
5772  * Register (SYSREG) ap_cvm_memdebug5_el3
5773  *
5774  * INTERNAL: AP Cavium Memory Debug 5 Register
5775  */
5776 union bdk_ap_cvm_memdebug5_el3
5777 {
5778     uint64_t u;
5779     struct bdk_ap_cvm_memdebug5_el3_s
5780     {
5781 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5782         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5783 #else /* Word 0 - Little Endian */
5784         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5785 #endif /* Word 0 - End */
5786     } s;
5787     /* struct bdk_ap_cvm_memdebug5_el3_s cn; */
5788 };
5789 typedef union bdk_ap_cvm_memdebug5_el3 bdk_ap_cvm_memdebug5_el3_t;
5790 
5791 #define BDK_AP_CVM_MEMDEBUG5_EL3 BDK_AP_CVM_MEMDEBUG5_EL3_FUNC()
5792 static inline uint64_t BDK_AP_CVM_MEMDEBUG5_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_MEMDEBUG5_EL3_FUNC(void)5793 static inline uint64_t BDK_AP_CVM_MEMDEBUG5_EL3_FUNC(void)
5794 {
5795     return 0x3060b050500ll;
5796 }
5797 
5798 #define typedef_BDK_AP_CVM_MEMDEBUG5_EL3 bdk_ap_cvm_memdebug5_el3_t
5799 #define bustype_BDK_AP_CVM_MEMDEBUG5_EL3 BDK_CSR_TYPE_SYSREG
5800 #define basename_BDK_AP_CVM_MEMDEBUG5_EL3 "AP_CVM_MEMDEBUG5_EL3"
5801 #define busnum_BDK_AP_CVM_MEMDEBUG5_EL3 0
5802 #define arguments_BDK_AP_CVM_MEMDEBUG5_EL3 -1,-1,-1,-1
5803 
5804 /**
5805  * Register (SYSREG) ap_cvm_memdebug6_el3
5806  *
5807  * INTERNAL: AP Cavium Memory Debug 6 Register
5808  */
5809 union bdk_ap_cvm_memdebug6_el3
5810 {
5811     uint64_t u;
5812     struct bdk_ap_cvm_memdebug6_el3_s
5813     {
5814 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5815         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5816 #else /* Word 0 - Little Endian */
5817         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5818 #endif /* Word 0 - End */
5819     } s;
5820     /* struct bdk_ap_cvm_memdebug6_el3_s cn; */
5821 };
5822 typedef union bdk_ap_cvm_memdebug6_el3 bdk_ap_cvm_memdebug6_el3_t;
5823 
5824 #define BDK_AP_CVM_MEMDEBUG6_EL3 BDK_AP_CVM_MEMDEBUG6_EL3_FUNC()
5825 static inline uint64_t BDK_AP_CVM_MEMDEBUG6_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_MEMDEBUG6_EL3_FUNC(void)5826 static inline uint64_t BDK_AP_CVM_MEMDEBUG6_EL3_FUNC(void)
5827 {
5828     return 0x3060b050600ll;
5829 }
5830 
5831 #define typedef_BDK_AP_CVM_MEMDEBUG6_EL3 bdk_ap_cvm_memdebug6_el3_t
5832 #define bustype_BDK_AP_CVM_MEMDEBUG6_EL3 BDK_CSR_TYPE_SYSREG
5833 #define basename_BDK_AP_CVM_MEMDEBUG6_EL3 "AP_CVM_MEMDEBUG6_EL3"
5834 #define busnum_BDK_AP_CVM_MEMDEBUG6_EL3 0
5835 #define arguments_BDK_AP_CVM_MEMDEBUG6_EL3 -1,-1,-1,-1
5836 
5837 /**
5838  * Register (SYSREG) ap_cvm_memdebug7_el3
5839  *
5840  * INTERNAL: AP Cavium Memory Debug 7 Register
5841  */
5842 union bdk_ap_cvm_memdebug7_el3
5843 {
5844     uint64_t u;
5845     struct bdk_ap_cvm_memdebug7_el3_s
5846     {
5847 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5848         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5849 #else /* Word 0 - Little Endian */
5850         uint64_t debug                 : 64; /**< [ 63:  0](RO) Undocumented debug. */
5851 #endif /* Word 0 - End */
5852     } s;
5853     /* struct bdk_ap_cvm_memdebug7_el3_s cn; */
5854 };
5855 typedef union bdk_ap_cvm_memdebug7_el3 bdk_ap_cvm_memdebug7_el3_t;
5856 
5857 #define BDK_AP_CVM_MEMDEBUG7_EL3 BDK_AP_CVM_MEMDEBUG7_EL3_FUNC()
5858 static inline uint64_t BDK_AP_CVM_MEMDEBUG7_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_MEMDEBUG7_EL3_FUNC(void)5859 static inline uint64_t BDK_AP_CVM_MEMDEBUG7_EL3_FUNC(void)
5860 {
5861     return 0x3060b050700ll;
5862 }
5863 
5864 #define typedef_BDK_AP_CVM_MEMDEBUG7_EL3 bdk_ap_cvm_memdebug7_el3_t
5865 #define bustype_BDK_AP_CVM_MEMDEBUG7_EL3 BDK_CSR_TYPE_SYSREG
5866 #define basename_BDK_AP_CVM_MEMDEBUG7_EL3 "AP_CVM_MEMDEBUG7_EL3"
5867 #define busnum_BDK_AP_CVM_MEMDEBUG7_EL3 0
5868 #define arguments_BDK_AP_CVM_MEMDEBUG7_EL3 -1,-1,-1,-1
5869 
5870 /**
5871  * Register (SYSREG) ap_cvm_nvbar_el3
5872  *
5873  * AP Cavium DEL3T Address Register
5874  */
5875 union bdk_ap_cvm_nvbar_el3
5876 {
5877     uint64_t u;
5878     struct bdk_ap_cvm_nvbar_el3_s
5879     {
5880 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5881         uint64_t vector_address        : 53; /**< [ 63: 11](R/W) Cavium-specific exception vector address. */
5882         uint64_t reserved_0_10         : 11;
5883 #else /* Word 0 - Little Endian */
5884         uint64_t reserved_0_10         : 11;
5885         uint64_t vector_address        : 53; /**< [ 63: 11](R/W) Cavium-specific exception vector address. */
5886 #endif /* Word 0 - End */
5887     } s;
5888     /* struct bdk_ap_cvm_nvbar_el3_s cn; */
5889 };
5890 typedef union bdk_ap_cvm_nvbar_el3 bdk_ap_cvm_nvbar_el3_t;
5891 
5892 #define BDK_AP_CVM_NVBAR_EL3 BDK_AP_CVM_NVBAR_EL3_FUNC()
5893 static inline uint64_t BDK_AP_CVM_NVBAR_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_NVBAR_EL3_FUNC(void)5894 static inline uint64_t BDK_AP_CVM_NVBAR_EL3_FUNC(void)
5895 {
5896     return 0x3060b060000ll;
5897 }
5898 
5899 #define typedef_BDK_AP_CVM_NVBAR_EL3 bdk_ap_cvm_nvbar_el3_t
5900 #define bustype_BDK_AP_CVM_NVBAR_EL3 BDK_CSR_TYPE_SYSREG
5901 #define basename_BDK_AP_CVM_NVBAR_EL3 "AP_CVM_NVBAR_EL3"
5902 #define busnum_BDK_AP_CVM_NVBAR_EL3 0
5903 #define arguments_BDK_AP_CVM_NVBAR_EL3 -1,-1,-1,-1
5904 
5905 /**
5906  * Register (SYSREG) ap_cvm_pn_el1
5907  *
5908  * AP Cavium Processor Number Register
5909  * This register is accessible at EL1, but subject to the access controls in AP_CVM_ACCESS_EL1/EL2/EL3
5910  */
5911 union bdk_ap_cvm_pn_el1
5912 {
5913     uint64_t u;
5914     struct bdk_ap_cvm_pn_el1_s
5915     {
5916 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5917         uint64_t reserved_40_63        : 24;
5918         uint64_t clu                   : 8;  /**< [ 39: 32](RO) The cluster this core resides in. */
5919         uint64_t reserved_16_31        : 16;
5920         uint64_t pn                    : 16; /**< [ 15:  0](RO) The flat processor number value for the core. */
5921 #else /* Word 0 - Little Endian */
5922         uint64_t pn                    : 16; /**< [ 15:  0](RO) The flat processor number value for the core. */
5923         uint64_t reserved_16_31        : 16;
5924         uint64_t clu                   : 8;  /**< [ 39: 32](RO) The cluster this core resides in. */
5925         uint64_t reserved_40_63        : 24;
5926 #endif /* Word 0 - End */
5927     } s;
5928     /* struct bdk_ap_cvm_pn_el1_s cn; */
5929 };
5930 typedef union bdk_ap_cvm_pn_el1 bdk_ap_cvm_pn_el1_t;
5931 
5932 #define BDK_AP_CVM_PN_EL1 BDK_AP_CVM_PN_EL1_FUNC()
5933 static inline uint64_t BDK_AP_CVM_PN_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_PN_EL1_FUNC(void)5934 static inline uint64_t BDK_AP_CVM_PN_EL1_FUNC(void)
5935 {
5936     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
5937         return 0x3000b040200ll;
5938     __bdk_csr_fatal("AP_CVM_PN_EL1", 0, 0, 0, 0, 0);
5939 }
5940 
5941 #define typedef_BDK_AP_CVM_PN_EL1 bdk_ap_cvm_pn_el1_t
5942 #define bustype_BDK_AP_CVM_PN_EL1 BDK_CSR_TYPE_SYSREG
5943 #define basename_BDK_AP_CVM_PN_EL1 "AP_CVM_PN_EL1"
5944 #define busnum_BDK_AP_CVM_PN_EL1 0
5945 #define arguments_BDK_AP_CVM_PN_EL1 -1,-1,-1,-1
5946 
5947 /**
5948  * Register (SYSREG) ap_cvm_power_el1
5949  *
5950  * AP Cavium Power Control Register
5951  * This register controls power management.
5952  */
5953 union bdk_ap_cvm_power_el1
5954 {
5955     uint64_t u;
5956     struct bdk_ap_cvm_power_el1_s
5957     {
5958 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5959         uint64_t maxpow                : 8;  /**< [ 63: 56](R/W) Reserved.
5960                                                                  Internal:
5961                                                                  Maximum power. */
5962         uint64_t average_power         : 8;  /**< [ 55: 48](R/W) Average power.
5963                                                                  Time-averaged dynamic-power estimate for this core, in mA/GHz.
5964                                                                  An approximation of this core's power is calculated with:
5965 
5966                                                                    _ core_power = core_const * core_powered_on + [AVERAGE_POWER] * voltage * freq.
5967 
5968                                                                  Where:
5969 
5970                                                                  _ core_power is in mW.
5971 
5972                                                                  _ core_const is a per-core constant leakage from the HRM power application note, and is in
5973                                                                  mA.
5974 
5975                                                                  _ core_powered_on is a boolean indicating power applied, from RST_PP_POWER\<core_number\>.
5976 
5977                                                                  _ voltage is determined by the platform, perhaps by reading a VRM setting.
5978 
5979                                                                  _ freq is in GHz and is from RST_BOOT[C_MUL] * 0.050, assuming standard 50 MHz ref-clock. */
5980         uint64_t current_setting       : 8;  /**< [ 47: 40](R/W) Reserved.
5981                                                                  Internal:
5982                                                                  Current setting. */
5983         uint64_t hrm_adjustment        : 8;  /**< [ 39: 32](R/W) Reserved.
5984                                                                  Internal:
5985                                                                  HRM adjustment. */
5986         uint64_t reserved_29_31        : 3;
5987         uint64_t override              : 1;  /**< [ 28: 28](R/W) Reserved.
5988                                                                  Internal:
5989                                                                  Override. */
5990         uint64_t disable_stagger       : 1;  /**< [ 27: 27](R/W) Reserved.
5991                                                                  Internal:
5992                                                                  Disable stagger. */
5993         uint64_t period                : 3;  /**< [ 26: 24](R/W) Reserved.
5994                                                                  Internal:
5995                                                                  Period. */
5996         uint64_t powlim                : 8;  /**< [ 23: 16](R/W) Reserved.
5997                                                                  Internal:
5998                                                                  Power limit. */
5999         uint64_t max_setting           : 8;  /**< [ 15:  8](R/W) Reserved.
6000                                                                  Internal:
6001                                                                  Maximum setting. */
6002         uint64_t min_setting           : 8;  /**< [  7:  0](R/W) Reserved.
6003                                                                  Internal:
6004                                                                  Minimum setting. */
6005 #else /* Word 0 - Little Endian */
6006         uint64_t min_setting           : 8;  /**< [  7:  0](R/W) Reserved.
6007                                                                  Internal:
6008                                                                  Minimum setting. */
6009         uint64_t max_setting           : 8;  /**< [ 15:  8](R/W) Reserved.
6010                                                                  Internal:
6011                                                                  Maximum setting. */
6012         uint64_t powlim                : 8;  /**< [ 23: 16](R/W) Reserved.
6013                                                                  Internal:
6014                                                                  Power limit. */
6015         uint64_t period                : 3;  /**< [ 26: 24](R/W) Reserved.
6016                                                                  Internal:
6017                                                                  Period. */
6018         uint64_t disable_stagger       : 1;  /**< [ 27: 27](R/W) Reserved.
6019                                                                  Internal:
6020                                                                  Disable stagger. */
6021         uint64_t override              : 1;  /**< [ 28: 28](R/W) Reserved.
6022                                                                  Internal:
6023                                                                  Override. */
6024         uint64_t reserved_29_31        : 3;
6025         uint64_t hrm_adjustment        : 8;  /**< [ 39: 32](R/W) Reserved.
6026                                                                  Internal:
6027                                                                  HRM adjustment. */
6028         uint64_t current_setting       : 8;  /**< [ 47: 40](R/W) Reserved.
6029                                                                  Internal:
6030                                                                  Current setting. */
6031         uint64_t average_power         : 8;  /**< [ 55: 48](R/W) Average power.
6032                                                                  Time-averaged dynamic-power estimate for this core, in mA/GHz.
6033                                                                  An approximation of this core's power is calculated with:
6034 
6035                                                                    _ core_power = core_const * core_powered_on + [AVERAGE_POWER] * voltage * freq.
6036 
6037                                                                  Where:
6038 
6039                                                                  _ core_power is in mW.
6040 
6041                                                                  _ core_const is a per-core constant leakage from the HRM power application note, and is in
6042                                                                  mA.
6043 
6044                                                                  _ core_powered_on is a boolean indicating power applied, from RST_PP_POWER\<core_number\>.
6045 
6046                                                                  _ voltage is determined by the platform, perhaps by reading a VRM setting.
6047 
6048                                                                  _ freq is in GHz and is from RST_BOOT[C_MUL] * 0.050, assuming standard 50 MHz ref-clock. */
6049         uint64_t maxpow                : 8;  /**< [ 63: 56](R/W) Reserved.
6050                                                                  Internal:
6051                                                                  Maximum power. */
6052 #endif /* Word 0 - End */
6053     } s;
6054     /* struct bdk_ap_cvm_power_el1_s cn8; */
6055     struct bdk_ap_cvm_power_el1_cn9
6056     {
6057 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6058         uint64_t maxpow                : 8;  /**< [ 63: 56](R/W) Reserved.
6059                                                                  Internal:
6060                                                                  Maximum power. */
6061         uint64_t average_power         : 8;  /**< [ 55: 48](R/W) Average power.
6062                                                                  Time-averaged dynamic-power estimate for this core, in mA/GHz.
6063                                                                  An approximation of this core's power is calculated with:
6064 
6065                                                                    _ core_power = core_const * core_powered_on + [AVERAGE_POWER] * voltage * freq.
6066 
6067                                                                  Where:
6068 
6069                                                                  _ core_power is in mW.
6070 
6071                                                                  _ core_const is a per-core constant leakage from the HRM power application note, and is in
6072                                                                  mA.
6073 
6074                                                                  _ core_powered_on is a boolean indicating power applied, from RST_PP_POWER\<core_number\>.
6075 
6076                                                                  _ voltage is determined by the platform, perhaps by reading a AVS setting.
6077 
6078                                                                  _ freq is in GHz and is from RST_BOOT[C_MUL] * 0.050, assuming standard 50 MHz ref-clock. */
6079         uint64_t current_setting       : 8;  /**< [ 47: 40](R/W) Reserved.
6080                                                                  Internal:
6081                                                                  Current setting. */
6082         uint64_t hrm_adjustment        : 8;  /**< [ 39: 32](R/W) Reserved.
6083                                                                  Internal:
6084                                                                  HRM adjustment. */
6085         uint64_t reserved_29_31        : 3;
6086         uint64_t override              : 1;  /**< [ 28: 28](R/W) Reserved.
6087                                                                  Internal:
6088                                                                  Override. */
6089         uint64_t disable_stagger       : 1;  /**< [ 27: 27](R/W) Reserved.
6090                                                                  Internal:
6091                                                                  Disable stagger. */
6092         uint64_t period                : 3;  /**< [ 26: 24](R/W) Reserved.
6093                                                                  Internal:
6094                                                                  Period. */
6095         uint64_t powlim                : 8;  /**< [ 23: 16](R/W) Reserved.
6096                                                                  Internal:
6097                                                                  Power limit. */
6098         uint64_t max_setting           : 8;  /**< [ 15:  8](R/W) Reserved.
6099                                                                  Internal:
6100                                                                  Maximum setting. */
6101         uint64_t min_setting           : 8;  /**< [  7:  0](R/W) Reserved.
6102                                                                  Internal:
6103                                                                  Minimum setting. */
6104 #else /* Word 0 - Little Endian */
6105         uint64_t min_setting           : 8;  /**< [  7:  0](R/W) Reserved.
6106                                                                  Internal:
6107                                                                  Minimum setting. */
6108         uint64_t max_setting           : 8;  /**< [ 15:  8](R/W) Reserved.
6109                                                                  Internal:
6110                                                                  Maximum setting. */
6111         uint64_t powlim                : 8;  /**< [ 23: 16](R/W) Reserved.
6112                                                                  Internal:
6113                                                                  Power limit. */
6114         uint64_t period                : 3;  /**< [ 26: 24](R/W) Reserved.
6115                                                                  Internal:
6116                                                                  Period. */
6117         uint64_t disable_stagger       : 1;  /**< [ 27: 27](R/W) Reserved.
6118                                                                  Internal:
6119                                                                  Disable stagger. */
6120         uint64_t override              : 1;  /**< [ 28: 28](R/W) Reserved.
6121                                                                  Internal:
6122                                                                  Override. */
6123         uint64_t reserved_29_31        : 3;
6124         uint64_t hrm_adjustment        : 8;  /**< [ 39: 32](R/W) Reserved.
6125                                                                  Internal:
6126                                                                  HRM adjustment. */
6127         uint64_t current_setting       : 8;  /**< [ 47: 40](R/W) Reserved.
6128                                                                  Internal:
6129                                                                  Current setting. */
6130         uint64_t average_power         : 8;  /**< [ 55: 48](R/W) Average power.
6131                                                                  Time-averaged dynamic-power estimate for this core, in mA/GHz.
6132                                                                  An approximation of this core's power is calculated with:
6133 
6134                                                                    _ core_power = core_const * core_powered_on + [AVERAGE_POWER] * voltage * freq.
6135 
6136                                                                  Where:
6137 
6138                                                                  _ core_power is in mW.
6139 
6140                                                                  _ core_const is a per-core constant leakage from the HRM power application note, and is in
6141                                                                  mA.
6142 
6143                                                                  _ core_powered_on is a boolean indicating power applied, from RST_PP_POWER\<core_number\>.
6144 
6145                                                                  _ voltage is determined by the platform, perhaps by reading a AVS setting.
6146 
6147                                                                  _ freq is in GHz and is from RST_BOOT[C_MUL] * 0.050, assuming standard 50 MHz ref-clock. */
6148         uint64_t maxpow                : 8;  /**< [ 63: 56](R/W) Reserved.
6149                                                                  Internal:
6150                                                                  Maximum power. */
6151 #endif /* Word 0 - End */
6152     } cn9;
6153 };
6154 typedef union bdk_ap_cvm_power_el1 bdk_ap_cvm_power_el1_t;
6155 
6156 #define BDK_AP_CVM_POWER_EL1 BDK_AP_CVM_POWER_EL1_FUNC()
6157 static inline uint64_t BDK_AP_CVM_POWER_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_POWER_EL1_FUNC(void)6158 static inline uint64_t BDK_AP_CVM_POWER_EL1_FUNC(void)
6159 {
6160     return 0x3000b000200ll;
6161 }
6162 
6163 #define typedef_BDK_AP_CVM_POWER_EL1 bdk_ap_cvm_power_el1_t
6164 #define bustype_BDK_AP_CVM_POWER_EL1 BDK_CSR_TYPE_SYSREG
6165 #define basename_BDK_AP_CVM_POWER_EL1 "AP_CVM_POWER_EL1"
6166 #define busnum_BDK_AP_CVM_POWER_EL1 0
6167 #define arguments_BDK_AP_CVM_POWER_EL1 -1,-1,-1,-1
6168 
6169 /**
6170  * Register (SYSREG) ap_cvm_scratch#_el1
6171  *
6172  * AP Cavium Scratchpad Register
6173  * This register provides aid to post silicon debug as a scratchpad for software.
6174  */
6175 union bdk_ap_cvm_scratchx_el1
6176 {
6177     uint64_t u;
6178     struct bdk_ap_cvm_scratchx_el1_s
6179     {
6180 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6181         uint64_t data                  : 64; /**< [ 63:  0](R/W) Scratch. */
6182 #else /* Word 0 - Little Endian */
6183         uint64_t data                  : 64; /**< [ 63:  0](R/W) Scratch. */
6184 #endif /* Word 0 - End */
6185     } s;
6186     /* struct bdk_ap_cvm_scratchx_el1_s cn; */
6187 };
6188 typedef union bdk_ap_cvm_scratchx_el1 bdk_ap_cvm_scratchx_el1_t;
6189 
6190 static inline uint64_t BDK_AP_CVM_SCRATCHX_EL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_CVM_SCRATCHX_EL1(unsigned long a)6191 static inline uint64_t BDK_AP_CVM_SCRATCHX_EL1(unsigned long a)
6192 {
6193     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
6194         return 0x3000b050000ll + 0x100ll * ((a) & 0x3);
6195     __bdk_csr_fatal("AP_CVM_SCRATCHX_EL1", 1, a, 0, 0, 0);
6196 }
6197 
6198 #define typedef_BDK_AP_CVM_SCRATCHX_EL1(a) bdk_ap_cvm_scratchx_el1_t
6199 #define bustype_BDK_AP_CVM_SCRATCHX_EL1(a) BDK_CSR_TYPE_SYSREG
6200 #define basename_BDK_AP_CVM_SCRATCHX_EL1(a) "AP_CVM_SCRATCHX_EL1"
6201 #define busnum_BDK_AP_CVM_SCRATCHX_EL1(a) (a)
6202 #define arguments_BDK_AP_CVM_SCRATCHX_EL1(a) (a),-1,-1,-1
6203 
6204 /**
6205  * Register (SYSREG) ap_cvm_statprofcmp_el1
6206  *
6207  * AP Cavium Statistical Profiling Comparator Value Register
6208  */
6209 union bdk_ap_cvm_statprofcmp_el1
6210 {
6211     uint64_t u;
6212     struct bdk_ap_cvm_statprofcmp_el1_s
6213     {
6214 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6215         uint64_t cmp_val               : 64; /**< [ 63:  0](R/W) When enabled (AP_CVM_STATPROFCTL_EL1[DIR_SAMPLE]=1), this register provides
6216                                                                  the value of the address or op-code and mask to be used in directed sample mode.
6217                                                                  The compare mode is indicated by AP_CVM_STATPROFCTL_EL1.OC_PC */
6218 #else /* Word 0 - Little Endian */
6219         uint64_t cmp_val               : 64; /**< [ 63:  0](R/W) When enabled (AP_CVM_STATPROFCTL_EL1[DIR_SAMPLE]=1), this register provides
6220                                                                  the value of the address or op-code and mask to be used in directed sample mode.
6221                                                                  The compare mode is indicated by AP_CVM_STATPROFCTL_EL1.OC_PC */
6222 #endif /* Word 0 - End */
6223     } s;
6224     /* struct bdk_ap_cvm_statprofcmp_el1_s cn; */
6225 };
6226 typedef union bdk_ap_cvm_statprofcmp_el1 bdk_ap_cvm_statprofcmp_el1_t;
6227 
6228 #define BDK_AP_CVM_STATPROFCMP_EL1 BDK_AP_CVM_STATPROFCMP_EL1_FUNC()
6229 static inline uint64_t BDK_AP_CVM_STATPROFCMP_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_STATPROFCMP_EL1_FUNC(void)6230 static inline uint64_t BDK_AP_CVM_STATPROFCMP_EL1_FUNC(void)
6231 {
6232     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
6233         return 0x3000b040100ll;
6234     __bdk_csr_fatal("AP_CVM_STATPROFCMP_EL1", 0, 0, 0, 0, 0);
6235 }
6236 
6237 #define typedef_BDK_AP_CVM_STATPROFCMP_EL1 bdk_ap_cvm_statprofcmp_el1_t
6238 #define bustype_BDK_AP_CVM_STATPROFCMP_EL1 BDK_CSR_TYPE_SYSREG
6239 #define basename_BDK_AP_CVM_STATPROFCMP_EL1 "AP_CVM_STATPROFCMP_EL1"
6240 #define busnum_BDK_AP_CVM_STATPROFCMP_EL1 0
6241 #define arguments_BDK_AP_CVM_STATPROFCMP_EL1 -1,-1,-1,-1
6242 
6243 /**
6244  * Register (SYSREG) ap_cvm_statprofctl_el1
6245  *
6246  * AP Cavium Statistical Profiling Configuration Register
6247  */
6248 union bdk_ap_cvm_statprofctl_el1
6249 {
6250     uint64_t u;
6251     struct bdk_ap_cvm_statprofctl_el1_s
6252     {
6253 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6254         uint64_t reserved_6_63         : 58;
6255         uint64_t el                    : 3;  /**< [  5:  3](R/W) When in directed sample mode, indicates whether the instruction matching
6256                                                                  logic includes a comparison of the EL of the target instruction.
6257                                                                  0x0 = Do not include an EL compare.
6258                                                                  0x4 = Instruction match if value match and instruction EL=0.
6259                                                                  0x5 = Instruction match if value match and instruction EL=1.
6260                                                                  0x6 = Instruction match if value match and instruction EL=2.
6261                                                                  0x7 = Instruction match if value match and instruction EL=3. */
6262         uint64_t oc_pc                 : 1;  /**< [  2:  2](R/W) When in directed sample mode, indicates whether the instruction to be
6263                                                                  sample is found by matching the PC or the OpCode.
6264                                                                  0 = Comparator matches AP_CVM_STATPROFCMP_EL1[52:2] against instruction PC.
6265                                                                  1 = Comparator matches AP_CVM_STATPROFCMP_EL1[31:0] against instruction opcode
6266                                                                     with bits enabled for comparison with a corresponding 1 in AP_CVM_STATPROFCMP_EL1[63:32]. */
6267         uint64_t dir_sample            : 1;  /**< [  1:  1](R/W) When set, replaces statistical profile's random sample selection logic
6268                                                                  with the output of the instruction and/or address comparators from the
6269                                                                  trace logic. This provides the ability to profile a specific instruction.
6270                                                                  Note that this feature will not function if trace is enabled. */
6271         uint64_t ernd                  : 1;  /**< [  0:  0](R/W) Provides the value for AP_PMSIDR_EL1[ERND]. This field describes how
6272                                                                  randomization is used in selecting the sample. See AP_PMSIDR_EL1[ERND]. */
6273 #else /* Word 0 - Little Endian */
6274         uint64_t ernd                  : 1;  /**< [  0:  0](R/W) Provides the value for AP_PMSIDR_EL1[ERND]. This field describes how
6275                                                                  randomization is used in selecting the sample. See AP_PMSIDR_EL1[ERND]. */
6276         uint64_t dir_sample            : 1;  /**< [  1:  1](R/W) When set, replaces statistical profile's random sample selection logic
6277                                                                  with the output of the instruction and/or address comparators from the
6278                                                                  trace logic. This provides the ability to profile a specific instruction.
6279                                                                  Note that this feature will not function if trace is enabled. */
6280         uint64_t oc_pc                 : 1;  /**< [  2:  2](R/W) When in directed sample mode, indicates whether the instruction to be
6281                                                                  sample is found by matching the PC or the OpCode.
6282                                                                  0 = Comparator matches AP_CVM_STATPROFCMP_EL1[52:2] against instruction PC.
6283                                                                  1 = Comparator matches AP_CVM_STATPROFCMP_EL1[31:0] against instruction opcode
6284                                                                     with bits enabled for comparison with a corresponding 1 in AP_CVM_STATPROFCMP_EL1[63:32]. */
6285         uint64_t el                    : 3;  /**< [  5:  3](R/W) When in directed sample mode, indicates whether the instruction matching
6286                                                                  logic includes a comparison of the EL of the target instruction.
6287                                                                  0x0 = Do not include an EL compare.
6288                                                                  0x4 = Instruction match if value match and instruction EL=0.
6289                                                                  0x5 = Instruction match if value match and instruction EL=1.
6290                                                                  0x6 = Instruction match if value match and instruction EL=2.
6291                                                                  0x7 = Instruction match if value match and instruction EL=3. */
6292         uint64_t reserved_6_63         : 58;
6293 #endif /* Word 0 - End */
6294     } s;
6295     /* struct bdk_ap_cvm_statprofctl_el1_s cn; */
6296 };
6297 typedef union bdk_ap_cvm_statprofctl_el1 bdk_ap_cvm_statprofctl_el1_t;
6298 
6299 #define BDK_AP_CVM_STATPROFCTL_EL1 BDK_AP_CVM_STATPROFCTL_EL1_FUNC()
6300 static inline uint64_t BDK_AP_CVM_STATPROFCTL_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_STATPROFCTL_EL1_FUNC(void)6301 static inline uint64_t BDK_AP_CVM_STATPROFCTL_EL1_FUNC(void)
6302 {
6303     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
6304         return 0x3000b040000ll;
6305     __bdk_csr_fatal("AP_CVM_STATPROFCTL_EL1", 0, 0, 0, 0, 0);
6306 }
6307 
6308 #define typedef_BDK_AP_CVM_STATPROFCTL_EL1 bdk_ap_cvm_statprofctl_el1_t
6309 #define bustype_BDK_AP_CVM_STATPROFCTL_EL1 BDK_CSR_TYPE_SYSREG
6310 #define basename_BDK_AP_CVM_STATPROFCTL_EL1 "AP_CVM_STATPROFCTL_EL1"
6311 #define busnum_BDK_AP_CVM_STATPROFCTL_EL1 0
6312 #define arguments_BDK_AP_CVM_STATPROFCTL_EL1 -1,-1,-1,-1
6313 
6314 /**
6315  * Register (SYSREG) ap_cvm_trapaddr#_el3
6316  *
6317  * AP Cavium Trap Address Register
6318  * This register provides ternary match bits for physical address traps.
6319  *
6320  * Usage Constraints:
6321  *   This register is R/W at EL3.
6322  *
6323  * Traps and Enables:
6324  *   There are no traps nor enables affecting this register.
6325  *
6326  * Configurations:
6327  *   R/W fields in this register reset to IMPLEMENTATION DEFINED values that might be UNKNOWN.
6328  *   Cavium implementations will reset to 0x0.
6329  */
6330 union bdk_ap_cvm_trapaddrx_el3
6331 {
6332     uint64_t u;
6333     struct bdk_ap_cvm_trapaddrx_el3_s
6334     {
6335 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6336         uint64_t stld                  : 2;  /**< [ 63: 62](R/W) 0x0 = Don't match (though redundant with enable bits in AP_CVM_TRAPCTL()_EL3).
6337                                                                  0x1 = Match load.
6338                                                                  0x2 = Match store.
6339                                                                  0x3 = Match load and store. */
6340         uint64_t reserved_52_61        : 10;
6341         uint64_t pa                    : 45; /**< [ 51:  7](R/W) Physical address match bits \<51:7\>. */
6342         uint64_t reserved_0_6          : 7;
6343 #else /* Word 0 - Little Endian */
6344         uint64_t reserved_0_6          : 7;
6345         uint64_t pa                    : 45; /**< [ 51:  7](R/W) Physical address match bits \<51:7\>. */
6346         uint64_t reserved_52_61        : 10;
6347         uint64_t stld                  : 2;  /**< [ 63: 62](R/W) 0x0 = Don't match (though redundant with enable bits in AP_CVM_TRAPCTL()_EL3).
6348                                                                  0x1 = Match load.
6349                                                                  0x2 = Match store.
6350                                                                  0x3 = Match load and store. */
6351 #endif /* Word 0 - End */
6352     } s;
6353     /* struct bdk_ap_cvm_trapaddrx_el3_s cn; */
6354 };
6355 typedef union bdk_ap_cvm_trapaddrx_el3 bdk_ap_cvm_trapaddrx_el3_t;
6356 
6357 static inline uint64_t BDK_AP_CVM_TRAPADDRX_EL3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_CVM_TRAPADDRX_EL3(unsigned long a)6358 static inline uint64_t BDK_AP_CVM_TRAPADDRX_EL3(unsigned long a)
6359 {
6360     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a>=4)&&(a<=7)))
6361         return 0x3060b070000ll + 0x100ll * ((a) & 0x7);
6362     __bdk_csr_fatal("AP_CVM_TRAPADDRX_EL3", 1, a, 0, 0, 0);
6363 }
6364 
6365 #define typedef_BDK_AP_CVM_TRAPADDRX_EL3(a) bdk_ap_cvm_trapaddrx_el3_t
6366 #define bustype_BDK_AP_CVM_TRAPADDRX_EL3(a) BDK_CSR_TYPE_SYSREG
6367 #define basename_BDK_AP_CVM_TRAPADDRX_EL3(a) "AP_CVM_TRAPADDRX_EL3"
6368 #define busnum_BDK_AP_CVM_TRAPADDRX_EL3(a) (a)
6369 #define arguments_BDK_AP_CVM_TRAPADDRX_EL3(a) (a),-1,-1,-1
6370 
6371 /**
6372  * Register (SYSREG) ap_cvm_trapaddrena#_el3
6373  *
6374  * AP Cavium Trap Address Enable Register
6375  * This register provides ternary enable bits for physical address traps.
6376  *
6377  * Usage Constraints:
6378  *   This register is R/W at EL3.
6379  *
6380  * Traps and Enables:
6381  *   There are no traps nor enables affecting this register.
6382  *
6383  * Configurations:
6384  *   R/W fields in this register reset to IMPLEMENTATION DEFINED values that might be UNKNOWN.
6385  *   Cavium implementations will reset to 0x0.
6386  */
6387 union bdk_ap_cvm_trapaddrenax_el3
6388 {
6389     uint64_t u;
6390     struct bdk_ap_cvm_trapaddrenax_el3_s
6391     {
6392 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6393         uint64_t reserved_52_63        : 12;
6394         uint64_t pa_ena                : 45; /**< [ 51:  7](R/W) Physical address match enable bits \<51:7\>. */
6395         uint64_t reserved_0_6          : 7;
6396 #else /* Word 0 - Little Endian */
6397         uint64_t reserved_0_6          : 7;
6398         uint64_t pa_ena                : 45; /**< [ 51:  7](R/W) Physical address match enable bits \<51:7\>. */
6399         uint64_t reserved_52_63        : 12;
6400 #endif /* Word 0 - End */
6401     } s;
6402     /* struct bdk_ap_cvm_trapaddrenax_el3_s cn; */
6403 };
6404 typedef union bdk_ap_cvm_trapaddrenax_el3 bdk_ap_cvm_trapaddrenax_el3_t;
6405 
6406 static inline uint64_t BDK_AP_CVM_TRAPADDRENAX_EL3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_CVM_TRAPADDRENAX_EL3(unsigned long a)6407 static inline uint64_t BDK_AP_CVM_TRAPADDRENAX_EL3(unsigned long a)
6408 {
6409     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a>=4)&&(a<=7)))
6410         return 0x3060b090000ll + 0x100ll * ((a) & 0x7);
6411     __bdk_csr_fatal("AP_CVM_TRAPADDRENAX_EL3", 1, a, 0, 0, 0);
6412 }
6413 
6414 #define typedef_BDK_AP_CVM_TRAPADDRENAX_EL3(a) bdk_ap_cvm_trapaddrenax_el3_t
6415 #define bustype_BDK_AP_CVM_TRAPADDRENAX_EL3(a) BDK_CSR_TYPE_SYSREG
6416 #define basename_BDK_AP_CVM_TRAPADDRENAX_EL3(a) "AP_CVM_TRAPADDRENAX_EL3"
6417 #define busnum_BDK_AP_CVM_TRAPADDRENAX_EL3(a) (a)
6418 #define arguments_BDK_AP_CVM_TRAPADDRENAX_EL3(a) (a),-1,-1,-1
6419 
6420 /**
6421  * Register (SYSREG) ap_cvm_trapctl#_el3
6422  *
6423  * AP Cavium Trap Control Register
6424  * This register provides control and identification of the Cavium physical address and
6425  * instruction trap functionality. There are eight of these registers. Registers zero
6426  * through three apply to the instruction matchers and registers four through seven apply
6427  * to the address matchers.
6428  *
6429  * Usage Constraints:
6430  *   This register is R/W at EL3.
6431  *
6432  * Traps and Enables:
6433  *   There are no traps nor enables affecting this register.
6434  *
6435  * Configurations:
6436  *   R/W fields in this register reset to IMPLEMENTATION DEFINED values that might be UNKNOWN.
6437  *   Cavium implementations will reset to 0x0.
6438  */
6439 union bdk_ap_cvm_trapctlx_el3
6440 {
6441     uint64_t u;
6442     struct bdk_ap_cvm_trapctlx_el3_s
6443     {
6444 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6445         uint64_t reserved_37_63        : 27;
6446         uint64_t el2                   : 1;  /**< [ 36: 36](R/W) Trap accesses from EL2. */
6447         uint64_t el1ns                 : 1;  /**< [ 35: 35](R/W) Trap accesses from EL1NS. */
6448         uint64_t el1s                  : 1;  /**< [ 34: 34](R/W) Trap accesses from EL1S. */
6449         uint64_t el0ns                 : 1;  /**< [ 33: 33](R/W) Trap accesses from EL0NS. */
6450         uint64_t el0s                  : 1;  /**< [ 32: 32](R/W) Trap accesses from EL0S. */
6451         uint64_t reserved_8_31         : 24;
6452         uint64_t action                : 4;  /**< [  7:  4](R/W) Trap action:
6453                                                                    0x0 = Trap to EL3 on a match.
6454                                                                    0x1 = Flush the instruction pipeline and reissue instruction. For instruction matches
6455                                                                  only, otherwise UNPREDICTABLE.
6456                                                                    0x2-0xF = Reserved. */
6457         uint64_t mtype                 : 3;  /**< [  3:  1](R/W) Read-only. Typs of matcher for software capability discovery:
6458                                                                    0x0 = Not present.
6459                                                                    0x1 = Physical address matcher. This value is advertised in indices 4..7.
6460                                                                    0x2 = Instruction matcher. This value is advertised in indices 0..3. */
6461         uint64_t ena                   : 1;  /**< [  0:  0](R/W) Enable. */
6462 #else /* Word 0 - Little Endian */
6463         uint64_t ena                   : 1;  /**< [  0:  0](R/W) Enable. */
6464         uint64_t mtype                 : 3;  /**< [  3:  1](R/W) Read-only. Typs of matcher for software capability discovery:
6465                                                                    0x0 = Not present.
6466                                                                    0x1 = Physical address matcher. This value is advertised in indices 4..7.
6467                                                                    0x2 = Instruction matcher. This value is advertised in indices 0..3. */
6468         uint64_t action                : 4;  /**< [  7:  4](R/W) Trap action:
6469                                                                    0x0 = Trap to EL3 on a match.
6470                                                                    0x1 = Flush the instruction pipeline and reissue instruction. For instruction matches
6471                                                                  only, otherwise UNPREDICTABLE.
6472                                                                    0x2-0xF = Reserved. */
6473         uint64_t reserved_8_31         : 24;
6474         uint64_t el0s                  : 1;  /**< [ 32: 32](R/W) Trap accesses from EL0S. */
6475         uint64_t el0ns                 : 1;  /**< [ 33: 33](R/W) Trap accesses from EL0NS. */
6476         uint64_t el1s                  : 1;  /**< [ 34: 34](R/W) Trap accesses from EL1S. */
6477         uint64_t el1ns                 : 1;  /**< [ 35: 35](R/W) Trap accesses from EL1NS. */
6478         uint64_t el2                   : 1;  /**< [ 36: 36](R/W) Trap accesses from EL2. */
6479         uint64_t reserved_37_63        : 27;
6480 #endif /* Word 0 - End */
6481     } s;
6482     /* struct bdk_ap_cvm_trapctlx_el3_s cn; */
6483 };
6484 typedef union bdk_ap_cvm_trapctlx_el3 bdk_ap_cvm_trapctlx_el3_t;
6485 
6486 static inline uint64_t BDK_AP_CVM_TRAPCTLX_EL3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_CVM_TRAPCTLX_EL3(unsigned long a)6487 static inline uint64_t BDK_AP_CVM_TRAPCTLX_EL3(unsigned long a)
6488 {
6489     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
6490         return 0x3060b080000ll + 0x100ll * ((a) & 0x7);
6491     __bdk_csr_fatal("AP_CVM_TRAPCTLX_EL3", 1, a, 0, 0, 0);
6492 }
6493 
6494 #define typedef_BDK_AP_CVM_TRAPCTLX_EL3(a) bdk_ap_cvm_trapctlx_el3_t
6495 #define bustype_BDK_AP_CVM_TRAPCTLX_EL3(a) BDK_CSR_TYPE_SYSREG
6496 #define basename_BDK_AP_CVM_TRAPCTLX_EL3(a) "AP_CVM_TRAPCTLX_EL3"
6497 #define busnum_BDK_AP_CVM_TRAPCTLX_EL3(a) (a)
6498 #define arguments_BDK_AP_CVM_TRAPCTLX_EL3(a) (a),-1,-1,-1
6499 
6500 /**
6501  * Register (SYSREG) ap_cvm_trapinsn#_el3
6502  *
6503  * AP Cavium Trap Instructions Register
6504  * This register provides ternary match and enable bits for instruction word traps.
6505  *
6506  * Usage Constraints:
6507  *   This register is R/W at EL3.
6508  *
6509  * Traps and Enables:
6510  *   There are no traps nor enables affecting this register.
6511  *
6512  * Configurations:
6513  *   R/W fields in this register reset to IMPLEMENTATION DEFINED values that might be UNKNOWN.
6514  *   Cavium implementations will reset to 0x0.
6515  */
6516 union bdk_ap_cvm_trapinsnx_el3
6517 {
6518     uint64_t u;
6519     struct bdk_ap_cvm_trapinsnx_el3_s
6520     {
6521 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6522         uint64_t insn_ena              : 32; /**< [ 63: 32](R/W) Instruction match bits. */
6523         uint64_t insn                  : 32; /**< [ 31:  0](R/W) Instruction match enable bits. */
6524 #else /* Word 0 - Little Endian */
6525         uint64_t insn                  : 32; /**< [ 31:  0](R/W) Instruction match enable bits. */
6526         uint64_t insn_ena              : 32; /**< [ 63: 32](R/W) Instruction match bits. */
6527 #endif /* Word 0 - End */
6528     } s;
6529     /* struct bdk_ap_cvm_trapinsnx_el3_s cn; */
6530 };
6531 typedef union bdk_ap_cvm_trapinsnx_el3 bdk_ap_cvm_trapinsnx_el3_t;
6532 
6533 static inline uint64_t BDK_AP_CVM_TRAPINSNX_EL3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_CVM_TRAPINSNX_EL3(unsigned long a)6534 static inline uint64_t BDK_AP_CVM_TRAPINSNX_EL3(unsigned long a)
6535 {
6536     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
6537         return 0x3060b090000ll + 0x100ll * ((a) & 0x3);
6538     __bdk_csr_fatal("AP_CVM_TRAPINSNX_EL3", 1, a, 0, 0, 0);
6539 }
6540 
6541 #define typedef_BDK_AP_CVM_TRAPINSNX_EL3(a) bdk_ap_cvm_trapinsnx_el3_t
6542 #define bustype_BDK_AP_CVM_TRAPINSNX_EL3(a) BDK_CSR_TYPE_SYSREG
6543 #define basename_BDK_AP_CVM_TRAPINSNX_EL3(a) "AP_CVM_TRAPINSNX_EL3"
6544 #define busnum_BDK_AP_CVM_TRAPINSNX_EL3(a) (a)
6545 #define arguments_BDK_AP_CVM_TRAPINSNX_EL3(a) (a),-1,-1,-1
6546 
6547 /**
6548  * Register (SYSREG) ap_cvm_trapopc_el3
6549  *
6550  * AP Cavium Trap Exception Opcode Register
6551  * This register stores syndrome information on a trap fault.
6552  *
6553  * Usage Constraints:
6554  *   This register is R/W at EL3.
6555  * Traps and Enables:
6556  *   There are no traps nor enables affecting this register.
6557  * Configurations:
6558  *   RW fields in this register reset to IMPLEMENTATION DEFINED values that might be UNKNOWN.
6559  *   Cavium implementations will reset to 0x0.
6560  */
6561 union bdk_ap_cvm_trapopc_el3
6562 {
6563     uint64_t u;
6564     struct bdk_ap_cvm_trapopc_el3_s
6565     {
6566 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6567         uint64_t reserved_37_63        : 27;
6568         uint64_t regset                : 5;  /**< [ 36: 32](R/W) Matching register set.
6569                                                                  Values zero through 15 refer to physical address match register sets and values 16-31
6570                                                                  refer to instruction match register sets. */
6571         uint64_t insn                  : 32; /**< [ 31:  0](R/W) Instruction word that caused the fault. */
6572 #else /* Word 0 - Little Endian */
6573         uint64_t insn                  : 32; /**< [ 31:  0](R/W) Instruction word that caused the fault. */
6574         uint64_t regset                : 5;  /**< [ 36: 32](R/W) Matching register set.
6575                                                                  Values zero through 15 refer to physical address match register sets and values 16-31
6576                                                                  refer to instruction match register sets. */
6577         uint64_t reserved_37_63        : 27;
6578 #endif /* Word 0 - End */
6579     } s;
6580     /* struct bdk_ap_cvm_trapopc_el3_s cn; */
6581 };
6582 typedef union bdk_ap_cvm_trapopc_el3 bdk_ap_cvm_trapopc_el3_t;
6583 
6584 #define BDK_AP_CVM_TRAPOPC_EL3 BDK_AP_CVM_TRAPOPC_EL3_FUNC()
6585 static inline uint64_t BDK_AP_CVM_TRAPOPC_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_TRAPOPC_EL3_FUNC(void)6586 static inline uint64_t BDK_AP_CVM_TRAPOPC_EL3_FUNC(void)
6587 {
6588     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
6589         return 0x3060b060100ll;
6590     __bdk_csr_fatal("AP_CVM_TRAPOPC_EL3", 0, 0, 0, 0, 0);
6591 }
6592 
6593 #define typedef_BDK_AP_CVM_TRAPOPC_EL3 bdk_ap_cvm_trapopc_el3_t
6594 #define bustype_BDK_AP_CVM_TRAPOPC_EL3 BDK_CSR_TYPE_SYSREG
6595 #define basename_BDK_AP_CVM_TRAPOPC_EL3 "AP_CVM_TRAPOPC_EL3"
6596 #define busnum_BDK_AP_CVM_TRAPOPC_EL3 0
6597 #define arguments_BDK_AP_CVM_TRAPOPC_EL3 -1,-1,-1,-1
6598 
6599 /**
6600  * Register (SYSREG) ap_cvm_xlatdata0_el1
6601  *
6602  * AP Cavium Translation Data 0 EL1 Register
6603  */
6604 union bdk_ap_cvm_xlatdata0_el1
6605 {
6606     uint64_t u;
6607     struct bdk_ap_cvm_xlatdata0_el1_s
6608     {
6609 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6610         uint64_t par                   : 2;  /**< [ 63: 62](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6611         uint64_t reserved_54_61        : 8;
6612         uint64_t walk                  : 2;  /**< [ 53: 52](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6613         uint64_t ng                    : 1;  /**< [ 51: 51](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6614         uint64_t reserved_50           : 1;
6615         uint64_t nsec                  : 1;  /**< [ 49: 49](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6616         uint64_t reserved_48           : 1;
6617         uint64_t ppn                   : 36; /**< [ 47: 12](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6618         uint64_t reserved_10_11        : 2;
6619         uint64_t sh1                   : 2;  /**< [  9:  8](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6620         uint64_t ap1                   : 2;  /**< [  7:  6](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6621         uint64_t xn1                   : 1;  /**< [  5:  5](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6622         uint64_t pxn1                  : 1;  /**< [  4:  4](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6623         uint64_t attr1                 : 4;  /**< [  3:  0](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6624 #else /* Word 0 - Little Endian */
6625         uint64_t attr1                 : 4;  /**< [  3:  0](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6626         uint64_t pxn1                  : 1;  /**< [  4:  4](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6627         uint64_t xn1                   : 1;  /**< [  5:  5](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6628         uint64_t ap1                   : 2;  /**< [  7:  6](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6629         uint64_t sh1                   : 2;  /**< [  9:  8](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6630         uint64_t reserved_10_11        : 2;
6631         uint64_t ppn                   : 36; /**< [ 47: 12](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6632         uint64_t reserved_48           : 1;
6633         uint64_t nsec                  : 1;  /**< [ 49: 49](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6634         uint64_t reserved_50           : 1;
6635         uint64_t ng                    : 1;  /**< [ 51: 51](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6636         uint64_t walk                  : 2;  /**< [ 53: 52](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6637         uint64_t reserved_54_61        : 8;
6638         uint64_t par                   : 2;  /**< [ 63: 62](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6639 #endif /* Word 0 - End */
6640     } s;
6641     /* struct bdk_ap_cvm_xlatdata0_el1_s cn; */
6642 };
6643 typedef union bdk_ap_cvm_xlatdata0_el1 bdk_ap_cvm_xlatdata0_el1_t;
6644 
6645 #define BDK_AP_CVM_XLATDATA0_EL1 BDK_AP_CVM_XLATDATA0_EL1_FUNC()
6646 static inline uint64_t BDK_AP_CVM_XLATDATA0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_XLATDATA0_EL1_FUNC(void)6647 static inline uint64_t BDK_AP_CVM_XLATDATA0_EL1_FUNC(void)
6648 {
6649     return 0x3000b050400ll;
6650 }
6651 
6652 #define typedef_BDK_AP_CVM_XLATDATA0_EL1 bdk_ap_cvm_xlatdata0_el1_t
6653 #define bustype_BDK_AP_CVM_XLATDATA0_EL1 BDK_CSR_TYPE_SYSREG
6654 #define basename_BDK_AP_CVM_XLATDATA0_EL1 "AP_CVM_XLATDATA0_EL1"
6655 #define busnum_BDK_AP_CVM_XLATDATA0_EL1 0
6656 #define arguments_BDK_AP_CVM_XLATDATA0_EL1 -1,-1,-1,-1
6657 
6658 /**
6659  * Register (SYSREG) ap_cvm_xlatdata1_el1
6660  *
6661  * AP Cavium Translation Data 1 EL1 Register
6662  */
6663 union bdk_ap_cvm_xlatdata1_el1
6664 {
6665     uint64_t u;
6666     struct bdk_ap_cvm_xlatdata1_el1_s
6667     {
6668 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6669         uint64_t reserved_63           : 1;
6670         uint64_t ent2                  : 9;  /**< [ 62: 54](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6671         uint64_t reserved_45_53        : 9;
6672         uint64_t ent1                  : 9;  /**< [ 44: 36](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6673         uint64_t reserved_34_35        : 2;
6674         uint64_t mask                  : 22; /**< [ 33: 12](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6675         uint64_t reserved_10_11        : 2;
6676         uint64_t sh2                   : 2;  /**< [  9:  8](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6677         uint64_t ap2                   : 2;  /**< [  7:  6](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6678         uint64_t xn2                   : 1;  /**< [  5:  5](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6679         uint64_t pxn2                  : 1;  /**< [  4:  4](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6680         uint64_t attr2                 : 4;  /**< [  3:  0](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6681 #else /* Word 0 - Little Endian */
6682         uint64_t attr2                 : 4;  /**< [  3:  0](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6683         uint64_t pxn2                  : 1;  /**< [  4:  4](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6684         uint64_t xn2                   : 1;  /**< [  5:  5](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6685         uint64_t ap2                   : 2;  /**< [  7:  6](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6686         uint64_t sh2                   : 2;  /**< [  9:  8](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6687         uint64_t reserved_10_11        : 2;
6688         uint64_t mask                  : 22; /**< [ 33: 12](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6689         uint64_t reserved_34_35        : 2;
6690         uint64_t ent1                  : 9;  /**< [ 44: 36](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6691         uint64_t reserved_45_53        : 9;
6692         uint64_t ent2                  : 9;  /**< [ 62: 54](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6693         uint64_t reserved_63           : 1;
6694 #endif /* Word 0 - End */
6695     } s;
6696     /* struct bdk_ap_cvm_xlatdata1_el1_s cn; */
6697 };
6698 typedef union bdk_ap_cvm_xlatdata1_el1 bdk_ap_cvm_xlatdata1_el1_t;
6699 
6700 #define BDK_AP_CVM_XLATDATA1_EL1 BDK_AP_CVM_XLATDATA1_EL1_FUNC()
6701 static inline uint64_t BDK_AP_CVM_XLATDATA1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_XLATDATA1_EL1_FUNC(void)6702 static inline uint64_t BDK_AP_CVM_XLATDATA1_EL1_FUNC(void)
6703 {
6704     return 0x3000b050500ll;
6705 }
6706 
6707 #define typedef_BDK_AP_CVM_XLATDATA1_EL1 bdk_ap_cvm_xlatdata1_el1_t
6708 #define bustype_BDK_AP_CVM_XLATDATA1_EL1 BDK_CSR_TYPE_SYSREG
6709 #define basename_BDK_AP_CVM_XLATDATA1_EL1 "AP_CVM_XLATDATA1_EL1"
6710 #define busnum_BDK_AP_CVM_XLATDATA1_EL1 0
6711 #define arguments_BDK_AP_CVM_XLATDATA1_EL1 -1,-1,-1,-1
6712 
6713 /**
6714  * Register (SYSREG) ap_cvm_xlatvtag0_el1
6715  *
6716  * AP Cavium Translation Tag 0 EL1 Register
6717  */
6718 union bdk_ap_cvm_xlatvtag0_el1
6719 {
6720     uint64_t u;
6721     struct bdk_ap_cvm_xlatvtag0_el1_s
6722     {
6723 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6724         uint64_t level                 : 2;  /**< [ 63: 62](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6725         uint64_t eva_asid              : 6;  /**< [ 61: 56](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6726         uint64_t eva_vmid              : 4;  /**< [ 55: 52](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6727         uint64_t ng                    : 1;  /**< [ 51: 51](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6728         uint64_t el_1or0               : 1;  /**< [ 50: 50](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6729         uint64_t nsec                  : 1;  /**< [ 49: 49](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6730         uint64_t r                     : 1;  /**< [ 48: 48](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6731         uint64_t vpn                   : 36; /**< [ 47: 12](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6732         uint64_t reserved_1_11         : 11;
6733         uint64_t val                   : 1;  /**< [  0:  0](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6734 #else /* Word 0 - Little Endian */
6735         uint64_t val                   : 1;  /**< [  0:  0](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6736         uint64_t reserved_1_11         : 11;
6737         uint64_t vpn                   : 36; /**< [ 47: 12](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6738         uint64_t r                     : 1;  /**< [ 48: 48](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6739         uint64_t nsec                  : 1;  /**< [ 49: 49](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6740         uint64_t el_1or0               : 1;  /**< [ 50: 50](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6741         uint64_t ng                    : 1;  /**< [ 51: 51](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6742         uint64_t eva_vmid              : 4;  /**< [ 55: 52](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6743         uint64_t eva_asid              : 6;  /**< [ 61: 56](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6744         uint64_t level                 : 2;  /**< [ 63: 62](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6745 #endif /* Word 0 - End */
6746     } s;
6747     /* struct bdk_ap_cvm_xlatvtag0_el1_s cn; */
6748 };
6749 typedef union bdk_ap_cvm_xlatvtag0_el1 bdk_ap_cvm_xlatvtag0_el1_t;
6750 
6751 #define BDK_AP_CVM_XLATVTAG0_EL1 BDK_AP_CVM_XLATVTAG0_EL1_FUNC()
6752 static inline uint64_t BDK_AP_CVM_XLATVTAG0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_XLATVTAG0_EL1_FUNC(void)6753 static inline uint64_t BDK_AP_CVM_XLATVTAG0_EL1_FUNC(void)
6754 {
6755     return 0x3000b050600ll;
6756 }
6757 
6758 #define typedef_BDK_AP_CVM_XLATVTAG0_EL1 bdk_ap_cvm_xlatvtag0_el1_t
6759 #define bustype_BDK_AP_CVM_XLATVTAG0_EL1 BDK_CSR_TYPE_SYSREG
6760 #define basename_BDK_AP_CVM_XLATVTAG0_EL1 "AP_CVM_XLATVTAG0_EL1"
6761 #define busnum_BDK_AP_CVM_XLATVTAG0_EL1 0
6762 #define arguments_BDK_AP_CVM_XLATVTAG0_EL1 -1,-1,-1,-1
6763 
6764 /**
6765  * Register (SYSREG) ap_cvm_xlatvtag1_el1
6766  *
6767  * AP Cavium Translation Tag 1 EL1 Register
6768  */
6769 union bdk_ap_cvm_xlatvtag1_el1
6770 {
6771     uint64_t u;
6772     struct bdk_ap_cvm_xlatvtag1_el1_s
6773     {
6774 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6775         uint64_t reserved_57_63        : 7;
6776         uint64_t ent2                  : 9;  /**< [ 56: 48](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6777         uint64_t reserved_45_47        : 3;
6778         uint64_t ent1                  : 9;  /**< [ 44: 36](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6779         uint64_t reserved_34_35        : 2;
6780         uint64_t mask                  : 22; /**< [ 33: 12](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6781         uint64_t reserved_2_11         : 10;
6782         uint64_t stage2                : 1;  /**< [  1:  1](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6783         uint64_t stage1                : 1;  /**< [  0:  0](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6784 #else /* Word 0 - Little Endian */
6785         uint64_t stage1                : 1;  /**< [  0:  0](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6786         uint64_t stage2                : 1;  /**< [  1:  1](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6787         uint64_t reserved_2_11         : 10;
6788         uint64_t mask                  : 22; /**< [ 33: 12](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6789         uint64_t reserved_34_35        : 2;
6790         uint64_t ent1                  : 9;  /**< [ 44: 36](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6791         uint64_t reserved_45_47        : 3;
6792         uint64_t ent2                  : 9;  /**< [ 56: 48](RO) SYS[CvmCACHE] debug read data from uTLB/MTLB/WCU. */
6793         uint64_t reserved_57_63        : 7;
6794 #endif /* Word 0 - End */
6795     } s;
6796     /* struct bdk_ap_cvm_xlatvtag1_el1_s cn; */
6797 };
6798 typedef union bdk_ap_cvm_xlatvtag1_el1 bdk_ap_cvm_xlatvtag1_el1_t;
6799 
6800 #define BDK_AP_CVM_XLATVTAG1_EL1 BDK_AP_CVM_XLATVTAG1_EL1_FUNC()
6801 static inline uint64_t BDK_AP_CVM_XLATVTAG1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVM_XLATVTAG1_EL1_FUNC(void)6802 static inline uint64_t BDK_AP_CVM_XLATVTAG1_EL1_FUNC(void)
6803 {
6804     return 0x3000b050700ll;
6805 }
6806 
6807 #define typedef_BDK_AP_CVM_XLATVTAG1_EL1 bdk_ap_cvm_xlatvtag1_el1_t
6808 #define bustype_BDK_AP_CVM_XLATVTAG1_EL1 BDK_CSR_TYPE_SYSREG
6809 #define basename_BDK_AP_CVM_XLATVTAG1_EL1 "AP_CVM_XLATVTAG1_EL1"
6810 #define busnum_BDK_AP_CVM_XLATVTAG1_EL1 0
6811 #define arguments_BDK_AP_CVM_XLATVTAG1_EL1 -1,-1,-1,-1
6812 
6813 /**
6814  * Register (SYSREG) ap_cvmctl2_el1
6815  *
6816  * AP Cavium Control Register
6817  * This register provides Cavium-specific control information.
6818  */
6819 union bdk_ap_cvmctl2_el1
6820 {
6821     uint64_t u;
6822     struct bdk_ap_cvmctl2_el1_s
6823     {
6824 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6825         uint64_t reserved_12_63        : 52;
6826         uint64_t livelock_stall_detect : 4;  /**< [ 11:  8](R/W) Livelock stall detector. 0=disable, cycles 16*1\<\<[[11:8] */
6827         uint64_t reserved_4_7          : 4;
6828         uint64_t reduce_map_bandwidth  : 2;  /**< [  3:  2](R/W) Reduce map bandwidth to 1-3 instr/cycle (also reduces max inflight instructions to 32,64,96) */
6829         uint64_t allow_one_ifi         : 1;  /**< [  1:  1](R/W) Allow only one inflight instruction. */
6830         uint64_t allow_one_ifmr        : 1;  /**< [  0:  0](R/W) Allow only one inflight memory reference. */
6831 #else /* Word 0 - Little Endian */
6832         uint64_t allow_one_ifmr        : 1;  /**< [  0:  0](R/W) Allow only one inflight memory reference. */
6833         uint64_t allow_one_ifi         : 1;  /**< [  1:  1](R/W) Allow only one inflight instruction. */
6834         uint64_t reduce_map_bandwidth  : 2;  /**< [  3:  2](R/W) Reduce map bandwidth to 1-3 instr/cycle (also reduces max inflight instructions to 32,64,96) */
6835         uint64_t reserved_4_7          : 4;
6836         uint64_t livelock_stall_detect : 4;  /**< [ 11:  8](R/W) Livelock stall detector. 0=disable, cycles 16*1\<\<[[11:8] */
6837         uint64_t reserved_12_63        : 52;
6838 #endif /* Word 0 - End */
6839     } s;
6840     /* struct bdk_ap_cvmctl2_el1_s cn; */
6841 };
6842 typedef union bdk_ap_cvmctl2_el1 bdk_ap_cvmctl2_el1_t;
6843 
6844 #define BDK_AP_CVMCTL2_EL1 BDK_AP_CVMCTL2_EL1_FUNC()
6845 static inline uint64_t BDK_AP_CVMCTL2_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVMCTL2_EL1_FUNC(void)6846 static inline uint64_t BDK_AP_CVMCTL2_EL1_FUNC(void)
6847 {
6848     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
6849         return 0x3000b000100ll;
6850     __bdk_csr_fatal("AP_CVMCTL2_EL1", 0, 0, 0, 0, 0);
6851 }
6852 
6853 #define typedef_BDK_AP_CVMCTL2_EL1 bdk_ap_cvmctl2_el1_t
6854 #define bustype_BDK_AP_CVMCTL2_EL1 BDK_CSR_TYPE_SYSREG
6855 #define basename_BDK_AP_CVMCTL2_EL1 "AP_CVMCTL2_EL1"
6856 #define busnum_BDK_AP_CVMCTL2_EL1 0
6857 #define arguments_BDK_AP_CVMCTL2_EL1 -1,-1,-1,-1
6858 
6859 /**
6860  * Register (SYSREG) ap_cvmctl_el1
6861  *
6862  * AP Cavium Control Register
6863  * This register provides Cavium-specific control information.
6864  */
6865 union bdk_ap_cvmctl_el1
6866 {
6867     uint64_t u;
6868     struct bdk_ap_cvmctl_el1_s
6869     {
6870 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6871         uint64_t reserved_57_63        : 7;
6872         uint64_t disable_const         : 1;  /**< [ 56: 56](R/W) Disable constant optimization. */
6873         uint64_t disable_alias         : 1;  /**< [ 55: 55](R/W) Disable alias optimization. */
6874         uint64_t disable_ldp_stp_fiss  : 1;  /**< [ 54: 54](R/W) Disable ldp/stp fissioning with unaligned prediction. */
6875         uint64_t disable_io_pred       : 1;  /**< [ 53: 53](R/W) Disable IO space prediction. */
6876         uint64_t disable_unaligned_pred : 1; /**< [ 52: 52](R/W) Disable unaligned prediction. */
6877         uint64_t disable_ldst_ordering_pred : 1;/**< [ 51: 51](R/W) Disable load/store ordering prediction. */
6878         uint64_t reserved_50           : 1;
6879         uint64_t disable_branch_elimination : 1;/**< [ 49: 49](R/W) Disable branch elimination. */
6880         uint64_t disable_optimum_occupancy : 1;/**< [ 48: 48](R/W) Increase ibuf occupancy time. */
6881         uint64_t disable_load2         : 1;  /**< [ 47: 47](R/W) Disable second load port. */
6882         uint64_t force_strong_ordering : 1;  /**< [ 46: 46](R/W) Force strong load ordering.
6883                                                                  0 = Weak ordering.
6884                                                                  1 = Strong ordering.
6885 
6886                                                                  Internal:
6887                                                                  CN8XXX is always strong ordering. */
6888         uint64_t disable_mem_ooo       : 1;  /**< [ 45: 45](R/W) Disable all memory out-of-order. */
6889         uint64_t disable_ooo           : 1;  /**< [ 44: 44](R/W) Disable all out-of-order. */
6890         uint64_t dpref_bp_dis          : 1;  /**< [ 43: 43](R/W) When set, hardware data prefetcher ignores memory system backpressure for next line prefetcher. */
6891         uint64_t dpref_lookahead       : 1;  /**< [ 42: 42](R/W) When set, hardware data prefetcher uses a lookahead of 2. When clear, lookahead of 1. */
6892         uint64_t dpref_next_line       : 1;  /**< [ 41: 41](R/W) Enable next line hardware data prefetcher. */
6893         uint64_t dpref_delta           : 1;  /**< [ 40: 40](R/W) Enable delta stream hardware data prefetcher. */
6894         uint64_t mrs_msr_hazard        : 1;  /**< [ 39: 39](R/W) Disable MRS/MSR pipelining, assume hazards. */
6895         uint64_t disable_eret_pred     : 1;  /**< [ 38: 38](R/W) Disable ERET prediction. */
6896         uint64_t disable_casp          : 1;  /**< [ 37: 37](R/W) Disable the CASP instruction. */
6897         uint64_t disable_cas           : 1;  /**< [ 36: 36](R/W) Disable the CAS instruction. */
6898         uint64_t force_cim_ich_vtr_to1 : 1;  /**< [ 35: 35](R/W) Set CIM AP_ICH_VTR_EL2[LISTREGS] to 0x1 (i.e. two LRs) on Pass 1. */
6899         uint64_t disable_wfe           : 1;  /**< [ 34: 34](R/W) Disable WFE. */
6900         uint64_t enable_v81            : 1;  /**< [ 33: 33](R/W) Enable v8.1 features, modifying the ID registers to show v8.1. */
6901         uint64_t isb_flush             : 1;  /**< [ 32: 32](R/W) Enable pipeline flush after an ISB. */
6902         uint64_t wfe_defer             : 8;  /**< [ 31: 24](R/W) WFE defer timer setting.  Time in core-clocks = {| WFE_DEFER, WFE_DEFER\<3:0\>} \<\<
6903                                                                  WFE_DEFER\<7:4\>. */
6904         uint64_t reserved_23           : 1;
6905         uint64_t force_icache_parity   : 1;  /**< [ 22: 22](R/W) Force icache correctable parity error on next Icache fill. This bit clears itself after
6906                                                                  the fill operation. */
6907         uint64_t suppress_parity_checking : 1;/**< [ 21: 21](R/W) Suppress Icache correctable parity checking. */
6908         uint64_t no_exc_icache_parity  : 1;  /**< [ 20: 20](R/W) Suppress exception on Icache correctable parity error. */
6909         uint64_t step_rate             : 4;  /**< [ 19: 16](R/W) Step rate. */
6910         uint64_t reserved_10_15        : 6;
6911         uint64_t disable_flex_execution : 1; /**< [  9:  9](R/W) Disable flex execution; also prevents overlapped execution of DIV/SQRT and other
6912                                                                  instructions (to prevent a DIV load collision). */
6913         uint64_t disable_branch_folding : 1; /**< [  8:  8](R/W) Disable branch folding. */
6914         uint64_t disable_wfi           : 1;  /**< [  7:  7](R/W) Disable WFI/WFE. */
6915         uint64_t reserved_6            : 1;
6916         uint64_t force_issue_clock     : 1;  /**< [  5:  5](R/W) Force issue-unit clock. */
6917         uint64_t force_exe_clock       : 1;  /**< [  4:  4](R/W) Force execution-unit clock. */
6918         uint64_t force_csr_clock       : 1;  /**< [  3:  3](R/W) Force CSR clock. */
6919         uint64_t reserved_2            : 1;
6920         uint64_t random_icache         : 1;  /**< [  1:  1](R/W) Random Icache replacement. */
6921         uint64_t disable_icache        : 1;  /**< [  0:  0](R/W) Disable Icache. */
6922 #else /* Word 0 - Little Endian */
6923         uint64_t disable_icache        : 1;  /**< [  0:  0](R/W) Disable Icache. */
6924         uint64_t random_icache         : 1;  /**< [  1:  1](R/W) Random Icache replacement. */
6925         uint64_t reserved_2            : 1;
6926         uint64_t force_csr_clock       : 1;  /**< [  3:  3](R/W) Force CSR clock. */
6927         uint64_t force_exe_clock       : 1;  /**< [  4:  4](R/W) Force execution-unit clock. */
6928         uint64_t force_issue_clock     : 1;  /**< [  5:  5](R/W) Force issue-unit clock. */
6929         uint64_t reserved_6            : 1;
6930         uint64_t disable_wfi           : 1;  /**< [  7:  7](R/W) Disable WFI/WFE. */
6931         uint64_t disable_branch_folding : 1; /**< [  8:  8](R/W) Disable branch folding. */
6932         uint64_t disable_flex_execution : 1; /**< [  9:  9](R/W) Disable flex execution; also prevents overlapped execution of DIV/SQRT and other
6933                                                                  instructions (to prevent a DIV load collision). */
6934         uint64_t reserved_10_15        : 6;
6935         uint64_t step_rate             : 4;  /**< [ 19: 16](R/W) Step rate. */
6936         uint64_t no_exc_icache_parity  : 1;  /**< [ 20: 20](R/W) Suppress exception on Icache correctable parity error. */
6937         uint64_t suppress_parity_checking : 1;/**< [ 21: 21](R/W) Suppress Icache correctable parity checking. */
6938         uint64_t force_icache_parity   : 1;  /**< [ 22: 22](R/W) Force icache correctable parity error on next Icache fill. This bit clears itself after
6939                                                                  the fill operation. */
6940         uint64_t reserved_23           : 1;
6941         uint64_t wfe_defer             : 8;  /**< [ 31: 24](R/W) WFE defer timer setting.  Time in core-clocks = {| WFE_DEFER, WFE_DEFER\<3:0\>} \<\<
6942                                                                  WFE_DEFER\<7:4\>. */
6943         uint64_t isb_flush             : 1;  /**< [ 32: 32](R/W) Enable pipeline flush after an ISB. */
6944         uint64_t enable_v81            : 1;  /**< [ 33: 33](R/W) Enable v8.1 features, modifying the ID registers to show v8.1. */
6945         uint64_t disable_wfe           : 1;  /**< [ 34: 34](R/W) Disable WFE. */
6946         uint64_t force_cim_ich_vtr_to1 : 1;  /**< [ 35: 35](R/W) Set CIM AP_ICH_VTR_EL2[LISTREGS] to 0x1 (i.e. two LRs) on Pass 1. */
6947         uint64_t disable_cas           : 1;  /**< [ 36: 36](R/W) Disable the CAS instruction. */
6948         uint64_t disable_casp          : 1;  /**< [ 37: 37](R/W) Disable the CASP instruction. */
6949         uint64_t disable_eret_pred     : 1;  /**< [ 38: 38](R/W) Disable ERET prediction. */
6950         uint64_t mrs_msr_hazard        : 1;  /**< [ 39: 39](R/W) Disable MRS/MSR pipelining, assume hazards. */
6951         uint64_t dpref_delta           : 1;  /**< [ 40: 40](R/W) Enable delta stream hardware data prefetcher. */
6952         uint64_t dpref_next_line       : 1;  /**< [ 41: 41](R/W) Enable next line hardware data prefetcher. */
6953         uint64_t dpref_lookahead       : 1;  /**< [ 42: 42](R/W) When set, hardware data prefetcher uses a lookahead of 2. When clear, lookahead of 1. */
6954         uint64_t dpref_bp_dis          : 1;  /**< [ 43: 43](R/W) When set, hardware data prefetcher ignores memory system backpressure for next line prefetcher. */
6955         uint64_t disable_ooo           : 1;  /**< [ 44: 44](R/W) Disable all out-of-order. */
6956         uint64_t disable_mem_ooo       : 1;  /**< [ 45: 45](R/W) Disable all memory out-of-order. */
6957         uint64_t force_strong_ordering : 1;  /**< [ 46: 46](R/W) Force strong load ordering.
6958                                                                  0 = Weak ordering.
6959                                                                  1 = Strong ordering.
6960 
6961                                                                  Internal:
6962                                                                  CN8XXX is always strong ordering. */
6963         uint64_t disable_load2         : 1;  /**< [ 47: 47](R/W) Disable second load port. */
6964         uint64_t disable_optimum_occupancy : 1;/**< [ 48: 48](R/W) Increase ibuf occupancy time. */
6965         uint64_t disable_branch_elimination : 1;/**< [ 49: 49](R/W) Disable branch elimination. */
6966         uint64_t reserved_50           : 1;
6967         uint64_t disable_ldst_ordering_pred : 1;/**< [ 51: 51](R/W) Disable load/store ordering prediction. */
6968         uint64_t disable_unaligned_pred : 1; /**< [ 52: 52](R/W) Disable unaligned prediction. */
6969         uint64_t disable_io_pred       : 1;  /**< [ 53: 53](R/W) Disable IO space prediction. */
6970         uint64_t disable_ldp_stp_fiss  : 1;  /**< [ 54: 54](R/W) Disable ldp/stp fissioning with unaligned prediction. */
6971         uint64_t disable_alias         : 1;  /**< [ 55: 55](R/W) Disable alias optimization. */
6972         uint64_t disable_const         : 1;  /**< [ 56: 56](R/W) Disable constant optimization. */
6973         uint64_t reserved_57_63        : 7;
6974 #endif /* Word 0 - End */
6975     } s;
6976     struct bdk_ap_cvmctl_el1_cn88xxp1
6977     {
6978 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6979         uint64_t reserved_40_63        : 24;
6980         uint64_t mrs_msr_hazard        : 1;  /**< [ 39: 39](R/W) Disable MRS/MSR pipelining, assume hazards. */
6981         uint64_t disable_eret_pred     : 1;  /**< [ 38: 38](R/W) Disable ERET prediction. */
6982         uint64_t disable_casp          : 1;  /**< [ 37: 37](R/W) Disable the CASP instruction. */
6983         uint64_t disable_cas           : 1;  /**< [ 36: 36](R/W) Disable the CAS instruction. */
6984         uint64_t force_cim_ich_vtr_to1 : 1;  /**< [ 35: 35](R/W) Set CIM AP_ICH_VTR_EL2[LISTREGS] to 0x1 (i.e. two LRs) on Pass 1. */
6985         uint64_t disable_wfe           : 1;  /**< [ 34: 34](R/W) Disable WFE. */
6986         uint64_t enable_v81            : 1;  /**< [ 33: 33](R/W) Enable v8.1 features, modifying the ID registers to show v8.1. */
6987         uint64_t isb_flush             : 1;  /**< [ 32: 32](R/W) Enable pipeline flush after an ISB. */
6988         uint64_t wfe_defer             : 8;  /**< [ 31: 24](R/W) WFE defer timer setting.  Time in core-clocks = {| WFE_DEFER, WFE_DEFER\<3:0\>} \<\<
6989                                                                  WFE_DEFER\<7:4\>. */
6990         uint64_t disable_icache_probes : 1;  /**< [ 23: 23](R/W) Disable Icache probes. */
6991         uint64_t force_icache_parity   : 1;  /**< [ 22: 22](R/W) Force icache correctable parity error on next Icache fill. This bit clears itself after
6992                                                                  the fill operation. */
6993         uint64_t suppress_parity_checking : 1;/**< [ 21: 21](R/W) Suppress Icache correctable parity checking. */
6994         uint64_t no_exc_icache_parity  : 1;  /**< [ 20: 20](R/W) Suppress exception on Icache correctable parity error. */
6995         uint64_t step_rate             : 4;  /**< [ 19: 16](R/W) Step rate. */
6996         uint64_t reserved_10_15        : 6;
6997         uint64_t disable_flex_execution : 1; /**< [  9:  9](R/W) Disable flex execution; also prevents overlapped execution of DIV/SQRT and other
6998                                                                  instructions (to prevent a DIV load collision). */
6999         uint64_t disable_branch_folding : 1; /**< [  8:  8](R/W) Disable branch folding. */
7000         uint64_t disable_wfi           : 1;  /**< [  7:  7](R/W) Disable WFI/WFE. */
7001         uint64_t disable_fetch_under_fill : 1;/**< [  6:  6](R/W) Disable fetch-under-fill. */
7002         uint64_t force_issue_clock     : 1;  /**< [  5:  5](R/W) Force issue-unit clock. */
7003         uint64_t force_exe_clock       : 1;  /**< [  4:  4](R/W) Force execution-unit clock. */
7004         uint64_t force_csr_clock       : 1;  /**< [  3:  3](R/W) Force CSR clock. */
7005         uint64_t disable_icache_prefetching : 1;/**< [  2:  2](R/W) Disable Icache prefetching. */
7006         uint64_t random_icache         : 1;  /**< [  1:  1](R/W) Random Icache replacement. */
7007         uint64_t disable_icache        : 1;  /**< [  0:  0](R/W) Disable Icache. */
7008 #else /* Word 0 - Little Endian */
7009         uint64_t disable_icache        : 1;  /**< [  0:  0](R/W) Disable Icache. */
7010         uint64_t random_icache         : 1;  /**< [  1:  1](R/W) Random Icache replacement. */
7011         uint64_t disable_icache_prefetching : 1;/**< [  2:  2](R/W) Disable Icache prefetching. */
7012         uint64_t force_csr_clock       : 1;  /**< [  3:  3](R/W) Force CSR clock. */
7013         uint64_t force_exe_clock       : 1;  /**< [  4:  4](R/W) Force execution-unit clock. */
7014         uint64_t force_issue_clock     : 1;  /**< [  5:  5](R/W) Force issue-unit clock. */
7015         uint64_t disable_fetch_under_fill : 1;/**< [  6:  6](R/W) Disable fetch-under-fill. */
7016         uint64_t disable_wfi           : 1;  /**< [  7:  7](R/W) Disable WFI/WFE. */
7017         uint64_t disable_branch_folding : 1; /**< [  8:  8](R/W) Disable branch folding. */
7018         uint64_t disable_flex_execution : 1; /**< [  9:  9](R/W) Disable flex execution; also prevents overlapped execution of DIV/SQRT and other
7019                                                                  instructions (to prevent a DIV load collision). */
7020         uint64_t reserved_10_15        : 6;
7021         uint64_t step_rate             : 4;  /**< [ 19: 16](R/W) Step rate. */
7022         uint64_t no_exc_icache_parity  : 1;  /**< [ 20: 20](R/W) Suppress exception on Icache correctable parity error. */
7023         uint64_t suppress_parity_checking : 1;/**< [ 21: 21](R/W) Suppress Icache correctable parity checking. */
7024         uint64_t force_icache_parity   : 1;  /**< [ 22: 22](R/W) Force icache correctable parity error on next Icache fill. This bit clears itself after
7025                                                                  the fill operation. */
7026         uint64_t disable_icache_probes : 1;  /**< [ 23: 23](R/W) Disable Icache probes. */
7027         uint64_t wfe_defer             : 8;  /**< [ 31: 24](R/W) WFE defer timer setting.  Time in core-clocks = {| WFE_DEFER, WFE_DEFER\<3:0\>} \<\<
7028                                                                  WFE_DEFER\<7:4\>. */
7029         uint64_t isb_flush             : 1;  /**< [ 32: 32](R/W) Enable pipeline flush after an ISB. */
7030         uint64_t enable_v81            : 1;  /**< [ 33: 33](R/W) Enable v8.1 features, modifying the ID registers to show v8.1. */
7031         uint64_t disable_wfe           : 1;  /**< [ 34: 34](R/W) Disable WFE. */
7032         uint64_t force_cim_ich_vtr_to1 : 1;  /**< [ 35: 35](R/W) Set CIM AP_ICH_VTR_EL2[LISTREGS] to 0x1 (i.e. two LRs) on Pass 1. */
7033         uint64_t disable_cas           : 1;  /**< [ 36: 36](R/W) Disable the CAS instruction. */
7034         uint64_t disable_casp          : 1;  /**< [ 37: 37](R/W) Disable the CASP instruction. */
7035         uint64_t disable_eret_pred     : 1;  /**< [ 38: 38](R/W) Disable ERET prediction. */
7036         uint64_t mrs_msr_hazard        : 1;  /**< [ 39: 39](R/W) Disable MRS/MSR pipelining, assume hazards. */
7037         uint64_t reserved_40_63        : 24;
7038 #endif /* Word 0 - End */
7039     } cn88xxp1;
7040     struct bdk_ap_cvmctl_el1_cn9
7041     {
7042 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7043         uint64_t reserved_57_63        : 7;
7044         uint64_t disable_const         : 1;  /**< [ 56: 56](R/W) Disable constant optimization. */
7045         uint64_t disable_alias         : 1;  /**< [ 55: 55](R/W) Disable alias optimization. */
7046         uint64_t disable_ldp_stp_fiss  : 1;  /**< [ 54: 54](R/W) Disable ldp/stp fissioning with unaligned prediction. */
7047         uint64_t disable_io_pred       : 1;  /**< [ 53: 53](R/W) Disable IO space prediction. */
7048         uint64_t disable_unaligned_pred : 1; /**< [ 52: 52](R/W) Disable unaligned prediction. */
7049         uint64_t disable_ldst_ordering_pred : 1;/**< [ 51: 51](R/W) Disable load/store ordering prediction. */
7050         uint64_t reserved_50           : 1;
7051         uint64_t disable_branch_elimination : 1;/**< [ 49: 49](R/W) Disable branch elimination. */
7052         uint64_t disable_optimum_occupancy : 1;/**< [ 48: 48](R/W) Increase ibuf occupancy time. */
7053         uint64_t disable_load2         : 1;  /**< [ 47: 47](R/W) Disable second load port. */
7054         uint64_t force_strong_ordering : 1;  /**< [ 46: 46](R/W) Force strong load ordering.
7055                                                                  0 = Weak ordering.
7056                                                                  1 = Strong ordering.
7057 
7058                                                                  Internal:
7059                                                                  CN8XXX is always strong ordering. */
7060         uint64_t disable_mem_ooo       : 1;  /**< [ 45: 45](R/W) Disable all memory out-of-order. */
7061         uint64_t disable_ooo           : 1;  /**< [ 44: 44](R/W) Disable all out-of-order. */
7062         uint64_t dpref_bp_dis          : 1;  /**< [ 43: 43](R/W) When set, hardware data prefetcher ignores memory system backpressure for next line prefetcher. */
7063         uint64_t dpref_lookahead       : 1;  /**< [ 42: 42](R/W) When set, hardware data prefetcher uses a lookahead of 2. When clear, lookahead of 1. */
7064         uint64_t dpref_next_line       : 1;  /**< [ 41: 41](R/W) Enable next line hardware data prefetcher. */
7065         uint64_t dpref_delta           : 1;  /**< [ 40: 40](R/W) Enable delta stream hardware data prefetcher. */
7066         uint64_t mrs_msr_hazard        : 1;  /**< [ 39: 39](R/W) Disable MRS/MSR pipelining, assume hazards. */
7067         uint64_t disable_eret_pred     : 1;  /**< [ 38: 38](R/W) Disable ERET prediction. */
7068         uint64_t disable_casp          : 1;  /**< [ 37: 37](R/W) Disable the CASP instruction. */
7069         uint64_t disable_cas           : 1;  /**< [ 36: 36](R/W) Disable the CAS instruction. */
7070         uint64_t reserved_35           : 1;
7071         uint64_t disable_wfe           : 1;  /**< [ 34: 34](R/W) Disable WFE. */
7072         uint64_t enable_v81            : 1;  /**< [ 33: 33](RO) Enable v8.1 features, modifying the ID registers to show v8.1.
7073                                                                  Internal:
7074                                                                  FIXME does this go away with CN98XX. */
7075         uint64_t isb_flush             : 1;  /**< [ 32: 32](R/W) Enable pipeline flush after an ISB. */
7076         uint64_t wfe_defer             : 8;  /**< [ 31: 24](R/W) WFE defer timer setting.  Time in core-clocks = {| WFE_DEFER, WFE_DEFER\<3:0\>} \<\<
7077                                                                  WFE_DEFER\<7:4\>. */
7078         uint64_t ldil1hwprefdis        : 1;  /**< [ 23: 23](R/W) Disable Istream LDI L1 hardware prefetcher. */
7079         uint64_t force_icache_parity   : 1;  /**< [ 22: 22](R/W) Force icache correctable parity error on next Icache fill. This bit clears itself after
7080                                                                  the fill operation. */
7081         uint64_t suppress_parity_checking : 1;/**< [ 21: 21](R/W) Suppress Icache correctable parity checking. */
7082         uint64_t no_exc_icache_parity  : 1;  /**< [ 20: 20](R/W) Suppress exception on Icache correctable parity error. */
7083         uint64_t reserved_16_19        : 4;
7084         uint64_t reserved_10_15        : 6;
7085         uint64_t reserved_9            : 1;
7086         uint64_t disable_branch_folding : 1; /**< [  8:  8](R/W) Disable branch folding and other fusions. */
7087         uint64_t disable_wfi           : 1;  /**< [  7:  7](R/W) Disable WFI/WFE. */
7088         uint64_t ldil1swprefdis        : 1;  /**< [  6:  6](R/W) Disable LDI L1 software prefetch instructions (PRFM). */
7089         uint64_t force_issue_clock     : 1;  /**< [  5:  5](R/W) Force issue-unit clock. */
7090         uint64_t force_exe_clock       : 1;  /**< [  4:  4](R/W) Force execution-unit clock. */
7091         uint64_t force_csr_clock       : 1;  /**< [  3:  3](R/W) Force CSR clock. */
7092         uint64_t ldil1specdis          : 1;  /**< [  2:  2](R/W) Disable all LDI L1 speculative fill requests (only demand fills with machine drained).
7093                                                                  Internal:
7094                                                                  CN88XX-like mode. */
7095         uint64_t random_icache         : 1;  /**< [  1:  1](R/W) Random Icache replacement. */
7096         uint64_t disable_icache        : 1;  /**< [  0:  0](R/W) Disable Icache. */
7097 #else /* Word 0 - Little Endian */
7098         uint64_t disable_icache        : 1;  /**< [  0:  0](R/W) Disable Icache. */
7099         uint64_t random_icache         : 1;  /**< [  1:  1](R/W) Random Icache replacement. */
7100         uint64_t ldil1specdis          : 1;  /**< [  2:  2](R/W) Disable all LDI L1 speculative fill requests (only demand fills with machine drained).
7101                                                                  Internal:
7102                                                                  CN88XX-like mode. */
7103         uint64_t force_csr_clock       : 1;  /**< [  3:  3](R/W) Force CSR clock. */
7104         uint64_t force_exe_clock       : 1;  /**< [  4:  4](R/W) Force execution-unit clock. */
7105         uint64_t force_issue_clock     : 1;  /**< [  5:  5](R/W) Force issue-unit clock. */
7106         uint64_t ldil1swprefdis        : 1;  /**< [  6:  6](R/W) Disable LDI L1 software prefetch instructions (PRFM). */
7107         uint64_t disable_wfi           : 1;  /**< [  7:  7](R/W) Disable WFI/WFE. */
7108         uint64_t disable_branch_folding : 1; /**< [  8:  8](R/W) Disable branch folding and other fusions. */
7109         uint64_t reserved_9            : 1;
7110         uint64_t reserved_10_15        : 6;
7111         uint64_t reserved_16_19        : 4;
7112         uint64_t no_exc_icache_parity  : 1;  /**< [ 20: 20](R/W) Suppress exception on Icache correctable parity error. */
7113         uint64_t suppress_parity_checking : 1;/**< [ 21: 21](R/W) Suppress Icache correctable parity checking. */
7114         uint64_t force_icache_parity   : 1;  /**< [ 22: 22](R/W) Force icache correctable parity error on next Icache fill. This bit clears itself after
7115                                                                  the fill operation. */
7116         uint64_t ldil1hwprefdis        : 1;  /**< [ 23: 23](R/W) Disable Istream LDI L1 hardware prefetcher. */
7117         uint64_t wfe_defer             : 8;  /**< [ 31: 24](R/W) WFE defer timer setting.  Time in core-clocks = {| WFE_DEFER, WFE_DEFER\<3:0\>} \<\<
7118                                                                  WFE_DEFER\<7:4\>. */
7119         uint64_t isb_flush             : 1;  /**< [ 32: 32](R/W) Enable pipeline flush after an ISB. */
7120         uint64_t enable_v81            : 1;  /**< [ 33: 33](RO) Enable v8.1 features, modifying the ID registers to show v8.1.
7121                                                                  Internal:
7122                                                                  FIXME does this go away with CN98XX. */
7123         uint64_t disable_wfe           : 1;  /**< [ 34: 34](R/W) Disable WFE. */
7124         uint64_t reserved_35           : 1;
7125         uint64_t disable_cas           : 1;  /**< [ 36: 36](R/W) Disable the CAS instruction. */
7126         uint64_t disable_casp          : 1;  /**< [ 37: 37](R/W) Disable the CASP instruction. */
7127         uint64_t disable_eret_pred     : 1;  /**< [ 38: 38](R/W) Disable ERET prediction. */
7128         uint64_t mrs_msr_hazard        : 1;  /**< [ 39: 39](R/W) Disable MRS/MSR pipelining, assume hazards. */
7129         uint64_t dpref_delta           : 1;  /**< [ 40: 40](R/W) Enable delta stream hardware data prefetcher. */
7130         uint64_t dpref_next_line       : 1;  /**< [ 41: 41](R/W) Enable next line hardware data prefetcher. */
7131         uint64_t dpref_lookahead       : 1;  /**< [ 42: 42](R/W) When set, hardware data prefetcher uses a lookahead of 2. When clear, lookahead of 1. */
7132         uint64_t dpref_bp_dis          : 1;  /**< [ 43: 43](R/W) When set, hardware data prefetcher ignores memory system backpressure for next line prefetcher. */
7133         uint64_t disable_ooo           : 1;  /**< [ 44: 44](R/W) Disable all out-of-order. */
7134         uint64_t disable_mem_ooo       : 1;  /**< [ 45: 45](R/W) Disable all memory out-of-order. */
7135         uint64_t force_strong_ordering : 1;  /**< [ 46: 46](R/W) Force strong load ordering.
7136                                                                  0 = Weak ordering.
7137                                                                  1 = Strong ordering.
7138 
7139                                                                  Internal:
7140                                                                  CN8XXX is always strong ordering. */
7141         uint64_t disable_load2         : 1;  /**< [ 47: 47](R/W) Disable second load port. */
7142         uint64_t disable_optimum_occupancy : 1;/**< [ 48: 48](R/W) Increase ibuf occupancy time. */
7143         uint64_t disable_branch_elimination : 1;/**< [ 49: 49](R/W) Disable branch elimination. */
7144         uint64_t reserved_50           : 1;
7145         uint64_t disable_ldst_ordering_pred : 1;/**< [ 51: 51](R/W) Disable load/store ordering prediction. */
7146         uint64_t disable_unaligned_pred : 1; /**< [ 52: 52](R/W) Disable unaligned prediction. */
7147         uint64_t disable_io_pred       : 1;  /**< [ 53: 53](R/W) Disable IO space prediction. */
7148         uint64_t disable_ldp_stp_fiss  : 1;  /**< [ 54: 54](R/W) Disable ldp/stp fissioning with unaligned prediction. */
7149         uint64_t disable_alias         : 1;  /**< [ 55: 55](R/W) Disable alias optimization. */
7150         uint64_t disable_const         : 1;  /**< [ 56: 56](R/W) Disable constant optimization. */
7151         uint64_t reserved_57_63        : 7;
7152 #endif /* Word 0 - End */
7153     } cn9;
7154     struct bdk_ap_cvmctl_el1_cn81xx
7155     {
7156 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7157         uint64_t reserved_44_63        : 20;
7158         uint64_t dpref_bp_dis          : 1;  /**< [ 43: 43](R/W) When set, hardware data prefetcher ignores memory system backpressure for next line prefetcher. */
7159         uint64_t dpref_lookahead       : 1;  /**< [ 42: 42](R/W) When set, hardware data prefetcher uses a lookahead of 2. When clear, lookahead of 1. */
7160         uint64_t dpref_next_line       : 1;  /**< [ 41: 41](R/W) Enable next line hardware data prefetcher. */
7161         uint64_t dpref_delta           : 1;  /**< [ 40: 40](R/W) Enable delta stream hardware data prefetcher. */
7162         uint64_t mrs_msr_hazard        : 1;  /**< [ 39: 39](R/W) Disable MRS/MSR pipelining, assume hazards. */
7163         uint64_t disable_eret_pred     : 1;  /**< [ 38: 38](R/W) Disable ERET prediction. */
7164         uint64_t disable_casp          : 1;  /**< [ 37: 37](R/W) Disable the CASP instruction. */
7165         uint64_t disable_cas           : 1;  /**< [ 36: 36](R/W) Disable the CAS instruction. */
7166         uint64_t force_cim_ich_vtr_to1 : 1;  /**< [ 35: 35](RAZ) Reserved. */
7167         uint64_t disable_wfe           : 1;  /**< [ 34: 34](R/W) Disable WFE. */
7168         uint64_t enable_v81            : 1;  /**< [ 33: 33](R/W) Enable v8.1 features, modifying the ID registers to show v8.1. */
7169         uint64_t isb_flush             : 1;  /**< [ 32: 32](R/W) Enable pipeline flush after an ISB. */
7170         uint64_t wfe_defer             : 8;  /**< [ 31: 24](R/W) WFE defer timer setting.  Time in core-clocks = {| WFE_DEFER, WFE_DEFER\<3:0\>} \<\<
7171                                                                  WFE_DEFER\<7:4\>. */
7172         uint64_t disable_icache_probes : 1;  /**< [ 23: 23](R/W) Disable Icache probes. */
7173         uint64_t force_icache_parity   : 1;  /**< [ 22: 22](R/W) Force icache correctable parity error on next Icache fill. This bit clears itself after
7174                                                                  the fill operation. */
7175         uint64_t suppress_parity_checking : 1;/**< [ 21: 21](R/W) Suppress Icache correctable parity checking. */
7176         uint64_t no_exc_icache_parity  : 1;  /**< [ 20: 20](R/W) Suppress exception on Icache correctable parity error. */
7177         uint64_t step_rate             : 4;  /**< [ 19: 16](R/W) Step rate. */
7178         uint64_t reserved_10_15        : 6;
7179         uint64_t disable_flex_execution : 1; /**< [  9:  9](R/W) Disable flex execution; also prevents overlapped execution of DIV/SQRT and other
7180                                                                  instructions (to prevent a DIV load collision). */
7181         uint64_t disable_branch_folding : 1; /**< [  8:  8](R/W) Disable branch folding. */
7182         uint64_t disable_wfi           : 1;  /**< [  7:  7](R/W) Disable WFI/WFE. */
7183         uint64_t disable_fetch_under_fill : 1;/**< [  6:  6](R/W) Disable fetch-under-fill. */
7184         uint64_t force_issue_clock     : 1;  /**< [  5:  5](R/W) Force issue-unit clock. */
7185         uint64_t force_exe_clock       : 1;  /**< [  4:  4](R/W) Force execution-unit clock. */
7186         uint64_t force_csr_clock       : 1;  /**< [  3:  3](R/W) Force CSR clock. */
7187         uint64_t disable_icache_prefetching : 1;/**< [  2:  2](R/W) Disable Icache prefetching. */
7188         uint64_t random_icache         : 1;  /**< [  1:  1](R/W) Random Icache replacement. */
7189         uint64_t disable_icache        : 1;  /**< [  0:  0](R/W) Disable Icache. */
7190 #else /* Word 0 - Little Endian */
7191         uint64_t disable_icache        : 1;  /**< [  0:  0](R/W) Disable Icache. */
7192         uint64_t random_icache         : 1;  /**< [  1:  1](R/W) Random Icache replacement. */
7193         uint64_t disable_icache_prefetching : 1;/**< [  2:  2](R/W) Disable Icache prefetching. */
7194         uint64_t force_csr_clock       : 1;  /**< [  3:  3](R/W) Force CSR clock. */
7195         uint64_t force_exe_clock       : 1;  /**< [  4:  4](R/W) Force execution-unit clock. */
7196         uint64_t force_issue_clock     : 1;  /**< [  5:  5](R/W) Force issue-unit clock. */
7197         uint64_t disable_fetch_under_fill : 1;/**< [  6:  6](R/W) Disable fetch-under-fill. */
7198         uint64_t disable_wfi           : 1;  /**< [  7:  7](R/W) Disable WFI/WFE. */
7199         uint64_t disable_branch_folding : 1; /**< [  8:  8](R/W) Disable branch folding. */
7200         uint64_t disable_flex_execution : 1; /**< [  9:  9](R/W) Disable flex execution; also prevents overlapped execution of DIV/SQRT and other
7201                                                                  instructions (to prevent a DIV load collision). */
7202         uint64_t reserved_10_15        : 6;
7203         uint64_t step_rate             : 4;  /**< [ 19: 16](R/W) Step rate. */
7204         uint64_t no_exc_icache_parity  : 1;  /**< [ 20: 20](R/W) Suppress exception on Icache correctable parity error. */
7205         uint64_t suppress_parity_checking : 1;/**< [ 21: 21](R/W) Suppress Icache correctable parity checking. */
7206         uint64_t force_icache_parity   : 1;  /**< [ 22: 22](R/W) Force icache correctable parity error on next Icache fill. This bit clears itself after
7207                                                                  the fill operation. */
7208         uint64_t disable_icache_probes : 1;  /**< [ 23: 23](R/W) Disable Icache probes. */
7209         uint64_t wfe_defer             : 8;  /**< [ 31: 24](R/W) WFE defer timer setting.  Time in core-clocks = {| WFE_DEFER, WFE_DEFER\<3:0\>} \<\<
7210                                                                  WFE_DEFER\<7:4\>. */
7211         uint64_t isb_flush             : 1;  /**< [ 32: 32](R/W) Enable pipeline flush after an ISB. */
7212         uint64_t enable_v81            : 1;  /**< [ 33: 33](R/W) Enable v8.1 features, modifying the ID registers to show v8.1. */
7213         uint64_t disable_wfe           : 1;  /**< [ 34: 34](R/W) Disable WFE. */
7214         uint64_t force_cim_ich_vtr_to1 : 1;  /**< [ 35: 35](RAZ) Reserved. */
7215         uint64_t disable_cas           : 1;  /**< [ 36: 36](R/W) Disable the CAS instruction. */
7216         uint64_t disable_casp          : 1;  /**< [ 37: 37](R/W) Disable the CASP instruction. */
7217         uint64_t disable_eret_pred     : 1;  /**< [ 38: 38](R/W) Disable ERET prediction. */
7218         uint64_t mrs_msr_hazard        : 1;  /**< [ 39: 39](R/W) Disable MRS/MSR pipelining, assume hazards. */
7219         uint64_t dpref_delta           : 1;  /**< [ 40: 40](R/W) Enable delta stream hardware data prefetcher. */
7220         uint64_t dpref_next_line       : 1;  /**< [ 41: 41](R/W) Enable next line hardware data prefetcher. */
7221         uint64_t dpref_lookahead       : 1;  /**< [ 42: 42](R/W) When set, hardware data prefetcher uses a lookahead of 2. When clear, lookahead of 1. */
7222         uint64_t dpref_bp_dis          : 1;  /**< [ 43: 43](R/W) When set, hardware data prefetcher ignores memory system backpressure for next line prefetcher. */
7223         uint64_t reserved_44_63        : 20;
7224 #endif /* Word 0 - End */
7225     } cn81xx;
7226     /* struct bdk_ap_cvmctl_el1_cn81xx cn83xx; */
7227     struct bdk_ap_cvmctl_el1_cn88xxp2
7228     {
7229 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7230         uint64_t reserved_40_63        : 24;
7231         uint64_t mrs_msr_hazard        : 1;  /**< [ 39: 39](R/W) Disable MRS/MSR pipelining, assume hazards. */
7232         uint64_t disable_eret_pred     : 1;  /**< [ 38: 38](R/W) Disable ERET prediction. */
7233         uint64_t disable_casp          : 1;  /**< [ 37: 37](R/W) Disable the CASP instruction. */
7234         uint64_t disable_cas           : 1;  /**< [ 36: 36](R/W) Disable the CAS instruction. */
7235         uint64_t force_cim_ich_vtr_to1 : 1;  /**< [ 35: 35](RAZ) Reserved. */
7236         uint64_t disable_wfe           : 1;  /**< [ 34: 34](R/W) Disable WFE. */
7237         uint64_t enable_v81            : 1;  /**< [ 33: 33](R/W) Enable v8.1 features, modifying the ID registers to show v8.1. */
7238         uint64_t isb_flush             : 1;  /**< [ 32: 32](R/W) Enable pipeline flush after an ISB. */
7239         uint64_t wfe_defer             : 8;  /**< [ 31: 24](R/W) WFE defer timer setting.  Time in core-clocks = {| WFE_DEFER, WFE_DEFER\<3:0\>} \<\<
7240                                                                  WFE_DEFER\<7:4\>. */
7241         uint64_t disable_icache_probes : 1;  /**< [ 23: 23](R/W) Disable Icache probes. */
7242         uint64_t force_icache_parity   : 1;  /**< [ 22: 22](R/W) Force icache correctable parity error on next Icache fill. This bit clears itself after
7243                                                                  the fill operation. */
7244         uint64_t suppress_parity_checking : 1;/**< [ 21: 21](R/W) Suppress Icache correctable parity checking. */
7245         uint64_t no_exc_icache_parity  : 1;  /**< [ 20: 20](R/W) Suppress exception on Icache correctable parity error. */
7246         uint64_t step_rate             : 4;  /**< [ 19: 16](R/W) Step rate. */
7247         uint64_t reserved_10_15        : 6;
7248         uint64_t disable_flex_execution : 1; /**< [  9:  9](R/W) Disable flex execution; also prevents overlapped execution of DIV/SQRT and other
7249                                                                  instructions (to prevent a DIV load collision). */
7250         uint64_t disable_branch_folding : 1; /**< [  8:  8](R/W) Disable branch folding. */
7251         uint64_t disable_wfi           : 1;  /**< [  7:  7](R/W) Disable WFI/WFE. */
7252         uint64_t disable_fetch_under_fill : 1;/**< [  6:  6](R/W) Disable fetch-under-fill. */
7253         uint64_t force_issue_clock     : 1;  /**< [  5:  5](R/W) Force issue-unit clock. */
7254         uint64_t force_exe_clock       : 1;  /**< [  4:  4](R/W) Force execution-unit clock. */
7255         uint64_t force_csr_clock       : 1;  /**< [  3:  3](R/W) Force CSR clock. */
7256         uint64_t disable_icache_prefetching : 1;/**< [  2:  2](R/W) Disable Icache prefetching. */
7257         uint64_t random_icache         : 1;  /**< [  1:  1](R/W) Random Icache replacement. */
7258         uint64_t disable_icache        : 1;  /**< [  0:  0](R/W) Disable Icache. */
7259 #else /* Word 0 - Little Endian */
7260         uint64_t disable_icache        : 1;  /**< [  0:  0](R/W) Disable Icache. */
7261         uint64_t random_icache         : 1;  /**< [  1:  1](R/W) Random Icache replacement. */
7262         uint64_t disable_icache_prefetching : 1;/**< [  2:  2](R/W) Disable Icache prefetching. */
7263         uint64_t force_csr_clock       : 1;  /**< [  3:  3](R/W) Force CSR clock. */
7264         uint64_t force_exe_clock       : 1;  /**< [  4:  4](R/W) Force execution-unit clock. */
7265         uint64_t force_issue_clock     : 1;  /**< [  5:  5](R/W) Force issue-unit clock. */
7266         uint64_t disable_fetch_under_fill : 1;/**< [  6:  6](R/W) Disable fetch-under-fill. */
7267         uint64_t disable_wfi           : 1;  /**< [  7:  7](R/W) Disable WFI/WFE. */
7268         uint64_t disable_branch_folding : 1; /**< [  8:  8](R/W) Disable branch folding. */
7269         uint64_t disable_flex_execution : 1; /**< [  9:  9](R/W) Disable flex execution; also prevents overlapped execution of DIV/SQRT and other
7270                                                                  instructions (to prevent a DIV load collision). */
7271         uint64_t reserved_10_15        : 6;
7272         uint64_t step_rate             : 4;  /**< [ 19: 16](R/W) Step rate. */
7273         uint64_t no_exc_icache_parity  : 1;  /**< [ 20: 20](R/W) Suppress exception on Icache correctable parity error. */
7274         uint64_t suppress_parity_checking : 1;/**< [ 21: 21](R/W) Suppress Icache correctable parity checking. */
7275         uint64_t force_icache_parity   : 1;  /**< [ 22: 22](R/W) Force icache correctable parity error on next Icache fill. This bit clears itself after
7276                                                                  the fill operation. */
7277         uint64_t disable_icache_probes : 1;  /**< [ 23: 23](R/W) Disable Icache probes. */
7278         uint64_t wfe_defer             : 8;  /**< [ 31: 24](R/W) WFE defer timer setting.  Time in core-clocks = {| WFE_DEFER, WFE_DEFER\<3:0\>} \<\<
7279                                                                  WFE_DEFER\<7:4\>. */
7280         uint64_t isb_flush             : 1;  /**< [ 32: 32](R/W) Enable pipeline flush after an ISB. */
7281         uint64_t enable_v81            : 1;  /**< [ 33: 33](R/W) Enable v8.1 features, modifying the ID registers to show v8.1. */
7282         uint64_t disable_wfe           : 1;  /**< [ 34: 34](R/W) Disable WFE. */
7283         uint64_t force_cim_ich_vtr_to1 : 1;  /**< [ 35: 35](RAZ) Reserved. */
7284         uint64_t disable_cas           : 1;  /**< [ 36: 36](R/W) Disable the CAS instruction. */
7285         uint64_t disable_casp          : 1;  /**< [ 37: 37](R/W) Disable the CASP instruction. */
7286         uint64_t disable_eret_pred     : 1;  /**< [ 38: 38](R/W) Disable ERET prediction. */
7287         uint64_t mrs_msr_hazard        : 1;  /**< [ 39: 39](R/W) Disable MRS/MSR pipelining, assume hazards. */
7288         uint64_t reserved_40_63        : 24;
7289 #endif /* Word 0 - End */
7290     } cn88xxp2;
7291 };
7292 typedef union bdk_ap_cvmctl_el1 bdk_ap_cvmctl_el1_t;
7293 
7294 #define BDK_AP_CVMCTL_EL1 BDK_AP_CVMCTL_EL1_FUNC()
7295 static inline uint64_t BDK_AP_CVMCTL_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVMCTL_EL1_FUNC(void)7296 static inline uint64_t BDK_AP_CVMCTL_EL1_FUNC(void)
7297 {
7298     return 0x3000b000000ll;
7299 }
7300 
7301 #define typedef_BDK_AP_CVMCTL_EL1 bdk_ap_cvmctl_el1_t
7302 #define bustype_BDK_AP_CVMCTL_EL1 BDK_CSR_TYPE_SYSREG
7303 #define basename_BDK_AP_CVMCTL_EL1 "AP_CVMCTL_EL1"
7304 #define busnum_BDK_AP_CVMCTL_EL1 0
7305 #define arguments_BDK_AP_CVMCTL_EL1 -1,-1,-1,-1
7306 
7307 /**
7308  * Register (SYSREG) ap_cvmmemctl0_el1
7309  *
7310  * AP Cavium Memory Control 0 Register
7311  * This register controls memory features.
7312  */
7313 union bdk_ap_cvmmemctl0_el1
7314 {
7315     uint64_t u;
7316     struct bdk_ap_cvmmemctl0_el1_s
7317     {
7318 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7319         uint64_t reserved_63           : 1;
7320         uint64_t node                  : 2;  /**< [ 62: 61](RO) Local node ID. */
7321         uint64_t stexfailcnt           : 3;  /**< [ 60: 58](RO) ST exclusive fail count. */
7322         uint64_t wfeldex1dis           : 1;  /**< [ 57: 57](R/W) WFE release behavior for LD-exclusive.
7323                                                                  0 = A global monitor transition from exclusive to open (lock flag transition
7324                                                                  from 1 to 0) causes SEV to local core.
7325                                                                  1 = A global monitor transition from exclusive to open (lock flag transition
7326                                                                  from 1 to 0) does not cause SEV to local core. */
7327         uint64_t stlstallforce         : 1;  /**< [ 56: 56](R/W) Force ST_release to wait for flushed write-buffer entries to be ACKed (pass 2.0 only).
7328                                                                  0 = Store-release instructions mark prior relevant write-buffer entries for flush but do
7329                                                                  not wait for the ACKs to return.
7330                                                                  1 = Store-release instructions mark prior relevant write-buffer entries for flush and wait
7331                                                                  for all the ACKs to return. */
7332         uint64_t dmbstallforce         : 1;  /**< [ 55: 55](R/W) Force DMB to wait for flushed write-buffer entries to be ACKed (pass 2.0 only).
7333                                                                  0 = DMB instructions mark prior relevant write-buffer entries for flush, but do not wait
7334                                                                  for the ACKs to return.
7335                                                                  1 = DMB instructions mark prior relevant write-buffer entries for flush and wait for all
7336                                                                  the ACKs to return. */
7337         uint64_t tlbinopdis            : 1;  /**< [ 54: 54](R/W) Disable broadcast TLBI optimization (pass 2.0 only).
7338 
7339                                                                  Address-based broadcast TLBI instructions that go to remote cores are converted
7340                                                                  from address-based TLBI instructions to context-based TLBI instructions. The
7341                                                                  actions on the local core generating the TLBI instruction are still precise.
7342 
7343                                                                  0 = The converted context-based TLBI instructions or original context-based
7344                                                                  TLBIs to remote cores (without intervening interruptions, such as a DSB) are
7345                                                                  coalesced into a single context-based TLBI. Converted and original ones do not
7346                                                                  coalesce.
7347 
7348                                                                  1 = The above-mentioned coalescing is suppressed and converted context-based
7349                                                                  remote TLBIs still go out as such. */
7350         uint64_t tlbiicflush           : 1;  /**< [ 53: 53](R/W) Some local TLBI instructions cause ICache flush (pass 2.0 only).
7351                                                                  0 = Icache flush operation do not happen on the TLBI instructions listed below.
7352                                                                  1 = Icache is flushed on the TLBI instructions listed below:
7353                                                                    * TLBI ALLE2{IS}.
7354                                                                    * TLBI ALLE3{IS}.
7355                                                                    * TLBI VAE1{IS}.
7356                                                                    * TLBI VALE1{IS}.
7357                                                                    * TLBI VAAE1{IS}.
7358                                                                    * TLBI VAALE1{IS}.
7359                                                                    * TLBI VAE2{IS}.
7360                                                                    * TLBI VALE2{IS}.
7361                                                                    * TLBI VAE3{IS}.
7362                                                                    * TLBI VALE3{IS}.
7363                                                                    * TLBI IPAS2E1{IS}.
7364                                                                    * TLBI IPAS2LE1{IS}. */
7365         uint64_t gsyncto               : 5;  /**< [ 52: 48](R/W) GlobalSync timeout. (pass 2.0 only.)
7366                                                                  timeout = 2^[GSYNCTO].
7367                                                                  0x0 = disable timeout. */
7368         uint64_t utlbfillbypdis        : 1;  /**< [ 47: 47](R/W) Disable uTLB fill bypass (pass 2.0 only).
7369                                                                  0 = On a stage1-only translation, the uTLB is written along with the MTLB.
7370                                                                  1 = On a stage1-only translation, the uTLB is not written along with the MTLB causing a
7371                                                                  uTLB miss replay to complete the uTLB fill. */
7372         uint64_t tlbiall               : 1;  /**< [ 46: 46](R/W) Treat all TLBIs like TLBI ALL for a specific exception level. */
7373         uint64_t wbfdsbflushall        : 1;  /**< [ 45: 45](R/W) Any DSB instruction flushes the write buffer. */
7374         uint64_t wbfdmbflushnext       : 1;  /**< [ 44: 44](R/W) DMB instruction to !NSH flushes next ST to !NSH.  uTLB is flushed when this value is
7375                                                                  changed. */
7376         uint64_t stexl2cforce          : 1;  /**< [ 43: 43](R/W) Send all store-exclusive instructions to L2 cache.  uTLB is flushed when this value is
7377                                                                  changed. */
7378         uint64_t ioglobalforce         : 1;  /**< [ 42: 42](R/W) Reserved.  uTLB is flushed when this value is changed.
7379                                                                  Internal:
7380                                                                  Force global order for IO references. */
7381         uint64_t wcumissforce          : 1;  /**< [ 41: 41](R/W) Force all walker cache lookups to miss.  uTLB is flushed when this value is changed. */
7382         uint64_t replayprefdis         : 1;  /**< [ 40: 40](R/W) Replay PREF disable. uTLB miss PREF instruction behavior (see chapter body).
7383                                                                  0 = PREF instructions do attempt a replay for MTLB to uTLB refill.
7384                                                                  1 = PREF instructions do not attempt a replay for MTLB to uTLB refill.
7385                                                                  uTLB is flushed when this value is changed. */
7386         uint64_t zval2cdis             : 1;  /**< [ 39: 39](R/W) ZVA bypass L2C.
7387                                                                  0 = DC_ZVA instructions to L2C are STFIL1 (full block store operation allocating in
7388                                                                  requester L2, fill 0s, self-invalidate L1 cache).
7389                                                                  1 = DC_ZVA instructions to L2C are STTIL1 (full block store operation through to DRAM,
7390                                                                  bypass home and requester L2, fill 0s, self-invalidate L1 cache). */
7391         uint64_t ldil2cdis             : 1;  /**< [ 38: 38](R/W) LDI instruction L2C usage.
7392                                                                  0 = LDI instructions to L2C are LDI (don't allocate in L1, allocates L2 at requester).
7393                                                                  1 = LDI instructions to L2C are LDT (don't allocate in L2 or L1 at home or requester). */
7394         uint64_t dcva47                : 1;  /**< [ 37: 37](R/W) If MMU translations are disabled,
7395                                                                  apply memory attributes to physical addresses where bit\<47\>
7396                                                                  is zero and device attributes to physical address bit\<47\> is
7397                                                                  one. */
7398         uint64_t stprefdis             : 1;  /**< [ 36: 36](R/W) ST PREF instructions disable. */
7399         uint64_t ldprefdis             : 1;  /**< [ 35: 35](R/W) LD PREF instructions disable. */
7400         uint64_t wfildexdis            : 1;  /**< [ 34: 34](R/W) WFE release behavior for LD-exclusive.
7401                                                                  0 = L2C invalidates to global monitor cause SEV to local core.
7402                                                                  1 = L2C invalidates have no effect on global monitor (i.e. lock_register).
7403 
7404                                                                  This field should never be set to 1; setting to 1 does not
7405                                                                  conform to the ARMv8 specification. */
7406         uint64_t wfito                 : 3;  /**< [ 33: 31](R/W) Wait-for-interrupt timeout; timeout=2^(8+[WFITO]). */
7407         uint64_t rbfshortto            : 5;  /**< [ 30: 26](R/W) Read buffer short timeout; timeout = 2^[RBFSHORTTO].
7408                                                                  Must be \>=0x6. The L2C directs the core to use either RBFSHORTTO or RBFTO. The short
7409                                                                  timeout is used when an CCPI link goes down to expedite error indication. */
7410         uint64_t rbfto                 : 5;  /**< [ 25: 21](R/W) Read buffer timeout; timeout = 2^[RBFTO]. Must be \>= 0x6. */
7411         uint64_t wbfallbarrier         : 1;  /**< [ 20: 20](R/W) Write-buffer apply barrier to all ST instructions. */
7412         uint64_t wbfnomerge            : 1;  /**< [ 19: 19](R/W) Write-buffer merge disable. */
7413         uint64_t wbftonshena           : 1;  /**< [ 18: 18](R/W) Write-buffer timeout for NSH entries enable.
7414                                                                  0 = Write-buffer time out for NSH entries = 218 cycles.
7415                                                                  1 = Write-buffer time out for NSH entries = 2^[WBFTO] (see [WBFTO]). */
7416         uint64_t wbftomrgclrena        : 1;  /**< [ 17: 17](R/W) Write-buffer timeout clear-on-merge enable. */
7417         uint64_t wbfto                 : 5;  /**< [ 16: 12](R/W) Write-buffer timeout for non-NSH entries; timeout = 2^WBFTO. */
7418         uint64_t wbfthresh             : 5;  /**< [ 11:  7](R/W) Write-buffer threshold. The write-buffer starts flushing entries to the L2 cache once the
7419                                                                  number of valid write-buffer entries reaches this threshold value. */
7420         uint64_t utlbentriesm1         : 5;  /**< [  6:  2](R/W) Number of uTLB entries - 1.  Future allocation is limited to this size (pass 1, pass 2) */
7421         uint64_t cclkforce             : 1;  /**< [  1:  1](R/W) Force CSR clock enable. When set, force CSR conditional clocking. */
7422         uint64_t mclkforce             : 1;  /**< [  0:  0](R/W) Force memory clock enable. When set, force memory conditional clocking. */
7423 #else /* Word 0 - Little Endian */
7424         uint64_t mclkforce             : 1;  /**< [  0:  0](R/W) Force memory clock enable. When set, force memory conditional clocking. */
7425         uint64_t cclkforce             : 1;  /**< [  1:  1](R/W) Force CSR clock enable. When set, force CSR conditional clocking. */
7426         uint64_t utlbentriesm1         : 5;  /**< [  6:  2](R/W) Number of uTLB entries - 1.  Future allocation is limited to this size (pass 1, pass 2) */
7427         uint64_t wbfthresh             : 5;  /**< [ 11:  7](R/W) Write-buffer threshold. The write-buffer starts flushing entries to the L2 cache once the
7428                                                                  number of valid write-buffer entries reaches this threshold value. */
7429         uint64_t wbfto                 : 5;  /**< [ 16: 12](R/W) Write-buffer timeout for non-NSH entries; timeout = 2^WBFTO. */
7430         uint64_t wbftomrgclrena        : 1;  /**< [ 17: 17](R/W) Write-buffer timeout clear-on-merge enable. */
7431         uint64_t wbftonshena           : 1;  /**< [ 18: 18](R/W) Write-buffer timeout for NSH entries enable.
7432                                                                  0 = Write-buffer time out for NSH entries = 218 cycles.
7433                                                                  1 = Write-buffer time out for NSH entries = 2^[WBFTO] (see [WBFTO]). */
7434         uint64_t wbfnomerge            : 1;  /**< [ 19: 19](R/W) Write-buffer merge disable. */
7435         uint64_t wbfallbarrier         : 1;  /**< [ 20: 20](R/W) Write-buffer apply barrier to all ST instructions. */
7436         uint64_t rbfto                 : 5;  /**< [ 25: 21](R/W) Read buffer timeout; timeout = 2^[RBFTO]. Must be \>= 0x6. */
7437         uint64_t rbfshortto            : 5;  /**< [ 30: 26](R/W) Read buffer short timeout; timeout = 2^[RBFSHORTTO].
7438                                                                  Must be \>=0x6. The L2C directs the core to use either RBFSHORTTO or RBFTO. The short
7439                                                                  timeout is used when an CCPI link goes down to expedite error indication. */
7440         uint64_t wfito                 : 3;  /**< [ 33: 31](R/W) Wait-for-interrupt timeout; timeout=2^(8+[WFITO]). */
7441         uint64_t wfildexdis            : 1;  /**< [ 34: 34](R/W) WFE release behavior for LD-exclusive.
7442                                                                  0 = L2C invalidates to global monitor cause SEV to local core.
7443                                                                  1 = L2C invalidates have no effect on global monitor (i.e. lock_register).
7444 
7445                                                                  This field should never be set to 1; setting to 1 does not
7446                                                                  conform to the ARMv8 specification. */
7447         uint64_t ldprefdis             : 1;  /**< [ 35: 35](R/W) LD PREF instructions disable. */
7448         uint64_t stprefdis             : 1;  /**< [ 36: 36](R/W) ST PREF instructions disable. */
7449         uint64_t dcva47                : 1;  /**< [ 37: 37](R/W) If MMU translations are disabled,
7450                                                                  apply memory attributes to physical addresses where bit\<47\>
7451                                                                  is zero and device attributes to physical address bit\<47\> is
7452                                                                  one. */
7453         uint64_t ldil2cdis             : 1;  /**< [ 38: 38](R/W) LDI instruction L2C usage.
7454                                                                  0 = LDI instructions to L2C are LDI (don't allocate in L1, allocates L2 at requester).
7455                                                                  1 = LDI instructions to L2C are LDT (don't allocate in L2 or L1 at home or requester). */
7456         uint64_t zval2cdis             : 1;  /**< [ 39: 39](R/W) ZVA bypass L2C.
7457                                                                  0 = DC_ZVA instructions to L2C are STFIL1 (full block store operation allocating in
7458                                                                  requester L2, fill 0s, self-invalidate L1 cache).
7459                                                                  1 = DC_ZVA instructions to L2C are STTIL1 (full block store operation through to DRAM,
7460                                                                  bypass home and requester L2, fill 0s, self-invalidate L1 cache). */
7461         uint64_t replayprefdis         : 1;  /**< [ 40: 40](R/W) Replay PREF disable. uTLB miss PREF instruction behavior (see chapter body).
7462                                                                  0 = PREF instructions do attempt a replay for MTLB to uTLB refill.
7463                                                                  1 = PREF instructions do not attempt a replay for MTLB to uTLB refill.
7464                                                                  uTLB is flushed when this value is changed. */
7465         uint64_t wcumissforce          : 1;  /**< [ 41: 41](R/W) Force all walker cache lookups to miss.  uTLB is flushed when this value is changed. */
7466         uint64_t ioglobalforce         : 1;  /**< [ 42: 42](R/W) Reserved.  uTLB is flushed when this value is changed.
7467                                                                  Internal:
7468                                                                  Force global order for IO references. */
7469         uint64_t stexl2cforce          : 1;  /**< [ 43: 43](R/W) Send all store-exclusive instructions to L2 cache.  uTLB is flushed when this value is
7470                                                                  changed. */
7471         uint64_t wbfdmbflushnext       : 1;  /**< [ 44: 44](R/W) DMB instruction to !NSH flushes next ST to !NSH.  uTLB is flushed when this value is
7472                                                                  changed. */
7473         uint64_t wbfdsbflushall        : 1;  /**< [ 45: 45](R/W) Any DSB instruction flushes the write buffer. */
7474         uint64_t tlbiall               : 1;  /**< [ 46: 46](R/W) Treat all TLBIs like TLBI ALL for a specific exception level. */
7475         uint64_t utlbfillbypdis        : 1;  /**< [ 47: 47](R/W) Disable uTLB fill bypass (pass 2.0 only).
7476                                                                  0 = On a stage1-only translation, the uTLB is written along with the MTLB.
7477                                                                  1 = On a stage1-only translation, the uTLB is not written along with the MTLB causing a
7478                                                                  uTLB miss replay to complete the uTLB fill. */
7479         uint64_t gsyncto               : 5;  /**< [ 52: 48](R/W) GlobalSync timeout. (pass 2.0 only.)
7480                                                                  timeout = 2^[GSYNCTO].
7481                                                                  0x0 = disable timeout. */
7482         uint64_t tlbiicflush           : 1;  /**< [ 53: 53](R/W) Some local TLBI instructions cause ICache flush (pass 2.0 only).
7483                                                                  0 = Icache flush operation do not happen on the TLBI instructions listed below.
7484                                                                  1 = Icache is flushed on the TLBI instructions listed below:
7485                                                                    * TLBI ALLE2{IS}.
7486                                                                    * TLBI ALLE3{IS}.
7487                                                                    * TLBI VAE1{IS}.
7488                                                                    * TLBI VALE1{IS}.
7489                                                                    * TLBI VAAE1{IS}.
7490                                                                    * TLBI VAALE1{IS}.
7491                                                                    * TLBI VAE2{IS}.
7492                                                                    * TLBI VALE2{IS}.
7493                                                                    * TLBI VAE3{IS}.
7494                                                                    * TLBI VALE3{IS}.
7495                                                                    * TLBI IPAS2E1{IS}.
7496                                                                    * TLBI IPAS2LE1{IS}. */
7497         uint64_t tlbinopdis            : 1;  /**< [ 54: 54](R/W) Disable broadcast TLBI optimization (pass 2.0 only).
7498 
7499                                                                  Address-based broadcast TLBI instructions that go to remote cores are converted
7500                                                                  from address-based TLBI instructions to context-based TLBI instructions. The
7501                                                                  actions on the local core generating the TLBI instruction are still precise.
7502 
7503                                                                  0 = The converted context-based TLBI instructions or original context-based
7504                                                                  TLBIs to remote cores (without intervening interruptions, such as a DSB) are
7505                                                                  coalesced into a single context-based TLBI. Converted and original ones do not
7506                                                                  coalesce.
7507 
7508                                                                  1 = The above-mentioned coalescing is suppressed and converted context-based
7509                                                                  remote TLBIs still go out as such. */
7510         uint64_t dmbstallforce         : 1;  /**< [ 55: 55](R/W) Force DMB to wait for flushed write-buffer entries to be ACKed (pass 2.0 only).
7511                                                                  0 = DMB instructions mark prior relevant write-buffer entries for flush, but do not wait
7512                                                                  for the ACKs to return.
7513                                                                  1 = DMB instructions mark prior relevant write-buffer entries for flush and wait for all
7514                                                                  the ACKs to return. */
7515         uint64_t stlstallforce         : 1;  /**< [ 56: 56](R/W) Force ST_release to wait for flushed write-buffer entries to be ACKed (pass 2.0 only).
7516                                                                  0 = Store-release instructions mark prior relevant write-buffer entries for flush but do
7517                                                                  not wait for the ACKs to return.
7518                                                                  1 = Store-release instructions mark prior relevant write-buffer entries for flush and wait
7519                                                                  for all the ACKs to return. */
7520         uint64_t wfeldex1dis           : 1;  /**< [ 57: 57](R/W) WFE release behavior for LD-exclusive.
7521                                                                  0 = A global monitor transition from exclusive to open (lock flag transition
7522                                                                  from 1 to 0) causes SEV to local core.
7523                                                                  1 = A global monitor transition from exclusive to open (lock flag transition
7524                                                                  from 1 to 0) does not cause SEV to local core. */
7525         uint64_t stexfailcnt           : 3;  /**< [ 60: 58](RO) ST exclusive fail count. */
7526         uint64_t node                  : 2;  /**< [ 62: 61](RO) Local node ID. */
7527         uint64_t reserved_63           : 1;
7528 #endif /* Word 0 - End */
7529     } s;
7530     struct bdk_ap_cvmmemctl0_el1_cn88xxp1
7531     {
7532 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7533         uint64_t reserved_63           : 1;
7534         uint64_t node                  : 2;  /**< [ 62: 61](RO) Local node ID. */
7535         uint64_t stexfailcnt           : 3;  /**< [ 60: 58](RO) ST exclusive fail count. */
7536         uint64_t reserved_57           : 1;
7537         uint64_t stlstallforce         : 1;  /**< [ 56: 56](R/W) Force ST_release to wait for flushed write-buffer entries to be ACKed (pass 2.0 only).
7538                                                                  0 = Store-release instructions mark prior relevant write-buffer entries for flush but do
7539                                                                  not wait for the ACKs to return.
7540                                                                  1 = Store-release instructions mark prior relevant write-buffer entries for flush and wait
7541                                                                  for all the ACKs to return. */
7542         uint64_t dmbstallforce         : 1;  /**< [ 55: 55](R/W) Force DMB to wait for flushed write-buffer entries to be ACKed (pass 2.0 only).
7543                                                                  0 = DMB instructions mark prior relevant write-buffer entries for flush, but do not wait
7544                                                                  for the ACKs to return.
7545                                                                  1 = DMB instructions mark prior relevant write-buffer entries for flush and wait for all
7546                                                                  the ACKs to return. */
7547         uint64_t tlbinopdis            : 1;  /**< [ 54: 54](R/W) Disable broadcast TLBI optimization (pass 2.0 only).
7548 
7549                                                                  Address-based broadcast TLBI instructions that go to remote cores are converted
7550                                                                  from address-based TLBI instructions to context-based TLBI instructions. The
7551                                                                  actions on the local core generating the TLBI instruction are still precise.
7552 
7553                                                                  0 = The converted context-based TLBI instructions or original context-based
7554                                                                  TLBIs to remote cores (without intervening interruptions, such as a DSB) are
7555                                                                  coalesced into a single context-based TLBI. Converted and original ones do not
7556                                                                  coalesce.
7557 
7558                                                                  1 = The above-mentioned coalescing is suppressed and converted context-based
7559                                                                  remote TLBIs still go out as such. */
7560         uint64_t tlbiicflush           : 1;  /**< [ 53: 53](R/W) Some local TLBI instructions cause ICache flush (pass 2.0 only).
7561                                                                  0 = Icache flush operation do not happen on the TLBI instructions listed below.
7562                                                                  1 = Icache is flushed on the TLBI instructions listed below:
7563                                                                    * TLBI ALLE2{IS}.
7564                                                                    * TLBI ALLE3{IS}.
7565                                                                    * TLBI VAE1{IS}.
7566                                                                    * TLBI VALE1{IS}.
7567                                                                    * TLBI VAAE1{IS}.
7568                                                                    * TLBI VAALE1{IS}.
7569                                                                    * TLBI VAE2{IS}.
7570                                                                    * TLBI VALE2{IS}.
7571                                                                    * TLBI VAE3{IS}.
7572                                                                    * TLBI VALE3{IS}.
7573                                                                    * TLBI IPAS2E1{IS}.
7574                                                                    * TLBI IPAS2LE1{IS}. */
7575         uint64_t gsyncto               : 5;  /**< [ 52: 48](R/W) GlobalSync timeout. (pass 2.0 only.)
7576                                                                  timeout = 2^[GSYNCTO].
7577                                                                  0x0 = disable timeout. */
7578         uint64_t utlbfillbypdis        : 1;  /**< [ 47: 47](R/W) Disable uTLB fill bypass (pass 2.0 only).
7579                                                                  0 = On a stage1-only translation, the uTLB is written along with the MTLB.
7580                                                                  1 = On a stage1-only translation, the uTLB is not written along with the MTLB causing a
7581                                                                  uTLB miss replay to complete the uTLB fill. */
7582         uint64_t tlbiall               : 1;  /**< [ 46: 46](R/W) Treat all TLBIs like TLBI ALL for a specific exception level. */
7583         uint64_t wbfdsbflushall        : 1;  /**< [ 45: 45](R/W) Any DSB instruction flushes the write buffer. */
7584         uint64_t wbfdmbflushnext       : 1;  /**< [ 44: 44](R/W) DMB instruction to !NSH flushes next ST to !NSH.  uTLB is flushed when this value is
7585                                                                  changed. */
7586         uint64_t stexl2cforce          : 1;  /**< [ 43: 43](R/W) Send all store-exclusive instructions to L2 cache.  uTLB is flushed when this value is
7587                                                                  changed. */
7588         uint64_t ioglobalforce         : 1;  /**< [ 42: 42](R/W) Reserved.  uTLB is flushed when this value is changed.
7589                                                                  Internal:
7590                                                                  Force global order for IO references. */
7591         uint64_t wcumissforce          : 1;  /**< [ 41: 41](R/W) Force all walker cache lookups to miss.  uTLB is flushed when this value is changed. */
7592         uint64_t replayprefdis         : 1;  /**< [ 40: 40](R/W) Replay PREF disable. uTLB miss PREF instruction behavior (see chapter body).
7593                                                                  0 = PREF instructions do attempt a replay for MTLB to uTLB refill.
7594                                                                  1 = PREF instructions do not attempt a replay for MTLB to uTLB refill.
7595                                                                  uTLB is flushed when this value is changed. */
7596         uint64_t zval2cdis             : 1;  /**< [ 39: 39](R/W) ZVA bypass L2C.
7597                                                                  0 = DC_ZVA instructions to L2C are STFIL1 (full block store operation allocating in
7598                                                                  requester L2, fill 0s, self-invalidate L1 cache).
7599                                                                  1 = DC_ZVA instructions to L2C are STTIL1 (full block store operation through to DRAM,
7600                                                                  bypass home and requester L2, fill 0s, self-invalidate L1 cache). */
7601         uint64_t ldil2cdis             : 1;  /**< [ 38: 38](R/W) LDI instruction L2C usage.
7602                                                                  0 = LDI instructions to L2C are LDI (don't allocate in L1, allocates L2 at requester).
7603                                                                  1 = LDI instructions to L2C are LDT (don't allocate in L2 or L1 at home or requester). */
7604         uint64_t dcva47                : 1;  /**< [ 37: 37](R/W) If MMU translations are disabled,
7605                                                                  apply memory attributes to physical addresses where bit\<47\>
7606                                                                  is zero and device attributes to physical address bit\<47\> is
7607                                                                  one. */
7608         uint64_t stprefdis             : 1;  /**< [ 36: 36](R/W) ST PREF instructions disable. */
7609         uint64_t ldprefdis             : 1;  /**< [ 35: 35](R/W) LD PREF instructions disable. */
7610         uint64_t wfildexdis            : 1;  /**< [ 34: 34](R/W) WFE release behavior for LD-exclusive.
7611                                                                  0 = L2C invalidates to global monitor cause SEV to local core.
7612                                                                  1 = L2C invalidates have no effect on global monitor (i.e. lock_register).
7613 
7614                                                                  This field should never be set to 1; setting to 1 does not
7615                                                                  conform to the ARMv8 specification. */
7616         uint64_t wfito                 : 3;  /**< [ 33: 31](R/W) Wait-for-interrupt timeout; timeout=2^(8+[WFITO]). */
7617         uint64_t rbfshortto            : 5;  /**< [ 30: 26](R/W) Read buffer short timeout; timeout = 2^[RBFSHORTTO].
7618                                                                  Must be \>=0x6. The L2C directs the core to use either RBFSHORTTO or RBFTO. The short
7619                                                                  timeout is used when an CCPI link goes down to expedite error indication. */
7620         uint64_t rbfto                 : 5;  /**< [ 25: 21](R/W) Read buffer timeout; timeout = 2^[RBFTO]. Must be \>= 0x6. */
7621         uint64_t wbfallbarrier         : 1;  /**< [ 20: 20](R/W) Write-buffer apply barrier to all ST instructions. */
7622         uint64_t wbfnomerge            : 1;  /**< [ 19: 19](R/W) Write-buffer merge disable. */
7623         uint64_t wbftonshena           : 1;  /**< [ 18: 18](R/W) Write-buffer timeout for NSH entries enable.
7624                                                                  0 = Write-buffer time out for NSH entries = 218 cycles.
7625                                                                  1 = Write-buffer time out for NSH entries = 2^[WBFTO] (see [WBFTO]). */
7626         uint64_t wbftomrgclrena        : 1;  /**< [ 17: 17](R/W) Write-buffer timeout clear-on-merge enable. */
7627         uint64_t wbfto                 : 5;  /**< [ 16: 12](R/W) Write-buffer timeout for non-NSH entries; timeout = 2^WBFTO. */
7628         uint64_t wbfthresh             : 5;  /**< [ 11:  7](R/W) Write-buffer threshold. The write-buffer starts flushing entries to the L2 cache once the
7629                                                                  number of valid write-buffer entries reaches this threshold value. */
7630         uint64_t utlbentriesm1         : 5;  /**< [  6:  2](R/W) Number of uTLB entries - 1.  Future allocation is limited to this size (pass 1, pass 2) */
7631         uint64_t cclkforce             : 1;  /**< [  1:  1](R/W) Force CSR clock enable. When set, force CSR conditional clocking. */
7632         uint64_t mclkforce             : 1;  /**< [  0:  0](R/W) Force memory clock enable. When set, force memory conditional clocking. */
7633 #else /* Word 0 - Little Endian */
7634         uint64_t mclkforce             : 1;  /**< [  0:  0](R/W) Force memory clock enable. When set, force memory conditional clocking. */
7635         uint64_t cclkforce             : 1;  /**< [  1:  1](R/W) Force CSR clock enable. When set, force CSR conditional clocking. */
7636         uint64_t utlbentriesm1         : 5;  /**< [  6:  2](R/W) Number of uTLB entries - 1.  Future allocation is limited to this size (pass 1, pass 2) */
7637         uint64_t wbfthresh             : 5;  /**< [ 11:  7](R/W) Write-buffer threshold. The write-buffer starts flushing entries to the L2 cache once the
7638                                                                  number of valid write-buffer entries reaches this threshold value. */
7639         uint64_t wbfto                 : 5;  /**< [ 16: 12](R/W) Write-buffer timeout for non-NSH entries; timeout = 2^WBFTO. */
7640         uint64_t wbftomrgclrena        : 1;  /**< [ 17: 17](R/W) Write-buffer timeout clear-on-merge enable. */
7641         uint64_t wbftonshena           : 1;  /**< [ 18: 18](R/W) Write-buffer timeout for NSH entries enable.
7642                                                                  0 = Write-buffer time out for NSH entries = 218 cycles.
7643                                                                  1 = Write-buffer time out for NSH entries = 2^[WBFTO] (see [WBFTO]). */
7644         uint64_t wbfnomerge            : 1;  /**< [ 19: 19](R/W) Write-buffer merge disable. */
7645         uint64_t wbfallbarrier         : 1;  /**< [ 20: 20](R/W) Write-buffer apply barrier to all ST instructions. */
7646         uint64_t rbfto                 : 5;  /**< [ 25: 21](R/W) Read buffer timeout; timeout = 2^[RBFTO]. Must be \>= 0x6. */
7647         uint64_t rbfshortto            : 5;  /**< [ 30: 26](R/W) Read buffer short timeout; timeout = 2^[RBFSHORTTO].
7648                                                                  Must be \>=0x6. The L2C directs the core to use either RBFSHORTTO or RBFTO. The short
7649                                                                  timeout is used when an CCPI link goes down to expedite error indication. */
7650         uint64_t wfito                 : 3;  /**< [ 33: 31](R/W) Wait-for-interrupt timeout; timeout=2^(8+[WFITO]). */
7651         uint64_t wfildexdis            : 1;  /**< [ 34: 34](R/W) WFE release behavior for LD-exclusive.
7652                                                                  0 = L2C invalidates to global monitor cause SEV to local core.
7653                                                                  1 = L2C invalidates have no effect on global monitor (i.e. lock_register).
7654 
7655                                                                  This field should never be set to 1; setting to 1 does not
7656                                                                  conform to the ARMv8 specification. */
7657         uint64_t ldprefdis             : 1;  /**< [ 35: 35](R/W) LD PREF instructions disable. */
7658         uint64_t stprefdis             : 1;  /**< [ 36: 36](R/W) ST PREF instructions disable. */
7659         uint64_t dcva47                : 1;  /**< [ 37: 37](R/W) If MMU translations are disabled,
7660                                                                  apply memory attributes to physical addresses where bit\<47\>
7661                                                                  is zero and device attributes to physical address bit\<47\> is
7662                                                                  one. */
7663         uint64_t ldil2cdis             : 1;  /**< [ 38: 38](R/W) LDI instruction L2C usage.
7664                                                                  0 = LDI instructions to L2C are LDI (don't allocate in L1, allocates L2 at requester).
7665                                                                  1 = LDI instructions to L2C are LDT (don't allocate in L2 or L1 at home or requester). */
7666         uint64_t zval2cdis             : 1;  /**< [ 39: 39](R/W) ZVA bypass L2C.
7667                                                                  0 = DC_ZVA instructions to L2C are STFIL1 (full block store operation allocating in
7668                                                                  requester L2, fill 0s, self-invalidate L1 cache).
7669                                                                  1 = DC_ZVA instructions to L2C are STTIL1 (full block store operation through to DRAM,
7670                                                                  bypass home and requester L2, fill 0s, self-invalidate L1 cache). */
7671         uint64_t replayprefdis         : 1;  /**< [ 40: 40](R/W) Replay PREF disable. uTLB miss PREF instruction behavior (see chapter body).
7672                                                                  0 = PREF instructions do attempt a replay for MTLB to uTLB refill.
7673                                                                  1 = PREF instructions do not attempt a replay for MTLB to uTLB refill.
7674                                                                  uTLB is flushed when this value is changed. */
7675         uint64_t wcumissforce          : 1;  /**< [ 41: 41](R/W) Force all walker cache lookups to miss.  uTLB is flushed when this value is changed. */
7676         uint64_t ioglobalforce         : 1;  /**< [ 42: 42](R/W) Reserved.  uTLB is flushed when this value is changed.
7677                                                                  Internal:
7678                                                                  Force global order for IO references. */
7679         uint64_t stexl2cforce          : 1;  /**< [ 43: 43](R/W) Send all store-exclusive instructions to L2 cache.  uTLB is flushed when this value is
7680                                                                  changed. */
7681         uint64_t wbfdmbflushnext       : 1;  /**< [ 44: 44](R/W) DMB instruction to !NSH flushes next ST to !NSH.  uTLB is flushed when this value is
7682                                                                  changed. */
7683         uint64_t wbfdsbflushall        : 1;  /**< [ 45: 45](R/W) Any DSB instruction flushes the write buffer. */
7684         uint64_t tlbiall               : 1;  /**< [ 46: 46](R/W) Treat all TLBIs like TLBI ALL for a specific exception level. */
7685         uint64_t utlbfillbypdis        : 1;  /**< [ 47: 47](R/W) Disable uTLB fill bypass (pass 2.0 only).
7686                                                                  0 = On a stage1-only translation, the uTLB is written along with the MTLB.
7687                                                                  1 = On a stage1-only translation, the uTLB is not written along with the MTLB causing a
7688                                                                  uTLB miss replay to complete the uTLB fill. */
7689         uint64_t gsyncto               : 5;  /**< [ 52: 48](R/W) GlobalSync timeout. (pass 2.0 only.)
7690                                                                  timeout = 2^[GSYNCTO].
7691                                                                  0x0 = disable timeout. */
7692         uint64_t tlbiicflush           : 1;  /**< [ 53: 53](R/W) Some local TLBI instructions cause ICache flush (pass 2.0 only).
7693                                                                  0 = Icache flush operation do not happen on the TLBI instructions listed below.
7694                                                                  1 = Icache is flushed on the TLBI instructions listed below:
7695                                                                    * TLBI ALLE2{IS}.
7696                                                                    * TLBI ALLE3{IS}.
7697                                                                    * TLBI VAE1{IS}.
7698                                                                    * TLBI VALE1{IS}.
7699                                                                    * TLBI VAAE1{IS}.
7700                                                                    * TLBI VAALE1{IS}.
7701                                                                    * TLBI VAE2{IS}.
7702                                                                    * TLBI VALE2{IS}.
7703                                                                    * TLBI VAE3{IS}.
7704                                                                    * TLBI VALE3{IS}.
7705                                                                    * TLBI IPAS2E1{IS}.
7706                                                                    * TLBI IPAS2LE1{IS}. */
7707         uint64_t tlbinopdis            : 1;  /**< [ 54: 54](R/W) Disable broadcast TLBI optimization (pass 2.0 only).
7708 
7709                                                                  Address-based broadcast TLBI instructions that go to remote cores are converted
7710                                                                  from address-based TLBI instructions to context-based TLBI instructions. The
7711                                                                  actions on the local core generating the TLBI instruction are still precise.
7712 
7713                                                                  0 = The converted context-based TLBI instructions or original context-based
7714                                                                  TLBIs to remote cores (without intervening interruptions, such as a DSB) are
7715                                                                  coalesced into a single context-based TLBI. Converted and original ones do not
7716                                                                  coalesce.
7717 
7718                                                                  1 = The above-mentioned coalescing is suppressed and converted context-based
7719                                                                  remote TLBIs still go out as such. */
7720         uint64_t dmbstallforce         : 1;  /**< [ 55: 55](R/W) Force DMB to wait for flushed write-buffer entries to be ACKed (pass 2.0 only).
7721                                                                  0 = DMB instructions mark prior relevant write-buffer entries for flush, but do not wait
7722                                                                  for the ACKs to return.
7723                                                                  1 = DMB instructions mark prior relevant write-buffer entries for flush and wait for all
7724                                                                  the ACKs to return. */
7725         uint64_t stlstallforce         : 1;  /**< [ 56: 56](R/W) Force ST_release to wait for flushed write-buffer entries to be ACKed (pass 2.0 only).
7726                                                                  0 = Store-release instructions mark prior relevant write-buffer entries for flush but do
7727                                                                  not wait for the ACKs to return.
7728                                                                  1 = Store-release instructions mark prior relevant write-buffer entries for flush and wait
7729                                                                  for all the ACKs to return. */
7730         uint64_t reserved_57           : 1;
7731         uint64_t stexfailcnt           : 3;  /**< [ 60: 58](RO) ST exclusive fail count. */
7732         uint64_t node                  : 2;  /**< [ 62: 61](RO) Local node ID. */
7733         uint64_t reserved_63           : 1;
7734 #endif /* Word 0 - End */
7735     } cn88xxp1;
7736     struct bdk_ap_cvmmemctl0_el1_cn9
7737     {
7738 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7739         uint64_t reserved_63           : 1;
7740         uint64_t node                  : 2;  /**< [ 62: 61](RO) Local node ID. */
7741         uint64_t stexfailcnt           : 3;  /**< [ 60: 58](RO) ST exclusive fail count. */
7742         uint64_t wfeldex1dis           : 1;  /**< [ 57: 57](R/W) WFE release behavior for LD-exclusive.
7743                                                                  0 = A global monitor transition from exclusive to open (lock flag transition
7744                                                                  from 1 to 0) causes SEV to local core.
7745                                                                  1 = A global monitor transition from exclusive to open (lock flag transition
7746                                                                  from 1 to 0) does not cause SEV to local core. */
7747         uint64_t stlstallforce         : 1;  /**< [ 56: 56](R/W) Force ST_release to wait for flushed write-buffer entries to be ACKed.
7748                                                                  0 = Store-release instructions mark prior relevant write-buffer entries for flush but do
7749                                                                  not wait for the ACKs to return.
7750                                                                  1 = Store-release instructions mark prior relevant write-buffer entries for flush and wait
7751                                                                  for all the ACKs to return. */
7752         uint64_t dmbstallforce         : 1;  /**< [ 55: 55](R/W) Force DMB to wait for flushed write-buffer entries to be ACKed.
7753                                                                  0 = DMB instructions mark prior relevant write-buffer entries for flush, but do not wait
7754                                                                  for the ACKs to return.
7755                                                                  1 = DMB instructions mark prior relevant write-buffer entries for flush and wait for all
7756                                                                  the ACKs to return. */
7757         uint64_t tlbinopdis            : 1;  /**< [ 54: 54](R/W) Disable broadcast TLBI optimization.
7758 
7759                                                                  Address-based broadcast TLBI instructions that go to remote cores are converted
7760                                                                  from address-based TLBI instructions to context-based TLBI instructions. The
7761                                                                  actions on the local core generating the TLBI instruction are still precise.
7762 
7763                                                                  0 = The converted context-based TLBI instructions or original context-based
7764                                                                  TLBIs to remote cores (without intervening interruptions, such as a DSB) are
7765                                                                  coalesced into a single context-based TLBI. Converted and original ones do not
7766                                                                  coalesce.
7767 
7768                                                                  1 = The above-mentioned coalescing is suppressed and converted context-based
7769                                                                  remote TLBIs still go out as such. */
7770         uint64_t tlbiicflush           : 1;  /**< [ 53: 53](R/W) Some local TLBI instructions cause ICache flush.
7771                                                                  0 = Icache flush operation do not happen on the TLBI instructions listed below.
7772                                                                  1 = Icache is flushed on the TLBI instructions listed below:
7773                                                                    * TLBI ALLE2{IS}.
7774                                                                    * TLBI ALLE3{IS}.
7775                                                                    * TLBI VAE1{IS}.
7776                                                                    * TLBI VALE1{IS}.
7777                                                                    * TLBI VAAE1{IS}.
7778                                                                    * TLBI VAALE1{IS}.
7779                                                                    * TLBI VAE2{IS}.
7780                                                                    * TLBI VALE2{IS}.
7781                                                                    * TLBI VAE3{IS}.
7782                                                                    * TLBI VALE3{IS}.
7783                                                                    * TLBI IPAS2E1{IS}.
7784                                                                    * TLBI IPAS2LE1{IS}. */
7785         uint64_t gsyncto               : 5;  /**< [ 52: 48](R/W) GlobalSync timeout.
7786                                                                  timeout = 2^[GSYNCTO].
7787                                                                  0x0 = disable timeout. */
7788         uint64_t utlbfillbypdis        : 1;  /**< [ 47: 47](R/W) Disable uTLB fill bypass.
7789                                                                  0 = On a stage1-only translation, the uTLB is written along with the MTLB.
7790                                                                  1 = On a stage1-only translation, the uTLB is not written along with the MTLB causing a
7791                                                                  uTLB miss replay to complete the uTLB fill. */
7792         uint64_t tlbiall               : 1;  /**< [ 46: 46](R/W) Treat all TLBIs like TLBI ALL for a specific exception level. */
7793         uint64_t wbfdsbflushall        : 1;  /**< [ 45: 45](R/W) Any DSB instruction flushes the write buffer. */
7794         uint64_t wbfdmbflushnext       : 1;  /**< [ 44: 44](R/W) DMB instruction to !NSH flushes next ST to !NSH.  uTLB is not flushed with this value is
7795                                                                  changed. */
7796         uint64_t stexl2cforce          : 1;  /**< [ 43: 43](R/W) Send all store-exclusive instructions to L2 cache.  uTLB is not flushed with this value is
7797                                                                  changed. */
7798         uint64_t ioglobalforce         : 1;  /**< [ 42: 42](R/W) Reserved.
7799                                                                  Internal:
7800                                                                  Force global order for IO references. */
7801         uint64_t wcumissforce          : 1;  /**< [ 41: 41](R/W) Force all walker cache lookups to miss.  uTLB is not flushed with this value is changed. */
7802         uint64_t replayprefdis         : 1;  /**< [ 40: 40](R/W) Replay PREF disable. uTLB miss PREF instruction behavior (see chapter body).
7803                                                                  0 = PREF instructions do attempt a replay for MTLB to uTLB refill.
7804                                                                  1 = PREF instructions do not attempt a replay for MTLB to uTLB refill.
7805 
7806                                                                  uTLB is not flushed with this value is changed. */
7807         uint64_t zval2cdis             : 1;  /**< [ 39: 39](R/W) ZVA bypass L2C.
7808                                                                  0 = DC_ZVA instructions to L2C are STFIL1 (full block store operation allocating in
7809                                                                  requester L2, fill 0s, self-invalidate L1 cache).
7810                                                                  1 = DC_ZVA instructions to L2C are STTIL1 (full block store operation through to DRAM,
7811                                                                  bypass home and requester L2, fill 0s, self-invalidate L1 cache). */
7812         uint64_t ldil2cdis             : 1;  /**< [ 38: 38](R/W) LDI instruction L2C usage.
7813                                                                  0 = LDI instructions to L2C are LDI (don't allocate in L1, allocates L2 at requester).
7814                                                                  1 = LDI instructions to L2C are LDT (don't allocate in L2 or L1 at home or requester). */
7815         uint64_t dcva47                : 1;  /**< [ 37: 37](R/W) If MMU translations are disabled,
7816                                                                  apply memory attributes to physical addresses where bit\<47\>
7817                                                                  is zero and device attributes to physical address bit\<47\> is
7818                                                                  one. */
7819         uint64_t stprefdis             : 1;  /**< [ 36: 36](R/W) ST PREF instructions disable. */
7820         uint64_t ldprefdis             : 1;  /**< [ 35: 35](R/W) LD PREF instructions disable. */
7821         uint64_t wfildexdis            : 1;  /**< [ 34: 34](R/W) WFE release behavior for LD-exclusive.
7822                                                                  0 = L2C invalidates to global monitor cause SEV to local core.
7823                                                                  1 = L2C invalidates have no effect on global monitor (i.e. lock_register).
7824 
7825                                                                  This field should never be set to 1; setting to 1 does not
7826                                                                  conform to the ARMv8 specification. */
7827         uint64_t wfito                 : 3;  /**< [ 33: 31](R/W) Wait-for-interrupt timeout; timeout=2^(8+[WFITO]). */
7828         uint64_t rbfshortto            : 5;  /**< [ 30: 26](R/W) Read buffer short timeout; timeout = 2^[RBFSHORTTO+6].
7829                                                                  The L2C directs the core to use either RBFSHORTTO or RBFTO. The short
7830                                                                  timeout is used when an CCPI link goes down to expedite error indication. */
7831         uint64_t rbfto                 : 5;  /**< [ 25: 21](R/W) Read buffer timeout; timeout = 2^[RBFTO+6]. */
7832         uint64_t wbfallbarrier         : 1;  /**< [ 20: 20](R/W) Write-buffer apply barrier to all ST instructions. */
7833         uint64_t wbfnomerge            : 1;  /**< [ 19: 19](R/W) Write-buffer merge disable. */
7834         uint64_t wbftonshena           : 1;  /**< [ 18: 18](R/W) Write-buffer timeout for NSH entries enable.
7835                                                                  0 = Write-buffer time out for NSH entries = 218 cycles.
7836                                                                  1 = Write-buffer time out for NSH entries = 2^[WBFTO] (see [WBFTO]). */
7837         uint64_t wbftomrgclrena        : 1;  /**< [ 17: 17](R/W) Write-buffer timeout clear-on-merge enable. */
7838         uint64_t wbfto                 : 5;  /**< [ 16: 12](R/W) Write-buffer timeout for non-NSH entries; timeout = 2^WBFTO. */
7839         uint64_t wbfthresh             : 5;  /**< [ 11:  7](R/W) Write-buffer threshold. The write-buffer starts flushing entries to the L2 cache once the
7840                                                                  number of valid write-buffer entries reaches this threshold value. */
7841         uint64_t utlbentriesm1         : 5;  /**< [  6:  2](R/W) Number of uTLB entries minus one.  uTLB is flushed when this value is changed. */
7842         uint64_t cclkforce             : 1;  /**< [  1:  1](R/W) Force CSR clock enable. When set, force CSR conditional clocking. */
7843         uint64_t mclkforce             : 1;  /**< [  0:  0](R/W) Force memory clock enable. When set, force memory conditional clocking. */
7844 #else /* Word 0 - Little Endian */
7845         uint64_t mclkforce             : 1;  /**< [  0:  0](R/W) Force memory clock enable. When set, force memory conditional clocking. */
7846         uint64_t cclkforce             : 1;  /**< [  1:  1](R/W) Force CSR clock enable. When set, force CSR conditional clocking. */
7847         uint64_t utlbentriesm1         : 5;  /**< [  6:  2](R/W) Number of uTLB entries minus one.  uTLB is flushed when this value is changed. */
7848         uint64_t wbfthresh             : 5;  /**< [ 11:  7](R/W) Write-buffer threshold. The write-buffer starts flushing entries to the L2 cache once the
7849                                                                  number of valid write-buffer entries reaches this threshold value. */
7850         uint64_t wbfto                 : 5;  /**< [ 16: 12](R/W) Write-buffer timeout for non-NSH entries; timeout = 2^WBFTO. */
7851         uint64_t wbftomrgclrena        : 1;  /**< [ 17: 17](R/W) Write-buffer timeout clear-on-merge enable. */
7852         uint64_t wbftonshena           : 1;  /**< [ 18: 18](R/W) Write-buffer timeout for NSH entries enable.
7853                                                                  0 = Write-buffer time out for NSH entries = 218 cycles.
7854                                                                  1 = Write-buffer time out for NSH entries = 2^[WBFTO] (see [WBFTO]). */
7855         uint64_t wbfnomerge            : 1;  /**< [ 19: 19](R/W) Write-buffer merge disable. */
7856         uint64_t wbfallbarrier         : 1;  /**< [ 20: 20](R/W) Write-buffer apply barrier to all ST instructions. */
7857         uint64_t rbfto                 : 5;  /**< [ 25: 21](R/W) Read buffer timeout; timeout = 2^[RBFTO+6]. */
7858         uint64_t rbfshortto            : 5;  /**< [ 30: 26](R/W) Read buffer short timeout; timeout = 2^[RBFSHORTTO+6].
7859                                                                  The L2C directs the core to use either RBFSHORTTO or RBFTO. The short
7860                                                                  timeout is used when an CCPI link goes down to expedite error indication. */
7861         uint64_t wfito                 : 3;  /**< [ 33: 31](R/W) Wait-for-interrupt timeout; timeout=2^(8+[WFITO]). */
7862         uint64_t wfildexdis            : 1;  /**< [ 34: 34](R/W) WFE release behavior for LD-exclusive.
7863                                                                  0 = L2C invalidates to global monitor cause SEV to local core.
7864                                                                  1 = L2C invalidates have no effect on global monitor (i.e. lock_register).
7865 
7866                                                                  This field should never be set to 1; setting to 1 does not
7867                                                                  conform to the ARMv8 specification. */
7868         uint64_t ldprefdis             : 1;  /**< [ 35: 35](R/W) LD PREF instructions disable. */
7869         uint64_t stprefdis             : 1;  /**< [ 36: 36](R/W) ST PREF instructions disable. */
7870         uint64_t dcva47                : 1;  /**< [ 37: 37](R/W) If MMU translations are disabled,
7871                                                                  apply memory attributes to physical addresses where bit\<47\>
7872                                                                  is zero and device attributes to physical address bit\<47\> is
7873                                                                  one. */
7874         uint64_t ldil2cdis             : 1;  /**< [ 38: 38](R/W) LDI instruction L2C usage.
7875                                                                  0 = LDI instructions to L2C are LDI (don't allocate in L1, allocates L2 at requester).
7876                                                                  1 = LDI instructions to L2C are LDT (don't allocate in L2 or L1 at home or requester). */
7877         uint64_t zval2cdis             : 1;  /**< [ 39: 39](R/W) ZVA bypass L2C.
7878                                                                  0 = DC_ZVA instructions to L2C are STFIL1 (full block store operation allocating in
7879                                                                  requester L2, fill 0s, self-invalidate L1 cache).
7880                                                                  1 = DC_ZVA instructions to L2C are STTIL1 (full block store operation through to DRAM,
7881                                                                  bypass home and requester L2, fill 0s, self-invalidate L1 cache). */
7882         uint64_t replayprefdis         : 1;  /**< [ 40: 40](R/W) Replay PREF disable. uTLB miss PREF instruction behavior (see chapter body).
7883                                                                  0 = PREF instructions do attempt a replay for MTLB to uTLB refill.
7884                                                                  1 = PREF instructions do not attempt a replay for MTLB to uTLB refill.
7885 
7886                                                                  uTLB is not flushed with this value is changed. */
7887         uint64_t wcumissforce          : 1;  /**< [ 41: 41](R/W) Force all walker cache lookups to miss.  uTLB is not flushed with this value is changed. */
7888         uint64_t ioglobalforce         : 1;  /**< [ 42: 42](R/W) Reserved.
7889                                                                  Internal:
7890                                                                  Force global order for IO references. */
7891         uint64_t stexl2cforce          : 1;  /**< [ 43: 43](R/W) Send all store-exclusive instructions to L2 cache.  uTLB is not flushed with this value is
7892                                                                  changed. */
7893         uint64_t wbfdmbflushnext       : 1;  /**< [ 44: 44](R/W) DMB instruction to !NSH flushes next ST to !NSH.  uTLB is not flushed with this value is
7894                                                                  changed. */
7895         uint64_t wbfdsbflushall        : 1;  /**< [ 45: 45](R/W) Any DSB instruction flushes the write buffer. */
7896         uint64_t tlbiall               : 1;  /**< [ 46: 46](R/W) Treat all TLBIs like TLBI ALL for a specific exception level. */
7897         uint64_t utlbfillbypdis        : 1;  /**< [ 47: 47](R/W) Disable uTLB fill bypass.
7898                                                                  0 = On a stage1-only translation, the uTLB is written along with the MTLB.
7899                                                                  1 = On a stage1-only translation, the uTLB is not written along with the MTLB causing a
7900                                                                  uTLB miss replay to complete the uTLB fill. */
7901         uint64_t gsyncto               : 5;  /**< [ 52: 48](R/W) GlobalSync timeout.
7902                                                                  timeout = 2^[GSYNCTO].
7903                                                                  0x0 = disable timeout. */
7904         uint64_t tlbiicflush           : 1;  /**< [ 53: 53](R/W) Some local TLBI instructions cause ICache flush.
7905                                                                  0 = Icache flush operation do not happen on the TLBI instructions listed below.
7906                                                                  1 = Icache is flushed on the TLBI instructions listed below:
7907                                                                    * TLBI ALLE2{IS}.
7908                                                                    * TLBI ALLE3{IS}.
7909                                                                    * TLBI VAE1{IS}.
7910                                                                    * TLBI VALE1{IS}.
7911                                                                    * TLBI VAAE1{IS}.
7912                                                                    * TLBI VAALE1{IS}.
7913                                                                    * TLBI VAE2{IS}.
7914                                                                    * TLBI VALE2{IS}.
7915                                                                    * TLBI VAE3{IS}.
7916                                                                    * TLBI VALE3{IS}.
7917                                                                    * TLBI IPAS2E1{IS}.
7918                                                                    * TLBI IPAS2LE1{IS}. */
7919         uint64_t tlbinopdis            : 1;  /**< [ 54: 54](R/W) Disable broadcast TLBI optimization.
7920 
7921                                                                  Address-based broadcast TLBI instructions that go to remote cores are converted
7922                                                                  from address-based TLBI instructions to context-based TLBI instructions. The
7923                                                                  actions on the local core generating the TLBI instruction are still precise.
7924 
7925                                                                  0 = The converted context-based TLBI instructions or original context-based
7926                                                                  TLBIs to remote cores (without intervening interruptions, such as a DSB) are
7927                                                                  coalesced into a single context-based TLBI. Converted and original ones do not
7928                                                                  coalesce.
7929 
7930                                                                  1 = The above-mentioned coalescing is suppressed and converted context-based
7931                                                                  remote TLBIs still go out as such. */
7932         uint64_t dmbstallforce         : 1;  /**< [ 55: 55](R/W) Force DMB to wait for flushed write-buffer entries to be ACKed.
7933                                                                  0 = DMB instructions mark prior relevant write-buffer entries for flush, but do not wait
7934                                                                  for the ACKs to return.
7935                                                                  1 = DMB instructions mark prior relevant write-buffer entries for flush and wait for all
7936                                                                  the ACKs to return. */
7937         uint64_t stlstallforce         : 1;  /**< [ 56: 56](R/W) Force ST_release to wait for flushed write-buffer entries to be ACKed.
7938                                                                  0 = Store-release instructions mark prior relevant write-buffer entries for flush but do
7939                                                                  not wait for the ACKs to return.
7940                                                                  1 = Store-release instructions mark prior relevant write-buffer entries for flush and wait
7941                                                                  for all the ACKs to return. */
7942         uint64_t wfeldex1dis           : 1;  /**< [ 57: 57](R/W) WFE release behavior for LD-exclusive.
7943                                                                  0 = A global monitor transition from exclusive to open (lock flag transition
7944                                                                  from 1 to 0) causes SEV to local core.
7945                                                                  1 = A global monitor transition from exclusive to open (lock flag transition
7946                                                                  from 1 to 0) does not cause SEV to local core. */
7947         uint64_t stexfailcnt           : 3;  /**< [ 60: 58](RO) ST exclusive fail count. */
7948         uint64_t node                  : 2;  /**< [ 62: 61](RO) Local node ID. */
7949         uint64_t reserved_63           : 1;
7950 #endif /* Word 0 - End */
7951     } cn9;
7952     struct bdk_ap_cvmmemctl0_el1_cn81xx
7953     {
7954 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
7955         uint64_t reserved_63           : 1;
7956         uint64_t node                  : 2;  /**< [ 62: 61](RO) Local node ID. */
7957         uint64_t stexfailcnt           : 3;  /**< [ 60: 58](RO) ST exclusive fail count. */
7958         uint64_t wfeldex1dis           : 1;  /**< [ 57: 57](R/W) WFE release behavior for LD-exclusive.
7959                                                                  0 = A global monitor transition from exclusive to open (lock flag transition
7960                                                                  from 1 to 0) causes SEV to local core.
7961                                                                  1 = A global monitor transition from exclusive to open (lock flag transition
7962                                                                  from 1 to 0) does not cause SEV to local core. */
7963         uint64_t stlstallforce         : 1;  /**< [ 56: 56](R/W) Force ST_release to wait for flushed write-buffer entries to be ACKed.
7964                                                                  0 = Store-release instructions mark prior relevant write-buffer entries for flush but do
7965                                                                  not wait for the ACKs to return.
7966                                                                  1 = Store-release instructions mark prior relevant write-buffer entries for flush and wait
7967                                                                  for all the ACKs to return. */
7968         uint64_t dmbstallforce         : 1;  /**< [ 55: 55](R/W) Force DMB to wait for flushed write-buffer entries to be ACKed.
7969                                                                  0 = DMB instructions mark prior relevant write-buffer entries for flush, but do not wait
7970                                                                  for the ACKs to return.
7971                                                                  1 = DMB instructions mark prior relevant write-buffer entries for flush and wait for all
7972                                                                  the ACKs to return. */
7973         uint64_t tlbinopdis            : 1;  /**< [ 54: 54](R/W) Disable broadcast TLBI optimization.
7974 
7975                                                                  Address-based broadcast TLBI instructions that go to remote cores are converted
7976                                                                  from address-based TLBI instructions to context-based TLBI instructions. The
7977                                                                  actions on the local core generating the TLBI instruction are still precise.
7978 
7979                                                                  0 = The converted context-based TLBI instructions or original context-based
7980                                                                  TLBIs to remote cores (without intervening interruptions, such as a DSB) are
7981                                                                  coalesced into a single context-based TLBI. Converted and original ones do not
7982                                                                  coalesce.
7983 
7984                                                                  1 = The above-mentioned coalescing is suppressed and converted context-based
7985                                                                  remote TLBIs still go out as such. */
7986         uint64_t tlbiicflush           : 1;  /**< [ 53: 53](R/W) Some local TLBI instructions cause ICache flush.
7987                                                                  0 = Icache flush operation do not happen on the TLBI instructions listed below.
7988                                                                  1 = Icache is flushed on the TLBI instructions listed below:
7989                                                                    * TLBI ALLE2{IS}.
7990                                                                    * TLBI ALLE3{IS}.
7991                                                                    * TLBI VAE1{IS}.
7992                                                                    * TLBI VALE1{IS}.
7993                                                                    * TLBI VAAE1{IS}.
7994                                                                    * TLBI VAALE1{IS}.
7995                                                                    * TLBI VAE2{IS}.
7996                                                                    * TLBI VALE2{IS}.
7997                                                                    * TLBI VAE3{IS}.
7998                                                                    * TLBI VALE3{IS}.
7999                                                                    * TLBI IPAS2E1{IS}.
8000                                                                    * TLBI IPAS2LE1{IS}. */
8001         uint64_t gsyncto               : 5;  /**< [ 52: 48](R/W) GlobalSync timeout.
8002                                                                  timeout = 2^[GSYNCTO].
8003                                                                  0x0 = disable timeout. */
8004         uint64_t utlbfillbypdis        : 1;  /**< [ 47: 47](R/W) Disable uTLB fill bypass.
8005                                                                  0 = On a stage1-only translation, the uTLB is written along with the MTLB.
8006                                                                  1 = On a stage1-only translation, the uTLB is not written along with the MTLB causing a
8007                                                                  uTLB miss replay to complete the uTLB fill. */
8008         uint64_t tlbiall               : 1;  /**< [ 46: 46](R/W) Treat all TLBIs like TLBI ALL for a specific exception level. */
8009         uint64_t wbfdsbflushall        : 1;  /**< [ 45: 45](R/W) Any DSB instruction flushes the write buffer. */
8010         uint64_t wbfdmbflushnext       : 1;  /**< [ 44: 44](R/W) DMB instruction to !NSH flushes next ST to !NSH.  uTLB is not flushed with this value is
8011                                                                  changed. */
8012         uint64_t stexl2cforce          : 1;  /**< [ 43: 43](R/W) Send all store-exclusive instructions to L2 cache.  uTLB is not flushed with this value is
8013                                                                  changed. */
8014         uint64_t ioglobalforce         : 1;  /**< [ 42: 42](R/W) Reserved.
8015                                                                  Internal:
8016                                                                  Force global order for IO references. */
8017         uint64_t wcumissforce          : 1;  /**< [ 41: 41](R/W) Force all walker cache lookups to miss.  uTLB is not flushed with this value is changed. */
8018         uint64_t replayprefdis         : 1;  /**< [ 40: 40](R/W) Replay PREF disable. uTLB miss PREF instruction behavior (see chapter body).
8019                                                                  0 = PREF instructions do attempt a replay for MTLB to uTLB refill.
8020                                                                  1 = PREF instructions do not attempt a replay for MTLB to uTLB refill.
8021 
8022                                                                  uTLB is not flushed with this value is changed. */
8023         uint64_t zval2cdis             : 1;  /**< [ 39: 39](R/W) ZVA bypass L2C.
8024                                                                  0 = DC_ZVA instructions to L2C are STFIL1 (full block store operation allocating in
8025                                                                  requester L2, fill 0s, self-invalidate L1 cache).
8026                                                                  1 = DC_ZVA instructions to L2C are STTIL1 (full block store operation through to DRAM,
8027                                                                  bypass home and requester L2, fill 0s, self-invalidate L1 cache). */
8028         uint64_t ldil2cdis             : 1;  /**< [ 38: 38](R/W) LDI instruction L2C usage.
8029                                                                  0 = LDI instructions to L2C are LDI (don't allocate in L1, allocates L2 at requester).
8030                                                                  1 = LDI instructions to L2C are LDT (don't allocate in L2 or L1 at home or requester). */
8031         uint64_t dcva47                : 1;  /**< [ 37: 37](R/W) If MMU translations are disabled,
8032                                                                  apply memory attributes to physical addresses where bit\<47\>
8033                                                                  is zero and device attributes to physical address bit\<47\> is
8034                                                                  one. */
8035         uint64_t stprefdis             : 1;  /**< [ 36: 36](R/W) ST PREF instructions disable. */
8036         uint64_t ldprefdis             : 1;  /**< [ 35: 35](R/W) LD PREF instructions disable. */
8037         uint64_t wfildexdis            : 1;  /**< [ 34: 34](R/W) WFE release behavior for LD-exclusive.
8038                                                                  0 = L2C invalidates to global monitor cause SEV to local core.
8039                                                                  1 = L2C invalidates have no effect on global monitor (i.e. lock_register).
8040 
8041                                                                  This field should never be set to 1; setting to 1 does not
8042                                                                  conform to the ARMv8 specification. */
8043         uint64_t wfito                 : 3;  /**< [ 33: 31](R/W) Wait-for-interrupt timeout; timeout=2^(8+[WFITO]). */
8044         uint64_t rbfshortto            : 5;  /**< [ 30: 26](R/W) Read buffer short timeout; timeout = 2^[RBFSHORTTO].
8045                                                                  Must be \>=0x6. The L2C directs the core to use either RBFSHORTTO or RBFTO. The short
8046                                                                  timeout is used when an CCPI link goes down to expedite error indication. */
8047         uint64_t rbfto                 : 5;  /**< [ 25: 21](R/W) Read buffer timeout; timeout = 2^[RBFTO]. Must be \>= 0x6. */
8048         uint64_t wbfallbarrier         : 1;  /**< [ 20: 20](R/W) Write-buffer apply barrier to all ST instructions. */
8049         uint64_t wbfnomerge            : 1;  /**< [ 19: 19](R/W) Write-buffer merge disable. */
8050         uint64_t wbftonshena           : 1;  /**< [ 18: 18](R/W) Write-buffer timeout for NSH entries enable.
8051                                                                  0 = Write-buffer time out for NSH entries = 218 cycles.
8052                                                                  1 = Write-buffer time out for NSH entries = 2^[WBFTO] (see [WBFTO]). */
8053         uint64_t wbftomrgclrena        : 1;  /**< [ 17: 17](R/W) Write-buffer timeout clear-on-merge enable. */
8054         uint64_t wbfto                 : 5;  /**< [ 16: 12](R/W) Write-buffer timeout for non-NSH entries; timeout = 2^WBFTO. */
8055         uint64_t wbfthresh             : 5;  /**< [ 11:  7](R/W) Write-buffer threshold. The write-buffer starts flushing entries to the L2 cache once the
8056                                                                  number of valid write-buffer entries reaches this threshold value. */
8057         uint64_t utlbentriesm1         : 5;  /**< [  6:  2](R/W) Number of uTLB entries - 1.  uTLB is flushed when this value is changed. */
8058         uint64_t cclkforce             : 1;  /**< [  1:  1](R/W) Force CSR clock enable. When set, force CSR conditional clocking. */
8059         uint64_t mclkforce             : 1;  /**< [  0:  0](R/W) Force memory clock enable. When set, force memory conditional clocking. */
8060 #else /* Word 0 - Little Endian */
8061         uint64_t mclkforce             : 1;  /**< [  0:  0](R/W) Force memory clock enable. When set, force memory conditional clocking. */
8062         uint64_t cclkforce             : 1;  /**< [  1:  1](R/W) Force CSR clock enable. When set, force CSR conditional clocking. */
8063         uint64_t utlbentriesm1         : 5;  /**< [  6:  2](R/W) Number of uTLB entries - 1.  uTLB is flushed when this value is changed. */
8064         uint64_t wbfthresh             : 5;  /**< [ 11:  7](R/W) Write-buffer threshold. The write-buffer starts flushing entries to the L2 cache once the
8065                                                                  number of valid write-buffer entries reaches this threshold value. */
8066         uint64_t wbfto                 : 5;  /**< [ 16: 12](R/W) Write-buffer timeout for non-NSH entries; timeout = 2^WBFTO. */
8067         uint64_t wbftomrgclrena        : 1;  /**< [ 17: 17](R/W) Write-buffer timeout clear-on-merge enable. */
8068         uint64_t wbftonshena           : 1;  /**< [ 18: 18](R/W) Write-buffer timeout for NSH entries enable.
8069                                                                  0 = Write-buffer time out for NSH entries = 218 cycles.
8070                                                                  1 = Write-buffer time out for NSH entries = 2^[WBFTO] (see [WBFTO]). */
8071         uint64_t wbfnomerge            : 1;  /**< [ 19: 19](R/W) Write-buffer merge disable. */
8072         uint64_t wbfallbarrier         : 1;  /**< [ 20: 20](R/W) Write-buffer apply barrier to all ST instructions. */
8073         uint64_t rbfto                 : 5;  /**< [ 25: 21](R/W) Read buffer timeout; timeout = 2^[RBFTO]. Must be \>= 0x6. */
8074         uint64_t rbfshortto            : 5;  /**< [ 30: 26](R/W) Read buffer short timeout; timeout = 2^[RBFSHORTTO].
8075                                                                  Must be \>=0x6. The L2C directs the core to use either RBFSHORTTO or RBFTO. The short
8076                                                                  timeout is used when an CCPI link goes down to expedite error indication. */
8077         uint64_t wfito                 : 3;  /**< [ 33: 31](R/W) Wait-for-interrupt timeout; timeout=2^(8+[WFITO]). */
8078         uint64_t wfildexdis            : 1;  /**< [ 34: 34](R/W) WFE release behavior for LD-exclusive.
8079                                                                  0 = L2C invalidates to global monitor cause SEV to local core.
8080                                                                  1 = L2C invalidates have no effect on global monitor (i.e. lock_register).
8081 
8082                                                                  This field should never be set to 1; setting to 1 does not
8083                                                                  conform to the ARMv8 specification. */
8084         uint64_t ldprefdis             : 1;  /**< [ 35: 35](R/W) LD PREF instructions disable. */
8085         uint64_t stprefdis             : 1;  /**< [ 36: 36](R/W) ST PREF instructions disable. */
8086         uint64_t dcva47                : 1;  /**< [ 37: 37](R/W) If MMU translations are disabled,
8087                                                                  apply memory attributes to physical addresses where bit\<47\>
8088                                                                  is zero and device attributes to physical address bit\<47\> is
8089                                                                  one. */
8090         uint64_t ldil2cdis             : 1;  /**< [ 38: 38](R/W) LDI instruction L2C usage.
8091                                                                  0 = LDI instructions to L2C are LDI (don't allocate in L1, allocates L2 at requester).
8092                                                                  1 = LDI instructions to L2C are LDT (don't allocate in L2 or L1 at home or requester). */
8093         uint64_t zval2cdis             : 1;  /**< [ 39: 39](R/W) ZVA bypass L2C.
8094                                                                  0 = DC_ZVA instructions to L2C are STFIL1 (full block store operation allocating in
8095                                                                  requester L2, fill 0s, self-invalidate L1 cache).
8096                                                                  1 = DC_ZVA instructions to L2C are STTIL1 (full block store operation through to DRAM,
8097                                                                  bypass home and requester L2, fill 0s, self-invalidate L1 cache). */
8098         uint64_t replayprefdis         : 1;  /**< [ 40: 40](R/W) Replay PREF disable. uTLB miss PREF instruction behavior (see chapter body).
8099                                                                  0 = PREF instructions do attempt a replay for MTLB to uTLB refill.
8100                                                                  1 = PREF instructions do not attempt a replay for MTLB to uTLB refill.
8101 
8102                                                                  uTLB is not flushed with this value is changed. */
8103         uint64_t wcumissforce          : 1;  /**< [ 41: 41](R/W) Force all walker cache lookups to miss.  uTLB is not flushed with this value is changed. */
8104         uint64_t ioglobalforce         : 1;  /**< [ 42: 42](R/W) Reserved.
8105                                                                  Internal:
8106                                                                  Force global order for IO references. */
8107         uint64_t stexl2cforce          : 1;  /**< [ 43: 43](R/W) Send all store-exclusive instructions to L2 cache.  uTLB is not flushed with this value is
8108                                                                  changed. */
8109         uint64_t wbfdmbflushnext       : 1;  /**< [ 44: 44](R/W) DMB instruction to !NSH flushes next ST to !NSH.  uTLB is not flushed with this value is
8110                                                                  changed. */
8111         uint64_t wbfdsbflushall        : 1;  /**< [ 45: 45](R/W) Any DSB instruction flushes the write buffer. */
8112         uint64_t tlbiall               : 1;  /**< [ 46: 46](R/W) Treat all TLBIs like TLBI ALL for a specific exception level. */
8113         uint64_t utlbfillbypdis        : 1;  /**< [ 47: 47](R/W) Disable uTLB fill bypass.
8114                                                                  0 = On a stage1-only translation, the uTLB is written along with the MTLB.
8115                                                                  1 = On a stage1-only translation, the uTLB is not written along with the MTLB causing a
8116                                                                  uTLB miss replay to complete the uTLB fill. */
8117         uint64_t gsyncto               : 5;  /**< [ 52: 48](R/W) GlobalSync timeout.
8118                                                                  timeout = 2^[GSYNCTO].
8119                                                                  0x0 = disable timeout. */
8120         uint64_t tlbiicflush           : 1;  /**< [ 53: 53](R/W) Some local TLBI instructions cause ICache flush.
8121                                                                  0 = Icache flush operation do not happen on the TLBI instructions listed below.
8122                                                                  1 = Icache is flushed on the TLBI instructions listed below:
8123                                                                    * TLBI ALLE2{IS}.
8124                                                                    * TLBI ALLE3{IS}.
8125                                                                    * TLBI VAE1{IS}.
8126                                                                    * TLBI VALE1{IS}.
8127                                                                    * TLBI VAAE1{IS}.
8128                                                                    * TLBI VAALE1{IS}.
8129                                                                    * TLBI VAE2{IS}.
8130                                                                    * TLBI VALE2{IS}.
8131                                                                    * TLBI VAE3{IS}.
8132                                                                    * TLBI VALE3{IS}.
8133                                                                    * TLBI IPAS2E1{IS}.
8134                                                                    * TLBI IPAS2LE1{IS}. */
8135         uint64_t tlbinopdis            : 1;  /**< [ 54: 54](R/W) Disable broadcast TLBI optimization.
8136 
8137                                                                  Address-based broadcast TLBI instructions that go to remote cores are converted
8138                                                                  from address-based TLBI instructions to context-based TLBI instructions. The
8139                                                                  actions on the local core generating the TLBI instruction are still precise.
8140 
8141                                                                  0 = The converted context-based TLBI instructions or original context-based
8142                                                                  TLBIs to remote cores (without intervening interruptions, such as a DSB) are
8143                                                                  coalesced into a single context-based TLBI. Converted and original ones do not
8144                                                                  coalesce.
8145 
8146                                                                  1 = The above-mentioned coalescing is suppressed and converted context-based
8147                                                                  remote TLBIs still go out as such. */
8148         uint64_t dmbstallforce         : 1;  /**< [ 55: 55](R/W) Force DMB to wait for flushed write-buffer entries to be ACKed.
8149                                                                  0 = DMB instructions mark prior relevant write-buffer entries for flush, but do not wait
8150                                                                  for the ACKs to return.
8151                                                                  1 = DMB instructions mark prior relevant write-buffer entries for flush and wait for all
8152                                                                  the ACKs to return. */
8153         uint64_t stlstallforce         : 1;  /**< [ 56: 56](R/W) Force ST_release to wait for flushed write-buffer entries to be ACKed.
8154                                                                  0 = Store-release instructions mark prior relevant write-buffer entries for flush but do
8155                                                                  not wait for the ACKs to return.
8156                                                                  1 = Store-release instructions mark prior relevant write-buffer entries for flush and wait
8157                                                                  for all the ACKs to return. */
8158         uint64_t wfeldex1dis           : 1;  /**< [ 57: 57](R/W) WFE release behavior for LD-exclusive.
8159                                                                  0 = A global monitor transition from exclusive to open (lock flag transition
8160                                                                  from 1 to 0) causes SEV to local core.
8161                                                                  1 = A global monitor transition from exclusive to open (lock flag transition
8162                                                                  from 1 to 0) does not cause SEV to local core. */
8163         uint64_t stexfailcnt           : 3;  /**< [ 60: 58](RO) ST exclusive fail count. */
8164         uint64_t node                  : 2;  /**< [ 62: 61](RO) Local node ID. */
8165         uint64_t reserved_63           : 1;
8166 #endif /* Word 0 - End */
8167     } cn81xx;
8168     /* struct bdk_ap_cvmmemctl0_el1_cn81xx cn83xx; */
8169     /* struct bdk_ap_cvmmemctl0_el1_s cn88xxp2; */
8170 };
8171 typedef union bdk_ap_cvmmemctl0_el1 bdk_ap_cvmmemctl0_el1_t;
8172 
8173 #define BDK_AP_CVMMEMCTL0_EL1 BDK_AP_CVMMEMCTL0_EL1_FUNC()
8174 static inline uint64_t BDK_AP_CVMMEMCTL0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVMMEMCTL0_EL1_FUNC(void)8175 static inline uint64_t BDK_AP_CVMMEMCTL0_EL1_FUNC(void)
8176 {
8177     return 0x3000b000400ll;
8178 }
8179 
8180 #define typedef_BDK_AP_CVMMEMCTL0_EL1 bdk_ap_cvmmemctl0_el1_t
8181 #define bustype_BDK_AP_CVMMEMCTL0_EL1 BDK_CSR_TYPE_SYSREG
8182 #define basename_BDK_AP_CVMMEMCTL0_EL1 "AP_CVMMEMCTL0_EL1"
8183 #define busnum_BDK_AP_CVMMEMCTL0_EL1 0
8184 #define arguments_BDK_AP_CVMMEMCTL0_EL1 -1,-1,-1,-1
8185 
8186 /**
8187  * Register (SYSREG) ap_cvmmemctl1_el1
8188  *
8189  * AP Cavium Memory Control 1 Register
8190  * This register controls additional memory-unit features.
8191  * Internal:
8192  * Back-end, non-debug.
8193  */
8194 union bdk_ap_cvmmemctl1_el1
8195 {
8196     uint64_t u;
8197     struct bdk_ap_cvmmemctl1_el1_s
8198     {
8199 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8200         uint64_t rsvd_57_63            : 7;  /**< [ 63: 57](R/W) Reserved. */
8201         uint64_t ldictxchkena          : 1;  /**< [ 56: 56](R/W) LDI context consistency check enable. For diagnostic use only. */
8202         uint64_t rbfevictbyp3dis       : 1;  /**< [ 55: 55](R/W) MAF RBUF evict datapath 3-cycle bypass disable. For diagnostic use only. */
8203         uint64_t rbfevictbyp2dis       : 1;  /**< [ 54: 54](R/W) MAF RBUF evict datapath 2-cycle bypass disable. For diagnostic use only. */
8204         uint64_t xmcpriwbfdis          : 1;  /**< [ 53: 53](R/W) XMC priority disable for predicted unlock WBF eviction. For diagnostic use only. */
8205         uint64_t xmcpristdis           : 1;  /**< [ 52: 52](R/W) XMC priority disable for predicted unlock ST. For diagnostic use only. */
8206         uint64_t xmcpriswpdis          : 1;  /**< [ 51: 51](R/W) XMC priority disable for predicted unlock SWP. For diagnostic use only. */
8207         uint64_t xmcpricasdis          : 1;  /**< [ 50: 50](R/W) XMC priority disable for predicted unlock CAS. For diagnostic use only. */
8208         uint64_t iostmergedis          : 1;  /**< [ 49: 49](R/W) IO ST merging disable. */
8209         uint64_t ioldmergedis          : 1;  /**< [ 48: 48](R/W) IO LD merging disable. */
8210         uint64_t gclkforce             : 1;  /**< [ 47: 47](R/W) Force gated clocks to be on. For diagnostic use only. */
8211         uint64_t ldil3prefdis          : 1;  /**< [ 46: 46](R/W) LDIL3 PREF instructions disable. */
8212         uint64_t ldil2prefdis          : 1;  /**< [ 45: 45](R/W) LDIL2 PREF instructions disable. */
8213         uint64_t spare44               : 1;  /**< [ 44: 44](R/W) Reserved; spare. */
8214         uint64_t evatt_limited_size    : 1;  /**< [ 43: 43](R/W) 0 = do not limit ASIDMAP/VMIDMAP size
8215                                                                  1 = ASIDMAP has 7 entries, VMIDMAP has 7 entries */
8216         uint64_t evatt_periodic_flush  : 1;  /**< [ 42: 42](R/W) 0 = EVATT is not periodically flushed
8217                                                                  1 = EVATT is flushed every 2^14 cycles */
8218         uint64_t cvap_dis              : 1;  /**< [ 41: 41](R/W) If set, convert DC_CVAP into DC_CVAC.  For diagnostic use only. */
8219         uint64_t tlbinoadr             : 1;  /**< [ 40: 40](R/W) If set, convert broadcast TLBI address-based opcodes to context-based opcode. For
8220                                                                  diagnostic use only. */
8221         uint64_t utlbentriesm1_5       : 1;  /**< [ 39: 39](R/W) Bit\<5\> of [UTLBENTRIESM1], the number of uTLB entries minus one. The uTLB is flushed when this
8222                                                                  value is changed. */
8223         uint64_t tlbiremoteicflush     : 1;  /**< [ 38: 38](R/W) Force ICache flush when any remote TLBI is received.
8224                                                                  0 = Do nothing.
8225                                                                  1 = Flush the ICache. */
8226         uint64_t tlbilocalicflush      : 1;  /**< [ 37: 37](R/W) Force ICache flush when any local TLBI is issued.
8227                                                                  0 = Do nothing.
8228                                                                  1 = Flush the ICache. */
8229         uint64_t dprefbpmode           : 1;  /**< [ 36: 36](R/W) Data-stream hardware prefetcher backpressure mode select.
8230                                                                  0 = Single counter mode (combined hit and miss latency counter).
8231                                                                  1 = Dual counter mode (separate hit and miss latency counters). */
8232         uint64_t dprefbpctl            : 4;  /**< [ 35: 32](R/W) Data-stream hardware prefetcher backpressure control mask for dual counter mode.
8233                                                                  Internal:
8234                                                                  Backpressure is applied if:
8235                                                                  \<pre\>
8236                                                                    (   ([DPREFBPCTL]\<0\> && !hit_ctr_bp && !miss_ctr_bp)
8237                                                                     || ([DPREFBPCTL]\<1\> && !hit_ctr_bp &&  miss_ctr_bp)
8238                                                                     || ([DPREFBPCTL]\<2\> &&  hit_ctr_bp && !miss_ctr_bp)
8239                                                                     || ([DPREFBPCTL]\<3\> &&  hit_ctr_bp &&  miss_ctr_bp))
8240                                                                  \</pre\>
8241 
8242                                                                  Where hit_ctr_bp is the MSB of the 4-bit hit counter being set, and miss_ctr_bp
8243                                                                  is the MSB of the 4-bit miss counter being set. */
8244         uint64_t dprefbphitthresh      : 12; /**< [ 31: 20](R/W) Data-stream hardware prefetcher backpressure threshold for L2C hit latency. */
8245         uint64_t dprefbpmissthresh     : 12; /**< [ 19:  8](R/W) Data-stream hardware prefetcher backpressure threshold for L2C miss latency. */
8246         uint64_t spare                 : 1;  /**< [  7:  7](R/W) Reserved; spare. */
8247         uint64_t switchtagena          : 1;  /**< [  6:  6](R/W) Reserved.
8248                                                                  Internal:
8249                                                                  83xx: Enable SSO switch-tag. */
8250         uint64_t node1trapena          : 1;  /**< [  5:  5](R/W) Reserved.
8251                                                                  Internal:
8252                                                                  83xx: Trap any access to nonzero node id. */
8253         uint64_t ioatomicena           : 1;  /**< [  4:  4](R/W) Reserved.
8254                                                                  Internal:
8255                                                                  Enable I/O SSO and PKO address region. */
8256         uint64_t lmtstena              : 1;  /**< [  3:  3](R/W) Reserved.
8257                                                                  Internal:
8258                                                                  83xx: Enable/disable LMTST(a). */
8259         uint64_t lodignoresh           : 1;  /**< [  2:  2](R/W) LocalOrderDomain DMB/DSB_NSH{ST} ignores shareability (applies to both nsh and ish pages). */
8260         uint64_t lodishena             : 1;  /**< [  1:  1](R/W) LocalOrderDomain DMB/DSB_ISH{ST} enable. */
8261         uint64_t lodnshena             : 1;  /**< [  0:  0](R/W) LocalOrderDomain DMB/DSB_NSH{ST} enable. */
8262 #else /* Word 0 - Little Endian */
8263         uint64_t lodnshena             : 1;  /**< [  0:  0](R/W) LocalOrderDomain DMB/DSB_NSH{ST} enable. */
8264         uint64_t lodishena             : 1;  /**< [  1:  1](R/W) LocalOrderDomain DMB/DSB_ISH{ST} enable. */
8265         uint64_t lodignoresh           : 1;  /**< [  2:  2](R/W) LocalOrderDomain DMB/DSB_NSH{ST} ignores shareability (applies to both nsh and ish pages). */
8266         uint64_t lmtstena              : 1;  /**< [  3:  3](R/W) Reserved.
8267                                                                  Internal:
8268                                                                  83xx: Enable/disable LMTST(a). */
8269         uint64_t ioatomicena           : 1;  /**< [  4:  4](R/W) Reserved.
8270                                                                  Internal:
8271                                                                  Enable I/O SSO and PKO address region. */
8272         uint64_t node1trapena          : 1;  /**< [  5:  5](R/W) Reserved.
8273                                                                  Internal:
8274                                                                  83xx: Trap any access to nonzero node id. */
8275         uint64_t switchtagena          : 1;  /**< [  6:  6](R/W) Reserved.
8276                                                                  Internal:
8277                                                                  83xx: Enable SSO switch-tag. */
8278         uint64_t spare                 : 1;  /**< [  7:  7](R/W) Reserved; spare. */
8279         uint64_t dprefbpmissthresh     : 12; /**< [ 19:  8](R/W) Data-stream hardware prefetcher backpressure threshold for L2C miss latency. */
8280         uint64_t dprefbphitthresh      : 12; /**< [ 31: 20](R/W) Data-stream hardware prefetcher backpressure threshold for L2C hit latency. */
8281         uint64_t dprefbpctl            : 4;  /**< [ 35: 32](R/W) Data-stream hardware prefetcher backpressure control mask for dual counter mode.
8282                                                                  Internal:
8283                                                                  Backpressure is applied if:
8284                                                                  \<pre\>
8285                                                                    (   ([DPREFBPCTL]\<0\> && !hit_ctr_bp && !miss_ctr_bp)
8286                                                                     || ([DPREFBPCTL]\<1\> && !hit_ctr_bp &&  miss_ctr_bp)
8287                                                                     || ([DPREFBPCTL]\<2\> &&  hit_ctr_bp && !miss_ctr_bp)
8288                                                                     || ([DPREFBPCTL]\<3\> &&  hit_ctr_bp &&  miss_ctr_bp))
8289                                                                  \</pre\>
8290 
8291                                                                  Where hit_ctr_bp is the MSB of the 4-bit hit counter being set, and miss_ctr_bp
8292                                                                  is the MSB of the 4-bit miss counter being set. */
8293         uint64_t dprefbpmode           : 1;  /**< [ 36: 36](R/W) Data-stream hardware prefetcher backpressure mode select.
8294                                                                  0 = Single counter mode (combined hit and miss latency counter).
8295                                                                  1 = Dual counter mode (separate hit and miss latency counters). */
8296         uint64_t tlbilocalicflush      : 1;  /**< [ 37: 37](R/W) Force ICache flush when any local TLBI is issued.
8297                                                                  0 = Do nothing.
8298                                                                  1 = Flush the ICache. */
8299         uint64_t tlbiremoteicflush     : 1;  /**< [ 38: 38](R/W) Force ICache flush when any remote TLBI is received.
8300                                                                  0 = Do nothing.
8301                                                                  1 = Flush the ICache. */
8302         uint64_t utlbentriesm1_5       : 1;  /**< [ 39: 39](R/W) Bit\<5\> of [UTLBENTRIESM1], the number of uTLB entries minus one. The uTLB is flushed when this
8303                                                                  value is changed. */
8304         uint64_t tlbinoadr             : 1;  /**< [ 40: 40](R/W) If set, convert broadcast TLBI address-based opcodes to context-based opcode. For
8305                                                                  diagnostic use only. */
8306         uint64_t cvap_dis              : 1;  /**< [ 41: 41](R/W) If set, convert DC_CVAP into DC_CVAC.  For diagnostic use only. */
8307         uint64_t evatt_periodic_flush  : 1;  /**< [ 42: 42](R/W) 0 = EVATT is not periodically flushed
8308                                                                  1 = EVATT is flushed every 2^14 cycles */
8309         uint64_t evatt_limited_size    : 1;  /**< [ 43: 43](R/W) 0 = do not limit ASIDMAP/VMIDMAP size
8310                                                                  1 = ASIDMAP has 7 entries, VMIDMAP has 7 entries */
8311         uint64_t spare44               : 1;  /**< [ 44: 44](R/W) Reserved; spare. */
8312         uint64_t ldil2prefdis          : 1;  /**< [ 45: 45](R/W) LDIL2 PREF instructions disable. */
8313         uint64_t ldil3prefdis          : 1;  /**< [ 46: 46](R/W) LDIL3 PREF instructions disable. */
8314         uint64_t gclkforce             : 1;  /**< [ 47: 47](R/W) Force gated clocks to be on. For diagnostic use only. */
8315         uint64_t ioldmergedis          : 1;  /**< [ 48: 48](R/W) IO LD merging disable. */
8316         uint64_t iostmergedis          : 1;  /**< [ 49: 49](R/W) IO ST merging disable. */
8317         uint64_t xmcpricasdis          : 1;  /**< [ 50: 50](R/W) XMC priority disable for predicted unlock CAS. For diagnostic use only. */
8318         uint64_t xmcpriswpdis          : 1;  /**< [ 51: 51](R/W) XMC priority disable for predicted unlock SWP. For diagnostic use only. */
8319         uint64_t xmcpristdis           : 1;  /**< [ 52: 52](R/W) XMC priority disable for predicted unlock ST. For diagnostic use only. */
8320         uint64_t xmcpriwbfdis          : 1;  /**< [ 53: 53](R/W) XMC priority disable for predicted unlock WBF eviction. For diagnostic use only. */
8321         uint64_t rbfevictbyp2dis       : 1;  /**< [ 54: 54](R/W) MAF RBUF evict datapath 2-cycle bypass disable. For diagnostic use only. */
8322         uint64_t rbfevictbyp3dis       : 1;  /**< [ 55: 55](R/W) MAF RBUF evict datapath 3-cycle bypass disable. For diagnostic use only. */
8323         uint64_t ldictxchkena          : 1;  /**< [ 56: 56](R/W) LDI context consistency check enable. For diagnostic use only. */
8324         uint64_t rsvd_57_63            : 7;  /**< [ 63: 57](R/W) Reserved. */
8325 #endif /* Word 0 - End */
8326     } s;
8327     struct bdk_ap_cvmmemctl1_el1_cn9
8328     {
8329 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8330         uint64_t rsvd_57_63            : 7;  /**< [ 63: 57](R/W) Reserved. */
8331         uint64_t ldictxchkena          : 1;  /**< [ 56: 56](R/W) LDI context consistency check enable. For diagnostic use only. */
8332         uint64_t rbfevictbyp3dis       : 1;  /**< [ 55: 55](R/W) MAF RBUF evict datapath 3-cycle bypass disable. For diagnostic use only. */
8333         uint64_t rbfevictbyp2dis       : 1;  /**< [ 54: 54](R/W) MAF RBUF evict datapath 2-cycle bypass disable. For diagnostic use only. */
8334         uint64_t xmcpriwbfdis          : 1;  /**< [ 53: 53](R/W) XMC priority disable for predicted unlock WBF eviction. For diagnostic use only. */
8335         uint64_t xmcpristdis           : 1;  /**< [ 52: 52](R/W) XMC priority disable for predicted unlock ST. For diagnostic use only. */
8336         uint64_t xmcpriswpdis          : 1;  /**< [ 51: 51](R/W) XMC priority disable for predicted unlock SWP. For diagnostic use only. */
8337         uint64_t xmcpricasdis          : 1;  /**< [ 50: 50](R/W) XMC priority disable for predicted unlock CAS. For diagnostic use only. */
8338         uint64_t iostmergedis          : 1;  /**< [ 49: 49](R/W) IO ST merging disable. */
8339         uint64_t ioldmergedis          : 1;  /**< [ 48: 48](R/W) IO LD merging disable. */
8340         uint64_t gclkforce             : 1;  /**< [ 47: 47](R/W) Force gated clocks to be on. For diagnostic use only. */
8341         uint64_t ldil3prefdis          : 1;  /**< [ 46: 46](R/W) LDIL3 PREF instructions disable. */
8342         uint64_t ldil2prefdis          : 1;  /**< [ 45: 45](R/W) LDIL2 PREF instructions disable. */
8343         uint64_t spare44               : 1;  /**< [ 44: 44](R/W) Reserved; spare. */
8344         uint64_t evatt_limited_size    : 1;  /**< [ 43: 43](R/W) 0 = do not limit ASIDMAP/VMIDMAP size
8345                                                                  1 = ASIDMAP has 7 entries, VMIDMAP has 7 entries */
8346         uint64_t evatt_periodic_flush  : 1;  /**< [ 42: 42](R/W) 0 = EVATT is not periodically flushed
8347                                                                  1 = EVATT is flushed every 2^14 cycles */
8348         uint64_t cvap_dis              : 1;  /**< [ 41: 41](R/W) If set, convert DC_CVAP into DC_CVAC.  For diagnostic use only. */
8349         uint64_t tlbinoadr             : 1;  /**< [ 40: 40](R/W) If set, convert broadcast TLBI address-based opcodes to context-based opcode. For
8350                                                                  diagnostic use only. */
8351         uint64_t utlbentriesm1_5       : 1;  /**< [ 39: 39](R/W) Bit\<5\> of [UTLBENTRIESM1], the number of uTLB entries minus one. The uTLB is flushed when this
8352                                                                  value is changed. */
8353         uint64_t tlbiremoteicflush     : 1;  /**< [ 38: 38](R/W) Force ICache flush when any remote TLBI is received.
8354                                                                  0 = Do nothing.
8355                                                                  1 = Flush the ICache. */
8356         uint64_t tlbilocalicflush      : 1;  /**< [ 37: 37](R/W) Force ICache flush when any local TLBI is issued.
8357                                                                  0 = Do nothing.
8358                                                                  1 = Flush the ICache. */
8359         uint64_t dprefbpmode           : 1;  /**< [ 36: 36](R/W) Data-stream hardware prefetcher backpressure mode select.
8360                                                                  0 = Single counter mode (combined hit and miss latency counter).
8361                                                                  1 = Dual counter mode (separate hit and miss latency counters). */
8362         uint64_t dprefbpctl            : 4;  /**< [ 35: 32](R/W) Data-stream hardware prefetcher backpressure control mask for dual counter mode.
8363                                                                  Internal:
8364                                                                  Backpressure is applied if:
8365                                                                  \<pre\>
8366                                                                    (   ([DPREFBPCTL]\<0\> && !hit_ctr_bp && !miss_ctr_bp)
8367                                                                     || ([DPREFBPCTL]\<1\> && !hit_ctr_bp &&  miss_ctr_bp)
8368                                                                     || ([DPREFBPCTL]\<2\> &&  hit_ctr_bp && !miss_ctr_bp)
8369                                                                     || ([DPREFBPCTL]\<3\> &&  hit_ctr_bp &&  miss_ctr_bp))
8370                                                                  \</pre\>
8371 
8372                                                                  Where hit_ctr_bp is the MSB of the 4-bit hit counter being set, and miss_ctr_bp
8373                                                                  is the MSB of the 4-bit miss counter being set. */
8374         uint64_t dprefbphitthresh      : 12; /**< [ 31: 20](R/W) Data-stream hardware prefetcher backpressure threshold for L2C hit latency. */
8375         uint64_t dprefbpmissthresh     : 12; /**< [ 19:  8](R/W) Data-stream hardware prefetcher backpressure threshold for L2C miss latency. */
8376         uint64_t spare                 : 1;  /**< [  7:  7](R/W) Reserved; spare. */
8377         uint64_t switchtagena          : 1;  /**< [  6:  6](R/W) Reserved.
8378                                                                  Internal:
8379                                                                  Enable SSO switch-tag. */
8380         uint64_t node1trapena          : 1;  /**< [  5:  5](R/W) Trap any access to nonzero node id. This should be clear on multi-socket
8381                                                                  systems, and set on single-socket systems. */
8382         uint64_t ioatomicena           : 1;  /**< [  4:  4](R/W) Enable SSO and PKO address region.
8383                                                                  0 = Accesses described below will trap.
8384                                                                  1 = Allow \> 64-bit memory instructions, multi-register memory instructions, and
8385                                                                  atomic instructions to SSO and PKO I/O address regions. This must be set if SSO
8386                                                                  or PKO are to be used.
8387 
8388                                                                  Other address regions (e.g. SLI) are not affected by this setting. */
8389         uint64_t lmtstena              : 1;  /**< [  3:  3](R/W) Enable LMTST. */
8390         uint64_t lodignoresh           : 1;  /**< [  2:  2](R/W) LocalOrderDomain DMB/DSB_NSH{ST} ignores shareability (applies to both nsh and ish pages). */
8391         uint64_t lodishena             : 1;  /**< [  1:  1](R/W) LocalOrderDomain DMB/DSB_ISH{ST} enable. */
8392         uint64_t lodnshena             : 1;  /**< [  0:  0](R/W) LocalOrderDomain DMB/DSB_NSH{ST} enable. */
8393 #else /* Word 0 - Little Endian */
8394         uint64_t lodnshena             : 1;  /**< [  0:  0](R/W) LocalOrderDomain DMB/DSB_NSH{ST} enable. */
8395         uint64_t lodishena             : 1;  /**< [  1:  1](R/W) LocalOrderDomain DMB/DSB_ISH{ST} enable. */
8396         uint64_t lodignoresh           : 1;  /**< [  2:  2](R/W) LocalOrderDomain DMB/DSB_NSH{ST} ignores shareability (applies to both nsh and ish pages). */
8397         uint64_t lmtstena              : 1;  /**< [  3:  3](R/W) Enable LMTST. */
8398         uint64_t ioatomicena           : 1;  /**< [  4:  4](R/W) Enable SSO and PKO address region.
8399                                                                  0 = Accesses described below will trap.
8400                                                                  1 = Allow \> 64-bit memory instructions, multi-register memory instructions, and
8401                                                                  atomic instructions to SSO and PKO I/O address regions. This must be set if SSO
8402                                                                  or PKO are to be used.
8403 
8404                                                                  Other address regions (e.g. SLI) are not affected by this setting. */
8405         uint64_t node1trapena          : 1;  /**< [  5:  5](R/W) Trap any access to nonzero node id. This should be clear on multi-socket
8406                                                                  systems, and set on single-socket systems. */
8407         uint64_t switchtagena          : 1;  /**< [  6:  6](R/W) Reserved.
8408                                                                  Internal:
8409                                                                  Enable SSO switch-tag. */
8410         uint64_t spare                 : 1;  /**< [  7:  7](R/W) Reserved; spare. */
8411         uint64_t dprefbpmissthresh     : 12; /**< [ 19:  8](R/W) Data-stream hardware prefetcher backpressure threshold for L2C miss latency. */
8412         uint64_t dprefbphitthresh      : 12; /**< [ 31: 20](R/W) Data-stream hardware prefetcher backpressure threshold for L2C hit latency. */
8413         uint64_t dprefbpctl            : 4;  /**< [ 35: 32](R/W) Data-stream hardware prefetcher backpressure control mask for dual counter mode.
8414                                                                  Internal:
8415                                                                  Backpressure is applied if:
8416                                                                  \<pre\>
8417                                                                    (   ([DPREFBPCTL]\<0\> && !hit_ctr_bp && !miss_ctr_bp)
8418                                                                     || ([DPREFBPCTL]\<1\> && !hit_ctr_bp &&  miss_ctr_bp)
8419                                                                     || ([DPREFBPCTL]\<2\> &&  hit_ctr_bp && !miss_ctr_bp)
8420                                                                     || ([DPREFBPCTL]\<3\> &&  hit_ctr_bp &&  miss_ctr_bp))
8421                                                                  \</pre\>
8422 
8423                                                                  Where hit_ctr_bp is the MSB of the 4-bit hit counter being set, and miss_ctr_bp
8424                                                                  is the MSB of the 4-bit miss counter being set. */
8425         uint64_t dprefbpmode           : 1;  /**< [ 36: 36](R/W) Data-stream hardware prefetcher backpressure mode select.
8426                                                                  0 = Single counter mode (combined hit and miss latency counter).
8427                                                                  1 = Dual counter mode (separate hit and miss latency counters). */
8428         uint64_t tlbilocalicflush      : 1;  /**< [ 37: 37](R/W) Force ICache flush when any local TLBI is issued.
8429                                                                  0 = Do nothing.
8430                                                                  1 = Flush the ICache. */
8431         uint64_t tlbiremoteicflush     : 1;  /**< [ 38: 38](R/W) Force ICache flush when any remote TLBI is received.
8432                                                                  0 = Do nothing.
8433                                                                  1 = Flush the ICache. */
8434         uint64_t utlbentriesm1_5       : 1;  /**< [ 39: 39](R/W) Bit\<5\> of [UTLBENTRIESM1], the number of uTLB entries minus one. The uTLB is flushed when this
8435                                                                  value is changed. */
8436         uint64_t tlbinoadr             : 1;  /**< [ 40: 40](R/W) If set, convert broadcast TLBI address-based opcodes to context-based opcode. For
8437                                                                  diagnostic use only. */
8438         uint64_t cvap_dis              : 1;  /**< [ 41: 41](R/W) If set, convert DC_CVAP into DC_CVAC.  For diagnostic use only. */
8439         uint64_t evatt_periodic_flush  : 1;  /**< [ 42: 42](R/W) 0 = EVATT is not periodically flushed
8440                                                                  1 = EVATT is flushed every 2^14 cycles */
8441         uint64_t evatt_limited_size    : 1;  /**< [ 43: 43](R/W) 0 = do not limit ASIDMAP/VMIDMAP size
8442                                                                  1 = ASIDMAP has 7 entries, VMIDMAP has 7 entries */
8443         uint64_t spare44               : 1;  /**< [ 44: 44](R/W) Reserved; spare. */
8444         uint64_t ldil2prefdis          : 1;  /**< [ 45: 45](R/W) LDIL2 PREF instructions disable. */
8445         uint64_t ldil3prefdis          : 1;  /**< [ 46: 46](R/W) LDIL3 PREF instructions disable. */
8446         uint64_t gclkforce             : 1;  /**< [ 47: 47](R/W) Force gated clocks to be on. For diagnostic use only. */
8447         uint64_t ioldmergedis          : 1;  /**< [ 48: 48](R/W) IO LD merging disable. */
8448         uint64_t iostmergedis          : 1;  /**< [ 49: 49](R/W) IO ST merging disable. */
8449         uint64_t xmcpricasdis          : 1;  /**< [ 50: 50](R/W) XMC priority disable for predicted unlock CAS. For diagnostic use only. */
8450         uint64_t xmcpriswpdis          : 1;  /**< [ 51: 51](R/W) XMC priority disable for predicted unlock SWP. For diagnostic use only. */
8451         uint64_t xmcpristdis           : 1;  /**< [ 52: 52](R/W) XMC priority disable for predicted unlock ST. For diagnostic use only. */
8452         uint64_t xmcpriwbfdis          : 1;  /**< [ 53: 53](R/W) XMC priority disable for predicted unlock WBF eviction. For diagnostic use only. */
8453         uint64_t rbfevictbyp2dis       : 1;  /**< [ 54: 54](R/W) MAF RBUF evict datapath 2-cycle bypass disable. For diagnostic use only. */
8454         uint64_t rbfevictbyp3dis       : 1;  /**< [ 55: 55](R/W) MAF RBUF evict datapath 3-cycle bypass disable. For diagnostic use only. */
8455         uint64_t ldictxchkena          : 1;  /**< [ 56: 56](R/W) LDI context consistency check enable. For diagnostic use only. */
8456         uint64_t rsvd_57_63            : 7;  /**< [ 63: 57](R/W) Reserved. */
8457 #endif /* Word 0 - End */
8458     } cn9;
8459     struct bdk_ap_cvmmemctl1_el1_cn81xx
8460     {
8461 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8462         uint64_t reserved_39_63        : 25;
8463         uint64_t tlbiremoteicflush     : 1;  /**< [ 38: 38](R/W) Force ICache flush when any remote TLBI is received.
8464                                                                  0 = Do nothing.
8465                                                                  1 = Flush the ICache. */
8466         uint64_t tlbilocalicflush      : 1;  /**< [ 37: 37](R/W) Force ICache flush when any local TLBI is issued.
8467                                                                  0 = Do nothing.
8468                                                                  1 = Flush the ICache. */
8469         uint64_t dprefbpmode           : 1;  /**< [ 36: 36](R/W) Data-stream hardware prefetcher backpressure mode select.
8470                                                                  0 = Single counter mode (combined hit and miss latency counter).
8471                                                                  1 = Dual counter mode (separate hit and miss latency counters). */
8472         uint64_t dprefbpctl            : 4;  /**< [ 35: 32](R/W) Data-stream hardware prefetcher backpressure control mask for dual counter mode.
8473                                                                  Internal:
8474                                                                  Backpressure is applied if:
8475                                                                  \<pre\>
8476                                                                    (   ([DPREFBPCTL]\<0\> && !hit_ctr_bp && !miss_ctr_bp)
8477                                                                     || ([DPREFBPCTL]\<1\> && !hit_ctr_bp &&  miss_ctr_bp)
8478                                                                     || ([DPREFBPCTL]\<2\> &&  hit_ctr_bp && !miss_ctr_bp)
8479                                                                     || ([DPREFBPCTL]\<3\> &&  hit_ctr_bp &&  miss_ctr_bp))
8480                                                                  \</pre\>
8481 
8482                                                                  Where hit_ctr_bp is the MSB of the 4-bit hit counter being set, and miss_ctr_bp
8483                                                                  is the MSB of the 4-bit miss counter being set. */
8484         uint64_t dprefbphitthresh      : 12; /**< [ 31: 20](R/W) Data-stream hardware prefetcher backpressure threshold for L2C hit latency. */
8485         uint64_t dprefbpmissthresh     : 12; /**< [ 19:  8](R/W) Data-stream hardware prefetcher backpressure threshold for L2C miss latency. */
8486         uint64_t spare                 : 1;  /**< [  7:  7](R/W) Reserved; spare. */
8487         uint64_t switchtagena          : 1;  /**< [  6:  6](R/W) Reserved.
8488                                                                  Internal:
8489                                                                  83xx: Enable SSO switch-tag. */
8490         uint64_t node1trapena          : 1;  /**< [  5:  5](R/W) Reserved.
8491                                                                  Internal:
8492                                                                  83xx: Trap any access to nonzero node id. */
8493         uint64_t ioatomicena           : 1;  /**< [  4:  4](R/W) Reserved.
8494                                                                  Internal:
8495                                                                  Enable I/O SSO and PKO address region. */
8496         uint64_t lmtstena              : 1;  /**< [  3:  3](R/W) Reserved.
8497                                                                  Internal:
8498                                                                  83xx: Enable/disable LMTST(a). */
8499         uint64_t lodignoresh           : 1;  /**< [  2:  2](R/W) LocalOrderDomain DMB/DSB_NSH{ST} ignores shareability (applies to both nsh and ish pages). */
8500         uint64_t lodishena             : 1;  /**< [  1:  1](R/W) LocalOrderDomain DMB/DSB_ISH{ST} enable. */
8501         uint64_t lodnshena             : 1;  /**< [  0:  0](R/W) LocalOrderDomain DMB/DSB_NSH{ST} enable. */
8502 #else /* Word 0 - Little Endian */
8503         uint64_t lodnshena             : 1;  /**< [  0:  0](R/W) LocalOrderDomain DMB/DSB_NSH{ST} enable. */
8504         uint64_t lodishena             : 1;  /**< [  1:  1](R/W) LocalOrderDomain DMB/DSB_ISH{ST} enable. */
8505         uint64_t lodignoresh           : 1;  /**< [  2:  2](R/W) LocalOrderDomain DMB/DSB_NSH{ST} ignores shareability (applies to both nsh and ish pages). */
8506         uint64_t lmtstena              : 1;  /**< [  3:  3](R/W) Reserved.
8507                                                                  Internal:
8508                                                                  83xx: Enable/disable LMTST(a). */
8509         uint64_t ioatomicena           : 1;  /**< [  4:  4](R/W) Reserved.
8510                                                                  Internal:
8511                                                                  Enable I/O SSO and PKO address region. */
8512         uint64_t node1trapena          : 1;  /**< [  5:  5](R/W) Reserved.
8513                                                                  Internal:
8514                                                                  83xx: Trap any access to nonzero node id. */
8515         uint64_t switchtagena          : 1;  /**< [  6:  6](R/W) Reserved.
8516                                                                  Internal:
8517                                                                  83xx: Enable SSO switch-tag. */
8518         uint64_t spare                 : 1;  /**< [  7:  7](R/W) Reserved; spare. */
8519         uint64_t dprefbpmissthresh     : 12; /**< [ 19:  8](R/W) Data-stream hardware prefetcher backpressure threshold for L2C miss latency. */
8520         uint64_t dprefbphitthresh      : 12; /**< [ 31: 20](R/W) Data-stream hardware prefetcher backpressure threshold for L2C hit latency. */
8521         uint64_t dprefbpctl            : 4;  /**< [ 35: 32](R/W) Data-stream hardware prefetcher backpressure control mask for dual counter mode.
8522                                                                  Internal:
8523                                                                  Backpressure is applied if:
8524                                                                  \<pre\>
8525                                                                    (   ([DPREFBPCTL]\<0\> && !hit_ctr_bp && !miss_ctr_bp)
8526                                                                     || ([DPREFBPCTL]\<1\> && !hit_ctr_bp &&  miss_ctr_bp)
8527                                                                     || ([DPREFBPCTL]\<2\> &&  hit_ctr_bp && !miss_ctr_bp)
8528                                                                     || ([DPREFBPCTL]\<3\> &&  hit_ctr_bp &&  miss_ctr_bp))
8529                                                                  \</pre\>
8530 
8531                                                                  Where hit_ctr_bp is the MSB of the 4-bit hit counter being set, and miss_ctr_bp
8532                                                                  is the MSB of the 4-bit miss counter being set. */
8533         uint64_t dprefbpmode           : 1;  /**< [ 36: 36](R/W) Data-stream hardware prefetcher backpressure mode select.
8534                                                                  0 = Single counter mode (combined hit and miss latency counter).
8535                                                                  1 = Dual counter mode (separate hit and miss latency counters). */
8536         uint64_t tlbilocalicflush      : 1;  /**< [ 37: 37](R/W) Force ICache flush when any local TLBI is issued.
8537                                                                  0 = Do nothing.
8538                                                                  1 = Flush the ICache. */
8539         uint64_t tlbiremoteicflush     : 1;  /**< [ 38: 38](R/W) Force ICache flush when any remote TLBI is received.
8540                                                                  0 = Do nothing.
8541                                                                  1 = Flush the ICache. */
8542         uint64_t reserved_39_63        : 25;
8543 #endif /* Word 0 - End */
8544     } cn81xx;
8545     struct bdk_ap_cvmmemctl1_el1_cn88xx
8546     {
8547 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8548         uint64_t reserved_37_63        : 27;
8549         uint64_t reserved_8_36         : 29;
8550         uint64_t reserved_7            : 1;
8551         uint64_t switchtagena          : 1;  /**< [  6:  6](R/W) Reserved.
8552                                                                  Internal:
8553                                                                  83xx: Enable SSO switch-tag. */
8554         uint64_t node1trapena          : 1;  /**< [  5:  5](R/W) Reserved.
8555                                                                  Internal:
8556                                                                  83xx: Trap any access to nonzero node id. */
8557         uint64_t ioatomicena           : 1;  /**< [  4:  4](R/W) Reserved.
8558                                                                  Internal:
8559                                                                  Enable I/O SSO and PKO address region. */
8560         uint64_t lmtstena              : 1;  /**< [  3:  3](R/W) Reserved.
8561                                                                  Internal:
8562                                                                  83xx: Enable/disable LMTST(a). */
8563         uint64_t lodignoresh           : 1;  /**< [  2:  2](R/W) LocalOrderDomain DMB/DSB_NSH{ST} ignores shareability (applies to both nsh and ish pages). */
8564         uint64_t lodishena             : 1;  /**< [  1:  1](R/W) LocalOrderDomain DMB/DSB_ISH{ST} enable. */
8565         uint64_t lodnshena             : 1;  /**< [  0:  0](R/W) LocalOrderDomain DMB/DSB_NSH{ST} enable. */
8566 #else /* Word 0 - Little Endian */
8567         uint64_t lodnshena             : 1;  /**< [  0:  0](R/W) LocalOrderDomain DMB/DSB_NSH{ST} enable. */
8568         uint64_t lodishena             : 1;  /**< [  1:  1](R/W) LocalOrderDomain DMB/DSB_ISH{ST} enable. */
8569         uint64_t lodignoresh           : 1;  /**< [  2:  2](R/W) LocalOrderDomain DMB/DSB_NSH{ST} ignores shareability (applies to both nsh and ish pages). */
8570         uint64_t lmtstena              : 1;  /**< [  3:  3](R/W) Reserved.
8571                                                                  Internal:
8572                                                                  83xx: Enable/disable LMTST(a). */
8573         uint64_t ioatomicena           : 1;  /**< [  4:  4](R/W) Reserved.
8574                                                                  Internal:
8575                                                                  Enable I/O SSO and PKO address region. */
8576         uint64_t node1trapena          : 1;  /**< [  5:  5](R/W) Reserved.
8577                                                                  Internal:
8578                                                                  83xx: Trap any access to nonzero node id. */
8579         uint64_t switchtagena          : 1;  /**< [  6:  6](R/W) Reserved.
8580                                                                  Internal:
8581                                                                  83xx: Enable SSO switch-tag. */
8582         uint64_t reserved_7            : 1;
8583         uint64_t reserved_8_36         : 29;
8584         uint64_t reserved_37_63        : 27;
8585 #endif /* Word 0 - End */
8586     } cn88xx;
8587     struct bdk_ap_cvmmemctl1_el1_cn83xx
8588     {
8589 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8590         uint64_t reserved_39_63        : 25;
8591         uint64_t tlbiremoteicflush     : 1;  /**< [ 38: 38](R/W) Force ICache flush when any remote TLBI is received.
8592                                                                  0 = Do nothing.
8593                                                                  1 = Flush the ICache. */
8594         uint64_t tlbilocalicflush      : 1;  /**< [ 37: 37](R/W) Force ICache flush when any local TLBI is issued.
8595                                                                  0 = Do nothing.
8596                                                                  1 = Flush the ICache. */
8597         uint64_t dprefbpmode           : 1;  /**< [ 36: 36](R/W) Data-stream hardware prefetcher backpressure mode select.
8598                                                                  0 = Single counter mode (combined hit and miss latency counter).
8599                                                                  1 = Dual counter mode (separate hit and miss latency counters). */
8600         uint64_t dprefbpctl            : 4;  /**< [ 35: 32](R/W) Data-stream hardware prefetcher backpressure control mask for dual counter mode.
8601                                                                  Internal:
8602                                                                  Backpressure is applied if:
8603                                                                  \<pre\>
8604                                                                    (   ([DPREFBPCTL]\<0\> && !hit_ctr_bp && !miss_ctr_bp)
8605                                                                     || ([DPREFBPCTL]\<1\> && !hit_ctr_bp &&  miss_ctr_bp)
8606                                                                     || ([DPREFBPCTL]\<2\> &&  hit_ctr_bp && !miss_ctr_bp)
8607                                                                     || ([DPREFBPCTL]\<3\> &&  hit_ctr_bp &&  miss_ctr_bp))
8608                                                                  \</pre\>
8609 
8610                                                                  Where hit_ctr_bp is the MSB of the 4-bit hit counter being set, and miss_ctr_bp
8611                                                                  is the MSB of the 4-bit miss counter being set. */
8612         uint64_t dprefbphitthresh      : 12; /**< [ 31: 20](R/W) Data-stream hardware prefetcher backpressure threshold for L2C hit latency. */
8613         uint64_t dprefbpmissthresh     : 12; /**< [ 19:  8](R/W) Data-stream hardware prefetcher backpressure threshold for L2C miss latency. */
8614         uint64_t spare                 : 1;  /**< [  7:  7](R/W) Reserved; spare. */
8615         uint64_t switchtagena          : 1;  /**< [  6:  6](R/W) Enable SSO switch-tag caching. The cache must be invalidated through e.g. use of
8616                                                                  SSO_WS_CFG[SSO_SAI_FLUSH] before clearing this bit. */
8617         uint64_t node1trapena          : 1;  /**< [  5:  5](R/W) Trap any access to nonzero node id. */
8618         uint64_t ioatomicena           : 1;  /**< [  4:  4](R/W) Enable SSO and PKO address region.
8619                                                                  0 = Accesses described below will trap.
8620                                                                  1 = Allow \> 64-bit memory instructions, multi-register memory instructions, and
8621                                                                  atomic instructions to SSO and PKO I/O address regions. This must be set if SSO
8622                                                                  or PKO are to be used.
8623 
8624                                                                  Other address regions (e.g. SLI) are not affected by this setting. */
8625         uint64_t lmtstena              : 1;  /**< [  3:  3](R/W) Enable LMTST. */
8626         uint64_t lodignoresh           : 1;  /**< [  2:  2](R/W) LocalOrderDomain DMB/DSB_NSH{ST} ignores shareability (applies to both nsh and ish pages). */
8627         uint64_t lodishena             : 1;  /**< [  1:  1](R/W) LocalOrderDomain DMB/DSB_ISH{ST} enable. */
8628         uint64_t lodnshena             : 1;  /**< [  0:  0](R/W) LocalOrderDomain DMB/DSB_NSH{ST} enable. */
8629 #else /* Word 0 - Little Endian */
8630         uint64_t lodnshena             : 1;  /**< [  0:  0](R/W) LocalOrderDomain DMB/DSB_NSH{ST} enable. */
8631         uint64_t lodishena             : 1;  /**< [  1:  1](R/W) LocalOrderDomain DMB/DSB_ISH{ST} enable. */
8632         uint64_t lodignoresh           : 1;  /**< [  2:  2](R/W) LocalOrderDomain DMB/DSB_NSH{ST} ignores shareability (applies to both nsh and ish pages). */
8633         uint64_t lmtstena              : 1;  /**< [  3:  3](R/W) Enable LMTST. */
8634         uint64_t ioatomicena           : 1;  /**< [  4:  4](R/W) Enable SSO and PKO address region.
8635                                                                  0 = Accesses described below will trap.
8636                                                                  1 = Allow \> 64-bit memory instructions, multi-register memory instructions, and
8637                                                                  atomic instructions to SSO and PKO I/O address regions. This must be set if SSO
8638                                                                  or PKO are to be used.
8639 
8640                                                                  Other address regions (e.g. SLI) are not affected by this setting. */
8641         uint64_t node1trapena          : 1;  /**< [  5:  5](R/W) Trap any access to nonzero node id. */
8642         uint64_t switchtagena          : 1;  /**< [  6:  6](R/W) Enable SSO switch-tag caching. The cache must be invalidated through e.g. use of
8643                                                                  SSO_WS_CFG[SSO_SAI_FLUSH] before clearing this bit. */
8644         uint64_t spare                 : 1;  /**< [  7:  7](R/W) Reserved; spare. */
8645         uint64_t dprefbpmissthresh     : 12; /**< [ 19:  8](R/W) Data-stream hardware prefetcher backpressure threshold for L2C miss latency. */
8646         uint64_t dprefbphitthresh      : 12; /**< [ 31: 20](R/W) Data-stream hardware prefetcher backpressure threshold for L2C hit latency. */
8647         uint64_t dprefbpctl            : 4;  /**< [ 35: 32](R/W) Data-stream hardware prefetcher backpressure control mask for dual counter mode.
8648                                                                  Internal:
8649                                                                  Backpressure is applied if:
8650                                                                  \<pre\>
8651                                                                    (   ([DPREFBPCTL]\<0\> && !hit_ctr_bp && !miss_ctr_bp)
8652                                                                     || ([DPREFBPCTL]\<1\> && !hit_ctr_bp &&  miss_ctr_bp)
8653                                                                     || ([DPREFBPCTL]\<2\> &&  hit_ctr_bp && !miss_ctr_bp)
8654                                                                     || ([DPREFBPCTL]\<3\> &&  hit_ctr_bp &&  miss_ctr_bp))
8655                                                                  \</pre\>
8656 
8657                                                                  Where hit_ctr_bp is the MSB of the 4-bit hit counter being set, and miss_ctr_bp
8658                                                                  is the MSB of the 4-bit miss counter being set. */
8659         uint64_t dprefbpmode           : 1;  /**< [ 36: 36](R/W) Data-stream hardware prefetcher backpressure mode select.
8660                                                                  0 = Single counter mode (combined hit and miss latency counter).
8661                                                                  1 = Dual counter mode (separate hit and miss latency counters). */
8662         uint64_t tlbilocalicflush      : 1;  /**< [ 37: 37](R/W) Force ICache flush when any local TLBI is issued.
8663                                                                  0 = Do nothing.
8664                                                                  1 = Flush the ICache. */
8665         uint64_t tlbiremoteicflush     : 1;  /**< [ 38: 38](R/W) Force ICache flush when any remote TLBI is received.
8666                                                                  0 = Do nothing.
8667                                                                  1 = Flush the ICache. */
8668         uint64_t reserved_39_63        : 25;
8669 #endif /* Word 0 - End */
8670     } cn83xx;
8671 };
8672 typedef union bdk_ap_cvmmemctl1_el1 bdk_ap_cvmmemctl1_el1_t;
8673 
8674 #define BDK_AP_CVMMEMCTL1_EL1 BDK_AP_CVMMEMCTL1_EL1_FUNC()
8675 static inline uint64_t BDK_AP_CVMMEMCTL1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVMMEMCTL1_EL1_FUNC(void)8676 static inline uint64_t BDK_AP_CVMMEMCTL1_EL1_FUNC(void)
8677 {
8678     return 0x3000b000500ll;
8679 }
8680 
8681 #define typedef_BDK_AP_CVMMEMCTL1_EL1 bdk_ap_cvmmemctl1_el1_t
8682 #define bustype_BDK_AP_CVMMEMCTL1_EL1 BDK_CSR_TYPE_SYSREG
8683 #define basename_BDK_AP_CVMMEMCTL1_EL1 "AP_CVMMEMCTL1_EL1"
8684 #define busnum_BDK_AP_CVMMEMCTL1_EL1 0
8685 #define arguments_BDK_AP_CVMMEMCTL1_EL1 -1,-1,-1,-1
8686 
8687 /**
8688  * Register (SYSREG) ap_cvmmemctl2_el1
8689  *
8690  * AP Cavium Memory Control 2 Register
8691  * This register controls additional memory-unit features.
8692  * Internal:
8693  * Back-end, non-debug.
8694  */
8695 union bdk_ap_cvmmemctl2_el1
8696 {
8697     uint64_t u;
8698     struct bdk_ap_cvmmemctl2_el1_s
8699     {
8700 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8701         uint64_t rsvd_63_60            : 4;  /**< [ 63: 60](R/W) Reserved. */
8702         uint64_t tlbiremotegsyncall    : 1;  /**< [ 59: 59](R/W) Remote TLBI apply GSYNC semantics.  For diagnostic use only. */
8703         uint64_t tlbiremotemultidis    : 1;  /**< [ 58: 58](R/W) Remote TLBI multiple processing disable.  For diagnostic use only. */
8704         uint64_t tlbiremotebatchdis    : 1;  /**< [ 57: 57](R/W) Remote TLBI batch processing disable.  For diagnostic use only. */
8705         uint64_t l1dwaysm1             : 6;  /**< [ 56: 51](R/W) Number of L1D WAYS minus one. */
8706         uint64_t wbfentriesm1          : 5;  /**< [ 50: 46](R/W) Number of MAF WBUF entries minus one. */
8707         uint64_t rbfentriesm1          : 4;  /**< [ 45: 42](R/W) Number of MAF RBUF entries minus one. */
8708         uint64_t ptwspecdis            : 1;  /**< [ 41: 41](R/W) Disable page table walker access on speculative instructions. */
8709         uint64_t ptwprefudis           : 1;  /**< [ 40: 40](R/W) Disable page table walker access on PREFU instructions. */
8710         uint64_t ptwdhwprefdis         : 1;  /**< [ 39: 39](R/W) Disable page table walker access on dstream hardware prefetches. */
8711         uint64_t ptwdswprefdis         : 1;  /**< [ 38: 38](R/W) Disable page table walker access on dstream software prefetches. */
8712         uint64_t ptwihwprefdis         : 1;  /**< [ 37: 37](R/W) Disable page table walker access on istream hardware prefetches. */
8713         uint64_t ptwiswprefdis         : 1;  /**< [ 36: 36](R/W) Disable page table walker access on istream software prefetches. */
8714         uint64_t mtlbdhwprefdis        : 1;  /**< [ 35: 35](R/W) Disable MTLB access on dstream hardware prefetches. */
8715         uint64_t mtlbdswprefdis        : 1;  /**< [ 34: 34](R/W) Disable MTLB access on dstream software prefetches. */
8716         uint64_t mtlbihwprefdis        : 1;  /**< [ 33: 33](R/W) Disable MTLB access on istream hardware prefetches. */
8717         uint64_t mtlbiswprefdis        : 1;  /**< [ 32: 32](R/W) Disable MTLB access on istream software prefetches. */
8718         uint64_t rsvd_25_31            : 7;  /**< [ 31: 25](R/W) Reserved. */
8719         uint64_t tlbi_block_msk        : 9;  /**< [ 24: 16](R/W) Mask of block sizes that are precisely invalidated by TLBI instructions.
8720                                                                  For each bit {a} in this field:
8721                                                                  _ Mask\<{a}\>=0 = blocksize {a} is not precisely invalidated.
8722                                                                  _ Mask\<{a}\>=1 = blocksize {a} is     precisely invalidated.
8723 
8724                                                                  _ Mask\<0\> represents block size 2^12.
8725                                                                  _ Mask\<1\> represents block size 2^14.
8726                                                                  _ Mask\<2\> represents block size 2^16.
8727                                                                  _ Mask\<3\> represents block size 2^21.
8728                                                                  _ Mask\<4\> represents block size 2^25.
8729                                                                  _ Mask\<5\> represents block size 2^29.
8730                                                                  _ Mask\<6\> represents block size 2^30.
8731                                                                  _ Mask\<7\> represents block size 2^34.
8732                                                                  _ Mask\<8\> represents block size 2^42. */
8733         uint64_t rsvd_9_15             : 7;  /**< [ 15:  9](R/W) Reserved. */
8734         uint64_t mtlb0_block_msk       : 9;  /**< [  8:  0](R/W) Mask of block sizes that are allocated in MTLB0.
8735                                                                  For each bit {a} in this field:
8736                                                                  _ Mask\<{a}\>=0 = blocksize {a} allocated in MTLB1.
8737                                                                  _ Mask\<{a}\>=1 = blocksize {a} allocated in MTLB0.
8738 
8739                                                                  _ Mask\<0\> represents block size 2^12.
8740                                                                  _ Mask\<1\> represents block size 2^14.
8741                                                                  _ Mask\<2\> represents block size 2^16.
8742                                                                  _ Mask\<3\> represents block size 2^21.
8743                                                                  _ Mask\<4\> represents block size 2^25.
8744                                                                  _ Mask\<5\> represents block size 2^29.
8745                                                                  _ Mask\<6\> represents block size 2^30.
8746                                                                  _ Mask\<7\> represents block size 2^34.
8747                                                                  _ Mask\<8\> represents block size 2^42. */
8748 #else /* Word 0 - Little Endian */
8749         uint64_t mtlb0_block_msk       : 9;  /**< [  8:  0](R/W) Mask of block sizes that are allocated in MTLB0.
8750                                                                  For each bit {a} in this field:
8751                                                                  _ Mask\<{a}\>=0 = blocksize {a} allocated in MTLB1.
8752                                                                  _ Mask\<{a}\>=1 = blocksize {a} allocated in MTLB0.
8753 
8754                                                                  _ Mask\<0\> represents block size 2^12.
8755                                                                  _ Mask\<1\> represents block size 2^14.
8756                                                                  _ Mask\<2\> represents block size 2^16.
8757                                                                  _ Mask\<3\> represents block size 2^21.
8758                                                                  _ Mask\<4\> represents block size 2^25.
8759                                                                  _ Mask\<5\> represents block size 2^29.
8760                                                                  _ Mask\<6\> represents block size 2^30.
8761                                                                  _ Mask\<7\> represents block size 2^34.
8762                                                                  _ Mask\<8\> represents block size 2^42. */
8763         uint64_t rsvd_9_15             : 7;  /**< [ 15:  9](R/W) Reserved. */
8764         uint64_t tlbi_block_msk        : 9;  /**< [ 24: 16](R/W) Mask of block sizes that are precisely invalidated by TLBI instructions.
8765                                                                  For each bit {a} in this field:
8766                                                                  _ Mask\<{a}\>=0 = blocksize {a} is not precisely invalidated.
8767                                                                  _ Mask\<{a}\>=1 = blocksize {a} is     precisely invalidated.
8768 
8769                                                                  _ Mask\<0\> represents block size 2^12.
8770                                                                  _ Mask\<1\> represents block size 2^14.
8771                                                                  _ Mask\<2\> represents block size 2^16.
8772                                                                  _ Mask\<3\> represents block size 2^21.
8773                                                                  _ Mask\<4\> represents block size 2^25.
8774                                                                  _ Mask\<5\> represents block size 2^29.
8775                                                                  _ Mask\<6\> represents block size 2^30.
8776                                                                  _ Mask\<7\> represents block size 2^34.
8777                                                                  _ Mask\<8\> represents block size 2^42. */
8778         uint64_t rsvd_25_31            : 7;  /**< [ 31: 25](R/W) Reserved. */
8779         uint64_t mtlbiswprefdis        : 1;  /**< [ 32: 32](R/W) Disable MTLB access on istream software prefetches. */
8780         uint64_t mtlbihwprefdis        : 1;  /**< [ 33: 33](R/W) Disable MTLB access on istream hardware prefetches. */
8781         uint64_t mtlbdswprefdis        : 1;  /**< [ 34: 34](R/W) Disable MTLB access on dstream software prefetches. */
8782         uint64_t mtlbdhwprefdis        : 1;  /**< [ 35: 35](R/W) Disable MTLB access on dstream hardware prefetches. */
8783         uint64_t ptwiswprefdis         : 1;  /**< [ 36: 36](R/W) Disable page table walker access on istream software prefetches. */
8784         uint64_t ptwihwprefdis         : 1;  /**< [ 37: 37](R/W) Disable page table walker access on istream hardware prefetches. */
8785         uint64_t ptwdswprefdis         : 1;  /**< [ 38: 38](R/W) Disable page table walker access on dstream software prefetches. */
8786         uint64_t ptwdhwprefdis         : 1;  /**< [ 39: 39](R/W) Disable page table walker access on dstream hardware prefetches. */
8787         uint64_t ptwprefudis           : 1;  /**< [ 40: 40](R/W) Disable page table walker access on PREFU instructions. */
8788         uint64_t ptwspecdis            : 1;  /**< [ 41: 41](R/W) Disable page table walker access on speculative instructions. */
8789         uint64_t rbfentriesm1          : 4;  /**< [ 45: 42](R/W) Number of MAF RBUF entries minus one. */
8790         uint64_t wbfentriesm1          : 5;  /**< [ 50: 46](R/W) Number of MAF WBUF entries minus one. */
8791         uint64_t l1dwaysm1             : 6;  /**< [ 56: 51](R/W) Number of L1D WAYS minus one. */
8792         uint64_t tlbiremotebatchdis    : 1;  /**< [ 57: 57](R/W) Remote TLBI batch processing disable.  For diagnostic use only. */
8793         uint64_t tlbiremotemultidis    : 1;  /**< [ 58: 58](R/W) Remote TLBI multiple processing disable.  For diagnostic use only. */
8794         uint64_t tlbiremotegsyncall    : 1;  /**< [ 59: 59](R/W) Remote TLBI apply GSYNC semantics.  For diagnostic use only. */
8795         uint64_t rsvd_63_60            : 4;  /**< [ 63: 60](R/W) Reserved. */
8796 #endif /* Word 0 - End */
8797     } s;
8798     /* struct bdk_ap_cvmmemctl2_el1_s cn; */
8799 };
8800 typedef union bdk_ap_cvmmemctl2_el1 bdk_ap_cvmmemctl2_el1_t;
8801 
8802 #define BDK_AP_CVMMEMCTL2_EL1 BDK_AP_CVMMEMCTL2_EL1_FUNC()
8803 static inline uint64_t BDK_AP_CVMMEMCTL2_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVMMEMCTL2_EL1_FUNC(void)8804 static inline uint64_t BDK_AP_CVMMEMCTL2_EL1_FUNC(void)
8805 {
8806     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
8807         return 0x3000b000600ll;
8808     __bdk_csr_fatal("AP_CVMMEMCTL2_EL1", 0, 0, 0, 0, 0);
8809 }
8810 
8811 #define typedef_BDK_AP_CVMMEMCTL2_EL1 bdk_ap_cvmmemctl2_el1_t
8812 #define bustype_BDK_AP_CVMMEMCTL2_EL1 BDK_CSR_TYPE_SYSREG
8813 #define basename_BDK_AP_CVMMEMCTL2_EL1 "AP_CVMMEMCTL2_EL1"
8814 #define busnum_BDK_AP_CVMMEMCTL2_EL1 0
8815 #define arguments_BDK_AP_CVMMEMCTL2_EL1 -1,-1,-1,-1
8816 
8817 /**
8818  * Register (SYSREG) ap_cvmmemctl3_el1
8819  *
8820  * AP Cavium Memory Control 3 Register
8821  * This register controls additional memory-unit features.
8822  * Internal:
8823  * Back-end, non-debug.
8824  */
8825 union bdk_ap_cvmmemctl3_el1
8826 {
8827     uint64_t u;
8828     struct bdk_ap_cvmmemctl3_el1_s
8829     {
8830 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8831         uint64_t rsvd_63_12            : 52; /**< [ 63: 12](RAZ) Reserved. */
8832         uint64_t iopredclrfreq         : 4;  /**< [ 11:  8](R/W) IO predictor clear frequency. For diagnostic use only. */
8833         uint64_t unalignpredclrfreq    : 4;  /**< [  7:  4](R/W) Unaligned predictor clear frequency. For diagnostic use only. */
8834         uint64_t ldstpredclrfreq       : 4;  /**< [  3:  0](R/W) Load-store predictor clear frequency. For diagnostic use only. */
8835 #else /* Word 0 - Little Endian */
8836         uint64_t ldstpredclrfreq       : 4;  /**< [  3:  0](R/W) Load-store predictor clear frequency. For diagnostic use only. */
8837         uint64_t unalignpredclrfreq    : 4;  /**< [  7:  4](R/W) Unaligned predictor clear frequency. For diagnostic use only. */
8838         uint64_t iopredclrfreq         : 4;  /**< [ 11:  8](R/W) IO predictor clear frequency. For diagnostic use only. */
8839         uint64_t rsvd_63_12            : 52; /**< [ 63: 12](RAZ) Reserved. */
8840 #endif /* Word 0 - End */
8841     } s;
8842     /* struct bdk_ap_cvmmemctl3_el1_s cn; */
8843 };
8844 typedef union bdk_ap_cvmmemctl3_el1 bdk_ap_cvmmemctl3_el1_t;
8845 
8846 #define BDK_AP_CVMMEMCTL3_EL1 BDK_AP_CVMMEMCTL3_EL1_FUNC()
8847 static inline uint64_t BDK_AP_CVMMEMCTL3_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_CVMMEMCTL3_EL1_FUNC(void)8848 static inline uint64_t BDK_AP_CVMMEMCTL3_EL1_FUNC(void)
8849 {
8850     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
8851         return 0x3000b000700ll;
8852     __bdk_csr_fatal("AP_CVMMEMCTL3_EL1", 0, 0, 0, 0, 0);
8853 }
8854 
8855 #define typedef_BDK_AP_CVMMEMCTL3_EL1 bdk_ap_cvmmemctl3_el1_t
8856 #define bustype_BDK_AP_CVMMEMCTL3_EL1 BDK_CSR_TYPE_SYSREG
8857 #define basename_BDK_AP_CVMMEMCTL3_EL1 "AP_CVMMEMCTL3_EL1"
8858 #define busnum_BDK_AP_CVMMEMCTL3_EL1 0
8859 #define arguments_BDK_AP_CVMMEMCTL3_EL1 -1,-1,-1,-1
8860 
8861 /**
8862  * Register (SYSREG) ap_dacr32_el2
8863  *
8864  * AP Domain Access Control Register
8865  * Allows access to the AArch32 DACR register from AArch64 state
8866  *     only. Its value has no effect on execution in AArch64 state.
8867  */
8868 union bdk_ap_dacr32_el2
8869 {
8870     uint32_t u;
8871     struct bdk_ap_dacr32_el2_s
8872     {
8873 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8874         uint32_t reserved_0_31         : 32;
8875 #else /* Word 0 - Little Endian */
8876         uint32_t reserved_0_31         : 32;
8877 #endif /* Word 0 - End */
8878     } s;
8879     /* struct bdk_ap_dacr32_el2_s cn; */
8880 };
8881 typedef union bdk_ap_dacr32_el2 bdk_ap_dacr32_el2_t;
8882 
8883 #define BDK_AP_DACR32_EL2 BDK_AP_DACR32_EL2_FUNC()
8884 static inline uint64_t BDK_AP_DACR32_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DACR32_EL2_FUNC(void)8885 static inline uint64_t BDK_AP_DACR32_EL2_FUNC(void)
8886 {
8887     return 0x30403000000ll;
8888 }
8889 
8890 #define typedef_BDK_AP_DACR32_EL2 bdk_ap_dacr32_el2_t
8891 #define bustype_BDK_AP_DACR32_EL2 BDK_CSR_TYPE_SYSREG
8892 #define basename_BDK_AP_DACR32_EL2 "AP_DACR32_EL2"
8893 #define busnum_BDK_AP_DACR32_EL2 0
8894 #define arguments_BDK_AP_DACR32_EL2 -1,-1,-1,-1
8895 
8896 /**
8897  * Register (SYSREG) ap_daif
8898  *
8899  * AP Interrupt Mask Bits Register
8900  * Allows access to the interrupt mask bits.
8901  */
8902 union bdk_ap_daif
8903 {
8904     uint32_t u;
8905     struct bdk_ap_daif_s
8906     {
8907 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8908         uint32_t reserved_10_31        : 22;
8909         uint32_t dd                    : 1;  /**< [  9:  9](R/W) Process state D mask.
8910                                                                  When the target Exception level of the debug exception is not
8911                                                                      than the current Exception level, the exception is not masked
8912                                                                      by this bit.
8913                                                                  0 = Debug exceptions from Watchpoint, Breakpoint, and Software
8914                                                                      step debug events targeted at the current Exception level are
8915                                                                      not masked.
8916                                                                  1 = Debug exceptions from Watchpoint, Breakpoint, and Software
8917                                                                      step debug events targeted at the current Exception level are
8918                                                                      masked. */
8919         uint32_t aa                    : 1;  /**< [  8:  8](R/W) SError (System Error) mask bit.
8920                                                                  0 = Exception not masked.
8921                                                                  1 = Exception masked. */
8922         uint32_t i                     : 1;  /**< [  7:  7](R/W) IRQ mask bit.
8923                                                                  0 = Exception not masked.
8924                                                                  1 = Exception masked. */
8925         uint32_t f                     : 1;  /**< [  6:  6](R/W) FIQ mask bit.
8926                                                                  0 = Exception not masked.
8927                                                                  1 = Exception masked. */
8928         uint32_t reserved_0_5          : 6;
8929 #else /* Word 0 - Little Endian */
8930         uint32_t reserved_0_5          : 6;
8931         uint32_t f                     : 1;  /**< [  6:  6](R/W) FIQ mask bit.
8932                                                                  0 = Exception not masked.
8933                                                                  1 = Exception masked. */
8934         uint32_t i                     : 1;  /**< [  7:  7](R/W) IRQ mask bit.
8935                                                                  0 = Exception not masked.
8936                                                                  1 = Exception masked. */
8937         uint32_t aa                    : 1;  /**< [  8:  8](R/W) SError (System Error) mask bit.
8938                                                                  0 = Exception not masked.
8939                                                                  1 = Exception masked. */
8940         uint32_t dd                    : 1;  /**< [  9:  9](R/W) Process state D mask.
8941                                                                  When the target Exception level of the debug exception is not
8942                                                                      than the current Exception level, the exception is not masked
8943                                                                      by this bit.
8944                                                                  0 = Debug exceptions from Watchpoint, Breakpoint, and Software
8945                                                                      step debug events targeted at the current Exception level are
8946                                                                      not masked.
8947                                                                  1 = Debug exceptions from Watchpoint, Breakpoint, and Software
8948                                                                      step debug events targeted at the current Exception level are
8949                                                                      masked. */
8950         uint32_t reserved_10_31        : 22;
8951 #endif /* Word 0 - End */
8952     } s;
8953     /* struct bdk_ap_daif_s cn; */
8954 };
8955 typedef union bdk_ap_daif bdk_ap_daif_t;
8956 
8957 #define BDK_AP_DAIF BDK_AP_DAIF_FUNC()
8958 static inline uint64_t BDK_AP_DAIF_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DAIF_FUNC(void)8959 static inline uint64_t BDK_AP_DAIF_FUNC(void)
8960 {
8961     return 0x30304020100ll;
8962 }
8963 
8964 #define typedef_BDK_AP_DAIF bdk_ap_daif_t
8965 #define bustype_BDK_AP_DAIF BDK_CSR_TYPE_SYSREG
8966 #define basename_BDK_AP_DAIF "AP_DAIF"
8967 #define busnum_BDK_AP_DAIF 0
8968 #define arguments_BDK_AP_DAIF -1,-1,-1,-1
8969 
8970 /**
8971  * Register (SYSREG) ap_dbgauthstatus_el1
8972  *
8973  * AP Debug Authentication Status Register
8974  * Provides information about the state of the implementation
8975  *     defined authentication interface for debug.
8976  */
8977 union bdk_ap_dbgauthstatus_el1
8978 {
8979     uint32_t u;
8980     struct bdk_ap_dbgauthstatus_el1_s
8981     {
8982 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
8983         uint32_t reserved_8_31         : 24;
8984         uint32_t snid                  : 2;  /**< [  7:  6](RO) Secure non-invasive debug.
8985                                                                  0x0 = Not implemented. EL3 is not implemented and the processor is
8986                                                                      nonsecure.
8987                                                                  0x2 = Implemented and disabled.
8988                                                                  0x3 = Implemented and enabled. */
8989         uint32_t sid                   : 2;  /**< [  5:  4](RO) Secure invasive debug.
8990                                                                  0x0 = Not implemented. EL3 is not implemented and the processor is
8991                                                                      nonsecure.
8992                                                                  0x2 = Implemented and disabled.
8993                                                                  0x3 = Implemented and enabled. */
8994         uint32_t nsnid                 : 2;  /**< [  3:  2](RO) Nonsecure non-invasive debug.
8995                                                                  0x0 = Not implemented. EL3 is not implemented and the processor is
8996                                                                      Secure.
8997                                                                  0x2 = Implemented and disabled.
8998                                                                  0x3 = Implemented and enabled. */
8999         uint32_t nsid                  : 2;  /**< [  1:  0](RO) Nonsecure invasive debug.
9000                                                                  0x0 = Not implemented. EL3 is not implemented and the processor is
9001                                                                  0x2 = Implemented and disabled.
9002                                                                  0x3 = Implemented and enabled. */
9003 #else /* Word 0 - Little Endian */
9004         uint32_t nsid                  : 2;  /**< [  1:  0](RO) Nonsecure invasive debug.
9005                                                                  0x0 = Not implemented. EL3 is not implemented and the processor is
9006                                                                  0x2 = Implemented and disabled.
9007                                                                  0x3 = Implemented and enabled. */
9008         uint32_t nsnid                 : 2;  /**< [  3:  2](RO) Nonsecure non-invasive debug.
9009                                                                  0x0 = Not implemented. EL3 is not implemented and the processor is
9010                                                                      Secure.
9011                                                                  0x2 = Implemented and disabled.
9012                                                                  0x3 = Implemented and enabled. */
9013         uint32_t sid                   : 2;  /**< [  5:  4](RO) Secure invasive debug.
9014                                                                  0x0 = Not implemented. EL3 is not implemented and the processor is
9015                                                                      nonsecure.
9016                                                                  0x2 = Implemented and disabled.
9017                                                                  0x3 = Implemented and enabled. */
9018         uint32_t snid                  : 2;  /**< [  7:  6](RO) Secure non-invasive debug.
9019                                                                  0x0 = Not implemented. EL3 is not implemented and the processor is
9020                                                                      nonsecure.
9021                                                                  0x2 = Implemented and disabled.
9022                                                                  0x3 = Implemented and enabled. */
9023         uint32_t reserved_8_31         : 24;
9024 #endif /* Word 0 - End */
9025     } s;
9026     /* struct bdk_ap_dbgauthstatus_el1_s cn; */
9027 };
9028 typedef union bdk_ap_dbgauthstatus_el1 bdk_ap_dbgauthstatus_el1_t;
9029 
9030 #define BDK_AP_DBGAUTHSTATUS_EL1 BDK_AP_DBGAUTHSTATUS_EL1_FUNC()
9031 static inline uint64_t BDK_AP_DBGAUTHSTATUS_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DBGAUTHSTATUS_EL1_FUNC(void)9032 static inline uint64_t BDK_AP_DBGAUTHSTATUS_EL1_FUNC(void)
9033 {
9034     return 0x200070e0600ll;
9035 }
9036 
9037 #define typedef_BDK_AP_DBGAUTHSTATUS_EL1 bdk_ap_dbgauthstatus_el1_t
9038 #define bustype_BDK_AP_DBGAUTHSTATUS_EL1 BDK_CSR_TYPE_SYSREG
9039 #define basename_BDK_AP_DBGAUTHSTATUS_EL1 "AP_DBGAUTHSTATUS_EL1"
9040 #define busnum_BDK_AP_DBGAUTHSTATUS_EL1 0
9041 #define arguments_BDK_AP_DBGAUTHSTATUS_EL1 -1,-1,-1,-1
9042 
9043 /**
9044  * Register (SYSREG) ap_dbgbcr#_el1
9045  *
9046  * AP Debug Breakpoint Control Registers
9047  * Holds control information for a breakpoint. Forms breakpoint n
9048  *     together with value register DBGBVR\<n\>_EL1, where n is 0 to
9049  *     15.
9050  */
9051 union bdk_ap_dbgbcrx_el1
9052 {
9053     uint32_t u;
9054     struct bdk_ap_dbgbcrx_el1_s
9055     {
9056 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9057         uint32_t reserved_24_31        : 8;
9058         uint32_t bt                    : 4;  /**< [ 23: 20](R/W) Breakpoint Type.
9059                                                                  The field breaks down as follows:
9060                                                                   BT[3:1]: Base type.- 0b000: Match address. DBGBVR\<n\>_EL1 is
9061                                                                      the address of an     instruction. - 0b010: Mismatch address.
9062                                                                      Behaves as type0b000 DBGBVR\<n\>_EL1     is the address of an
9063                                                                      instruction to be stepped. - 0b001: Match context ID.
9064                                                                      DBGBVR\<n\>_EL1[31:0] is a context     ID. - 0b100: Match VMID.
9065                                                                      DBGBVR\<n\>_EL1[39:32] is a VMID. - 0b101: Match VMID and
9066                                                                      context ID. DBGBVR\<n\>_EL1[31:0] is a     context ID, and
9067                                                                      DBGBVR\<n\>_EL1[39:32] is a VMID.
9068                                                                   BT[0]: Enable linking.
9069 
9070                                                                  If the breakpoint is not context-aware, BT[3] and BT[1] are
9071                                                                      RES0. If EL2 is not implemented, BT[3] is RES0. If EL1 using
9072                                                                      AArch32 is not implemented, BT[2] is RES0.
9073 
9074                                                                  0x0 = Unlinked address match.
9075                                                                  0x1 = Linked address match.
9076                                                                  0x2 = Unlinked context ID match.
9077                                                                  0x3 = Linked context ID match
9078                                                                  0x4 = Unlinked address mismatch.
9079                                                                  0x5 = Linked address mismatch.
9080                                                                  0x8 = Unlinked VMID match.
9081                                                                  0x9 = Linked VMID match.
9082                                                                  0xA = Unlinked VMID and context ID match.
9083                                                                  0xB = Linked VMID and context ID match. */
9084         uint32_t lbn                   : 4;  /**< [ 19: 16](R/W) Linked breakpoint number. For Linked address matching
9085                                                                      breakpoints, this specifies the index of the Context-matching
9086                                                                      breakpoint linked to. */
9087         uint32_t ssc                   : 2;  /**< [ 15: 14](R/W) Security state control. Determines the Security states under
9088                                                                      which a breakpoint debug event for breakpoint n is generated.
9089                                                                      This field must be interpreted along with the HMC and PMC
9090                                                                      fields. */
9091         uint32_t hmc                   : 1;  /**< [ 13: 13](R/W) Higher mode control. Determines the debug perspective for
9092                                                                      deciding when a breakpoint debug event for breakpoint n is
9093                                                                      generated. This field must be interpreted along with the SSC
9094                                                                      and PMC fields. */
9095         uint32_t reserved_9_12         : 4;
9096         uint32_t rsvd_5_8              : 4;  /**< [  8:  5](RO) Byte address select. Defines which half-words an address-
9097                                                                      matching breakpoint matches, regardless of the instruction set
9098                                                                      and Execution state. In an AArch64-only implementation, this
9099                                                                      field is reserved, RES1. Otherwise:
9100 
9101                                                                   BAS[2] and BAS[0] are read/write.
9102 
9103                                                                   BAS[3] and BAS[1] are read-only copies of BAS[2] and BAS[0]
9104                                                                      respectively.
9105 
9106                                                                  The permitted values depend on the breakpoint type.
9107 
9108                                                                  For Address match breakpoints in either AArch32 or AArch64
9109                                                                      state:
9110                                                                  BAS Match instruction at    Constraint for debuggers
9111                                                                  0b0011       DBGBVR\<n\>_EL1  Use for T32 instructions.
9112                                                                  0b1100       DBGBVR\<n\>_EL1+2        Use for T32 instructions.
9113                                                                  0b1111       DBGBVR\<n\>_EL1  Use for A64 and A32 instructions.
9114                                                                  0b0000
9115 
9116                                                                  For Address mismatch breakpoints in an AArch32 stage 1
9117                                                                      translation regime:
9118                                                                  BAS Step instruction at     Constraint for debuggers
9119                                                                  0b0000      -       Use for a match anywhere breakpoint.
9120                                                                  0b0011       DBGBVR\<n\>_EL1  Use for stepping T32 instructions.
9121                                                                  0b1100       DBGBVR\<n\>_EL1+2        Use for stepping T32 instructions.
9122                                                                  0b1111       DBGBVR\<n\>_EL1  Use for stepping A32 instructions.
9123 
9124                                                                  For Context matching breakpoints, this field is RES1 and
9125                                                                      ignored. */
9126         uint32_t reserved_3_4          : 2;
9127         uint32_t pmc                   : 2;  /**< [  2:  1](R/W) Privilege mode control. Determines the Exception level or
9128                                                                      levels at which a breakpoint debug event for breakpoint n is
9129                                                                      generated. This field must be interpreted along with the SSC
9130                                                                      and HMC fields. */
9131         uint32_t ee                    : 1;  /**< [  0:  0](R/W) Enable breakpoint DBGBVR\<n\>_EL1.
9132                                                                  0 = Breakpoint disabled.
9133                                                                  1 = Breakpoint enabled. */
9134 #else /* Word 0 - Little Endian */
9135         uint32_t ee                    : 1;  /**< [  0:  0](R/W) Enable breakpoint DBGBVR\<n\>_EL1.
9136                                                                  0 = Breakpoint disabled.
9137                                                                  1 = Breakpoint enabled. */
9138         uint32_t pmc                   : 2;  /**< [  2:  1](R/W) Privilege mode control. Determines the Exception level or
9139                                                                      levels at which a breakpoint debug event for breakpoint n is
9140                                                                      generated. This field must be interpreted along with the SSC
9141                                                                      and HMC fields. */
9142         uint32_t reserved_3_4          : 2;
9143         uint32_t rsvd_5_8              : 4;  /**< [  8:  5](RO) Byte address select. Defines which half-words an address-
9144                                                                      matching breakpoint matches, regardless of the instruction set
9145                                                                      and Execution state. In an AArch64-only implementation, this
9146                                                                      field is reserved, RES1. Otherwise:
9147 
9148                                                                   BAS[2] and BAS[0] are read/write.
9149 
9150                                                                   BAS[3] and BAS[1] are read-only copies of BAS[2] and BAS[0]
9151                                                                      respectively.
9152 
9153                                                                  The permitted values depend on the breakpoint type.
9154 
9155                                                                  For Address match breakpoints in either AArch32 or AArch64
9156                                                                      state:
9157                                                                  BAS Match instruction at    Constraint for debuggers
9158                                                                  0b0011       DBGBVR\<n\>_EL1  Use for T32 instructions.
9159                                                                  0b1100       DBGBVR\<n\>_EL1+2        Use for T32 instructions.
9160                                                                  0b1111       DBGBVR\<n\>_EL1  Use for A64 and A32 instructions.
9161                                                                  0b0000
9162 
9163                                                                  For Address mismatch breakpoints in an AArch32 stage 1
9164                                                                      translation regime:
9165                                                                  BAS Step instruction at     Constraint for debuggers
9166                                                                  0b0000      -       Use for a match anywhere breakpoint.
9167                                                                  0b0011       DBGBVR\<n\>_EL1  Use for stepping T32 instructions.
9168                                                                  0b1100       DBGBVR\<n\>_EL1+2        Use for stepping T32 instructions.
9169                                                                  0b1111       DBGBVR\<n\>_EL1  Use for stepping A32 instructions.
9170 
9171                                                                  For Context matching breakpoints, this field is RES1 and
9172                                                                      ignored. */
9173         uint32_t reserved_9_12         : 4;
9174         uint32_t hmc                   : 1;  /**< [ 13: 13](R/W) Higher mode control. Determines the debug perspective for
9175                                                                      deciding when a breakpoint debug event for breakpoint n is
9176                                                                      generated. This field must be interpreted along with the SSC
9177                                                                      and PMC fields. */
9178         uint32_t ssc                   : 2;  /**< [ 15: 14](R/W) Security state control. Determines the Security states under
9179                                                                      which a breakpoint debug event for breakpoint n is generated.
9180                                                                      This field must be interpreted along with the HMC and PMC
9181                                                                      fields. */
9182         uint32_t lbn                   : 4;  /**< [ 19: 16](R/W) Linked breakpoint number. For Linked address matching
9183                                                                      breakpoints, this specifies the index of the Context-matching
9184                                                                      breakpoint linked to. */
9185         uint32_t bt                    : 4;  /**< [ 23: 20](R/W) Breakpoint Type.
9186                                                                  The field breaks down as follows:
9187                                                                   BT[3:1]: Base type.- 0b000: Match address. DBGBVR\<n\>_EL1 is
9188                                                                      the address of an     instruction. - 0b010: Mismatch address.
9189                                                                      Behaves as type0b000 DBGBVR\<n\>_EL1     is the address of an
9190                                                                      instruction to be stepped. - 0b001: Match context ID.
9191                                                                      DBGBVR\<n\>_EL1[31:0] is a context     ID. - 0b100: Match VMID.
9192                                                                      DBGBVR\<n\>_EL1[39:32] is a VMID. - 0b101: Match VMID and
9193                                                                      context ID. DBGBVR\<n\>_EL1[31:0] is a     context ID, and
9194                                                                      DBGBVR\<n\>_EL1[39:32] is a VMID.
9195                                                                   BT[0]: Enable linking.
9196 
9197                                                                  If the breakpoint is not context-aware, BT[3] and BT[1] are
9198                                                                      RES0. If EL2 is not implemented, BT[3] is RES0. If EL1 using
9199                                                                      AArch32 is not implemented, BT[2] is RES0.
9200 
9201                                                                  0x0 = Unlinked address match.
9202                                                                  0x1 = Linked address match.
9203                                                                  0x2 = Unlinked context ID match.
9204                                                                  0x3 = Linked context ID match
9205                                                                  0x4 = Unlinked address mismatch.
9206                                                                  0x5 = Linked address mismatch.
9207                                                                  0x8 = Unlinked VMID match.
9208                                                                  0x9 = Linked VMID match.
9209                                                                  0xA = Unlinked VMID and context ID match.
9210                                                                  0xB = Linked VMID and context ID match. */
9211         uint32_t reserved_24_31        : 8;
9212 #endif /* Word 0 - End */
9213     } s;
9214     /* struct bdk_ap_dbgbcrx_el1_s cn; */
9215 };
9216 typedef union bdk_ap_dbgbcrx_el1 bdk_ap_dbgbcrx_el1_t;
9217 
9218 static inline uint64_t BDK_AP_DBGBCRX_EL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_DBGBCRX_EL1(unsigned long a)9219 static inline uint64_t BDK_AP_DBGBCRX_EL1(unsigned long a)
9220 {
9221     if (a<=15)
9222         return 0x20000000500ll + 0x10000ll * ((a) & 0xf);
9223     __bdk_csr_fatal("AP_DBGBCRX_EL1", 1, a, 0, 0, 0);
9224 }
9225 
9226 #define typedef_BDK_AP_DBGBCRX_EL1(a) bdk_ap_dbgbcrx_el1_t
9227 #define bustype_BDK_AP_DBGBCRX_EL1(a) BDK_CSR_TYPE_SYSREG
9228 #define basename_BDK_AP_DBGBCRX_EL1(a) "AP_DBGBCRX_EL1"
9229 #define busnum_BDK_AP_DBGBCRX_EL1(a) (a)
9230 #define arguments_BDK_AP_DBGBCRX_EL1(a) (a),-1,-1,-1
9231 
9232 /**
9233  * Register (SYSREG) ap_dbgbvr#_el1
9234  *
9235  * AP Debug Breakpoint Value Registers
9236  * Holds a virtual address, or a VMID and/or a context ID, for
9237  *     use in breakpoint matching. Forms breakpoint n together with
9238  *     control register DBGBCR\<n\>_EL1, where n is 0 to 15.
9239  */
9240 union bdk_ap_dbgbvrx_el1
9241 {
9242     uint64_t u;
9243     struct bdk_ap_dbgbvrx_el1_s
9244     {
9245 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9246         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data for breakpoint value. This doesn't match ARM docs as
9247                                                                  they have many encoding of the same register.
9248                                                                  Reserved, Sign extended. Hardwired to the value of the sign
9249                                                                      bit, bit [48]. Hardware and software must treat this field as
9250                                                                      RES0 if bit[48] is 0, and as RES1 if bit[48] is 1. */
9251 #else /* Word 0 - Little Endian */
9252         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data for breakpoint value. This doesn't match ARM docs as
9253                                                                  they have many encoding of the same register.
9254                                                                  Reserved, Sign extended. Hardwired to the value of the sign
9255                                                                      bit, bit [48]. Hardware and software must treat this field as
9256                                                                      RES0 if bit[48] is 0, and as RES1 if bit[48] is 1. */
9257 #endif /* Word 0 - End */
9258     } s;
9259     /* struct bdk_ap_dbgbvrx_el1_s cn; */
9260 };
9261 typedef union bdk_ap_dbgbvrx_el1 bdk_ap_dbgbvrx_el1_t;
9262 
9263 static inline uint64_t BDK_AP_DBGBVRX_EL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_DBGBVRX_EL1(unsigned long a)9264 static inline uint64_t BDK_AP_DBGBVRX_EL1(unsigned long a)
9265 {
9266     if (a<=15)
9267         return 0x20000000400ll + 0x10000ll * ((a) & 0xf);
9268     __bdk_csr_fatal("AP_DBGBVRX_EL1", 1, a, 0, 0, 0);
9269 }
9270 
9271 #define typedef_BDK_AP_DBGBVRX_EL1(a) bdk_ap_dbgbvrx_el1_t
9272 #define bustype_BDK_AP_DBGBVRX_EL1(a) BDK_CSR_TYPE_SYSREG
9273 #define basename_BDK_AP_DBGBVRX_EL1(a) "AP_DBGBVRX_EL1"
9274 #define busnum_BDK_AP_DBGBVRX_EL1(a) (a)
9275 #define arguments_BDK_AP_DBGBVRX_EL1(a) (a),-1,-1,-1
9276 
9277 /**
9278  * Register (SYSREG) ap_dbgclaimclr_el1
9279  *
9280  * AP Debug Claim Tag Clear Register
9281  * Used by software to read the values of the CLAIM bits, and to
9282  *     clear these bits to 0.
9283  */
9284 union bdk_ap_dbgclaimclr_el1
9285 {
9286     uint32_t u;
9287     struct bdk_ap_dbgclaimclr_el1_s
9288     {
9289 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9290         uint32_t reserved_8_31         : 24;
9291         uint32_t claim                 : 8;  /**< [  7:  0](R/W) Claim clear bits. Reading this field returns the current value
9292                                                                      of the CLAIM bits.
9293                                                                  Writing a 1 to one of these bits clears the corresponding
9294                                                                      CLAIM bit to 0. This is an indirect write to the CLAIM bits.
9295                                                                  A single write operation can clear multiple bits to 0. Writing
9296                                                                      0 to one of these bits has no effect. */
9297 #else /* Word 0 - Little Endian */
9298         uint32_t claim                 : 8;  /**< [  7:  0](R/W) Claim clear bits. Reading this field returns the current value
9299                                                                      of the CLAIM bits.
9300                                                                  Writing a 1 to one of these bits clears the corresponding
9301                                                                      CLAIM bit to 0. This is an indirect write to the CLAIM bits.
9302                                                                  A single write operation can clear multiple bits to 0. Writing
9303                                                                      0 to one of these bits has no effect. */
9304         uint32_t reserved_8_31         : 24;
9305 #endif /* Word 0 - End */
9306     } s;
9307     /* struct bdk_ap_dbgclaimclr_el1_s cn; */
9308 };
9309 typedef union bdk_ap_dbgclaimclr_el1 bdk_ap_dbgclaimclr_el1_t;
9310 
9311 #define BDK_AP_DBGCLAIMCLR_EL1 BDK_AP_DBGCLAIMCLR_EL1_FUNC()
9312 static inline uint64_t BDK_AP_DBGCLAIMCLR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DBGCLAIMCLR_EL1_FUNC(void)9313 static inline uint64_t BDK_AP_DBGCLAIMCLR_EL1_FUNC(void)
9314 {
9315     return 0x20007090600ll;
9316 }
9317 
9318 #define typedef_BDK_AP_DBGCLAIMCLR_EL1 bdk_ap_dbgclaimclr_el1_t
9319 #define bustype_BDK_AP_DBGCLAIMCLR_EL1 BDK_CSR_TYPE_SYSREG
9320 #define basename_BDK_AP_DBGCLAIMCLR_EL1 "AP_DBGCLAIMCLR_EL1"
9321 #define busnum_BDK_AP_DBGCLAIMCLR_EL1 0
9322 #define arguments_BDK_AP_DBGCLAIMCLR_EL1 -1,-1,-1,-1
9323 
9324 /**
9325  * Register (SYSREG) ap_dbgclaimset_el1
9326  *
9327  * AP Debug Claim Tag Set Register
9328  * Used by software to set CLAIM bits to 1.
9329  */
9330 union bdk_ap_dbgclaimset_el1
9331 {
9332     uint32_t u;
9333     struct bdk_ap_dbgclaimset_el1_s
9334     {
9335 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9336         uint32_t reserved_8_31         : 24;
9337         uint32_t claim                 : 8;  /**< [  7:  0](R/W) Claim set bits. RAO.
9338                                                                  Writing a 1 to one of these bits sets the corresponding CLAIM
9339                                                                      bit to 1. This is an indirect write to the CLAIM bits.
9340                                                                  A single write operation can set multiple bits to 1. Writing 0
9341                                                                      to one of these bits has no effect. */
9342 #else /* Word 0 - Little Endian */
9343         uint32_t claim                 : 8;  /**< [  7:  0](R/W) Claim set bits. RAO.
9344                                                                  Writing a 1 to one of these bits sets the corresponding CLAIM
9345                                                                      bit to 1. This is an indirect write to the CLAIM bits.
9346                                                                  A single write operation can set multiple bits to 1. Writing 0
9347                                                                      to one of these bits has no effect. */
9348         uint32_t reserved_8_31         : 24;
9349 #endif /* Word 0 - End */
9350     } s;
9351     /* struct bdk_ap_dbgclaimset_el1_s cn; */
9352 };
9353 typedef union bdk_ap_dbgclaimset_el1 bdk_ap_dbgclaimset_el1_t;
9354 
9355 #define BDK_AP_DBGCLAIMSET_EL1 BDK_AP_DBGCLAIMSET_EL1_FUNC()
9356 static inline uint64_t BDK_AP_DBGCLAIMSET_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DBGCLAIMSET_EL1_FUNC(void)9357 static inline uint64_t BDK_AP_DBGCLAIMSET_EL1_FUNC(void)
9358 {
9359     return 0x20007080600ll;
9360 }
9361 
9362 #define typedef_BDK_AP_DBGCLAIMSET_EL1 bdk_ap_dbgclaimset_el1_t
9363 #define bustype_BDK_AP_DBGCLAIMSET_EL1 BDK_CSR_TYPE_SYSREG
9364 #define basename_BDK_AP_DBGCLAIMSET_EL1 "AP_DBGCLAIMSET_EL1"
9365 #define busnum_BDK_AP_DBGCLAIMSET_EL1 0
9366 #define arguments_BDK_AP_DBGCLAIMSET_EL1 -1,-1,-1,-1
9367 
9368 /**
9369  * Register (SYSREG) ap_dbgdtr_el0
9370  *
9371  * AP Debug Data Transfer Half-Duplex Register
9372  * Transfers 64 bits of data between the processor and an
9373  *     external host. Can transfer both ways using only a single
9374  *     register.
9375  */
9376 union bdk_ap_dbgdtr_el0
9377 {
9378     uint64_t u;
9379     struct bdk_ap_dbgdtr_el0_s
9380     {
9381 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9382         uint64_t highword              : 32; /**< [ 63: 32](R/W) Writes to this register set DTRRX to the value in this field.
9383                                                                      Reads from this register return the value of DTRTX. */
9384         uint64_t lowword               : 32; /**< [ 31:  0](R/W) Writes to this register set DTRTX to the value in this field.
9385                                                                      Reads from this register return the value of DTRRX. */
9386 #else /* Word 0 - Little Endian */
9387         uint64_t lowword               : 32; /**< [ 31:  0](R/W) Writes to this register set DTRTX to the value in this field.
9388                                                                      Reads from this register return the value of DTRRX. */
9389         uint64_t highword              : 32; /**< [ 63: 32](R/W) Writes to this register set DTRRX to the value in this field.
9390                                                                      Reads from this register return the value of DTRTX. */
9391 #endif /* Word 0 - End */
9392     } s;
9393     /* struct bdk_ap_dbgdtr_el0_s cn; */
9394 };
9395 typedef union bdk_ap_dbgdtr_el0 bdk_ap_dbgdtr_el0_t;
9396 
9397 #define BDK_AP_DBGDTR_EL0 BDK_AP_DBGDTR_EL0_FUNC()
9398 static inline uint64_t BDK_AP_DBGDTR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DBGDTR_EL0_FUNC(void)9399 static inline uint64_t BDK_AP_DBGDTR_EL0_FUNC(void)
9400 {
9401     return 0x20300040000ll;
9402 }
9403 
9404 #define typedef_BDK_AP_DBGDTR_EL0 bdk_ap_dbgdtr_el0_t
9405 #define bustype_BDK_AP_DBGDTR_EL0 BDK_CSR_TYPE_SYSREG
9406 #define basename_BDK_AP_DBGDTR_EL0 "AP_DBGDTR_EL0"
9407 #define busnum_BDK_AP_DBGDTR_EL0 0
9408 #define arguments_BDK_AP_DBGDTR_EL0 -1,-1,-1,-1
9409 
9410 /**
9411  * Register (SYSREG) ap_dbgdtrrx_el0
9412  *
9413  * AP Debug Data Transfer Receive Register
9414  * Transfers 32 bits of data from an external host to the
9415  *     processor.
9416  *
9417  * This register is at the same select as AP_DBGDTRTX_EL0.
9418  */
9419 union bdk_ap_dbgdtrrx_el0
9420 {
9421     uint32_t u;
9422     struct bdk_ap_dbgdtrrx_el0_s
9423     {
9424 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9425         uint32_t data                  : 32; /**< [ 31:  0](RO) Host to target data
9426                                                                  Host to target data. One word of data for transfer from the
9427                                                                      debug host to the debug target.
9428                                                                  For the full behavior of the Debug Communications Channel, see
9429                                                                      section 9 (The Debug Communications Channel and Instruction
9430                                                                      Transfer Register) in document PRD03-PRDC-010486. */
9431 #else /* Word 0 - Little Endian */
9432         uint32_t data                  : 32; /**< [ 31:  0](RO) Host to target data
9433                                                                  Host to target data. One word of data for transfer from the
9434                                                                      debug host to the debug target.
9435                                                                  For the full behavior of the Debug Communications Channel, see
9436                                                                      section 9 (The Debug Communications Channel and Instruction
9437                                                                      Transfer Register) in document PRD03-PRDC-010486. */
9438 #endif /* Word 0 - End */
9439     } s;
9440     /* struct bdk_ap_dbgdtrrx_el0_s cn; */
9441 };
9442 typedef union bdk_ap_dbgdtrrx_el0 bdk_ap_dbgdtrrx_el0_t;
9443 
9444 #define BDK_AP_DBGDTRRX_EL0 BDK_AP_DBGDTRRX_EL0_FUNC()
9445 static inline uint64_t BDK_AP_DBGDTRRX_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DBGDTRRX_EL0_FUNC(void)9446 static inline uint64_t BDK_AP_DBGDTRRX_EL0_FUNC(void)
9447 {
9448     return 0x20300050000ll;
9449 }
9450 
9451 #define typedef_BDK_AP_DBGDTRRX_EL0 bdk_ap_dbgdtrrx_el0_t
9452 #define bustype_BDK_AP_DBGDTRRX_EL0 BDK_CSR_TYPE_SYSREG
9453 #define basename_BDK_AP_DBGDTRRX_EL0 "AP_DBGDTRRX_EL0"
9454 #define busnum_BDK_AP_DBGDTRRX_EL0 0
9455 #define arguments_BDK_AP_DBGDTRRX_EL0 -1,-1,-1,-1
9456 
9457 /**
9458  * Register (SYSREG) ap_dbgdtrtx_el0
9459  *
9460  * AP Debug Data Transfer Transmit Register
9461  * Transfers 32 bits of data from the processor to an external
9462  *     host.
9463  *
9464  * This register is at the same select as AP_DBGDTRRX_EL0.
9465  */
9466 union bdk_ap_dbgdtrtx_el0
9467 {
9468     uint32_t u;
9469     struct bdk_ap_dbgdtrtx_el0_s
9470     {
9471 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9472         uint32_t data                  : 32; /**< [ 31:  0](RO) Target to host data. One word of data for transfer from the
9473                                                                      debug target to the debug host.
9474                                                                  For the full behavior of the Debug Communications Channel, see
9475                                                                      section 9 (The Debug Communications Channel and Instruction
9476                                                                      Transfer Register) in document PRD03-PRDC-010486. */
9477 #else /* Word 0 - Little Endian */
9478         uint32_t data                  : 32; /**< [ 31:  0](RO) Target to host data. One word of data for transfer from the
9479                                                                      debug target to the debug host.
9480                                                                  For the full behavior of the Debug Communications Channel, see
9481                                                                      section 9 (The Debug Communications Channel and Instruction
9482                                                                      Transfer Register) in document PRD03-PRDC-010486. */
9483 #endif /* Word 0 - End */
9484     } s;
9485     /* struct bdk_ap_dbgdtrtx_el0_s cn8; */
9486     struct bdk_ap_dbgdtrtx_el0_cn9
9487     {
9488 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9489         uint32_t data                  : 32; /**< [ 31:  0](WO) Target to host data. One word of data for transfer from the
9490                                                                      debug target to the debug host.
9491                                                                  For the full behavior of the Debug Communications Channel, see
9492                                                                      section 9 (The Debug Communications Channel and Instruction
9493                                                                      Transfer Register) in document PRD03-PRDC-010486. */
9494 #else /* Word 0 - Little Endian */
9495         uint32_t data                  : 32; /**< [ 31:  0](WO) Target to host data. One word of data for transfer from the
9496                                                                      debug target to the debug host.
9497                                                                  For the full behavior of the Debug Communications Channel, see
9498                                                                      section 9 (The Debug Communications Channel and Instruction
9499                                                                      Transfer Register) in document PRD03-PRDC-010486. */
9500 #endif /* Word 0 - End */
9501     } cn9;
9502 };
9503 typedef union bdk_ap_dbgdtrtx_el0 bdk_ap_dbgdtrtx_el0_t;
9504 
9505 #define BDK_AP_DBGDTRTX_EL0 BDK_AP_DBGDTRTX_EL0_FUNC()
9506 static inline uint64_t BDK_AP_DBGDTRTX_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DBGDTRTX_EL0_FUNC(void)9507 static inline uint64_t BDK_AP_DBGDTRTX_EL0_FUNC(void)
9508 {
9509     return 0x20300050010ll;
9510 }
9511 
9512 #define typedef_BDK_AP_DBGDTRTX_EL0 bdk_ap_dbgdtrtx_el0_t
9513 #define bustype_BDK_AP_DBGDTRTX_EL0 BDK_CSR_TYPE_SYSREG
9514 #define basename_BDK_AP_DBGDTRTX_EL0 "AP_DBGDTRTX_EL0"
9515 #define busnum_BDK_AP_DBGDTRTX_EL0 0
9516 #define arguments_BDK_AP_DBGDTRTX_EL0 -1,-1,-1,-1
9517 
9518 /**
9519  * Register (SYSREG) ap_dbgprcr_el1
9520  *
9521  * AP Debug Power Control Register
9522  * Controls behavior of processor on power-down request.
9523  */
9524 union bdk_ap_dbgprcr_el1
9525 {
9526     uint32_t u;
9527     struct bdk_ap_dbgprcr_el1_s
9528     {
9529 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9530         uint32_t reserved_1_31         : 31;
9531         uint32_t corenpdrq             : 1;  /**< [  0:  0](R/W) Core no powerdown request. Requests emulation of powerdown.
9532 
9533                                                                  0 = On a powerdown request, the system powers down the Core power
9534                                                                      domain.
9535                                                                  1 = On a powerdown request, the system emulates powerdown of the
9536                                                                      Core power domain. In this emulation mode the Core power
9537                                                                      domain is not actually powered down. */
9538 #else /* Word 0 - Little Endian */
9539         uint32_t corenpdrq             : 1;  /**< [  0:  0](R/W) Core no powerdown request. Requests emulation of powerdown.
9540 
9541                                                                  0 = On a powerdown request, the system powers down the Core power
9542                                                                      domain.
9543                                                                  1 = On a powerdown request, the system emulates powerdown of the
9544                                                                      Core power domain. In this emulation mode the Core power
9545                                                                      domain is not actually powered down. */
9546         uint32_t reserved_1_31         : 31;
9547 #endif /* Word 0 - End */
9548     } s;
9549     /* struct bdk_ap_dbgprcr_el1_s cn; */
9550 };
9551 typedef union bdk_ap_dbgprcr_el1 bdk_ap_dbgprcr_el1_t;
9552 
9553 #define BDK_AP_DBGPRCR_EL1 BDK_AP_DBGPRCR_EL1_FUNC()
9554 static inline uint64_t BDK_AP_DBGPRCR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DBGPRCR_EL1_FUNC(void)9555 static inline uint64_t BDK_AP_DBGPRCR_EL1_FUNC(void)
9556 {
9557     return 0x20001040400ll;
9558 }
9559 
9560 #define typedef_BDK_AP_DBGPRCR_EL1 bdk_ap_dbgprcr_el1_t
9561 #define bustype_BDK_AP_DBGPRCR_EL1 BDK_CSR_TYPE_SYSREG
9562 #define basename_BDK_AP_DBGPRCR_EL1 "AP_DBGPRCR_EL1"
9563 #define busnum_BDK_AP_DBGPRCR_EL1 0
9564 #define arguments_BDK_AP_DBGPRCR_EL1 -1,-1,-1,-1
9565 
9566 /**
9567  * Register (SYSREG) ap_dbgvcr32_el2
9568  *
9569  * AP Debug Vector Catch Register
9570  * Allows access to the AArch32 register DBGVCR from AArch64
9571  *     state only. Its value has no effect on execution in AArch64
9572  *     state.
9573  */
9574 union bdk_ap_dbgvcr32_el2
9575 {
9576     uint32_t u;
9577     struct bdk_ap_dbgvcr32_el2_s
9578     {
9579 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9580         uint32_t nsf                   : 1;  /**< [ 31: 31](R/W) FIQ vector catch enable in nonsecure state.
9581                                                                  The exception vector offset is 0x1C. */
9582         uint32_t nsi                   : 1;  /**< [ 30: 30](R/W) IRQ vector catch enable in nonsecure state.
9583                                                                  The exception vector offset is 0x18. */
9584         uint32_t reserved_29           : 1;
9585         uint32_t nsd                   : 1;  /**< [ 28: 28](R/W) Data Abort vector catch enable in nonsecure state.
9586                                                                  The exception vector offset is 0x10. */
9587         uint32_t nsp                   : 1;  /**< [ 27: 27](R/W) Prefetch Abort vector catch enable in nonsecure state.
9588                                                                  The exception vector offset is 0x0C. */
9589         uint32_t nss                   : 1;  /**< [ 26: 26](R/W) Supervisor Call (SVC) vector catch enable in nonsecure state.
9590                                                                  The exception vector offset is 0x08. */
9591         uint32_t nsu                   : 1;  /**< [ 25: 25](R/W) Undefined Instruction vector catch enable in nonsecure state.
9592                                                                  The exception vector offset is 0x04. */
9593         uint32_t reserved_8_24         : 17;
9594         uint32_t sf                    : 1;  /**< [  7:  7](R/W) FIQ vector catch enable in Secure state.
9595                                                                  The exception vector offset is 0x1C. */
9596         uint32_t si                    : 1;  /**< [  6:  6](R/W) IRQ vector catch enable in Secure state.
9597                                                                  The exception vector offset is 0x18. */
9598         uint32_t reserved_5            : 1;
9599         uint32_t sd                    : 1;  /**< [  4:  4](R/W) Data Abort vector catch enable in Secure state.
9600                                                                  The exception vector offset is 0x10. */
9601         uint32_t sp                    : 1;  /**< [  3:  3](R/W) Prefetch Abort vector catch enable in Secure state.
9602                                                                  The exception vector offset is 0x0C. */
9603         uint32_t ss                    : 1;  /**< [  2:  2](R/W) Supervisor Call (SVC) vector catch enable in Secure state.
9604                                                                  The exception vector offset is 0x08. */
9605         uint32_t su                    : 1;  /**< [  1:  1](R/W) Undefined Instruction vector catch enable in Secure state.
9606                                                                  The exception vector offset is 0x04. */
9607         uint32_t reserved_0            : 1;
9608 #else /* Word 0 - Little Endian */
9609         uint32_t reserved_0            : 1;
9610         uint32_t su                    : 1;  /**< [  1:  1](R/W) Undefined Instruction vector catch enable in Secure state.
9611                                                                  The exception vector offset is 0x04. */
9612         uint32_t ss                    : 1;  /**< [  2:  2](R/W) Supervisor Call (SVC) vector catch enable in Secure state.
9613                                                                  The exception vector offset is 0x08. */
9614         uint32_t sp                    : 1;  /**< [  3:  3](R/W) Prefetch Abort vector catch enable in Secure state.
9615                                                                  The exception vector offset is 0x0C. */
9616         uint32_t sd                    : 1;  /**< [  4:  4](R/W) Data Abort vector catch enable in Secure state.
9617                                                                  The exception vector offset is 0x10. */
9618         uint32_t reserved_5            : 1;
9619         uint32_t si                    : 1;  /**< [  6:  6](R/W) IRQ vector catch enable in Secure state.
9620                                                                  The exception vector offset is 0x18. */
9621         uint32_t sf                    : 1;  /**< [  7:  7](R/W) FIQ vector catch enable in Secure state.
9622                                                                  The exception vector offset is 0x1C. */
9623         uint32_t reserved_8_24         : 17;
9624         uint32_t nsu                   : 1;  /**< [ 25: 25](R/W) Undefined Instruction vector catch enable in nonsecure state.
9625                                                                  The exception vector offset is 0x04. */
9626         uint32_t nss                   : 1;  /**< [ 26: 26](R/W) Supervisor Call (SVC) vector catch enable in nonsecure state.
9627                                                                  The exception vector offset is 0x08. */
9628         uint32_t nsp                   : 1;  /**< [ 27: 27](R/W) Prefetch Abort vector catch enable in nonsecure state.
9629                                                                  The exception vector offset is 0x0C. */
9630         uint32_t nsd                   : 1;  /**< [ 28: 28](R/W) Data Abort vector catch enable in nonsecure state.
9631                                                                  The exception vector offset is 0x10. */
9632         uint32_t reserved_29           : 1;
9633         uint32_t nsi                   : 1;  /**< [ 30: 30](R/W) IRQ vector catch enable in nonsecure state.
9634                                                                  The exception vector offset is 0x18. */
9635         uint32_t nsf                   : 1;  /**< [ 31: 31](R/W) FIQ vector catch enable in nonsecure state.
9636                                                                  The exception vector offset is 0x1C. */
9637 #endif /* Word 0 - End */
9638     } s;
9639     /* struct bdk_ap_dbgvcr32_el2_s cn8; */
9640     struct bdk_ap_dbgvcr32_el2_cn9
9641     {
9642 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9643         uint32_t nsf                   : 1;  /**< [ 31: 31](RAZ) FIQ vector catch enable in nonsecure state.
9644                                                                  The exception vector offset is 0x1C. */
9645         uint32_t nsi                   : 1;  /**< [ 30: 30](RAZ) IRQ vector catch enable in nonsecure state.
9646                                                                  The exception vector offset is 0x18. */
9647         uint32_t reserved_29           : 1;
9648         uint32_t nsd                   : 1;  /**< [ 28: 28](RAZ) Data Abort vector catch enable in nonsecure state.
9649                                                                  The exception vector offset is 0x10. */
9650         uint32_t nsp                   : 1;  /**< [ 27: 27](RAZ) Prefetch Abort vector catch enable in nonsecure state.
9651                                                                  The exception vector offset is 0x0C. */
9652         uint32_t nss                   : 1;  /**< [ 26: 26](RAZ) Supervisor Call (SVC) vector catch enable in nonsecure state.
9653                                                                  The exception vector offset is 0x08. */
9654         uint32_t nsu                   : 1;  /**< [ 25: 25](RAZ) Undefined Instruction vector catch enable in nonsecure state.
9655                                                                  The exception vector offset is 0x04. */
9656         uint32_t reserved_8_24         : 17;
9657         uint32_t sf                    : 1;  /**< [  7:  7](RAZ) FIQ vector catch enable in Secure state.
9658                                                                  The exception vector offset is 0x1C. */
9659         uint32_t si                    : 1;  /**< [  6:  6](RAZ) IRQ vector catch enable in Secure state.
9660                                                                  The exception vector offset is 0x18. */
9661         uint32_t reserved_5            : 1;
9662         uint32_t sd                    : 1;  /**< [  4:  4](RAZ) Data Abort vector catch enable in Secure state.
9663                                                                  The exception vector offset is 0x10. */
9664         uint32_t sp                    : 1;  /**< [  3:  3](RAZ) Prefetch Abort vector catch enable in Secure state.
9665                                                                  The exception vector offset is 0x0C. */
9666         uint32_t ss                    : 1;  /**< [  2:  2](RAZ) Supervisor Call (SVC) vector catch enable in Secure state.
9667                                                                  The exception vector offset is 0x08. */
9668         uint32_t su                    : 1;  /**< [  1:  1](RAZ) Undefined Instruction vector catch enable in Secure state.
9669                                                                  The exception vector offset is 0x04. */
9670         uint32_t reserved_0            : 1;
9671 #else /* Word 0 - Little Endian */
9672         uint32_t reserved_0            : 1;
9673         uint32_t su                    : 1;  /**< [  1:  1](RAZ) Undefined Instruction vector catch enable in Secure state.
9674                                                                  The exception vector offset is 0x04. */
9675         uint32_t ss                    : 1;  /**< [  2:  2](RAZ) Supervisor Call (SVC) vector catch enable in Secure state.
9676                                                                  The exception vector offset is 0x08. */
9677         uint32_t sp                    : 1;  /**< [  3:  3](RAZ) Prefetch Abort vector catch enable in Secure state.
9678                                                                  The exception vector offset is 0x0C. */
9679         uint32_t sd                    : 1;  /**< [  4:  4](RAZ) Data Abort vector catch enable in Secure state.
9680                                                                  The exception vector offset is 0x10. */
9681         uint32_t reserved_5            : 1;
9682         uint32_t si                    : 1;  /**< [  6:  6](RAZ) IRQ vector catch enable in Secure state.
9683                                                                  The exception vector offset is 0x18. */
9684         uint32_t sf                    : 1;  /**< [  7:  7](RAZ) FIQ vector catch enable in Secure state.
9685                                                                  The exception vector offset is 0x1C. */
9686         uint32_t reserved_8_24         : 17;
9687         uint32_t nsu                   : 1;  /**< [ 25: 25](RAZ) Undefined Instruction vector catch enable in nonsecure state.
9688                                                                  The exception vector offset is 0x04. */
9689         uint32_t nss                   : 1;  /**< [ 26: 26](RAZ) Supervisor Call (SVC) vector catch enable in nonsecure state.
9690                                                                  The exception vector offset is 0x08. */
9691         uint32_t nsp                   : 1;  /**< [ 27: 27](RAZ) Prefetch Abort vector catch enable in nonsecure state.
9692                                                                  The exception vector offset is 0x0C. */
9693         uint32_t nsd                   : 1;  /**< [ 28: 28](RAZ) Data Abort vector catch enable in nonsecure state.
9694                                                                  The exception vector offset is 0x10. */
9695         uint32_t reserved_29           : 1;
9696         uint32_t nsi                   : 1;  /**< [ 30: 30](RAZ) IRQ vector catch enable in nonsecure state.
9697                                                                  The exception vector offset is 0x18. */
9698         uint32_t nsf                   : 1;  /**< [ 31: 31](RAZ) FIQ vector catch enable in nonsecure state.
9699                                                                  The exception vector offset is 0x1C. */
9700 #endif /* Word 0 - End */
9701     } cn9;
9702 };
9703 typedef union bdk_ap_dbgvcr32_el2 bdk_ap_dbgvcr32_el2_t;
9704 
9705 #define BDK_AP_DBGVCR32_EL2 BDK_AP_DBGVCR32_EL2_FUNC()
9706 static inline uint64_t BDK_AP_DBGVCR32_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DBGVCR32_EL2_FUNC(void)9707 static inline uint64_t BDK_AP_DBGVCR32_EL2_FUNC(void)
9708 {
9709     return 0x20400070000ll;
9710 }
9711 
9712 #define typedef_BDK_AP_DBGVCR32_EL2 bdk_ap_dbgvcr32_el2_t
9713 #define bustype_BDK_AP_DBGVCR32_EL2 BDK_CSR_TYPE_SYSREG
9714 #define basename_BDK_AP_DBGVCR32_EL2 "AP_DBGVCR32_EL2"
9715 #define busnum_BDK_AP_DBGVCR32_EL2 0
9716 #define arguments_BDK_AP_DBGVCR32_EL2 -1,-1,-1,-1
9717 
9718 /**
9719  * Register (SYSREG) ap_dbgwcr#_el1
9720  *
9721  * AP Debug Watchpoint Control Registers
9722  * Holds control information for a watchpoint. Forms watchpoint n
9723  *     together with value register DBGWVR\<n\>_EL1, where n is 0 to
9724  *     15.
9725  */
9726 union bdk_ap_dbgwcrx_el1
9727 {
9728     uint32_t u;
9729     struct bdk_ap_dbgwcrx_el1_s
9730     {
9731 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9732         uint32_t reserved_29_31        : 3;
9733         uint32_t mask                  : 5;  /**< [ 28: 24](R/W) Address mask. Only objects up to 2GB can be watched using a
9734                                                                      single mask.
9735                                                                  Other values mask the corresponding number of address bits.
9736 
9737                                                                  0x0 = No mask.
9738                                                                  0x1 = Reserved.
9739                                                                  0x2 = Reserved. */
9740         uint32_t reserved_21_23        : 3;
9741         uint32_t wt                    : 1;  /**< [ 20: 20](R/W) Watchpoint type.
9742                                                                  0 = Unlinked data address match.
9743                                                                  1 = Linked data address match. */
9744         uint32_t lbn                   : 4;  /**< [ 19: 16](R/W) Linked breakpoint number. For Linked data address watchpoints,
9745                                                                      this specifies the index of the Context-matching breakpoint
9746                                                                      linked to. */
9747         uint32_t ssc                   : 2;  /**< [ 15: 14](R/W) Security state control. Determines the Security states under
9748                                                                      which a watchpoint debug event for watchpoint n is generated.
9749                                                                      This field must be interpreted along with the HMC and PAC
9750                                                                      fields. */
9751         uint32_t hmc                   : 1;  /**< [ 13: 13](R/W) Higher mode control. Determines the debug perspective for
9752                                                                      deciding when a watchpoint debug event for watchpoint n is
9753                                                                      generated. This field must be interpreted along with the SSC
9754                                                                      and PAC fields. */
9755         uint32_t bas                   : 8;  /**< [ 12:  5](R/W) Byte address select. Each bit of this field selects whether a
9756                                                                      byte from within the word or double-word addressed by
9757                                                                      DBGWVR\<n\>_EL1 is being watched.
9758 
9759                                                                  xxxxxxx1    Match byte at DBGWVR\<n\>_EL1
9760                                                                  xxxxxx1x    Match byte at DBGWVR\<n\>_EL1+1
9761                                                                  xxxxx1xx    Match byte at DBGWVR\<n\>_EL1+2
9762                                                                  xxxx1xxx    Match byte at DBGWVR\<n\>_EL1+3
9763 
9764                                                                  In cases where DBGWVR\<n\>_EL1 addresses a double-word:
9765                                                                  BAS Description, if DBGWVR\<n\>_EL1[2] == 0
9766 
9767                                                                  xxx1xxxx    Match byte at DBGWVR\<n\>_EL1+4
9768                                                                  xx1xxxxx    Match byte at DBGWVR\<n\>_EL1+5
9769                                                                  x1xxxxxx    Match byte at DBGWVR\<n\>_EL1+6
9770                                                                  1xxxxxxx    Match byte at DBGWVR\<n\>_EL1+7
9771 
9772                                                                  If DBGWVR\<n\>_EL1[2] == 1, only BAS[3:0] is used. ARM
9773                                                                      deprecates setting DBGWVR\<n\>_EL1 == 1.
9774                                                                  If BAS is zero, no bytes are watched by this watchpoint.
9775                                                                  Ignored if E is 0. */
9776         uint32_t lsc                   : 2;  /**< [  4:  3](R/W) Load/store control. This field enables watchpoint matching on
9777                                                                      the type of access being made.
9778                                                                  All other values are reserved, but must behave as if the
9779                                                                      watchpoint is disabled. Software must not rely on this
9780                                                                      property as the behavior of reserved values might change in a
9781                                                                      future revision of the architecture.
9782                                                                  Ignored if E is 0.
9783                                                                  0x1 = Match instructions that load from a watchpointed address.
9784                                                                  0x2 = Match instructions that store to a watchpointed address.
9785                                                                  0x3 = Match instructions that load from or store to a watchpointed
9786                                                                      address. */
9787         uint32_t pac                   : 2;  /**< [  2:  1](R/W) Privilege of access control. Determines the Exception level or
9788                                                                      levels at which a watchpoint debug event for watchpoint n is
9789                                                                      generated. This field must be interpreted along with the SSC
9790                                                                      and HMC fields. */
9791         uint32_t ee                    : 1;  /**< [  0:  0](R/W) Enable watchpoint n.
9792                                                                  0 = Watchpoint disabled.
9793                                                                  1 = Watchpoint enabled. */
9794 #else /* Word 0 - Little Endian */
9795         uint32_t ee                    : 1;  /**< [  0:  0](R/W) Enable watchpoint n.
9796                                                                  0 = Watchpoint disabled.
9797                                                                  1 = Watchpoint enabled. */
9798         uint32_t pac                   : 2;  /**< [  2:  1](R/W) Privilege of access control. Determines the Exception level or
9799                                                                      levels at which a watchpoint debug event for watchpoint n is
9800                                                                      generated. This field must be interpreted along with the SSC
9801                                                                      and HMC fields. */
9802         uint32_t lsc                   : 2;  /**< [  4:  3](R/W) Load/store control. This field enables watchpoint matching on
9803                                                                      the type of access being made.
9804                                                                  All other values are reserved, but must behave as if the
9805                                                                      watchpoint is disabled. Software must not rely on this
9806                                                                      property as the behavior of reserved values might change in a
9807                                                                      future revision of the architecture.
9808                                                                  Ignored if E is 0.
9809                                                                  0x1 = Match instructions that load from a watchpointed address.
9810                                                                  0x2 = Match instructions that store to a watchpointed address.
9811                                                                  0x3 = Match instructions that load from or store to a watchpointed
9812                                                                      address. */
9813         uint32_t bas                   : 8;  /**< [ 12:  5](R/W) Byte address select. Each bit of this field selects whether a
9814                                                                      byte from within the word or double-word addressed by
9815                                                                      DBGWVR\<n\>_EL1 is being watched.
9816 
9817                                                                  xxxxxxx1    Match byte at DBGWVR\<n\>_EL1
9818                                                                  xxxxxx1x    Match byte at DBGWVR\<n\>_EL1+1
9819                                                                  xxxxx1xx    Match byte at DBGWVR\<n\>_EL1+2
9820                                                                  xxxx1xxx    Match byte at DBGWVR\<n\>_EL1+3
9821 
9822                                                                  In cases where DBGWVR\<n\>_EL1 addresses a double-word:
9823                                                                  BAS Description, if DBGWVR\<n\>_EL1[2] == 0
9824 
9825                                                                  xxx1xxxx    Match byte at DBGWVR\<n\>_EL1+4
9826                                                                  xx1xxxxx    Match byte at DBGWVR\<n\>_EL1+5
9827                                                                  x1xxxxxx    Match byte at DBGWVR\<n\>_EL1+6
9828                                                                  1xxxxxxx    Match byte at DBGWVR\<n\>_EL1+7
9829 
9830                                                                  If DBGWVR\<n\>_EL1[2] == 1, only BAS[3:0] is used. ARM
9831                                                                      deprecates setting DBGWVR\<n\>_EL1 == 1.
9832                                                                  If BAS is zero, no bytes are watched by this watchpoint.
9833                                                                  Ignored if E is 0. */
9834         uint32_t hmc                   : 1;  /**< [ 13: 13](R/W) Higher mode control. Determines the debug perspective for
9835                                                                      deciding when a watchpoint debug event for watchpoint n is
9836                                                                      generated. This field must be interpreted along with the SSC
9837                                                                      and PAC fields. */
9838         uint32_t ssc                   : 2;  /**< [ 15: 14](R/W) Security state control. Determines the Security states under
9839                                                                      which a watchpoint debug event for watchpoint n is generated.
9840                                                                      This field must be interpreted along with the HMC and PAC
9841                                                                      fields. */
9842         uint32_t lbn                   : 4;  /**< [ 19: 16](R/W) Linked breakpoint number. For Linked data address watchpoints,
9843                                                                      this specifies the index of the Context-matching breakpoint
9844                                                                      linked to. */
9845         uint32_t wt                    : 1;  /**< [ 20: 20](R/W) Watchpoint type.
9846                                                                  0 = Unlinked data address match.
9847                                                                  1 = Linked data address match. */
9848         uint32_t reserved_21_23        : 3;
9849         uint32_t mask                  : 5;  /**< [ 28: 24](R/W) Address mask. Only objects up to 2GB can be watched using a
9850                                                                      single mask.
9851                                                                  Other values mask the corresponding number of address bits.
9852 
9853                                                                  0x0 = No mask.
9854                                                                  0x1 = Reserved.
9855                                                                  0x2 = Reserved. */
9856         uint32_t reserved_29_31        : 3;
9857 #endif /* Word 0 - End */
9858     } s;
9859     /* struct bdk_ap_dbgwcrx_el1_s cn; */
9860 };
9861 typedef union bdk_ap_dbgwcrx_el1 bdk_ap_dbgwcrx_el1_t;
9862 
9863 static inline uint64_t BDK_AP_DBGWCRX_EL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_DBGWCRX_EL1(unsigned long a)9864 static inline uint64_t BDK_AP_DBGWCRX_EL1(unsigned long a)
9865 {
9866     if (a<=15)
9867         return 0x20000000700ll + 0x10000ll * ((a) & 0xf);
9868     __bdk_csr_fatal("AP_DBGWCRX_EL1", 1, a, 0, 0, 0);
9869 }
9870 
9871 #define typedef_BDK_AP_DBGWCRX_EL1(a) bdk_ap_dbgwcrx_el1_t
9872 #define bustype_BDK_AP_DBGWCRX_EL1(a) BDK_CSR_TYPE_SYSREG
9873 #define basename_BDK_AP_DBGWCRX_EL1(a) "AP_DBGWCRX_EL1"
9874 #define busnum_BDK_AP_DBGWCRX_EL1(a) (a)
9875 #define arguments_BDK_AP_DBGWCRX_EL1(a) (a),-1,-1,-1
9876 
9877 /**
9878  * Register (SYSREG) ap_dbgwvr#_el1
9879  *
9880  * AP Debug Watchpoint Value Registers
9881  * Holds a data address value for use in watchpoint matching.
9882  *     Forms watchpoint n together with control register
9883  *     DBGWCR\<n\>_EL1, where n is 0 to 15.
9884  */
9885 union bdk_ap_dbgwvrx_el1
9886 {
9887     uint64_t u;
9888     struct bdk_ap_dbgwvrx_el1_s
9889     {
9890 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9891         uint64_t reserved_0_63         : 64;
9892 #else /* Word 0 - Little Endian */
9893         uint64_t reserved_0_63         : 64;
9894 #endif /* Word 0 - End */
9895     } s;
9896     struct bdk_ap_dbgwvrx_el1_cn8
9897     {
9898 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9899         uint64_t ress                  : 15; /**< [ 63: 49](R/W) Reserved, Sign extended. Hardwired to the value of the sign
9900                                                                      bit, bit [48]. Hardware and software must treat this field as
9901                                                                      RES0 if bit[48] is 0, and as RES1 if bit[48] is 1. */
9902         uint64_t va                    : 47; /**< [ 48:  2](R/W) Bits[48:2] of the address value for comparison.
9903                                                                  ARM deprecates setting DBGWVR\<n\>_EL1[2] == 1. */
9904         uint64_t reserved_0_1          : 2;
9905 #else /* Word 0 - Little Endian */
9906         uint64_t reserved_0_1          : 2;
9907         uint64_t va                    : 47; /**< [ 48:  2](R/W) Bits[48:2] of the address value for comparison.
9908                                                                  ARM deprecates setting DBGWVR\<n\>_EL1[2] == 1. */
9909         uint64_t ress                  : 15; /**< [ 63: 49](R/W) Reserved, Sign extended. Hardwired to the value of the sign
9910                                                                      bit, bit [48]. Hardware and software must treat this field as
9911                                                                      RES0 if bit[48] is 0, and as RES1 if bit[48] is 1. */
9912 #endif /* Word 0 - End */
9913     } cn8;
9914     struct bdk_ap_dbgwvrx_el1_cn9
9915     {
9916 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9917         uint64_t ress                  : 11; /**< [ 63: 53](R/W) Reserved, Sign extended. Hardwired to the value of the sign
9918                                                                      bit, bit [52]. Hardware and software must treat this field as
9919                                                                      RES0 if bit[52] is 0, and as RES1 if bit[52] is 1. */
9920         uint64_t va                    : 51; /**< [ 52:  2](R/W) Bits[52:2] of the address value for comparison.
9921                                                                  ARM deprecates setting DBGWVR\<n\>_EL1[2] == 1. */
9922         uint64_t reserved_0_1          : 2;
9923 #else /* Word 0 - Little Endian */
9924         uint64_t reserved_0_1          : 2;
9925         uint64_t va                    : 51; /**< [ 52:  2](R/W) Bits[52:2] of the address value for comparison.
9926                                                                  ARM deprecates setting DBGWVR\<n\>_EL1[2] == 1. */
9927         uint64_t ress                  : 11; /**< [ 63: 53](R/W) Reserved, Sign extended. Hardwired to the value of the sign
9928                                                                      bit, bit [52]. Hardware and software must treat this field as
9929                                                                      RES0 if bit[52] is 0, and as RES1 if bit[52] is 1. */
9930 #endif /* Word 0 - End */
9931     } cn9;
9932 };
9933 typedef union bdk_ap_dbgwvrx_el1 bdk_ap_dbgwvrx_el1_t;
9934 
9935 static inline uint64_t BDK_AP_DBGWVRX_EL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_DBGWVRX_EL1(unsigned long a)9936 static inline uint64_t BDK_AP_DBGWVRX_EL1(unsigned long a)
9937 {
9938     if (a<=15)
9939         return 0x20000000600ll + 0x10000ll * ((a) & 0xf);
9940     __bdk_csr_fatal("AP_DBGWVRX_EL1", 1, a, 0, 0, 0);
9941 }
9942 
9943 #define typedef_BDK_AP_DBGWVRX_EL1(a) bdk_ap_dbgwvrx_el1_t
9944 #define bustype_BDK_AP_DBGWVRX_EL1(a) BDK_CSR_TYPE_SYSREG
9945 #define basename_BDK_AP_DBGWVRX_EL1(a) "AP_DBGWVRX_EL1"
9946 #define busnum_BDK_AP_DBGWVRX_EL1(a) (a)
9947 #define arguments_BDK_AP_DBGWVRX_EL1(a) (a),-1,-1,-1
9948 
9949 /**
9950  * Register (SYSREG) ap_dczid_el0
9951  *
9952  * AP Data Cache Zero ID Register
9953  * This register indicates the block size that is written with byte values of 0 by the
9954  * DC ZVA (Data Cache Zero by Address) system instruction.
9955  */
9956 union bdk_ap_dczid_el0
9957 {
9958     uint32_t u;
9959     struct bdk_ap_dczid_el0_s
9960     {
9961 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
9962         uint32_t reserved_5_31         : 27;
9963         uint32_t dzp                   : 1;  /**< [  4:  4](RO) Data Zero prohibited.
9964                                                                  The value read from this field is governed by the access state
9965                                                                      and the values of the AP_HCR_EL2[TDZ] and AP_SCTLR_EL1[DZE] bits.
9966                                                                  0 =  DC ZVA instruction is permitted.
9967                                                                  1 =  DC ZVA instruction is prohibited. */
9968         uint32_t bs                    : 4;  /**< [  3:  0](RO) Log2 of the block size in words. The maximum size supported is 2KB (value == 9).
9969 
9970                                                                  In CNXXXX, 128 bytes. */
9971 #else /* Word 0 - Little Endian */
9972         uint32_t bs                    : 4;  /**< [  3:  0](RO) Log2 of the block size in words. The maximum size supported is 2KB (value == 9).
9973 
9974                                                                  In CNXXXX, 128 bytes. */
9975         uint32_t dzp                   : 1;  /**< [  4:  4](RO) Data Zero prohibited.
9976                                                                  The value read from this field is governed by the access state
9977                                                                      and the values of the AP_HCR_EL2[TDZ] and AP_SCTLR_EL1[DZE] bits.
9978                                                                  0 =  DC ZVA instruction is permitted.
9979                                                                  1 =  DC ZVA instruction is prohibited. */
9980         uint32_t reserved_5_31         : 27;
9981 #endif /* Word 0 - End */
9982     } s;
9983     /* struct bdk_ap_dczid_el0_s cn; */
9984 };
9985 typedef union bdk_ap_dczid_el0 bdk_ap_dczid_el0_t;
9986 
9987 #define BDK_AP_DCZID_EL0 BDK_AP_DCZID_EL0_FUNC()
9988 static inline uint64_t BDK_AP_DCZID_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DCZID_EL0_FUNC(void)9989 static inline uint64_t BDK_AP_DCZID_EL0_FUNC(void)
9990 {
9991     return 0x30300000700ll;
9992 }
9993 
9994 #define typedef_BDK_AP_DCZID_EL0 bdk_ap_dczid_el0_t
9995 #define bustype_BDK_AP_DCZID_EL0 BDK_CSR_TYPE_SYSREG
9996 #define basename_BDK_AP_DCZID_EL0 "AP_DCZID_EL0"
9997 #define busnum_BDK_AP_DCZID_EL0 0
9998 #define arguments_BDK_AP_DCZID_EL0 -1,-1,-1,-1
9999 
10000 /**
10001  * Register (SYSREG) ap_disr_el1
10002  *
10003  * AP Deferred Interrupt Status Register
10004  * Records that an SError interrupt has been consumed by an ESB instruction.
10005  *
10006  * Usage constraints:
10007  *   DISR_EL1 is UNDEFINED at EL0.
10008  *   Direct reads and writes of DISR_EL1:
10009  *     - If EL2 is implemented and HCR_EL2.AMO is set to 1 access VDISR_EL2 at Non-secure EL1.
10010  *     - If EL3 is implemented and SCR_EL3.EA == 1, are RAZ/WI at EL2, Secure EL1, and, if they
10011  * do not access VDISR_EL2, Non-secure EL1.
10012  *   An indirect write to DISR_EL1 made by an ESB instruction does not require an explicit
10013  * synchronization operation for the value written to be observed by a direct read of DISR_EL1
10014  * occurring in program order after the ESB.
10015  */
10016 union bdk_ap_disr_el1
10017 {
10018     uint64_t u;
10019     struct bdk_ap_disr_el1_s
10020     {
10021 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10022         uint64_t reserved_32_63        : 32;
10023         uint64_t aa                    : 1;  /**< [ 31: 31](R/W) Set to 1 when ESB defers an asynchronous SError interrupt. If the implementation does not
10024                                                                  include any synchronizable sources of SError interrupt, this bit is RES0. */
10025         uint64_t reserved_25_30        : 6;
10026         uint64_t ids                   : 1;  /**< [ 24: 24](R/W) Indicates whether the deferred SError interrupt was of an implementation defined type.
10027                                                                    0 = Deferred error uses architecturally-defined format.
10028                                                                    1 = Deferred error uses implementation defined format.  ISS, bits [23:0], when
10029                                                                    IDS = 1 contain an implementation defined SError interrupt syndrome. See the
10030                                                                    description of ESR_ELx[23:0] for an SError interrupt. */
10031         uint64_t reserved_13_23        : 11;
10032         uint64_t aet                   : 3;  /**< [ 12: 10](R/W) Asynchronous error type. See the description of ESR_ELx.AET for an SError interrupt. */
10033         uint64_t ea                    : 1;  /**< [  9:  9](R/W) External abort type. See the description of ESR_ELx.EA for an SError interrupt. */
10034         uint64_t reserved_6_8          : 3;
10035         uint64_t dfsc                  : 6;  /**< [  5:  0](R/W) Fault status code. See the description of ESR_ELx.DFSC for an SError interrupt. */
10036 #else /* Word 0 - Little Endian */
10037         uint64_t dfsc                  : 6;  /**< [  5:  0](R/W) Fault status code. See the description of ESR_ELx.DFSC for an SError interrupt. */
10038         uint64_t reserved_6_8          : 3;
10039         uint64_t ea                    : 1;  /**< [  9:  9](R/W) External abort type. See the description of ESR_ELx.EA for an SError interrupt. */
10040         uint64_t aet                   : 3;  /**< [ 12: 10](R/W) Asynchronous error type. See the description of ESR_ELx.AET for an SError interrupt. */
10041         uint64_t reserved_13_23        : 11;
10042         uint64_t ids                   : 1;  /**< [ 24: 24](R/W) Indicates whether the deferred SError interrupt was of an implementation defined type.
10043                                                                    0 = Deferred error uses architecturally-defined format.
10044                                                                    1 = Deferred error uses implementation defined format.  ISS, bits [23:0], when
10045                                                                    IDS = 1 contain an implementation defined SError interrupt syndrome. See the
10046                                                                    description of ESR_ELx[23:0] for an SError interrupt. */
10047         uint64_t reserved_25_30        : 6;
10048         uint64_t aa                    : 1;  /**< [ 31: 31](R/W) Set to 1 when ESB defers an asynchronous SError interrupt. If the implementation does not
10049                                                                  include any synchronizable sources of SError interrupt, this bit is RES0. */
10050         uint64_t reserved_32_63        : 32;
10051 #endif /* Word 0 - End */
10052     } s;
10053     /* struct bdk_ap_disr_el1_s cn; */
10054 };
10055 typedef union bdk_ap_disr_el1 bdk_ap_disr_el1_t;
10056 
10057 #define BDK_AP_DISR_EL1 BDK_AP_DISR_EL1_FUNC()
10058 static inline uint64_t BDK_AP_DISR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DISR_EL1_FUNC(void)10059 static inline uint64_t BDK_AP_DISR_EL1_FUNC(void)
10060 {
10061     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
10062         return 0x3000c010100ll;
10063     __bdk_csr_fatal("AP_DISR_EL1", 0, 0, 0, 0, 0);
10064 }
10065 
10066 #define typedef_BDK_AP_DISR_EL1 bdk_ap_disr_el1_t
10067 #define bustype_BDK_AP_DISR_EL1 BDK_CSR_TYPE_SYSREG
10068 #define basename_BDK_AP_DISR_EL1 "AP_DISR_EL1"
10069 #define busnum_BDK_AP_DISR_EL1 0
10070 #define arguments_BDK_AP_DISR_EL1 -1,-1,-1,-1
10071 
10072 /**
10073  * Register (SYSREG) ap_dlr_el0
10074  *
10075  * AP Debug Link Register
10076  * In Debug state, holds the address to restart from.
10077  */
10078 union bdk_ap_dlr_el0
10079 {
10080     uint64_t u;
10081     struct bdk_ap_dlr_el0_s
10082     {
10083 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10084         uint64_t data                  : 64; /**< [ 63:  0](R/W) Restart address. */
10085 #else /* Word 0 - Little Endian */
10086         uint64_t data                  : 64; /**< [ 63:  0](R/W) Restart address. */
10087 #endif /* Word 0 - End */
10088     } s;
10089     /* struct bdk_ap_dlr_el0_s cn; */
10090 };
10091 typedef union bdk_ap_dlr_el0 bdk_ap_dlr_el0_t;
10092 
10093 #define BDK_AP_DLR_EL0 BDK_AP_DLR_EL0_FUNC()
10094 static inline uint64_t BDK_AP_DLR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DLR_EL0_FUNC(void)10095 static inline uint64_t BDK_AP_DLR_EL0_FUNC(void)
10096 {
10097     return 0x30304050100ll;
10098 }
10099 
10100 #define typedef_BDK_AP_DLR_EL0 bdk_ap_dlr_el0_t
10101 #define bustype_BDK_AP_DLR_EL0 BDK_CSR_TYPE_SYSREG
10102 #define basename_BDK_AP_DLR_EL0 "AP_DLR_EL0"
10103 #define busnum_BDK_AP_DLR_EL0 0
10104 #define arguments_BDK_AP_DLR_EL0 -1,-1,-1,-1
10105 
10106 /**
10107  * Register (SYSREG) ap_dspsr_el0
10108  *
10109  * AP Debug Saved Program Status Register
10110  * Holds the saved processor state on entry to debug state.
10111  */
10112 union bdk_ap_dspsr_el0
10113 {
10114     uint32_t u;
10115     struct bdk_ap_dspsr_el0_s
10116     {
10117 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10118         uint32_t n                     : 1;  /**< [ 31: 31](R/W) Set to the value of CPSR[N] on entering Debug state, and copied
10119                                                                      to CPSR[N] on exiting Debug state. */
10120         uint32_t z                     : 1;  /**< [ 30: 30](R/W) Set to the value of CPSR[Z] on entering Debug state, and copied
10121                                                                      to CPSR[Z] on exiting Debug state. */
10122         uint32_t cc                    : 1;  /**< [ 29: 29](R/W) Set to the value of CPSR[C] on entering Debug state, and copied
10123                                                                      to CPSR[C] on exiting Debug state. */
10124         uint32_t v                     : 1;  /**< [ 28: 28](R/W) Set to the value of CPSR[V] on entering Debug state, and copied
10125                                                                      to CPSR[V] on exiting Debug state. */
10126         uint32_t reserved_24_27        : 4;
10127         uint32_t uao                   : 1;  /**< [ 23: 23](R/W) User access override. */
10128         uint32_t reserved_22           : 1;
10129         uint32_t ss                    : 1;  /**< [ 21: 21](R/W) Software step. Indicates whether software step was enabled when
10130                                                                  Debug state was entered. */
10131         uint32_t il                    : 1;  /**< [ 20: 20](R/W) Illegal Execution State bit. Shows the value of PSTATE[IL]
10132                                                                      immediately before Debug state was entered. */
10133         uint32_t reserved_10_19        : 10;
10134         uint32_t dd                    : 1;  /**< [  9:  9](R/W) Interrupt masks - can also be accessed as PSTATE.[D,A,I,F] */
10135         uint32_t aa                    : 1;  /**< [  8:  8](R/W) Asynchronous data abort mask bit.
10136                                                                  0 = Exception not masked.
10137                                                                  1 = Exception masked. */
10138         uint32_t i                     : 1;  /**< [  7:  7](R/W) IRQ mask bit.
10139                                                                  0 = Exception not masked.
10140                                                                  1 = Exception masked. */
10141         uint32_t f                     : 1;  /**< [  6:  6](R/W) FIQ mask bit.
10142                                                                  0 = Exception not masked.
10143                                                                  1 = Exception masked. */
10144         uint32_t reserved_5            : 1;
10145         uint32_t nrw                   : 1;  /**< [  4:  4](R/W) Current register width:  0 = AArch64, 1 = AArch32. */
10146         uint32_t el                    : 2;  /**< [  3:  2](R/W) Current exception level: 0x0 = EL0, 0x1 = EL1, 0x2 = EL2, 0x3 = EL3. */
10147         uint32_t reserved_1            : 1;
10148         uint32_t sp                    : 1;  /**< [  0:  0](R/W) AArch64 only - Stack Pointer selection - 0 - SP0, 1 - SPx. */
10149 #else /* Word 0 - Little Endian */
10150         uint32_t sp                    : 1;  /**< [  0:  0](R/W) AArch64 only - Stack Pointer selection - 0 - SP0, 1 - SPx. */
10151         uint32_t reserved_1            : 1;
10152         uint32_t el                    : 2;  /**< [  3:  2](R/W) Current exception level: 0x0 = EL0, 0x1 = EL1, 0x2 = EL2, 0x3 = EL3. */
10153         uint32_t nrw                   : 1;  /**< [  4:  4](R/W) Current register width:  0 = AArch64, 1 = AArch32. */
10154         uint32_t reserved_5            : 1;
10155         uint32_t f                     : 1;  /**< [  6:  6](R/W) FIQ mask bit.
10156                                                                  0 = Exception not masked.
10157                                                                  1 = Exception masked. */
10158         uint32_t i                     : 1;  /**< [  7:  7](R/W) IRQ mask bit.
10159                                                                  0 = Exception not masked.
10160                                                                  1 = Exception masked. */
10161         uint32_t aa                    : 1;  /**< [  8:  8](R/W) Asynchronous data abort mask bit.
10162                                                                  0 = Exception not masked.
10163                                                                  1 = Exception masked. */
10164         uint32_t dd                    : 1;  /**< [  9:  9](R/W) Interrupt masks - can also be accessed as PSTATE.[D,A,I,F] */
10165         uint32_t reserved_10_19        : 10;
10166         uint32_t il                    : 1;  /**< [ 20: 20](R/W) Illegal Execution State bit. Shows the value of PSTATE[IL]
10167                                                                      immediately before Debug state was entered. */
10168         uint32_t ss                    : 1;  /**< [ 21: 21](R/W) Software step. Indicates whether software step was enabled when
10169                                                                  Debug state was entered. */
10170         uint32_t reserved_22           : 1;
10171         uint32_t uao                   : 1;  /**< [ 23: 23](R/W) User access override. */
10172         uint32_t reserved_24_27        : 4;
10173         uint32_t v                     : 1;  /**< [ 28: 28](R/W) Set to the value of CPSR[V] on entering Debug state, and copied
10174                                                                      to CPSR[V] on exiting Debug state. */
10175         uint32_t cc                    : 1;  /**< [ 29: 29](R/W) Set to the value of CPSR[C] on entering Debug state, and copied
10176                                                                      to CPSR[C] on exiting Debug state. */
10177         uint32_t z                     : 1;  /**< [ 30: 30](R/W) Set to the value of CPSR[Z] on entering Debug state, and copied
10178                                                                      to CPSR[Z] on exiting Debug state. */
10179         uint32_t n                     : 1;  /**< [ 31: 31](R/W) Set to the value of CPSR[N] on entering Debug state, and copied
10180                                                                      to CPSR[N] on exiting Debug state. */
10181 #endif /* Word 0 - End */
10182     } s;
10183     struct bdk_ap_dspsr_el0_cn8
10184     {
10185 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10186         uint32_t n                     : 1;  /**< [ 31: 31](R/W) Set to the value of CPSR[N] on entering Debug state, and copied
10187                                                                      to CPSR[N] on exiting Debug state. */
10188         uint32_t z                     : 1;  /**< [ 30: 30](R/W) Set to the value of CPSR[Z] on entering Debug state, and copied
10189                                                                      to CPSR[Z] on exiting Debug state. */
10190         uint32_t cc                    : 1;  /**< [ 29: 29](R/W) Set to the value of CPSR[C] on entering Debug state, and copied
10191                                                                      to CPSR[C] on exiting Debug state. */
10192         uint32_t v                     : 1;  /**< [ 28: 28](R/W) Set to the value of CPSR[V] on entering Debug state, and copied
10193                                                                      to CPSR[V] on exiting Debug state. */
10194         uint32_t reserved_22_27        : 6;
10195         uint32_t ss                    : 1;  /**< [ 21: 21](R/W) Software step. Indicates whether software step was enabled when
10196                                                                  Debug state was entered. */
10197         uint32_t il                    : 1;  /**< [ 20: 20](R/W) Illegal Execution State bit. Shows the value of PSTATE[IL]
10198                                                                      immediately before Debug state was entered. */
10199         uint32_t reserved_10_19        : 10;
10200         uint32_t dd                    : 1;  /**< [  9:  9](R/W) Interrupt masks - can also be accessed as PSTATE.[D,A,I,F] */
10201         uint32_t aa                    : 1;  /**< [  8:  8](R/W) Asynchronous data abort mask bit.
10202                                                                  0 = Exception not masked.
10203                                                                  1 = Exception masked. */
10204         uint32_t i                     : 1;  /**< [  7:  7](R/W) IRQ mask bit.
10205                                                                  0 = Exception not masked.
10206                                                                  1 = Exception masked. */
10207         uint32_t f                     : 1;  /**< [  6:  6](R/W) FIQ mask bit.
10208                                                                  0 = Exception not masked.
10209                                                                  1 = Exception masked. */
10210         uint32_t reserved_5            : 1;
10211         uint32_t nrw                   : 1;  /**< [  4:  4](R/W) Current register width:  0 = AArch64, 1 = AArch32. */
10212         uint32_t el                    : 2;  /**< [  3:  2](R/W) Current exception level: 0x0 = EL0, 0x1 = EL1, 0x2 = EL2, 0x3 = EL3. */
10213         uint32_t reserved_1            : 1;
10214         uint32_t sp                    : 1;  /**< [  0:  0](R/W) AArch64 only - Stack Pointer selection - 0 - SP0, 1 - SPx. */
10215 #else /* Word 0 - Little Endian */
10216         uint32_t sp                    : 1;  /**< [  0:  0](R/W) AArch64 only - Stack Pointer selection - 0 - SP0, 1 - SPx. */
10217         uint32_t reserved_1            : 1;
10218         uint32_t el                    : 2;  /**< [  3:  2](R/W) Current exception level: 0x0 = EL0, 0x1 = EL1, 0x2 = EL2, 0x3 = EL3. */
10219         uint32_t nrw                   : 1;  /**< [  4:  4](R/W) Current register width:  0 = AArch64, 1 = AArch32. */
10220         uint32_t reserved_5            : 1;
10221         uint32_t f                     : 1;  /**< [  6:  6](R/W) FIQ mask bit.
10222                                                                  0 = Exception not masked.
10223                                                                  1 = Exception masked. */
10224         uint32_t i                     : 1;  /**< [  7:  7](R/W) IRQ mask bit.
10225                                                                  0 = Exception not masked.
10226                                                                  1 = Exception masked. */
10227         uint32_t aa                    : 1;  /**< [  8:  8](R/W) Asynchronous data abort mask bit.
10228                                                                  0 = Exception not masked.
10229                                                                  1 = Exception masked. */
10230         uint32_t dd                    : 1;  /**< [  9:  9](R/W) Interrupt masks - can also be accessed as PSTATE.[D,A,I,F] */
10231         uint32_t reserved_10_19        : 10;
10232         uint32_t il                    : 1;  /**< [ 20: 20](R/W) Illegal Execution State bit. Shows the value of PSTATE[IL]
10233                                                                      immediately before Debug state was entered. */
10234         uint32_t ss                    : 1;  /**< [ 21: 21](R/W) Software step. Indicates whether software step was enabled when
10235                                                                  Debug state was entered. */
10236         uint32_t reserved_22_27        : 6;
10237         uint32_t v                     : 1;  /**< [ 28: 28](R/W) Set to the value of CPSR[V] on entering Debug state, and copied
10238                                                                      to CPSR[V] on exiting Debug state. */
10239         uint32_t cc                    : 1;  /**< [ 29: 29](R/W) Set to the value of CPSR[C] on entering Debug state, and copied
10240                                                                      to CPSR[C] on exiting Debug state. */
10241         uint32_t z                     : 1;  /**< [ 30: 30](R/W) Set to the value of CPSR[Z] on entering Debug state, and copied
10242                                                                      to CPSR[Z] on exiting Debug state. */
10243         uint32_t n                     : 1;  /**< [ 31: 31](R/W) Set to the value of CPSR[N] on entering Debug state, and copied
10244                                                                      to CPSR[N] on exiting Debug state. */
10245 #endif /* Word 0 - End */
10246     } cn8;
10247     /* struct bdk_ap_dspsr_el0_s cn9; */
10248 };
10249 typedef union bdk_ap_dspsr_el0 bdk_ap_dspsr_el0_t;
10250 
10251 #define BDK_AP_DSPSR_EL0 BDK_AP_DSPSR_EL0_FUNC()
10252 static inline uint64_t BDK_AP_DSPSR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_DSPSR_EL0_FUNC(void)10253 static inline uint64_t BDK_AP_DSPSR_EL0_FUNC(void)
10254 {
10255     return 0x30304050000ll;
10256 }
10257 
10258 #define typedef_BDK_AP_DSPSR_EL0 bdk_ap_dspsr_el0_t
10259 #define bustype_BDK_AP_DSPSR_EL0 BDK_CSR_TYPE_SYSREG
10260 #define basename_BDK_AP_DSPSR_EL0 "AP_DSPSR_EL0"
10261 #define busnum_BDK_AP_DSPSR_EL0 0
10262 #define arguments_BDK_AP_DSPSR_EL0 -1,-1,-1,-1
10263 
10264 /**
10265  * Register (SYSREG) ap_elr_el#
10266  *
10267  * AP Exception Link Register
10268  * Return address for exception
10269  */
10270 union bdk_ap_elr_elx
10271 {
10272     uint64_t u;
10273     struct bdk_ap_elr_elx_s
10274     {
10275 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10276         uint64_t address               : 64; /**< [ 63:  0](R/W) Return address for exception. */
10277 #else /* Word 0 - Little Endian */
10278         uint64_t address               : 64; /**< [ 63:  0](R/W) Return address for exception. */
10279 #endif /* Word 0 - End */
10280     } s;
10281     /* struct bdk_ap_elr_elx_s cn; */
10282 };
10283 typedef union bdk_ap_elr_elx bdk_ap_elr_elx_t;
10284 
10285 static inline uint64_t BDK_AP_ELR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ELR_ELX(unsigned long a)10286 static inline uint64_t BDK_AP_ELR_ELX(unsigned long a)
10287 {
10288     if ((a>=1)&&(a<=3))
10289         return 0x30004000100ll + 0ll * ((a) & 0x3);
10290     __bdk_csr_fatal("AP_ELR_ELX", 1, a, 0, 0, 0);
10291 }
10292 
10293 #define typedef_BDK_AP_ELR_ELX(a) bdk_ap_elr_elx_t
10294 #define bustype_BDK_AP_ELR_ELX(a) BDK_CSR_TYPE_SYSREG
10295 #define basename_BDK_AP_ELR_ELX(a) "AP_ELR_ELX"
10296 #define busnum_BDK_AP_ELR_ELX(a) (a)
10297 #define arguments_BDK_AP_ELR_ELX(a) (a),-1,-1,-1
10298 
10299 /**
10300  * Register (SYSREG) ap_elr_el12
10301  *
10302  * AP Exception Link EL2/3 Alias Register
10303  * Alias to allow EL2/3 access to ELR_EL1 when AP_HCR_EL2[E2H]==1.
10304  */
10305 union bdk_ap_elr_el12
10306 {
10307     uint64_t u;
10308     struct bdk_ap_elr_el12_s
10309     {
10310 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10311         uint64_t address               : 64; /**< [ 63:  0](R/W) Return address for exception. */
10312 #else /* Word 0 - Little Endian */
10313         uint64_t address               : 64; /**< [ 63:  0](R/W) Return address for exception. */
10314 #endif /* Word 0 - End */
10315     } s;
10316     /* struct bdk_ap_elr_el12_s cn; */
10317 };
10318 typedef union bdk_ap_elr_el12 bdk_ap_elr_el12_t;
10319 
10320 #define BDK_AP_ELR_EL12 BDK_AP_ELR_EL12_FUNC()
10321 static inline uint64_t BDK_AP_ELR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ELR_EL12_FUNC(void)10322 static inline uint64_t BDK_AP_ELR_EL12_FUNC(void)
10323 {
10324     return 0x30504000100ll;
10325 }
10326 
10327 #define typedef_BDK_AP_ELR_EL12 bdk_ap_elr_el12_t
10328 #define bustype_BDK_AP_ELR_EL12 BDK_CSR_TYPE_SYSREG
10329 #define basename_BDK_AP_ELR_EL12 "AP_ELR_EL12"
10330 #define busnum_BDK_AP_ELR_EL12 0
10331 #define arguments_BDK_AP_ELR_EL12 -1,-1,-1,-1
10332 
10333 /**
10334  * Register (SYSREG) ap_erridr_el1
10335  *
10336  * AP Error Record ID Register
10337  * Defines the number of error records that can be accessed through the Error Record system
10338  * registers.
10339  *
10340  * Usage constraints:
10341  *   AP_ERRIDR_EL1 is UNDEFINED at EL0.
10342  *   If EL2 is implemented and AP_HCR_EL2[TERR] == 1, then direct reads of AP_ERRIDR_EL1 at
10343  * nonsecure
10344  * EL1 generate a Trap exception to EL2.
10345  *   If EL3 is implemented and AP_SCR_EL3[TERR] == 1, then direct reads of AP_ERRIDR_EL1 at EL1
10346  * and EL2
10347  * generate a Trap exception to EL3.
10348  */
10349 union bdk_ap_erridr_el1
10350 {
10351     uint64_t u;
10352     struct bdk_ap_erridr_el1_s
10353     {
10354 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10355         uint64_t reserved_16_63        : 48;
10356         uint64_t num                   : 16; /**< [ 15:  0](RO) Number of records that can be accessed through the error record system registers. Each
10357                                                                  record is notionally owned by a node. A node might own multiple records. */
10358 #else /* Word 0 - Little Endian */
10359         uint64_t num                   : 16; /**< [ 15:  0](RO) Number of records that can be accessed through the error record system registers. Each
10360                                                                  record is notionally owned by a node. A node might own multiple records. */
10361         uint64_t reserved_16_63        : 48;
10362 #endif /* Word 0 - End */
10363     } s;
10364     /* struct bdk_ap_erridr_el1_s cn; */
10365 };
10366 typedef union bdk_ap_erridr_el1 bdk_ap_erridr_el1_t;
10367 
10368 #define BDK_AP_ERRIDR_EL1 BDK_AP_ERRIDR_EL1_FUNC()
10369 static inline uint64_t BDK_AP_ERRIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ERRIDR_EL1_FUNC(void)10370 static inline uint64_t BDK_AP_ERRIDR_EL1_FUNC(void)
10371 {
10372     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
10373         return 0x30005030000ll;
10374     __bdk_csr_fatal("AP_ERRIDR_EL1", 0, 0, 0, 0, 0);
10375 }
10376 
10377 #define typedef_BDK_AP_ERRIDR_EL1 bdk_ap_erridr_el1_t
10378 #define bustype_BDK_AP_ERRIDR_EL1 BDK_CSR_TYPE_SYSREG
10379 #define basename_BDK_AP_ERRIDR_EL1 "AP_ERRIDR_EL1"
10380 #define busnum_BDK_AP_ERRIDR_EL1 0
10381 #define arguments_BDK_AP_ERRIDR_EL1 -1,-1,-1,-1
10382 
10383 /**
10384  * Register (SYSREG) ap_errselr_el1
10385  *
10386  * AP Error Record Select Register
10387  * ERRSELR_EL1 is UNDEFINED at EL0.
10388  * If EL2 is implemented and HCR_EL2.TERR == 1, then direct reads and writes of ERRSELR_EL1 at
10389  * Non-secure EL1 generate a Trap exception to EL2.
10390  * If EL3 is implemented and SCR_EL3.TERR == 1, then direct reads and writes of ERRSELR_EL1 at
10391  * EL1 and EL2 generate a Trap exception to EL3.
10392  * If ERRIDR_EL1 indicates that zero records are implemented, ERRSELR_EL1 might be UNDEFINED or
10393  * RES0.
10394  */
10395 union bdk_ap_errselr_el1
10396 {
10397     uint64_t u;
10398     struct bdk_ap_errselr_el1_s
10399     {
10400 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10401         uint64_t reserved_16_63        : 48;
10402         uint64_t sel                   : 16; /**< [ 15:  0](R/W) Selects the record accessed through the ERX registers.
10403                                                                  For example, if AP_ERRSELR_EL1[SEL] is set to 4, then reads and writes of AP_ERXSTATUS_EL1
10404                                                                  access
10405                                                                  ERR4STATUS.
10406                                                                  If AP_ERRSELR_EL1[SEL] is set to a value greater than or equal to AP_ERRIDR_EL1[NUM] then:
10407                                                                    - The value read back from AP_ERRSELR_EL1[SEL] is UNKNOWN.
10408                                                                    - One of:
10409                                                                        - An UNKNOWN record is selected.
10410                                                                        - The ERX* registers are RAZ/WI.
10411                                                                        - ERX* register reads and writes are NOPs.
10412                                                                        - ERX* register reads and writes are UNDEFINED.
10413                                                                      Note: The ARM preferred behavior if one or more records are implemented is:
10414                                                                        - SEL is implemented as an N-bit field, where N is the smallest value such that
10415                                                                  ERRIDR_EL1.NUM . 2N.
10416                                                                        - If the value written to SEL modulo 2N is greater than or equal to ERRIDR_EL1.NUM,
10417                                                                  a dummy RAZ/WI record is selected.
10418                                                                      If zero records are implemented, the ARM preferred behavior is for ERRSELR_EL1 and
10419                                                                  ERX* to be undefined. */
10420 #else /* Word 0 - Little Endian */
10421         uint64_t sel                   : 16; /**< [ 15:  0](R/W) Selects the record accessed through the ERX registers.
10422                                                                  For example, if AP_ERRSELR_EL1[SEL] is set to 4, then reads and writes of AP_ERXSTATUS_EL1
10423                                                                  access
10424                                                                  ERR4STATUS.
10425                                                                  If AP_ERRSELR_EL1[SEL] is set to a value greater than or equal to AP_ERRIDR_EL1[NUM] then:
10426                                                                    - The value read back from AP_ERRSELR_EL1[SEL] is UNKNOWN.
10427                                                                    - One of:
10428                                                                        - An UNKNOWN record is selected.
10429                                                                        - The ERX* registers are RAZ/WI.
10430                                                                        - ERX* register reads and writes are NOPs.
10431                                                                        - ERX* register reads and writes are UNDEFINED.
10432                                                                      Note: The ARM preferred behavior if one or more records are implemented is:
10433                                                                        - SEL is implemented as an N-bit field, where N is the smallest value such that
10434                                                                  ERRIDR_EL1.NUM . 2N.
10435                                                                        - If the value written to SEL modulo 2N is greater than or equal to ERRIDR_EL1.NUM,
10436                                                                  a dummy RAZ/WI record is selected.
10437                                                                      If zero records are implemented, the ARM preferred behavior is for ERRSELR_EL1 and
10438                                                                  ERX* to be undefined. */
10439         uint64_t reserved_16_63        : 48;
10440 #endif /* Word 0 - End */
10441     } s;
10442     /* struct bdk_ap_errselr_el1_s cn; */
10443 };
10444 typedef union bdk_ap_errselr_el1 bdk_ap_errselr_el1_t;
10445 
10446 #define BDK_AP_ERRSELR_EL1 BDK_AP_ERRSELR_EL1_FUNC()
10447 static inline uint64_t BDK_AP_ERRSELR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ERRSELR_EL1_FUNC(void)10448 static inline uint64_t BDK_AP_ERRSELR_EL1_FUNC(void)
10449 {
10450     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
10451         return 0x30005030100ll;
10452     __bdk_csr_fatal("AP_ERRSELR_EL1", 0, 0, 0, 0, 0);
10453 }
10454 
10455 #define typedef_BDK_AP_ERRSELR_EL1 bdk_ap_errselr_el1_t
10456 #define bustype_BDK_AP_ERRSELR_EL1 BDK_CSR_TYPE_SYSREG
10457 #define basename_BDK_AP_ERRSELR_EL1 "AP_ERRSELR_EL1"
10458 #define busnum_BDK_AP_ERRSELR_EL1 0
10459 #define arguments_BDK_AP_ERRSELR_EL1 -1,-1,-1,-1
10460 
10461 /**
10462  * Register (SYSREG) ap_erxaddr_el1
10463  *
10464  * AP Selected Error Record Address Register
10465  * Accesses the ERR\<n\>ADDR address register for the error record selected by ERRSELR_EL1.SEL.
10466  *
10467  * Usage constraints as described in AP_ERXFR_EL1.
10468  */
10469 union bdk_ap_erxaddr_el1
10470 {
10471     uint64_t u;
10472     struct bdk_ap_erxaddr_el1_s
10473     {
10474 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10475         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10476 #else /* Word 0 - Little Endian */
10477         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10478 #endif /* Word 0 - End */
10479     } s;
10480     /* struct bdk_ap_erxaddr_el1_s cn; */
10481 };
10482 typedef union bdk_ap_erxaddr_el1 bdk_ap_erxaddr_el1_t;
10483 
10484 #define BDK_AP_ERXADDR_EL1 BDK_AP_ERXADDR_EL1_FUNC()
10485 static inline uint64_t BDK_AP_ERXADDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ERXADDR_EL1_FUNC(void)10486 static inline uint64_t BDK_AP_ERXADDR_EL1_FUNC(void)
10487 {
10488     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
10489         return 0x30005040300ll;
10490     __bdk_csr_fatal("AP_ERXADDR_EL1", 0, 0, 0, 0, 0);
10491 }
10492 
10493 #define typedef_BDK_AP_ERXADDR_EL1 bdk_ap_erxaddr_el1_t
10494 #define bustype_BDK_AP_ERXADDR_EL1 BDK_CSR_TYPE_SYSREG
10495 #define basename_BDK_AP_ERXADDR_EL1 "AP_ERXADDR_EL1"
10496 #define busnum_BDK_AP_ERXADDR_EL1 0
10497 #define arguments_BDK_AP_ERXADDR_EL1 -1,-1,-1,-1
10498 
10499 /**
10500  * Register (SYSREG) ap_erxctlr_el1
10501  *
10502  * AP Selected Error Record Control Register
10503  * Accesses the ERR\<n\>CTLR control register for the error record selected by AP_ERRSELR_EL1[SEL].
10504  *
10505  * Usage constraints as described in AP_ERXFR_EL1.
10506  */
10507 union bdk_ap_erxctlr_el1
10508 {
10509     uint64_t u;
10510     struct bdk_ap_erxctlr_el1_s
10511     {
10512 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10513         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10514 #else /* Word 0 - Little Endian */
10515         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10516 #endif /* Word 0 - End */
10517     } s;
10518     /* struct bdk_ap_erxctlr_el1_s cn; */
10519 };
10520 typedef union bdk_ap_erxctlr_el1 bdk_ap_erxctlr_el1_t;
10521 
10522 #define BDK_AP_ERXCTLR_EL1 BDK_AP_ERXCTLR_EL1_FUNC()
10523 static inline uint64_t BDK_AP_ERXCTLR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ERXCTLR_EL1_FUNC(void)10524 static inline uint64_t BDK_AP_ERXCTLR_EL1_FUNC(void)
10525 {
10526     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
10527         return 0x30005040100ll;
10528     __bdk_csr_fatal("AP_ERXCTLR_EL1", 0, 0, 0, 0, 0);
10529 }
10530 
10531 #define typedef_BDK_AP_ERXCTLR_EL1 bdk_ap_erxctlr_el1_t
10532 #define bustype_BDK_AP_ERXCTLR_EL1 BDK_CSR_TYPE_SYSREG
10533 #define basename_BDK_AP_ERXCTLR_EL1 "AP_ERXCTLR_EL1"
10534 #define busnum_BDK_AP_ERXCTLR_EL1 0
10535 #define arguments_BDK_AP_ERXCTLR_EL1 -1,-1,-1,-1
10536 
10537 /**
10538  * Register (SYSREG) ap_erxfr_el1
10539  *
10540  * AP Selected Error Record Feature Register
10541  * Accesses the ERR\<n\>FR feature register for the error record selected by AP_ERRSELR_EL1[SEL].
10542  *
10543  * Usage constraints:
10544  *   AP_ERXFR_EL1 is UNDEFINED at EL0.
10545  *   If EL2 is implemented and AP_HCR_EL2[TERR] == 1, then direct reads of AP_ERXFR_EL1 at Non-
10546  * secure
10547  * EL1 generate a Trap exception to EL2.
10548  *   If EL3 is implemented and AP_SCR_EL3[TERR] == 1, then direct reads of AP_ERXFR_EL1 at EL1
10549  * and EL2
10550  * generate a Trap exception to EL3.
10551  *   If AP_ERRIDR_EL1[NUM] == 0 or AP_ERRSELR_EL1[SEL] is set to a value greater than or equal to
10552  *   AP_ERRIDR_EL1[NUM] then one of:
10553  *     - An UNKNOWN record is selected.
10554  *     - AP_ERXFR_EL1 is RAZ/WI.
10555  *     - Direct reads of AP_ERXFR_EL1 are NOPs.
10556  *     - Direct reads of AP_ERXFR_EL1 are undefined.
10557  */
10558 union bdk_ap_erxfr_el1
10559 {
10560     uint64_t u;
10561     struct bdk_ap_erxfr_el1_s
10562     {
10563 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10564         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10565 #else /* Word 0 - Little Endian */
10566         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10567 #endif /* Word 0 - End */
10568     } s;
10569     /* struct bdk_ap_erxfr_el1_s cn; */
10570 };
10571 typedef union bdk_ap_erxfr_el1 bdk_ap_erxfr_el1_t;
10572 
10573 #define BDK_AP_ERXFR_EL1 BDK_AP_ERXFR_EL1_FUNC()
10574 static inline uint64_t BDK_AP_ERXFR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ERXFR_EL1_FUNC(void)10575 static inline uint64_t BDK_AP_ERXFR_EL1_FUNC(void)
10576 {
10577     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
10578         return 0x30005040000ll;
10579     __bdk_csr_fatal("AP_ERXFR_EL1", 0, 0, 0, 0, 0);
10580 }
10581 
10582 #define typedef_BDK_AP_ERXFR_EL1 bdk_ap_erxfr_el1_t
10583 #define bustype_BDK_AP_ERXFR_EL1 BDK_CSR_TYPE_SYSREG
10584 #define basename_BDK_AP_ERXFR_EL1 "AP_ERXFR_EL1"
10585 #define busnum_BDK_AP_ERXFR_EL1 0
10586 #define arguments_BDK_AP_ERXFR_EL1 -1,-1,-1,-1
10587 
10588 /**
10589  * Register (SYSREG) ap_erxmisc0_el1
10590  *
10591  * AP Selected Error Record Miscellaneous Register 0
10592  * Accesses the ERR\<n\>MISC0 miscellaneous register 0 for the error record selected by
10593  * ERRSELR_EL1.SEL.
10594  *
10595  * Usage constraints as described in AP_ERXFR_EL1.
10596  */
10597 union bdk_ap_erxmisc0_el1
10598 {
10599     uint64_t u;
10600     struct bdk_ap_erxmisc0_el1_s
10601     {
10602 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10603         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10604 #else /* Word 0 - Little Endian */
10605         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10606 #endif /* Word 0 - End */
10607     } s;
10608     /* struct bdk_ap_erxmisc0_el1_s cn; */
10609 };
10610 typedef union bdk_ap_erxmisc0_el1 bdk_ap_erxmisc0_el1_t;
10611 
10612 #define BDK_AP_ERXMISC0_EL1 BDK_AP_ERXMISC0_EL1_FUNC()
10613 static inline uint64_t BDK_AP_ERXMISC0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ERXMISC0_EL1_FUNC(void)10614 static inline uint64_t BDK_AP_ERXMISC0_EL1_FUNC(void)
10615 {
10616     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
10617         return 0x30005050000ll;
10618     __bdk_csr_fatal("AP_ERXMISC0_EL1", 0, 0, 0, 0, 0);
10619 }
10620 
10621 #define typedef_BDK_AP_ERXMISC0_EL1 bdk_ap_erxmisc0_el1_t
10622 #define bustype_BDK_AP_ERXMISC0_EL1 BDK_CSR_TYPE_SYSREG
10623 #define basename_BDK_AP_ERXMISC0_EL1 "AP_ERXMISC0_EL1"
10624 #define busnum_BDK_AP_ERXMISC0_EL1 0
10625 #define arguments_BDK_AP_ERXMISC0_EL1 -1,-1,-1,-1
10626 
10627 /**
10628  * Register (SYSREG) ap_erxmisc1_el1
10629  *
10630  * AP Selected Error Record Miscellaneous Register 1
10631  * Accesses the ERR\<n\>MISC1 miscellaneous register 1 for the error record selected by
10632  * ERRSELR_EL1.SEL.
10633  *
10634  * Usage constraints as described in AP_ERXFR_EL1.
10635  */
10636 union bdk_ap_erxmisc1_el1
10637 {
10638     uint64_t u;
10639     struct bdk_ap_erxmisc1_el1_s
10640     {
10641 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10642         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10643 #else /* Word 0 - Little Endian */
10644         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10645 #endif /* Word 0 - End */
10646     } s;
10647     /* struct bdk_ap_erxmisc1_el1_s cn; */
10648 };
10649 typedef union bdk_ap_erxmisc1_el1 bdk_ap_erxmisc1_el1_t;
10650 
10651 #define BDK_AP_ERXMISC1_EL1 BDK_AP_ERXMISC1_EL1_FUNC()
10652 static inline uint64_t BDK_AP_ERXMISC1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ERXMISC1_EL1_FUNC(void)10653 static inline uint64_t BDK_AP_ERXMISC1_EL1_FUNC(void)
10654 {
10655     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
10656         return 0x30005050100ll;
10657     __bdk_csr_fatal("AP_ERXMISC1_EL1", 0, 0, 0, 0, 0);
10658 }
10659 
10660 #define typedef_BDK_AP_ERXMISC1_EL1 bdk_ap_erxmisc1_el1_t
10661 #define bustype_BDK_AP_ERXMISC1_EL1 BDK_CSR_TYPE_SYSREG
10662 #define basename_BDK_AP_ERXMISC1_EL1 "AP_ERXMISC1_EL1"
10663 #define busnum_BDK_AP_ERXMISC1_EL1 0
10664 #define arguments_BDK_AP_ERXMISC1_EL1 -1,-1,-1,-1
10665 
10666 /**
10667  * Register (SYSREG) ap_erxstatus_el1
10668  *
10669  * AP Selected Error Record Primary Status Register
10670  * Accesses the ERR\<n\>STATUS primary status register for the error record selected by
10671  * ERRSELR_EL1.SEL.
10672  *
10673  * Usage constraints as described in AP_ERXFR_EL1.
10674  */
10675 union bdk_ap_erxstatus_el1
10676 {
10677     uint64_t u;
10678     struct bdk_ap_erxstatus_el1_s
10679     {
10680 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10681         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10682 #else /* Word 0 - Little Endian */
10683         uint64_t data                  : 64; /**< [ 63:  0](R/W) Data. */
10684 #endif /* Word 0 - End */
10685     } s;
10686     /* struct bdk_ap_erxstatus_el1_s cn; */
10687 };
10688 typedef union bdk_ap_erxstatus_el1 bdk_ap_erxstatus_el1_t;
10689 
10690 #define BDK_AP_ERXSTATUS_EL1 BDK_AP_ERXSTATUS_EL1_FUNC()
10691 static inline uint64_t BDK_AP_ERXSTATUS_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ERXSTATUS_EL1_FUNC(void)10692 static inline uint64_t BDK_AP_ERXSTATUS_EL1_FUNC(void)
10693 {
10694     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
10695         return 0x30005040200ll;
10696     __bdk_csr_fatal("AP_ERXSTATUS_EL1", 0, 0, 0, 0, 0);
10697 }
10698 
10699 #define typedef_BDK_AP_ERXSTATUS_EL1 bdk_ap_erxstatus_el1_t
10700 #define bustype_BDK_AP_ERXSTATUS_EL1 BDK_CSR_TYPE_SYSREG
10701 #define basename_BDK_AP_ERXSTATUS_EL1 "AP_ERXSTATUS_EL1"
10702 #define busnum_BDK_AP_ERXSTATUS_EL1 0
10703 #define arguments_BDK_AP_ERXSTATUS_EL1 -1,-1,-1,-1
10704 
10705 /**
10706  * Register (SYSREG) ap_esr_el#
10707  *
10708  * AP Exception Syndrome Register
10709  * Holds syndrome information for an exception taken to EL*.
10710  */
10711 union bdk_ap_esr_elx
10712 {
10713     uint32_t u;
10714     struct bdk_ap_esr_elx_s
10715     {
10716 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10717         uint32_t ec                    : 6;  /**< [ 31: 26](R/W) Exception Class. Indicates the reason for the exception that
10718                                                                      this register holds information about.
10719 
10720                                                                  0x0 = Unknown or Uncategorized Reason - generally used for
10721                                                                      exceptions as a result of erroneous execution.
10722                                                                  0x1 = Exceptions from WFE/WFI from either AArch32 or AArch64 as a
10723                                                                      result of configurable traps, enables, or disables.
10724 
10725                                                                  Conditional WFE and WFI instructions that fail their condition
10726                                                                      code check do not cause an exception.
10727 
10728                                                                  0x3 = Exceptions from MCR/MRC to CP15 from AArch32 as a result of
10729                                                                      configurable traps, enables, or disables that do not use
10730                                                                      code 0x0.
10731                                                                  0x4 = Exceptions from MCRR/MRRC to CP15 from AArch32 as a result of
10732                                                                      configurable traps, enables, or disables that do not use
10733                                                                      code 0x0.
10734                                                                  0x5 = Exceptions from MCR/MRC to CP14 from AArch32 as a result of
10735                                                                      configurable traps, enables, or disables that do not use
10736                                                                      code 0x0.
10737                                                                  0x6 = Exceptions from LDC/STC to CP14 from AArch32 as a result of
10738                                                                      configurable traps, enables, or disables. The only architected
10739                                                                      uses of these instructions to access CP14 are:
10740                                                                   An STC to write to AP_DBGDTRRX_EL0 or DBGDTRRXint.
10741                                                                   An LDC to read from AP_DBGDTRTX_EL0 or DBGDTRTXint.
10742 
10743                                                                  0x7 = Exceptions from access to Advanced SIMD or Floating Point as a
10744                                                                      result of configurable traps, enables, or disables.
10745                                                                  0xC = Exceptions from MCRR/MRRC to CP14 from AArch32 as a result of
10746                                                                      configurable traps, enables, or disables.
10747                                                                  0xE = Exceptions that occur because the value of PSTATE[IL] is 1.
10748                                                                  0x13 =SMC that is not disabled executed in AArch32.
10749                                                                  0x15 = SVC executed in AArch64.
10750                                                                  0x16 = HVC that is not disabled executed in AArch64.
10751                                                                  0x17 = SMC that is not disabled executed in AArch64.
10752                                                                  0x18 = Exceptions as a result of MSR, MRS, or System AArch64
10753                                                                      instructions as a result of configurable traps, enables, or
10754                                                                      disables, except those using codes0b0000000b0000010b000111
10755                                                                  0x20 = Instruction Abort that caused entry from a lower Exception
10756                                                                      level (AArch32 or AArch64). Used for instruction access
10757                                                                      generated MMU faults and synchronous external aborts,
10758                                                                      including synchronous parity errors. Not used for debug
10759                                                                      related exceptions.
10760                                                                  0x21 = Instruction Abort that caused entry from a current Exception
10761                                                                      level (AArch64). Used for instruction access generated MMU
10762                                                                      faults and synchronous external aborts, including synchronous
10763                                                                      parity errors. Not used for debug related exceptions.
10764                                                                  0x22 = PC Alignment Exception.
10765                                                                  0x24 = Data Abort that caused entry from a lower Exception level
10766                                                                      (AArch32 or AArch64). Used for data access generated MMU
10767                                                                      faults, alignment faults other than those caused by the Stack
10768                                                                      Pointer misalignment, and synchronous external aborts,
10769                                                                      including synchronous parity errors. Not used for debug
10770                                                                      related exceptions.
10771                                                                  0x25 = Data Abort that caused entry from a current Exception level
10772                                                                      (AArch64). Used for data access generated MMU faults,
10773                                                                      alignment faults other than those caused by the Stack Pointer
10774                                                                      misalignment, and synchronous external aborts, including
10775                                                                      synchronous parity errors. Not used for debug related
10776                                                                      exceptions.
10777                                                                  0x26 = Stack Pointer Alignment Exception.
10778                                                                  0x2C = Exceptions as a result of Floating-point exception (optional
10779                                                                      feature) from AArch64.
10780                                                                  0x2F = SError Interrupt.
10781                                                                  0x3C = BRK instruction executed in AArch64 state. */
10782         uint32_t il                    : 1;  /**< [ 25: 25](R/W) Instruction Length for synchronous exceptions.
10783                                                                  0 = 16-bit instruction trapped.
10784                                                                  1 = 32-bit instruction trapped. This value is also used when the
10785                                                                      exception is one of the following:
10786                                                                   * An SError interrupt.
10787                                                                   * An Instruction Abort exception.
10788                                                                   * A Misaligned PC exception.
10789                                                                   * A Misaligned Stack Pointer exception.
10790                                                                   * A Data Abort exception for which the value of the ISV bit is 0.
10791                                                                   * An Illegal Execution State exception.
10792                                                                   * Any debug exception except for Software Breakpoint
10793                                                                      Instruction exceptions. For Software Breakpoint Instruction
10794                                                                      exceptions, this bit has its standard meaning:- 0: 16-bit T32
10795                                                                      BKPT instruction. - 1: 32-bit A32 BKPT instruction or A64 BRK
10796                                                                      instruction.
10797                                                                   * An exception reported using EC value 0b000000. */
10798         uint32_t iss                   : 25; /**< [ 24:  0](R/W) Instruction Specific Syndrome. Architecturally, this field can
10799                                                                      be defined independently for each defined Exception class.
10800                                                                      However, in practice, some ISS encodings are used for more
10801                                                                      than one Exception class.
10802 
10803                                                                  Typically, an ISS encoding has a number of subfields. When an
10804                                                                      ISS subfield holds a register number, the value returned in
10805                                                                      that field is the AArch64 view of the register number, even if
10806                                                                      the reported exception was taken from AArch32 state. If the
10807                                                                      register number is AArch32 register R15, then:
10808 
10809                                                                   If the instruction that generated the exception was not
10810                                                                      UNPREDICTABLE, the field takes the value 0b11111.
10811 
10812                                                                   If the instruction that generated the exception was
10813                                                                      UNPREDICTABLE, the field takes an UNKNOWN value that must be
10814                                                                      either: The AArch64 view of the register number of a register
10815                                                                      that     might have been used at the Exception level from
10816                                                                      which the     exception was taken.  The value 0b11111.
10817 
10818                                                                  When the EC field is0b000000 RES0. */
10819 #else /* Word 0 - Little Endian */
10820         uint32_t iss                   : 25; /**< [ 24:  0](R/W) Instruction Specific Syndrome. Architecturally, this field can
10821                                                                      be defined independently for each defined Exception class.
10822                                                                      However, in practice, some ISS encodings are used for more
10823                                                                      than one Exception class.
10824 
10825                                                                  Typically, an ISS encoding has a number of subfields. When an
10826                                                                      ISS subfield holds a register number, the value returned in
10827                                                                      that field is the AArch64 view of the register number, even if
10828                                                                      the reported exception was taken from AArch32 state. If the
10829                                                                      register number is AArch32 register R15, then:
10830 
10831                                                                   If the instruction that generated the exception was not
10832                                                                      UNPREDICTABLE, the field takes the value 0b11111.
10833 
10834                                                                   If the instruction that generated the exception was
10835                                                                      UNPREDICTABLE, the field takes an UNKNOWN value that must be
10836                                                                      either: The AArch64 view of the register number of a register
10837                                                                      that     might have been used at the Exception level from
10838                                                                      which the     exception was taken.  The value 0b11111.
10839 
10840                                                                  When the EC field is0b000000 RES0. */
10841         uint32_t il                    : 1;  /**< [ 25: 25](R/W) Instruction Length for synchronous exceptions.
10842                                                                  0 = 16-bit instruction trapped.
10843                                                                  1 = 32-bit instruction trapped. This value is also used when the
10844                                                                      exception is one of the following:
10845                                                                   * An SError interrupt.
10846                                                                   * An Instruction Abort exception.
10847                                                                   * A Misaligned PC exception.
10848                                                                   * A Misaligned Stack Pointer exception.
10849                                                                   * A Data Abort exception for which the value of the ISV bit is 0.
10850                                                                   * An Illegal Execution State exception.
10851                                                                   * Any debug exception except for Software Breakpoint
10852                                                                      Instruction exceptions. For Software Breakpoint Instruction
10853                                                                      exceptions, this bit has its standard meaning:- 0: 16-bit T32
10854                                                                      BKPT instruction. - 1: 32-bit A32 BKPT instruction or A64 BRK
10855                                                                      instruction.
10856                                                                   * An exception reported using EC value 0b000000. */
10857         uint32_t ec                    : 6;  /**< [ 31: 26](R/W) Exception Class. Indicates the reason for the exception that
10858                                                                      this register holds information about.
10859 
10860                                                                  0x0 = Unknown or Uncategorized Reason - generally used for
10861                                                                      exceptions as a result of erroneous execution.
10862                                                                  0x1 = Exceptions from WFE/WFI from either AArch32 or AArch64 as a
10863                                                                      result of configurable traps, enables, or disables.
10864 
10865                                                                  Conditional WFE and WFI instructions that fail their condition
10866                                                                      code check do not cause an exception.
10867 
10868                                                                  0x3 = Exceptions from MCR/MRC to CP15 from AArch32 as a result of
10869                                                                      configurable traps, enables, or disables that do not use
10870                                                                      code 0x0.
10871                                                                  0x4 = Exceptions from MCRR/MRRC to CP15 from AArch32 as a result of
10872                                                                      configurable traps, enables, or disables that do not use
10873                                                                      code 0x0.
10874                                                                  0x5 = Exceptions from MCR/MRC to CP14 from AArch32 as a result of
10875                                                                      configurable traps, enables, or disables that do not use
10876                                                                      code 0x0.
10877                                                                  0x6 = Exceptions from LDC/STC to CP14 from AArch32 as a result of
10878                                                                      configurable traps, enables, or disables. The only architected
10879                                                                      uses of these instructions to access CP14 are:
10880                                                                   An STC to write to AP_DBGDTRRX_EL0 or DBGDTRRXint.
10881                                                                   An LDC to read from AP_DBGDTRTX_EL0 or DBGDTRTXint.
10882 
10883                                                                  0x7 = Exceptions from access to Advanced SIMD or Floating Point as a
10884                                                                      result of configurable traps, enables, or disables.
10885                                                                  0xC = Exceptions from MCRR/MRRC to CP14 from AArch32 as a result of
10886                                                                      configurable traps, enables, or disables.
10887                                                                  0xE = Exceptions that occur because the value of PSTATE[IL] is 1.
10888                                                                  0x13 =SMC that is not disabled executed in AArch32.
10889                                                                  0x15 = SVC executed in AArch64.
10890                                                                  0x16 = HVC that is not disabled executed in AArch64.
10891                                                                  0x17 = SMC that is not disabled executed in AArch64.
10892                                                                  0x18 = Exceptions as a result of MSR, MRS, or System AArch64
10893                                                                      instructions as a result of configurable traps, enables, or
10894                                                                      disables, except those using codes0b0000000b0000010b000111
10895                                                                  0x20 = Instruction Abort that caused entry from a lower Exception
10896                                                                      level (AArch32 or AArch64). Used for instruction access
10897                                                                      generated MMU faults and synchronous external aborts,
10898                                                                      including synchronous parity errors. Not used for debug
10899                                                                      related exceptions.
10900                                                                  0x21 = Instruction Abort that caused entry from a current Exception
10901                                                                      level (AArch64). Used for instruction access generated MMU
10902                                                                      faults and synchronous external aborts, including synchronous
10903                                                                      parity errors. Not used for debug related exceptions.
10904                                                                  0x22 = PC Alignment Exception.
10905                                                                  0x24 = Data Abort that caused entry from a lower Exception level
10906                                                                      (AArch32 or AArch64). Used for data access generated MMU
10907                                                                      faults, alignment faults other than those caused by the Stack
10908                                                                      Pointer misalignment, and synchronous external aborts,
10909                                                                      including synchronous parity errors. Not used for debug
10910                                                                      related exceptions.
10911                                                                  0x25 = Data Abort that caused entry from a current Exception level
10912                                                                      (AArch64). Used for data access generated MMU faults,
10913                                                                      alignment faults other than those caused by the Stack Pointer
10914                                                                      misalignment, and synchronous external aborts, including
10915                                                                      synchronous parity errors. Not used for debug related
10916                                                                      exceptions.
10917                                                                  0x26 = Stack Pointer Alignment Exception.
10918                                                                  0x2C = Exceptions as a result of Floating-point exception (optional
10919                                                                      feature) from AArch64.
10920                                                                  0x2F = SError Interrupt.
10921                                                                  0x3C = BRK instruction executed in AArch64 state. */
10922 #endif /* Word 0 - End */
10923     } s;
10924     /* struct bdk_ap_esr_elx_s cn; */
10925 };
10926 typedef union bdk_ap_esr_elx bdk_ap_esr_elx_t;
10927 
10928 static inline uint64_t BDK_AP_ESR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ESR_ELX(unsigned long a)10929 static inline uint64_t BDK_AP_ESR_ELX(unsigned long a)
10930 {
10931     if ((a>=1)&&(a<=3))
10932         return 0x30005020000ll + 0ll * ((a) & 0x3);
10933     __bdk_csr_fatal("AP_ESR_ELX", 1, a, 0, 0, 0);
10934 }
10935 
10936 #define typedef_BDK_AP_ESR_ELX(a) bdk_ap_esr_elx_t
10937 #define bustype_BDK_AP_ESR_ELX(a) BDK_CSR_TYPE_SYSREG
10938 #define basename_BDK_AP_ESR_ELX(a) "AP_ESR_ELX"
10939 #define busnum_BDK_AP_ESR_ELX(a) (a)
10940 #define arguments_BDK_AP_ESR_ELX(a) (a),-1,-1,-1
10941 
10942 /**
10943  * Register (SYSREG) ap_esr_el12
10944  *
10945  * AP Exception Syndrome Register
10946  * Alias of ESR_EL1 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
10947  */
10948 union bdk_ap_esr_el12
10949 {
10950     uint32_t u;
10951     struct bdk_ap_esr_el12_s
10952     {
10953 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10954         uint32_t reserved_0_31         : 32;
10955 #else /* Word 0 - Little Endian */
10956         uint32_t reserved_0_31         : 32;
10957 #endif /* Word 0 - End */
10958     } s;
10959     /* struct bdk_ap_esr_el12_s cn; */
10960 };
10961 typedef union bdk_ap_esr_el12 bdk_ap_esr_el12_t;
10962 
10963 #define BDK_AP_ESR_EL12 BDK_AP_ESR_EL12_FUNC()
10964 static inline uint64_t BDK_AP_ESR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ESR_EL12_FUNC(void)10965 static inline uint64_t BDK_AP_ESR_EL12_FUNC(void)
10966 {
10967     return 0x30505020000ll;
10968 }
10969 
10970 #define typedef_BDK_AP_ESR_EL12 bdk_ap_esr_el12_t
10971 #define bustype_BDK_AP_ESR_EL12 BDK_CSR_TYPE_SYSREG
10972 #define basename_BDK_AP_ESR_EL12 "AP_ESR_EL12"
10973 #define busnum_BDK_AP_ESR_EL12 0
10974 #define arguments_BDK_AP_ESR_EL12 -1,-1,-1,-1
10975 
10976 /**
10977  * Register (SYSREG) ap_far_el#
10978  *
10979  * AP Fault Address Register
10980  * Holds the faulting Virtual Address for all synchronous
10981  *     instruction or data aborts, or exceptions from a misaligned
10982  *     PC, taken to EL*.
10983  */
10984 union bdk_ap_far_elx
10985 {
10986     uint64_t u;
10987     struct bdk_ap_far_elx_s
10988     {
10989 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
10990         uint64_t data                  : 64; /**< [ 63:  0](R/W) Faulting Virtual Address for exceptions taken to EL*.
10991                                                                      Exceptions that set the FAR_EL* are all synchronous
10992                                                                      instruction aborts or data aborts, or an exception from a
10993                                                                      misaligned PC.
10994                                                                  If a memory fault that sets FAR_EL* is generated from one of
10995                                                                      the data cache instructions, this field holds the address
10996                                                                      specified in the register argument of the instruction. */
10997 #else /* Word 0 - Little Endian */
10998         uint64_t data                  : 64; /**< [ 63:  0](R/W) Faulting Virtual Address for exceptions taken to EL*.
10999                                                                      Exceptions that set the FAR_EL* are all synchronous
11000                                                                      instruction aborts or data aborts, or an exception from a
11001                                                                      misaligned PC.
11002                                                                  If a memory fault that sets FAR_EL* is generated from one of
11003                                                                      the data cache instructions, this field holds the address
11004                                                                      specified in the register argument of the instruction. */
11005 #endif /* Word 0 - End */
11006     } s;
11007     /* struct bdk_ap_far_elx_s cn; */
11008 };
11009 typedef union bdk_ap_far_elx bdk_ap_far_elx_t;
11010 
11011 static inline uint64_t BDK_AP_FAR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_FAR_ELX(unsigned long a)11012 static inline uint64_t BDK_AP_FAR_ELX(unsigned long a)
11013 {
11014     if ((a>=1)&&(a<=3))
11015         return 0x30006000000ll + 0ll * ((a) & 0x3);
11016     __bdk_csr_fatal("AP_FAR_ELX", 1, a, 0, 0, 0);
11017 }
11018 
11019 #define typedef_BDK_AP_FAR_ELX(a) bdk_ap_far_elx_t
11020 #define bustype_BDK_AP_FAR_ELX(a) BDK_CSR_TYPE_SYSREG
11021 #define basename_BDK_AP_FAR_ELX(a) "AP_FAR_ELX"
11022 #define busnum_BDK_AP_FAR_ELX(a) (a)
11023 #define arguments_BDK_AP_FAR_ELX(a) (a),-1,-1,-1
11024 
11025 /**
11026  * Register (SYSREG) ap_far_el12
11027  *
11028  * AP Fault Address Register
11029  * Alias of ESR_EL1 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
11030  */
11031 union bdk_ap_far_el12
11032 {
11033     uint64_t u;
11034     struct bdk_ap_far_el12_s
11035     {
11036 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11037         uint64_t reserved_0_63         : 64;
11038 #else /* Word 0 - Little Endian */
11039         uint64_t reserved_0_63         : 64;
11040 #endif /* Word 0 - End */
11041     } s;
11042     /* struct bdk_ap_far_el12_s cn; */
11043 };
11044 typedef union bdk_ap_far_el12 bdk_ap_far_el12_t;
11045 
11046 #define BDK_AP_FAR_EL12 BDK_AP_FAR_EL12_FUNC()
11047 static inline uint64_t BDK_AP_FAR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_FAR_EL12_FUNC(void)11048 static inline uint64_t BDK_AP_FAR_EL12_FUNC(void)
11049 {
11050     return 0x30506000000ll;
11051 }
11052 
11053 #define typedef_BDK_AP_FAR_EL12 bdk_ap_far_el12_t
11054 #define bustype_BDK_AP_FAR_EL12 BDK_CSR_TYPE_SYSREG
11055 #define basename_BDK_AP_FAR_EL12 "AP_FAR_EL12"
11056 #define busnum_BDK_AP_FAR_EL12 0
11057 #define arguments_BDK_AP_FAR_EL12 -1,-1,-1,-1
11058 
11059 /**
11060  * Register (SYSREG) ap_fpcr
11061  *
11062  * AP Floating-point Control Register
11063  * Controls floating-point extension behavior.
11064  */
11065 union bdk_ap_fpcr
11066 {
11067     uint32_t u;
11068     struct bdk_ap_fpcr_s
11069     {
11070 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11071         uint32_t reserved_27_31        : 5;
11072         uint32_t ahp                   : 1;  /**< [ 26: 26](R/W) Alternative half-precision control bit:
11073                                                                  0 = IEEE half-precision format selected.
11074                                                                  1 = Alternative half-precision format selected. */
11075         uint32_t dn                    : 1;  /**< [ 25: 25](R/W) Default NaN mode control bit:
11076                                                                  The value of this bit controls both scalar and Advanced SIMD
11077                                                                      floating-point arithmetic.
11078                                                                  0 = NaN operands propagate through to the output of a floating-
11079                                                                      point operation.
11080                                                                  1 = Any operation involving one or more NaNs returns the Default
11081                                                                      NaN. */
11082         uint32_t fz                    : 1;  /**< [ 24: 24](R/W) Flush-to-zero mode control bit:
11083                                                                  The value of this bit controls both scalar and Advanced SIMD
11084                                                                      floating-point arithmetic.
11085                                                                  0 = Flush-to-zero mode disabled. Behavior of the floating-point
11086                                                                      system is fully compliant with the IEEE 754 standard.
11087                                                                  1 = Flush-to-zero mode enabled. */
11088         uint32_t rmode                 : 2;  /**< [ 23: 22](R/W) Rounding Mode control field. The encoding of this field is:
11089                                                                  The specified rounding mode is used by both scalar and
11090                                                                      Advanced SIMD floating-point instructions.
11091                                                                  0x0 = Round to Nearest (RN) mode.
11092                                                                  0x1 = Round towards Plus Infinity (RP) mode.
11093                                                                  0x2 = Round towards Minus Infinity (RM) mode.
11094                                                                  0x3 = Round towards Zero (RZ) mode. */
11095         uint32_t reserved_0_21         : 22;
11096 #else /* Word 0 - Little Endian */
11097         uint32_t reserved_0_21         : 22;
11098         uint32_t rmode                 : 2;  /**< [ 23: 22](R/W) Rounding Mode control field. The encoding of this field is:
11099                                                                  The specified rounding mode is used by both scalar and
11100                                                                      Advanced SIMD floating-point instructions.
11101                                                                  0x0 = Round to Nearest (RN) mode.
11102                                                                  0x1 = Round towards Plus Infinity (RP) mode.
11103                                                                  0x2 = Round towards Minus Infinity (RM) mode.
11104                                                                  0x3 = Round towards Zero (RZ) mode. */
11105         uint32_t fz                    : 1;  /**< [ 24: 24](R/W) Flush-to-zero mode control bit:
11106                                                                  The value of this bit controls both scalar and Advanced SIMD
11107                                                                      floating-point arithmetic.
11108                                                                  0 = Flush-to-zero mode disabled. Behavior of the floating-point
11109                                                                      system is fully compliant with the IEEE 754 standard.
11110                                                                  1 = Flush-to-zero mode enabled. */
11111         uint32_t dn                    : 1;  /**< [ 25: 25](R/W) Default NaN mode control bit:
11112                                                                  The value of this bit controls both scalar and Advanced SIMD
11113                                                                      floating-point arithmetic.
11114                                                                  0 = NaN operands propagate through to the output of a floating-
11115                                                                      point operation.
11116                                                                  1 = Any operation involving one or more NaNs returns the Default
11117                                                                      NaN. */
11118         uint32_t ahp                   : 1;  /**< [ 26: 26](R/W) Alternative half-precision control bit:
11119                                                                  0 = IEEE half-precision format selected.
11120                                                                  1 = Alternative half-precision format selected. */
11121         uint32_t reserved_27_31        : 5;
11122 #endif /* Word 0 - End */
11123     } s;
11124     struct bdk_ap_fpcr_cn
11125     {
11126 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11127         uint32_t reserved_27_31        : 5;
11128         uint32_t ahp                   : 1;  /**< [ 26: 26](R/W) Alternative half-precision control bit:
11129                                                                  0 = IEEE half-precision format selected.
11130                                                                  1 = Alternative half-precision format selected. */
11131         uint32_t dn                    : 1;  /**< [ 25: 25](R/W) Default NaN mode control bit:
11132                                                                  The value of this bit controls both scalar and Advanced SIMD
11133                                                                      floating-point arithmetic.
11134                                                                  0 = NaN operands propagate through to the output of a floating-
11135                                                                      point operation.
11136                                                                  1 = Any operation involving one or more NaNs returns the Default
11137                                                                      NaN. */
11138         uint32_t fz                    : 1;  /**< [ 24: 24](R/W) Flush-to-zero mode control bit:
11139                                                                  The value of this bit controls both scalar and Advanced SIMD
11140                                                                      floating-point arithmetic.
11141                                                                  0 = Flush-to-zero mode disabled. Behavior of the floating-point
11142                                                                      system is fully compliant with the IEEE 754 standard.
11143                                                                  1 = Flush-to-zero mode enabled. */
11144         uint32_t rmode                 : 2;  /**< [ 23: 22](R/W) Rounding Mode control field. The encoding of this field is:
11145                                                                  The specified rounding mode is used by both scalar and
11146                                                                      Advanced SIMD floating-point instructions.
11147                                                                  0x0 = Round to Nearest (RN) mode.
11148                                                                  0x1 = Round towards Plus Infinity (RP) mode.
11149                                                                  0x2 = Round towards Minus Infinity (RM) mode.
11150                                                                  0x3 = Round towards Zero (RZ) mode. */
11151         uint32_t reserved_20_21        : 2;
11152         uint32_t reserved_19           : 1;
11153         uint32_t reserved_16_18        : 3;
11154         uint32_t reserved_15           : 1;
11155         uint32_t reserved_13_14        : 2;
11156         uint32_t reserved_12           : 1;
11157         uint32_t reserved_11           : 1;
11158         uint32_t reserved_10           : 1;
11159         uint32_t reserved_9            : 1;
11160         uint32_t reserved_8            : 1;
11161         uint32_t reserved_0_7          : 8;
11162 #else /* Word 0 - Little Endian */
11163         uint32_t reserved_0_7          : 8;
11164         uint32_t reserved_8            : 1;
11165         uint32_t reserved_9            : 1;
11166         uint32_t reserved_10           : 1;
11167         uint32_t reserved_11           : 1;
11168         uint32_t reserved_12           : 1;
11169         uint32_t reserved_13_14        : 2;
11170         uint32_t reserved_15           : 1;
11171         uint32_t reserved_16_18        : 3;
11172         uint32_t reserved_19           : 1;
11173         uint32_t reserved_20_21        : 2;
11174         uint32_t rmode                 : 2;  /**< [ 23: 22](R/W) Rounding Mode control field. The encoding of this field is:
11175                                                                  The specified rounding mode is used by both scalar and
11176                                                                      Advanced SIMD floating-point instructions.
11177                                                                  0x0 = Round to Nearest (RN) mode.
11178                                                                  0x1 = Round towards Plus Infinity (RP) mode.
11179                                                                  0x2 = Round towards Minus Infinity (RM) mode.
11180                                                                  0x3 = Round towards Zero (RZ) mode. */
11181         uint32_t fz                    : 1;  /**< [ 24: 24](R/W) Flush-to-zero mode control bit:
11182                                                                  The value of this bit controls both scalar and Advanced SIMD
11183                                                                      floating-point arithmetic.
11184                                                                  0 = Flush-to-zero mode disabled. Behavior of the floating-point
11185                                                                      system is fully compliant with the IEEE 754 standard.
11186                                                                  1 = Flush-to-zero mode enabled. */
11187         uint32_t dn                    : 1;  /**< [ 25: 25](R/W) Default NaN mode control bit:
11188                                                                  The value of this bit controls both scalar and Advanced SIMD
11189                                                                      floating-point arithmetic.
11190                                                                  0 = NaN operands propagate through to the output of a floating-
11191                                                                      point operation.
11192                                                                  1 = Any operation involving one or more NaNs returns the Default
11193                                                                      NaN. */
11194         uint32_t ahp                   : 1;  /**< [ 26: 26](R/W) Alternative half-precision control bit:
11195                                                                  0 = IEEE half-precision format selected.
11196                                                                  1 = Alternative half-precision format selected. */
11197         uint32_t reserved_27_31        : 5;
11198 #endif /* Word 0 - End */
11199     } cn;
11200 };
11201 typedef union bdk_ap_fpcr bdk_ap_fpcr_t;
11202 
11203 #define BDK_AP_FPCR BDK_AP_FPCR_FUNC()
11204 static inline uint64_t BDK_AP_FPCR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_FPCR_FUNC(void)11205 static inline uint64_t BDK_AP_FPCR_FUNC(void)
11206 {
11207     return 0x30304040000ll;
11208 }
11209 
11210 #define typedef_BDK_AP_FPCR bdk_ap_fpcr_t
11211 #define bustype_BDK_AP_FPCR BDK_CSR_TYPE_SYSREG
11212 #define basename_BDK_AP_FPCR "AP_FPCR"
11213 #define busnum_BDK_AP_FPCR 0
11214 #define arguments_BDK_AP_FPCR -1,-1,-1,-1
11215 
11216 /**
11217  * Register (SYSREG) ap_fpexc32_el2
11218  *
11219  * AP Floating-point Exception Control Register
11220  * Allows access to the AArch32 register FPEXC from AArch64 state
11221  *     only. Its value has no effect on execution in AArch64 state.
11222  */
11223 union bdk_ap_fpexc32_el2
11224 {
11225     uint32_t u;
11226     struct bdk_ap_fpexc32_el2_s
11227     {
11228 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11229         uint32_t reserved_0_31         : 32;
11230 #else /* Word 0 - Little Endian */
11231         uint32_t reserved_0_31         : 32;
11232 #endif /* Word 0 - End */
11233     } s;
11234     /* struct bdk_ap_fpexc32_el2_s cn; */
11235 };
11236 typedef union bdk_ap_fpexc32_el2 bdk_ap_fpexc32_el2_t;
11237 
11238 #define BDK_AP_FPEXC32_EL2 BDK_AP_FPEXC32_EL2_FUNC()
11239 static inline uint64_t BDK_AP_FPEXC32_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_FPEXC32_EL2_FUNC(void)11240 static inline uint64_t BDK_AP_FPEXC32_EL2_FUNC(void)
11241 {
11242     return 0x30405030000ll;
11243 }
11244 
11245 #define typedef_BDK_AP_FPEXC32_EL2 bdk_ap_fpexc32_el2_t
11246 #define bustype_BDK_AP_FPEXC32_EL2 BDK_CSR_TYPE_SYSREG
11247 #define basename_BDK_AP_FPEXC32_EL2 "AP_FPEXC32_EL2"
11248 #define busnum_BDK_AP_FPEXC32_EL2 0
11249 #define arguments_BDK_AP_FPEXC32_EL2 -1,-1,-1,-1
11250 
11251 /**
11252  * Register (SYSREG) ap_fpsr
11253  *
11254  * AP Floating-point Status Register
11255  * Provides floating-point system status information.
11256  */
11257 union bdk_ap_fpsr
11258 {
11259     uint32_t u;
11260     struct bdk_ap_fpsr_s
11261     {
11262 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11263         uint32_t reserved_28_31        : 4;
11264         uint32_t qc                    : 1;  /**< [ 27: 27](R/W) Cumulative saturation bit, Advanced SIMD only. This bit is set
11265                                                                      to 1 to indicate that an Advanced SIMD integer operation has
11266                                                                      saturated since 0 was last written to this bit. */
11267         uint32_t reserved_8_26         : 19;
11268         uint32_t idc                   : 1;  /**< [  7:  7](R/W) Input Denormal cumulative exception bit. This bit is set to 1
11269                                                                      to indicate that the Input Denormal exception has occurred
11270                                                                      since 0 was last written to this bit.
11271 
11272                                                                  How scalar and Advanced SIMD floating-point instructions
11273                                                                      update this bit depends on the value of the AP_FPCR[IDE] bit. This
11274                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IDE] is
11275                                                                      0, or if trapping software sets it. */
11276         uint32_t reserved_5_6          : 2;
11277         uint32_t ixc                   : 1;  /**< [  4:  4](R/W) Inexact cumulative exception bit. This bit is set to 1 to
11278                                                                      indicate that the Inexact exception has occurred since 0 was
11279                                                                      last written to this bit.
11280 
11281                                                                  How scalar and Advanced SIMD floating-point instructions
11282                                                                      update this bit depends on the value of the AP_FPCR[IXE] bit. This
11283                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IXE] is
11284                                                                      0, or if trapping software sets it. */
11285         uint32_t ufc                   : 1;  /**< [  3:  3](R/W) Underflow cumulative exception bit. This bit is set to 1 to
11286                                                                      indicate that the Underflow exception has occurred since 0 was
11287                                                                      last written to this bit.
11288 
11289                                                                  How scalar and Advanced SIMD floating-point instructions
11290                                                                      update this bit depends on the value of the AP_FPCR[UFE] bit. This
11291                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[UFE] is
11292                                                                      0, or if trapping software sets it. */
11293         uint32_t ofc                   : 1;  /**< [  2:  2](R/W) Overflow cumulative exception bit. This bit is set to 1 to
11294                                                                      indicate that the Overflow exception has occurred since 0 was
11295                                                                      last written to this bit.
11296 
11297                                                                  How scalar and Advanced SIMD floating-point instructions
11298                                                                      update this bit depends on the value of the AP_FPCR[OFE] bit. This
11299                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[OFE] is
11300                                                                      0, or if trapping software sets it. */
11301         uint32_t dzc                   : 1;  /**< [  1:  1](R/W) Division by Zero cumulative exception bit. This bit is set to
11302                                                                      1 to indicate that the Division by Zero exception has occurred
11303                                                                      since 0 was last written to this bit.
11304 
11305                                                                  How scalar and Advanced SIMD floating-point instructions
11306                                                                      update this bit depends on the value of the AP_FPCR[DZE] bit. This
11307                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[DZE] is
11308                                                                      0, or if trapping software sets it. */
11309         uint32_t ioc                   : 1;  /**< [  0:  0](R/W) Invalid Operation cumulative exception bit. This bit is set to
11310                                                                      1 to indicate that the Invalid Operation exception has
11311                                                                      occurred since 0 was last written to this bit.
11312 
11313                                                                  How scalar and Advanced SIMD floating-point instructions
11314                                                                      update this bit depends on the value of the AP_FPCR[IOE] bit. This
11315                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IOE] is
11316                                                                      0, or if trapping software sets it. */
11317 #else /* Word 0 - Little Endian */
11318         uint32_t ioc                   : 1;  /**< [  0:  0](R/W) Invalid Operation cumulative exception bit. This bit is set to
11319                                                                      1 to indicate that the Invalid Operation exception has
11320                                                                      occurred since 0 was last written to this bit.
11321 
11322                                                                  How scalar and Advanced SIMD floating-point instructions
11323                                                                      update this bit depends on the value of the AP_FPCR[IOE] bit. This
11324                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IOE] is
11325                                                                      0, or if trapping software sets it. */
11326         uint32_t dzc                   : 1;  /**< [  1:  1](R/W) Division by Zero cumulative exception bit. This bit is set to
11327                                                                      1 to indicate that the Division by Zero exception has occurred
11328                                                                      since 0 was last written to this bit.
11329 
11330                                                                  How scalar and Advanced SIMD floating-point instructions
11331                                                                      update this bit depends on the value of the AP_FPCR[DZE] bit. This
11332                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[DZE] is
11333                                                                      0, or if trapping software sets it. */
11334         uint32_t ofc                   : 1;  /**< [  2:  2](R/W) Overflow cumulative exception bit. This bit is set to 1 to
11335                                                                      indicate that the Overflow exception has occurred since 0 was
11336                                                                      last written to this bit.
11337 
11338                                                                  How scalar and Advanced SIMD floating-point instructions
11339                                                                      update this bit depends on the value of the AP_FPCR[OFE] bit. This
11340                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[OFE] is
11341                                                                      0, or if trapping software sets it. */
11342         uint32_t ufc                   : 1;  /**< [  3:  3](R/W) Underflow cumulative exception bit. This bit is set to 1 to
11343                                                                      indicate that the Underflow exception has occurred since 0 was
11344                                                                      last written to this bit.
11345 
11346                                                                  How scalar and Advanced SIMD floating-point instructions
11347                                                                      update this bit depends on the value of the AP_FPCR[UFE] bit. This
11348                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[UFE] is
11349                                                                      0, or if trapping software sets it. */
11350         uint32_t ixc                   : 1;  /**< [  4:  4](R/W) Inexact cumulative exception bit. This bit is set to 1 to
11351                                                                      indicate that the Inexact exception has occurred since 0 was
11352                                                                      last written to this bit.
11353 
11354                                                                  How scalar and Advanced SIMD floating-point instructions
11355                                                                      update this bit depends on the value of the AP_FPCR[IXE] bit. This
11356                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IXE] is
11357                                                                      0, or if trapping software sets it. */
11358         uint32_t reserved_5_6          : 2;
11359         uint32_t idc                   : 1;  /**< [  7:  7](R/W) Input Denormal cumulative exception bit. This bit is set to 1
11360                                                                      to indicate that the Input Denormal exception has occurred
11361                                                                      since 0 was last written to this bit.
11362 
11363                                                                  How scalar and Advanced SIMD floating-point instructions
11364                                                                      update this bit depends on the value of the AP_FPCR[IDE] bit. This
11365                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IDE] is
11366                                                                      0, or if trapping software sets it. */
11367         uint32_t reserved_8_26         : 19;
11368         uint32_t qc                    : 1;  /**< [ 27: 27](R/W) Cumulative saturation bit, Advanced SIMD only. This bit is set
11369                                                                      to 1 to indicate that an Advanced SIMD integer operation has
11370                                                                      saturated since 0 was last written to this bit. */
11371         uint32_t reserved_28_31        : 4;
11372 #endif /* Word 0 - End */
11373     } s;
11374     struct bdk_ap_fpsr_cn
11375     {
11376 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11377         uint32_t reserved_31           : 1;
11378         uint32_t reserved_30           : 1;
11379         uint32_t reserved_29           : 1;
11380         uint32_t reserved_28           : 1;
11381         uint32_t qc                    : 1;  /**< [ 27: 27](R/W) Cumulative saturation bit, Advanced SIMD only. This bit is set
11382                                                                      to 1 to indicate that an Advanced SIMD integer operation has
11383                                                                      saturated since 0 was last written to this bit. */
11384         uint32_t reserved_8_26         : 19;
11385         uint32_t idc                   : 1;  /**< [  7:  7](R/W) Input Denormal cumulative exception bit. This bit is set to 1
11386                                                                      to indicate that the Input Denormal exception has occurred
11387                                                                      since 0 was last written to this bit.
11388 
11389                                                                  How scalar and Advanced SIMD floating-point instructions
11390                                                                      update this bit depends on the value of the AP_FPCR[IDE] bit. This
11391                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IDE] is
11392                                                                      0, or if trapping software sets it. */
11393         uint32_t reserved_5_6          : 2;
11394         uint32_t ixc                   : 1;  /**< [  4:  4](R/W) Inexact cumulative exception bit. This bit is set to 1 to
11395                                                                      indicate that the Inexact exception has occurred since 0 was
11396                                                                      last written to this bit.
11397 
11398                                                                  How scalar and Advanced SIMD floating-point instructions
11399                                                                      update this bit depends on the value of the AP_FPCR[IXE] bit. This
11400                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IXE] is
11401                                                                      0, or if trapping software sets it. */
11402         uint32_t ufc                   : 1;  /**< [  3:  3](R/W) Underflow cumulative exception bit. This bit is set to 1 to
11403                                                                      indicate that the Underflow exception has occurred since 0 was
11404                                                                      last written to this bit.
11405 
11406                                                                  How scalar and Advanced SIMD floating-point instructions
11407                                                                      update this bit depends on the value of the AP_FPCR[UFE] bit. This
11408                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[UFE] is
11409                                                                      0, or if trapping software sets it. */
11410         uint32_t ofc                   : 1;  /**< [  2:  2](R/W) Overflow cumulative exception bit. This bit is set to 1 to
11411                                                                      indicate that the Overflow exception has occurred since 0 was
11412                                                                      last written to this bit.
11413 
11414                                                                  How scalar and Advanced SIMD floating-point instructions
11415                                                                      update this bit depends on the value of the AP_FPCR[OFE] bit. This
11416                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[OFE] is
11417                                                                      0, or if trapping software sets it. */
11418         uint32_t dzc                   : 1;  /**< [  1:  1](R/W) Division by Zero cumulative exception bit. This bit is set to
11419                                                                      1 to indicate that the Division by Zero exception has occurred
11420                                                                      since 0 was last written to this bit.
11421 
11422                                                                  How scalar and Advanced SIMD floating-point instructions
11423                                                                      update this bit depends on the value of the AP_FPCR[DZE] bit. This
11424                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[DZE] is
11425                                                                      0, or if trapping software sets it. */
11426         uint32_t ioc                   : 1;  /**< [  0:  0](R/W) Invalid Operation cumulative exception bit. This bit is set to
11427                                                                      1 to indicate that the Invalid Operation exception has
11428                                                                      occurred since 0 was last written to this bit.
11429 
11430                                                                  How scalar and Advanced SIMD floating-point instructions
11431                                                                      update this bit depends on the value of the AP_FPCR[IOE] bit. This
11432                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IOE] is
11433                                                                      0, or if trapping software sets it. */
11434 #else /* Word 0 - Little Endian */
11435         uint32_t ioc                   : 1;  /**< [  0:  0](R/W) Invalid Operation cumulative exception bit. This bit is set to
11436                                                                      1 to indicate that the Invalid Operation exception has
11437                                                                      occurred since 0 was last written to this bit.
11438 
11439                                                                  How scalar and Advanced SIMD floating-point instructions
11440                                                                      update this bit depends on the value of the AP_FPCR[IOE] bit. This
11441                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IOE] is
11442                                                                      0, or if trapping software sets it. */
11443         uint32_t dzc                   : 1;  /**< [  1:  1](R/W) Division by Zero cumulative exception bit. This bit is set to
11444                                                                      1 to indicate that the Division by Zero exception has occurred
11445                                                                      since 0 was last written to this bit.
11446 
11447                                                                  How scalar and Advanced SIMD floating-point instructions
11448                                                                      update this bit depends on the value of the AP_FPCR[DZE] bit. This
11449                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[DZE] is
11450                                                                      0, or if trapping software sets it. */
11451         uint32_t ofc                   : 1;  /**< [  2:  2](R/W) Overflow cumulative exception bit. This bit is set to 1 to
11452                                                                      indicate that the Overflow exception has occurred since 0 was
11453                                                                      last written to this bit.
11454 
11455                                                                  How scalar and Advanced SIMD floating-point instructions
11456                                                                      update this bit depends on the value of the AP_FPCR[OFE] bit. This
11457                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[OFE] is
11458                                                                      0, or if trapping software sets it. */
11459         uint32_t ufc                   : 1;  /**< [  3:  3](R/W) Underflow cumulative exception bit. This bit is set to 1 to
11460                                                                      indicate that the Underflow exception has occurred since 0 was
11461                                                                      last written to this bit.
11462 
11463                                                                  How scalar and Advanced SIMD floating-point instructions
11464                                                                      update this bit depends on the value of the AP_FPCR[UFE] bit. This
11465                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[UFE] is
11466                                                                      0, or if trapping software sets it. */
11467         uint32_t ixc                   : 1;  /**< [  4:  4](R/W) Inexact cumulative exception bit. This bit is set to 1 to
11468                                                                      indicate that the Inexact exception has occurred since 0 was
11469                                                                      last written to this bit.
11470 
11471                                                                  How scalar and Advanced SIMD floating-point instructions
11472                                                                      update this bit depends on the value of the AP_FPCR[IXE] bit. This
11473                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IXE] is
11474                                                                      0, or if trapping software sets it. */
11475         uint32_t reserved_5_6          : 2;
11476         uint32_t idc                   : 1;  /**< [  7:  7](R/W) Input Denormal cumulative exception bit. This bit is set to 1
11477                                                                      to indicate that the Input Denormal exception has occurred
11478                                                                      since 0 was last written to this bit.
11479 
11480                                                                  How scalar and Advanced SIMD floating-point instructions
11481                                                                      update this bit depends on the value of the AP_FPCR[IDE] bit. This
11482                                                                      bit is only set to 1 to indicate an exception if AP_FPCR[IDE] is
11483                                                                      0, or if trapping software sets it. */
11484         uint32_t reserved_8_26         : 19;
11485         uint32_t qc                    : 1;  /**< [ 27: 27](R/W) Cumulative saturation bit, Advanced SIMD only. This bit is set
11486                                                                      to 1 to indicate that an Advanced SIMD integer operation has
11487                                                                      saturated since 0 was last written to this bit. */
11488         uint32_t reserved_28           : 1;
11489         uint32_t reserved_29           : 1;
11490         uint32_t reserved_30           : 1;
11491         uint32_t reserved_31           : 1;
11492 #endif /* Word 0 - End */
11493     } cn;
11494 };
11495 typedef union bdk_ap_fpsr bdk_ap_fpsr_t;
11496 
11497 #define BDK_AP_FPSR BDK_AP_FPSR_FUNC()
11498 static inline uint64_t BDK_AP_FPSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_FPSR_FUNC(void)11499 static inline uint64_t BDK_AP_FPSR_FUNC(void)
11500 {
11501     return 0x30304040100ll;
11502 }
11503 
11504 #define typedef_BDK_AP_FPSR bdk_ap_fpsr_t
11505 #define bustype_BDK_AP_FPSR BDK_CSR_TYPE_SYSREG
11506 #define basename_BDK_AP_FPSR "AP_FPSR"
11507 #define busnum_BDK_AP_FPSR 0
11508 #define arguments_BDK_AP_FPSR -1,-1,-1,-1
11509 
11510 /**
11511  * Register (SYSREG) ap_hacr_el2
11512  *
11513  * AP Hypervisor Auxiliary Control Register
11514  * Controls trapping to EL2 of implementation defined aspects of
11515  *     nonsecure EL1 or EL0 operation.
11516  */
11517 union bdk_ap_hacr_el2
11518 {
11519     uint32_t u;
11520     struct bdk_ap_hacr_el2_s
11521     {
11522 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11523         uint32_t reserved_0_31         : 32;
11524 #else /* Word 0 - Little Endian */
11525         uint32_t reserved_0_31         : 32;
11526 #endif /* Word 0 - End */
11527     } s;
11528     /* struct bdk_ap_hacr_el2_s cn; */
11529 };
11530 typedef union bdk_ap_hacr_el2 bdk_ap_hacr_el2_t;
11531 
11532 #define BDK_AP_HACR_EL2 BDK_AP_HACR_EL2_FUNC()
11533 static inline uint64_t BDK_AP_HACR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_HACR_EL2_FUNC(void)11534 static inline uint64_t BDK_AP_HACR_EL2_FUNC(void)
11535 {
11536     return 0x30401010700ll;
11537 }
11538 
11539 #define typedef_BDK_AP_HACR_EL2 bdk_ap_hacr_el2_t
11540 #define bustype_BDK_AP_HACR_EL2 BDK_CSR_TYPE_SYSREG
11541 #define basename_BDK_AP_HACR_EL2 "AP_HACR_EL2"
11542 #define busnum_BDK_AP_HACR_EL2 0
11543 #define arguments_BDK_AP_HACR_EL2 -1,-1,-1,-1
11544 
11545 /**
11546  * Register (SYSREG) ap_hcr_el2
11547  *
11548  * AP Hypervisor Configuration Register
11549  * Provides configuration controls for virtualization, including
11550  *     defining whether various nonsecure operations are trapped to
11551  *     EL2.
11552  */
11553 union bdk_ap_hcr_el2
11554 {
11555     uint64_t u;
11556     struct bdk_ap_hcr_el2_s
11557     {
11558 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
11559         uint64_t reserved_38_63        : 26;
11560         uint64_t tea                   : 1;  /**< [ 37: 37](R/W) RAS: Route synchronous external aborts to EL2.
11561                                                                    0 = Do not route synchronous external aborts from Non-secure EL0 and EL1 to EL2.
11562                                                                    1 = Route synchronous external aborts from Non-secure EL0 and EL1 to EL2, if not routed
11563                                                                  to EL3. */
11564         uint64_t terr                  : 1;  /**< [ 36: 36](R/W) RAS: Trap Error record accesses.
11565                                                                    0 = Do not trap accesses to error record registers from Non-secure EL1 to EL2.
11566                                                                    1 = Accesses to the ER* registers from Non-secure EL1 generate a Trap exception to EL2. */
11567         uint64_t tlor                  : 1;  /**< [ 35: 35](R/W) v8.1: Trap access to the LOR Registers from nonsecure EL1 to EL2.
11568                                                                  0 = Nonsecure EL1 accesses to the LOR Registers are not trapped to EL2.
11569                                                                  1 = Nonsecure EL1 accesses to the LOR Registers are trapped to EL2. */
11570         uint64_t e2h                   : 1;  /**< [ 34: 34](R/W) V8.1: Enable EL2 host. */
11571         uint64_t id                    : 1;  /**< [ 33: 33](R/W) Stage 2 Instruction cache disable. When AP_HCR_EL2[VM]==1, this
11572                                                                      forces all stage 2 translations for instruction accesses to
11573                                                                      Normal memory to be Non-cacheable for the EL1&0 translation
11574                                                                      regime.
11575                                                                  This bit has no effect on the EL2 or EL3 translation regimes.
11576                                                                  0 = No effect on the stage 2 of the EL1&0 translation regime for
11577                                                                      instruction accesses.
11578                                                                  1 = Forces all stage 2 translations for instruction accesses to
11579                                                                      Normal memory to be Non-cacheable for the EL1&0 translation
11580                                                                      regime. */
11581         uint64_t cd                    : 1;  /**< [ 32: 32](R/W) Stage 2 Data cache disable. When AP_HCR_EL2[VM]==1, this forces
11582                                                                      all stage 2 translations for data accesses and translation
11583                                                                      table walks to Normal memory to be Non-cacheable for the EL1&0
11584                                                                      translation regime.
11585                                                                  This bit has no effect on the EL2 or EL3 translation regimes.
11586                                                                  0 = No effect on the stage 2 of the EL1&0 translation regime for
11587                                                                      data accesses and translation table walks.
11588                                                                  1 = Forces all stage 2 translations for data accesses and
11589                                                                      translation table walks to Normal memory to be Non-cacheable
11590                                                                      for the EL1&0 translation regime. */
11591         uint64_t rsvd_31               : 1;  /**< [ 31: 31](RO) rw - Register Width control for lower exception levels:
11592                                                                  When AP_SCR_EL3[NS]==0, this bit behaves as if it has the same
11593                                                                      value as the AP_SCR_EL3[RW] bit except for the value read back.
11594                                                                  The RW bit is permitted to be cached in a TLB.
11595                                                                  0 = Lower levels are all AArch32.
11596                                                                  1 = EL1 is AArch64. EL0 is determined by the Execution state
11597                                                                      described in the current process state when executing at EL0. */
11598         uint64_t trvm                  : 1;  /**< [ 30: 30](R/W) Trap Read of Virtual Memory controls. When this bit is set to
11599                                                                      1, this causes Reads to the EL1 virtual memory control
11600                                                                      registers from EL1 to be trapped to EL2. This covers the
11601                                                                      following registers:
11602 
11603                                                                  AArch32: SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR,
11604                                                                      IFAR, ADFSR, AIFSR, PRRR/ MAIR0, NMRR/ MAIR1, AMAIR0, AMAIR1,
11605                                                                      CONTEXTIDR.
11606 
11607                                                                  AArch64: AP_SCTLR_EL1, AP_TTBR0_EL1, AP_TTBR1_EL1, AP_TCR_EL1, ESR_EL1,
11608                                                                      FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1,
11609                                                                      AP_CONTEXTIDR_EL1. */
11610         uint64_t reserved_29           : 1;
11611         uint64_t tdz                   : 1;  /**< [ 28: 28](R/W) Trap DC ZVA instruction:
11612                                                                  This bit also has an effect on the value read from the
11613                                                                      AP_DCZID_EL0 register. If this bit is 1, then reading
11614                                                                      AP_DCZID_EL0[DZP] from nonsecure EL1 or EL0 will return 1 to
11615                                                                      indicate that DC ZVA is prohibited.
11616                                                                  0 = The instruction is not trapped.
11617                                                                  1 = The instruction is trapped to EL2 when executed in nonsecure
11618                                                                      EL1 or EL0. */
11619         uint64_t tge                   : 1;  /**< [ 27: 27](R/W) Trap General Exceptions. If this bit is set to 1, and
11620                                                                      AP_SCR_EL3[NS] is set to 1, then:
11621 
11622                                                                   All exceptions that would be routed to EL1 are routed to EL2.
11623 
11624                                                                   The AP_SCTLR_EL1[M] bit is treated as being 0 regardless of its
11625                                                                      actual state (for EL1 using AArch32 or AArch64) other than for
11626                                                                      the purpose of reading the bit.
11627 
11628                                                                   The AP_HCR_EL2[FMO], IMO and AMO bits are treated as being 1
11629                                                                      regardless of their actual state other than for the purpose of
11630                                                                      reading the bits.
11631 
11632                                                                   All virtual interrupts are disabled.
11633 
11634                                                                   Any implementation defined mechanisms for signalling virtual
11635                                                                      interrupts are disabled.
11636 
11637                                                                   An exception return to EL1 is treated as an illegal exception
11638                                                                      return.
11639 
11640                                                                  Additionally, if AP_HCR_EL2[TGE] == 1, the
11641                                                                      AP_MDCR_EL2.{TDRA,TDOSA,TDA} bits are ignored and the processor
11642                                                                      behaves as if they are set to 1, other than for the value read
11643                                                                      back from AP_MDCR_EL2. */
11644         uint64_t tvm                   : 1;  /**< [ 26: 26](R/W) Trap Virtual Memory controls. When this bit is set to 1, this
11645                                                                      causes Writes to the EL1 virtual memory control registers from
11646                                                                      EL1 to be trapped to EL2. This covers the following registers:
11647 
11648                                                                  AArch32: SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR,
11649                                                                      IFAR, ADFSR, AIFSR, PRRR/ MAIR0, NMRR/ MAIR1, AMAIR0, AMAIR1,
11650                                                                      CONTEXTIDR.
11651 
11652                                                                  AArch64: AP_SCTLR_EL1, AP_TTBR0_EL1, AP_TTBR1_EL1, AP_TCR_EL1, ESR_EL1,
11653                                                                      FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1,
11654                                                                      AP_CONTEXTIDR_EL1 */
11655         uint64_t ttlb                  : 1;  /**< [ 25: 25](R/W) Trap TLB maintenance instructions. When this bit is set to 1,
11656                                                                      this causes TLB maintenance instructions executed from EL1
11657                                                                      which are not UNdefined to be trapped to EL2. This covers the
11658                                                                      following instructions:
11659 
11660                                                                  AArch32: TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS,
11661                                                                      TLBIALL, TLBIMVA, TLBIASID, DTLBIALL, DTLBIMVA, DTLBIASID,
11662                                                                      ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA, TLBIMVALIS,
11663                                                                      TLBIMVAALIS, TLBIMVAL, TLBIMVAAL
11664 
11665                                                                  AArch64: TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
11666                                                                      TLBI VALE1, TLBI VAALE1, TLBI VMALLE1IS, TLBI VAE1IS, TLBI
11667                                                                      ASIDE1IS, TLBI VAAE1IS, TLBI VALE1IS, TLBI VAALE1IS */
11668         uint64_t tpu                   : 1;  /**< [ 24: 24](R/W) Trap Cache maintenance instructions to Point of Unification.
11669                                                                      When this bit is set to 1, this causes Cache maintenance
11670                                                                      instructions to the point of unification executed from EL1 or
11671                                                                      EL0 which are not UNdefined to be trapped to EL2. This covers
11672                                                                      the following instructions:
11673 
11674                                                                  AArch32: ICIMVAU, ICIALLU, ICIALLUIS, DCCMVAU.
11675 
11676                                                                  AArch64: IC IVAU, IC IALLU, IC IALLUIS, DC CVAU. */
11677         uint64_t tpc                   : 1;  /**< [ 23: 23](R/W) Trap Data/Unified Cache maintenance operations to Point of
11678                                                                      Coherency. When this bit is set to 1, this causes Data or
11679                                                                      Unified Cache maintenance instructions by address to the point
11680                                                                      of coherency executed from EL1 or EL0 which are not UNdefined
11681                                                                      to be trapped to EL2. This covers the following instructions:
11682 
11683                                                                  AArch32: DCIMVAC, DCCIMVAC, DCCMVAC.
11684 
11685                                                                  AArch64: DC IVAC, DC CIVAC, DC CVAC. */
11686         uint64_t tsw                   : 1;  /**< [ 22: 22](R/W) Trap Data/Unified Cache maintenance operations by Set/Way.
11687                                                                      When this bit is set to 1, this causes Data or Unified Cache
11688                                                                      maintenance instructions by set/way executed from EL1 which
11689                                                                      are not UNdefined to be trapped to EL2. This covers the
11690                                                                      following instructions:
11691 
11692                                                                  AArch32: DCISW, DCCSW, DCCISW.
11693 
11694                                                                  AArch64: DC ISW, DC CSW, DC CISW. */
11695         uint64_t tacr                  : 1;  /**< [ 21: 21](R/W) Trap Auxiliary Control Register. When this bit is set to 1,
11696                                                                      this causes accesses to the following registers executed from
11697                                                                      EL1 to be trapped to EL2:
11698 
11699                                                                  AArch32: ACTLR.
11700 
11701                                                                  AArch64: ACTLR_EL1. */
11702         uint64_t tidcp                 : 1;  /**< [ 20: 20](R/W) Trap Implementation Dependent functionality. When this bit is
11703                                                                      set to 1, this causes accesses to the following instruction
11704                                                                      set space executed from EL1 to be trapped to EL2.
11705 
11706                                                                  AArch32: MCR and MRC instructions as follows:
11707 
11708                                                                   All CP15, CRn==9,  Opcode1 = {0-7}, CRm == {c0-c2, c5-c8},
11709                                                                      opcode2 == {0-7}.
11710 
11711                                                                   All CP15, CRn==10, Opcode1 =={0-7}, CRm == {c0, c1, c4, c8},
11712                                                                      opcode2 == {0-7}.
11713 
11714                                                                   All CP15, CRn==11, Opcode1=={0-7}, CRm == {c0-c8, c15},
11715                                                                      opcode2 == {0-7}.
11716 
11717                                                                  AArch64: All encoding space reserved for implementation
11718                                                                      defined system operations ( S1_\<op1\>_\<Cn\>_\<Cm\>_\<op2\>) and
11719                                                                      system registers ( S3_\<op1\>_\<Cn\>_\<Cm\>_\<op2\>).
11720 
11721                                                                  It is implementation defined whether any of this functionality
11722                                                                      accessed from EL0 is trapped to EL2 when the AP_HCR_EL2[TIDCP] bit
11723                                                                      is set. If it is not trapped to EL2, it results in an
11724                                                                      Undefined exception taken to EL1. */
11725         uint64_t tsc                   : 1;  /**< [ 19: 19](R/W) Trap SMC. When this bit is set to 1, this causes the following
11726                                                                      instructions executed from EL1 to be trapped to EL2:
11727 
11728                                                                  AArch32: SMC.
11729 
11730                                                                  AArch64: SMC.
11731 
11732                                                                  If EL3 is not implemented, this bit is RES0. */
11733         uint64_t tid3                  : 1;  /**< [ 18: 18](R/W) Trap ID Group 3. When this bit is set to 1, this causes reads
11734                                                                      to the following registers executed from EL1 to be trapped to
11735                                                                      EL2:
11736 
11737                                                                  AArch32: ID_PFR0, ID_PFR1, ID_DFR0, ID_AFR0, ID_MMFR0,
11738                                                                      ID_MMFR1, ID_MMFR2, ID_MMFR3, ID_ISAR0, ID_ISAR1, ID_ISAR2,
11739                                                                      ID_ISAR3, ID_ISAR4, ID_ISAR5, MVFR0, MVFR1, MVFR2. Also MRC to
11740                                                                      any of the following encodings:
11741 
11742                                                                   CP15, CRn == 0, Opc1 == 0, CRm == {3-7}, Opc2 == {0,1}.
11743 
11744                                                                   CP15, CRn == 0, Opc1 == 0, CRm == 3, Opc2 == 2.
11745 
11746                                                                   CP15, CRn == 0, Opc1 == 0, CRm == 5, Opc2 == {4,5}.
11747 
11748                                                                  AArch64: AP_ID_PFR0_EL1, AP_ID_PFR1_EL1, AP_ID_DFR0_EL1, AP_ID_AFR0_EL1,
11749                                                                      ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1,
11750                                                                      ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1,
11751                                                                      ID_ISAR4_EL1, ID_ISAR5_EL1, MVFR0_EL1, MVFR1_EL1, MVFR2_EL1,
11752                                                                      AP_ID_AA64PFR0_EL1, AP_ID_AA64PFR1_EL1, AP_ID_AA64DFR0_EL1,
11753                                                                      AP_ID_AA64DFR1_EL1, AP_ID_AA64ISAR0_EL1, AP_ID_AA64ISAR1_EL1,
11754                                                                      AP_ID_AA64MMFR0_EL1, AP_ID_AA64MMFR1_EL1, AP_ID_AA64AFR0_EL1,
11755                                                                      AP_ID_AA64AFR1_EL1. */
11756         uint64_t tid2                  : 1;  /**< [ 17: 17](R/W) Trap ID Group 2. When this bit is set to 1, this causes reads
11757                                                                      (or writes to CSSELR/ AP_CSSELR_EL1) to the following registers
11758                                                                      executed from EL1 or EL0 if not UNdefined to be trapped to
11759                                                                      EL2:
11760 
11761                                                                  AArch32: CTR, CCSIDR, CLIDR, CSSELR.
11762 
11763                                                                  AArch64: AP_CTR_EL0, AP_CCSIDR_EL1, AP_CLIDR_EL1, AP_CSSELR_EL1. */
11764         uint64_t tid1                  : 1;  /**< [ 16: 16](R/W) Trap ID Group 1. When this bit is set to 1, this causes reads
11765                                                                      to the following registers executed from EL1 to be trapped to
11766                                                                      EL2:
11767 
11768                                                                  AArch32: TCMTR, TLBTR, AIDR, REVIDR.
11769 
11770                                                                  AArch64: AP_AIDR_EL1, AP_REVIDR_EL1. */
11771         uint64_t tid0                  : 1;  /**< [ 15: 15](R/W) Trap ID Group 0. When this bit is set to 1, this causes reads
11772                                                                      to the following registers executed from EL1 or EL0 if not
11773                                                                      UNdefined to be trapped to EL2:
11774 
11775                                                                  AArch32: FPSID, JIDR.
11776 
11777                                                                  AArch64: None. */
11778         uint64_t twe                   : 1;  /**< [ 14: 14](R/W) Trap WFE. When this bit is set to 1, this causes the following
11779                                                                      instructions executed from EL1 or EL0 to be trapped to EL2 if
11780                                                                      the instruction would otherwise cause suspension of execution
11781                                                                      (i.e. if the event register is not set):
11782 
11783                                                                  AArch32: WFE.
11784 
11785                                                                  AArch64: WFE.
11786 
11787                                                                  Conditional WFE instructions that fail their condition are not
11788                                                                      trapped if this bit is set to 1. */
11789         uint64_t twi                   : 1;  /**< [ 13: 13](R/W) Trap WFI. When this bit is set to 1, this causes the following
11790                                                                      instructions executed from EL1 or EL0 to be trapped to EL2 if
11791                                                                      the instruction would otherwise cause suspension of execution
11792                                                                      (i.e. if there is not a pending WFI wakeup event):
11793 
11794                                                                  AArch32: WFI.
11795 
11796                                                                  AArch64: WFI.
11797 
11798                                                                  Conditional WFI instructions that fail their condition are not
11799                                                                      trapped if this bit is set to 1. */
11800         uint64_t dc                    : 1;  /**< [ 12: 12](R/W) Default Cacheable. When this bit is set to 1, this causes:
11801 
11802                                                                  * The AP_SCTLR_EL1[M] bit to behave as 0 when in the nonsecure
11803                                                                      state for all purposes other than reading the value of the
11804                                                                      bit.
11805 
11806                                                                  * The AP_HCR_EL2[VM] bit to behave as 1 when in the nonsecure
11807                                                                      state for all purposes other than reading the value of the
11808                                                                      bit.
11809 
11810                                                                  The memory type produced by the first stage of translation
11811                                                                      used by EL1 and EL0 is Normal Non-Shareable, Inner WriteBack
11812                                                                      Read-WriteAllocate, Outer WriteBack Read-WriteAllocate.
11813 
11814                                                                  When this bit is 0 and the stage 1 MMU is disabled, the
11815                                                                      default memory attribute for Data accesses is Device-nGnRnE.
11816 
11817                                                                  This bit is permitted to be cached in a TLB. */
11818         uint64_t bsu                   : 2;  /**< [ 11: 10](R/W) Barrier Shareability upgrade. The value in this field
11819                                                                      determines the minimum shareability domain that is applied to
11820                                                                      any barrier executed from EL1 or EL0.
11821 
11822                                                                  This value is combined with the specified level of the barrier
11823                                                                      held in its instruction, using the same principles as
11824                                                                      combining the shareability attributes from two stages of
11825                                                                      address translation.
11826 
11827                                                                  0x0 = No effect.
11828                                                                  0x1 = Inner Shareable.
11829                                                                  0x2 = Outer Shareable.
11830                                                                  0x3 = Full system. */
11831         uint64_t fb                    : 1;  /**< [  9:  9](R/W) Force broadcast. When this bit is set to 1, this causes the
11832                                                                      following instructions to be broadcast within the Inner
11833                                                                      Shareable domain when executed from nonsecure EL1:
11834 
11835                                                                  AArch32: BPIALL, TLBIALL, TLBIMVA, TLBIASID, DTLBIALL,
11836                                                                      DTLBIMVA, DTLBIASID, ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA,
11837                                                                      ICIALLU, TLBIMVAL, TLBIMVAAL.
11838 
11839                                                                  AArch64: TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
11840                                                                      TLBI VALE1, TLBI VAALE1, IC IALLU. */
11841         uint64_t vse                   : 1;  /**< [  8:  8](R/W) Virtual System Error/Asynchronous Abort.
11842                                                                  The virtual System Error/Asynchronous Abort is only enabled
11843                                                                      when the AP_HCR_EL2[AMO] bit is set.
11844                                                                  0 = Virtual System Error/Asynchronous Abort is not pending by this
11845                                                                      mechanism.
11846                                                                  1 = Virtual System Error/Asynchronous Abort is pending by this
11847                                                                      mechanism. */
11848         uint64_t vi                    : 1;  /**< [  7:  7](R/W) Virtual IRQ Interrupt.
11849                                                                  The virtual IRQ is only enabled when the AP_HCR_EL2[IMO] bit is
11850                                                                      set.
11851                                                                  0 = Virtual IRQ is not pending by this mechanism.
11852                                                                  1 = Virtual IRQ is pending by this mechanism. */
11853         uint64_t vf                    : 1;  /**< [  6:  6](R/W) Virtual FIQ Interrupt.
11854                                                                  The virtual FIQ is only enabled when the AP_HCR_EL2[FMO] bit is
11855                                                                      set.
11856                                                                  0 = Virtual FIQ is not pending by this mechanism.
11857                                                                  1 = Virtual FIQ is pending by this mechanism. */
11858         uint64_t amo                   : 1;  /**< [  5:  5](R/W) Asynchronous abort and error interrupt routing.
11859                                                                  0 = Asynchronous External Aborts and SError Interrupts while
11860                                                                      executing at exception levels lower than EL2 are not taken in
11861                                                                      EL2. Virtual System Error/Asynchronous Abort is disabled.
11862                                                                  1 = Asynchronous External Aborts and SError Interrupts while
11863                                                                      executing at EL2 or lower are taken in EL2 unless routed by
11864                                                                      the AP_SCR_EL3[EA] bit to EL3. Virtual System Error/Asynchronous
11865                                                                      Abort is enabled. */
11866         uint64_t imo                   : 1;  /**< [  4:  4](R/W) Physical IRQ Routing.
11867                                                                  0 = Physical IRQ while executing at exception levels lower than
11868                                                                      EL2 are not taken in EL2. Virtual IRQ Interrupt is disabled.
11869                                                                  1 = Physical IRQ while executing at EL2 or lower are taken in EL2
11870                                                                      unless routed by the AP_SCR_EL3[IRQ] bit to EL3. Virtual IRQ
11871                                                                      Interrupt is enabled. */
11872         uint64_t fmo                   : 1;  /**< [  3:  3](R/W) Physical FIQ Routing.
11873                                                                  0 = Physical FIQ while executing at exception levels lower than
11874                                                                      EL2 are not taken in EL2. Virtual FIQ Interrupt is disabled.
11875                                                                  1 = Physical FIQ while executing at EL2 or lower are taken in EL2
11876                                                                      unless routed by the AP_SCR_EL3[FIQ] bit to EL3. Virtual FIQ
11877                                                                      Interrupt is enabled. */
11878         uint64_t ptw                   : 1;  /**< [  2:  2](R/W) Protected Table Walk. When this bit is set to 1, if the stage
11879                                                                      2 translation of a translation table access made as part of a
11880                                                                      stage 1 translation table walk at EL0 or EL1 maps that
11881                                                                      translation table access to Strongly-ordered or Device memory,
11882                                                                      the access is faulted as a stage 2 Permission fault.
11883                                                                  This bit is permitted to be cached in a TLB. */
11884         uint64_t swio                  : 1;  /**< [  1:  1](R/W) Set/Way Invalidation Override. When this bit is set to 1, this
11885                                                                      causes EL1 execution of the data cache invalidate by set/way
11886                                                                      instruction to be treated as data cache clean and invalidate
11887                                                                      by set/way. That is:
11888 
11889                                                                  AArch32: DCISW is executed as DCCISW.
11890 
11891                                                                  AArch64: DC ISW is executed as DC CISW.
11892 
11893                                                                  As a result of changes to the behavior of DCISW, this bit is
11894                                                                      redundant in ARMv8. It is permissible that an implementation
11895                                                                      makes this bit RES1. */
11896         uint64_t vm                    : 1;  /**< [  0:  0](R/W) Virtualization MMU enable for EL1 and EL0 stage 2 address
11897                                                                      translation.
11898                                                                  This bit is permitted to be cached in a TLB.
11899                                                                  0 = EL1 and EL0 stage 2 address translation disabled.
11900                                                                  1 = EL1 and EL0 stage 2 address translation enabled. */
11901 #else /* Word 0 - Little Endian */
11902         uint64_t vm                    : 1;  /**< [  0:  0](R/W) Virtualization MMU enable for EL1 and EL0 stage 2 address
11903                                                                      translation.
11904                                                                  This bit is permitted to be cached in a TLB.
11905                                                                  0 = EL1 and EL0 stage 2 address translation disabled.
11906                                                                  1 = EL1 and EL0 stage 2 address translation enabled. */
11907         uint64_t swio                  : 1;  /**< [  1:  1](R/W) Set/Way Invalidation Override. When this bit is set to 1, this
11908                                                                      causes EL1 execution of the data cache invalidate by set/way
11909                                                                      instruction to be treated as data cache clean and invalidate
11910                                                                      by set/way. That is:
11911 
11912                                                                  AArch32: DCISW is executed as DCCISW.
11913 
11914                                                                  AArch64: DC ISW is executed as DC CISW.
11915 
11916                                                                  As a result of changes to the behavior of DCISW, this bit is
11917                                                                      redundant in ARMv8. It is permissible that an implementation
11918                                                                      makes this bit RES1. */
11919         uint64_t ptw                   : 1;  /**< [  2:  2](R/W) Protected Table Walk. When this bit is set to 1, if the stage
11920                                                                      2 translation of a translation table access made as part of a
11921                                                                      stage 1 translation table walk at EL0 or EL1 maps that
11922                                                                      translation table access to Strongly-ordered or Device memory,
11923                                                                      the access is faulted as a stage 2 Permission fault.
11924                                                                  This bit is permitted to be cached in a TLB. */
11925         uint64_t fmo                   : 1;  /**< [  3:  3](R/W) Physical FIQ Routing.
11926                                                                  0 = Physical FIQ while executing at exception levels lower than
11927                                                                      EL2 are not taken in EL2. Virtual FIQ Interrupt is disabled.
11928                                                                  1 = Physical FIQ while executing at EL2 or lower are taken in EL2
11929                                                                      unless routed by the AP_SCR_EL3[FIQ] bit to EL3. Virtual FIQ
11930                                                                      Interrupt is enabled. */
11931         uint64_t imo                   : 1;  /**< [  4:  4](R/W) Physical IRQ Routing.
11932                                                                  0 = Physical IRQ while executing at exception levels lower than
11933                                                                      EL2 are not taken in EL2. Virtual IRQ Interrupt is disabled.
11934                                                                  1 = Physical IRQ while executing at EL2 or lower are taken in EL2
11935                                                                      unless routed by the AP_SCR_EL3[IRQ] bit to EL3. Virtual IRQ
11936                                                                      Interrupt is enabled. */
11937         uint64_t amo                   : 1;  /**< [  5:  5](R/W) Asynchronous abort and error interrupt routing.
11938                                                                  0 = Asynchronous External Aborts and SError Interrupts while
11939                                                                      executing at exception levels lower than EL2 are not taken in
11940                                                                      EL2. Virtual System Error/Asynchronous Abort is disabled.
11941                                                                  1 = Asynchronous External Aborts and SError Interrupts while
11942                                                                      executing at EL2 or lower are taken in EL2 unless routed by
11943                                                                      the AP_SCR_EL3[EA] bit to EL3. Virtual System Error/Asynchronous
11944                                                                      Abort is enabled. */
11945         uint64_t vf                    : 1;  /**< [  6:  6](R/W) Virtual FIQ Interrupt.
11946                                                                  The virtual FIQ is only enabled when the AP_HCR_EL2[FMO] bit is
11947                                                                      set.
11948                                                                  0 = Virtual FIQ is not pending by this mechanism.
11949                                                                  1 = Virtual FIQ is pending by this mechanism. */
11950         uint64_t vi                    : 1;  /**< [  7:  7](R/W) Virtual IRQ Interrupt.
11951                                                                  The virtual IRQ is only enabled when the AP_HCR_EL2[IMO] bit is
11952                                                                      set.
11953                                                                  0 = Virtual IRQ is not pending by this mechanism.
11954                                                                  1 = Virtual IRQ is pending by this mechanism. */
11955         uint64_t vse                   : 1;  /**< [  8:  8](R/W) Virtual System Error/Asynchronous Abort.
11956                                                                  The virtual System Error/Asynchronous Abort is only enabled
11957                                                                      when the AP_HCR_EL2[AMO] bit is set.
11958                                                                  0 = Virtual System Error/Asynchronous Abort is not pending by this
11959                                                                      mechanism.
11960                                                                  1 = Virtual System Error/Asynchronous Abort is pending by this
11961                                                                      mechanism. */
11962         uint64_t fb                    : 1;  /**< [  9:  9](R/W) Force broadcast. When this bit is set to 1, this causes the
11963                                                                      following instructions to be broadcast within the Inner
11964                                                                      Shareable domain when executed from nonsecure EL1:
11965 
11966                                                                  AArch32: BPIALL, TLBIALL, TLBIMVA, TLBIASID, DTLBIALL,
11967                                                                      DTLBIMVA, DTLBIASID, ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA,
11968                                                                      ICIALLU, TLBIMVAL, TLBIMVAAL.
11969 
11970                                                                  AArch64: TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
11971                                                                      TLBI VALE1, TLBI VAALE1, IC IALLU. */
11972         uint64_t bsu                   : 2;  /**< [ 11: 10](R/W) Barrier Shareability upgrade. The value in this field
11973                                                                      determines the minimum shareability domain that is applied to
11974                                                                      any barrier executed from EL1 or EL0.
11975 
11976                                                                  This value is combined with the specified level of the barrier
11977                                                                      held in its instruction, using the same principles as
11978                                                                      combining the shareability attributes from two stages of
11979                                                                      address translation.
11980 
11981                                                                  0x0 = No effect.
11982                                                                  0x1 = Inner Shareable.
11983                                                                  0x2 = Outer Shareable.
11984                                                                  0x3 = Full system. */
11985         uint64_t dc                    : 1;  /**< [ 12: 12](R/W) Default Cacheable. When this bit is set to 1, this causes:
11986 
11987                                                                  * The AP_SCTLR_EL1[M] bit to behave as 0 when in the nonsecure
11988                                                                      state for all purposes other than reading the value of the
11989                                                                      bit.
11990 
11991                                                                  * The AP_HCR_EL2[VM] bit to behave as 1 when in the nonsecure
11992                                                                      state for all purposes other than reading the value of the
11993                                                                      bit.
11994 
11995                                                                  The memory type produced by the first stage of translation
11996                                                                      used by EL1 and EL0 is Normal Non-Shareable, Inner WriteBack
11997                                                                      Read-WriteAllocate, Outer WriteBack Read-WriteAllocate.
11998 
11999                                                                  When this bit is 0 and the stage 1 MMU is disabled, the
12000                                                                      default memory attribute for Data accesses is Device-nGnRnE.
12001 
12002                                                                  This bit is permitted to be cached in a TLB. */
12003         uint64_t twi                   : 1;  /**< [ 13: 13](R/W) Trap WFI. When this bit is set to 1, this causes the following
12004                                                                      instructions executed from EL1 or EL0 to be trapped to EL2 if
12005                                                                      the instruction would otherwise cause suspension of execution
12006                                                                      (i.e. if there is not a pending WFI wakeup event):
12007 
12008                                                                  AArch32: WFI.
12009 
12010                                                                  AArch64: WFI.
12011 
12012                                                                  Conditional WFI instructions that fail their condition are not
12013                                                                      trapped if this bit is set to 1. */
12014         uint64_t twe                   : 1;  /**< [ 14: 14](R/W) Trap WFE. When this bit is set to 1, this causes the following
12015                                                                      instructions executed from EL1 or EL0 to be trapped to EL2 if
12016                                                                      the instruction would otherwise cause suspension of execution
12017                                                                      (i.e. if the event register is not set):
12018 
12019                                                                  AArch32: WFE.
12020 
12021                                                                  AArch64: WFE.
12022 
12023                                                                  Conditional WFE instructions that fail their condition are not
12024                                                                      trapped if this bit is set to 1. */
12025         uint64_t tid0                  : 1;  /**< [ 15: 15](R/W) Trap ID Group 0. When this bit is set to 1, this causes reads
12026                                                                      to the following registers executed from EL1 or EL0 if not
12027                                                                      UNdefined to be trapped to EL2:
12028 
12029                                                                  AArch32: FPSID, JIDR.
12030 
12031                                                                  AArch64: None. */
12032         uint64_t tid1                  : 1;  /**< [ 16: 16](R/W) Trap ID Group 1. When this bit is set to 1, this causes reads
12033                                                                      to the following registers executed from EL1 to be trapped to
12034                                                                      EL2:
12035 
12036                                                                  AArch32: TCMTR, TLBTR, AIDR, REVIDR.
12037 
12038                                                                  AArch64: AP_AIDR_EL1, AP_REVIDR_EL1. */
12039         uint64_t tid2                  : 1;  /**< [ 17: 17](R/W) Trap ID Group 2. When this bit is set to 1, this causes reads
12040                                                                      (or writes to CSSELR/ AP_CSSELR_EL1) to the following registers
12041                                                                      executed from EL1 or EL0 if not UNdefined to be trapped to
12042                                                                      EL2:
12043 
12044                                                                  AArch32: CTR, CCSIDR, CLIDR, CSSELR.
12045 
12046                                                                  AArch64: AP_CTR_EL0, AP_CCSIDR_EL1, AP_CLIDR_EL1, AP_CSSELR_EL1. */
12047         uint64_t tid3                  : 1;  /**< [ 18: 18](R/W) Trap ID Group 3. When this bit is set to 1, this causes reads
12048                                                                      to the following registers executed from EL1 to be trapped to
12049                                                                      EL2:
12050 
12051                                                                  AArch32: ID_PFR0, ID_PFR1, ID_DFR0, ID_AFR0, ID_MMFR0,
12052                                                                      ID_MMFR1, ID_MMFR2, ID_MMFR3, ID_ISAR0, ID_ISAR1, ID_ISAR2,
12053                                                                      ID_ISAR3, ID_ISAR4, ID_ISAR5, MVFR0, MVFR1, MVFR2. Also MRC to
12054                                                                      any of the following encodings:
12055 
12056                                                                   CP15, CRn == 0, Opc1 == 0, CRm == {3-7}, Opc2 == {0,1}.
12057 
12058                                                                   CP15, CRn == 0, Opc1 == 0, CRm == 3, Opc2 == 2.
12059 
12060                                                                   CP15, CRn == 0, Opc1 == 0, CRm == 5, Opc2 == {4,5}.
12061 
12062                                                                  AArch64: AP_ID_PFR0_EL1, AP_ID_PFR1_EL1, AP_ID_DFR0_EL1, AP_ID_AFR0_EL1,
12063                                                                      ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1,
12064                                                                      ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1,
12065                                                                      ID_ISAR4_EL1, ID_ISAR5_EL1, MVFR0_EL1, MVFR1_EL1, MVFR2_EL1,
12066                                                                      AP_ID_AA64PFR0_EL1, AP_ID_AA64PFR1_EL1, AP_ID_AA64DFR0_EL1,
12067                                                                      AP_ID_AA64DFR1_EL1, AP_ID_AA64ISAR0_EL1, AP_ID_AA64ISAR1_EL1,
12068                                                                      AP_ID_AA64MMFR0_EL1, AP_ID_AA64MMFR1_EL1, AP_ID_AA64AFR0_EL1,
12069                                                                      AP_ID_AA64AFR1_EL1. */
12070         uint64_t tsc                   : 1;  /**< [ 19: 19](R/W) Trap SMC. When this bit is set to 1, this causes the following
12071                                                                      instructions executed from EL1 to be trapped to EL2:
12072 
12073                                                                  AArch32: SMC.
12074 
12075                                                                  AArch64: SMC.
12076 
12077                                                                  If EL3 is not implemented, this bit is RES0. */
12078         uint64_t tidcp                 : 1;  /**< [ 20: 20](R/W) Trap Implementation Dependent functionality. When this bit is
12079                                                                      set to 1, this causes accesses to the following instruction
12080                                                                      set space executed from EL1 to be trapped to EL2.
12081 
12082                                                                  AArch32: MCR and MRC instructions as follows:
12083 
12084                                                                   All CP15, CRn==9,  Opcode1 = {0-7}, CRm == {c0-c2, c5-c8},
12085                                                                      opcode2 == {0-7}.
12086 
12087                                                                   All CP15, CRn==10, Opcode1 =={0-7}, CRm == {c0, c1, c4, c8},
12088                                                                      opcode2 == {0-7}.
12089 
12090                                                                   All CP15, CRn==11, Opcode1=={0-7}, CRm == {c0-c8, c15},
12091                                                                      opcode2 == {0-7}.
12092 
12093                                                                  AArch64: All encoding space reserved for implementation
12094                                                                      defined system operations ( S1_\<op1\>_\<Cn\>_\<Cm\>_\<op2\>) and
12095                                                                      system registers ( S3_\<op1\>_\<Cn\>_\<Cm\>_\<op2\>).
12096 
12097                                                                  It is implementation defined whether any of this functionality
12098                                                                      accessed from EL0 is trapped to EL2 when the AP_HCR_EL2[TIDCP] bit
12099                                                                      is set. If it is not trapped to EL2, it results in an
12100                                                                      Undefined exception taken to EL1. */
12101         uint64_t tacr                  : 1;  /**< [ 21: 21](R/W) Trap Auxiliary Control Register. When this bit is set to 1,
12102                                                                      this causes accesses to the following registers executed from
12103                                                                      EL1 to be trapped to EL2:
12104 
12105                                                                  AArch32: ACTLR.
12106 
12107                                                                  AArch64: ACTLR_EL1. */
12108         uint64_t tsw                   : 1;  /**< [ 22: 22](R/W) Trap Data/Unified Cache maintenance operations by Set/Way.
12109                                                                      When this bit is set to 1, this causes Data or Unified Cache
12110                                                                      maintenance instructions by set/way executed from EL1 which
12111                                                                      are not UNdefined to be trapped to EL2. This covers the
12112                                                                      following instructions:
12113 
12114                                                                  AArch32: DCISW, DCCSW, DCCISW.
12115 
12116                                                                  AArch64: DC ISW, DC CSW, DC CISW. */
12117         uint64_t tpc                   : 1;  /**< [ 23: 23](R/W) Trap Data/Unified Cache maintenance operations to Point of
12118                                                                      Coherency. When this bit is set to 1, this causes Data or
12119                                                                      Unified Cache maintenance instructions by address to the point
12120                                                                      of coherency executed from EL1 or EL0 which are not UNdefined
12121                                                                      to be trapped to EL2. This covers the following instructions:
12122 
12123                                                                  AArch32: DCIMVAC, DCCIMVAC, DCCMVAC.
12124 
12125                                                                  AArch64: DC IVAC, DC CIVAC, DC CVAC. */
12126         uint64_t tpu                   : 1;  /**< [ 24: 24](R/W) Trap Cache maintenance instructions to Point of Unification.
12127                                                                      When this bit is set to 1, this causes Cache maintenance
12128                                                                      instructions to the point of unification executed from EL1 or
12129                                                                      EL0 which are not UNdefined to be trapped to EL2. This covers
12130                                                                      the following instructions:
12131 
12132                                                                  AArch32: ICIMVAU, ICIALLU, ICIALLUIS, DCCMVAU.
12133 
12134                                                                  AArch64: IC IVAU, IC IALLU, IC IALLUIS, DC CVAU. */
12135         uint64_t ttlb                  : 1;  /**< [ 25: 25](R/W) Trap TLB maintenance instructions. When this bit is set to 1,
12136                                                                      this causes TLB maintenance instructions executed from EL1
12137                                                                      which are not UNdefined to be trapped to EL2. This covers the
12138                                                                      following instructions:
12139 
12140                                                                  AArch32: TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS,
12141                                                                      TLBIALL, TLBIMVA, TLBIASID, DTLBIALL, DTLBIMVA, DTLBIASID,
12142                                                                      ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA, TLBIMVALIS,
12143                                                                      TLBIMVAALIS, TLBIMVAL, TLBIMVAAL
12144 
12145                                                                  AArch64: TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
12146                                                                      TLBI VALE1, TLBI VAALE1, TLBI VMALLE1IS, TLBI VAE1IS, TLBI
12147                                                                      ASIDE1IS, TLBI VAAE1IS, TLBI VALE1IS, TLBI VAALE1IS */
12148         uint64_t tvm                   : 1;  /**< [ 26: 26](R/W) Trap Virtual Memory controls. When this bit is set to 1, this
12149                                                                      causes Writes to the EL1 virtual memory control registers from
12150                                                                      EL1 to be trapped to EL2. This covers the following registers:
12151 
12152                                                                  AArch32: SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR,
12153                                                                      IFAR, ADFSR, AIFSR, PRRR/ MAIR0, NMRR/ MAIR1, AMAIR0, AMAIR1,
12154                                                                      CONTEXTIDR.
12155 
12156                                                                  AArch64: AP_SCTLR_EL1, AP_TTBR0_EL1, AP_TTBR1_EL1, AP_TCR_EL1, ESR_EL1,
12157                                                                      FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1,
12158                                                                      AP_CONTEXTIDR_EL1 */
12159         uint64_t tge                   : 1;  /**< [ 27: 27](R/W) Trap General Exceptions. If this bit is set to 1, and
12160                                                                      AP_SCR_EL3[NS] is set to 1, then:
12161 
12162                                                                   All exceptions that would be routed to EL1 are routed to EL2.
12163 
12164                                                                   The AP_SCTLR_EL1[M] bit is treated as being 0 regardless of its
12165                                                                      actual state (for EL1 using AArch32 or AArch64) other than for
12166                                                                      the purpose of reading the bit.
12167 
12168                                                                   The AP_HCR_EL2[FMO], IMO and AMO bits are treated as being 1
12169                                                                      regardless of their actual state other than for the purpose of
12170                                                                      reading the bits.
12171 
12172                                                                   All virtual interrupts are disabled.
12173 
12174                                                                   Any implementation defined mechanisms for signalling virtual
12175                                                                      interrupts are disabled.
12176 
12177                                                                   An exception return to EL1 is treated as an illegal exception
12178                                                                      return.
12179 
12180                                                                  Additionally, if AP_HCR_EL2[TGE] == 1, the
12181                                                                      AP_MDCR_EL2.{TDRA,TDOSA,TDA} bits are ignored and the processor
12182                                                                      behaves as if they are set to 1, other than for the value read
12183                                                                      back from AP_MDCR_EL2. */
12184         uint64_t tdz                   : 1;  /**< [ 28: 28](R/W) Trap DC ZVA instruction:
12185                                                                  This bit also has an effect on the value read from the
12186                                                                      AP_DCZID_EL0 register. If this bit is 1, then reading
12187                                                                      AP_DCZID_EL0[DZP] from nonsecure EL1 or EL0 will return 1 to
12188                                                                      indicate that DC ZVA is prohibited.
12189                                                                  0 = The instruction is not trapped.
12190                                                                  1 = The instruction is trapped to EL2 when executed in nonsecure
12191                                                                      EL1 or EL0. */
12192         uint64_t reserved_29           : 1;
12193         uint64_t trvm                  : 1;  /**< [ 30: 30](R/W) Trap Read of Virtual Memory controls. When this bit is set to
12194                                                                      1, this causes Reads to the EL1 virtual memory control
12195                                                                      registers from EL1 to be trapped to EL2. This covers the
12196                                                                      following registers:
12197 
12198                                                                  AArch32: SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR,
12199                                                                      IFAR, ADFSR, AIFSR, PRRR/ MAIR0, NMRR/ MAIR1, AMAIR0, AMAIR1,
12200                                                                      CONTEXTIDR.
12201 
12202                                                                  AArch64: AP_SCTLR_EL1, AP_TTBR0_EL1, AP_TTBR1_EL1, AP_TCR_EL1, ESR_EL1,
12203                                                                      FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1,
12204                                                                      AP_CONTEXTIDR_EL1. */
12205         uint64_t rsvd_31               : 1;  /**< [ 31: 31](RO) rw - Register Width control for lower exception levels:
12206                                                                  When AP_SCR_EL3[NS]==0, this bit behaves as if it has the same
12207                                                                      value as the AP_SCR_EL3[RW] bit except for the value read back.
12208                                                                  The RW bit is permitted to be cached in a TLB.
12209                                                                  0 = Lower levels are all AArch32.
12210                                                                  1 = EL1 is AArch64. EL0 is determined by the Execution state
12211                                                                      described in the current process state when executing at EL0. */
12212         uint64_t cd                    : 1;  /**< [ 32: 32](R/W) Stage 2 Data cache disable. When AP_HCR_EL2[VM]==1, this forces
12213                                                                      all stage 2 translations for data accesses and translation
12214                                                                      table walks to Normal memory to be Non-cacheable for the EL1&0
12215                                                                      translation regime.
12216                                                                  This bit has no effect on the EL2 or EL3 translation regimes.
12217                                                                  0 = No effect on the stage 2 of the EL1&0 translation regime for
12218                                                                      data accesses and translation table walks.
12219                                                                  1 = Forces all stage 2 translations for data accesses and
12220                                                                      translation table walks to Normal memory to be Non-cacheable
12221                                                                      for the EL1&0 translation regime. */
12222         uint64_t id                    : 1;  /**< [ 33: 33](R/W) Stage 2 Instruction cache disable. When AP_HCR_EL2[VM]==1, this
12223                                                                      forces all stage 2 translations for instruction accesses to
12224                                                                      Normal memory to be Non-cacheable for the EL1&0 translation
12225                                                                      regime.
12226                                                                  This bit has no effect on the EL2 or EL3 translation regimes.
12227                                                                  0 = No effect on the stage 2 of the EL1&0 translation regime for
12228                                                                      instruction accesses.
12229                                                                  1 = Forces all stage 2 translations for instruction accesses to
12230                                                                      Normal memory to be Non-cacheable for the EL1&0 translation
12231                                                                      regime. */
12232         uint64_t e2h                   : 1;  /**< [ 34: 34](R/W) V8.1: Enable EL2 host. */
12233         uint64_t tlor                  : 1;  /**< [ 35: 35](R/W) v8.1: Trap access to the LOR Registers from nonsecure EL1 to EL2.
12234                                                                  0 = Nonsecure EL1 accesses to the LOR Registers are not trapped to EL2.
12235                                                                  1 = Nonsecure EL1 accesses to the LOR Registers are trapped to EL2. */
12236         uint64_t terr                  : 1;  /**< [ 36: 36](R/W) RAS: Trap Error record accesses.
12237                                                                    0 = Do not trap accesses to error record registers from Non-secure EL1 to EL2.
12238                                                                    1 = Accesses to the ER* registers from Non-secure EL1 generate a Trap exception to EL2. */
12239         uint64_t tea                   : 1;  /**< [ 37: 37](R/W) RAS: Route synchronous external aborts to EL2.
12240                                                                    0 = Do not route synchronous external aborts from Non-secure EL0 and EL1 to EL2.
12241                                                                    1 = Route synchronous external aborts from Non-secure EL0 and EL1 to EL2, if not routed
12242                                                                  to EL3. */
12243         uint64_t reserved_38_63        : 26;
12244 #endif /* Word 0 - End */
12245     } s;
12246     struct bdk_ap_hcr_el2_cn8
12247     {
12248 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12249         uint64_t reserved_36_63        : 28;
12250         uint64_t tlor                  : 1;  /**< [ 35: 35](R/W) v8.1: Trap access to the LOR Registers from nonsecure EL1 to EL2.
12251                                                                  0 = Nonsecure EL1 accesses to the LOR Registers are not trapped to EL2.
12252                                                                  1 = Nonsecure EL1 accesses to the LOR Registers are trapped to EL2. */
12253         uint64_t e2h                   : 1;  /**< [ 34: 34](R/W) V8.1: Enable EL2 host. */
12254         uint64_t id                    : 1;  /**< [ 33: 33](R/W) Stage 2 Instruction cache disable. When AP_HCR_EL2[VM]==1, this
12255                                                                      forces all stage 2 translations for instruction accesses to
12256                                                                      Normal memory to be Non-cacheable for the EL1&0 translation
12257                                                                      regime.
12258                                                                  This bit has no effect on the EL2 or EL3 translation regimes.
12259                                                                  0 = No effect on the stage 2 of the EL1&0 translation regime for
12260                                                                      instruction accesses.
12261                                                                  1 = Forces all stage 2 translations for instruction accesses to
12262                                                                      Normal memory to be Non-cacheable for the EL1&0 translation
12263                                                                      regime. */
12264         uint64_t cd                    : 1;  /**< [ 32: 32](R/W) Stage 2 Data cache disable. When AP_HCR_EL2[VM]==1, this forces
12265                                                                      all stage 2 translations for data accesses and translation
12266                                                                      table walks to Normal memory to be Non-cacheable for the EL1&0
12267                                                                      translation regime.
12268                                                                  This bit has no effect on the EL2 or EL3 translation regimes.
12269                                                                  0 = No effect on the stage 2 of the EL1&0 translation regime for
12270                                                                      data accesses and translation table walks.
12271                                                                  1 = Forces all stage 2 translations for data accesses and
12272                                                                      translation table walks to Normal memory to be Non-cacheable
12273                                                                      for the EL1&0 translation regime. */
12274         uint64_t rsvd_31               : 1;  /**< [ 31: 31](RO) rw - Register Width control for lower exception levels:
12275                                                                  When AP_SCR_EL3[NS]==0, this bit behaves as if it has the same
12276                                                                      value as the AP_SCR_EL3[RW] bit except for the value read back.
12277                                                                  The RW bit is permitted to be cached in a TLB.
12278                                                                  0 = Lower levels are all AArch32.
12279                                                                  1 = EL1 is AArch64. EL0 is determined by the Execution state
12280                                                                      described in the current process state when executing at EL0. */
12281         uint64_t trvm                  : 1;  /**< [ 30: 30](R/W) Trap Read of Virtual Memory controls. When this bit is set to
12282                                                                      1, this causes Reads to the EL1 virtual memory control
12283                                                                      registers from EL1 to be trapped to EL2. This covers the
12284                                                                      following registers:
12285 
12286                                                                  AArch32: SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR,
12287                                                                      IFAR, ADFSR, AIFSR, PRRR/ MAIR0, NMRR/ MAIR1, AMAIR0, AMAIR1,
12288                                                                      CONTEXTIDR.
12289 
12290                                                                  AArch64: AP_SCTLR_EL1, AP_TTBR0_EL1, AP_TTBR1_EL1, AP_TCR_EL1, ESR_EL1,
12291                                                                      FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1,
12292                                                                      AP_CONTEXTIDR_EL1. */
12293         uint64_t reserved_29           : 1;
12294         uint64_t tdz                   : 1;  /**< [ 28: 28](R/W) Trap DC ZVA instruction:
12295                                                                  This bit also has an effect on the value read from the
12296                                                                      AP_DCZID_EL0 register. If this bit is 1, then reading
12297                                                                      AP_DCZID_EL0[DZP] from nonsecure EL1 or EL0 will return 1 to
12298                                                                      indicate that DC ZVA is prohibited.
12299                                                                  0 = The instruction is not trapped.
12300                                                                  1 = The instruction is trapped to EL2 when executed in nonsecure
12301                                                                      EL1 or EL0. */
12302         uint64_t tge                   : 1;  /**< [ 27: 27](R/W) Trap General Exceptions. If this bit is set to 1, and
12303                                                                      AP_SCR_EL3[NS] is set to 1, then:
12304 
12305                                                                   All exceptions that would be routed to EL1 are routed to EL2.
12306 
12307                                                                   The AP_SCTLR_EL1[M] bit is treated as being 0 regardless of its
12308                                                                      actual state (for EL1 using AArch32 or AArch64) other than for
12309                                                                      the purpose of reading the bit.
12310 
12311                                                                   The AP_HCR_EL2[FMO], IMO and AMO bits are treated as being 1
12312                                                                      regardless of their actual state other than for the purpose of
12313                                                                      reading the bits.
12314 
12315                                                                   All virtual interrupts are disabled.
12316 
12317                                                                   Any implementation defined mechanisms for signalling virtual
12318                                                                      interrupts are disabled.
12319 
12320                                                                   An exception return to EL1 is treated as an illegal exception
12321                                                                      return.
12322 
12323                                                                  Additionally, if AP_HCR_EL2[TGE] == 1, the
12324                                                                      AP_MDCR_EL2.{TDRA,TDOSA,TDA} bits are ignored and the processor
12325                                                                      behaves as if they are set to 1, other than for the value read
12326                                                                      back from AP_MDCR_EL2. */
12327         uint64_t tvm                   : 1;  /**< [ 26: 26](R/W) Trap Virtual Memory controls. When this bit is set to 1, this
12328                                                                      causes Writes to the EL1 virtual memory control registers from
12329                                                                      EL1 to be trapped to EL2. This covers the following registers:
12330 
12331                                                                  AArch32: SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR,
12332                                                                      IFAR, ADFSR, AIFSR, PRRR/ MAIR0, NMRR/ MAIR1, AMAIR0, AMAIR1,
12333                                                                      CONTEXTIDR.
12334 
12335                                                                  AArch64: AP_SCTLR_EL1, AP_TTBR0_EL1, AP_TTBR1_EL1, AP_TCR_EL1, ESR_EL1,
12336                                                                      FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1,
12337                                                                      AP_CONTEXTIDR_EL1 */
12338         uint64_t ttlb                  : 1;  /**< [ 25: 25](R/W) Trap TLB maintenance instructions. When this bit is set to 1,
12339                                                                      this causes TLB maintenance instructions executed from EL1
12340                                                                      which are not UNdefined to be trapped to EL2. This covers the
12341                                                                      following instructions:
12342 
12343                                                                  AArch32: TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS,
12344                                                                      TLBIALL, TLBIMVA, TLBIASID, DTLBIALL, DTLBIMVA, DTLBIASID,
12345                                                                      ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA, TLBIMVALIS,
12346                                                                      TLBIMVAALIS, TLBIMVAL, TLBIMVAAL
12347 
12348                                                                  AArch64: TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
12349                                                                      TLBI VALE1, TLBI VAALE1, TLBI VMALLE1IS, TLBI VAE1IS, TLBI
12350                                                                      ASIDE1IS, TLBI VAAE1IS, TLBI VALE1IS, TLBI VAALE1IS */
12351         uint64_t tpu                   : 1;  /**< [ 24: 24](R/W) Trap Cache maintenance instructions to Point of Unification.
12352                                                                      When this bit is set to 1, this causes Cache maintenance
12353                                                                      instructions to the point of unification executed from EL1 or
12354                                                                      EL0 which are not UNdefined to be trapped to EL2. This covers
12355                                                                      the following instructions:
12356 
12357                                                                  AArch32: ICIMVAU, ICIALLU, ICIALLUIS, DCCMVAU.
12358 
12359                                                                  AArch64: IC IVAU, IC IALLU, IC IALLUIS, DC CVAU. */
12360         uint64_t tpc                   : 1;  /**< [ 23: 23](R/W) Trap Data/Unified Cache maintenance operations to Point of
12361                                                                      Coherency. When this bit is set to 1, this causes Data or
12362                                                                      Unified Cache maintenance instructions by address to the point
12363                                                                      of coherency executed from EL1 or EL0 which are not UNdefined
12364                                                                      to be trapped to EL2. This covers the following instructions:
12365 
12366                                                                  AArch32: DCIMVAC, DCCIMVAC, DCCMVAC.
12367 
12368                                                                  AArch64: DC IVAC, DC CIVAC, DC CVAC. */
12369         uint64_t tsw                   : 1;  /**< [ 22: 22](R/W) Trap Data/Unified Cache maintenance operations by Set/Way.
12370                                                                      When this bit is set to 1, this causes Data or Unified Cache
12371                                                                      maintenance instructions by set/way executed from EL1 which
12372                                                                      are not UNdefined to be trapped to EL2. This covers the
12373                                                                      following instructions:
12374 
12375                                                                  AArch32: DCISW, DCCSW, DCCISW.
12376 
12377                                                                  AArch64: DC ISW, DC CSW, DC CISW. */
12378         uint64_t tacr                  : 1;  /**< [ 21: 21](R/W) Trap Auxiliary Control Register. When this bit is set to 1,
12379                                                                      this causes accesses to the following registers executed from
12380                                                                      EL1 to be trapped to EL2:
12381 
12382                                                                  AArch32: ACTLR.
12383 
12384                                                                  AArch64: ACTLR_EL1. */
12385         uint64_t tidcp                 : 1;  /**< [ 20: 20](R/W) Trap Implementation Dependent functionality. When this bit is
12386                                                                      set to 1, this causes accesses to the following instruction
12387                                                                      set space executed from EL1 to be trapped to EL2.
12388 
12389                                                                  AArch32: MCR and MRC instructions as follows:
12390 
12391                                                                   All CP15, CRn==9,  Opcode1 = {0-7}, CRm == {c0-c2, c5-c8},
12392                                                                      opcode2 == {0-7}.
12393 
12394                                                                   All CP15, CRn==10, Opcode1 =={0-7}, CRm == {c0, c1, c4, c8},
12395                                                                      opcode2 == {0-7}.
12396 
12397                                                                   All CP15, CRn==11, Opcode1=={0-7}, CRm == {c0-c8, c15},
12398                                                                      opcode2 == {0-7}.
12399 
12400                                                                  AArch64: All encoding space reserved for implementation
12401                                                                      defined system operations ( S1_\<op1\>_\<Cn\>_\<Cm\>_\<op2\>) and
12402                                                                      system registers ( S3_\<op1\>_\<Cn\>_\<Cm\>_\<op2\>).
12403 
12404                                                                  It is implementation defined whether any of this functionality
12405                                                                      accessed from EL0 is trapped to EL2 when the AP_HCR_EL2[TIDCP] bit
12406                                                                      is set. If it is not trapped to EL2, it results in an
12407                                                                      Undefined exception taken to EL1. */
12408         uint64_t tsc                   : 1;  /**< [ 19: 19](R/W) Trap SMC. When this bit is set to 1, this causes the following
12409                                                                      instructions executed from EL1 to be trapped to EL2:
12410 
12411                                                                  AArch32: SMC.
12412 
12413                                                                  AArch64: SMC.
12414 
12415                                                                  If EL3 is not implemented, this bit is RES0. */
12416         uint64_t tid3                  : 1;  /**< [ 18: 18](R/W) Trap ID Group 3. When this bit is set to 1, this causes reads
12417                                                                      to the following registers executed from EL1 to be trapped to
12418                                                                      EL2:
12419 
12420                                                                  AArch32: ID_PFR0, ID_PFR1, ID_DFR0, ID_AFR0, ID_MMFR0,
12421                                                                      ID_MMFR1, ID_MMFR2, ID_MMFR3, ID_ISAR0, ID_ISAR1, ID_ISAR2,
12422                                                                      ID_ISAR3, ID_ISAR4, ID_ISAR5, MVFR0, MVFR1, MVFR2. Also MRC to
12423                                                                      any of the following encodings:
12424 
12425                                                                   CP15, CRn == 0, Opc1 == 0, CRm == {3-7}, Opc2 == {0,1}.
12426 
12427                                                                   CP15, CRn == 0, Opc1 == 0, CRm == 3, Opc2 == 2.
12428 
12429                                                                   CP15, CRn == 0, Opc1 == 0, CRm == 5, Opc2 == {4,5}.
12430 
12431                                                                  AArch64: AP_ID_PFR0_EL1, AP_ID_PFR1_EL1, AP_ID_DFR0_EL1, AP_ID_AFR0_EL1,
12432                                                                      ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1,
12433                                                                      ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1,
12434                                                                      ID_ISAR4_EL1, ID_ISAR5_EL1, MVFR0_EL1, MVFR1_EL1, MVFR2_EL1,
12435                                                                      AP_ID_AA64PFR0_EL1, AP_ID_AA64PFR1_EL1, AP_ID_AA64DFR0_EL1,
12436                                                                      AP_ID_AA64DFR1_EL1, AP_ID_AA64ISAR0_EL1, AP_ID_AA64ISAR1_EL1,
12437                                                                      AP_ID_AA64MMFR0_EL1, AP_ID_AA64MMFR1_EL1, AP_ID_AA64AFR0_EL1,
12438                                                                      AP_ID_AA64AFR1_EL1. */
12439         uint64_t tid2                  : 1;  /**< [ 17: 17](R/W) Trap ID Group 2. When this bit is set to 1, this causes reads
12440                                                                      (or writes to CSSELR/ AP_CSSELR_EL1) to the following registers
12441                                                                      executed from EL1 or EL0 if not UNdefined to be trapped to
12442                                                                      EL2:
12443 
12444                                                                  AArch32: CTR, CCSIDR, CLIDR, CSSELR.
12445 
12446                                                                  AArch64: AP_CTR_EL0, AP_CCSIDR_EL1, AP_CLIDR_EL1, AP_CSSELR_EL1. */
12447         uint64_t tid1                  : 1;  /**< [ 16: 16](R/W) Trap ID Group 1. When this bit is set to 1, this causes reads
12448                                                                      to the following registers executed from EL1 to be trapped to
12449                                                                      EL2:
12450 
12451                                                                  AArch32: TCMTR, TLBTR, AIDR, REVIDR.
12452 
12453                                                                  AArch64: AP_AIDR_EL1, AP_REVIDR_EL1. */
12454         uint64_t tid0                  : 1;  /**< [ 15: 15](R/W) Trap ID Group 0. When this bit is set to 1, this causes reads
12455                                                                      to the following registers executed from EL1 or EL0 if not
12456                                                                      UNdefined to be trapped to EL2:
12457 
12458                                                                  AArch32: FPSID, JIDR.
12459 
12460                                                                  AArch64: None. */
12461         uint64_t twe                   : 1;  /**< [ 14: 14](R/W) Trap WFE. When this bit is set to 1, this causes the following
12462                                                                      instructions executed from EL1 or EL0 to be trapped to EL2 if
12463                                                                      the instruction would otherwise cause suspension of execution
12464                                                                      (i.e. if the event register is not set):
12465 
12466                                                                  AArch32: WFE.
12467 
12468                                                                  AArch64: WFE.
12469 
12470                                                                  Conditional WFE instructions that fail their condition are not
12471                                                                      trapped if this bit is set to 1. */
12472         uint64_t twi                   : 1;  /**< [ 13: 13](R/W) Trap WFI. When this bit is set to 1, this causes the following
12473                                                                      instructions executed from EL1 or EL0 to be trapped to EL2 if
12474                                                                      the instruction would otherwise cause suspension of execution
12475                                                                      (i.e. if there is not a pending WFI wakeup event):
12476 
12477                                                                  AArch32: WFI.
12478 
12479                                                                  AArch64: WFI.
12480 
12481                                                                  Conditional WFI instructions that fail their condition are not
12482                                                                      trapped if this bit is set to 1. */
12483         uint64_t dc                    : 1;  /**< [ 12: 12](R/W) Default Cacheable. When this bit is set to 1, this causes:
12484 
12485                                                                  * The AP_SCTLR_EL1[M] bit to behave as 0 when in the nonsecure
12486                                                                      state for all purposes other than reading the value of the
12487                                                                      bit.
12488 
12489                                                                  * The AP_HCR_EL2[VM] bit to behave as 1 when in the nonsecure
12490                                                                      state for all purposes other than reading the value of the
12491                                                                      bit.
12492 
12493                                                                  The memory type produced by the first stage of translation
12494                                                                      used by EL1 and EL0 is Normal Non-Shareable, Inner WriteBack
12495                                                                      Read-WriteAllocate, Outer WriteBack Read-WriteAllocate.
12496 
12497                                                                  When this bit is 0 and the stage 1 MMU is disabled, the
12498                                                                      default memory attribute for Data accesses is Device-nGnRnE.
12499 
12500                                                                  This bit is permitted to be cached in a TLB. */
12501         uint64_t bsu                   : 2;  /**< [ 11: 10](R/W) Barrier Shareability upgrade. The value in this field
12502                                                                      determines the minimum shareability domain that is applied to
12503                                                                      any barrier executed from EL1 or EL0.
12504 
12505                                                                  This value is combined with the specified level of the barrier
12506                                                                      held in its instruction, using the same principles as
12507                                                                      combining the shareability attributes from two stages of
12508                                                                      address translation.
12509 
12510                                                                  0x0 = No effect.
12511                                                                  0x1 = Inner Shareable.
12512                                                                  0x2 = Outer Shareable.
12513                                                                  0x3 = Full system. */
12514         uint64_t fb                    : 1;  /**< [  9:  9](R/W) Force broadcast. When this bit is set to 1, this causes the
12515                                                                      following instructions to be broadcast within the Inner
12516                                                                      Shareable domain when executed from nonsecure EL1:
12517 
12518                                                                  AArch32: BPIALL, TLBIALL, TLBIMVA, TLBIASID, DTLBIALL,
12519                                                                      DTLBIMVA, DTLBIASID, ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA,
12520                                                                      ICIALLU, TLBIMVAL, TLBIMVAAL.
12521 
12522                                                                  AArch64: TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
12523                                                                      TLBI VALE1, TLBI VAALE1, IC IALLU. */
12524         uint64_t vse                   : 1;  /**< [  8:  8](R/W) Virtual System Error/Asynchronous Abort.
12525                                                                  The virtual System Error/Asynchronous Abort is only enabled
12526                                                                      when the AP_HCR_EL2[AMO] bit is set.
12527                                                                  0 = Virtual System Error/Asynchronous Abort is not pending by this
12528                                                                      mechanism.
12529                                                                  1 = Virtual System Error/Asynchronous Abort is pending by this
12530                                                                      mechanism. */
12531         uint64_t vi                    : 1;  /**< [  7:  7](R/W) Virtual IRQ Interrupt.
12532                                                                  The virtual IRQ is only enabled when the AP_HCR_EL2[IMO] bit is
12533                                                                      set.
12534                                                                  0 = Virtual IRQ is not pending by this mechanism.
12535                                                                  1 = Virtual IRQ is pending by this mechanism. */
12536         uint64_t vf                    : 1;  /**< [  6:  6](R/W) Virtual FIQ Interrupt.
12537                                                                  The virtual FIQ is only enabled when the AP_HCR_EL2[FMO] bit is
12538                                                                      set.
12539                                                                  0 = Virtual FIQ is not pending by this mechanism.
12540                                                                  1 = Virtual FIQ is pending by this mechanism. */
12541         uint64_t amo                   : 1;  /**< [  5:  5](R/W) Asynchronous abort and error interrupt routing.
12542                                                                  0 = Asynchronous External Aborts and SError Interrupts while
12543                                                                      executing at exception levels lower than EL2 are not taken in
12544                                                                      EL2. Virtual System Error/Asynchronous Abort is disabled.
12545                                                                  1 = Asynchronous External Aborts and SError Interrupts while
12546                                                                      executing at EL2 or lower are taken in EL2 unless routed by
12547                                                                      the AP_SCR_EL3[EA] bit to EL3. Virtual System Error/Asynchronous
12548                                                                      Abort is enabled. */
12549         uint64_t imo                   : 1;  /**< [  4:  4](R/W) Physical IRQ Routing.
12550                                                                  0 = Physical IRQ while executing at exception levels lower than
12551                                                                      EL2 are not taken in EL2. Virtual IRQ Interrupt is disabled.
12552                                                                  1 = Physical IRQ while executing at EL2 or lower are taken in EL2
12553                                                                      unless routed by the AP_SCR_EL3[IRQ] bit to EL3. Virtual IRQ
12554                                                                      Interrupt is enabled. */
12555         uint64_t fmo                   : 1;  /**< [  3:  3](R/W) Physical FIQ Routing.
12556                                                                  0 = Physical FIQ while executing at exception levels lower than
12557                                                                      EL2 are not taken in EL2. Virtual FIQ Interrupt is disabled.
12558                                                                  1 = Physical FIQ while executing at EL2 or lower are taken in EL2
12559                                                                      unless routed by the AP_SCR_EL3[FIQ] bit to EL3. Virtual FIQ
12560                                                                      Interrupt is enabled. */
12561         uint64_t ptw                   : 1;  /**< [  2:  2](R/W) Protected Table Walk. When this bit is set to 1, if the stage
12562                                                                      2 translation of a translation table access made as part of a
12563                                                                      stage 1 translation table walk at EL0 or EL1 maps that
12564                                                                      translation table access to Strongly-ordered or Device memory,
12565                                                                      the access is faulted as a stage 2 Permission fault.
12566                                                                  This bit is permitted to be cached in a TLB. */
12567         uint64_t swio                  : 1;  /**< [  1:  1](R/W) Set/Way Invalidation Override. When this bit is set to 1, this
12568                                                                      causes EL1 execution of the data cache invalidate by set/way
12569                                                                      instruction to be treated as data cache clean and invalidate
12570                                                                      by set/way. That is:
12571 
12572                                                                  AArch32: DCISW is executed as DCCISW.
12573 
12574                                                                  AArch64: DC ISW is executed as DC CISW.
12575 
12576                                                                  As a result of changes to the behavior of DCISW, this bit is
12577                                                                      redundant in ARMv8. It is permissible that an implementation
12578                                                                      makes this bit RES1. */
12579         uint64_t vm                    : 1;  /**< [  0:  0](R/W) Virtualization MMU enable for EL1 and EL0 stage 2 address
12580                                                                      translation.
12581                                                                  This bit is permitted to be cached in a TLB.
12582                                                                  0 = EL1 and EL0 stage 2 address translation disabled.
12583                                                                  1 = EL1 and EL0 stage 2 address translation enabled. */
12584 #else /* Word 0 - Little Endian */
12585         uint64_t vm                    : 1;  /**< [  0:  0](R/W) Virtualization MMU enable for EL1 and EL0 stage 2 address
12586                                                                      translation.
12587                                                                  This bit is permitted to be cached in a TLB.
12588                                                                  0 = EL1 and EL0 stage 2 address translation disabled.
12589                                                                  1 = EL1 and EL0 stage 2 address translation enabled. */
12590         uint64_t swio                  : 1;  /**< [  1:  1](R/W) Set/Way Invalidation Override. When this bit is set to 1, this
12591                                                                      causes EL1 execution of the data cache invalidate by set/way
12592                                                                      instruction to be treated as data cache clean and invalidate
12593                                                                      by set/way. That is:
12594 
12595                                                                  AArch32: DCISW is executed as DCCISW.
12596 
12597                                                                  AArch64: DC ISW is executed as DC CISW.
12598 
12599                                                                  As a result of changes to the behavior of DCISW, this bit is
12600                                                                      redundant in ARMv8. It is permissible that an implementation
12601                                                                      makes this bit RES1. */
12602         uint64_t ptw                   : 1;  /**< [  2:  2](R/W) Protected Table Walk. When this bit is set to 1, if the stage
12603                                                                      2 translation of a translation table access made as part of a
12604                                                                      stage 1 translation table walk at EL0 or EL1 maps that
12605                                                                      translation table access to Strongly-ordered or Device memory,
12606                                                                      the access is faulted as a stage 2 Permission fault.
12607                                                                  This bit is permitted to be cached in a TLB. */
12608         uint64_t fmo                   : 1;  /**< [  3:  3](R/W) Physical FIQ Routing.
12609                                                                  0 = Physical FIQ while executing at exception levels lower than
12610                                                                      EL2 are not taken in EL2. Virtual FIQ Interrupt is disabled.
12611                                                                  1 = Physical FIQ while executing at EL2 or lower are taken in EL2
12612                                                                      unless routed by the AP_SCR_EL3[FIQ] bit to EL3. Virtual FIQ
12613                                                                      Interrupt is enabled. */
12614         uint64_t imo                   : 1;  /**< [  4:  4](R/W) Physical IRQ Routing.
12615                                                                  0 = Physical IRQ while executing at exception levels lower than
12616                                                                      EL2 are not taken in EL2. Virtual IRQ Interrupt is disabled.
12617                                                                  1 = Physical IRQ while executing at EL2 or lower are taken in EL2
12618                                                                      unless routed by the AP_SCR_EL3[IRQ] bit to EL3. Virtual IRQ
12619                                                                      Interrupt is enabled. */
12620         uint64_t amo                   : 1;  /**< [  5:  5](R/W) Asynchronous abort and error interrupt routing.
12621                                                                  0 = Asynchronous External Aborts and SError Interrupts while
12622                                                                      executing at exception levels lower than EL2 are not taken in
12623                                                                      EL2. Virtual System Error/Asynchronous Abort is disabled.
12624                                                                  1 = Asynchronous External Aborts and SError Interrupts while
12625                                                                      executing at EL2 or lower are taken in EL2 unless routed by
12626                                                                      the AP_SCR_EL3[EA] bit to EL3. Virtual System Error/Asynchronous
12627                                                                      Abort is enabled. */
12628         uint64_t vf                    : 1;  /**< [  6:  6](R/W) Virtual FIQ Interrupt.
12629                                                                  The virtual FIQ is only enabled when the AP_HCR_EL2[FMO] bit is
12630                                                                      set.
12631                                                                  0 = Virtual FIQ is not pending by this mechanism.
12632                                                                  1 = Virtual FIQ is pending by this mechanism. */
12633         uint64_t vi                    : 1;  /**< [  7:  7](R/W) Virtual IRQ Interrupt.
12634                                                                  The virtual IRQ is only enabled when the AP_HCR_EL2[IMO] bit is
12635                                                                      set.
12636                                                                  0 = Virtual IRQ is not pending by this mechanism.
12637                                                                  1 = Virtual IRQ is pending by this mechanism. */
12638         uint64_t vse                   : 1;  /**< [  8:  8](R/W) Virtual System Error/Asynchronous Abort.
12639                                                                  The virtual System Error/Asynchronous Abort is only enabled
12640                                                                      when the AP_HCR_EL2[AMO] bit is set.
12641                                                                  0 = Virtual System Error/Asynchronous Abort is not pending by this
12642                                                                      mechanism.
12643                                                                  1 = Virtual System Error/Asynchronous Abort is pending by this
12644                                                                      mechanism. */
12645         uint64_t fb                    : 1;  /**< [  9:  9](R/W) Force broadcast. When this bit is set to 1, this causes the
12646                                                                      following instructions to be broadcast within the Inner
12647                                                                      Shareable domain when executed from nonsecure EL1:
12648 
12649                                                                  AArch32: BPIALL, TLBIALL, TLBIMVA, TLBIASID, DTLBIALL,
12650                                                                      DTLBIMVA, DTLBIASID, ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA,
12651                                                                      ICIALLU, TLBIMVAL, TLBIMVAAL.
12652 
12653                                                                  AArch64: TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
12654                                                                      TLBI VALE1, TLBI VAALE1, IC IALLU. */
12655         uint64_t bsu                   : 2;  /**< [ 11: 10](R/W) Barrier Shareability upgrade. The value in this field
12656                                                                      determines the minimum shareability domain that is applied to
12657                                                                      any barrier executed from EL1 or EL0.
12658 
12659                                                                  This value is combined with the specified level of the barrier
12660                                                                      held in its instruction, using the same principles as
12661                                                                      combining the shareability attributes from two stages of
12662                                                                      address translation.
12663 
12664                                                                  0x0 = No effect.
12665                                                                  0x1 = Inner Shareable.
12666                                                                  0x2 = Outer Shareable.
12667                                                                  0x3 = Full system. */
12668         uint64_t dc                    : 1;  /**< [ 12: 12](R/W) Default Cacheable. When this bit is set to 1, this causes:
12669 
12670                                                                  * The AP_SCTLR_EL1[M] bit to behave as 0 when in the nonsecure
12671                                                                      state for all purposes other than reading the value of the
12672                                                                      bit.
12673 
12674                                                                  * The AP_HCR_EL2[VM] bit to behave as 1 when in the nonsecure
12675                                                                      state for all purposes other than reading the value of the
12676                                                                      bit.
12677 
12678                                                                  The memory type produced by the first stage of translation
12679                                                                      used by EL1 and EL0 is Normal Non-Shareable, Inner WriteBack
12680                                                                      Read-WriteAllocate, Outer WriteBack Read-WriteAllocate.
12681 
12682                                                                  When this bit is 0 and the stage 1 MMU is disabled, the
12683                                                                      default memory attribute for Data accesses is Device-nGnRnE.
12684 
12685                                                                  This bit is permitted to be cached in a TLB. */
12686         uint64_t twi                   : 1;  /**< [ 13: 13](R/W) Trap WFI. When this bit is set to 1, this causes the following
12687                                                                      instructions executed from EL1 or EL0 to be trapped to EL2 if
12688                                                                      the instruction would otherwise cause suspension of execution
12689                                                                      (i.e. if there is not a pending WFI wakeup event):
12690 
12691                                                                  AArch32: WFI.
12692 
12693                                                                  AArch64: WFI.
12694 
12695                                                                  Conditional WFI instructions that fail their condition are not
12696                                                                      trapped if this bit is set to 1. */
12697         uint64_t twe                   : 1;  /**< [ 14: 14](R/W) Trap WFE. When this bit is set to 1, this causes the following
12698                                                                      instructions executed from EL1 or EL0 to be trapped to EL2 if
12699                                                                      the instruction would otherwise cause suspension of execution
12700                                                                      (i.e. if the event register is not set):
12701 
12702                                                                  AArch32: WFE.
12703 
12704                                                                  AArch64: WFE.
12705 
12706                                                                  Conditional WFE instructions that fail their condition are not
12707                                                                      trapped if this bit is set to 1. */
12708         uint64_t tid0                  : 1;  /**< [ 15: 15](R/W) Trap ID Group 0. When this bit is set to 1, this causes reads
12709                                                                      to the following registers executed from EL1 or EL0 if not
12710                                                                      UNdefined to be trapped to EL2:
12711 
12712                                                                  AArch32: FPSID, JIDR.
12713 
12714                                                                  AArch64: None. */
12715         uint64_t tid1                  : 1;  /**< [ 16: 16](R/W) Trap ID Group 1. When this bit is set to 1, this causes reads
12716                                                                      to the following registers executed from EL1 to be trapped to
12717                                                                      EL2:
12718 
12719                                                                  AArch32: TCMTR, TLBTR, AIDR, REVIDR.
12720 
12721                                                                  AArch64: AP_AIDR_EL1, AP_REVIDR_EL1. */
12722         uint64_t tid2                  : 1;  /**< [ 17: 17](R/W) Trap ID Group 2. When this bit is set to 1, this causes reads
12723                                                                      (or writes to CSSELR/ AP_CSSELR_EL1) to the following registers
12724                                                                      executed from EL1 or EL0 if not UNdefined to be trapped to
12725                                                                      EL2:
12726 
12727                                                                  AArch32: CTR, CCSIDR, CLIDR, CSSELR.
12728 
12729                                                                  AArch64: AP_CTR_EL0, AP_CCSIDR_EL1, AP_CLIDR_EL1, AP_CSSELR_EL1. */
12730         uint64_t tid3                  : 1;  /**< [ 18: 18](R/W) Trap ID Group 3. When this bit is set to 1, this causes reads
12731                                                                      to the following registers executed from EL1 to be trapped to
12732                                                                      EL2:
12733 
12734                                                                  AArch32: ID_PFR0, ID_PFR1, ID_DFR0, ID_AFR0, ID_MMFR0,
12735                                                                      ID_MMFR1, ID_MMFR2, ID_MMFR3, ID_ISAR0, ID_ISAR1, ID_ISAR2,
12736                                                                      ID_ISAR3, ID_ISAR4, ID_ISAR5, MVFR0, MVFR1, MVFR2. Also MRC to
12737                                                                      any of the following encodings:
12738 
12739                                                                   CP15, CRn == 0, Opc1 == 0, CRm == {3-7}, Opc2 == {0,1}.
12740 
12741                                                                   CP15, CRn == 0, Opc1 == 0, CRm == 3, Opc2 == 2.
12742 
12743                                                                   CP15, CRn == 0, Opc1 == 0, CRm == 5, Opc2 == {4,5}.
12744 
12745                                                                  AArch64: AP_ID_PFR0_EL1, AP_ID_PFR1_EL1, AP_ID_DFR0_EL1, AP_ID_AFR0_EL1,
12746                                                                      ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1,
12747                                                                      ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1,
12748                                                                      ID_ISAR4_EL1, ID_ISAR5_EL1, MVFR0_EL1, MVFR1_EL1, MVFR2_EL1,
12749                                                                      AP_ID_AA64PFR0_EL1, AP_ID_AA64PFR1_EL1, AP_ID_AA64DFR0_EL1,
12750                                                                      AP_ID_AA64DFR1_EL1, AP_ID_AA64ISAR0_EL1, AP_ID_AA64ISAR1_EL1,
12751                                                                      AP_ID_AA64MMFR0_EL1, AP_ID_AA64MMFR1_EL1, AP_ID_AA64AFR0_EL1,
12752                                                                      AP_ID_AA64AFR1_EL1. */
12753         uint64_t tsc                   : 1;  /**< [ 19: 19](R/W) Trap SMC. When this bit is set to 1, this causes the following
12754                                                                      instructions executed from EL1 to be trapped to EL2:
12755 
12756                                                                  AArch32: SMC.
12757 
12758                                                                  AArch64: SMC.
12759 
12760                                                                  If EL3 is not implemented, this bit is RES0. */
12761         uint64_t tidcp                 : 1;  /**< [ 20: 20](R/W) Trap Implementation Dependent functionality. When this bit is
12762                                                                      set to 1, this causes accesses to the following instruction
12763                                                                      set space executed from EL1 to be trapped to EL2.
12764 
12765                                                                  AArch32: MCR and MRC instructions as follows:
12766 
12767                                                                   All CP15, CRn==9,  Opcode1 = {0-7}, CRm == {c0-c2, c5-c8},
12768                                                                      opcode2 == {0-7}.
12769 
12770                                                                   All CP15, CRn==10, Opcode1 =={0-7}, CRm == {c0, c1, c4, c8},
12771                                                                      opcode2 == {0-7}.
12772 
12773                                                                   All CP15, CRn==11, Opcode1=={0-7}, CRm == {c0-c8, c15},
12774                                                                      opcode2 == {0-7}.
12775 
12776                                                                  AArch64: All encoding space reserved for implementation
12777                                                                      defined system operations ( S1_\<op1\>_\<Cn\>_\<Cm\>_\<op2\>) and
12778                                                                      system registers ( S3_\<op1\>_\<Cn\>_\<Cm\>_\<op2\>).
12779 
12780                                                                  It is implementation defined whether any of this functionality
12781                                                                      accessed from EL0 is trapped to EL2 when the AP_HCR_EL2[TIDCP] bit
12782                                                                      is set. If it is not trapped to EL2, it results in an
12783                                                                      Undefined exception taken to EL1. */
12784         uint64_t tacr                  : 1;  /**< [ 21: 21](R/W) Trap Auxiliary Control Register. When this bit is set to 1,
12785                                                                      this causes accesses to the following registers executed from
12786                                                                      EL1 to be trapped to EL2:
12787 
12788                                                                  AArch32: ACTLR.
12789 
12790                                                                  AArch64: ACTLR_EL1. */
12791         uint64_t tsw                   : 1;  /**< [ 22: 22](R/W) Trap Data/Unified Cache maintenance operations by Set/Way.
12792                                                                      When this bit is set to 1, this causes Data or Unified Cache
12793                                                                      maintenance instructions by set/way executed from EL1 which
12794                                                                      are not UNdefined to be trapped to EL2. This covers the
12795                                                                      following instructions:
12796 
12797                                                                  AArch32: DCISW, DCCSW, DCCISW.
12798 
12799                                                                  AArch64: DC ISW, DC CSW, DC CISW. */
12800         uint64_t tpc                   : 1;  /**< [ 23: 23](R/W) Trap Data/Unified Cache maintenance operations to Point of
12801                                                                      Coherency. When this bit is set to 1, this causes Data or
12802                                                                      Unified Cache maintenance instructions by address to the point
12803                                                                      of coherency executed from EL1 or EL0 which are not UNdefined
12804                                                                      to be trapped to EL2. This covers the following instructions:
12805 
12806                                                                  AArch32: DCIMVAC, DCCIMVAC, DCCMVAC.
12807 
12808                                                                  AArch64: DC IVAC, DC CIVAC, DC CVAC. */
12809         uint64_t tpu                   : 1;  /**< [ 24: 24](R/W) Trap Cache maintenance instructions to Point of Unification.
12810                                                                      When this bit is set to 1, this causes Cache maintenance
12811                                                                      instructions to the point of unification executed from EL1 or
12812                                                                      EL0 which are not UNdefined to be trapped to EL2. This covers
12813                                                                      the following instructions:
12814 
12815                                                                  AArch32: ICIMVAU, ICIALLU, ICIALLUIS, DCCMVAU.
12816 
12817                                                                  AArch64: IC IVAU, IC IALLU, IC IALLUIS, DC CVAU. */
12818         uint64_t ttlb                  : 1;  /**< [ 25: 25](R/W) Trap TLB maintenance instructions. When this bit is set to 1,
12819                                                                      this causes TLB maintenance instructions executed from EL1
12820                                                                      which are not UNdefined to be trapped to EL2. This covers the
12821                                                                      following instructions:
12822 
12823                                                                  AArch32: TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS,
12824                                                                      TLBIALL, TLBIMVA, TLBIASID, DTLBIALL, DTLBIMVA, DTLBIASID,
12825                                                                      ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA, TLBIMVALIS,
12826                                                                      TLBIMVAALIS, TLBIMVAL, TLBIMVAAL
12827 
12828                                                                  AArch64: TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
12829                                                                      TLBI VALE1, TLBI VAALE1, TLBI VMALLE1IS, TLBI VAE1IS, TLBI
12830                                                                      ASIDE1IS, TLBI VAAE1IS, TLBI VALE1IS, TLBI VAALE1IS */
12831         uint64_t tvm                   : 1;  /**< [ 26: 26](R/W) Trap Virtual Memory controls. When this bit is set to 1, this
12832                                                                      causes Writes to the EL1 virtual memory control registers from
12833                                                                      EL1 to be trapped to EL2. This covers the following registers:
12834 
12835                                                                  AArch32: SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR,
12836                                                                      IFAR, ADFSR, AIFSR, PRRR/ MAIR0, NMRR/ MAIR1, AMAIR0, AMAIR1,
12837                                                                      CONTEXTIDR.
12838 
12839                                                                  AArch64: AP_SCTLR_EL1, AP_TTBR0_EL1, AP_TTBR1_EL1, AP_TCR_EL1, ESR_EL1,
12840                                                                      FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1,
12841                                                                      AP_CONTEXTIDR_EL1 */
12842         uint64_t tge                   : 1;  /**< [ 27: 27](R/W) Trap General Exceptions. If this bit is set to 1, and
12843                                                                      AP_SCR_EL3[NS] is set to 1, then:
12844 
12845                                                                   All exceptions that would be routed to EL1 are routed to EL2.
12846 
12847                                                                   The AP_SCTLR_EL1[M] bit is treated as being 0 regardless of its
12848                                                                      actual state (for EL1 using AArch32 or AArch64) other than for
12849                                                                      the purpose of reading the bit.
12850 
12851                                                                   The AP_HCR_EL2[FMO], IMO and AMO bits are treated as being 1
12852                                                                      regardless of their actual state other than for the purpose of
12853                                                                      reading the bits.
12854 
12855                                                                   All virtual interrupts are disabled.
12856 
12857                                                                   Any implementation defined mechanisms for signalling virtual
12858                                                                      interrupts are disabled.
12859 
12860                                                                   An exception return to EL1 is treated as an illegal exception
12861                                                                      return.
12862 
12863                                                                  Additionally, if AP_HCR_EL2[TGE] == 1, the
12864                                                                      AP_MDCR_EL2.{TDRA,TDOSA,TDA} bits are ignored and the processor
12865                                                                      behaves as if they are set to 1, other than for the value read
12866                                                                      back from AP_MDCR_EL2. */
12867         uint64_t tdz                   : 1;  /**< [ 28: 28](R/W) Trap DC ZVA instruction:
12868                                                                  This bit also has an effect on the value read from the
12869                                                                      AP_DCZID_EL0 register. If this bit is 1, then reading
12870                                                                      AP_DCZID_EL0[DZP] from nonsecure EL1 or EL0 will return 1 to
12871                                                                      indicate that DC ZVA is prohibited.
12872                                                                  0 = The instruction is not trapped.
12873                                                                  1 = The instruction is trapped to EL2 when executed in nonsecure
12874                                                                      EL1 or EL0. */
12875         uint64_t reserved_29           : 1;
12876         uint64_t trvm                  : 1;  /**< [ 30: 30](R/W) Trap Read of Virtual Memory controls. When this bit is set to
12877                                                                      1, this causes Reads to the EL1 virtual memory control
12878                                                                      registers from EL1 to be trapped to EL2. This covers the
12879                                                                      following registers:
12880 
12881                                                                  AArch32: SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR,
12882                                                                      IFAR, ADFSR, AIFSR, PRRR/ MAIR0, NMRR/ MAIR1, AMAIR0, AMAIR1,
12883                                                                      CONTEXTIDR.
12884 
12885                                                                  AArch64: AP_SCTLR_EL1, AP_TTBR0_EL1, AP_TTBR1_EL1, AP_TCR_EL1, ESR_EL1,
12886                                                                      FAR_EL1, AFSR0_EL1, AFSR1_EL1, MAIR_EL1, AMAIR_EL1,
12887                                                                      AP_CONTEXTIDR_EL1. */
12888         uint64_t rsvd_31               : 1;  /**< [ 31: 31](RO) rw - Register Width control for lower exception levels:
12889                                                                  When AP_SCR_EL3[NS]==0, this bit behaves as if it has the same
12890                                                                      value as the AP_SCR_EL3[RW] bit except for the value read back.
12891                                                                  The RW bit is permitted to be cached in a TLB.
12892                                                                  0 = Lower levels are all AArch32.
12893                                                                  1 = EL1 is AArch64. EL0 is determined by the Execution state
12894                                                                      described in the current process state when executing at EL0. */
12895         uint64_t cd                    : 1;  /**< [ 32: 32](R/W) Stage 2 Data cache disable. When AP_HCR_EL2[VM]==1, this forces
12896                                                                      all stage 2 translations for data accesses and translation
12897                                                                      table walks to Normal memory to be Non-cacheable for the EL1&0
12898                                                                      translation regime.
12899                                                                  This bit has no effect on the EL2 or EL3 translation regimes.
12900                                                                  0 = No effect on the stage 2 of the EL1&0 translation regime for
12901                                                                      data accesses and translation table walks.
12902                                                                  1 = Forces all stage 2 translations for data accesses and
12903                                                                      translation table walks to Normal memory to be Non-cacheable
12904                                                                      for the EL1&0 translation regime. */
12905         uint64_t id                    : 1;  /**< [ 33: 33](R/W) Stage 2 Instruction cache disable. When AP_HCR_EL2[VM]==1, this
12906                                                                      forces all stage 2 translations for instruction accesses to
12907                                                                      Normal memory to be Non-cacheable for the EL1&0 translation
12908                                                                      regime.
12909                                                                  This bit has no effect on the EL2 or EL3 translation regimes.
12910                                                                  0 = No effect on the stage 2 of the EL1&0 translation regime for
12911                                                                      instruction accesses.
12912                                                                  1 = Forces all stage 2 translations for instruction accesses to
12913                                                                      Normal memory to be Non-cacheable for the EL1&0 translation
12914                                                                      regime. */
12915         uint64_t e2h                   : 1;  /**< [ 34: 34](R/W) V8.1: Enable EL2 host. */
12916         uint64_t tlor                  : 1;  /**< [ 35: 35](R/W) v8.1: Trap access to the LOR Registers from nonsecure EL1 to EL2.
12917                                                                  0 = Nonsecure EL1 accesses to the LOR Registers are not trapped to EL2.
12918                                                                  1 = Nonsecure EL1 accesses to the LOR Registers are trapped to EL2. */
12919         uint64_t reserved_36_63        : 28;
12920 #endif /* Word 0 - End */
12921     } cn8;
12922     /* struct bdk_ap_hcr_el2_s cn9; */
12923 };
12924 typedef union bdk_ap_hcr_el2 bdk_ap_hcr_el2_t;
12925 
12926 #define BDK_AP_HCR_EL2 BDK_AP_HCR_EL2_FUNC()
12927 static inline uint64_t BDK_AP_HCR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_HCR_EL2_FUNC(void)12928 static inline uint64_t BDK_AP_HCR_EL2_FUNC(void)
12929 {
12930     return 0x30401010000ll;
12931 }
12932 
12933 #define typedef_BDK_AP_HCR_EL2 bdk_ap_hcr_el2_t
12934 #define bustype_BDK_AP_HCR_EL2 BDK_CSR_TYPE_SYSREG
12935 #define basename_BDK_AP_HCR_EL2 "AP_HCR_EL2"
12936 #define busnum_BDK_AP_HCR_EL2 0
12937 #define arguments_BDK_AP_HCR_EL2 -1,-1,-1,-1
12938 
12939 /**
12940  * Register (SYSREG) ap_hpfar_el2
12941  *
12942  * AP Hypervisor IPA Fault Address Register
12943  * Holds the faulting IPA for some aborts on a stage 2
12944  *     translation taken to EL2.
12945  */
12946 union bdk_ap_hpfar_el2
12947 {
12948     uint64_t u;
12949     struct bdk_ap_hpfar_el2_s
12950     {
12951 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12952         uint64_t reserved_45_63        : 19;
12953         uint64_t fipa                  : 41; /**< [ 44:  4](R/W) Bits \<47:12\> of the faulting intermediate physical address.
12954                                                                      For implementations with fewer than 48 physical address bits,
12955                                                                      the equivalent upper bits in this field are RES0. */
12956         uint64_t reserved_0_3          : 4;
12957 #else /* Word 0 - Little Endian */
12958         uint64_t reserved_0_3          : 4;
12959         uint64_t fipa                  : 41; /**< [ 44:  4](R/W) Bits \<47:12\> of the faulting intermediate physical address.
12960                                                                      For implementations with fewer than 48 physical address bits,
12961                                                                      the equivalent upper bits in this field are RES0. */
12962         uint64_t reserved_45_63        : 19;
12963 #endif /* Word 0 - End */
12964     } s;
12965     struct bdk_ap_hpfar_el2_cn8
12966     {
12967 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12968         uint64_t reserved_40_63        : 24;
12969         uint64_t fipa                  : 36; /**< [ 39:  4](R/W) Bits \<47:12\> of the faulting intermediate physical address.
12970                                                                      For implementations with fewer than 48 physical address bits,
12971                                                                      the equivalent upper bits in this field are RES0. */
12972         uint64_t reserved_0_3          : 4;
12973 #else /* Word 0 - Little Endian */
12974         uint64_t reserved_0_3          : 4;
12975         uint64_t fipa                  : 36; /**< [ 39:  4](R/W) Bits \<47:12\> of the faulting intermediate physical address.
12976                                                                      For implementations with fewer than 48 physical address bits,
12977                                                                      the equivalent upper bits in this field are RES0. */
12978         uint64_t reserved_40_63        : 24;
12979 #endif /* Word 0 - End */
12980     } cn8;
12981     struct bdk_ap_hpfar_el2_cn9
12982     {
12983 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
12984         uint64_t reserved_45_63        : 19;
12985         uint64_t fipa                  : 41; /**< [ 44:  4](R/W) Bits \<51:12\> of the faulting intermediate physical address.
12986                                                                  For implementations that don't support as large an IPA, or when
12987                                                                  using a translation granule, the upper in this field are RES0. */
12988         uint64_t reserved_0_3          : 4;
12989 #else /* Word 0 - Little Endian */
12990         uint64_t reserved_0_3          : 4;
12991         uint64_t fipa                  : 41; /**< [ 44:  4](R/W) Bits \<51:12\> of the faulting intermediate physical address.
12992                                                                  For implementations that don't support as large an IPA, or when
12993                                                                  using a translation granule, the upper in this field are RES0. */
12994         uint64_t reserved_45_63        : 19;
12995 #endif /* Word 0 - End */
12996     } cn9;
12997 };
12998 typedef union bdk_ap_hpfar_el2 bdk_ap_hpfar_el2_t;
12999 
13000 #define BDK_AP_HPFAR_EL2 BDK_AP_HPFAR_EL2_FUNC()
13001 static inline uint64_t BDK_AP_HPFAR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_HPFAR_EL2_FUNC(void)13002 static inline uint64_t BDK_AP_HPFAR_EL2_FUNC(void)
13003 {
13004     return 0x30406000400ll;
13005 }
13006 
13007 #define typedef_BDK_AP_HPFAR_EL2 bdk_ap_hpfar_el2_t
13008 #define bustype_BDK_AP_HPFAR_EL2 BDK_CSR_TYPE_SYSREG
13009 #define basename_BDK_AP_HPFAR_EL2 "AP_HPFAR_EL2"
13010 #define busnum_BDK_AP_HPFAR_EL2 0
13011 #define arguments_BDK_AP_HPFAR_EL2 -1,-1,-1,-1
13012 
13013 /**
13014  * Register (SYSREG) ap_hstr_el2
13015  *
13016  * AP Hypervisor System Trap Register
13017  * Controls access to coprocessor registers at lower Exception
13018  *     levels in AArch32.
13019  */
13020 union bdk_ap_hstr_el2
13021 {
13022     uint32_t u;
13023     struct bdk_ap_hstr_el2_s
13024     {
13025 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13026         uint32_t reserved_0_31         : 32;
13027 #else /* Word 0 - Little Endian */
13028         uint32_t reserved_0_31         : 32;
13029 #endif /* Word 0 - End */
13030     } s;
13031     /* struct bdk_ap_hstr_el2_s cn; */
13032 };
13033 typedef union bdk_ap_hstr_el2 bdk_ap_hstr_el2_t;
13034 
13035 #define BDK_AP_HSTR_EL2 BDK_AP_HSTR_EL2_FUNC()
13036 static inline uint64_t BDK_AP_HSTR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_HSTR_EL2_FUNC(void)13037 static inline uint64_t BDK_AP_HSTR_EL2_FUNC(void)
13038 {
13039     return 0x30401010300ll;
13040 }
13041 
13042 #define typedef_BDK_AP_HSTR_EL2 bdk_ap_hstr_el2_t
13043 #define bustype_BDK_AP_HSTR_EL2 BDK_CSR_TYPE_SYSREG
13044 #define basename_BDK_AP_HSTR_EL2 "AP_HSTR_EL2"
13045 #define busnum_BDK_AP_HSTR_EL2 0
13046 #define arguments_BDK_AP_HSTR_EL2 -1,-1,-1,-1
13047 
13048 /**
13049  * Register (SYSREG) ap_icc_ap0r#_el1
13050  *
13051  * AP Interrupt Controller Active Priorities Group 0 (1,3) Register
13052  * Provides information about the active priorities for the
13053  *     current interrupt regime.
13054  */
13055 union bdk_ap_icc_ap0rx_el1
13056 {
13057     uint32_t u;
13058     struct bdk_ap_icc_ap0rx_el1_s
13059     {
13060 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13061         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
13062                                                                      following relationship:
13063                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
13064                                                                      minus 1, where U is the number of unimplemented bits of
13065                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRI]bits).
13066                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRI]bits == 0b100:
13067 
13068                                                                   There are 5 bits of implemented priority.
13069 
13070                                                                   This means there are 3 bits of unimplemented priority, which
13071                                                                      are always at the least significant end (bits [2:0] are RES0).
13072 
13073                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
13074                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
13075 
13076                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
13077                                                                      provide information about those priorities.
13078 
13079                                                                  Accesses to these registers from an interrupt regime give a
13080                                                                      view of the active priorities that is appropriate for that
13081                                                                      interrupt regime, to allow save and restore of the appropriate
13082                                                                      state.
13083 
13084                                                                  Interrupt regime and the number of Security states supported
13085                                                                      by the Distributor affect the view as follows. Unless
13086                                                                      otherwise stated, when a bit is successfully set to one, this
13087                                                                      clears any other active priorities corresponding to that bit.
13088 
13089                                                                  Exception level     AP0Rn access
13090 
13091                                                                  (Secure) EL3        Permitted. Accesses Group 0 Secure active priorities.
13092 
13093                                                                  Secure EL1  Permitted. Accesses Group 0 Secure active priorities.
13094 
13095                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP0Rn_EL2
13096 
13097                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
13098                                                                  0) Permitted. Accesses Group 0 Secure active priorities.
13099 
13100                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
13101                                                                  1)  Permitted. Accesses Group 0 active priorities.
13102 
13103                                                                  A Virtual interrupt in this case means that the interrupt
13104                                                                      group associated with the register has been virtualized. */
13105 #else /* Word 0 - Little Endian */
13106         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
13107                                                                      following relationship:
13108                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
13109                                                                      minus 1, where U is the number of unimplemented bits of
13110                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRI]bits).
13111                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRI]bits == 0b100:
13112 
13113                                                                   There are 5 bits of implemented priority.
13114 
13115                                                                   This means there are 3 bits of unimplemented priority, which
13116                                                                      are always at the least significant end (bits [2:0] are RES0).
13117 
13118                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
13119                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
13120 
13121                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
13122                                                                      provide information about those priorities.
13123 
13124                                                                  Accesses to these registers from an interrupt regime give a
13125                                                                      view of the active priorities that is appropriate for that
13126                                                                      interrupt regime, to allow save and restore of the appropriate
13127                                                                      state.
13128 
13129                                                                  Interrupt regime and the number of Security states supported
13130                                                                      by the Distributor affect the view as follows. Unless
13131                                                                      otherwise stated, when a bit is successfully set to one, this
13132                                                                      clears any other active priorities corresponding to that bit.
13133 
13134                                                                  Exception level     AP0Rn access
13135 
13136                                                                  (Secure) EL3        Permitted. Accesses Group 0 Secure active priorities.
13137 
13138                                                                  Secure EL1  Permitted. Accesses Group 0 Secure active priorities.
13139 
13140                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP0Rn_EL2
13141 
13142                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
13143                                                                  0) Permitted. Accesses Group 0 Secure active priorities.
13144 
13145                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
13146                                                                  1)  Permitted. Accesses Group 0 active priorities.
13147 
13148                                                                  A Virtual interrupt in this case means that the interrupt
13149                                                                      group associated with the register has been virtualized. */
13150 #endif /* Word 0 - End */
13151     } s;
13152     /* struct bdk_ap_icc_ap0rx_el1_s cn; */
13153 };
13154 typedef union bdk_ap_icc_ap0rx_el1 bdk_ap_icc_ap0rx_el1_t;
13155 
13156 static inline uint64_t BDK_AP_ICC_AP0RX_EL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ICC_AP0RX_EL1(unsigned long a)13157 static inline uint64_t BDK_AP_ICC_AP0RX_EL1(unsigned long a)
13158 {
13159     if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=3))
13160         return 0x3000c080400ll + 0x100ll * ((a) & 0x3);
13161     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a>=1)&&(a<=3)))
13162         return 0x3000c080400ll + 0x100ll * ((a) & 0x3);
13163     __bdk_csr_fatal("AP_ICC_AP0RX_EL1", 1, a, 0, 0, 0);
13164 }
13165 
13166 #define typedef_BDK_AP_ICC_AP0RX_EL1(a) bdk_ap_icc_ap0rx_el1_t
13167 #define bustype_BDK_AP_ICC_AP0RX_EL1(a) BDK_CSR_TYPE_SYSREG
13168 #define basename_BDK_AP_ICC_AP0RX_EL1(a) "AP_ICC_AP0RX_EL1"
13169 #define busnum_BDK_AP_ICC_AP0RX_EL1(a) (a)
13170 #define arguments_BDK_AP_ICC_AP0RX_EL1(a) (a),-1,-1,-1
13171 
13172 /**
13173  * Register (SYSREG) ap_icc_ap0r0_el1
13174  *
13175  * AP Interrupt Controller Active Priorities Group 0 (0,0) Register
13176  * Provides information about the active priorities for the
13177  *     current interrupt regime.
13178  */
13179 union bdk_ap_icc_ap0r0_el1
13180 {
13181     uint32_t u;
13182     struct bdk_ap_icc_ap0r0_el1_s
13183     {
13184 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13185         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
13186                                                                      following relationship:
13187                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
13188                                                                      minus 1, where U is the number of unimplemented bits of
13189                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRI]bits).
13190                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRI]bits == 0b100:
13191 
13192                                                                   There are 5 bits of implemented priority.
13193 
13194                                                                   This means there are 3 bits of unimplemented priority, which
13195                                                                      are always at the least significant end (bits [2:0] are RES0).
13196 
13197                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
13198                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
13199 
13200                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
13201                                                                      provide information about those priorities.
13202 
13203                                                                  Accesses to these registers from an interrupt regime give a
13204                                                                      view of the active priorities that is appropriate for that
13205                                                                      interrupt regime, to allow save and restore of the appropriate
13206                                                                      state.
13207 
13208                                                                  Interrupt regime and the number of Security states supported
13209                                                                      by the Distributor affect the view as follows. Unless
13210                                                                      otherwise stated, when a bit is successfully set to one, this
13211                                                                      clears any other active priorities corresponding to that bit.
13212 
13213                                                                  Exception level     AP0Rn access
13214 
13215                                                                  (Secure) EL3        Permitted. Accesses Group 0 Secure active priorities.
13216 
13217                                                                  Secure EL1  Permitted. Accesses Group 0 Secure active priorities.
13218 
13219                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP0Rn_EL2
13220 
13221                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
13222                                                                  0) Permitted. Accesses Group 0 Secure active priorities.
13223 
13224                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
13225                                                                  1)  Permitted. Accesses Group 0 active priorities.
13226 
13227                                                                  A Virtual interrupt in this case means that the interrupt
13228                                                                      group associated with the register has been virtualized. */
13229 #else /* Word 0 - Little Endian */
13230         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
13231                                                                      following relationship:
13232                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
13233                                                                      minus 1, where U is the number of unimplemented bits of
13234                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRI]bits).
13235                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRI]bits == 0b100:
13236 
13237                                                                   There are 5 bits of implemented priority.
13238 
13239                                                                   This means there are 3 bits of unimplemented priority, which
13240                                                                      are always at the least significant end (bits [2:0] are RES0).
13241 
13242                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
13243                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
13244 
13245                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
13246                                                                      provide information about those priorities.
13247 
13248                                                                  Accesses to these registers from an interrupt regime give a
13249                                                                      view of the active priorities that is appropriate for that
13250                                                                      interrupt regime, to allow save and restore of the appropriate
13251                                                                      state.
13252 
13253                                                                  Interrupt regime and the number of Security states supported
13254                                                                      by the Distributor affect the view as follows. Unless
13255                                                                      otherwise stated, when a bit is successfully set to one, this
13256                                                                      clears any other active priorities corresponding to that bit.
13257 
13258                                                                  Exception level     AP0Rn access
13259 
13260                                                                  (Secure) EL3        Permitted. Accesses Group 0 Secure active priorities.
13261 
13262                                                                  Secure EL1  Permitted. Accesses Group 0 Secure active priorities.
13263 
13264                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP0Rn_EL2
13265 
13266                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
13267                                                                  0) Permitted. Accesses Group 0 Secure active priorities.
13268 
13269                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
13270                                                                  1)  Permitted. Accesses Group 0 active priorities.
13271 
13272                                                                  A Virtual interrupt in this case means that the interrupt
13273                                                                      group associated with the register has been virtualized. */
13274 #endif /* Word 0 - End */
13275     } s;
13276     /* struct bdk_ap_icc_ap0r0_el1_s cn; */
13277 };
13278 typedef union bdk_ap_icc_ap0r0_el1 bdk_ap_icc_ap0r0_el1_t;
13279 
13280 #define BDK_AP_ICC_AP0R0_EL1 BDK_AP_ICC_AP0R0_EL1_FUNC()
13281 static inline uint64_t BDK_AP_ICC_AP0R0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_AP0R0_EL1_FUNC(void)13282 static inline uint64_t BDK_AP_ICC_AP0R0_EL1_FUNC(void)
13283 {
13284     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
13285         return 0x3000c080400ll;
13286     __bdk_csr_fatal("AP_ICC_AP0R0_EL1", 0, 0, 0, 0, 0);
13287 }
13288 
13289 #define typedef_BDK_AP_ICC_AP0R0_EL1 bdk_ap_icc_ap0r0_el1_t
13290 #define bustype_BDK_AP_ICC_AP0R0_EL1 BDK_CSR_TYPE_SYSREG
13291 #define basename_BDK_AP_ICC_AP0R0_EL1 "AP_ICC_AP0R0_EL1"
13292 #define busnum_BDK_AP_ICC_AP0R0_EL1 0
13293 #define arguments_BDK_AP_ICC_AP0R0_EL1 -1,-1,-1,-1
13294 
13295 /**
13296  * Register (SYSREG) ap_icc_ap1r#_el1
13297  *
13298  * AP Interrupt Controller Active Priorities Group 1(1,3) Register
13299  * Provides information about the active priorities for the
13300  *     current interrupt regime.
13301  */
13302 union bdk_ap_icc_ap1rx_el1
13303 {
13304     uint32_t u;
13305     struct bdk_ap_icc_ap1rx_el1_s
13306     {
13307 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13308         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
13309                                                                      following relationship:
13310 
13311                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
13312                                                                      minus 1, where U is the number of unimplemented bits of
13313                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRI]bits).
13314 
13315                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRI]bits ==0b100
13316 
13317                                                                   There are 5 bits of implemented priority.
13318 
13319                                                                   This means there are 3 bits of unimplemented priority, which
13320                                                                      are always at the least significant end (bits [2:0] are RES0).
13321 
13322                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
13323                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
13324 
13325                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
13326                                                                      provide information about those priorities.
13327 
13328                                                                  Accesses to these registers from an interrupt regime give a
13329                                                                      view of the active priorities that is appropriate for that
13330                                                                      interrupt regime, to allow save and restore of the appropriate
13331                                                                      state.
13332 
13333                                                                  Interrupt regime and the number of Security states supported
13334                                                                      by the Distributor affect the view as follows. Unless
13335                                                                      otherwise stated, when a bit is successfully set to one, this
13336                                                                      clears any other active priorities corresponding to that bit.
13337 
13338                                                                  Current Exception level and Security state  AP1Rn access
13339 
13340                                                                  (Secure) EL3        Permitted. When AP_SCR_EL3[NS] is 0, accesses Group 1 Secure active
13341                                                                  priorities. When AP_SCR_EL3[NS] is 1, accesses Group 1 nonsecure active priorities
13342                                                                  (unshifted). When a bit is written, the bit is only updated if the corresponding Group 0
13343                                                                  and Group 1 Secure active priority is zero.
13344 
13345                                                                  Secure EL1  Permitted. Accesses Group 1 Secure active priorities (unshifted). When a bit
13346                                                                  is written, the bit is only updated if the corresponding Group 0 Secure active priority is
13347                                                                  zero.
13348 
13349                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP1Rn_EL2
13350 
13351                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
13352                                                                  0) Permitted. Accesses Group 1 Nonsecure active priorities (shifted). When a bit is
13353                                                                  written, the bit is only updated if the corresponding Group 0 and Group 1 Secure active
13354                                                                  priority is zero.
13355 
13356                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
13357                                                                  1)  Permitted. Accesses Group 1 Nonsecure active priorities (unshifted). When a bit is
13358                                                                  written, the bit is only updated if the Group 0 active priority is zero.
13359 
13360                                                                  A Virtual interrupt in this case means that the interrupt
13361                                                                      group associated with the register has been virtualized. */
13362 #else /* Word 0 - Little Endian */
13363         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
13364                                                                      following relationship:
13365 
13366                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
13367                                                                      minus 1, where U is the number of unimplemented bits of
13368                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRI]bits).
13369 
13370                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRI]bits ==0b100
13371 
13372                                                                   There are 5 bits of implemented priority.
13373 
13374                                                                   This means there are 3 bits of unimplemented priority, which
13375                                                                      are always at the least significant end (bits [2:0] are RES0).
13376 
13377                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
13378                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
13379 
13380                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
13381                                                                      provide information about those priorities.
13382 
13383                                                                  Accesses to these registers from an interrupt regime give a
13384                                                                      view of the active priorities that is appropriate for that
13385                                                                      interrupt regime, to allow save and restore of the appropriate
13386                                                                      state.
13387 
13388                                                                  Interrupt regime and the number of Security states supported
13389                                                                      by the Distributor affect the view as follows. Unless
13390                                                                      otherwise stated, when a bit is successfully set to one, this
13391                                                                      clears any other active priorities corresponding to that bit.
13392 
13393                                                                  Current Exception level and Security state  AP1Rn access
13394 
13395                                                                  (Secure) EL3        Permitted. When AP_SCR_EL3[NS] is 0, accesses Group 1 Secure active
13396                                                                  priorities. When AP_SCR_EL3[NS] is 1, accesses Group 1 nonsecure active priorities
13397                                                                  (unshifted). When a bit is written, the bit is only updated if the corresponding Group 0
13398                                                                  and Group 1 Secure active priority is zero.
13399 
13400                                                                  Secure EL1  Permitted. Accesses Group 1 Secure active priorities (unshifted). When a bit
13401                                                                  is written, the bit is only updated if the corresponding Group 0 Secure active priority is
13402                                                                  zero.
13403 
13404                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP1Rn_EL2
13405 
13406                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
13407                                                                  0) Permitted. Accesses Group 1 Nonsecure active priorities (shifted). When a bit is
13408                                                                  written, the bit is only updated if the corresponding Group 0 and Group 1 Secure active
13409                                                                  priority is zero.
13410 
13411                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
13412                                                                  1)  Permitted. Accesses Group 1 Nonsecure active priorities (unshifted). When a bit is
13413                                                                  written, the bit is only updated if the Group 0 active priority is zero.
13414 
13415                                                                  A Virtual interrupt in this case means that the interrupt
13416                                                                      group associated with the register has been virtualized. */
13417 #endif /* Word 0 - End */
13418     } s;
13419     /* struct bdk_ap_icc_ap1rx_el1_s cn; */
13420 };
13421 typedef union bdk_ap_icc_ap1rx_el1 bdk_ap_icc_ap1rx_el1_t;
13422 
13423 static inline uint64_t BDK_AP_ICC_AP1RX_EL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ICC_AP1RX_EL1(unsigned long a)13424 static inline uint64_t BDK_AP_ICC_AP1RX_EL1(unsigned long a)
13425 {
13426     if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=3))
13427         return 0x3000c090000ll + 0x100ll * ((a) & 0x3);
13428     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a>=1)&&(a<=3)))
13429         return 0x3000c090000ll + 0x100ll * ((a) & 0x3);
13430     __bdk_csr_fatal("AP_ICC_AP1RX_EL1", 1, a, 0, 0, 0);
13431 }
13432 
13433 #define typedef_BDK_AP_ICC_AP1RX_EL1(a) bdk_ap_icc_ap1rx_el1_t
13434 #define bustype_BDK_AP_ICC_AP1RX_EL1(a) BDK_CSR_TYPE_SYSREG
13435 #define basename_BDK_AP_ICC_AP1RX_EL1(a) "AP_ICC_AP1RX_EL1"
13436 #define busnum_BDK_AP_ICC_AP1RX_EL1(a) (a)
13437 #define arguments_BDK_AP_ICC_AP1RX_EL1(a) (a),-1,-1,-1
13438 
13439 /**
13440  * Register (SYSREG) ap_icc_ap1r0_el1
13441  *
13442  * AP Interrupt Controller Active Priorities Group 1 (0,0) Register
13443  * Provides information about the active priorities for the
13444  *     current interrupt regime.
13445  */
13446 union bdk_ap_icc_ap1r0_el1
13447 {
13448     uint32_t u;
13449     struct bdk_ap_icc_ap1r0_el1_s
13450     {
13451 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13452         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
13453                                                                      following relationship:
13454 
13455                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
13456                                                                      minus 1, where U is the number of unimplemented bits of
13457                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRI]bits).
13458 
13459                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRI]bits ==0b100
13460 
13461                                                                   There are 5 bits of implemented priority.
13462 
13463                                                                   This means there are 3 bits of unimplemented priority, which
13464                                                                      are always at the least significant end (bits [2:0] are RES0).
13465 
13466                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
13467                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
13468 
13469                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
13470                                                                      provide information about those priorities.
13471 
13472                                                                  Accesses to these registers from an interrupt regime give a
13473                                                                      view of the active priorities that is appropriate for that
13474                                                                      interrupt regime, to allow save and restore of the appropriate
13475                                                                      state.
13476 
13477                                                                  Interrupt regime and the number of Security states supported
13478                                                                      by the Distributor affect the view as follows. Unless
13479                                                                      otherwise stated, when a bit is successfully set to one, this
13480                                                                      clears any other active priorities corresponding to that bit.
13481 
13482                                                                  Current Exception level and Security state  AP1Rn access
13483 
13484                                                                  (Secure) EL3        Permitted. When AP_SCR_EL3[NS] is 0, accesses Group 1 Secure active
13485                                                                  priorities. When AP_SCR_EL3[NS] is 1, accesses Group 1 nonsecure active priorities
13486                                                                  (unshifted). When a bit is written, the bit is only updated if the corresponding Group 0
13487                                                                  and Group 1 Secure active priority is zero.
13488 
13489                                                                  Secure EL1  Permitted. Accesses Group 1 Secure active priorities (unshifted). When a bit
13490                                                                  is written, the bit is only updated if the corresponding Group 0 Secure active priority is
13491                                                                  zero.
13492 
13493                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP1Rn_EL2
13494 
13495                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
13496                                                                  0) Permitted. Accesses Group 1 Nonsecure active priorities (shifted). When a bit is
13497                                                                  written, the bit is only updated if the corresponding Group 0 and Group 1 Secure active
13498                                                                  priority is zero.
13499 
13500                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
13501                                                                  1)  Permitted. Accesses Group 1 Nonsecure active priorities (unshifted). When a bit is
13502                                                                  written, the bit is only updated if the Group 0 active priority is zero.
13503 
13504                                                                  A Virtual interrupt in this case means that the interrupt
13505                                                                      group associated with the register has been virtualized. */
13506 #else /* Word 0 - Little Endian */
13507         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
13508                                                                      following relationship:
13509 
13510                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
13511                                                                      minus 1, where U is the number of unimplemented bits of
13512                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRI]bits).
13513 
13514                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRI]bits ==0b100
13515 
13516                                                                   There are 5 bits of implemented priority.
13517 
13518                                                                   This means there are 3 bits of unimplemented priority, which
13519                                                                      are always at the least significant end (bits [2:0] are RES0).
13520 
13521                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
13522                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
13523 
13524                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
13525                                                                      provide information about those priorities.
13526 
13527                                                                  Accesses to these registers from an interrupt regime give a
13528                                                                      view of the active priorities that is appropriate for that
13529                                                                      interrupt regime, to allow save and restore of the appropriate
13530                                                                      state.
13531 
13532                                                                  Interrupt regime and the number of Security states supported
13533                                                                      by the Distributor affect the view as follows. Unless
13534                                                                      otherwise stated, when a bit is successfully set to one, this
13535                                                                      clears any other active priorities corresponding to that bit.
13536 
13537                                                                  Current Exception level and Security state  AP1Rn access
13538 
13539                                                                  (Secure) EL3        Permitted. When AP_SCR_EL3[NS] is 0, accesses Group 1 Secure active
13540                                                                  priorities. When AP_SCR_EL3[NS] is 1, accesses Group 1 nonsecure active priorities
13541                                                                  (unshifted). When a bit is written, the bit is only updated if the corresponding Group 0
13542                                                                  and Group 1 Secure active priority is zero.
13543 
13544                                                                  Secure EL1  Permitted. Accesses Group 1 Secure active priorities (unshifted). When a bit
13545                                                                  is written, the bit is only updated if the corresponding Group 0 Secure active priority is
13546                                                                  zero.
13547 
13548                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP1Rn_EL2
13549 
13550                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
13551                                                                  0) Permitted. Accesses Group 1 Nonsecure active priorities (shifted). When a bit is
13552                                                                  written, the bit is only updated if the corresponding Group 0 and Group 1 Secure active
13553                                                                  priority is zero.
13554 
13555                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
13556                                                                  1)  Permitted. Accesses Group 1 Nonsecure active priorities (unshifted). When a bit is
13557                                                                  written, the bit is only updated if the Group 0 active priority is zero.
13558 
13559                                                                  A Virtual interrupt in this case means that the interrupt
13560                                                                      group associated with the register has been virtualized. */
13561 #endif /* Word 0 - End */
13562     } s;
13563     /* struct bdk_ap_icc_ap1r0_el1_s cn; */
13564 };
13565 typedef union bdk_ap_icc_ap1r0_el1 bdk_ap_icc_ap1r0_el1_t;
13566 
13567 #define BDK_AP_ICC_AP1R0_EL1 BDK_AP_ICC_AP1R0_EL1_FUNC()
13568 static inline uint64_t BDK_AP_ICC_AP1R0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_AP1R0_EL1_FUNC(void)13569 static inline uint64_t BDK_AP_ICC_AP1R0_EL1_FUNC(void)
13570 {
13571     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
13572         return 0x3000c090000ll;
13573     __bdk_csr_fatal("AP_ICC_AP1R0_EL1", 0, 0, 0, 0, 0);
13574 }
13575 
13576 #define typedef_BDK_AP_ICC_AP1R0_EL1 bdk_ap_icc_ap1r0_el1_t
13577 #define bustype_BDK_AP_ICC_AP1R0_EL1 BDK_CSR_TYPE_SYSREG
13578 #define basename_BDK_AP_ICC_AP1R0_EL1 "AP_ICC_AP1R0_EL1"
13579 #define busnum_BDK_AP_ICC_AP1R0_EL1 0
13580 #define arguments_BDK_AP_ICC_AP1R0_EL1 -1,-1,-1,-1
13581 
13582 /**
13583  * Register (SYSREG) ap_icc_asgi1r_el1
13584  *
13585  * AP Interrupt Controller Alias Software Generated Interrupt Group 1 Register
13586  * Provides software the ability to generate group 1 SGIs for the
13587  *     other Security state.
13588  */
13589 union bdk_ap_icc_asgi1r_el1
13590 {
13591     uint64_t u;
13592     struct bdk_ap_icc_asgi1r_el1_s
13593     {
13594 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13595         uint64_t reserved_56_63        : 8;
13596         uint64_t aff3                  : 8;  /**< [ 55: 48](R/W) The affinity 3 value of the affinity path of the cluster for
13597                                                                      which SGI interrupts will be generated. */
13598         uint64_t reserved_41_47        : 7;
13599         uint64_t irm                   : 1;  /**< [ 40: 40](R/W) Interrupt Routing Mode. Determines how the generated
13600                                                                      interrupts should be distributed to processors. Possible
13601                                                                      values are:
13602                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
13603                                                                      list}. In this routing, a, b, and c are the values of fields
13604                                                                      Aff3, Aff2, and Aff1 respectively.
13605                                                                  1 = Interrupts routed to all processors in the system, excluding
13606                                                                      "self". */
13607         uint64_t aff2                  : 8;  /**< [ 39: 32](R/W) The affinity 2 value of the affinity path of the cluster for
13608                                                                      which SGI interrupts will be generated. */
13609         uint64_t reserved_28_31        : 4;
13610         uint64_t sgiid                 : 4;  /**< [ 27: 24](R/W) SGI Interrupt ID. */
13611         uint64_t aff1                  : 8;  /**< [ 23: 16](R/W) The affinity 1 value of the affinity path of the cluster for
13612                                                                      which SGI interrupts will be generated. */
13613         uint64_t targetlist            : 16; /**< [ 15:  0](R/W) Target List. The set of processors for which SGI interrupts
13614                                                                      will be generated. Each bit corresponds to the processor
13615                                                                      within a cluster with an Affinity 0 value equal to the bit
13616                                                                      number.
13617 
13618                                                                  If a bit is 1 and the bit does not correspond to a valid
13619                                                                      target processor, the bit must be ignored by the Distributor.
13620                                                                      In such cases, a Distributor may optionally generate an SError
13621                                                                      interrupt.
13622 
13623                                                                  This restricts distribution of SGIs to the first 16 processors
13624                                                                      of an affinity 1 cluster. */
13625 #else /* Word 0 - Little Endian */
13626         uint64_t targetlist            : 16; /**< [ 15:  0](R/W) Target List. The set of processors for which SGI interrupts
13627                                                                      will be generated. Each bit corresponds to the processor
13628                                                                      within a cluster with an Affinity 0 value equal to the bit
13629                                                                      number.
13630 
13631                                                                  If a bit is 1 and the bit does not correspond to a valid
13632                                                                      target processor, the bit must be ignored by the Distributor.
13633                                                                      In such cases, a Distributor may optionally generate an SError
13634                                                                      interrupt.
13635 
13636                                                                  This restricts distribution of SGIs to the first 16 processors
13637                                                                      of an affinity 1 cluster. */
13638         uint64_t aff1                  : 8;  /**< [ 23: 16](R/W) The affinity 1 value of the affinity path of the cluster for
13639                                                                      which SGI interrupts will be generated. */
13640         uint64_t sgiid                 : 4;  /**< [ 27: 24](R/W) SGI Interrupt ID. */
13641         uint64_t reserved_28_31        : 4;
13642         uint64_t aff2                  : 8;  /**< [ 39: 32](R/W) The affinity 2 value of the affinity path of the cluster for
13643                                                                      which SGI interrupts will be generated. */
13644         uint64_t irm                   : 1;  /**< [ 40: 40](R/W) Interrupt Routing Mode. Determines how the generated
13645                                                                      interrupts should be distributed to processors. Possible
13646                                                                      values are:
13647                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
13648                                                                      list}. In this routing, a, b, and c are the values of fields
13649                                                                      Aff3, Aff2, and Aff1 respectively.
13650                                                                  1 = Interrupts routed to all processors in the system, excluding
13651                                                                      "self". */
13652         uint64_t reserved_41_47        : 7;
13653         uint64_t aff3                  : 8;  /**< [ 55: 48](R/W) The affinity 3 value of the affinity path of the cluster for
13654                                                                      which SGI interrupts will be generated. */
13655         uint64_t reserved_56_63        : 8;
13656 #endif /* Word 0 - End */
13657     } s;
13658     /* struct bdk_ap_icc_asgi1r_el1_s cn8; */
13659     struct bdk_ap_icc_asgi1r_el1_cn9
13660     {
13661 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13662         uint64_t reserved_56_63        : 8;
13663         uint64_t aff3                  : 8;  /**< [ 55: 48](WO) The affinity 3 value of the affinity path of the cluster for
13664                                                                      which SGI interrupts will be generated. */
13665         uint64_t reserved_41_47        : 7;
13666         uint64_t irm                   : 1;  /**< [ 40: 40](WO) Interrupt Routing Mode. Determines how the generated
13667                                                                      interrupts should be distributed to processors.
13668                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
13669                                                                      list}. In this routing, a, b, and c are the values of fields
13670                                                                      Aff3, Aff2, and Aff1 respectively.
13671                                                                  1 = Interrupts routed to all processors in the system, excluding
13672                                                                      self. */
13673         uint64_t aff2                  : 8;  /**< [ 39: 32](WO) The affinity 2 value of the affinity path of the cluster for
13674                                                                      which SGI interrupts will be generated. */
13675         uint64_t reserved_28_31        : 4;
13676         uint64_t sgiid                 : 4;  /**< [ 27: 24](WO) SGI Interrupt ID. */
13677         uint64_t aff1                  : 8;  /**< [ 23: 16](WO) The affinity 1 value of the affinity path of the cluster for
13678                                                                      which SGI interrupts will be generated. */
13679         uint64_t targetlist            : 16; /**< [ 15:  0](WO) Target List. The set of processors for which SGI interrupts
13680                                                                      will be generated. Each bit corresponds to the processor
13681                                                                      within a cluster with an Affinity 0 value equal to the bit
13682                                                                      number.
13683 
13684                                                                  If a bit is 1 and the bit does not correspond to a valid
13685                                                                      target processor, the bit must be ignored by the Distributor.
13686                                                                      In such cases, a Distributor may optionally generate an SError
13687                                                                      interrupt.
13688 
13689                                                                  This restricts distribution of SGIs to the first 16 processors
13690                                                                      of an affinity 1 cluster. */
13691 #else /* Word 0 - Little Endian */
13692         uint64_t targetlist            : 16; /**< [ 15:  0](WO) Target List. The set of processors for which SGI interrupts
13693                                                                      will be generated. Each bit corresponds to the processor
13694                                                                      within a cluster with an Affinity 0 value equal to the bit
13695                                                                      number.
13696 
13697                                                                  If a bit is 1 and the bit does not correspond to a valid
13698                                                                      target processor, the bit must be ignored by the Distributor.
13699                                                                      In such cases, a Distributor may optionally generate an SError
13700                                                                      interrupt.
13701 
13702                                                                  This restricts distribution of SGIs to the first 16 processors
13703                                                                      of an affinity 1 cluster. */
13704         uint64_t aff1                  : 8;  /**< [ 23: 16](WO) The affinity 1 value of the affinity path of the cluster for
13705                                                                      which SGI interrupts will be generated. */
13706         uint64_t sgiid                 : 4;  /**< [ 27: 24](WO) SGI Interrupt ID. */
13707         uint64_t reserved_28_31        : 4;
13708         uint64_t aff2                  : 8;  /**< [ 39: 32](WO) The affinity 2 value of the affinity path of the cluster for
13709                                                                      which SGI interrupts will be generated. */
13710         uint64_t irm                   : 1;  /**< [ 40: 40](WO) Interrupt Routing Mode. Determines how the generated
13711                                                                      interrupts should be distributed to processors.
13712                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
13713                                                                      list}. In this routing, a, b, and c are the values of fields
13714                                                                      Aff3, Aff2, and Aff1 respectively.
13715                                                                  1 = Interrupts routed to all processors in the system, excluding
13716                                                                      self. */
13717         uint64_t reserved_41_47        : 7;
13718         uint64_t aff3                  : 8;  /**< [ 55: 48](WO) The affinity 3 value of the affinity path of the cluster for
13719                                                                      which SGI interrupts will be generated. */
13720         uint64_t reserved_56_63        : 8;
13721 #endif /* Word 0 - End */
13722     } cn9;
13723 };
13724 typedef union bdk_ap_icc_asgi1r_el1 bdk_ap_icc_asgi1r_el1_t;
13725 
13726 #define BDK_AP_ICC_ASGI1R_EL1 BDK_AP_ICC_ASGI1R_EL1_FUNC()
13727 static inline uint64_t BDK_AP_ICC_ASGI1R_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_ASGI1R_EL1_FUNC(void)13728 static inline uint64_t BDK_AP_ICC_ASGI1R_EL1_FUNC(void)
13729 {
13730     return 0x3000c0b0600ll;
13731 }
13732 
13733 #define typedef_BDK_AP_ICC_ASGI1R_EL1 bdk_ap_icc_asgi1r_el1_t
13734 #define bustype_BDK_AP_ICC_ASGI1R_EL1 BDK_CSR_TYPE_SYSREG
13735 #define basename_BDK_AP_ICC_ASGI1R_EL1 "AP_ICC_ASGI1R_EL1"
13736 #define busnum_BDK_AP_ICC_ASGI1R_EL1 0
13737 #define arguments_BDK_AP_ICC_ASGI1R_EL1 -1,-1,-1,-1
13738 
13739 /**
13740  * Register (SYSREG) ap_icc_bpr0_el1
13741  *
13742  * AP Interrupt Controller Binary Point Register 0
13743  * Defines the point at which the priority value fields split
13744  *     into two parts, the group priority field and the subpriority
13745  *     field. The group priority field is used to determine interrupt
13746  *     preemption.
13747  */
13748 union bdk_ap_icc_bpr0_el1
13749 {
13750     uint32_t u;
13751     struct bdk_ap_icc_bpr0_el1_s
13752     {
13753 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13754         uint32_t reserved_3_31         : 29;
13755         uint32_t binarypoint           : 3;  /**< [  2:  0](R/W) The value of this field controls how the 8-bit interrupt
13756                                                                      priority field is split into a group priority field, used to
13757                                                                      determine interrupt preemption, and a subpriority field. This
13758                                                                      is done as follows:
13759 
13760                                                                  \<pre\>
13761                                                                  Binary point value  Group priority field    Subpriority field       Field with binary
13762                                                                  point
13763                                                                  0   [7:1]   [0]     ggggggg.s
13764                                                                  1   [7:2]   [1:0]   gggggg.ss
13765                                                                  2   [7:3]   [2:0]   ggggg.sss
13766                                                                  3   [7:4]   [3:0]   gggg.ssss
13767                                                                  4   [7:5]   [4:0]   ggg.sssss
13768                                                                  5   [7:6]   [5:0]   gg.ssssss
13769                                                                  6   [7]     [6:0]   g.sssssss
13770                                                                  7   No preemption   [7:0]   .ssssssss
13771                                                                  \</pre\> */
13772 #else /* Word 0 - Little Endian */
13773         uint32_t binarypoint           : 3;  /**< [  2:  0](R/W) The value of this field controls how the 8-bit interrupt
13774                                                                      priority field is split into a group priority field, used to
13775                                                                      determine interrupt preemption, and a subpriority field. This
13776                                                                      is done as follows:
13777 
13778                                                                  \<pre\>
13779                                                                  Binary point value  Group priority field    Subpriority field       Field with binary
13780                                                                  point
13781                                                                  0   [7:1]   [0]     ggggggg.s
13782                                                                  1   [7:2]   [1:0]   gggggg.ss
13783                                                                  2   [7:3]   [2:0]   ggggg.sss
13784                                                                  3   [7:4]   [3:0]   gggg.ssss
13785                                                                  4   [7:5]   [4:0]   ggg.sssss
13786                                                                  5   [7:6]   [5:0]   gg.ssssss
13787                                                                  6   [7]     [6:0]   g.sssssss
13788                                                                  7   No preemption   [7:0]   .ssssssss
13789                                                                  \</pre\> */
13790         uint32_t reserved_3_31         : 29;
13791 #endif /* Word 0 - End */
13792     } s;
13793     /* struct bdk_ap_icc_bpr0_el1_s cn; */
13794 };
13795 typedef union bdk_ap_icc_bpr0_el1 bdk_ap_icc_bpr0_el1_t;
13796 
13797 #define BDK_AP_ICC_BPR0_EL1 BDK_AP_ICC_BPR0_EL1_FUNC()
13798 static inline uint64_t BDK_AP_ICC_BPR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_BPR0_EL1_FUNC(void)13799 static inline uint64_t BDK_AP_ICC_BPR0_EL1_FUNC(void)
13800 {
13801     return 0x3000c080300ll;
13802 }
13803 
13804 #define typedef_BDK_AP_ICC_BPR0_EL1 bdk_ap_icc_bpr0_el1_t
13805 #define bustype_BDK_AP_ICC_BPR0_EL1 BDK_CSR_TYPE_SYSREG
13806 #define basename_BDK_AP_ICC_BPR0_EL1 "AP_ICC_BPR0_EL1"
13807 #define busnum_BDK_AP_ICC_BPR0_EL1 0
13808 #define arguments_BDK_AP_ICC_BPR0_EL1 -1,-1,-1,-1
13809 
13810 /**
13811  * Register (SYSREG) ap_icc_bpr1_el1
13812  *
13813  * AP Interrupt Controller Binary Point Register 1
13814  * Defines the point at which the priority value fields split
13815  *     into two parts, the group priority field and the subpriority
13816  *     field. The group priority field is used to determine Group 1
13817  *     interrupt preemption.
13818  */
13819 union bdk_ap_icc_bpr1_el1
13820 {
13821     uint32_t u;
13822     struct bdk_ap_icc_bpr1_el1_s
13823     {
13824 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13825         uint32_t reserved_3_31         : 29;
13826         uint32_t binarypoint           : 3;  /**< [  2:  0](R/W) The value of this field controls how the 8-bit interrupt
13827                                                                      priority field is split into a group priority field, used to
13828                                                                      determine interrupt preemption, and a subpriority field. This
13829                                                                      is done as follows:
13830                                                                  \<pre\>
13831                                                                  Binary point value  Group priority field    Subpriority field       Field with binary
13832                                                                  point
13833                                                                  0   [7:1]   [0]     ggggggg.s
13834                                                                  1   [7:2]   [1:0]   gggggg.ss
13835                                                                  2   [7:3]   [2:0]   ggggg.sss
13836                                                                  3   [7:4]   [3:0]   gggg.ssss
13837                                                                  4   [7:5]   [4:0]   ggg.sssss
13838                                                                  5   [7:6]   [5:0]   gg.ssssss
13839                                                                  6   [7]     [6:0]   g.sssssss
13840                                                                  7   No preemption   [7:0]   .ssssssss
13841                                                                  \</pre\> */
13842 #else /* Word 0 - Little Endian */
13843         uint32_t binarypoint           : 3;  /**< [  2:  0](R/W) The value of this field controls how the 8-bit interrupt
13844                                                                      priority field is split into a group priority field, used to
13845                                                                      determine interrupt preemption, and a subpriority field. This
13846                                                                      is done as follows:
13847                                                                  \<pre\>
13848                                                                  Binary point value  Group priority field    Subpriority field       Field with binary
13849                                                                  point
13850                                                                  0   [7:1]   [0]     ggggggg.s
13851                                                                  1   [7:2]   [1:0]   gggggg.ss
13852                                                                  2   [7:3]   [2:0]   ggggg.sss
13853                                                                  3   [7:4]   [3:0]   gggg.ssss
13854                                                                  4   [7:5]   [4:0]   ggg.sssss
13855                                                                  5   [7:6]   [5:0]   gg.ssssss
13856                                                                  6   [7]     [6:0]   g.sssssss
13857                                                                  7   No preemption   [7:0]   .ssssssss
13858                                                                  \</pre\> */
13859         uint32_t reserved_3_31         : 29;
13860 #endif /* Word 0 - End */
13861     } s;
13862     /* struct bdk_ap_icc_bpr1_el1_s cn; */
13863 };
13864 typedef union bdk_ap_icc_bpr1_el1 bdk_ap_icc_bpr1_el1_t;
13865 
13866 #define BDK_AP_ICC_BPR1_EL1 BDK_AP_ICC_BPR1_EL1_FUNC()
13867 static inline uint64_t BDK_AP_ICC_BPR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_BPR1_EL1_FUNC(void)13868 static inline uint64_t BDK_AP_ICC_BPR1_EL1_FUNC(void)
13869 {
13870     return 0x3000c0c0300ll;
13871 }
13872 
13873 #define typedef_BDK_AP_ICC_BPR1_EL1 bdk_ap_icc_bpr1_el1_t
13874 #define bustype_BDK_AP_ICC_BPR1_EL1 BDK_CSR_TYPE_SYSREG
13875 #define basename_BDK_AP_ICC_BPR1_EL1 "AP_ICC_BPR1_EL1"
13876 #define busnum_BDK_AP_ICC_BPR1_EL1 0
13877 #define arguments_BDK_AP_ICC_BPR1_EL1 -1,-1,-1,-1
13878 
13879 /**
13880  * Register (SYSREG) ap_icc_ctlr_el1
13881  *
13882  * AP Interrupt Controller Control EL1 Register
13883  * Controls aspects of the behaviour of the GIC CPU interface and
13884  *     provides information about the features implemented.
13885  */
13886 union bdk_ap_icc_ctlr_el1
13887 {
13888     uint32_t u;
13889     struct bdk_ap_icc_ctlr_el1_s
13890     {
13891 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
13892         uint32_t reserved_16_31        : 16;
13893         uint32_t a3v                   : 1;  /**< [ 15: 15](RO) Affinity 3 Valid. Read-only and writes are ignored. Possible
13894                                                                      values are:
13895                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[A3V].
13896                                                                  0 = The CPU interface logic only supports zero values of Affinity
13897                                                                      3 in SGI generation system registers.
13898                                                                  1 = The CPU interface logic supports nonzero values of Affinity 3
13899                                                                      in SGI generation system registers. */
13900         uint32_t seis                  : 1;  /**< [ 14: 14](RO) SEI Support. Read-only and writes are ignored. Indicates
13901                                                                      whether the CPU interface supports local generation of SEIs:
13902                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[SEIS].
13903                                                                  0 = The CPU interface logic does not support local generation of
13904                                                                      SEIs by the CPU interface.
13905                                                                  1 = The CPU interface logic supports local generation of SEIs by
13906                                                                      the CPU interface. */
13907         uint32_t idbits                : 3;  /**< [ 13: 11](RO) Identifier bits. Read-only and writes are ignored. The number
13908                                                                      of physical interrupt identifier bits supported:
13909                                                                  All other values are reserved.
13910                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[IDBITS].
13911                                                                  0x0 = 16 bits.
13912                                                                  0x1 = 24 bits. */
13913         uint32_t pribits               : 3;  /**< [ 10:  8](RO) Priority bits. Read-only and writes are ignored. The number of
13914                                                                      priority bits implemented, minus one.
13915                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[PRI] bits. */
13916         uint32_t reserved_7            : 1;
13917         uint32_t pmhe                  : 1;  /**< [  6:  6](R/W) Priority Mask Hint Enable.
13918                                                                  If EL3 is present and GICD_CTLR[DS] == 0, this bit is a read-
13919                                                                      only alias of AP_ICC_CTLR_EL3[PMHE].
13920                                                                  If EL3 is present and GICD_CTLR[DS] == 1, this bit is writable
13921                                                                      at EL1 and EL2. */
13922         uint32_t reserved_2_5          : 4;
13923         uint32_t eoimode               : 1;  /**< [  1:  1](R/W) Alias of AP_ICC_CTLR_EL3[EOI]mode_EL1{S,NS} as appropriate to the
13924                                                                      current Security state.
13925                                                                  Virtual accesses modify AP_ICH_VMCR_EL2[VEOIM]. */
13926         uint32_t cbpr                  : 1;  /**< [  0:  0](R/W) Common Binary Point Register.
13927                                                                  If EL3 is present and GICD_CTLR[DS] == 0, this bit is a read-
13928                                                                      only alias of AP_ICC_CTLR_EL3[CBPR]_EL1{S,NS} as appropriate.
13929                                                                  If EL3 is not present, this field resets to zero.
13930                                                                  If EL3 is present and GICD_CTLR[DS] == 1, this bit is writable
13931                                                                      at EL1 and EL2.
13932                                                                  Virtual accesses modify AP_ICH_VMCR_EL2[VCBPR]. An access is
13933                                                                      virtual when accessed at nonsecure EL1 and either of FIQ or
13934                                                                      IRQ has been virtualized.  That is, when (AP_SCR_EL3[NS] == 1 &&
13935                                                                      (AP_HCR_EL2[FMO] == 1 || AP_HCR_EL2[IMO] == 1)). */
13936 #else /* Word 0 - Little Endian */
13937         uint32_t cbpr                  : 1;  /**< [  0:  0](R/W) Common Binary Point Register.
13938                                                                  If EL3 is present and GICD_CTLR[DS] == 0, this bit is a read-
13939                                                                      only alias of AP_ICC_CTLR_EL3[CBPR]_EL1{S,NS} as appropriate.
13940                                                                  If EL3 is not present, this field resets to zero.
13941                                                                  If EL3 is present and GICD_CTLR[DS] == 1, this bit is writable
13942                                                                      at EL1 and EL2.
13943                                                                  Virtual accesses modify AP_ICH_VMCR_EL2[VCBPR]. An access is
13944                                                                      virtual when accessed at nonsecure EL1 and either of FIQ or
13945                                                                      IRQ has been virtualized.  That is, when (AP_SCR_EL3[NS] == 1 &&
13946                                                                      (AP_HCR_EL2[FMO] == 1 || AP_HCR_EL2[IMO] == 1)). */
13947         uint32_t eoimode               : 1;  /**< [  1:  1](R/W) Alias of AP_ICC_CTLR_EL3[EOI]mode_EL1{S,NS} as appropriate to the
13948                                                                      current Security state.
13949                                                                  Virtual accesses modify AP_ICH_VMCR_EL2[VEOIM]. */
13950         uint32_t reserved_2_5          : 4;
13951         uint32_t pmhe                  : 1;  /**< [  6:  6](R/W) Priority Mask Hint Enable.
13952                                                                  If EL3 is present and GICD_CTLR[DS] == 0, this bit is a read-
13953                                                                      only alias of AP_ICC_CTLR_EL3[PMHE].
13954                                                                  If EL3 is present and GICD_CTLR[DS] == 1, this bit is writable
13955                                                                      at EL1 and EL2. */
13956         uint32_t reserved_7            : 1;
13957         uint32_t pribits               : 3;  /**< [ 10:  8](RO) Priority bits. Read-only and writes are ignored. The number of
13958                                                                      priority bits implemented, minus one.
13959                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[PRI] bits. */
13960         uint32_t idbits                : 3;  /**< [ 13: 11](RO) Identifier bits. Read-only and writes are ignored. The number
13961                                                                      of physical interrupt identifier bits supported:
13962                                                                  All other values are reserved.
13963                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[IDBITS].
13964                                                                  0x0 = 16 bits.
13965                                                                  0x1 = 24 bits. */
13966         uint32_t seis                  : 1;  /**< [ 14: 14](RO) SEI Support. Read-only and writes are ignored. Indicates
13967                                                                      whether the CPU interface supports local generation of SEIs:
13968                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[SEIS].
13969                                                                  0 = The CPU interface logic does not support local generation of
13970                                                                      SEIs by the CPU interface.
13971                                                                  1 = The CPU interface logic supports local generation of SEIs by
13972                                                                      the CPU interface. */
13973         uint32_t a3v                   : 1;  /**< [ 15: 15](RO) Affinity 3 Valid. Read-only and writes are ignored. Possible
13974                                                                      values are:
13975                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[A3V].
13976                                                                  0 = The CPU interface logic only supports zero values of Affinity
13977                                                                      3 in SGI generation system registers.
13978                                                                  1 = The CPU interface logic supports nonzero values of Affinity 3
13979                                                                      in SGI generation system registers. */
13980         uint32_t reserved_16_31        : 16;
13981 #endif /* Word 0 - End */
13982     } s;
13983     /* struct bdk_ap_icc_ctlr_el1_s cn; */
13984 };
13985 typedef union bdk_ap_icc_ctlr_el1 bdk_ap_icc_ctlr_el1_t;
13986 
13987 #define BDK_AP_ICC_CTLR_EL1 BDK_AP_ICC_CTLR_EL1_FUNC()
13988 static inline uint64_t BDK_AP_ICC_CTLR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_CTLR_EL1_FUNC(void)13989 static inline uint64_t BDK_AP_ICC_CTLR_EL1_FUNC(void)
13990 {
13991     return 0x3000c0c0400ll;
13992 }
13993 
13994 #define typedef_BDK_AP_ICC_CTLR_EL1 bdk_ap_icc_ctlr_el1_t
13995 #define bustype_BDK_AP_ICC_CTLR_EL1 BDK_CSR_TYPE_SYSREG
13996 #define basename_BDK_AP_ICC_CTLR_EL1 "AP_ICC_CTLR_EL1"
13997 #define busnum_BDK_AP_ICC_CTLR_EL1 0
13998 #define arguments_BDK_AP_ICC_CTLR_EL1 -1,-1,-1,-1
13999 
14000 /**
14001  * Register (SYSREG) ap_icc_ctlr_el3
14002  *
14003  * AP Interrupt Controller Control EL3 Register
14004  * Controls aspects of the behaviour of the GIC CPU interface and
14005  *     provides information about the features implemented.
14006  */
14007 union bdk_ap_icc_ctlr_el3
14008 {
14009     uint32_t u;
14010     struct bdk_ap_icc_ctlr_el3_s
14011     {
14012 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14013         uint32_t reserved_16_31        : 16;
14014         uint32_t a3v                   : 1;  /**< [ 15: 15](RO) Affinity 3 Valid. Read-only and writes are ignored. Possible
14015                                                                      values are:
14016                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[A3V].
14017                                                                  0 = The CPU interface logic only supports zero values of Affinity
14018                                                                      3 in SGI generation system registers.
14019                                                                  1 = The CPU interface logic supports nonzero values of Affinity 3
14020                                                                      in SGI generation system registers. */
14021         uint32_t seis                  : 1;  /**< [ 14: 14](RO) SEI Support. Read-only and writes are ignored. Indicates
14022                                                                      whether the CPU interface supports generation of SEIs:
14023                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[SEIS].
14024                                                                  0 = The CPU interface logic does not support generation of SEIs.
14025                                                                  1 = The CPU interface logic supports generation of SEIs. */
14026         uint32_t idbits                : 3;  /**< [ 13: 11](RO) Identifier bits. Read-only and writes are ignored. The number
14027                                                                      of physical interrupt identifier bits supported:
14028                                                                  All other values are reserved.
14029                                                                  0x0 = 16 bits.
14030                                                                  0x1 = 24 bits. */
14031         uint32_t pribits               : 3;  /**< [ 10:  8](RO) Priority bits. Read-only and writes are ignored. The number of
14032                                                                      priority bits implemented, minus one. */
14033         uint32_t reserved_7            : 1;
14034         uint32_t pmhe                  : 1;  /**< [  6:  6](R/W) Priority Mask Hint Enable.
14035                                                                  When set, enables use of the PMR as a hint for interrupt
14036                                                                      distribution. */
14037         uint32_t rm                    : 1;  /**< [  5:  5](RO) Routing Modifier.  Note: In systems without EL3 or where the secure
14038                                                                  copy of AP_ICC_SRE_EL1 is RES1, this bit is RES0.
14039                                                                  This bit is used to modify the behaviour of
14040                                                                  AP_ICC_IAR0_EL1 and AP_ICC_IAR1_EL1 such that systems with legacy
14041                                                                  secure software may be supported correctly.
14042                                                                  0 = Secure Group 0 and nonsecure group 1 interrupts can be
14043                                                                      acknowleged and observed as the highest priority interrupt
14044                                                                      at EL3 in AArch64 or Monitor mode in AArch32.
14045                                                                  1 = Secure Group 0 and nonsecure group 1 interrupts cannot be
14046                                                                      acknowleged and observed as the highest priority interrupt
14047                                                                      at EL3 in AArch64 or Monitor mode in AArch32 but return
14048                                                                      special values. */
14049         uint32_t eoimode_el1ns         : 1;  /**< [  4:  4](R/W) EOI mode for interrupts handled at nonsecure EL1 and EL2. */
14050         uint32_t eoimode_el1s          : 1;  /**< [  3:  3](R/W) EOI mode for interrupts handled at secure EL1. */
14051         uint32_t eoimode_el3           : 1;  /**< [  2:  2](R/W) EOI mode for interrupts handled at EL3. */
14052         uint32_t cbpr_el1ns            : 1;  /**< [  1:  1](R/W) When set, nonsecure accesses to GICC_BPR and AP_ICC_BPR1_EL1
14053                                                                      access the state of AP_ICC_BPR0_EL1. AP_ICC_BPR0_EL1 is used to
14054                                                                      determine the preemption group for nonsecure group 1
14055                                                                      interrupts. */
14056         uint32_t cbpr_el1s             : 1;  /**< [  0:  0](R/W) When set, secure EL1 accesses to AP_ICC_BPR1_EL1 access the state
14057                                                                      of AP_ICC_BPR0_EL1. AP_ICC_BPR0_EL1 is used to determine the
14058                                                                      preemption group for Secure Group 1 interrupts. */
14059 #else /* Word 0 - Little Endian */
14060         uint32_t cbpr_el1s             : 1;  /**< [  0:  0](R/W) When set, secure EL1 accesses to AP_ICC_BPR1_EL1 access the state
14061                                                                      of AP_ICC_BPR0_EL1. AP_ICC_BPR0_EL1 is used to determine the
14062                                                                      preemption group for Secure Group 1 interrupts. */
14063         uint32_t cbpr_el1ns            : 1;  /**< [  1:  1](R/W) When set, nonsecure accesses to GICC_BPR and AP_ICC_BPR1_EL1
14064                                                                      access the state of AP_ICC_BPR0_EL1. AP_ICC_BPR0_EL1 is used to
14065                                                                      determine the preemption group for nonsecure group 1
14066                                                                      interrupts. */
14067         uint32_t eoimode_el3           : 1;  /**< [  2:  2](R/W) EOI mode for interrupts handled at EL3. */
14068         uint32_t eoimode_el1s          : 1;  /**< [  3:  3](R/W) EOI mode for interrupts handled at secure EL1. */
14069         uint32_t eoimode_el1ns         : 1;  /**< [  4:  4](R/W) EOI mode for interrupts handled at nonsecure EL1 and EL2. */
14070         uint32_t rm                    : 1;  /**< [  5:  5](RO) Routing Modifier.  Note: In systems without EL3 or where the secure
14071                                                                  copy of AP_ICC_SRE_EL1 is RES1, this bit is RES0.
14072                                                                  This bit is used to modify the behaviour of
14073                                                                  AP_ICC_IAR0_EL1 and AP_ICC_IAR1_EL1 such that systems with legacy
14074                                                                  secure software may be supported correctly.
14075                                                                  0 = Secure Group 0 and nonsecure group 1 interrupts can be
14076                                                                      acknowleged and observed as the highest priority interrupt
14077                                                                      at EL3 in AArch64 or Monitor mode in AArch32.
14078                                                                  1 = Secure Group 0 and nonsecure group 1 interrupts cannot be
14079                                                                      acknowleged and observed as the highest priority interrupt
14080                                                                      at EL3 in AArch64 or Monitor mode in AArch32 but return
14081                                                                      special values. */
14082         uint32_t pmhe                  : 1;  /**< [  6:  6](R/W) Priority Mask Hint Enable.
14083                                                                  When set, enables use of the PMR as a hint for interrupt
14084                                                                      distribution. */
14085         uint32_t reserved_7            : 1;
14086         uint32_t pribits               : 3;  /**< [ 10:  8](RO) Priority bits. Read-only and writes are ignored. The number of
14087                                                                      priority bits implemented, minus one. */
14088         uint32_t idbits                : 3;  /**< [ 13: 11](RO) Identifier bits. Read-only and writes are ignored. The number
14089                                                                      of physical interrupt identifier bits supported:
14090                                                                  All other values are reserved.
14091                                                                  0x0 = 16 bits.
14092                                                                  0x1 = 24 bits. */
14093         uint32_t seis                  : 1;  /**< [ 14: 14](RO) SEI Support. Read-only and writes are ignored. Indicates
14094                                                                      whether the CPU interface supports generation of SEIs:
14095                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[SEIS].
14096                                                                  0 = The CPU interface logic does not support generation of SEIs.
14097                                                                  1 = The CPU interface logic supports generation of SEIs. */
14098         uint32_t a3v                   : 1;  /**< [ 15: 15](RO) Affinity 3 Valid. Read-only and writes are ignored. Possible
14099                                                                      values are:
14100                                                                  Virtual accesses return the value from AP_ICH_VTR_EL2[A3V].
14101                                                                  0 = The CPU interface logic only supports zero values of Affinity
14102                                                                      3 in SGI generation system registers.
14103                                                                  1 = The CPU interface logic supports nonzero values of Affinity 3
14104                                                                      in SGI generation system registers. */
14105         uint32_t reserved_16_31        : 16;
14106 #endif /* Word 0 - End */
14107     } s;
14108     /* struct bdk_ap_icc_ctlr_el3_s cn; */
14109 };
14110 typedef union bdk_ap_icc_ctlr_el3 bdk_ap_icc_ctlr_el3_t;
14111 
14112 #define BDK_AP_ICC_CTLR_EL3 BDK_AP_ICC_CTLR_EL3_FUNC()
14113 static inline uint64_t BDK_AP_ICC_CTLR_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_CTLR_EL3_FUNC(void)14114 static inline uint64_t BDK_AP_ICC_CTLR_EL3_FUNC(void)
14115 {
14116     return 0x3060c0c0400ll;
14117 }
14118 
14119 #define typedef_BDK_AP_ICC_CTLR_EL3 bdk_ap_icc_ctlr_el3_t
14120 #define bustype_BDK_AP_ICC_CTLR_EL3 BDK_CSR_TYPE_SYSREG
14121 #define basename_BDK_AP_ICC_CTLR_EL3 "AP_ICC_CTLR_EL3"
14122 #define busnum_BDK_AP_ICC_CTLR_EL3 0
14123 #define arguments_BDK_AP_ICC_CTLR_EL3 -1,-1,-1,-1
14124 
14125 /**
14126  * Register (SYSREG) ap_icc_dir_el1
14127  *
14128  * AP Interrupt Controller Deactivate Interrupt Register
14129  * When interrupt priority drop is separated from interrupt
14130  *     deactivation, a write to this register deactivates the
14131  *     specified interrupt.
14132  */
14133 union bdk_ap_icc_dir_el1
14134 {
14135     uint32_t u;
14136     struct bdk_ap_icc_dir_el1_s
14137     {
14138 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14139         uint32_t reserved_24_31        : 8;
14140         uint32_t interruptid           : 24; /**< [ 23:  0](WO) The interrupt ID.
14141                                                                  This field has either 16 or 24 bits implemented. The number of
14142                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14143                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14144                                                                      [23:16] of this register are RES0. */
14145 #else /* Word 0 - Little Endian */
14146         uint32_t interruptid           : 24; /**< [ 23:  0](WO) The interrupt ID.
14147                                                                  This field has either 16 or 24 bits implemented. The number of
14148                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14149                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14150                                                                      [23:16] of this register are RES0. */
14151         uint32_t reserved_24_31        : 8;
14152 #endif /* Word 0 - End */
14153     } s;
14154     /* struct bdk_ap_icc_dir_el1_s cn; */
14155 };
14156 typedef union bdk_ap_icc_dir_el1 bdk_ap_icc_dir_el1_t;
14157 
14158 #define BDK_AP_ICC_DIR_EL1 BDK_AP_ICC_DIR_EL1_FUNC()
14159 static inline uint64_t BDK_AP_ICC_DIR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_DIR_EL1_FUNC(void)14160 static inline uint64_t BDK_AP_ICC_DIR_EL1_FUNC(void)
14161 {
14162     return 0x3000c0b0100ll;
14163 }
14164 
14165 #define typedef_BDK_AP_ICC_DIR_EL1 bdk_ap_icc_dir_el1_t
14166 #define bustype_BDK_AP_ICC_DIR_EL1 BDK_CSR_TYPE_SYSREG
14167 #define basename_BDK_AP_ICC_DIR_EL1 "AP_ICC_DIR_EL1"
14168 #define busnum_BDK_AP_ICC_DIR_EL1 0
14169 #define arguments_BDK_AP_ICC_DIR_EL1 -1,-1,-1,-1
14170 
14171 /**
14172  * Register (SYSREG) ap_icc_eoir0_el1
14173  *
14174  * AP Interrupt Controller End Of Interrupt Register 0
14175  * A processor writes to this register to inform the CPU
14176  *     interface that it has completed the processing of the
14177  *     specified interrupt.
14178  */
14179 union bdk_ap_icc_eoir0_el1
14180 {
14181     uint32_t u;
14182     struct bdk_ap_icc_eoir0_el1_s
14183     {
14184 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14185         uint32_t reserved_24_31        : 8;
14186         uint32_t intvector             : 24; /**< [ 23:  0](WO) The InterruptID value from the corresponding GICC_IAR access.
14187                                                                  This field has either 16 or 24 bits implemented. The number of
14188                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14189                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14190                                                                      [23:16] of this register are RES0. */
14191 #else /* Word 0 - Little Endian */
14192         uint32_t intvector             : 24; /**< [ 23:  0](WO) The InterruptID value from the corresponding GICC_IAR access.
14193                                                                  This field has either 16 or 24 bits implemented. The number of
14194                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14195                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14196                                                                      [23:16] of this register are RES0. */
14197         uint32_t reserved_24_31        : 8;
14198 #endif /* Word 0 - End */
14199     } s;
14200     /* struct bdk_ap_icc_eoir0_el1_s cn; */
14201 };
14202 typedef union bdk_ap_icc_eoir0_el1 bdk_ap_icc_eoir0_el1_t;
14203 
14204 #define BDK_AP_ICC_EOIR0_EL1 BDK_AP_ICC_EOIR0_EL1_FUNC()
14205 static inline uint64_t BDK_AP_ICC_EOIR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_EOIR0_EL1_FUNC(void)14206 static inline uint64_t BDK_AP_ICC_EOIR0_EL1_FUNC(void)
14207 {
14208     return 0x3000c080100ll;
14209 }
14210 
14211 #define typedef_BDK_AP_ICC_EOIR0_EL1 bdk_ap_icc_eoir0_el1_t
14212 #define bustype_BDK_AP_ICC_EOIR0_EL1 BDK_CSR_TYPE_SYSREG
14213 #define basename_BDK_AP_ICC_EOIR0_EL1 "AP_ICC_EOIR0_EL1"
14214 #define busnum_BDK_AP_ICC_EOIR0_EL1 0
14215 #define arguments_BDK_AP_ICC_EOIR0_EL1 -1,-1,-1,-1
14216 
14217 /**
14218  * Register (SYSREG) ap_icc_eoir1_el1
14219  *
14220  * AP Interrupt Controller End Of Interrupt Register 1
14221  * A processor writes to this register to inform the CPU
14222  *     interface that it has completed the processing of the
14223  *     specified Group 1 interrupt.
14224  */
14225 union bdk_ap_icc_eoir1_el1
14226 {
14227     uint32_t u;
14228     struct bdk_ap_icc_eoir1_el1_s
14229     {
14230 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14231         uint32_t reserved_24_31        : 8;
14232         uint32_t intvector             : 24; /**< [ 23:  0](WO) The InterruptID value from the corresponding GICC_IAR access.
14233                                                                  This field has either 16 or 24 bits implemented. The number of
14234                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14235                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14236                                                                      [23:16] of this register are RES0. */
14237 #else /* Word 0 - Little Endian */
14238         uint32_t intvector             : 24; /**< [ 23:  0](WO) The InterruptID value from the corresponding GICC_IAR access.
14239                                                                  This field has either 16 or 24 bits implemented. The number of
14240                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14241                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14242                                                                      [23:16] of this register are RES0. */
14243         uint32_t reserved_24_31        : 8;
14244 #endif /* Word 0 - End */
14245     } s;
14246     /* struct bdk_ap_icc_eoir1_el1_s cn; */
14247 };
14248 typedef union bdk_ap_icc_eoir1_el1 bdk_ap_icc_eoir1_el1_t;
14249 
14250 #define BDK_AP_ICC_EOIR1_EL1 BDK_AP_ICC_EOIR1_EL1_FUNC()
14251 static inline uint64_t BDK_AP_ICC_EOIR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_EOIR1_EL1_FUNC(void)14252 static inline uint64_t BDK_AP_ICC_EOIR1_EL1_FUNC(void)
14253 {
14254     return 0x3000c0c0100ll;
14255 }
14256 
14257 #define typedef_BDK_AP_ICC_EOIR1_EL1 bdk_ap_icc_eoir1_el1_t
14258 #define bustype_BDK_AP_ICC_EOIR1_EL1 BDK_CSR_TYPE_SYSREG
14259 #define basename_BDK_AP_ICC_EOIR1_EL1 "AP_ICC_EOIR1_EL1"
14260 #define busnum_BDK_AP_ICC_EOIR1_EL1 0
14261 #define arguments_BDK_AP_ICC_EOIR1_EL1 -1,-1,-1,-1
14262 
14263 /**
14264  * Register (SYSREG) ap_icc_hppir0_el1
14265  *
14266  * AP Interrupt Controller Highest Priority Pending Interrupt Register 0
14267  * Indicates the Interrupt ID, and processor ID if appropriate,
14268  *     of the highest priority pending interrupt on the CPU
14269  *     interface.
14270  */
14271 union bdk_ap_icc_hppir0_el1
14272 {
14273     uint32_t u;
14274     struct bdk_ap_icc_hppir0_el1_s
14275     {
14276 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14277         uint32_t reserved_24_31        : 8;
14278         uint32_t intvector             : 24; /**< [ 23:  0](RO) The interrupt ID of the highest priority pending interrupt.
14279                                                                  This field has either 16 or 24 bits implemented. The number of
14280                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14281                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14282                                                                      [23:16] of this register are RES0. */
14283 #else /* Word 0 - Little Endian */
14284         uint32_t intvector             : 24; /**< [ 23:  0](RO) The interrupt ID of the highest priority pending interrupt.
14285                                                                  This field has either 16 or 24 bits implemented. The number of
14286                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14287                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14288                                                                      [23:16] of this register are RES0. */
14289         uint32_t reserved_24_31        : 8;
14290 #endif /* Word 0 - End */
14291     } s;
14292     /* struct bdk_ap_icc_hppir0_el1_s cn; */
14293 };
14294 typedef union bdk_ap_icc_hppir0_el1 bdk_ap_icc_hppir0_el1_t;
14295 
14296 #define BDK_AP_ICC_HPPIR0_EL1 BDK_AP_ICC_HPPIR0_EL1_FUNC()
14297 static inline uint64_t BDK_AP_ICC_HPPIR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_HPPIR0_EL1_FUNC(void)14298 static inline uint64_t BDK_AP_ICC_HPPIR0_EL1_FUNC(void)
14299 {
14300     return 0x3000c080200ll;
14301 }
14302 
14303 #define typedef_BDK_AP_ICC_HPPIR0_EL1 bdk_ap_icc_hppir0_el1_t
14304 #define bustype_BDK_AP_ICC_HPPIR0_EL1 BDK_CSR_TYPE_SYSREG
14305 #define basename_BDK_AP_ICC_HPPIR0_EL1 "AP_ICC_HPPIR0_EL1"
14306 #define busnum_BDK_AP_ICC_HPPIR0_EL1 0
14307 #define arguments_BDK_AP_ICC_HPPIR0_EL1 -1,-1,-1,-1
14308 
14309 /**
14310  * Register (SYSREG) ap_icc_hppir1_el1
14311  *
14312  * AP Interrupt Controller Highest Priority Pending Interrupt Register 1
14313  * If the highest priority pending interrupt on the CPU interface
14314  *     is a Group 1 interrupt, returns the interrupt ID of that
14315  *     interrupt. Otherwise, returns a spurious interrupt ID of 1023.
14316  */
14317 union bdk_ap_icc_hppir1_el1
14318 {
14319     uint32_t u;
14320     struct bdk_ap_icc_hppir1_el1_s
14321     {
14322 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14323         uint32_t reserved_24_31        : 8;
14324         uint32_t intvector             : 24; /**< [ 23:  0](RO) The interrupt ID of the highest priority pending interrupt.
14325 
14326                                                                  This field has either 16 or 24 bits implemented. The number of
14327                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14328                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14329                                                                      [23:16] of this register are RES0. */
14330 #else /* Word 0 - Little Endian */
14331         uint32_t intvector             : 24; /**< [ 23:  0](RO) The interrupt ID of the highest priority pending interrupt.
14332 
14333                                                                  This field has either 16 or 24 bits implemented. The number of
14334                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14335                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14336                                                                      [23:16] of this register are RES0. */
14337         uint32_t reserved_24_31        : 8;
14338 #endif /* Word 0 - End */
14339     } s;
14340     /* struct bdk_ap_icc_hppir1_el1_s cn; */
14341 };
14342 typedef union bdk_ap_icc_hppir1_el1 bdk_ap_icc_hppir1_el1_t;
14343 
14344 #define BDK_AP_ICC_HPPIR1_EL1 BDK_AP_ICC_HPPIR1_EL1_FUNC()
14345 static inline uint64_t BDK_AP_ICC_HPPIR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_HPPIR1_EL1_FUNC(void)14346 static inline uint64_t BDK_AP_ICC_HPPIR1_EL1_FUNC(void)
14347 {
14348     return 0x3000c0c0200ll;
14349 }
14350 
14351 #define typedef_BDK_AP_ICC_HPPIR1_EL1 bdk_ap_icc_hppir1_el1_t
14352 #define bustype_BDK_AP_ICC_HPPIR1_EL1 BDK_CSR_TYPE_SYSREG
14353 #define basename_BDK_AP_ICC_HPPIR1_EL1 "AP_ICC_HPPIR1_EL1"
14354 #define busnum_BDK_AP_ICC_HPPIR1_EL1 0
14355 #define arguments_BDK_AP_ICC_HPPIR1_EL1 -1,-1,-1,-1
14356 
14357 /**
14358  * Register (SYSREG) ap_icc_iar0_el1
14359  *
14360  * AP Interrupt Controller Interrupt Acknowledge Register 0
14361  * The processor reads this register to obtain the interrupt ID
14362  *     of the signaled interrupt. This read acts as an acknowledge
14363  *     for the interrupt.
14364  */
14365 union bdk_ap_icc_iar0_el1
14366 {
14367     uint32_t u;
14368     struct bdk_ap_icc_iar0_el1_s
14369     {
14370 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14371         uint32_t reserved_24_31        : 8;
14372         uint32_t intvector             : 24; /**< [ 23:  0](RO) The ID of the signaled interrupt. IDs 1020 to 1023 are
14373                                                                      reserved and convey additional information such as spurious
14374                                                                      interrupts.
14375 
14376                                                                  This field has either 16 or 24 bits implemented. The number of
14377                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14378                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14379                                                                      [23:16] of this register are RES0. */
14380 #else /* Word 0 - Little Endian */
14381         uint32_t intvector             : 24; /**< [ 23:  0](RO) The ID of the signaled interrupt. IDs 1020 to 1023 are
14382                                                                      reserved and convey additional information such as spurious
14383                                                                      interrupts.
14384 
14385                                                                  This field has either 16 or 24 bits implemented. The number of
14386                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14387                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14388                                                                      [23:16] of this register are RES0. */
14389         uint32_t reserved_24_31        : 8;
14390 #endif /* Word 0 - End */
14391     } s;
14392     /* struct bdk_ap_icc_iar0_el1_s cn; */
14393 };
14394 typedef union bdk_ap_icc_iar0_el1 bdk_ap_icc_iar0_el1_t;
14395 
14396 #define BDK_AP_ICC_IAR0_EL1 BDK_AP_ICC_IAR0_EL1_FUNC()
14397 static inline uint64_t BDK_AP_ICC_IAR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_IAR0_EL1_FUNC(void)14398 static inline uint64_t BDK_AP_ICC_IAR0_EL1_FUNC(void)
14399 {
14400     return 0x3000c080000ll;
14401 }
14402 
14403 #define typedef_BDK_AP_ICC_IAR0_EL1 bdk_ap_icc_iar0_el1_t
14404 #define bustype_BDK_AP_ICC_IAR0_EL1 BDK_CSR_TYPE_SYSREG
14405 #define basename_BDK_AP_ICC_IAR0_EL1 "AP_ICC_IAR0_EL1"
14406 #define busnum_BDK_AP_ICC_IAR0_EL1 0
14407 #define arguments_BDK_AP_ICC_IAR0_EL1 -1,-1,-1,-1
14408 
14409 /**
14410  * Register (SYSREG) ap_icc_iar1_el1
14411  *
14412  * AP Interrupt Controller Interrupt Acknowledge Register 1
14413  * The processor reads this register to obtain the interrupt ID
14414  *     of the signaled Group 1 interrupt. This read acts as an
14415  *     acknowledge for the interrupt.
14416  */
14417 union bdk_ap_icc_iar1_el1
14418 {
14419     uint32_t u;
14420     struct bdk_ap_icc_iar1_el1_s
14421     {
14422 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14423         uint32_t reserved_24_31        : 8;
14424         uint32_t intvector             : 24; /**< [ 23:  0](RO) The ID of the signaled interrupt. IDs 1020 to 1023 are
14425                                                                      reserved and convey additional information such as spurious
14426                                                                      interrupts.
14427 
14428                                                                  This field has either 16 or 24 bits implemented. The number of
14429                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14430                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14431                                                                      [23:16] of this register are RES0. */
14432 #else /* Word 0 - Little Endian */
14433         uint32_t intvector             : 24; /**< [ 23:  0](RO) The ID of the signaled interrupt. IDs 1020 to 1023 are
14434                                                                      reserved and convey additional information such as spurious
14435                                                                      interrupts.
14436 
14437                                                                  This field has either 16 or 24 bits implemented. The number of
14438                                                                      implemented bits can be found in AP_ICC_CTLR_EL1[IDBITS] and
14439                                                                      AP_ICC_CTLR_EL3[IDBITS]. If only 16 bits are implemented, bits
14440                                                                      [23:16] of this register are RES0. */
14441         uint32_t reserved_24_31        : 8;
14442 #endif /* Word 0 - End */
14443     } s;
14444     /* struct bdk_ap_icc_iar1_el1_s cn; */
14445 };
14446 typedef union bdk_ap_icc_iar1_el1 bdk_ap_icc_iar1_el1_t;
14447 
14448 #define BDK_AP_ICC_IAR1_EL1 BDK_AP_ICC_IAR1_EL1_FUNC()
14449 static inline uint64_t BDK_AP_ICC_IAR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_IAR1_EL1_FUNC(void)14450 static inline uint64_t BDK_AP_ICC_IAR1_EL1_FUNC(void)
14451 {
14452     return 0x3000c0c0000ll;
14453 }
14454 
14455 #define typedef_BDK_AP_ICC_IAR1_EL1 bdk_ap_icc_iar1_el1_t
14456 #define bustype_BDK_AP_ICC_IAR1_EL1 BDK_CSR_TYPE_SYSREG
14457 #define basename_BDK_AP_ICC_IAR1_EL1 "AP_ICC_IAR1_EL1"
14458 #define busnum_BDK_AP_ICC_IAR1_EL1 0
14459 #define arguments_BDK_AP_ICC_IAR1_EL1 -1,-1,-1,-1
14460 
14461 /**
14462  * Register (SYSREG) ap_icc_igrpen0_el1
14463  *
14464  * AP Interrupt Controller Interrupt Group 0 Enable Register
14465  * Controls whether Group 0 interrupts are enabled or not.
14466  */
14467 union bdk_ap_icc_igrpen0_el1
14468 {
14469     uint32_t u;
14470     struct bdk_ap_icc_igrpen0_el1_s
14471     {
14472 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14473         uint32_t reserved_1_31         : 31;
14474         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables Group 0 interrupts.
14475                                                                  Virtual accesses to this register update AP_ICH_VMCR_EL2[VENG0].
14476                                                                  0 = Group 0 interrupts are disabled.
14477                                                                  1 = Group 0 interrupts are enabled. */
14478 #else /* Word 0 - Little Endian */
14479         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables Group 0 interrupts.
14480                                                                  Virtual accesses to this register update AP_ICH_VMCR_EL2[VENG0].
14481                                                                  0 = Group 0 interrupts are disabled.
14482                                                                  1 = Group 0 interrupts are enabled. */
14483         uint32_t reserved_1_31         : 31;
14484 #endif /* Word 0 - End */
14485     } s;
14486     /* struct bdk_ap_icc_igrpen0_el1_s cn; */
14487 };
14488 typedef union bdk_ap_icc_igrpen0_el1 bdk_ap_icc_igrpen0_el1_t;
14489 
14490 #define BDK_AP_ICC_IGRPEN0_EL1 BDK_AP_ICC_IGRPEN0_EL1_FUNC()
14491 static inline uint64_t BDK_AP_ICC_IGRPEN0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_IGRPEN0_EL1_FUNC(void)14492 static inline uint64_t BDK_AP_ICC_IGRPEN0_EL1_FUNC(void)
14493 {
14494     return 0x3000c0c0600ll;
14495 }
14496 
14497 #define typedef_BDK_AP_ICC_IGRPEN0_EL1 bdk_ap_icc_igrpen0_el1_t
14498 #define bustype_BDK_AP_ICC_IGRPEN0_EL1 BDK_CSR_TYPE_SYSREG
14499 #define basename_BDK_AP_ICC_IGRPEN0_EL1 "AP_ICC_IGRPEN0_EL1"
14500 #define busnum_BDK_AP_ICC_IGRPEN0_EL1 0
14501 #define arguments_BDK_AP_ICC_IGRPEN0_EL1 -1,-1,-1,-1
14502 
14503 /**
14504  * Register (SYSREG) ap_icc_igrpen1_el1
14505  *
14506  * AP Interrupt Controller Interrupt Group 1 Enable Register
14507  * Controls whether Group 1 interrupts are enabled for the
14508  *     current Security state.
14509  */
14510 union bdk_ap_icc_igrpen1_el1
14511 {
14512     uint32_t u;
14513     struct bdk_ap_icc_igrpen1_el1_s
14514     {
14515 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14516         uint32_t reserved_1_31         : 31;
14517         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables Group 1 interrupts for the current Security state.
14518                                                                  Virtual accesses to this register update AP_ICH_VMCR_EL2[VENG1].
14519                                                                  When this register is accessed at EL3, the copy of this
14520                                                                      register appropriate to the current setting of AP_SCR_EL3[NS] is
14521                                                                      accessed.
14522                                                                  0 = Group 1 interrupts are disabled for the current Security
14523                                                                      state.
14524                                                                  1 = Group 1 interrupts are enabled for the current Security state. */
14525 #else /* Word 0 - Little Endian */
14526         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables Group 1 interrupts for the current Security state.
14527                                                                  Virtual accesses to this register update AP_ICH_VMCR_EL2[VENG1].
14528                                                                  When this register is accessed at EL3, the copy of this
14529                                                                      register appropriate to the current setting of AP_SCR_EL3[NS] is
14530                                                                      accessed.
14531                                                                  0 = Group 1 interrupts are disabled for the current Security
14532                                                                      state.
14533                                                                  1 = Group 1 interrupts are enabled for the current Security state. */
14534         uint32_t reserved_1_31         : 31;
14535 #endif /* Word 0 - End */
14536     } s;
14537     /* struct bdk_ap_icc_igrpen1_el1_s cn; */
14538 };
14539 typedef union bdk_ap_icc_igrpen1_el1 bdk_ap_icc_igrpen1_el1_t;
14540 
14541 #define BDK_AP_ICC_IGRPEN1_EL1 BDK_AP_ICC_IGRPEN1_EL1_FUNC()
14542 static inline uint64_t BDK_AP_ICC_IGRPEN1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_IGRPEN1_EL1_FUNC(void)14543 static inline uint64_t BDK_AP_ICC_IGRPEN1_EL1_FUNC(void)
14544 {
14545     return 0x3000c0c0700ll;
14546 }
14547 
14548 #define typedef_BDK_AP_ICC_IGRPEN1_EL1 bdk_ap_icc_igrpen1_el1_t
14549 #define bustype_BDK_AP_ICC_IGRPEN1_EL1 BDK_CSR_TYPE_SYSREG
14550 #define basename_BDK_AP_ICC_IGRPEN1_EL1 "AP_ICC_IGRPEN1_EL1"
14551 #define busnum_BDK_AP_ICC_IGRPEN1_EL1 0
14552 #define arguments_BDK_AP_ICC_IGRPEN1_EL1 -1,-1,-1,-1
14553 
14554 /**
14555  * Register (SYSREG) ap_icc_igrpen1_el3
14556  *
14557  * AP Interrupt Controller Interrupt Group 1 Enable EL3 Register
14558  * Controls whether Group 1 interrupts are enabled or not.
14559  */
14560 union bdk_ap_icc_igrpen1_el3
14561 {
14562     uint32_t u;
14563     struct bdk_ap_icc_igrpen1_el3_s
14564     {
14565 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14566         uint32_t reserved_2_31         : 30;
14567         uint32_t enablegrp1s           : 1;  /**< [  1:  1](R/W) Enables Group 1 interrupts for the Secure state.
14568                                                                  0 = Group 1 interrupts are disabled for the Secure state.
14569                                                                  1 = Group 1 interrupts are enabled for the Secure state. */
14570         uint32_t enablegrp1ns          : 1;  /**< [  0:  0](R/W) Enables Group 1 interrupts for the nonsecure state.
14571                                                                  0 = Group 1 interrupts are disabled for the nonsecure state.
14572                                                                  1 = Group 1 interrupts are enabled for the nonsecure state. */
14573 #else /* Word 0 - Little Endian */
14574         uint32_t enablegrp1ns          : 1;  /**< [  0:  0](R/W) Enables Group 1 interrupts for the nonsecure state.
14575                                                                  0 = Group 1 interrupts are disabled for the nonsecure state.
14576                                                                  1 = Group 1 interrupts are enabled for the nonsecure state. */
14577         uint32_t enablegrp1s           : 1;  /**< [  1:  1](R/W) Enables Group 1 interrupts for the Secure state.
14578                                                                  0 = Group 1 interrupts are disabled for the Secure state.
14579                                                                  1 = Group 1 interrupts are enabled for the Secure state. */
14580         uint32_t reserved_2_31         : 30;
14581 #endif /* Word 0 - End */
14582     } s;
14583     /* struct bdk_ap_icc_igrpen1_el3_s cn; */
14584 };
14585 typedef union bdk_ap_icc_igrpen1_el3 bdk_ap_icc_igrpen1_el3_t;
14586 
14587 #define BDK_AP_ICC_IGRPEN1_EL3 BDK_AP_ICC_IGRPEN1_EL3_FUNC()
14588 static inline uint64_t BDK_AP_ICC_IGRPEN1_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_IGRPEN1_EL3_FUNC(void)14589 static inline uint64_t BDK_AP_ICC_IGRPEN1_EL3_FUNC(void)
14590 {
14591     return 0x3060c0c0700ll;
14592 }
14593 
14594 #define typedef_BDK_AP_ICC_IGRPEN1_EL3 bdk_ap_icc_igrpen1_el3_t
14595 #define bustype_BDK_AP_ICC_IGRPEN1_EL3 BDK_CSR_TYPE_SYSREG
14596 #define basename_BDK_AP_ICC_IGRPEN1_EL3 "AP_ICC_IGRPEN1_EL3"
14597 #define busnum_BDK_AP_ICC_IGRPEN1_EL3 0
14598 #define arguments_BDK_AP_ICC_IGRPEN1_EL3 -1,-1,-1,-1
14599 
14600 /**
14601  * Register (SYSREG) ap_icc_pmr_el1
14602  *
14603  * AP Interrupt Controller Interrupt Priority Mask Register
14604  * Provides an interrupt priority filter. Only interrupts with
14605  *     higher priority than the value in this register are signaled
14606  *     to the processor.
14607  */
14608 union bdk_ap_icc_pmr_el1
14609 {
14610     uint32_t u;
14611     struct bdk_ap_icc_pmr_el1_s
14612     {
14613 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14614         uint32_t reserved_8_31         : 24;
14615         uint32_t pri                   : 8;  /**< [  7:  0](R/W) The priority mask level for the CPU interface. If the priority
14616                                                                      of an interrupt is higher than the value indicated by this
14617                                                                      field, the interface signals the interrupt to the processor.
14618 
14619                                                                  If the GIC supports fewer than 256 priority levels then some
14620                                                                      bits are RAZ/WI, as follows:
14621                                                                  - 128 supported levels: Bit [0] = 0.
14622                                                                  - 64 supported levels: Bits [1:0] =0b00
14623                                                                  - 32 supported levels: Bits [2:0] =0b000
14624                                                                  - 16 supported levels: Bits [3:0] =0b0000
14625 
14626                                                                  The possible priority field values are as follows:
14627 
14628                                                                  \<pre\>
14629                                                                  Implemented priority bits
14630                                                                           Possible priority field values
14631                                                                                      Number of priority levels
14632                                                                  [7:0]       0x000xFF        256
14633                                                                  [7:1]       0x000xFE        128
14634                                                                  [7:2]       0x000xFC        64
14635                                                                  [7:3]       0x000xF8        32
14636                                                                  [7:4]       0x000xF0        16
14637                                                                  \</pre\> */
14638 #else /* Word 0 - Little Endian */
14639         uint32_t pri                   : 8;  /**< [  7:  0](R/W) The priority mask level for the CPU interface. If the priority
14640                                                                      of an interrupt is higher than the value indicated by this
14641                                                                      field, the interface signals the interrupt to the processor.
14642 
14643                                                                  If the GIC supports fewer than 256 priority levels then some
14644                                                                      bits are RAZ/WI, as follows:
14645                                                                  - 128 supported levels: Bit [0] = 0.
14646                                                                  - 64 supported levels: Bits [1:0] =0b00
14647                                                                  - 32 supported levels: Bits [2:0] =0b000
14648                                                                  - 16 supported levels: Bits [3:0] =0b0000
14649 
14650                                                                  The possible priority field values are as follows:
14651 
14652                                                                  \<pre\>
14653                                                                  Implemented priority bits
14654                                                                           Possible priority field values
14655                                                                                      Number of priority levels
14656                                                                  [7:0]       0x000xFF        256
14657                                                                  [7:1]       0x000xFE        128
14658                                                                  [7:2]       0x000xFC        64
14659                                                                  [7:3]       0x000xF8        32
14660                                                                  [7:4]       0x000xF0        16
14661                                                                  \</pre\> */
14662         uint32_t reserved_8_31         : 24;
14663 #endif /* Word 0 - End */
14664     } s;
14665     /* struct bdk_ap_icc_pmr_el1_s cn; */
14666 };
14667 typedef union bdk_ap_icc_pmr_el1 bdk_ap_icc_pmr_el1_t;
14668 
14669 #define BDK_AP_ICC_PMR_EL1 BDK_AP_ICC_PMR_EL1_FUNC()
14670 static inline uint64_t BDK_AP_ICC_PMR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_PMR_EL1_FUNC(void)14671 static inline uint64_t BDK_AP_ICC_PMR_EL1_FUNC(void)
14672 {
14673     return 0x30004060000ll;
14674 }
14675 
14676 #define typedef_BDK_AP_ICC_PMR_EL1 bdk_ap_icc_pmr_el1_t
14677 #define bustype_BDK_AP_ICC_PMR_EL1 BDK_CSR_TYPE_SYSREG
14678 #define basename_BDK_AP_ICC_PMR_EL1 "AP_ICC_PMR_EL1"
14679 #define busnum_BDK_AP_ICC_PMR_EL1 0
14680 #define arguments_BDK_AP_ICC_PMR_EL1 -1,-1,-1,-1
14681 
14682 /**
14683  * Register (SYSREG) ap_icc_rpr_el1
14684  *
14685  * AP Interrupt Controller Running Priority Register
14686  * Indicates the Running priority of the CPU interface.
14687  */
14688 union bdk_ap_icc_rpr_el1
14689 {
14690     uint32_t u;
14691     struct bdk_ap_icc_rpr_el1_s
14692     {
14693 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14694         uint32_t reserved_8_31         : 24;
14695         uint32_t pri                   : 8;  /**< [  7:  0](R/W) The current running priority on the CPU interface. This is the
14696                                                                      priority of the current active interrupt. */
14697 #else /* Word 0 - Little Endian */
14698         uint32_t pri                   : 8;  /**< [  7:  0](R/W) The current running priority on the CPU interface. This is the
14699                                                                      priority of the current active interrupt. */
14700         uint32_t reserved_8_31         : 24;
14701 #endif /* Word 0 - End */
14702     } s;
14703     /* struct bdk_ap_icc_rpr_el1_s cn; */
14704 };
14705 typedef union bdk_ap_icc_rpr_el1 bdk_ap_icc_rpr_el1_t;
14706 
14707 #define BDK_AP_ICC_RPR_EL1 BDK_AP_ICC_RPR_EL1_FUNC()
14708 static inline uint64_t BDK_AP_ICC_RPR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_RPR_EL1_FUNC(void)14709 static inline uint64_t BDK_AP_ICC_RPR_EL1_FUNC(void)
14710 {
14711     return 0x3000c0b0300ll;
14712 }
14713 
14714 #define typedef_BDK_AP_ICC_RPR_EL1 bdk_ap_icc_rpr_el1_t
14715 #define bustype_BDK_AP_ICC_RPR_EL1 BDK_CSR_TYPE_SYSREG
14716 #define basename_BDK_AP_ICC_RPR_EL1 "AP_ICC_RPR_EL1"
14717 #define busnum_BDK_AP_ICC_RPR_EL1 0
14718 #define arguments_BDK_AP_ICC_RPR_EL1 -1,-1,-1,-1
14719 
14720 /**
14721  * Register (SYSREG) ap_icc_seien_el1
14722  *
14723  * AP Interrupt Controller System Error Interrupt Enable Register
14724  * Controls whether System Error Interrupts generated by bus
14725  *     message are enabled.
14726  */
14727 union bdk_ap_icc_seien_el1
14728 {
14729     uint32_t u;
14730     struct bdk_ap_icc_seien_el1_s
14731     {
14732 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14733         uint32_t reserved_1_31         : 31;
14734         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables System Error Interrupts generated by bus message.
14735                                                                  Virtual accesses to this register update AP_ICH_VMCR_EL2[VENSEI].
14736                                                                  0 = System Error Interrupts generated by bus message are disabled.
14737                                                                  1 = System Error Interrupts generated by bus message are enabled. */
14738 #else /* Word 0 - Little Endian */
14739         uint32_t enable                : 1;  /**< [  0:  0](R/W) Enables System Error Interrupts generated by bus message.
14740                                                                  Virtual accesses to this register update AP_ICH_VMCR_EL2[VENSEI].
14741                                                                  0 = System Error Interrupts generated by bus message are disabled.
14742                                                                  1 = System Error Interrupts generated by bus message are enabled. */
14743         uint32_t reserved_1_31         : 31;
14744 #endif /* Word 0 - End */
14745     } s;
14746     /* struct bdk_ap_icc_seien_el1_s cn; */
14747 };
14748 typedef union bdk_ap_icc_seien_el1 bdk_ap_icc_seien_el1_t;
14749 
14750 #define BDK_AP_ICC_SEIEN_EL1 BDK_AP_ICC_SEIEN_EL1_FUNC()
14751 static inline uint64_t BDK_AP_ICC_SEIEN_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_SEIEN_EL1_FUNC(void)14752 static inline uint64_t BDK_AP_ICC_SEIEN_EL1_FUNC(void)
14753 {
14754     if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
14755         return 0x3000c0d0000ll;
14756     __bdk_csr_fatal("AP_ICC_SEIEN_EL1", 0, 0, 0, 0, 0);
14757 }
14758 
14759 #define typedef_BDK_AP_ICC_SEIEN_EL1 bdk_ap_icc_seien_el1_t
14760 #define bustype_BDK_AP_ICC_SEIEN_EL1 BDK_CSR_TYPE_SYSREG
14761 #define basename_BDK_AP_ICC_SEIEN_EL1 "AP_ICC_SEIEN_EL1"
14762 #define busnum_BDK_AP_ICC_SEIEN_EL1 0
14763 #define arguments_BDK_AP_ICC_SEIEN_EL1 -1,-1,-1,-1
14764 
14765 /**
14766  * Register (SYSREG) ap_icc_sgi0r_el1
14767  *
14768  * AP Interrupt Controller Software Generated Interrupt group 0 Register
14769  * Provides software the ability to generate secure group 0 SGIs,
14770  *     including from the nonsecure state when permitted by
14771  *     GICR_NSACR.
14772  */
14773 union bdk_ap_icc_sgi0r_el1
14774 {
14775     uint64_t u;
14776     struct bdk_ap_icc_sgi0r_el1_s
14777     {
14778 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14779         uint64_t reserved_56_63        : 8;
14780         uint64_t aff3                  : 8;  /**< [ 55: 48](R/W) The affinity 3 value of the affinity path of the cluster for
14781                                                                      which SGI interrupts will be generated. */
14782         uint64_t reserved_41_47        : 7;
14783         uint64_t irm                   : 1;  /**< [ 40: 40](R/W) Interrupt Routing Mode. Determines how the generated
14784                                                                      interrupts should be distributed to processors. Possible
14785                                                                      values are:
14786                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
14787                                                                      list}. In this routing, a, b, and c are the values of fields
14788                                                                      Aff3, Aff2, and Aff1 respectively.
14789                                                                  1 = Interrupts routed to all processors in the system, excluding
14790                                                                      "self". */
14791         uint64_t aff2                  : 8;  /**< [ 39: 32](R/W) The affinity 2 value of the affinity path of the cluster for
14792                                                                      which SGI interrupts will be generated. */
14793         uint64_t reserved_28_31        : 4;
14794         uint64_t sgiid                 : 4;  /**< [ 27: 24](R/W) SGI Interrupt ID. */
14795         uint64_t aff1                  : 8;  /**< [ 23: 16](R/W) The affinity 1 value of the affinity path of the cluster for
14796                                                                      which SGI interrupts will be generated. */
14797         uint64_t targetlist            : 16; /**< [ 15:  0](R/W) Target List. The set of processors for which SGI interrupts
14798                                                                      will be generated. Each bit corresponds to the processor
14799                                                                      within a cluster with an Affinity 0 value equal to the bit
14800                                                                      number.
14801 
14802                                                                  If a bit is 1 and the bit does not correspond to a valid
14803                                                                      target processor, the bit must be ignored by the Distributor.
14804                                                                      In such cases, a Distributor may optionally generate an SError
14805                                                                      interrupt.
14806 
14807                                                                  This restricts distribution of SGIs to the first 16 processors
14808                                                                      of an affinity 1 cluster. */
14809 #else /* Word 0 - Little Endian */
14810         uint64_t targetlist            : 16; /**< [ 15:  0](R/W) Target List. The set of processors for which SGI interrupts
14811                                                                      will be generated. Each bit corresponds to the processor
14812                                                                      within a cluster with an Affinity 0 value equal to the bit
14813                                                                      number.
14814 
14815                                                                  If a bit is 1 and the bit does not correspond to a valid
14816                                                                      target processor, the bit must be ignored by the Distributor.
14817                                                                      In such cases, a Distributor may optionally generate an SError
14818                                                                      interrupt.
14819 
14820                                                                  This restricts distribution of SGIs to the first 16 processors
14821                                                                      of an affinity 1 cluster. */
14822         uint64_t aff1                  : 8;  /**< [ 23: 16](R/W) The affinity 1 value of the affinity path of the cluster for
14823                                                                      which SGI interrupts will be generated. */
14824         uint64_t sgiid                 : 4;  /**< [ 27: 24](R/W) SGI Interrupt ID. */
14825         uint64_t reserved_28_31        : 4;
14826         uint64_t aff2                  : 8;  /**< [ 39: 32](R/W) The affinity 2 value of the affinity path of the cluster for
14827                                                                      which SGI interrupts will be generated. */
14828         uint64_t irm                   : 1;  /**< [ 40: 40](R/W) Interrupt Routing Mode. Determines how the generated
14829                                                                      interrupts should be distributed to processors. Possible
14830                                                                      values are:
14831                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
14832                                                                      list}. In this routing, a, b, and c are the values of fields
14833                                                                      Aff3, Aff2, and Aff1 respectively.
14834                                                                  1 = Interrupts routed to all processors in the system, excluding
14835                                                                      "self". */
14836         uint64_t reserved_41_47        : 7;
14837         uint64_t aff3                  : 8;  /**< [ 55: 48](R/W) The affinity 3 value of the affinity path of the cluster for
14838                                                                      which SGI interrupts will be generated. */
14839         uint64_t reserved_56_63        : 8;
14840 #endif /* Word 0 - End */
14841     } s;
14842     /* struct bdk_ap_icc_sgi0r_el1_s cn8; */
14843     struct bdk_ap_icc_sgi0r_el1_cn9
14844     {
14845 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14846         uint64_t reserved_56_63        : 8;
14847         uint64_t aff3                  : 8;  /**< [ 55: 48](WO) The affinity 3 value of the affinity path of the cluster for
14848                                                                      which SGI interrupts will be generated. */
14849         uint64_t reserved_41_47        : 7;
14850         uint64_t irm                   : 1;  /**< [ 40: 40](WO) Interrupt Routing Mode. Determines how the generated
14851                                                                      interrupts should be distributed to processors. Possible
14852                                                                      values are:
14853                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
14854                                                                      list}. In this routing, a, b, and c are the values of fields
14855                                                                      Aff3, Aff2, and Aff1 respectively.
14856                                                                  1 = Interrupts routed to all processors in the system, excluding
14857                                                                      self. */
14858         uint64_t aff2                  : 8;  /**< [ 39: 32](WO) The affinity 2 value of the affinity path of the cluster for
14859                                                                      which SGI interrupts will be generated. */
14860         uint64_t reserved_28_31        : 4;
14861         uint64_t sgiid                 : 4;  /**< [ 27: 24](WO) SGI Interrupt ID. */
14862         uint64_t aff1                  : 8;  /**< [ 23: 16](WO) The affinity 1 value of the affinity path of the cluster for
14863                                                                      which SGI interrupts will be generated. */
14864         uint64_t targetlist            : 16; /**< [ 15:  0](WO) Target List. The set of processors for which SGI interrupts
14865                                                                      will be generated. Each bit corresponds to the processor
14866                                                                      within a cluster with an Affinity 0 value equal to the bit
14867                                                                      number.
14868 
14869                                                                  If a bit is 1 and the bit does not correspond to a valid
14870                                                                      target processor, the bit must be ignored by the Distributor.
14871                                                                      In such cases, a Distributor may optionally generate an SError
14872                                                                      interrupt.
14873 
14874                                                                  This restricts distribution of SGIs to the first 16 processors
14875                                                                      of an affinity 1 cluster. */
14876 #else /* Word 0 - Little Endian */
14877         uint64_t targetlist            : 16; /**< [ 15:  0](WO) Target List. The set of processors for which SGI interrupts
14878                                                                      will be generated. Each bit corresponds to the processor
14879                                                                      within a cluster with an Affinity 0 value equal to the bit
14880                                                                      number.
14881 
14882                                                                  If a bit is 1 and the bit does not correspond to a valid
14883                                                                      target processor, the bit must be ignored by the Distributor.
14884                                                                      In such cases, a Distributor may optionally generate an SError
14885                                                                      interrupt.
14886 
14887                                                                  This restricts distribution of SGIs to the first 16 processors
14888                                                                      of an affinity 1 cluster. */
14889         uint64_t aff1                  : 8;  /**< [ 23: 16](WO) The affinity 1 value of the affinity path of the cluster for
14890                                                                      which SGI interrupts will be generated. */
14891         uint64_t sgiid                 : 4;  /**< [ 27: 24](WO) SGI Interrupt ID. */
14892         uint64_t reserved_28_31        : 4;
14893         uint64_t aff2                  : 8;  /**< [ 39: 32](WO) The affinity 2 value of the affinity path of the cluster for
14894                                                                      which SGI interrupts will be generated. */
14895         uint64_t irm                   : 1;  /**< [ 40: 40](WO) Interrupt Routing Mode. Determines how the generated
14896                                                                      interrupts should be distributed to processors. Possible
14897                                                                      values are:
14898                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
14899                                                                      list}. In this routing, a, b, and c are the values of fields
14900                                                                      Aff3, Aff2, and Aff1 respectively.
14901                                                                  1 = Interrupts routed to all processors in the system, excluding
14902                                                                      self. */
14903         uint64_t reserved_41_47        : 7;
14904         uint64_t aff3                  : 8;  /**< [ 55: 48](WO) The affinity 3 value of the affinity path of the cluster for
14905                                                                      which SGI interrupts will be generated. */
14906         uint64_t reserved_56_63        : 8;
14907 #endif /* Word 0 - End */
14908     } cn9;
14909 };
14910 typedef union bdk_ap_icc_sgi0r_el1 bdk_ap_icc_sgi0r_el1_t;
14911 
14912 #define BDK_AP_ICC_SGI0R_EL1 BDK_AP_ICC_SGI0R_EL1_FUNC()
14913 static inline uint64_t BDK_AP_ICC_SGI0R_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_SGI0R_EL1_FUNC(void)14914 static inline uint64_t BDK_AP_ICC_SGI0R_EL1_FUNC(void)
14915 {
14916     return 0x3000c0b0700ll;
14917 }
14918 
14919 #define typedef_BDK_AP_ICC_SGI0R_EL1 bdk_ap_icc_sgi0r_el1_t
14920 #define bustype_BDK_AP_ICC_SGI0R_EL1 BDK_CSR_TYPE_SYSREG
14921 #define basename_BDK_AP_ICC_SGI0R_EL1 "AP_ICC_SGI0R_EL1"
14922 #define busnum_BDK_AP_ICC_SGI0R_EL1 0
14923 #define arguments_BDK_AP_ICC_SGI0R_EL1 -1,-1,-1,-1
14924 
14925 /**
14926  * Register (SYSREG) ap_icc_sgi1r_el1
14927  *
14928  * AP Interrupt Controller Software Generated Interrupt group 1 Register
14929  * Provides software the ability to generate group 1 SGIs for the
14930  *     current security state.
14931  */
14932 union bdk_ap_icc_sgi1r_el1
14933 {
14934     uint64_t u;
14935     struct bdk_ap_icc_sgi1r_el1_s
14936     {
14937 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
14938         uint64_t reserved_56_63        : 8;
14939         uint64_t aff3                  : 8;  /**< [ 55: 48](R/W) The affinity 3 value of the affinity path of the cluster for
14940                                                                      which SGI interrupts will be generated. */
14941         uint64_t reserved_41_47        : 7;
14942         uint64_t irm                   : 1;  /**< [ 40: 40](R/W) Interrupt Routing Mode. Determines how the generated
14943                                                                      interrupts should be distributed to processors. Possible
14944                                                                      values are:
14945                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
14946                                                                      list}. In this routing, a, b, and c are the values of fields
14947                                                                      Aff3, Aff2, and Aff1 respectively.
14948                                                                  1 = Interrupts routed to all processors in the system, excluding
14949                                                                      "self". */
14950         uint64_t aff2                  : 8;  /**< [ 39: 32](R/W) The affinity 2 value of the affinity path of the cluster for
14951                                                                      which SGI interrupts will be generated. */
14952         uint64_t reserved_28_31        : 4;
14953         uint64_t sgiid                 : 4;  /**< [ 27: 24](R/W) SGI Interrupt ID. */
14954         uint64_t aff1                  : 8;  /**< [ 23: 16](R/W) The affinity 1 value of the affinity path of the cluster for
14955                                                                      which SGI interrupts will be generated. */
14956         uint64_t targetlist            : 16; /**< [ 15:  0](R/W) Target List. The set of processors for which SGI interrupts
14957                                                                      will be generated. Each bit corresponds to the processor
14958                                                                      within a cluster with an Affinity 0 value equal to the bit
14959                                                                      number.
14960                                                                  If a bit is 1 and the bit does not correspond to a valid
14961                                                                      target processor, the bit must be ignored by the Distributor.
14962                                                                      In such cases, a Distributor may optionally generate an SError
14963                                                                      interrupt.
14964                                                                  This restricts distribution of SGIs to the first 16 processors
14965                                                                      of an affinity 1 cluster. */
14966 #else /* Word 0 - Little Endian */
14967         uint64_t targetlist            : 16; /**< [ 15:  0](R/W) Target List. The set of processors for which SGI interrupts
14968                                                                      will be generated. Each bit corresponds to the processor
14969                                                                      within a cluster with an Affinity 0 value equal to the bit
14970                                                                      number.
14971                                                                  If a bit is 1 and the bit does not correspond to a valid
14972                                                                      target processor, the bit must be ignored by the Distributor.
14973                                                                      In such cases, a Distributor may optionally generate an SError
14974                                                                      interrupt.
14975                                                                  This restricts distribution of SGIs to the first 16 processors
14976                                                                      of an affinity 1 cluster. */
14977         uint64_t aff1                  : 8;  /**< [ 23: 16](R/W) The affinity 1 value of the affinity path of the cluster for
14978                                                                      which SGI interrupts will be generated. */
14979         uint64_t sgiid                 : 4;  /**< [ 27: 24](R/W) SGI Interrupt ID. */
14980         uint64_t reserved_28_31        : 4;
14981         uint64_t aff2                  : 8;  /**< [ 39: 32](R/W) The affinity 2 value of the affinity path of the cluster for
14982                                                                      which SGI interrupts will be generated. */
14983         uint64_t irm                   : 1;  /**< [ 40: 40](R/W) Interrupt Routing Mode. Determines how the generated
14984                                                                      interrupts should be distributed to processors. Possible
14985                                                                      values are:
14986                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
14987                                                                      list}. In this routing, a, b, and c are the values of fields
14988                                                                      Aff3, Aff2, and Aff1 respectively.
14989                                                                  1 = Interrupts routed to all processors in the system, excluding
14990                                                                      "self". */
14991         uint64_t reserved_41_47        : 7;
14992         uint64_t aff3                  : 8;  /**< [ 55: 48](R/W) The affinity 3 value of the affinity path of the cluster for
14993                                                                      which SGI interrupts will be generated. */
14994         uint64_t reserved_56_63        : 8;
14995 #endif /* Word 0 - End */
14996     } s;
14997     /* struct bdk_ap_icc_sgi1r_el1_s cn8; */
14998     struct bdk_ap_icc_sgi1r_el1_cn9
14999     {
15000 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15001         uint64_t reserved_56_63        : 8;
15002         uint64_t aff3                  : 8;  /**< [ 55: 48](WO) The affinity 3 value of the affinity path of the cluster for
15003                                                                      which SGI interrupts will be generated. */
15004         uint64_t reserved_41_47        : 7;
15005         uint64_t irm                   : 1;  /**< [ 40: 40](WO) Interrupt Routing Mode. Determines how the generated
15006                                                                      interrupts should be distributed to processors.
15007                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
15008                                                                      list}. In this routing, a, b, and c are the values of fields
15009                                                                      Aff3, Aff2, and Aff1 respectively.
15010                                                                  1 = Interrupts routed to all processors in the system, excluding
15011                                                                      self. */
15012         uint64_t aff2                  : 8;  /**< [ 39: 32](WO) The affinity 2 value of the affinity path of the cluster for
15013                                                                      which SGI interrupts will be generated. */
15014         uint64_t reserved_28_31        : 4;
15015         uint64_t sgiid                 : 4;  /**< [ 27: 24](WO) SGI Interrupt ID. */
15016         uint64_t aff1                  : 8;  /**< [ 23: 16](WO) The affinity 1 value of the affinity path of the cluster for
15017                                                                      which SGI interrupts will be generated. */
15018         uint64_t targetlist            : 16; /**< [ 15:  0](WO) Target List. The set of processors for which SGI interrupts
15019                                                                      will be generated. Each bit corresponds to the processor
15020                                                                      within a cluster with an Affinity 0 value equal to the bit
15021                                                                      number.
15022                                                                  If a bit is 1 and the bit does not correspond to a valid
15023                                                                      target processor, the bit must be ignored by the Distributor.
15024                                                                      In such cases, a Distributor may optionally generate an SError
15025                                                                      interrupt.
15026                                                                  This restricts distribution of SGIs to the first 16 processors
15027                                                                      of an affinity 1 cluster. */
15028 #else /* Word 0 - Little Endian */
15029         uint64_t targetlist            : 16; /**< [ 15:  0](WO) Target List. The set of processors for which SGI interrupts
15030                                                                      will be generated. Each bit corresponds to the processor
15031                                                                      within a cluster with an Affinity 0 value equal to the bit
15032                                                                      number.
15033                                                                  If a bit is 1 and the bit does not correspond to a valid
15034                                                                      target processor, the bit must be ignored by the Distributor.
15035                                                                      In such cases, a Distributor may optionally generate an SError
15036                                                                      interrupt.
15037                                                                  This restricts distribution of SGIs to the first 16 processors
15038                                                                      of an affinity 1 cluster. */
15039         uint64_t aff1                  : 8;  /**< [ 23: 16](WO) The affinity 1 value of the affinity path of the cluster for
15040                                                                      which SGI interrupts will be generated. */
15041         uint64_t sgiid                 : 4;  /**< [ 27: 24](WO) SGI Interrupt ID. */
15042         uint64_t reserved_28_31        : 4;
15043         uint64_t aff2                  : 8;  /**< [ 39: 32](WO) The affinity 2 value of the affinity path of the cluster for
15044                                                                      which SGI interrupts will be generated. */
15045         uint64_t irm                   : 1;  /**< [ 40: 40](WO) Interrupt Routing Mode. Determines how the generated
15046                                                                      interrupts should be distributed to processors.
15047                                                                  0 = Interrupts routed to the processors specified by a.b.c.{target
15048                                                                      list}. In this routing, a, b, and c are the values of fields
15049                                                                      Aff3, Aff2, and Aff1 respectively.
15050                                                                  1 = Interrupts routed to all processors in the system, excluding
15051                                                                      self. */
15052         uint64_t reserved_41_47        : 7;
15053         uint64_t aff3                  : 8;  /**< [ 55: 48](WO) The affinity 3 value of the affinity path of the cluster for
15054                                                                      which SGI interrupts will be generated. */
15055         uint64_t reserved_56_63        : 8;
15056 #endif /* Word 0 - End */
15057     } cn9;
15058 };
15059 typedef union bdk_ap_icc_sgi1r_el1 bdk_ap_icc_sgi1r_el1_t;
15060 
15061 #define BDK_AP_ICC_SGI1R_EL1 BDK_AP_ICC_SGI1R_EL1_FUNC()
15062 static inline uint64_t BDK_AP_ICC_SGI1R_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_SGI1R_EL1_FUNC(void)15063 static inline uint64_t BDK_AP_ICC_SGI1R_EL1_FUNC(void)
15064 {
15065     return 0x3000c0b0500ll;
15066 }
15067 
15068 #define typedef_BDK_AP_ICC_SGI1R_EL1 bdk_ap_icc_sgi1r_el1_t
15069 #define bustype_BDK_AP_ICC_SGI1R_EL1 BDK_CSR_TYPE_SYSREG
15070 #define basename_BDK_AP_ICC_SGI1R_EL1 "AP_ICC_SGI1R_EL1"
15071 #define busnum_BDK_AP_ICC_SGI1R_EL1 0
15072 #define arguments_BDK_AP_ICC_SGI1R_EL1 -1,-1,-1,-1
15073 
15074 /**
15075  * Register (SYSREG) ap_icc_sre_el1
15076  *
15077  * AP Interrupt Controller System Register Enable EL1 Register
15078  * Controls whether the system register interface or the memory
15079  *     mapped interface to the GIC CPU interface is used for EL0 and
15080  *     EL1.
15081  */
15082 union bdk_ap_icc_sre_el1
15083 {
15084     uint32_t u;
15085     struct bdk_ap_icc_sre_el1_s
15086     {
15087 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15088         uint32_t reserved_3_31         : 29;
15089         uint32_t dib                   : 1;  /**< [  2:  2](RO) Disable IRQ bypass.
15090                                                                  If EL3 is present, this field is a read-only alias of
15091                                                                      AP_ICC_SRE_EL3[DIB].
15092                                                                  If EL3 is not present and EL2 is present, this field is a
15093                                                                      read-only alias of AP_ICC_SRE_EL2[DIB]. */
15094         uint32_t dfb                   : 1;  /**< [  1:  1](RO) Disable FIQ bypass.
15095                                                                  If EL3 is present, this field is a read-only alias of
15096                                                                      AP_ICC_SRE_EL3[DFB].
15097                                                                  If EL3 is not present and EL2 is present, this field is a
15098                                                                      read-only alias of AP_ICC_SRE_EL2[DFB]. */
15099         uint32_t sre                   : 1;  /**< [  0:  0](RO) System Register Enable.
15100                                                                  Virtual accesses modify AP_ICH_VMCR_EL2[VSRE].
15101                                                                  0 = The memory mapped interface must be used. Access at EL1 to any
15102                                                                      ICC_* system register other than AP_ICC_SRE_EL1 results in an
15103                                                                      Undefined exception.
15104                                                                  1 = The system register interface for the current Security state
15105                                                                      is enabled. */
15106 #else /* Word 0 - Little Endian */
15107         uint32_t sre                   : 1;  /**< [  0:  0](RO) System Register Enable.
15108                                                                  Virtual accesses modify AP_ICH_VMCR_EL2[VSRE].
15109                                                                  0 = The memory mapped interface must be used. Access at EL1 to any
15110                                                                      ICC_* system register other than AP_ICC_SRE_EL1 results in an
15111                                                                      Undefined exception.
15112                                                                  1 = The system register interface for the current Security state
15113                                                                      is enabled. */
15114         uint32_t dfb                   : 1;  /**< [  1:  1](RO) Disable FIQ bypass.
15115                                                                  If EL3 is present, this field is a read-only alias of
15116                                                                      AP_ICC_SRE_EL3[DFB].
15117                                                                  If EL3 is not present and EL2 is present, this field is a
15118                                                                      read-only alias of AP_ICC_SRE_EL2[DFB]. */
15119         uint32_t dib                   : 1;  /**< [  2:  2](RO) Disable IRQ bypass.
15120                                                                  If EL3 is present, this field is a read-only alias of
15121                                                                      AP_ICC_SRE_EL3[DIB].
15122                                                                  If EL3 is not present and EL2 is present, this field is a
15123                                                                      read-only alias of AP_ICC_SRE_EL2[DIB]. */
15124         uint32_t reserved_3_31         : 29;
15125 #endif /* Word 0 - End */
15126     } s;
15127     /* struct bdk_ap_icc_sre_el1_s cn; */
15128 };
15129 typedef union bdk_ap_icc_sre_el1 bdk_ap_icc_sre_el1_t;
15130 
15131 #define BDK_AP_ICC_SRE_EL1 BDK_AP_ICC_SRE_EL1_FUNC()
15132 static inline uint64_t BDK_AP_ICC_SRE_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_SRE_EL1_FUNC(void)15133 static inline uint64_t BDK_AP_ICC_SRE_EL1_FUNC(void)
15134 {
15135     return 0x3000c0c0500ll;
15136 }
15137 
15138 #define typedef_BDK_AP_ICC_SRE_EL1 bdk_ap_icc_sre_el1_t
15139 #define bustype_BDK_AP_ICC_SRE_EL1 BDK_CSR_TYPE_SYSREG
15140 #define basename_BDK_AP_ICC_SRE_EL1 "AP_ICC_SRE_EL1"
15141 #define busnum_BDK_AP_ICC_SRE_EL1 0
15142 #define arguments_BDK_AP_ICC_SRE_EL1 -1,-1,-1,-1
15143 
15144 /**
15145  * Register (SYSREG) ap_icc_sre_el2
15146  *
15147  * AP Interrupt Controller System Register Enable EL2 Register
15148  * Controls whether the system register interface or the memory
15149  *     mapped interface to the GIC CPU interface is used for EL2.
15150  */
15151 union bdk_ap_icc_sre_el2
15152 {
15153     uint32_t u;
15154     struct bdk_ap_icc_sre_el2_s
15155     {
15156 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15157         uint32_t reserved_4_31         : 28;
15158         uint32_t enable                : 1;  /**< [  3:  3](R/W) Enable. Enables lower Exception level access to AP_ICC_SRE_EL1.
15159                                                                  0 = Nonsecure EL1 accesses to AP_ICC_SRE_EL1 trap to EL2.
15160                                                                  1 = Nonsecure EL1 accesses to AP_ICC_SRE_EL1 are permitted if EL3 is
15161                                                                      not present or AP_ICC_SRE_EL3[ENABLE] is 1, otherwise nonsecure
15162                                                                      EL1 accesses to AP_ICC_SRE_EL1 trap to EL3. */
15163         uint32_t dib                   : 1;  /**< [  2:  2](RO) Disable IRQ bypass.
15164                                                                  If EL3 is present and GICD_CTLR[DS] is 0, this field is a read-
15165                                                                      only alias of AP_ICC_SRE_EL3[DIB]. */
15166         uint32_t dfb                   : 1;  /**< [  1:  1](RO) Disable FIQ bypass.
15167                                                                  If EL3 is present and GICD_CTLR[DS] is 0, this field is a read-
15168                                                                      only alias of AP_ICC_SRE_EL3[DFB]. */
15169         uint32_t sre                   : 1;  /**< [  0:  0](RO) System Register Enable.
15170                                                                  0 = The memory mapped interface must be used. Access at EL2 to any
15171                                                                      ICH_* system register, or any EL1 or EL2 ICC_* register other
15172                                                                      than AP_ICC_SRE_EL1 or AP_ICC_SRE_EL2, results in an Undefined
15173                                                                      exception.
15174                                                                  1 = The system register interface to the ICH_* registers and the
15175                                                                      EL1 and EL2 ICC_* registers is enabled for EL2. */
15176 #else /* Word 0 - Little Endian */
15177         uint32_t sre                   : 1;  /**< [  0:  0](RO) System Register Enable.
15178                                                                  0 = The memory mapped interface must be used. Access at EL2 to any
15179                                                                      ICH_* system register, or any EL1 or EL2 ICC_* register other
15180                                                                      than AP_ICC_SRE_EL1 or AP_ICC_SRE_EL2, results in an Undefined
15181                                                                      exception.
15182                                                                  1 = The system register interface to the ICH_* registers and the
15183                                                                      EL1 and EL2 ICC_* registers is enabled for EL2. */
15184         uint32_t dfb                   : 1;  /**< [  1:  1](RO) Disable FIQ bypass.
15185                                                                  If EL3 is present and GICD_CTLR[DS] is 0, this field is a read-
15186                                                                      only alias of AP_ICC_SRE_EL3[DFB]. */
15187         uint32_t dib                   : 1;  /**< [  2:  2](RO) Disable IRQ bypass.
15188                                                                  If EL3 is present and GICD_CTLR[DS] is 0, this field is a read-
15189                                                                      only alias of AP_ICC_SRE_EL3[DIB]. */
15190         uint32_t enable                : 1;  /**< [  3:  3](R/W) Enable. Enables lower Exception level access to AP_ICC_SRE_EL1.
15191                                                                  0 = Nonsecure EL1 accesses to AP_ICC_SRE_EL1 trap to EL2.
15192                                                                  1 = Nonsecure EL1 accesses to AP_ICC_SRE_EL1 are permitted if EL3 is
15193                                                                      not present or AP_ICC_SRE_EL3[ENABLE] is 1, otherwise nonsecure
15194                                                                      EL1 accesses to AP_ICC_SRE_EL1 trap to EL3. */
15195         uint32_t reserved_4_31         : 28;
15196 #endif /* Word 0 - End */
15197     } s;
15198     /* struct bdk_ap_icc_sre_el2_s cn; */
15199 };
15200 typedef union bdk_ap_icc_sre_el2 bdk_ap_icc_sre_el2_t;
15201 
15202 #define BDK_AP_ICC_SRE_EL2 BDK_AP_ICC_SRE_EL2_FUNC()
15203 static inline uint64_t BDK_AP_ICC_SRE_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_SRE_EL2_FUNC(void)15204 static inline uint64_t BDK_AP_ICC_SRE_EL2_FUNC(void)
15205 {
15206     return 0x3040c090500ll;
15207 }
15208 
15209 #define typedef_BDK_AP_ICC_SRE_EL2 bdk_ap_icc_sre_el2_t
15210 #define bustype_BDK_AP_ICC_SRE_EL2 BDK_CSR_TYPE_SYSREG
15211 #define basename_BDK_AP_ICC_SRE_EL2 "AP_ICC_SRE_EL2"
15212 #define busnum_BDK_AP_ICC_SRE_EL2 0
15213 #define arguments_BDK_AP_ICC_SRE_EL2 -1,-1,-1,-1
15214 
15215 /**
15216  * Register (SYSREG) ap_icc_sre_el3
15217  *
15218  * AP Interrupt Controller System Register Enable EL3 Register
15219  * Controls whether the system register interface or the memory
15220  *     mapped interface to the GIC CPU interface is used for EL2.
15221  */
15222 union bdk_ap_icc_sre_el3
15223 {
15224     uint32_t u;
15225     struct bdk_ap_icc_sre_el3_s
15226     {
15227 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15228         uint32_t reserved_4_31         : 28;
15229         uint32_t enable                : 1;  /**< [  3:  3](R/W) Enable. Enables lower Exception level access to AP_ICC_SRE_EL1
15230                                                                      and AP_ICC_SRE_EL2.
15231                                                                  0 = EL1 and EL2 accesses to AP_ICC_SRE_EL1 or AP_ICC_SRE_EL2 trap to
15232                                                                      EL3.
15233                                                                  1 = EL2 accesses to AP_ICC_SRE_EL2 are permitted. If the Enable bit
15234                                                                      of AP_ICC_SRE_EL2 is 1, then EL1 accesses to AP_ICC_SRE_EL1 are also
15235                                                                      permitted. */
15236         uint32_t dib                   : 1;  /**< [  2:  2](RO) Disable IRQ bypass. */
15237         uint32_t dfb                   : 1;  /**< [  1:  1](RO) Disable FIQ bypass. */
15238         uint32_t sre                   : 1;  /**< [  0:  0](RO) System Register Enable.
15239                                                                  0 = The memory mapped interface must be used. Access at EL3 to any
15240                                                                      ICH_* system register, or any EL1, EL2, or EL3 ICC_* register
15241                                                                      other than AP_ICC_SRE_EL1, AP_ICC_SRE_EL2, or AP_ICC_SRE_EL3, results
15242                                                                      in an Undefined exception.
15243                                                                  1 = The system register interface to the ICH_* registers and the
15244                                                                      EL1, EL2, and EL3 ICC_* registers is enabled for EL3. */
15245 #else /* Word 0 - Little Endian */
15246         uint32_t sre                   : 1;  /**< [  0:  0](RO) System Register Enable.
15247                                                                  0 = The memory mapped interface must be used. Access at EL3 to any
15248                                                                      ICH_* system register, or any EL1, EL2, or EL3 ICC_* register
15249                                                                      other than AP_ICC_SRE_EL1, AP_ICC_SRE_EL2, or AP_ICC_SRE_EL3, results
15250                                                                      in an Undefined exception.
15251                                                                  1 = The system register interface to the ICH_* registers and the
15252                                                                      EL1, EL2, and EL3 ICC_* registers is enabled for EL3. */
15253         uint32_t dfb                   : 1;  /**< [  1:  1](RO) Disable FIQ bypass. */
15254         uint32_t dib                   : 1;  /**< [  2:  2](RO) Disable IRQ bypass. */
15255         uint32_t enable                : 1;  /**< [  3:  3](R/W) Enable. Enables lower Exception level access to AP_ICC_SRE_EL1
15256                                                                      and AP_ICC_SRE_EL2.
15257                                                                  0 = EL1 and EL2 accesses to AP_ICC_SRE_EL1 or AP_ICC_SRE_EL2 trap to
15258                                                                      EL3.
15259                                                                  1 = EL2 accesses to AP_ICC_SRE_EL2 are permitted. If the Enable bit
15260                                                                      of AP_ICC_SRE_EL2 is 1, then EL1 accesses to AP_ICC_SRE_EL1 are also
15261                                                                      permitted. */
15262         uint32_t reserved_4_31         : 28;
15263 #endif /* Word 0 - End */
15264     } s;
15265     /* struct bdk_ap_icc_sre_el3_s cn; */
15266 };
15267 typedef union bdk_ap_icc_sre_el3 bdk_ap_icc_sre_el3_t;
15268 
15269 #define BDK_AP_ICC_SRE_EL3 BDK_AP_ICC_SRE_EL3_FUNC()
15270 static inline uint64_t BDK_AP_ICC_SRE_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICC_SRE_EL3_FUNC(void)15271 static inline uint64_t BDK_AP_ICC_SRE_EL3_FUNC(void)
15272 {
15273     return 0x3060c0c0500ll;
15274 }
15275 
15276 #define typedef_BDK_AP_ICC_SRE_EL3 bdk_ap_icc_sre_el3_t
15277 #define bustype_BDK_AP_ICC_SRE_EL3 BDK_CSR_TYPE_SYSREG
15278 #define basename_BDK_AP_ICC_SRE_EL3 "AP_ICC_SRE_EL3"
15279 #define busnum_BDK_AP_ICC_SRE_EL3 0
15280 #define arguments_BDK_AP_ICC_SRE_EL3 -1,-1,-1,-1
15281 
15282 /**
15283  * Register (SYSREG) ap_ich_ap0r0_el2
15284  *
15285  * AP Interrupt Controller Hyp Active Priorities (0,0) Register
15286  * Provides information about the active priorities for the
15287  *     current EL2 interrupt regime.
15288  */
15289 union bdk_ap_ich_ap0r0_el2
15290 {
15291     uint32_t u;
15292     struct bdk_ap_ich_ap0r0_el2_s
15293     {
15294 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15295         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
15296                                                                      following relationship:
15297 
15298                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
15299                                                                      minus 1, where U is the number of unimplemented bits of
15300                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRIBITS]).
15301 
15302                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRIBITS] == 0x4:
15303 
15304                                                                   There are 5 bits of implemented priority.
15305 
15306                                                                   This means there are 3 bits of unimplemented priority, which
15307                                                                      are always at the least significant end (bits [2:0] are RES0).
15308 
15309                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
15310                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
15311 
15312                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
15313                                                                      provide information about those priorities.
15314 
15315                                                                  Accesses to these registers from an interrupt regime give a
15316                                                                      view of the active priorities that is appropriate for that
15317                                                                      interrupt regime, to allow save and restore of the appropriate
15318                                                                      state.
15319 
15320                                                                  Interrupt regime and the number of Security states supported
15321                                                                      by the Distributor affect the view as follows. Unless
15322                                                                      otherwise stated, when a bit is successfully set to one, this
15323                                                                      clears any other active priorities corresponding to that bit.
15324 
15325                                                                  Exception level     AP0Rn access
15326 
15327                                                                  (Secure) EL3        Permitted. Accesses Group 0 Secure active priorities.
15328 
15329                                                                  Secure EL1  Permitted. Accesses Group 0 Secure active priorities.
15330 
15331                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP0Rn_EL2
15332 
15333                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
15334                                                                  0) Permitted. Accesses Group 0 Secure active priorities.
15335 
15336                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
15337                                                                  1)  Permitted. Accesses Group 0 active priorities.
15338 
15339                                                                  A Virtual interrupt in this case means that the interrupt
15340                                                                      group associated with the register has been virtualized. */
15341 #else /* Word 0 - Little Endian */
15342         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
15343                                                                      following relationship:
15344 
15345                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
15346                                                                      minus 1, where U is the number of unimplemented bits of
15347                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRIBITS]).
15348 
15349                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRIBITS] == 0x4:
15350 
15351                                                                   There are 5 bits of implemented priority.
15352 
15353                                                                   This means there are 3 bits of unimplemented priority, which
15354                                                                      are always at the least significant end (bits [2:0] are RES0).
15355 
15356                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
15357                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
15358 
15359                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
15360                                                                      provide information about those priorities.
15361 
15362                                                                  Accesses to these registers from an interrupt regime give a
15363                                                                      view of the active priorities that is appropriate for that
15364                                                                      interrupt regime, to allow save and restore of the appropriate
15365                                                                      state.
15366 
15367                                                                  Interrupt regime and the number of Security states supported
15368                                                                      by the Distributor affect the view as follows. Unless
15369                                                                      otherwise stated, when a bit is successfully set to one, this
15370                                                                      clears any other active priorities corresponding to that bit.
15371 
15372                                                                  Exception level     AP0Rn access
15373 
15374                                                                  (Secure) EL3        Permitted. Accesses Group 0 Secure active priorities.
15375 
15376                                                                  Secure EL1  Permitted. Accesses Group 0 Secure active priorities.
15377 
15378                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP0Rn_EL2
15379 
15380                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
15381                                                                  0) Permitted. Accesses Group 0 Secure active priorities.
15382 
15383                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
15384                                                                  1)  Permitted. Accesses Group 0 active priorities.
15385 
15386                                                                  A Virtual interrupt in this case means that the interrupt
15387                                                                      group associated with the register has been virtualized. */
15388 #endif /* Word 0 - End */
15389     } s;
15390     /* struct bdk_ap_ich_ap0r0_el2_s cn; */
15391 };
15392 typedef union bdk_ap_ich_ap0r0_el2 bdk_ap_ich_ap0r0_el2_t;
15393 
15394 #define BDK_AP_ICH_AP0R0_EL2 BDK_AP_ICH_AP0R0_EL2_FUNC()
15395 static inline uint64_t BDK_AP_ICH_AP0R0_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_AP0R0_EL2_FUNC(void)15396 static inline uint64_t BDK_AP_ICH_AP0R0_EL2_FUNC(void)
15397 {
15398     return 0x3040c080000ll;
15399 }
15400 
15401 #define typedef_BDK_AP_ICH_AP0R0_EL2 bdk_ap_ich_ap0r0_el2_t
15402 #define bustype_BDK_AP_ICH_AP0R0_EL2 BDK_CSR_TYPE_SYSREG
15403 #define basename_BDK_AP_ICH_AP0R0_EL2 "AP_ICH_AP0R0_EL2"
15404 #define busnum_BDK_AP_ICH_AP0R0_EL2 0
15405 #define arguments_BDK_AP_ICH_AP0R0_EL2 -1,-1,-1,-1
15406 
15407 /**
15408  * Register (SYSREG) ap_ich_ap0r1_el2
15409  *
15410  * AP Interrupt Controller Hyp Active Priorities (0,1) Register
15411  * Provides information about the active priorities for the
15412  *     current EL2 interrupt regime.
15413  */
15414 union bdk_ap_ich_ap0r1_el2
15415 {
15416     uint32_t u;
15417     struct bdk_ap_ich_ap0r1_el2_s
15418     {
15419 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15420         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP0R0_EL2[PRIORITYBITS]. */
15421 #else /* Word 0 - Little Endian */
15422         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP0R0_EL2[PRIORITYBITS]. */
15423 #endif /* Word 0 - End */
15424     } s;
15425     /* struct bdk_ap_ich_ap0r1_el2_s cn; */
15426 };
15427 typedef union bdk_ap_ich_ap0r1_el2 bdk_ap_ich_ap0r1_el2_t;
15428 
15429 #define BDK_AP_ICH_AP0R1_EL2 BDK_AP_ICH_AP0R1_EL2_FUNC()
15430 static inline uint64_t BDK_AP_ICH_AP0R1_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_AP0R1_EL2_FUNC(void)15431 static inline uint64_t BDK_AP_ICH_AP0R1_EL2_FUNC(void)
15432 {
15433     return 0x3040c080100ll;
15434 }
15435 
15436 #define typedef_BDK_AP_ICH_AP0R1_EL2 bdk_ap_ich_ap0r1_el2_t
15437 #define bustype_BDK_AP_ICH_AP0R1_EL2 BDK_CSR_TYPE_SYSREG
15438 #define basename_BDK_AP_ICH_AP0R1_EL2 "AP_ICH_AP0R1_EL2"
15439 #define busnum_BDK_AP_ICH_AP0R1_EL2 0
15440 #define arguments_BDK_AP_ICH_AP0R1_EL2 -1,-1,-1,-1
15441 
15442 /**
15443  * Register (SYSREG) ap_ich_ap0r2_el2
15444  *
15445  * AP Interrupt Controller Hyp Active Priorities (0,2) Register
15446  * Provides information about the active priorities for the
15447  *     current EL2 interrupt regime.
15448  */
15449 union bdk_ap_ich_ap0r2_el2
15450 {
15451     uint32_t u;
15452     struct bdk_ap_ich_ap0r2_el2_s
15453     {
15454 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15455         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP0R0_EL2[PRIORITYBITS]. */
15456 #else /* Word 0 - Little Endian */
15457         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP0R0_EL2[PRIORITYBITS]. */
15458 #endif /* Word 0 - End */
15459     } s;
15460     /* struct bdk_ap_ich_ap0r2_el2_s cn; */
15461 };
15462 typedef union bdk_ap_ich_ap0r2_el2 bdk_ap_ich_ap0r2_el2_t;
15463 
15464 #define BDK_AP_ICH_AP0R2_EL2 BDK_AP_ICH_AP0R2_EL2_FUNC()
15465 static inline uint64_t BDK_AP_ICH_AP0R2_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_AP0R2_EL2_FUNC(void)15466 static inline uint64_t BDK_AP_ICH_AP0R2_EL2_FUNC(void)
15467 {
15468     return 0x3040c080200ll;
15469 }
15470 
15471 #define typedef_BDK_AP_ICH_AP0R2_EL2 bdk_ap_ich_ap0r2_el2_t
15472 #define bustype_BDK_AP_ICH_AP0R2_EL2 BDK_CSR_TYPE_SYSREG
15473 #define basename_BDK_AP_ICH_AP0R2_EL2 "AP_ICH_AP0R2_EL2"
15474 #define busnum_BDK_AP_ICH_AP0R2_EL2 0
15475 #define arguments_BDK_AP_ICH_AP0R2_EL2 -1,-1,-1,-1
15476 
15477 /**
15478  * Register (SYSREG) ap_ich_ap0r3_el2
15479  *
15480  * AP Interrupt Controller Hyp Active Priorities (0,3) Register
15481  * Provides information about the active priorities for the
15482  *     current EL2 interrupt regime.
15483  */
15484 union bdk_ap_ich_ap0r3_el2
15485 {
15486     uint32_t u;
15487     struct bdk_ap_ich_ap0r3_el2_s
15488     {
15489 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15490         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP0R0_EL2[PRIORITYBITS]. */
15491 #else /* Word 0 - Little Endian */
15492         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP0R0_EL2[PRIORITYBITS]. */
15493 #endif /* Word 0 - End */
15494     } s;
15495     /* struct bdk_ap_ich_ap0r3_el2_s cn; */
15496 };
15497 typedef union bdk_ap_ich_ap0r3_el2 bdk_ap_ich_ap0r3_el2_t;
15498 
15499 #define BDK_AP_ICH_AP0R3_EL2 BDK_AP_ICH_AP0R3_EL2_FUNC()
15500 static inline uint64_t BDK_AP_ICH_AP0R3_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_AP0R3_EL2_FUNC(void)15501 static inline uint64_t BDK_AP_ICH_AP0R3_EL2_FUNC(void)
15502 {
15503     return 0x3040c080300ll;
15504 }
15505 
15506 #define typedef_BDK_AP_ICH_AP0R3_EL2 bdk_ap_ich_ap0r3_el2_t
15507 #define bustype_BDK_AP_ICH_AP0R3_EL2 BDK_CSR_TYPE_SYSREG
15508 #define basename_BDK_AP_ICH_AP0R3_EL2 "AP_ICH_AP0R3_EL2"
15509 #define busnum_BDK_AP_ICH_AP0R3_EL2 0
15510 #define arguments_BDK_AP_ICH_AP0R3_EL2 -1,-1,-1,-1
15511 
15512 /**
15513  * Register (SYSREG) ap_ich_ap1r0_el2
15514  *
15515  * AP Interrupt Controller Hyp Active Priorities (1,0) Register
15516  * Provides information about the active priorities for the
15517  *     current EL2 interrupt regime.
15518  */
15519 union bdk_ap_ich_ap1r0_el2
15520 {
15521     uint32_t u;
15522     struct bdk_ap_ich_ap1r0_el2_s
15523     {
15524 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15525         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
15526                                                                      following relationship:
15527 
15528                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
15529                                                                      minus 1, where U is the number of unimplemented bits of
15530                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRIBITS]).
15531 
15532                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRIBITS] = 0x4:
15533 
15534                                                                   There are 5 bits of implemented priority.
15535 
15536                                                                   This means there are 3 bits of unimplemented priority, which
15537                                                                      are always at the least significant end (bits [2:0] are RES0).
15538 
15539                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
15540                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
15541 
15542                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
15543                                                                      provide information about those priorities.
15544 
15545                                                                  Accesses to these registers from an interrupt regime give a
15546                                                                      view of the active priorities that is appropriate for that
15547                                                                      interrupt regime, to allow save and restore of the appropriate
15548                                                                      state.
15549 
15550                                                                  Interrupt regime and the number of Security states supported
15551                                                                      by the Distributor affect the view as follows. Unless
15552                                                                      otherwise stated, when a bit is successfully set to one, this
15553                                                                      clears any other active priorities corresponding to that bit.
15554 
15555                                                                  Current Exception level and Security state  AP1Rn access
15556 
15557                                                                  (Secure) EL3        Permitted. When AP_SCR_EL3[NS] is 0, accesses Group 1 Secure active
15558                                                                  priorities. When AP_SCR_EL3[NS] is 1, accesses Group 1 nonsecure active priorities
15559                                                                  (unshifted). When a bit is written, the bit is only updated if the corresponding Group 0
15560                                                                  and Group 1 Secure active priority is zero.
15561 
15562                                                                  Secure EL1  Permitted. Accesses Group 1 Secure active priorities (unshifted). When a bit
15563                                                                  is written, the bit is only updated if the corresponding Group 0 Secure active priority is
15564                                                                  zero.
15565 
15566                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP1Rn_EL2
15567 
15568                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
15569                                                                  0) Permitted. Accesses Group 1 nonsecure active priorities (shifted). When a bit is
15570                                                                  written, the bit is only updated if the corresponding Group 0 and Group 1 Secure active
15571                                                                  priority is zero.
15572 
15573                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
15574                                                                  1)  Permitted. Accesses Group 1 nonsecure active priorities (unshifted). When a bit is
15575                                                                  written, the bit is only updated if the Group 0 active priority is zero.
15576 
15577                                                                  A Virtual interrupt in this case means that the interrupt
15578                                                                      group associated with the register has been virtualized. */
15579 #else /* Word 0 - Little Endian */
15580         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) Provides information about priority M, according to the
15581                                                                      following relationship:
15582 
15583                                                                  Bit P\<n\> corresponds to priority (M divided by 22^(U))
15584                                                                      minus 1, where U is the number of unimplemented bits of
15585                                                                      priority and is equal to (7 -  AP_ICC_CTLR_EL1[PRIBITS]).
15586 
15587                                                                  For example, in a system with AP_ICC_CTLR_EL1[PRIBITS] = 0x4:
15588 
15589                                                                   There are 5 bits of implemented priority.
15590 
15591                                                                   This means there are 3 bits of unimplemented priority, which
15592                                                                      are always at the least significant end (bits [2:0] are RES0).
15593 
15594                                                                   Valid priorities are 8, 16, 24, 32, and so on. Dividing these
15595                                                                      by 22^(3) gives 1, 2, 3, 4, and so on.
15596 
15597                                                                   Subtracting 1 from each gives bits 0, 1, 2, 3, and so on that
15598                                                                      provide information about those priorities.
15599 
15600                                                                  Accesses to these registers from an interrupt regime give a
15601                                                                      view of the active priorities that is appropriate for that
15602                                                                      interrupt regime, to allow save and restore of the appropriate
15603                                                                      state.
15604 
15605                                                                  Interrupt regime and the number of Security states supported
15606                                                                      by the Distributor affect the view as follows. Unless
15607                                                                      otherwise stated, when a bit is successfully set to one, this
15608                                                                      clears any other active priorities corresponding to that bit.
15609 
15610                                                                  Current Exception level and Security state  AP1Rn access
15611 
15612                                                                  (Secure) EL3        Permitted. When AP_SCR_EL3[NS] is 0, accesses Group 1 Secure active
15613                                                                  priorities. When AP_SCR_EL3[NS] is 1, accesses Group 1 nonsecure active priorities
15614                                                                  (unshifted). When a bit is written, the bit is only updated if the corresponding Group 0
15615                                                                  and Group 1 Secure active priority is zero.
15616 
15617                                                                  Secure EL1  Permitted. Accesses Group 1 Secure active priorities (unshifted). When a bit
15618                                                                  is written, the bit is only updated if the corresponding Group 0 Secure active priority is
15619                                                                  zero.
15620 
15621                                                                  Nonsecure EL1 access for a Virtual interrupt       ICH_AP1Rn_EL2
15622 
15623                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports two Security states (GICD_CTLR[DS] is
15624                                                                  0) Permitted. Accesses Group 1 nonsecure active priorities (shifted). When a bit is
15625                                                                  written, the bit is only updated if the corresponding Group 0 and Group 1 Secure active
15626                                                                  priority is zero.
15627 
15628                                                                  Nonsecure EL1 or EL2 when GIC Distributor supports one Security state (GICD_CTLR[DS] is
15629                                                                  1)  Permitted. Accesses Group 1 nonsecure active priorities (unshifted). When a bit is
15630                                                                  written, the bit is only updated if the Group 0 active priority is zero.
15631 
15632                                                                  A Virtual interrupt in this case means that the interrupt
15633                                                                      group associated with the register has been virtualized. */
15634 #endif /* Word 0 - End */
15635     } s;
15636     /* struct bdk_ap_ich_ap1r0_el2_s cn; */
15637 };
15638 typedef union bdk_ap_ich_ap1r0_el2 bdk_ap_ich_ap1r0_el2_t;
15639 
15640 #define BDK_AP_ICH_AP1R0_EL2 BDK_AP_ICH_AP1R0_EL2_FUNC()
15641 static inline uint64_t BDK_AP_ICH_AP1R0_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_AP1R0_EL2_FUNC(void)15642 static inline uint64_t BDK_AP_ICH_AP1R0_EL2_FUNC(void)
15643 {
15644     return 0x3040c090000ll;
15645 }
15646 
15647 #define typedef_BDK_AP_ICH_AP1R0_EL2 bdk_ap_ich_ap1r0_el2_t
15648 #define bustype_BDK_AP_ICH_AP1R0_EL2 BDK_CSR_TYPE_SYSREG
15649 #define basename_BDK_AP_ICH_AP1R0_EL2 "AP_ICH_AP1R0_EL2"
15650 #define busnum_BDK_AP_ICH_AP1R0_EL2 0
15651 #define arguments_BDK_AP_ICH_AP1R0_EL2 -1,-1,-1,-1
15652 
15653 /**
15654  * Register (SYSREG) ap_ich_ap1r1_el2
15655  *
15656  * AP Interrupt Controller Hyp Active Priorities (1,1) Register
15657  * Provides information about the active priorities for the
15658  *     current EL2 interrupt regime.
15659  */
15660 union bdk_ap_ich_ap1r1_el2
15661 {
15662     uint32_t u;
15663     struct bdk_ap_ich_ap1r1_el2_s
15664     {
15665 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15666         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP1R0_EL2[PRIORITYBITS]. */
15667 #else /* Word 0 - Little Endian */
15668         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP1R0_EL2[PRIORITYBITS]. */
15669 #endif /* Word 0 - End */
15670     } s;
15671     /* struct bdk_ap_ich_ap1r1_el2_s cn; */
15672 };
15673 typedef union bdk_ap_ich_ap1r1_el2 bdk_ap_ich_ap1r1_el2_t;
15674 
15675 #define BDK_AP_ICH_AP1R1_EL2 BDK_AP_ICH_AP1R1_EL2_FUNC()
15676 static inline uint64_t BDK_AP_ICH_AP1R1_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_AP1R1_EL2_FUNC(void)15677 static inline uint64_t BDK_AP_ICH_AP1R1_EL2_FUNC(void)
15678 {
15679     return 0x3040c090100ll;
15680 }
15681 
15682 #define typedef_BDK_AP_ICH_AP1R1_EL2 bdk_ap_ich_ap1r1_el2_t
15683 #define bustype_BDK_AP_ICH_AP1R1_EL2 BDK_CSR_TYPE_SYSREG
15684 #define basename_BDK_AP_ICH_AP1R1_EL2 "AP_ICH_AP1R1_EL2"
15685 #define busnum_BDK_AP_ICH_AP1R1_EL2 0
15686 #define arguments_BDK_AP_ICH_AP1R1_EL2 -1,-1,-1,-1
15687 
15688 /**
15689  * Register (SYSREG) ap_ich_ap1r2_el2
15690  *
15691  * AP Interrupt Controller Hyp Active Priorities (1,2) Register
15692  * Provides information about the active priorities for the
15693  *     current EL2 interrupt regime.
15694  */
15695 union bdk_ap_ich_ap1r2_el2
15696 {
15697     uint32_t u;
15698     struct bdk_ap_ich_ap1r2_el2_s
15699     {
15700 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15701         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP1R0_EL2[PRIORITYBITS]. */
15702 #else /* Word 0 - Little Endian */
15703         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP1R0_EL2[PRIORITYBITS]. */
15704 #endif /* Word 0 - End */
15705     } s;
15706     /* struct bdk_ap_ich_ap1r2_el2_s cn; */
15707 };
15708 typedef union bdk_ap_ich_ap1r2_el2 bdk_ap_ich_ap1r2_el2_t;
15709 
15710 #define BDK_AP_ICH_AP1R2_EL2 BDK_AP_ICH_AP1R2_EL2_FUNC()
15711 static inline uint64_t BDK_AP_ICH_AP1R2_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_AP1R2_EL2_FUNC(void)15712 static inline uint64_t BDK_AP_ICH_AP1R2_EL2_FUNC(void)
15713 {
15714     return 0x3040c090200ll;
15715 }
15716 
15717 #define typedef_BDK_AP_ICH_AP1R2_EL2 bdk_ap_ich_ap1r2_el2_t
15718 #define bustype_BDK_AP_ICH_AP1R2_EL2 BDK_CSR_TYPE_SYSREG
15719 #define basename_BDK_AP_ICH_AP1R2_EL2 "AP_ICH_AP1R2_EL2"
15720 #define busnum_BDK_AP_ICH_AP1R2_EL2 0
15721 #define arguments_BDK_AP_ICH_AP1R2_EL2 -1,-1,-1,-1
15722 
15723 /**
15724  * Register (SYSREG) ap_ich_ap1r3_el2
15725  *
15726  * AP Interrupt Controller Hyp Active Priorities (1,3) Register
15727  * Provides information about the active priorities for the
15728  *     current EL2 interrupt regime.
15729  */
15730 union bdk_ap_ich_ap1r3_el2
15731 {
15732     uint32_t u;
15733     struct bdk_ap_ich_ap1r3_el2_s
15734     {
15735 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15736         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP1R0_EL2[PRIORITYBITS]. */
15737 #else /* Word 0 - Little Endian */
15738         uint32_t prioritybits          : 32; /**< [ 31:  0](R/W) See description of AP_ICH_AP1R0_EL2[PRIORITYBITS]. */
15739 #endif /* Word 0 - End */
15740     } s;
15741     /* struct bdk_ap_ich_ap1r3_el2_s cn; */
15742 };
15743 typedef union bdk_ap_ich_ap1r3_el2 bdk_ap_ich_ap1r3_el2_t;
15744 
15745 #define BDK_AP_ICH_AP1R3_EL2 BDK_AP_ICH_AP1R3_EL2_FUNC()
15746 static inline uint64_t BDK_AP_ICH_AP1R3_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_AP1R3_EL2_FUNC(void)15747 static inline uint64_t BDK_AP_ICH_AP1R3_EL2_FUNC(void)
15748 {
15749     return 0x3040c090300ll;
15750 }
15751 
15752 #define typedef_BDK_AP_ICH_AP1R3_EL2 bdk_ap_ich_ap1r3_el2_t
15753 #define bustype_BDK_AP_ICH_AP1R3_EL2 BDK_CSR_TYPE_SYSREG
15754 #define basename_BDK_AP_ICH_AP1R3_EL2 "AP_ICH_AP1R3_EL2"
15755 #define busnum_BDK_AP_ICH_AP1R3_EL2 0
15756 #define arguments_BDK_AP_ICH_AP1R3_EL2 -1,-1,-1,-1
15757 
15758 /**
15759  * Register (SYSREG) ap_ich_eisr_el2
15760  *
15761  * AP Interrupt Controller End of Interrupt Status Register
15762  * When a maintenance interrupt is received, this register helps
15763  *     determine which List registers have outstanding EOI interrupts
15764  *     that require servicing.
15765  */
15766 union bdk_ap_ich_eisr_el2
15767 {
15768     uint32_t u;
15769     struct bdk_ap_ich_eisr_el2_s
15770     {
15771 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15772         uint32_t status_bits           : 32; /**< [ 31:  0](RO) EOI status bit for List register \<n\>:
15773                                                                  For any ICH_LR\<n\>_EL2, the corresponding status bit is set to
15774                                                                      1 if ICH_LR\<n\>_EL2[State] is 0x0.
15775                                                                  0 = List register \<n\>, ICH_LR\<n\>_EL2, does not have an EOI.
15776                                                                  1 = List register \<n\>, ICH_LR\<n\>_EL2, has an EOI. */
15777 #else /* Word 0 - Little Endian */
15778         uint32_t status_bits           : 32; /**< [ 31:  0](RO) EOI status bit for List register \<n\>:
15779                                                                  For any ICH_LR\<n\>_EL2, the corresponding status bit is set to
15780                                                                      1 if ICH_LR\<n\>_EL2[State] is 0x0.
15781                                                                  0 = List register \<n\>, ICH_LR\<n\>_EL2, does not have an EOI.
15782                                                                  1 = List register \<n\>, ICH_LR\<n\>_EL2, has an EOI. */
15783 #endif /* Word 0 - End */
15784     } s;
15785     /* struct bdk_ap_ich_eisr_el2_s cn; */
15786 };
15787 typedef union bdk_ap_ich_eisr_el2 bdk_ap_ich_eisr_el2_t;
15788 
15789 #define BDK_AP_ICH_EISR_EL2 BDK_AP_ICH_EISR_EL2_FUNC()
15790 static inline uint64_t BDK_AP_ICH_EISR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_EISR_EL2_FUNC(void)15791 static inline uint64_t BDK_AP_ICH_EISR_EL2_FUNC(void)
15792 {
15793     return 0x3040c0b0300ll;
15794 }
15795 
15796 #define typedef_BDK_AP_ICH_EISR_EL2 bdk_ap_ich_eisr_el2_t
15797 #define bustype_BDK_AP_ICH_EISR_EL2 BDK_CSR_TYPE_SYSREG
15798 #define basename_BDK_AP_ICH_EISR_EL2 "AP_ICH_EISR_EL2"
15799 #define busnum_BDK_AP_ICH_EISR_EL2 0
15800 #define arguments_BDK_AP_ICH_EISR_EL2 -1,-1,-1,-1
15801 
15802 /**
15803  * Register (SYSREG) ap_ich_elrsr_el2
15804  *
15805  * AP Interrupt Controller Empty List Register Status Register
15806  * This register can be used to locate a usable List register
15807  *     when the hypervisor is delivering an interrupt to a Guest OS.
15808  *
15809  * Internal:
15810  * This register was renamed ICH_ELRSR_EL2 in OBAN of 2014-06-13 after release v20 of GIC v3.
15811  */
15812 union bdk_ap_ich_elrsr_el2
15813 {
15814     uint32_t u;
15815     struct bdk_ap_ich_elrsr_el2_s
15816     {
15817 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15818         uint32_t status_bits           : 32; /**< [ 31:  0](RO) Status bit for List register \<n\>, ICH_LR\<n\>_EL2:
15819                                                                  For any ICH_LR\<n\>_EL2, the corresponding status bit is set to
15820                                                                      1 if ICH_LR\<n\>_EL2[State] is 0x0.
15821                                                                  0 = List register ICH_LR\<n\>_EL2, if implemented, contains a valid
15822                                                                     interrupt. Using this List register can result in overwriting
15823                                                                      a valid interrupt.
15824                                                                  1 = List register ICH_LR\<n\>_EL2 does not contain a valid
15825                                                                      interrupt. The List register is empty and can be used without
15826                                                                      overwriting a valid interrupt or losing an EOI maintenance
15827                                                                      interrupt. */
15828 #else /* Word 0 - Little Endian */
15829         uint32_t status_bits           : 32; /**< [ 31:  0](RO) Status bit for List register \<n\>, ICH_LR\<n\>_EL2:
15830                                                                  For any ICH_LR\<n\>_EL2, the corresponding status bit is set to
15831                                                                      1 if ICH_LR\<n\>_EL2[State] is 0x0.
15832                                                                  0 = List register ICH_LR\<n\>_EL2, if implemented, contains a valid
15833                                                                     interrupt. Using this List register can result in overwriting
15834                                                                      a valid interrupt.
15835                                                                  1 = List register ICH_LR\<n\>_EL2 does not contain a valid
15836                                                                      interrupt. The List register is empty and can be used without
15837                                                                      overwriting a valid interrupt or losing an EOI maintenance
15838                                                                      interrupt. */
15839 #endif /* Word 0 - End */
15840     } s;
15841     /* struct bdk_ap_ich_elrsr_el2_s cn; */
15842 };
15843 typedef union bdk_ap_ich_elrsr_el2 bdk_ap_ich_elrsr_el2_t;
15844 
15845 #define BDK_AP_ICH_ELRSR_EL2 BDK_AP_ICH_ELRSR_EL2_FUNC()
15846 static inline uint64_t BDK_AP_ICH_ELRSR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_ELRSR_EL2_FUNC(void)15847 static inline uint64_t BDK_AP_ICH_ELRSR_EL2_FUNC(void)
15848 {
15849     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
15850         return 0x3040c0b0500ll;
15851     __bdk_csr_fatal("AP_ICH_ELRSR_EL2", 0, 0, 0, 0, 0);
15852 }
15853 
15854 #define typedef_BDK_AP_ICH_ELRSR_EL2 bdk_ap_ich_elrsr_el2_t
15855 #define bustype_BDK_AP_ICH_ELRSR_EL2 BDK_CSR_TYPE_SYSREG
15856 #define basename_BDK_AP_ICH_ELRSR_EL2 "AP_ICH_ELRSR_EL2"
15857 #define busnum_BDK_AP_ICH_ELRSR_EL2 0
15858 #define arguments_BDK_AP_ICH_ELRSR_EL2 -1,-1,-1,-1
15859 
15860 /**
15861  * Register (SYSREG) ap_ich_elsr_el2
15862  *
15863  * AP Interrupt Controller Empty List Register Status Register
15864  * This register can be used to locate a usable List register
15865  *     when the hypervisor is delivering an interrupt to a Guest OS.
15866  */
15867 union bdk_ap_ich_elsr_el2
15868 {
15869     uint32_t u;
15870     struct bdk_ap_ich_elsr_el2_s
15871     {
15872 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15873         uint32_t status_bits           : 32; /**< [ 31:  0](RO) Status bit for List register \<n\>, ICH_LR\<n\>_EL2:
15874                                                                  For any ICH_LR\<n\>_EL2, the corresponding status bit is set to
15875                                                                      1 if ICH_LR\<n\>_EL2[State] is 0x0.
15876                                                                  0 = List register ICH_LR\<n\>_EL2, if implemented, contains a valid
15877                                                                     interrupt. Using this List register can result in overwriting
15878                                                                      a valid interrupt.
15879                                                                  1 = List register ICH_LR\<n\>_EL2 does not contain a valid
15880                                                                      interrupt. The List register is empty and can be used without
15881                                                                      overwriting a valid interrupt or losing an EOI maintenance
15882                                                                      interrupt. */
15883 #else /* Word 0 - Little Endian */
15884         uint32_t status_bits           : 32; /**< [ 31:  0](RO) Status bit for List register \<n\>, ICH_LR\<n\>_EL2:
15885                                                                  For any ICH_LR\<n\>_EL2, the corresponding status bit is set to
15886                                                                      1 if ICH_LR\<n\>_EL2[State] is 0x0.
15887                                                                  0 = List register ICH_LR\<n\>_EL2, if implemented, contains a valid
15888                                                                     interrupt. Using this List register can result in overwriting
15889                                                                      a valid interrupt.
15890                                                                  1 = List register ICH_LR\<n\>_EL2 does not contain a valid
15891                                                                      interrupt. The List register is empty and can be used without
15892                                                                      overwriting a valid interrupt or losing an EOI maintenance
15893                                                                      interrupt. */
15894 #endif /* Word 0 - End */
15895     } s;
15896     /* struct bdk_ap_ich_elsr_el2_s cn; */
15897 };
15898 typedef union bdk_ap_ich_elsr_el2 bdk_ap_ich_elsr_el2_t;
15899 
15900 #define BDK_AP_ICH_ELSR_EL2 BDK_AP_ICH_ELSR_EL2_FUNC()
15901 static inline uint64_t BDK_AP_ICH_ELSR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_ELSR_EL2_FUNC(void)15902 static inline uint64_t BDK_AP_ICH_ELSR_EL2_FUNC(void)
15903 {
15904     if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
15905         return 0x3040c0b0500ll;
15906     __bdk_csr_fatal("AP_ICH_ELSR_EL2", 0, 0, 0, 0, 0);
15907 }
15908 
15909 #define typedef_BDK_AP_ICH_ELSR_EL2 bdk_ap_ich_elsr_el2_t
15910 #define bustype_BDK_AP_ICH_ELSR_EL2 BDK_CSR_TYPE_SYSREG
15911 #define basename_BDK_AP_ICH_ELSR_EL2 "AP_ICH_ELSR_EL2"
15912 #define busnum_BDK_AP_ICH_ELSR_EL2 0
15913 #define arguments_BDK_AP_ICH_ELSR_EL2 -1,-1,-1,-1
15914 
15915 /**
15916  * Register (SYSREG) ap_ich_hcr_el2
15917  *
15918  * AP Interrupt Controller Hyp Control Register
15919  * Controls the environment for guest operating systems.
15920  */
15921 union bdk_ap_ich_hcr_el2
15922 {
15923     uint32_t u;
15924     struct bdk_ap_ich_hcr_el2_s
15925     {
15926 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
15927         uint32_t eoicount              : 5;  /**< [ 31: 27](R/W) Counts the number of EOIs received that do not have a
15928                                                                      corresponding entry in the List registers. The virtual CPU
15929                                                                      interface increments this field automatically when a matching
15930                                                                      EOI is received.
15931 
15932                                                                  EOIs that do not clear a bit in one of the Active Priorities
15933                                                                      registers ICH_APmRn_EL2 do not cause an increment.
15934 
15935                                                                  Although not possible under correct operation, if an EOI
15936                                                                      occurs when the value of this field is 31, this field wraps to
15937                                                                      0.
15938 
15939                                                                  The maintenance interrupt is asserted whenever this field is
15940                                                                      nonzero and the LRENPIE bit is set to 1. */
15941         uint32_t reserved_15_26        : 12;
15942         uint32_t tdir                  : 1;  /**< [ 14: 14](R/W) Trap nonsecure EL1 writes to ICC_DIR_EL1:
15943                                                                    0 = Nonsecure EL1 writes of ICC_DIR_EL1 do not cause a trap to EL2, unless trapped by
15944                                                                  other mechanisms.
15945                                                                    1 = Nonsecure EL1 writes of ICC_DIR_EL1 are trapped to EL2. */
15946         uint32_t tsei                  : 1;  /**< [ 13: 13](RO) A locally generated SEI will trap to EL2 if this bit is set.  This bit is RES0 when
15947                                                                  AP_ICH_VTR_EL2[SEIS] is not set. */
15948         uint32_t tall1                 : 1;  /**< [ 12: 12](R/W) Trap all nonsecure EL1 accesses to ICC_* system registers for
15949                                                                      group 1 interrupts to EL2.
15950                                                                  0 = Non-Secure EL1 accesses to ICC_* registers for group 1
15951                                                                      interrupts proceed as normal.
15952                                                                  1 = Any nonsecure EL1 accesses to ICC_* registers for group 1
15953                                                                      interrupts trap to EL2. */
15954         uint32_t tall0                 : 1;  /**< [ 11: 11](R/W) Trap all nonsecure EL1 accesses to ICC_* system registers for
15955                                                                      group 0 interrupts to EL2.
15956                                                                  0 = Non-Secure EL1 accesses to ICC_* registers for group 0
15957                                                                      interrupts proceed as normal.
15958                                                                  1 = Any nonsecure EL1 accesses to ICC_* registers for group 0
15959                                                                      interrupts trap to EL2. */
15960         uint32_t tc                    : 1;  /**< [ 10: 10](R/W) Trap all nonsecure El1 accesses to system registers that are
15961                                                                      common to group 0 and group 1 to EL2.
15962                                                                  This affects AP_ICC_DIR_EL1, AP_ICC_PMR_EL1, and AP_ICC_RPR_EL1.
15963                                                                  0 = Nonsecure EL1 accesses to common registers proceed as normal.
15964                                                                  1 = Any nonsecure EL1 accesses to common registers trap to EL2. */
15965         uint32_t reserved_8_9          : 2;
15966         uint32_t vgrp1die              : 1;  /**< [  7:  7](R/W) VM Disable Group 1 Interrupt Enable. Enables the signaling of
15967                                                                      a maintenance interrupt while signaling of Group 1 interrupts
15968                                                                      from the virtual CPU interface to the connected virtual
15969                                                                      machine is disabled:
15970                                                                  0 = Maintenance interrupt disabled.
15971                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp1] is
15972                                                                      set to 0. */
15973         uint32_t vgrp1eie              : 1;  /**< [  6:  6](R/W) VM Enable Group 1 Interrupt Enable. Enables the signaling of a
15974                                                                      maintenance interrupt while signaling of Group 1 interrupts
15975                                                                      from the virtual CPU interface to the connected virtual
15976                                                                      machine is enabled:
15977                                                                  0 = Maintenance interrupt disabled.
15978                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp1] is
15979                                                                      set to 1. */
15980         uint32_t vgrp0die              : 1;  /**< [  5:  5](R/W) VM Disable Group 0 Interrupt Enable. Enables the signaling of
15981                                                                      a maintenance interrupt while signaling of Group 0 interrupts
15982                                                                      from the virtual CPU interface to the connected virtual
15983                                                                      machine is disabled:
15984                                                                  0 = Maintenance interrupt disabled.
15985                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp0] is
15986                                                                      set to 0. */
15987         uint32_t vgrp0eie              : 1;  /**< [  4:  4](R/W) VM Enable Group 0 Interrupt Enable. Enables the signaling of a
15988                                                                      maintenance interrupt while signaling of Group 0 interrupts
15989                                                                      from the virtual CPU interface to the connected virtual
15990                                                                      machine is enabled:
15991                                                                  0 = Maintenance interrupt disabled.
15992                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp0] is
15993                                                                      set to 1. */
15994         uint32_t npie                  : 1;  /**< [  3:  3](R/W) No Pending Interrupt Enable. Enables the signaling of a
15995                                                                      maintenance interrupt while no pending interrupts are present
15996                                                                      in the List registers:
15997                                                                  0 = Maintenance interrupt disabled.
15998                                                                  1 = Maintenance interupt signaled while the List registers contain
15999                                                                      no interrupts in the pending state. */
16000         uint32_t lrenpie               : 1;  /**< [  2:  2](R/W) List Register Entry Not Present Interrupt Enable. Enables the
16001                                                                      signaling of a maintenance interrupt while the virtual CPU
16002                                                                      interface does not have a corresponding valid List register
16003                                                                      entry for an EOI request:
16004                                                                  0 = Maintenance interrupt disabled.
16005                                                                  1 = A maintenance interrupt is asserted while the EOIcount field
16006                                                                      is not 0. */
16007         uint32_t uie                   : 1;  /**< [  1:  1](R/W) Underflow Interrupt Enable. Enables the signaling of a
16008                                                                      maintenance interrupt when the List registers are empty, or
16009                                                                      hold only one valid entry:
16010                                                                  0 = Maintenance interrupt disabled.
16011                                                                  1 = A maintenance interrupt is asserted if none, or only one, of
16012                                                                      the List register entries is marked as a valid interrupt. */
16013         uint32_t en                    : 1;  /**< [  0:  0](R/W) Enable. Global enable bit for the virtual CPU interface:
16014                                                                  When this field is set to 0:
16015                                                                   The virtual CPU interface does not signal any maintenance
16016                                                                      interrupts.
16017                                                                   The virtual CPU interface does not signal any virtual
16018                                                                      interrupts.
16019                                                                   A read of GICV_IAR or GICV_AIAR returns a spurious interrupt
16020                                                                      ID.
16021                                                                  0 = Virtual CPU interface operation disabled.
16022                                                                  1 = Virtual CPU interface operation enabled. */
16023 #else /* Word 0 - Little Endian */
16024         uint32_t en                    : 1;  /**< [  0:  0](R/W) Enable. Global enable bit for the virtual CPU interface:
16025                                                                  When this field is set to 0:
16026                                                                   The virtual CPU interface does not signal any maintenance
16027                                                                      interrupts.
16028                                                                   The virtual CPU interface does not signal any virtual
16029                                                                      interrupts.
16030                                                                   A read of GICV_IAR or GICV_AIAR returns a spurious interrupt
16031                                                                      ID.
16032                                                                  0 = Virtual CPU interface operation disabled.
16033                                                                  1 = Virtual CPU interface operation enabled. */
16034         uint32_t uie                   : 1;  /**< [  1:  1](R/W) Underflow Interrupt Enable. Enables the signaling of a
16035                                                                      maintenance interrupt when the List registers are empty, or
16036                                                                      hold only one valid entry:
16037                                                                  0 = Maintenance interrupt disabled.
16038                                                                  1 = A maintenance interrupt is asserted if none, or only one, of
16039                                                                      the List register entries is marked as a valid interrupt. */
16040         uint32_t lrenpie               : 1;  /**< [  2:  2](R/W) List Register Entry Not Present Interrupt Enable. Enables the
16041                                                                      signaling of a maintenance interrupt while the virtual CPU
16042                                                                      interface does not have a corresponding valid List register
16043                                                                      entry for an EOI request:
16044                                                                  0 = Maintenance interrupt disabled.
16045                                                                  1 = A maintenance interrupt is asserted while the EOIcount field
16046                                                                      is not 0. */
16047         uint32_t npie                  : 1;  /**< [  3:  3](R/W) No Pending Interrupt Enable. Enables the signaling of a
16048                                                                      maintenance interrupt while no pending interrupts are present
16049                                                                      in the List registers:
16050                                                                  0 = Maintenance interrupt disabled.
16051                                                                  1 = Maintenance interupt signaled while the List registers contain
16052                                                                      no interrupts in the pending state. */
16053         uint32_t vgrp0eie              : 1;  /**< [  4:  4](R/W) VM Enable Group 0 Interrupt Enable. Enables the signaling of a
16054                                                                      maintenance interrupt while signaling of Group 0 interrupts
16055                                                                      from the virtual CPU interface to the connected virtual
16056                                                                      machine is enabled:
16057                                                                  0 = Maintenance interrupt disabled.
16058                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp0] is
16059                                                                      set to 1. */
16060         uint32_t vgrp0die              : 1;  /**< [  5:  5](R/W) VM Disable Group 0 Interrupt Enable. Enables the signaling of
16061                                                                      a maintenance interrupt while signaling of Group 0 interrupts
16062                                                                      from the virtual CPU interface to the connected virtual
16063                                                                      machine is disabled:
16064                                                                  0 = Maintenance interrupt disabled.
16065                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp0] is
16066                                                                      set to 0. */
16067         uint32_t vgrp1eie              : 1;  /**< [  6:  6](R/W) VM Enable Group 1 Interrupt Enable. Enables the signaling of a
16068                                                                      maintenance interrupt while signaling of Group 1 interrupts
16069                                                                      from the virtual CPU interface to the connected virtual
16070                                                                      machine is enabled:
16071                                                                  0 = Maintenance interrupt disabled.
16072                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp1] is
16073                                                                      set to 1. */
16074         uint32_t vgrp1die              : 1;  /**< [  7:  7](R/W) VM Disable Group 1 Interrupt Enable. Enables the signaling of
16075                                                                      a maintenance interrupt while signaling of Group 1 interrupts
16076                                                                      from the virtual CPU interface to the connected virtual
16077                                                                      machine is disabled:
16078                                                                  0 = Maintenance interrupt disabled.
16079                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp1] is
16080                                                                      set to 0. */
16081         uint32_t reserved_8_9          : 2;
16082         uint32_t tc                    : 1;  /**< [ 10: 10](R/W) Trap all nonsecure El1 accesses to system registers that are
16083                                                                      common to group 0 and group 1 to EL2.
16084                                                                  This affects AP_ICC_DIR_EL1, AP_ICC_PMR_EL1, and AP_ICC_RPR_EL1.
16085                                                                  0 = Nonsecure EL1 accesses to common registers proceed as normal.
16086                                                                  1 = Any nonsecure EL1 accesses to common registers trap to EL2. */
16087         uint32_t tall0                 : 1;  /**< [ 11: 11](R/W) Trap all nonsecure EL1 accesses to ICC_* system registers for
16088                                                                      group 0 interrupts to EL2.
16089                                                                  0 = Non-Secure EL1 accesses to ICC_* registers for group 0
16090                                                                      interrupts proceed as normal.
16091                                                                  1 = Any nonsecure EL1 accesses to ICC_* registers for group 0
16092                                                                      interrupts trap to EL2. */
16093         uint32_t tall1                 : 1;  /**< [ 12: 12](R/W) Trap all nonsecure EL1 accesses to ICC_* system registers for
16094                                                                      group 1 interrupts to EL2.
16095                                                                  0 = Non-Secure EL1 accesses to ICC_* registers for group 1
16096                                                                      interrupts proceed as normal.
16097                                                                  1 = Any nonsecure EL1 accesses to ICC_* registers for group 1
16098                                                                      interrupts trap to EL2. */
16099         uint32_t tsei                  : 1;  /**< [ 13: 13](RO) A locally generated SEI will trap to EL2 if this bit is set.  This bit is RES0 when
16100                                                                  AP_ICH_VTR_EL2[SEIS] is not set. */
16101         uint32_t tdir                  : 1;  /**< [ 14: 14](R/W) Trap nonsecure EL1 writes to ICC_DIR_EL1:
16102                                                                    0 = Nonsecure EL1 writes of ICC_DIR_EL1 do not cause a trap to EL2, unless trapped by
16103                                                                  other mechanisms.
16104                                                                    1 = Nonsecure EL1 writes of ICC_DIR_EL1 are trapped to EL2. */
16105         uint32_t reserved_15_26        : 12;
16106         uint32_t eoicount              : 5;  /**< [ 31: 27](R/W) Counts the number of EOIs received that do not have a
16107                                                                      corresponding entry in the List registers. The virtual CPU
16108                                                                      interface increments this field automatically when a matching
16109                                                                      EOI is received.
16110 
16111                                                                  EOIs that do not clear a bit in one of the Active Priorities
16112                                                                      registers ICH_APmRn_EL2 do not cause an increment.
16113 
16114                                                                  Although not possible under correct operation, if an EOI
16115                                                                      occurs when the value of this field is 31, this field wraps to
16116                                                                      0.
16117 
16118                                                                  The maintenance interrupt is asserted whenever this field is
16119                                                                      nonzero and the LRENPIE bit is set to 1. */
16120 #endif /* Word 0 - End */
16121     } s;
16122     struct bdk_ap_ich_hcr_el2_cn8
16123     {
16124 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16125         uint32_t eoicount              : 5;  /**< [ 31: 27](R/W) Counts the number of EOIs received that do not have a
16126                                                                      corresponding entry in the List registers. The virtual CPU
16127                                                                      interface increments this field automatically when a matching
16128                                                                      EOI is received.
16129 
16130                                                                  EOIs that do not clear a bit in one of the Active Priorities
16131                                                                      registers ICH_APmRn_EL2 do not cause an increment.
16132 
16133                                                                  Although not possible under correct operation, if an EOI
16134                                                                      occurs when the value of this field is 31, this field wraps to
16135                                                                      0.
16136 
16137                                                                  The maintenance interrupt is asserted whenever this field is
16138                                                                      nonzero and the LRENPIE bit is set to 1. */
16139         uint32_t reserved_14_26        : 13;
16140         uint32_t tsei                  : 1;  /**< [ 13: 13](RO) A locally generated SEI will trap to EL2 if this bit is set.  This bit is RES0 when
16141                                                                  AP_ICH_VTR_EL2[SEIS] is not set. */
16142         uint32_t tall1                 : 1;  /**< [ 12: 12](R/W) Trap all nonsecure EL1 accesses to ICC_* system registers for
16143                                                                      group 1 interrupts to EL2.
16144                                                                  0 = Non-Secure EL1 accesses to ICC_* registers for group 1
16145                                                                      interrupts proceed as normal.
16146                                                                  1 = Any nonsecure EL1 accesses to ICC_* registers for group 1
16147                                                                      interrupts trap to EL2. */
16148         uint32_t tall0                 : 1;  /**< [ 11: 11](R/W) Trap all nonsecure EL1 accesses to ICC_* system registers for
16149                                                                      group 0 interrupts to EL2.
16150                                                                  0 = Non-Secure EL1 accesses to ICC_* registers for group 0
16151                                                                      interrupts proceed as normal.
16152                                                                  1 = Any nonsecure EL1 accesses to ICC_* registers for group 0
16153                                                                      interrupts trap to EL2. */
16154         uint32_t tc                    : 1;  /**< [ 10: 10](R/W) Trap all nonsecure El1 accesses to system registers that are
16155                                                                      common to group 0 and group 1 to EL2.
16156                                                                  This affects AP_ICC_DIR_EL1, AP_ICC_PMR_EL1, and AP_ICC_RPR_EL1.
16157                                                                  0 = Nonsecure EL1 accesses to common registers proceed as normal.
16158                                                                  1 = Any nonsecure EL1 accesses to common registers trap to EL2. */
16159         uint32_t reserved_8_9          : 2;
16160         uint32_t vgrp1die              : 1;  /**< [  7:  7](R/W) VM Disable Group 1 Interrupt Enable. Enables the signaling of
16161                                                                      a maintenance interrupt while signaling of Group 1 interrupts
16162                                                                      from the virtual CPU interface to the connected virtual
16163                                                                      machine is disabled:
16164                                                                  0 = Maintenance interrupt disabled.
16165                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp1] is
16166                                                                      set to 0. */
16167         uint32_t vgrp1eie              : 1;  /**< [  6:  6](R/W) VM Enable Group 1 Interrupt Enable. Enables the signaling of a
16168                                                                      maintenance interrupt while signaling of Group 1 interrupts
16169                                                                      from the virtual CPU interface to the connected virtual
16170                                                                      machine is enabled:
16171                                                                  0 = Maintenance interrupt disabled.
16172                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp1] is
16173                                                                      set to 1. */
16174         uint32_t vgrp0die              : 1;  /**< [  5:  5](R/W) VM Disable Group 0 Interrupt Enable. Enables the signaling of
16175                                                                      a maintenance interrupt while signaling of Group 0 interrupts
16176                                                                      from the virtual CPU interface to the connected virtual
16177                                                                      machine is disabled:
16178                                                                  0 = Maintenance interrupt disabled.
16179                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp0] is
16180                                                                      set to 0. */
16181         uint32_t vgrp0eie              : 1;  /**< [  4:  4](R/W) VM Enable Group 0 Interrupt Enable. Enables the signaling of a
16182                                                                      maintenance interrupt while signaling of Group 0 interrupts
16183                                                                      from the virtual CPU interface to the connected virtual
16184                                                                      machine is enabled:
16185                                                                  0 = Maintenance interrupt disabled.
16186                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp0] is
16187                                                                      set to 1. */
16188         uint32_t npie                  : 1;  /**< [  3:  3](R/W) No Pending Interrupt Enable. Enables the signaling of a
16189                                                                      maintenance interrupt while no pending interrupts are present
16190                                                                      in the List registers:
16191                                                                  0 = Maintenance interrupt disabled.
16192                                                                  1 = Maintenance interupt signaled while the List registers contain
16193                                                                      no interrupts in the pending state. */
16194         uint32_t lrenpie               : 1;  /**< [  2:  2](R/W) List Register Entry Not Present Interrupt Enable. Enables the
16195                                                                      signaling of a maintenance interrupt while the virtual CPU
16196                                                                      interface does not have a corresponding valid List register
16197                                                                      entry for an EOI request:
16198                                                                  0 = Maintenance interrupt disabled.
16199                                                                  1 = A maintenance interrupt is asserted while the EOIcount field
16200                                                                      is not 0. */
16201         uint32_t uie                   : 1;  /**< [  1:  1](R/W) Underflow Interrupt Enable. Enables the signaling of a
16202                                                                      maintenance interrupt when the List registers are empty, or
16203                                                                      hold only one valid entry:
16204                                                                  0 = Maintenance interrupt disabled.
16205                                                                  1 = A maintenance interrupt is asserted if none, or only one, of
16206                                                                      the List register entries is marked as a valid interrupt. */
16207         uint32_t en                    : 1;  /**< [  0:  0](R/W) Enable. Global enable bit for the virtual CPU interface:
16208                                                                  When this field is set to 0:
16209                                                                   The virtual CPU interface does not signal any maintenance
16210                                                                      interrupts.
16211                                                                   The virtual CPU interface does not signal any virtual
16212                                                                      interrupts.
16213                                                                   A read of GICV_IAR or GICV_AIAR returns a spurious interrupt
16214                                                                      ID.
16215                                                                  0 = Virtual CPU interface operation disabled.
16216                                                                  1 = Virtual CPU interface operation enabled. */
16217 #else /* Word 0 - Little Endian */
16218         uint32_t en                    : 1;  /**< [  0:  0](R/W) Enable. Global enable bit for the virtual CPU interface:
16219                                                                  When this field is set to 0:
16220                                                                   The virtual CPU interface does not signal any maintenance
16221                                                                      interrupts.
16222                                                                   The virtual CPU interface does not signal any virtual
16223                                                                      interrupts.
16224                                                                   A read of GICV_IAR or GICV_AIAR returns a spurious interrupt
16225                                                                      ID.
16226                                                                  0 = Virtual CPU interface operation disabled.
16227                                                                  1 = Virtual CPU interface operation enabled. */
16228         uint32_t uie                   : 1;  /**< [  1:  1](R/W) Underflow Interrupt Enable. Enables the signaling of a
16229                                                                      maintenance interrupt when the List registers are empty, or
16230                                                                      hold only one valid entry:
16231                                                                  0 = Maintenance interrupt disabled.
16232                                                                  1 = A maintenance interrupt is asserted if none, or only one, of
16233                                                                      the List register entries is marked as a valid interrupt. */
16234         uint32_t lrenpie               : 1;  /**< [  2:  2](R/W) List Register Entry Not Present Interrupt Enable. Enables the
16235                                                                      signaling of a maintenance interrupt while the virtual CPU
16236                                                                      interface does not have a corresponding valid List register
16237                                                                      entry for an EOI request:
16238                                                                  0 = Maintenance interrupt disabled.
16239                                                                  1 = A maintenance interrupt is asserted while the EOIcount field
16240                                                                      is not 0. */
16241         uint32_t npie                  : 1;  /**< [  3:  3](R/W) No Pending Interrupt Enable. Enables the signaling of a
16242                                                                      maintenance interrupt while no pending interrupts are present
16243                                                                      in the List registers:
16244                                                                  0 = Maintenance interrupt disabled.
16245                                                                  1 = Maintenance interupt signaled while the List registers contain
16246                                                                      no interrupts in the pending state. */
16247         uint32_t vgrp0eie              : 1;  /**< [  4:  4](R/W) VM Enable Group 0 Interrupt Enable. Enables the signaling of a
16248                                                                      maintenance interrupt while signaling of Group 0 interrupts
16249                                                                      from the virtual CPU interface to the connected virtual
16250                                                                      machine is enabled:
16251                                                                  0 = Maintenance interrupt disabled.
16252                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp0] is
16253                                                                      set to 1. */
16254         uint32_t vgrp0die              : 1;  /**< [  5:  5](R/W) VM Disable Group 0 Interrupt Enable. Enables the signaling of
16255                                                                      a maintenance interrupt while signaling of Group 0 interrupts
16256                                                                      from the virtual CPU interface to the connected virtual
16257                                                                      machine is disabled:
16258                                                                  0 = Maintenance interrupt disabled.
16259                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp0] is
16260                                                                      set to 0. */
16261         uint32_t vgrp1eie              : 1;  /**< [  6:  6](R/W) VM Enable Group 1 Interrupt Enable. Enables the signaling of a
16262                                                                      maintenance interrupt while signaling of Group 1 interrupts
16263                                                                      from the virtual CPU interface to the connected virtual
16264                                                                      machine is enabled:
16265                                                                  0 = Maintenance interrupt disabled.
16266                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp1] is
16267                                                                      set to 1. */
16268         uint32_t vgrp1die              : 1;  /**< [  7:  7](R/W) VM Disable Group 1 Interrupt Enable. Enables the signaling of
16269                                                                      a maintenance interrupt while signaling of Group 1 interrupts
16270                                                                      from the virtual CPU interface to the connected virtual
16271                                                                      machine is disabled:
16272                                                                  0 = Maintenance interrupt disabled.
16273                                                                  1 = Maintenance interrupt signaled while GICV_CTLR[EnableGrp1] is
16274                                                                      set to 0. */
16275         uint32_t reserved_8_9          : 2;
16276         uint32_t tc                    : 1;  /**< [ 10: 10](R/W) Trap all nonsecure El1 accesses to system registers that are
16277                                                                      common to group 0 and group 1 to EL2.
16278                                                                  This affects AP_ICC_DIR_EL1, AP_ICC_PMR_EL1, and AP_ICC_RPR_EL1.
16279                                                                  0 = Nonsecure EL1 accesses to common registers proceed as normal.
16280                                                                  1 = Any nonsecure EL1 accesses to common registers trap to EL2. */
16281         uint32_t tall0                 : 1;  /**< [ 11: 11](R/W) Trap all nonsecure EL1 accesses to ICC_* system registers for
16282                                                                      group 0 interrupts to EL2.
16283                                                                  0 = Non-Secure EL1 accesses to ICC_* registers for group 0
16284                                                                      interrupts proceed as normal.
16285                                                                  1 = Any nonsecure EL1 accesses to ICC_* registers for group 0
16286                                                                      interrupts trap to EL2. */
16287         uint32_t tall1                 : 1;  /**< [ 12: 12](R/W) Trap all nonsecure EL1 accesses to ICC_* system registers for
16288                                                                      group 1 interrupts to EL2.
16289                                                                  0 = Non-Secure EL1 accesses to ICC_* registers for group 1
16290                                                                      interrupts proceed as normal.
16291                                                                  1 = Any nonsecure EL1 accesses to ICC_* registers for group 1
16292                                                                      interrupts trap to EL2. */
16293         uint32_t tsei                  : 1;  /**< [ 13: 13](RO) A locally generated SEI will trap to EL2 if this bit is set.  This bit is RES0 when
16294                                                                  AP_ICH_VTR_EL2[SEIS] is not set. */
16295         uint32_t reserved_14_26        : 13;
16296         uint32_t eoicount              : 5;  /**< [ 31: 27](R/W) Counts the number of EOIs received that do not have a
16297                                                                      corresponding entry in the List registers. The virtual CPU
16298                                                                      interface increments this field automatically when a matching
16299                                                                      EOI is received.
16300 
16301                                                                  EOIs that do not clear a bit in one of the Active Priorities
16302                                                                      registers ICH_APmRn_EL2 do not cause an increment.
16303 
16304                                                                  Although not possible under correct operation, if an EOI
16305                                                                      occurs when the value of this field is 31, this field wraps to
16306                                                                      0.
16307 
16308                                                                  The maintenance interrupt is asserted whenever this field is
16309                                                                      nonzero and the LRENPIE bit is set to 1. */
16310 #endif /* Word 0 - End */
16311     } cn8;
16312     /* struct bdk_ap_ich_hcr_el2_s cn9; */
16313 };
16314 typedef union bdk_ap_ich_hcr_el2 bdk_ap_ich_hcr_el2_t;
16315 
16316 #define BDK_AP_ICH_HCR_EL2 BDK_AP_ICH_HCR_EL2_FUNC()
16317 static inline uint64_t BDK_AP_ICH_HCR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_HCR_EL2_FUNC(void)16318 static inline uint64_t BDK_AP_ICH_HCR_EL2_FUNC(void)
16319 {
16320     return 0x3040c0b0000ll;
16321 }
16322 
16323 #define typedef_BDK_AP_ICH_HCR_EL2 bdk_ap_ich_hcr_el2_t
16324 #define bustype_BDK_AP_ICH_HCR_EL2 BDK_CSR_TYPE_SYSREG
16325 #define basename_BDK_AP_ICH_HCR_EL2 "AP_ICH_HCR_EL2"
16326 #define busnum_BDK_AP_ICH_HCR_EL2 0
16327 #define arguments_BDK_AP_ICH_HCR_EL2 -1,-1,-1,-1
16328 
16329 /**
16330  * Register (SYSREG) ap_ich_lr#_el2
16331  *
16332  * AP List Registers
16333  * Provides interrupt context information for the virtual CPU interface.
16334  */
16335 union bdk_ap_ich_lrx_el2
16336 {
16337     uint64_t u;
16338     struct bdk_ap_ich_lrx_el2_s
16339     {
16340 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16341         uint64_t state                 : 2;  /**< [ 63: 62](R/W) 0x0 = Invalid.
16342                                                                  0x1 = Pending.
16343                                                                  0x2 = Active.
16344                                                                  0x3 = Pending and Active. */
16345         uint64_t hw                    : 1;  /**< [ 61: 61](R/W) Virtual interrupt corresponds to physical interrupt. */
16346         uint64_t group                 : 1;  /**< [ 60: 60](R/W) Indicates interrupt is group 1. */
16347         uint64_t reserved_56_59        : 4;
16348         uint64_t pri                   : 8;  /**< [ 55: 48](R/W) Interrupt priority. */
16349         uint64_t reserved_42_47        : 6;
16350         uint64_t physical_id           : 10; /**< [ 41: 32](R/W) When [HW] is zero, bit 41 indicates whether this interrupt triggers an EOI
16351                                                                  maintenance interrupt and bits 40..32 are RES0. */
16352         uint64_t virtual_id            : 32; /**< [ 31:  0](R/W) Virtual interrupt ID. */
16353 #else /* Word 0 - Little Endian */
16354         uint64_t virtual_id            : 32; /**< [ 31:  0](R/W) Virtual interrupt ID. */
16355         uint64_t physical_id           : 10; /**< [ 41: 32](R/W) When [HW] is zero, bit 41 indicates whether this interrupt triggers an EOI
16356                                                                  maintenance interrupt and bits 40..32 are RES0. */
16357         uint64_t reserved_42_47        : 6;
16358         uint64_t pri                   : 8;  /**< [ 55: 48](R/W) Interrupt priority. */
16359         uint64_t reserved_56_59        : 4;
16360         uint64_t group                 : 1;  /**< [ 60: 60](R/W) Indicates interrupt is group 1. */
16361         uint64_t hw                    : 1;  /**< [ 61: 61](R/W) Virtual interrupt corresponds to physical interrupt. */
16362         uint64_t state                 : 2;  /**< [ 63: 62](R/W) 0x0 = Invalid.
16363                                                                  0x1 = Pending.
16364                                                                  0x2 = Active.
16365                                                                  0x3 = Pending and Active. */
16366 #endif /* Word 0 - End */
16367     } s;
16368     /* struct bdk_ap_ich_lrx_el2_s cn; */
16369 };
16370 typedef union bdk_ap_ich_lrx_el2 bdk_ap_ich_lrx_el2_t;
16371 
16372 static inline uint64_t BDK_AP_ICH_LRX_EL2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ICH_LRX_EL2(unsigned long a)16373 static inline uint64_t BDK_AP_ICH_LRX_EL2(unsigned long a)
16374 {
16375     if (a<=15)
16376         return 0x3040c0c0000ll + 0x100ll * ((a) & 0xf);
16377     __bdk_csr_fatal("AP_ICH_LRX_EL2", 1, a, 0, 0, 0);
16378 }
16379 
16380 #define typedef_BDK_AP_ICH_LRX_EL2(a) bdk_ap_ich_lrx_el2_t
16381 #define bustype_BDK_AP_ICH_LRX_EL2(a) BDK_CSR_TYPE_SYSREG
16382 #define basename_BDK_AP_ICH_LRX_EL2(a) "AP_ICH_LRX_EL2"
16383 #define busnum_BDK_AP_ICH_LRX_EL2(a) (a)
16384 #define arguments_BDK_AP_ICH_LRX_EL2(a) (a),-1,-1,-1
16385 
16386 /**
16387  * Register (SYSREG) ap_ich_lrc#
16388  *
16389  * AP List 32-bit Registers
16390  * Provides interrupt context information for the virtual CPU interface. Only used for Aarch32.
16391  * Here for disassembly only.
16392  */
16393 union bdk_ap_ich_lrcx
16394 {
16395     uint32_t u;
16396     struct bdk_ap_ich_lrcx_s
16397     {
16398 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16399         uint32_t reserved_0_31         : 32;
16400 #else /* Word 0 - Little Endian */
16401         uint32_t reserved_0_31         : 32;
16402 #endif /* Word 0 - End */
16403     } s;
16404     /* struct bdk_ap_ich_lrcx_s cn; */
16405 };
16406 typedef union bdk_ap_ich_lrcx bdk_ap_ich_lrcx_t;
16407 
16408 static inline uint64_t BDK_AP_ICH_LRCX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ICH_LRCX(unsigned long a)16409 static inline uint64_t BDK_AP_ICH_LRCX(unsigned long a)
16410 {
16411     if (a<=15)
16412         return 0x3040c0e0000ll + 0x100ll * ((a) & 0xf);
16413     __bdk_csr_fatal("AP_ICH_LRCX", 1, a, 0, 0, 0);
16414 }
16415 
16416 #define typedef_BDK_AP_ICH_LRCX(a) bdk_ap_ich_lrcx_t
16417 #define bustype_BDK_AP_ICH_LRCX(a) BDK_CSR_TYPE_SYSREG
16418 #define basename_BDK_AP_ICH_LRCX(a) "AP_ICH_LRCX"
16419 #define busnum_BDK_AP_ICH_LRCX(a) (a)
16420 #define arguments_BDK_AP_ICH_LRCX(a) (a),-1,-1,-1
16421 
16422 /**
16423  * Register (SYSREG) ap_ich_misr_el2
16424  *
16425  * AP Interrupt Controller Maintenance Interrupt State Register
16426  * Indicates which maintenance interrupts are asserted.
16427  */
16428 union bdk_ap_ich_misr_el2
16429 {
16430     uint32_t u;
16431     struct bdk_ap_ich_misr_el2_s
16432     {
16433 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16434         uint32_t reserved_9_31         : 23;
16435         uint32_t vsei                  : 1;  /**< [  8:  8](RO) Virtual SEI. Set to 1 when a condition that would result in
16436                                                                      generation of an SEI is detected during a virtual access to an
16437                                                                      ICC_* system register. */
16438         uint32_t vgrp1d                : 1;  /**< [  7:  7](RO) Disabled Group 1 maintenance interrupt.
16439                                                                  Asserted whenever AP_ICH_HCR_EL2[VGrp1DIE] is 1 and
16440                                                                      AP_ICH_VMCR_EL2[VMGrp1En] is 0. */
16441         uint32_t vgrp1e                : 1;  /**< [  6:  6](RO) Enabled Group 1 maintenance interrupt.
16442                                                                  Asserted whenever AP_ICH_HCR_EL2[VGrp1EIE] is 1 and
16443                                                                      AP_ICH_VMCR_EL2[VMGrp1En] is 1. */
16444         uint32_t vgrp0d                : 1;  /**< [  5:  5](RO) Disabled Group 0 maintenance interrupt.
16445                                                                  Asserted whenever AP_ICH_HCR_EL2[VGrp0DIE] is 1 and
16446                                                                      AP_ICH_VMCR_EL2[VMGrp0En] is 0. */
16447         uint32_t vgrp0e                : 1;  /**< [  4:  4](RO) Enabled Group 0 maintenance interrupt.
16448                                                                  Asserted whenever AP_ICH_HCR_EL2[VGrp0EIE] is 1 and
16449                                                                      AP_ICH_VMCR_EL2[VMGrp0En] is 1. */
16450         uint32_t np                    : 1;  /**< [  3:  3](RO) No Pending maintenance interrupt.
16451                                                                  Asserted whenever AP_ICH_HCR_EL2[NPIE] is 1 and no List register
16452                                                                      is in pending state. */
16453         uint32_t lrenp                 : 1;  /**< [  2:  2](RO) List Register Entry Not Present maintenance interrupt.
16454                                                                  Asserted whenever AP_ICH_HCR_EL2[LRENPIE] is 1 and
16455                                                                      AP_ICH_HCR_EL2[EOIcount] is nonzero. */
16456         uint32_t u                     : 1;  /**< [  1:  1](RO) Underflow maintenance interrupt.
16457                                                                  Asserted whenever AP_ICH_HCR_EL2[UIE] is 1 and if none, or only
16458                                                                      one, of the List register entries are marked as a valid
16459                                                                      interrupt, that is, if the corresponding ICH_LR\<n\>_EL2[State]
16460                                                                      bits do not equal0x0 */
16461         uint32_t eoi                   : 1;  /**< [  0:  0](RO) EOI maintenance interrupt.
16462                                                                  Asserted whenever at least one List register is asserting an
16463                                                                      EOI interrupt. That is, when at least one bit in ICH_EISR0_EL1
16464                                                                      or ICH_EISR1_EL1 is 1. */
16465 #else /* Word 0 - Little Endian */
16466         uint32_t eoi                   : 1;  /**< [  0:  0](RO) EOI maintenance interrupt.
16467                                                                  Asserted whenever at least one List register is asserting an
16468                                                                      EOI interrupt. That is, when at least one bit in ICH_EISR0_EL1
16469                                                                      or ICH_EISR1_EL1 is 1. */
16470         uint32_t u                     : 1;  /**< [  1:  1](RO) Underflow maintenance interrupt.
16471                                                                  Asserted whenever AP_ICH_HCR_EL2[UIE] is 1 and if none, or only
16472                                                                      one, of the List register entries are marked as a valid
16473                                                                      interrupt, that is, if the corresponding ICH_LR\<n\>_EL2[State]
16474                                                                      bits do not equal0x0 */
16475         uint32_t lrenp                 : 1;  /**< [  2:  2](RO) List Register Entry Not Present maintenance interrupt.
16476                                                                  Asserted whenever AP_ICH_HCR_EL2[LRENPIE] is 1 and
16477                                                                      AP_ICH_HCR_EL2[EOIcount] is nonzero. */
16478         uint32_t np                    : 1;  /**< [  3:  3](RO) No Pending maintenance interrupt.
16479                                                                  Asserted whenever AP_ICH_HCR_EL2[NPIE] is 1 and no List register
16480                                                                      is in pending state. */
16481         uint32_t vgrp0e                : 1;  /**< [  4:  4](RO) Enabled Group 0 maintenance interrupt.
16482                                                                  Asserted whenever AP_ICH_HCR_EL2[VGrp0EIE] is 1 and
16483                                                                      AP_ICH_VMCR_EL2[VMGrp0En] is 1. */
16484         uint32_t vgrp0d                : 1;  /**< [  5:  5](RO) Disabled Group 0 maintenance interrupt.
16485                                                                  Asserted whenever AP_ICH_HCR_EL2[VGrp0DIE] is 1 and
16486                                                                      AP_ICH_VMCR_EL2[VMGrp0En] is 0. */
16487         uint32_t vgrp1e                : 1;  /**< [  6:  6](RO) Enabled Group 1 maintenance interrupt.
16488                                                                  Asserted whenever AP_ICH_HCR_EL2[VGrp1EIE] is 1 and
16489                                                                      AP_ICH_VMCR_EL2[VMGrp1En] is 1. */
16490         uint32_t vgrp1d                : 1;  /**< [  7:  7](RO) Disabled Group 1 maintenance interrupt.
16491                                                                  Asserted whenever AP_ICH_HCR_EL2[VGrp1DIE] is 1 and
16492                                                                      AP_ICH_VMCR_EL2[VMGrp1En] is 0. */
16493         uint32_t vsei                  : 1;  /**< [  8:  8](RO) Virtual SEI. Set to 1 when a condition that would result in
16494                                                                      generation of an SEI is detected during a virtual access to an
16495                                                                      ICC_* system register. */
16496         uint32_t reserved_9_31         : 23;
16497 #endif /* Word 0 - End */
16498     } s;
16499     /* struct bdk_ap_ich_misr_el2_s cn; */
16500 };
16501 typedef union bdk_ap_ich_misr_el2 bdk_ap_ich_misr_el2_t;
16502 
16503 #define BDK_AP_ICH_MISR_EL2 BDK_AP_ICH_MISR_EL2_FUNC()
16504 static inline uint64_t BDK_AP_ICH_MISR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_MISR_EL2_FUNC(void)16505 static inline uint64_t BDK_AP_ICH_MISR_EL2_FUNC(void)
16506 {
16507     return 0x3040c0b0200ll;
16508 }
16509 
16510 #define typedef_BDK_AP_ICH_MISR_EL2 bdk_ap_ich_misr_el2_t
16511 #define bustype_BDK_AP_ICH_MISR_EL2 BDK_CSR_TYPE_SYSREG
16512 #define basename_BDK_AP_ICH_MISR_EL2 "AP_ICH_MISR_EL2"
16513 #define busnum_BDK_AP_ICH_MISR_EL2 0
16514 #define arguments_BDK_AP_ICH_MISR_EL2 -1,-1,-1,-1
16515 
16516 /**
16517  * Register (SYSREG) ap_ich_vmcr_el2
16518  *
16519  * AP Interrupt Controller Virtual Machine Control Register
16520  * Enables the hypervisor to save and restore the virtual machine
16521  *     view of the GIC state.
16522  */
16523 union bdk_ap_ich_vmcr_el2
16524 {
16525     uint32_t u;
16526     struct bdk_ap_ich_vmcr_el2_s
16527     {
16528 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16529         uint32_t vpmr                  : 8;  /**< [ 31: 24](R/W) Virtual Priority Mask.
16530                                                                  Visible to the guest OS as AP_ICC_PMR_EL1 / GICV_PMR. */
16531         uint32_t vbpr0                 : 3;  /**< [ 23: 21](R/W) Virtual BPR0.
16532                                                                  Visible to the guest OS as AP_ICC_BPR0_EL1 / GICV_BPR. */
16533         uint32_t vbpr1                 : 3;  /**< [ 20: 18](R/W) Virtual BPR1.
16534                                                                  Visible to the guest OS as AP_ICC_BPR1_EL1 / GICV_ABPR. */
16535         uint32_t reserved_10_17        : 8;
16536         uint32_t veoim                 : 1;  /**< [  9:  9](R/W) Virtual EOImode.
16537                                                                  Visible to the guest OS as AP_ICC_CTLR_EL1[EOImode] /
16538                                                                      GICV_CTLR[EOImode]. */
16539         uint32_t reserved_5_8          : 4;
16540         uint32_t vcbpr                 : 1;  /**< [  4:  4](R/W) Virtual CBPR.
16541                                                                  Visible to the guest OS as AP_ICC_CTLR_EL1[CBPR] / GICV_CTLR[CBPR]. */
16542         uint32_t vfiqen                : 1;  /**< [  3:  3](R/W) Virtual FIQ enable.
16543                                                                  Visible to the guest OS as GICV_CTLR[FIQEn]. */
16544         uint32_t vackctl               : 1;  /**< [  2:  2](R/W) Virtual AckCtl.
16545                                                                  Visible to the guest OS as GICV_CTLR[AckCtl]. */
16546         uint32_t veng1                 : 1;  /**< [  1:  1](R/W) Virtual group 1 interrupt enable.
16547                                                                  Visible to the guest OS as AP_ICC_IGRPEN1_EL1[Enable] /
16548                                                                      GICV_CTLR[EnableGrp1]. */
16549         uint32_t veng0                 : 1;  /**< [  0:  0](R/W) Virtual group 0 interrupt enable.
16550                                                                  Visible to the guest OS as AP_ICC_IGRPEN0_EL1[Enable] /
16551                                                                      GICV_CTLR[EnableGrp0]. */
16552 #else /* Word 0 - Little Endian */
16553         uint32_t veng0                 : 1;  /**< [  0:  0](R/W) Virtual group 0 interrupt enable.
16554                                                                  Visible to the guest OS as AP_ICC_IGRPEN0_EL1[Enable] /
16555                                                                      GICV_CTLR[EnableGrp0]. */
16556         uint32_t veng1                 : 1;  /**< [  1:  1](R/W) Virtual group 1 interrupt enable.
16557                                                                  Visible to the guest OS as AP_ICC_IGRPEN1_EL1[Enable] /
16558                                                                      GICV_CTLR[EnableGrp1]. */
16559         uint32_t vackctl               : 1;  /**< [  2:  2](R/W) Virtual AckCtl.
16560                                                                  Visible to the guest OS as GICV_CTLR[AckCtl]. */
16561         uint32_t vfiqen                : 1;  /**< [  3:  3](R/W) Virtual FIQ enable.
16562                                                                  Visible to the guest OS as GICV_CTLR[FIQEn]. */
16563         uint32_t vcbpr                 : 1;  /**< [  4:  4](R/W) Virtual CBPR.
16564                                                                  Visible to the guest OS as AP_ICC_CTLR_EL1[CBPR] / GICV_CTLR[CBPR]. */
16565         uint32_t reserved_5_8          : 4;
16566         uint32_t veoim                 : 1;  /**< [  9:  9](R/W) Virtual EOImode.
16567                                                                  Visible to the guest OS as AP_ICC_CTLR_EL1[EOImode] /
16568                                                                      GICV_CTLR[EOImode]. */
16569         uint32_t reserved_10_17        : 8;
16570         uint32_t vbpr1                 : 3;  /**< [ 20: 18](R/W) Virtual BPR1.
16571                                                                  Visible to the guest OS as AP_ICC_BPR1_EL1 / GICV_ABPR. */
16572         uint32_t vbpr0                 : 3;  /**< [ 23: 21](R/W) Virtual BPR0.
16573                                                                  Visible to the guest OS as AP_ICC_BPR0_EL1 / GICV_BPR. */
16574         uint32_t vpmr                  : 8;  /**< [ 31: 24](R/W) Virtual Priority Mask.
16575                                                                  Visible to the guest OS as AP_ICC_PMR_EL1 / GICV_PMR. */
16576 #endif /* Word 0 - End */
16577     } s;
16578     /* struct bdk_ap_ich_vmcr_el2_s cn; */
16579 };
16580 typedef union bdk_ap_ich_vmcr_el2 bdk_ap_ich_vmcr_el2_t;
16581 
16582 #define BDK_AP_ICH_VMCR_EL2 BDK_AP_ICH_VMCR_EL2_FUNC()
16583 static inline uint64_t BDK_AP_ICH_VMCR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_VMCR_EL2_FUNC(void)16584 static inline uint64_t BDK_AP_ICH_VMCR_EL2_FUNC(void)
16585 {
16586     return 0x3040c0b0700ll;
16587 }
16588 
16589 #define typedef_BDK_AP_ICH_VMCR_EL2 bdk_ap_ich_vmcr_el2_t
16590 #define bustype_BDK_AP_ICH_VMCR_EL2 BDK_CSR_TYPE_SYSREG
16591 #define basename_BDK_AP_ICH_VMCR_EL2 "AP_ICH_VMCR_EL2"
16592 #define busnum_BDK_AP_ICH_VMCR_EL2 0
16593 #define arguments_BDK_AP_ICH_VMCR_EL2 -1,-1,-1,-1
16594 
16595 /**
16596  * Register (SYSREG) ap_ich_vseir_el2
16597  *
16598  * AP Interrupt Controller Virtual System Error Interrupt Register
16599  * Allows the hypervisor to inject a virtual SEI.
16600  */
16601 union bdk_ap_ich_vseir_el2
16602 {
16603     uint32_t u;
16604     struct bdk_ap_ich_vseir_el2_s
16605     {
16606 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16607         uint32_t valid                 : 1;  /**< [ 31: 31](R/W) System error interrupt valid.
16608                                                                  0 = No virtual system error exception is pending.
16609                                                                  1 = A virtual system error exception is pending for nonsecure
16610                                                                      EL1. */
16611         uint32_t reserved_25_30        : 6;
16612         uint32_t syndrome              : 25; /**< [ 24:  0](R/W) The value that will be presented in bits [24:0] of ESR_EL1 on
16613                                                                      entry into the SError exception handler. */
16614 #else /* Word 0 - Little Endian */
16615         uint32_t syndrome              : 25; /**< [ 24:  0](R/W) The value that will be presented in bits [24:0] of ESR_EL1 on
16616                                                                      entry into the SError exception handler. */
16617         uint32_t reserved_25_30        : 6;
16618         uint32_t valid                 : 1;  /**< [ 31: 31](R/W) System error interrupt valid.
16619                                                                  0 = No virtual system error exception is pending.
16620                                                                  1 = A virtual system error exception is pending for nonsecure
16621                                                                      EL1. */
16622 #endif /* Word 0 - End */
16623     } s;
16624     /* struct bdk_ap_ich_vseir_el2_s cn; */
16625 };
16626 typedef union bdk_ap_ich_vseir_el2 bdk_ap_ich_vseir_el2_t;
16627 
16628 #define BDK_AP_ICH_VSEIR_EL2 BDK_AP_ICH_VSEIR_EL2_FUNC()
16629 static inline uint64_t BDK_AP_ICH_VSEIR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_VSEIR_EL2_FUNC(void)16630 static inline uint64_t BDK_AP_ICH_VSEIR_EL2_FUNC(void)
16631 {
16632     if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
16633         return 0x3040c090400ll;
16634     __bdk_csr_fatal("AP_ICH_VSEIR_EL2", 0, 0, 0, 0, 0);
16635 }
16636 
16637 #define typedef_BDK_AP_ICH_VSEIR_EL2 bdk_ap_ich_vseir_el2_t
16638 #define bustype_BDK_AP_ICH_VSEIR_EL2 BDK_CSR_TYPE_SYSREG
16639 #define basename_BDK_AP_ICH_VSEIR_EL2 "AP_ICH_VSEIR_EL2"
16640 #define busnum_BDK_AP_ICH_VSEIR_EL2 0
16641 #define arguments_BDK_AP_ICH_VSEIR_EL2 -1,-1,-1,-1
16642 
16643 /**
16644  * Register (SYSREG) ap_ich_vtr_el2
16645  *
16646  * AP Interrupt Controller VGIC Type Register
16647  * Describes the number of implemented virtual priority bits and
16648  *     List registers.
16649  */
16650 union bdk_ap_ich_vtr_el2
16651 {
16652     uint32_t u;
16653     struct bdk_ap_ich_vtr_el2_s
16654     {
16655 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16656         uint32_t pribits               : 3;  /**< [ 31: 29](RO) The number of virtual priority bits implemented, minus one. */
16657         uint32_t prebits               : 3;  /**< [ 28: 26](RO) The number of virtual preemption bits implemented, minus one. */
16658         uint32_t idbits                : 3;  /**< [ 25: 23](RO) The number of virtual interrupt identifier bits supported:
16659                                                                  All other values are reserved.
16660                                                                  0x0 = 16 bits.
16661                                                                  0x1 = 24 bits. */
16662         uint32_t seis                  : 1;  /**< [ 22: 22](RO) SEI Support. Indicates whether the virtual CPU interface
16663                                                                      supports generation of SEIs:
16664                                                                  Virtual system errors may still be generated by writing to
16665                                                                      AP_ICH_VSEIR_EL2 regardless of the value of this field.
16666                                                                  0 = The virtual CPU interface logic does not support generation of
16667                                                                      SEIs.
16668                                                                  1 = The virtual CPU interface logic supports generation of SEIs. */
16669         uint32_t a3v                   : 1;  /**< [ 21: 21](RO) Affinity 3 Valid.
16670                                                                  0 = The virtual CPU interface logic only supports zero values of
16671                                                                      Affinity 3 in SGI generation system registers.
16672                                                                  1 = The virtual CPU interface logic supports nonzero values of
16673                                                                      Affinity 3 in SGI generation system registers. */
16674         uint32_t reserved_20           : 1;
16675         uint32_t tds                   : 1;  /**< [ 19: 19](RO) Separate trapping of nonsecure EL1 writes supported.
16676                                                                  0 = Implementation does not support CIM()_ICH_HCR_EL2[TDIR].
16677                                                                  1 = Implementation supports CIM()_ICH_HCR_EL2[TDIR]. */
16678         uint32_t reserved_5_18         : 14;
16679         uint32_t listregs              : 5;  /**< [  4:  0](RO) The number of implemented List registers, minus one. */
16680 #else /* Word 0 - Little Endian */
16681         uint32_t listregs              : 5;  /**< [  4:  0](RO) The number of implemented List registers, minus one. */
16682         uint32_t reserved_5_18         : 14;
16683         uint32_t tds                   : 1;  /**< [ 19: 19](RO) Separate trapping of nonsecure EL1 writes supported.
16684                                                                  0 = Implementation does not support CIM()_ICH_HCR_EL2[TDIR].
16685                                                                  1 = Implementation supports CIM()_ICH_HCR_EL2[TDIR]. */
16686         uint32_t reserved_20           : 1;
16687         uint32_t a3v                   : 1;  /**< [ 21: 21](RO) Affinity 3 Valid.
16688                                                                  0 = The virtual CPU interface logic only supports zero values of
16689                                                                      Affinity 3 in SGI generation system registers.
16690                                                                  1 = The virtual CPU interface logic supports nonzero values of
16691                                                                      Affinity 3 in SGI generation system registers. */
16692         uint32_t seis                  : 1;  /**< [ 22: 22](RO) SEI Support. Indicates whether the virtual CPU interface
16693                                                                      supports generation of SEIs:
16694                                                                  Virtual system errors may still be generated by writing to
16695                                                                      AP_ICH_VSEIR_EL2 regardless of the value of this field.
16696                                                                  0 = The virtual CPU interface logic does not support generation of
16697                                                                      SEIs.
16698                                                                  1 = The virtual CPU interface logic supports generation of SEIs. */
16699         uint32_t idbits                : 3;  /**< [ 25: 23](RO) The number of virtual interrupt identifier bits supported:
16700                                                                  All other values are reserved.
16701                                                                  0x0 = 16 bits.
16702                                                                  0x1 = 24 bits. */
16703         uint32_t prebits               : 3;  /**< [ 28: 26](RO) The number of virtual preemption bits implemented, minus one. */
16704         uint32_t pribits               : 3;  /**< [ 31: 29](RO) The number of virtual priority bits implemented, minus one. */
16705 #endif /* Word 0 - End */
16706     } s;
16707     struct bdk_ap_ich_vtr_el2_cn8
16708     {
16709 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16710         uint32_t pribits               : 3;  /**< [ 31: 29](RO) The number of virtual priority bits implemented, minus one. */
16711         uint32_t prebits               : 3;  /**< [ 28: 26](RO) The number of virtual preemption bits implemented, minus one. */
16712         uint32_t idbits                : 3;  /**< [ 25: 23](RO) The number of virtual interrupt identifier bits supported:
16713                                                                  All other values are reserved.
16714                                                                  0x0 = 16 bits.
16715                                                                  0x1 = 24 bits. */
16716         uint32_t seis                  : 1;  /**< [ 22: 22](RO) SEI Support. Indicates whether the virtual CPU interface
16717                                                                      supports generation of SEIs:
16718                                                                  Virtual system errors may still be generated by writing to
16719                                                                      AP_ICH_VSEIR_EL2 regardless of the value of this field.
16720                                                                  0 = The virtual CPU interface logic does not support generation of
16721                                                                      SEIs.
16722                                                                  1 = The virtual CPU interface logic supports generation of SEIs. */
16723         uint32_t a3v                   : 1;  /**< [ 21: 21](RO) Affinity 3 Valid.
16724                                                                  0 = The virtual CPU interface logic only supports zero values of
16725                                                                      Affinity 3 in SGI generation system registers.
16726                                                                  1 = The virtual CPU interface logic supports nonzero values of
16727                                                                      Affinity 3 in SGI generation system registers. */
16728         uint32_t reserved_5_20         : 16;
16729         uint32_t listregs              : 5;  /**< [  4:  0](RO) The number of implemented List registers, minus one. */
16730 #else /* Word 0 - Little Endian */
16731         uint32_t listregs              : 5;  /**< [  4:  0](RO) The number of implemented List registers, minus one. */
16732         uint32_t reserved_5_20         : 16;
16733         uint32_t a3v                   : 1;  /**< [ 21: 21](RO) Affinity 3 Valid.
16734                                                                  0 = The virtual CPU interface logic only supports zero values of
16735                                                                      Affinity 3 in SGI generation system registers.
16736                                                                  1 = The virtual CPU interface logic supports nonzero values of
16737                                                                      Affinity 3 in SGI generation system registers. */
16738         uint32_t seis                  : 1;  /**< [ 22: 22](RO) SEI Support. Indicates whether the virtual CPU interface
16739                                                                      supports generation of SEIs:
16740                                                                  Virtual system errors may still be generated by writing to
16741                                                                      AP_ICH_VSEIR_EL2 regardless of the value of this field.
16742                                                                  0 = The virtual CPU interface logic does not support generation of
16743                                                                      SEIs.
16744                                                                  1 = The virtual CPU interface logic supports generation of SEIs. */
16745         uint32_t idbits                : 3;  /**< [ 25: 23](RO) The number of virtual interrupt identifier bits supported:
16746                                                                  All other values are reserved.
16747                                                                  0x0 = 16 bits.
16748                                                                  0x1 = 24 bits. */
16749         uint32_t prebits               : 3;  /**< [ 28: 26](RO) The number of virtual preemption bits implemented, minus one. */
16750         uint32_t pribits               : 3;  /**< [ 31: 29](RO) The number of virtual priority bits implemented, minus one. */
16751 #endif /* Word 0 - End */
16752     } cn8;
16753     struct bdk_ap_ich_vtr_el2_cn9
16754     {
16755 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16756         uint32_t pribits               : 3;  /**< [ 31: 29](RO) The number of virtual priority bits implemented, minus one. */
16757         uint32_t prebits               : 3;  /**< [ 28: 26](RO) The number of virtual preemption bits implemented, minus one. */
16758         uint32_t idbits                : 3;  /**< [ 25: 23](RO) The number of virtual interrupt identifier bits supported:
16759                                                                  All other values are reserved.
16760                                                                  0x0 = 16 bits.
16761                                                                  0x1 = 24 bits. */
16762         uint32_t seis                  : 1;  /**< [ 22: 22](RO) SEI Support. Indicates whether the virtual CPU interface
16763                                                                      supports generation of SEIs:
16764                                                                  0 = The virtual CPU interface logic does not support generation of
16765                                                                      SEIs.
16766                                                                  1 = The virtual CPU interface logic supports generation of SEIs. */
16767         uint32_t a3v                   : 1;  /**< [ 21: 21](RO) Affinity 3 Valid.
16768                                                                  0 = The virtual CPU interface logic only supports zero values of
16769                                                                      Affinity 3 in SGI generation system registers.
16770                                                                  1 = The virtual CPU interface logic supports nonzero values of
16771                                                                      Affinity 3 in SGI generation system registers. */
16772         uint32_t reserved_20           : 1;
16773         uint32_t tds                   : 1;  /**< [ 19: 19](RO) Separate trapping of nonsecure EL1 writes supported.
16774                                                                  0 = Implementation does not support CIM()_ICH_HCR_EL2[TDIR].
16775                                                                  1 = Implementation supports CIM()_ICH_HCR_EL2[TDIR]. */
16776         uint32_t reserved_5_18         : 14;
16777         uint32_t listregs              : 5;  /**< [  4:  0](RO) The number of implemented List registers, minus one. */
16778 #else /* Word 0 - Little Endian */
16779         uint32_t listregs              : 5;  /**< [  4:  0](RO) The number of implemented List registers, minus one. */
16780         uint32_t reserved_5_18         : 14;
16781         uint32_t tds                   : 1;  /**< [ 19: 19](RO) Separate trapping of nonsecure EL1 writes supported.
16782                                                                  0 = Implementation does not support CIM()_ICH_HCR_EL2[TDIR].
16783                                                                  1 = Implementation supports CIM()_ICH_HCR_EL2[TDIR]. */
16784         uint32_t reserved_20           : 1;
16785         uint32_t a3v                   : 1;  /**< [ 21: 21](RO) Affinity 3 Valid.
16786                                                                  0 = The virtual CPU interface logic only supports zero values of
16787                                                                      Affinity 3 in SGI generation system registers.
16788                                                                  1 = The virtual CPU interface logic supports nonzero values of
16789                                                                      Affinity 3 in SGI generation system registers. */
16790         uint32_t seis                  : 1;  /**< [ 22: 22](RO) SEI Support. Indicates whether the virtual CPU interface
16791                                                                      supports generation of SEIs:
16792                                                                  0 = The virtual CPU interface logic does not support generation of
16793                                                                      SEIs.
16794                                                                  1 = The virtual CPU interface logic supports generation of SEIs. */
16795         uint32_t idbits                : 3;  /**< [ 25: 23](RO) The number of virtual interrupt identifier bits supported:
16796                                                                  All other values are reserved.
16797                                                                  0x0 = 16 bits.
16798                                                                  0x1 = 24 bits. */
16799         uint32_t prebits               : 3;  /**< [ 28: 26](RO) The number of virtual preemption bits implemented, minus one. */
16800         uint32_t pribits               : 3;  /**< [ 31: 29](RO) The number of virtual priority bits implemented, minus one. */
16801 #endif /* Word 0 - End */
16802     } cn9;
16803 };
16804 typedef union bdk_ap_ich_vtr_el2 bdk_ap_ich_vtr_el2_t;
16805 
16806 #define BDK_AP_ICH_VTR_EL2 BDK_AP_ICH_VTR_EL2_FUNC()
16807 static inline uint64_t BDK_AP_ICH_VTR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ICH_VTR_EL2_FUNC(void)16808 static inline uint64_t BDK_AP_ICH_VTR_EL2_FUNC(void)
16809 {
16810     return 0x3040c0b0100ll;
16811 }
16812 
16813 #define typedef_BDK_AP_ICH_VTR_EL2 bdk_ap_ich_vtr_el2_t
16814 #define bustype_BDK_AP_ICH_VTR_EL2 BDK_CSR_TYPE_SYSREG
16815 #define basename_BDK_AP_ICH_VTR_EL2 "AP_ICH_VTR_EL2"
16816 #define busnum_BDK_AP_ICH_VTR_EL2 0
16817 #define arguments_BDK_AP_ICH_VTR_EL2 -1,-1,-1,-1
16818 
16819 /**
16820  * Register (SYSREG) ap_id_aa64afr#_el1_res0
16821  *
16822  * INTERNAL: AP AArch64 Reserved Register
16823  *
16824  * Reserved for future expansion of information about the
16825  *     implementation defined features of the processor in AArch64.
16826  *     ARM doesn't actually assign a name to these registers, so
16827  *     for CNXXXX a made up one.
16828  */
16829 union bdk_ap_id_aa64afrx_el1_res0
16830 {
16831     uint64_t u;
16832     struct bdk_ap_id_aa64afrx_el1_res0_s
16833     {
16834 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16835         uint64_t reserved_0_63         : 64;
16836 #else /* Word 0 - Little Endian */
16837         uint64_t reserved_0_63         : 64;
16838 #endif /* Word 0 - End */
16839     } s;
16840     /* struct bdk_ap_id_aa64afrx_el1_res0_s cn; */
16841 };
16842 typedef union bdk_ap_id_aa64afrx_el1_res0 bdk_ap_id_aa64afrx_el1_res0_t;
16843 
16844 static inline uint64_t BDK_AP_ID_AA64AFRX_EL1_RES0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64AFRX_EL1_RES0(unsigned long a)16845 static inline uint64_t BDK_AP_ID_AA64AFRX_EL1_RES0(unsigned long a)
16846 {
16847     if ((a>=2)&&(a<=3))
16848         return 0x30000050400ll + 0x100ll * ((a) & 0x3);
16849     __bdk_csr_fatal("AP_ID_AA64AFRX_EL1_RES0", 1, a, 0, 0, 0);
16850 }
16851 
16852 #define typedef_BDK_AP_ID_AA64AFRX_EL1_RES0(a) bdk_ap_id_aa64afrx_el1_res0_t
16853 #define bustype_BDK_AP_ID_AA64AFRX_EL1_RES0(a) BDK_CSR_TYPE_SYSREG
16854 #define basename_BDK_AP_ID_AA64AFRX_EL1_RES0(a) "AP_ID_AA64AFRX_EL1_RES0"
16855 #define busnum_BDK_AP_ID_AA64AFRX_EL1_RES0(a) (a)
16856 #define arguments_BDK_AP_ID_AA64AFRX_EL1_RES0(a) (a),-1,-1,-1
16857 
16858 /**
16859  * Register (SYSREG) ap_id_aa64afr0_el1
16860  *
16861  * AP AArch64 Auxiliary Feature Register 0
16862  * Provides information about the implementation defined features
16863  *     of the processor in AArch64.
16864  */
16865 union bdk_ap_id_aa64afr0_el1
16866 {
16867     uint64_t u;
16868     struct bdk_ap_id_aa64afr0_el1_s
16869     {
16870 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16871         uint64_t reserved_0_63         : 64;
16872 #else /* Word 0 - Little Endian */
16873         uint64_t reserved_0_63         : 64;
16874 #endif /* Word 0 - End */
16875     } s;
16876     /* struct bdk_ap_id_aa64afr0_el1_s cn; */
16877 };
16878 typedef union bdk_ap_id_aa64afr0_el1 bdk_ap_id_aa64afr0_el1_t;
16879 
16880 #define BDK_AP_ID_AA64AFR0_EL1 BDK_AP_ID_AA64AFR0_EL1_FUNC()
16881 static inline uint64_t BDK_AP_ID_AA64AFR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64AFR0_EL1_FUNC(void)16882 static inline uint64_t BDK_AP_ID_AA64AFR0_EL1_FUNC(void)
16883 {
16884     return 0x30000050400ll;
16885 }
16886 
16887 #define typedef_BDK_AP_ID_AA64AFR0_EL1 bdk_ap_id_aa64afr0_el1_t
16888 #define bustype_BDK_AP_ID_AA64AFR0_EL1 BDK_CSR_TYPE_SYSREG
16889 #define basename_BDK_AP_ID_AA64AFR0_EL1 "AP_ID_AA64AFR0_EL1"
16890 #define busnum_BDK_AP_ID_AA64AFR0_EL1 0
16891 #define arguments_BDK_AP_ID_AA64AFR0_EL1 -1,-1,-1,-1
16892 
16893 /**
16894  * Register (SYSREG) ap_id_aa64afr1_el1
16895  *
16896  * AP AArch64 Auxiliary Feature Register 1
16897  * Reserved for future expansion of information about the
16898  *     implementation defined features of the processor in AArch64.
16899  */
16900 union bdk_ap_id_aa64afr1_el1
16901 {
16902     uint64_t u;
16903     struct bdk_ap_id_aa64afr1_el1_s
16904     {
16905 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16906         uint64_t reserved_0_63         : 64;
16907 #else /* Word 0 - Little Endian */
16908         uint64_t reserved_0_63         : 64;
16909 #endif /* Word 0 - End */
16910     } s;
16911     /* struct bdk_ap_id_aa64afr1_el1_s cn; */
16912 };
16913 typedef union bdk_ap_id_aa64afr1_el1 bdk_ap_id_aa64afr1_el1_t;
16914 
16915 #define BDK_AP_ID_AA64AFR1_EL1 BDK_AP_ID_AA64AFR1_EL1_FUNC()
16916 static inline uint64_t BDK_AP_ID_AA64AFR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64AFR1_EL1_FUNC(void)16917 static inline uint64_t BDK_AP_ID_AA64AFR1_EL1_FUNC(void)
16918 {
16919     return 0x30000050500ll;
16920 }
16921 
16922 #define typedef_BDK_AP_ID_AA64AFR1_EL1 bdk_ap_id_aa64afr1_el1_t
16923 #define bustype_BDK_AP_ID_AA64AFR1_EL1 BDK_CSR_TYPE_SYSREG
16924 #define basename_BDK_AP_ID_AA64AFR1_EL1 "AP_ID_AA64AFR1_EL1"
16925 #define busnum_BDK_AP_ID_AA64AFR1_EL1 0
16926 #define arguments_BDK_AP_ID_AA64AFR1_EL1 -1,-1,-1,-1
16927 
16928 /**
16929  * Register (SYSREG) ap_id_aa64dfr#_el1_res0
16930  *
16931  * INTERNAL: AP AArch64 Reserved Register
16932  *
16933  * Reserved for future expansion of top level information about
16934  *     the debug system in AArch64. ARM doesn't actually assign
16935  *     a name to these registers, so CNXXXX made up one.
16936  */
16937 union bdk_ap_id_aa64dfrx_el1_res0
16938 {
16939     uint64_t u;
16940     struct bdk_ap_id_aa64dfrx_el1_res0_s
16941     {
16942 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16943         uint64_t reserved_0_63         : 64;
16944 #else /* Word 0 - Little Endian */
16945         uint64_t reserved_0_63         : 64;
16946 #endif /* Word 0 - End */
16947     } s;
16948     /* struct bdk_ap_id_aa64dfrx_el1_res0_s cn; */
16949 };
16950 typedef union bdk_ap_id_aa64dfrx_el1_res0 bdk_ap_id_aa64dfrx_el1_res0_t;
16951 
16952 static inline uint64_t BDK_AP_ID_AA64DFRX_EL1_RES0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64DFRX_EL1_RES0(unsigned long a)16953 static inline uint64_t BDK_AP_ID_AA64DFRX_EL1_RES0(unsigned long a)
16954 {
16955     if ((a>=2)&&(a<=3))
16956         return 0x30000050000ll + 0x100ll * ((a) & 0x3);
16957     __bdk_csr_fatal("AP_ID_AA64DFRX_EL1_RES0", 1, a, 0, 0, 0);
16958 }
16959 
16960 #define typedef_BDK_AP_ID_AA64DFRX_EL1_RES0(a) bdk_ap_id_aa64dfrx_el1_res0_t
16961 #define bustype_BDK_AP_ID_AA64DFRX_EL1_RES0(a) BDK_CSR_TYPE_SYSREG
16962 #define basename_BDK_AP_ID_AA64DFRX_EL1_RES0(a) "AP_ID_AA64DFRX_EL1_RES0"
16963 #define busnum_BDK_AP_ID_AA64DFRX_EL1_RES0(a) (a)
16964 #define arguments_BDK_AP_ID_AA64DFRX_EL1_RES0(a) (a),-1,-1,-1
16965 
16966 /**
16967  * Register (SYSREG) ap_id_aa64dfr0_el1
16968  *
16969  * AP AArch64 Debug Feature Register 0
16970  * This register provides top level information about the debug system in AArch64.
16971  */
16972 union bdk_ap_id_aa64dfr0_el1
16973 {
16974     uint64_t u;
16975     struct bdk_ap_id_aa64dfr0_el1_s
16976     {
16977 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
16978         uint64_t reserved_36_63        : 28;
16979         uint64_t pmsver                : 4;  /**< [ 35: 32](RO) Statistical profiling extension version.
16980                                                                  0x0 = No statistical profiling extension.
16981                                                                  0x1 = Version 1 of the statistical profiling extension present.
16982 
16983                                                                  All other values are reserved. Reserved values might be defined in a future
16984                                                                  version of the architecture. */
16985         uint64_t ctx_cmps              : 4;  /**< [ 31: 28](RO) Number of breakpoints that are context-aware, minus 1. These
16986                                                                      are the highest numbered breakpoints.
16987 
16988                                                                  In CNXXXX all breakpoints are context-aware. */
16989         uint64_t reserved_24_27        : 4;
16990         uint64_t wrps                  : 4;  /**< [ 23: 20](RO) Number of watchpoints, minus 1. The value of 0b0000 is reserved.
16991 
16992                                                                  In CNXXXX 4 watchpoints. */
16993         uint64_t reserved_16_19        : 4;
16994         uint64_t brps                  : 4;  /**< [ 15: 12](RO) Number of breakpoints, minus 1. The value of 0b0000 is reserved.
16995 
16996                                                                  In CNXXXX 6 breakpoints. */
16997         uint64_t pmuver                : 4;  /**< [ 11:  8](RO) Performance Monitors extension version. Indicates whether
16998                                                                      system register interface to Performance Monitors extension is
16999                                                                      implemented.
17000                                                                  All other values are reserved.
17001                                                                  0x0 = Performance Monitors extension system registers not
17002                                                                      implemented.
17003                                                                  0x1 = Performance Monitors extension system registers implemented,
17004                                                                      PMUv3.
17005                                                                  0x4 = v8.1: Performance Monitors extension system registers
17006                                                                      implemented, PMUv3 with 16bit evtCount.
17007                                                                  0xF =  implementation defined form of performance monitors
17008                                                                      supported, PMUv3 not supported.
17009 
17010                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x4, else 0x1. */
17011         uint64_t tracever              : 4;  /**< [  7:  4](RO) Trace extension. Indicates whether system register interface to the trace
17012                                                                  extension is implemented.
17013                                                                  All other values are reserved.
17014                                                                  0x0 = Trace extension system registers not implemented.
17015                                                                  0x1 = Trace extension system registers implemented. */
17016         uint64_t debugver              : 4;  /**< [  3:  0](RO) Debug architecture version. Indicates presence of ARMv8 debug
17017                                                                      architecture.
17018                                                                  All other values are reserved.
17019                                                                  0x6 = ARMv8 debug architecture.
17020                                                                  0x7 = ARMv8.1 debug architecture.
17021                                                                  0x8 = ARMv8.2 debug architecture.
17022 
17023                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x7, else 0x6. */
17024 #else /* Word 0 - Little Endian */
17025         uint64_t debugver              : 4;  /**< [  3:  0](RO) Debug architecture version. Indicates presence of ARMv8 debug
17026                                                                      architecture.
17027                                                                  All other values are reserved.
17028                                                                  0x6 = ARMv8 debug architecture.
17029                                                                  0x7 = ARMv8.1 debug architecture.
17030                                                                  0x8 = ARMv8.2 debug architecture.
17031 
17032                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x7, else 0x6. */
17033         uint64_t tracever              : 4;  /**< [  7:  4](RO) Trace extension. Indicates whether system register interface to the trace
17034                                                                  extension is implemented.
17035                                                                  All other values are reserved.
17036                                                                  0x0 = Trace extension system registers not implemented.
17037                                                                  0x1 = Trace extension system registers implemented. */
17038         uint64_t pmuver                : 4;  /**< [ 11:  8](RO) Performance Monitors extension version. Indicates whether
17039                                                                      system register interface to Performance Monitors extension is
17040                                                                      implemented.
17041                                                                  All other values are reserved.
17042                                                                  0x0 = Performance Monitors extension system registers not
17043                                                                      implemented.
17044                                                                  0x1 = Performance Monitors extension system registers implemented,
17045                                                                      PMUv3.
17046                                                                  0x4 = v8.1: Performance Monitors extension system registers
17047                                                                      implemented, PMUv3 with 16bit evtCount.
17048                                                                  0xF =  implementation defined form of performance monitors
17049                                                                      supported, PMUv3 not supported.
17050 
17051                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x4, else 0x1. */
17052         uint64_t brps                  : 4;  /**< [ 15: 12](RO) Number of breakpoints, minus 1. The value of 0b0000 is reserved.
17053 
17054                                                                  In CNXXXX 6 breakpoints. */
17055         uint64_t reserved_16_19        : 4;
17056         uint64_t wrps                  : 4;  /**< [ 23: 20](RO) Number of watchpoints, minus 1. The value of 0b0000 is reserved.
17057 
17058                                                                  In CNXXXX 4 watchpoints. */
17059         uint64_t reserved_24_27        : 4;
17060         uint64_t ctx_cmps              : 4;  /**< [ 31: 28](RO) Number of breakpoints that are context-aware, minus 1. These
17061                                                                      are the highest numbered breakpoints.
17062 
17063                                                                  In CNXXXX all breakpoints are context-aware. */
17064         uint64_t pmsver                : 4;  /**< [ 35: 32](RO) Statistical profiling extension version.
17065                                                                  0x0 = No statistical profiling extension.
17066                                                                  0x1 = Version 1 of the statistical profiling extension present.
17067 
17068                                                                  All other values are reserved. Reserved values might be defined in a future
17069                                                                  version of the architecture. */
17070         uint64_t reserved_36_63        : 28;
17071 #endif /* Word 0 - End */
17072     } s;
17073     struct bdk_ap_id_aa64dfr0_el1_cn8
17074     {
17075 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17076         uint64_t reserved_32_63        : 32;
17077         uint64_t ctx_cmps              : 4;  /**< [ 31: 28](RO) Number of breakpoints that are context-aware, minus 1. These
17078                                                                      are the highest numbered breakpoints.
17079 
17080                                                                  In CNXXXX all breakpoints are context-aware. */
17081         uint64_t reserved_24_27        : 4;
17082         uint64_t wrps                  : 4;  /**< [ 23: 20](RO) Number of watchpoints, minus 1. The value of 0b0000 is reserved.
17083 
17084                                                                  In CNXXXX 4 watchpoints. */
17085         uint64_t reserved_16_19        : 4;
17086         uint64_t brps                  : 4;  /**< [ 15: 12](RO) Number of breakpoints, minus 1. The value of 0b0000 is reserved.
17087 
17088                                                                  In CNXXXX 6 breakpoints. */
17089         uint64_t pmuver                : 4;  /**< [ 11:  8](RO) Performance Monitors extension version. Indicates whether
17090                                                                      system register interface to Performance Monitors extension is
17091                                                                      implemented.
17092                                                                  All other values are reserved.
17093                                                                  0x0 = Performance Monitors extension system registers not
17094                                                                      implemented.
17095                                                                  0x1 = Performance Monitors extension system registers implemented,
17096                                                                      PMUv3.
17097                                                                  0x4 = v8.1: Performance Monitors extension system registers
17098                                                                      implemented, PMUv3 with 16bit evtCount.
17099                                                                  0xF =  implementation defined form of performance monitors
17100                                                                      supported, PMUv3 not supported.
17101 
17102                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x4, else 0x1. */
17103         uint64_t tracever              : 4;  /**< [  7:  4](RO) Trace extension. Indicates whether system register interface to the trace
17104                                                                  extension is implemented.
17105                                                                  All other values are reserved.
17106                                                                  0x0 = Trace extension system registers not implemented.
17107                                                                  0x1 = Trace extension system registers implemented. */
17108         uint64_t debugver              : 4;  /**< [  3:  0](RO) Debug architecture version. Indicates presence of ARMv8 debug
17109                                                                      architecture.
17110                                                                  All other values are reserved.
17111                                                                  0x6 = ARMv8 debug architecture.
17112                                                                  0x7 = ARMv8.1 debug architecture.
17113                                                                  0x8 = ARMv8.2 debug architecture.
17114 
17115                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x7, else 0x6. */
17116 #else /* Word 0 - Little Endian */
17117         uint64_t debugver              : 4;  /**< [  3:  0](RO) Debug architecture version. Indicates presence of ARMv8 debug
17118                                                                      architecture.
17119                                                                  All other values are reserved.
17120                                                                  0x6 = ARMv8 debug architecture.
17121                                                                  0x7 = ARMv8.1 debug architecture.
17122                                                                  0x8 = ARMv8.2 debug architecture.
17123 
17124                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x7, else 0x6. */
17125         uint64_t tracever              : 4;  /**< [  7:  4](RO) Trace extension. Indicates whether system register interface to the trace
17126                                                                  extension is implemented.
17127                                                                  All other values are reserved.
17128                                                                  0x0 = Trace extension system registers not implemented.
17129                                                                  0x1 = Trace extension system registers implemented. */
17130         uint64_t pmuver                : 4;  /**< [ 11:  8](RO) Performance Monitors extension version. Indicates whether
17131                                                                      system register interface to Performance Monitors extension is
17132                                                                      implemented.
17133                                                                  All other values are reserved.
17134                                                                  0x0 = Performance Monitors extension system registers not
17135                                                                      implemented.
17136                                                                  0x1 = Performance Monitors extension system registers implemented,
17137                                                                      PMUv3.
17138                                                                  0x4 = v8.1: Performance Monitors extension system registers
17139                                                                      implemented, PMUv3 with 16bit evtCount.
17140                                                                  0xF =  implementation defined form of performance monitors
17141                                                                      supported, PMUv3 not supported.
17142 
17143                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x4, else 0x1. */
17144         uint64_t brps                  : 4;  /**< [ 15: 12](RO) Number of breakpoints, minus 1. The value of 0b0000 is reserved.
17145 
17146                                                                  In CNXXXX 6 breakpoints. */
17147         uint64_t reserved_16_19        : 4;
17148         uint64_t wrps                  : 4;  /**< [ 23: 20](RO) Number of watchpoints, minus 1. The value of 0b0000 is reserved.
17149 
17150                                                                  In CNXXXX 4 watchpoints. */
17151         uint64_t reserved_24_27        : 4;
17152         uint64_t ctx_cmps              : 4;  /**< [ 31: 28](RO) Number of breakpoints that are context-aware, minus 1. These
17153                                                                      are the highest numbered breakpoints.
17154 
17155                                                                  In CNXXXX all breakpoints are context-aware. */
17156         uint64_t reserved_32_63        : 32;
17157 #endif /* Word 0 - End */
17158     } cn8;
17159     /* struct bdk_ap_id_aa64dfr0_el1_s cn9; */
17160 };
17161 typedef union bdk_ap_id_aa64dfr0_el1 bdk_ap_id_aa64dfr0_el1_t;
17162 
17163 #define BDK_AP_ID_AA64DFR0_EL1 BDK_AP_ID_AA64DFR0_EL1_FUNC()
17164 static inline uint64_t BDK_AP_ID_AA64DFR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64DFR0_EL1_FUNC(void)17165 static inline uint64_t BDK_AP_ID_AA64DFR0_EL1_FUNC(void)
17166 {
17167     return 0x30000050000ll;
17168 }
17169 
17170 #define typedef_BDK_AP_ID_AA64DFR0_EL1 bdk_ap_id_aa64dfr0_el1_t
17171 #define bustype_BDK_AP_ID_AA64DFR0_EL1 BDK_CSR_TYPE_SYSREG
17172 #define basename_BDK_AP_ID_AA64DFR0_EL1 "AP_ID_AA64DFR0_EL1"
17173 #define busnum_BDK_AP_ID_AA64DFR0_EL1 0
17174 #define arguments_BDK_AP_ID_AA64DFR0_EL1 -1,-1,-1,-1
17175 
17176 /**
17177  * Register (SYSREG) ap_id_aa64dfr1_el1
17178  *
17179  * AP AArch64 Debug Feature Register 1
17180  * Reserved for future expansion of top level information about
17181  *     the debug system in AArch64.
17182  */
17183 union bdk_ap_id_aa64dfr1_el1
17184 {
17185     uint64_t u;
17186     struct bdk_ap_id_aa64dfr1_el1_s
17187     {
17188 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17189         uint64_t reserved_0_63         : 64;
17190 #else /* Word 0 - Little Endian */
17191         uint64_t reserved_0_63         : 64;
17192 #endif /* Word 0 - End */
17193     } s;
17194     /* struct bdk_ap_id_aa64dfr1_el1_s cn; */
17195 };
17196 typedef union bdk_ap_id_aa64dfr1_el1 bdk_ap_id_aa64dfr1_el1_t;
17197 
17198 #define BDK_AP_ID_AA64DFR1_EL1 BDK_AP_ID_AA64DFR1_EL1_FUNC()
17199 static inline uint64_t BDK_AP_ID_AA64DFR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64DFR1_EL1_FUNC(void)17200 static inline uint64_t BDK_AP_ID_AA64DFR1_EL1_FUNC(void)
17201 {
17202     return 0x30000050100ll;
17203 }
17204 
17205 #define typedef_BDK_AP_ID_AA64DFR1_EL1 bdk_ap_id_aa64dfr1_el1_t
17206 #define bustype_BDK_AP_ID_AA64DFR1_EL1 BDK_CSR_TYPE_SYSREG
17207 #define basename_BDK_AP_ID_AA64DFR1_EL1 "AP_ID_AA64DFR1_EL1"
17208 #define busnum_BDK_AP_ID_AA64DFR1_EL1 0
17209 #define arguments_BDK_AP_ID_AA64DFR1_EL1 -1,-1,-1,-1
17210 
17211 /**
17212  * Register (SYSREG) ap_id_aa64isar#_el1_res0
17213  *
17214  * INTERNAL: AP AArch64 Reserved Register
17215  *
17216  * Reserved for future expansion of the information about the
17217  *     instruction sets implemented by the processor in AArch64.
17218  *     ARM doesn't actually assign a name to these registers, so
17219  *     CNXXXX made up one.
17220  */
17221 union bdk_ap_id_aa64isarx_el1_res0
17222 {
17223     uint64_t u;
17224     struct bdk_ap_id_aa64isarx_el1_res0_s
17225     {
17226 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17227         uint64_t reserved_0_63         : 64;
17228 #else /* Word 0 - Little Endian */
17229         uint64_t reserved_0_63         : 64;
17230 #endif /* Word 0 - End */
17231     } s;
17232     /* struct bdk_ap_id_aa64isarx_el1_res0_s cn; */
17233 };
17234 typedef union bdk_ap_id_aa64isarx_el1_res0 bdk_ap_id_aa64isarx_el1_res0_t;
17235 
17236 static inline uint64_t BDK_AP_ID_AA64ISARX_EL1_RES0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64ISARX_EL1_RES0(unsigned long a)17237 static inline uint64_t BDK_AP_ID_AA64ISARX_EL1_RES0(unsigned long a)
17238 {
17239     if ((a>=2)&&(a<=7))
17240         return 0x30000060000ll + 0x100ll * ((a) & 0x7);
17241     __bdk_csr_fatal("AP_ID_AA64ISARX_EL1_RES0", 1, a, 0, 0, 0);
17242 }
17243 
17244 #define typedef_BDK_AP_ID_AA64ISARX_EL1_RES0(a) bdk_ap_id_aa64isarx_el1_res0_t
17245 #define bustype_BDK_AP_ID_AA64ISARX_EL1_RES0(a) BDK_CSR_TYPE_SYSREG
17246 #define basename_BDK_AP_ID_AA64ISARX_EL1_RES0(a) "AP_ID_AA64ISARX_EL1_RES0"
17247 #define busnum_BDK_AP_ID_AA64ISARX_EL1_RES0(a) (a)
17248 #define arguments_BDK_AP_ID_AA64ISARX_EL1_RES0(a) (a),-1,-1,-1
17249 
17250 /**
17251  * Register (SYSREG) ap_id_aa64isar0_el1
17252  *
17253  * AP AArch64 Instruction Set Attribute Register 0
17254  * This register provides information about the instructions implemented by the
17255  * processor in AArch64.
17256  */
17257 union bdk_ap_id_aa64isar0_el1
17258 {
17259     uint64_t u;
17260     struct bdk_ap_id_aa64isar0_el1_s
17261     {
17262 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17263         uint64_t reserved_32_63        : 32;
17264         uint64_t sqrdml                : 4;  /**< [ 31: 28](RO) 0x0 = SQRDMLAH and SQRDMLSH not supported in AArch64.
17265                                                                  0x1 = SQRDMLAH and SQRDMLSH supported in AArch64.
17266                                                                  All other values reserved.
17267 
17268                                                                  In CNXXXX, 0x1 if AP_CVMCTL_EL1[ENABLE_V81] is set, else 0x0. */
17269         uint64_t reserved_24_27        : 4;
17270         uint64_t atomic                : 4;  /**< [ 23: 20](RO) Atomic instructions in AArch64
17271                                                                      0x0 = No Atomic instructions implemented.
17272                                                                      0x1 = Reserved.
17273                                                                      0x2 = LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, CASP,
17274                                                                          SWP instructions implemented.
17275 
17276                                                                  For CNXXXX, 0x2. */
17277         uint64_t crc32                 : 4;  /**< [ 19: 16](RO) CRC32 instructions in AArch64.
17278                                                                  All other values are reserved.
17279                                                                  This field must have the same value as ID_ISAR5[CRC32]. The
17280                                                                      architecture requires that if CRC32 is supported in one
17281                                                                      Execution state, it must be supported in both Execution
17282                                                                      states.
17283                                                                  0x0 = No CRC32 instructions implemented.
17284                                                                  0x1 = CRC32B, CRC32H, CRC32W, CRC32X, CRC32CB, CRC32CH, CRC32CW, and
17285                                                                      CRC32CX instructions implemented.
17286 
17287                                                                  In CNXXXX, supported unless crypto disabled by MIO_FUS_DAT2[NOCRYPTO]. */
17288         uint64_t sha2                  : 4;  /**< [ 15: 12](RO) SHA2 instructions in AArch64.
17289                                                                  All other values are reserved.
17290                                                                  0x0 = No SHA2 instructions implemented.
17291                                                                  0x1 = SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions
17292                                                                      implemented.
17293 
17294                                                                  In CNXXXX, supported unless crypto disabled by MIO_FUS_DAT2[NOCRYPTO]. */
17295         uint64_t sha1                  : 4;  /**< [ 11:  8](RO) SHA1 instructions in AArch64.
17296                                                                  All other values are reserved.
17297                                                                  0x0 = No SHA1 instructions implemented.
17298                                                                  0x1 = SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions
17299                                                                      implemented.
17300 
17301                                                                  In CNXXXX, supported unless crypto disabled by MIO_FUS_DAT2[NOCRYPTO]. */
17302         uint64_t aes                   : 4;  /**< [  7:  4](RO) AES instructions in AArch64.
17303                                                                  0x0 = No AES instructions implemented.
17304                                                                  0x1 = AESE, AESD, AESMC, and AESIMC instructions implemented.
17305                                                                  0x2 = As for 0x1, plus PMULL/PMULL2 instructions operate on
17306                                                                  64-bit data quantities.
17307 
17308                                                                  In CNXXXX, supported with PMULL/PMULL2. */
17309         uint64_t reserved_0_3          : 4;
17310 #else /* Word 0 - Little Endian */
17311         uint64_t reserved_0_3          : 4;
17312         uint64_t aes                   : 4;  /**< [  7:  4](RO) AES instructions in AArch64.
17313                                                                  0x0 = No AES instructions implemented.
17314                                                                  0x1 = AESE, AESD, AESMC, and AESIMC instructions implemented.
17315                                                                  0x2 = As for 0x1, plus PMULL/PMULL2 instructions operate on
17316                                                                  64-bit data quantities.
17317 
17318                                                                  In CNXXXX, supported with PMULL/PMULL2. */
17319         uint64_t sha1                  : 4;  /**< [ 11:  8](RO) SHA1 instructions in AArch64.
17320                                                                  All other values are reserved.
17321                                                                  0x0 = No SHA1 instructions implemented.
17322                                                                  0x1 = SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions
17323                                                                      implemented.
17324 
17325                                                                  In CNXXXX, supported unless crypto disabled by MIO_FUS_DAT2[NOCRYPTO]. */
17326         uint64_t sha2                  : 4;  /**< [ 15: 12](RO) SHA2 instructions in AArch64.
17327                                                                  All other values are reserved.
17328                                                                  0x0 = No SHA2 instructions implemented.
17329                                                                  0x1 = SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions
17330                                                                      implemented.
17331 
17332                                                                  In CNXXXX, supported unless crypto disabled by MIO_FUS_DAT2[NOCRYPTO]. */
17333         uint64_t crc32                 : 4;  /**< [ 19: 16](RO) CRC32 instructions in AArch64.
17334                                                                  All other values are reserved.
17335                                                                  This field must have the same value as ID_ISAR5[CRC32]. The
17336                                                                      architecture requires that if CRC32 is supported in one
17337                                                                      Execution state, it must be supported in both Execution
17338                                                                      states.
17339                                                                  0x0 = No CRC32 instructions implemented.
17340                                                                  0x1 = CRC32B, CRC32H, CRC32W, CRC32X, CRC32CB, CRC32CH, CRC32CW, and
17341                                                                      CRC32CX instructions implemented.
17342 
17343                                                                  In CNXXXX, supported unless crypto disabled by MIO_FUS_DAT2[NOCRYPTO]. */
17344         uint64_t atomic                : 4;  /**< [ 23: 20](RO) Atomic instructions in AArch64
17345                                                                      0x0 = No Atomic instructions implemented.
17346                                                                      0x1 = Reserved.
17347                                                                      0x2 = LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, CASP,
17348                                                                          SWP instructions implemented.
17349 
17350                                                                  For CNXXXX, 0x2. */
17351         uint64_t reserved_24_27        : 4;
17352         uint64_t sqrdml                : 4;  /**< [ 31: 28](RO) 0x0 = SQRDMLAH and SQRDMLSH not supported in AArch64.
17353                                                                  0x1 = SQRDMLAH and SQRDMLSH supported in AArch64.
17354                                                                  All other values reserved.
17355 
17356                                                                  In CNXXXX, 0x1 if AP_CVMCTL_EL1[ENABLE_V81] is set, else 0x0. */
17357         uint64_t reserved_32_63        : 32;
17358 #endif /* Word 0 - End */
17359     } s;
17360     /* struct bdk_ap_id_aa64isar0_el1_s cn; */
17361 };
17362 typedef union bdk_ap_id_aa64isar0_el1 bdk_ap_id_aa64isar0_el1_t;
17363 
17364 #define BDK_AP_ID_AA64ISAR0_EL1 BDK_AP_ID_AA64ISAR0_EL1_FUNC()
17365 static inline uint64_t BDK_AP_ID_AA64ISAR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64ISAR0_EL1_FUNC(void)17366 static inline uint64_t BDK_AP_ID_AA64ISAR0_EL1_FUNC(void)
17367 {
17368     return 0x30000060000ll;
17369 }
17370 
17371 #define typedef_BDK_AP_ID_AA64ISAR0_EL1 bdk_ap_id_aa64isar0_el1_t
17372 #define bustype_BDK_AP_ID_AA64ISAR0_EL1 BDK_CSR_TYPE_SYSREG
17373 #define basename_BDK_AP_ID_AA64ISAR0_EL1 "AP_ID_AA64ISAR0_EL1"
17374 #define busnum_BDK_AP_ID_AA64ISAR0_EL1 0
17375 #define arguments_BDK_AP_ID_AA64ISAR0_EL1 -1,-1,-1,-1
17376 
17377 /**
17378  * Register (SYSREG) ap_id_aa64isar1_el1
17379  *
17380  * AP AArch64 Instruction Set Attribute Register 1
17381  * Reserved for future expansion of the information about the
17382  *     instruction sets implemented by the processor in AArch64.
17383  */
17384 union bdk_ap_id_aa64isar1_el1
17385 {
17386     uint64_t u;
17387     struct bdk_ap_id_aa64isar1_el1_s
17388     {
17389 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17390         uint64_t reserved_4_63         : 60;
17391         uint64_t dpb                   : 4;  /**< [  3:  0](RO) 0x0 = DC CVAP not supported in AArch64.
17392                                                                  0x1 = DC CVAP supported in AArch64.
17393 
17394                                                                  All other values reserved. */
17395 #else /* Word 0 - Little Endian */
17396         uint64_t dpb                   : 4;  /**< [  3:  0](RO) 0x0 = DC CVAP not supported in AArch64.
17397                                                                  0x1 = DC CVAP supported in AArch64.
17398 
17399                                                                  All other values reserved. */
17400         uint64_t reserved_4_63         : 60;
17401 #endif /* Word 0 - End */
17402     } s;
17403     struct bdk_ap_id_aa64isar1_el1_cn8
17404     {
17405 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17406         uint64_t reserved_0_63         : 64;
17407 #else /* Word 0 - Little Endian */
17408         uint64_t reserved_0_63         : 64;
17409 #endif /* Word 0 - End */
17410     } cn8;
17411     /* struct bdk_ap_id_aa64isar1_el1_s cn9; */
17412 };
17413 typedef union bdk_ap_id_aa64isar1_el1 bdk_ap_id_aa64isar1_el1_t;
17414 
17415 #define BDK_AP_ID_AA64ISAR1_EL1 BDK_AP_ID_AA64ISAR1_EL1_FUNC()
17416 static inline uint64_t BDK_AP_ID_AA64ISAR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64ISAR1_EL1_FUNC(void)17417 static inline uint64_t BDK_AP_ID_AA64ISAR1_EL1_FUNC(void)
17418 {
17419     return 0x30000060100ll;
17420 }
17421 
17422 #define typedef_BDK_AP_ID_AA64ISAR1_EL1 bdk_ap_id_aa64isar1_el1_t
17423 #define bustype_BDK_AP_ID_AA64ISAR1_EL1 BDK_CSR_TYPE_SYSREG
17424 #define basename_BDK_AP_ID_AA64ISAR1_EL1 "AP_ID_AA64ISAR1_EL1"
17425 #define busnum_BDK_AP_ID_AA64ISAR1_EL1 0
17426 #define arguments_BDK_AP_ID_AA64ISAR1_EL1 -1,-1,-1,-1
17427 
17428 /**
17429  * Register (SYSREG) ap_id_aa64mmfr#_el1_res0
17430  *
17431  * INTERNAL: AP AArch64 Reserved Register
17432  *
17433  * Reserved for future expansion of the information about the
17434  *     implemented memory model and memory management support in
17435  *     AArch64. ARM doesn't actually assign a name to these
17436  *     registers, so CNXXXX made up one.
17437  */
17438 union bdk_ap_id_aa64mmfrx_el1_res0
17439 {
17440     uint64_t u;
17441     struct bdk_ap_id_aa64mmfrx_el1_res0_s
17442     {
17443 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17444         uint64_t reserved_0_63         : 64;
17445 #else /* Word 0 - Little Endian */
17446         uint64_t reserved_0_63         : 64;
17447 #endif /* Word 0 - End */
17448     } s;
17449     /* struct bdk_ap_id_aa64mmfrx_el1_res0_s cn; */
17450 };
17451 typedef union bdk_ap_id_aa64mmfrx_el1_res0 bdk_ap_id_aa64mmfrx_el1_res0_t;
17452 
17453 static inline uint64_t BDK_AP_ID_AA64MMFRX_EL1_RES0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64MMFRX_EL1_RES0(unsigned long a)17454 static inline uint64_t BDK_AP_ID_AA64MMFRX_EL1_RES0(unsigned long a)
17455 {
17456     if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && ((a>=2)&&(a<=7)))
17457         return 0x30000070000ll + 0x100ll * ((a) & 0x7);
17458     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && ((a>=3)&&(a<=7)))
17459         return 0x30000070000ll + 0x100ll * ((a) & 0x7);
17460     __bdk_csr_fatal("AP_ID_AA64MMFRX_EL1_RES0", 1, a, 0, 0, 0);
17461 }
17462 
17463 #define typedef_BDK_AP_ID_AA64MMFRX_EL1_RES0(a) bdk_ap_id_aa64mmfrx_el1_res0_t
17464 #define bustype_BDK_AP_ID_AA64MMFRX_EL1_RES0(a) BDK_CSR_TYPE_SYSREG
17465 #define basename_BDK_AP_ID_AA64MMFRX_EL1_RES0(a) "AP_ID_AA64MMFRX_EL1_RES0"
17466 #define busnum_BDK_AP_ID_AA64MMFRX_EL1_RES0(a) (a)
17467 #define arguments_BDK_AP_ID_AA64MMFRX_EL1_RES0(a) (a),-1,-1,-1
17468 
17469 /**
17470  * Register (SYSREG) ap_id_aa64mmfr0_el1
17471  *
17472  * AP AArch64 Memory Model Feature Register 0
17473  * This register provides information about the implemented memory model and memory
17474  * management support in AArch64.
17475  */
17476 union bdk_ap_id_aa64mmfr0_el1
17477 {
17478     uint64_t u;
17479     struct bdk_ap_id_aa64mmfr0_el1_s
17480     {
17481 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17482         uint64_t reserved_32_63        : 32;
17483         uint64_t tgran4                : 4;  /**< [ 31: 28](RO) Support for 4KB memory translation granule size.
17484                                                                  All other values are reserved.
17485                                                                  0x0 = 4KB granule supported.
17486                                                                  0xF = 4KB granule not supported.
17487 
17488                                                                  In CNXXXX, supported. */
17489         uint64_t tgran64               : 4;  /**< [ 27: 24](RO) Support for 64KB memory translation granule size.
17490                                                                  All other values are reserved.
17491                                                                  0x0 = 64KB granule supported.
17492                                                                  0xF = 64KB granule not supported.
17493 
17494                                                                  In CNXXXX, supported. */
17495         uint64_t tgran16               : 4;  /**< [ 23: 20](RO) Support for 16KB memory translation granule size.
17496                                                                  All other values are reserved.
17497                                                                  0x0 = 16KB granule not supported.
17498                                                                  0x1 = 16KB granule supported.
17499 
17500                                                                  In CNXXXX, supported. */
17501         uint64_t bigendel0             : 4;  /**< [ 19: 16](RO) Mixed-endian support at EL0 only.
17502                                                                  All other values are reserved.
17503                                                                  This field is invalid and is RES0 if the BigEnd field, bits
17504                                                                      [11:8], is not 0x0.
17505                                                                  0x0 = No mixed-endian support at EL0. The AP_SCTLR_EL1[E0E] bit has a
17506                                                                      fixed value.
17507                                                                  0x1 = Mixed-endian support at EL0. The AP_SCTLR_EL1[E0E] bit can be
17508                                                                      configured.
17509 
17510                                                                  In CNXXXX, supported. */
17511         uint64_t snsmem                : 4;  /**< [ 15: 12](RO) Secure versus nonsecure memory distinction.
17512                                                                  All other values are reserved.
17513                                                                  0x0 = Does not support a distinction between secure and nonsecure
17514                                                                      memory.
17515                                                                  0x1 = Does support a distinction between secure and nonsecure
17516                                                                      memory.
17517 
17518                                                                  In CNXXXX, supported. */
17519         uint64_t bigend                : 4;  /**< [ 11:  8](RO) Mixed-endian configuration support.
17520                                                                  All other values are reserved.
17521                                                                  0x0 = No mixed-endian support. The AP_SCTLR_ELx[EE] bits have a fixed
17522                                                                      value. See the BigEndEL0 field, bits[19:16], for whether EL0
17523                                                                      supports mixed-endian.
17524                                                                  0x1 = Mixed-endian support. The AP_SCTLR_ELx[EE] and AP_SCTLR_EL1[E0E] bits
17525                                                                      can be configured.
17526 
17527                                                                  In CNXXXX, supported. */
17528         uint64_t asidbits              : 4;  /**< [  7:  4](RO) Number of ASID bits.
17529                                                                  All other values are reserved.
17530                                                                  0x0 = 8 bits.
17531                                                                  0x2 = 16 bits.
17532 
17533                                                                  In CNXXXX, 16 bits. */
17534         uint64_t parange               : 4;  /**< [  3:  0](RO) Physical address range supported.
17535                                                                  All other values are reserved.
17536                                                                  0x0 = 32 bits, 4GB.
17537                                                                  0x1 = 36 bits, 64GB.
17538                                                                  0x2 = 40 bits, 1TB.
17539                                                                  0x3 = 42 bits, 4TB.
17540                                                                  0x4 = 44 bits, 16TB.
17541                                                                  0x5 = 48 bits, 256TB.
17542 
17543                                                                  In CNXXXX, 48 bits. */
17544 #else /* Word 0 - Little Endian */
17545         uint64_t parange               : 4;  /**< [  3:  0](RO) Physical address range supported.
17546                                                                  All other values are reserved.
17547                                                                  0x0 = 32 bits, 4GB.
17548                                                                  0x1 = 36 bits, 64GB.
17549                                                                  0x2 = 40 bits, 1TB.
17550                                                                  0x3 = 42 bits, 4TB.
17551                                                                  0x4 = 44 bits, 16TB.
17552                                                                  0x5 = 48 bits, 256TB.
17553 
17554                                                                  In CNXXXX, 48 bits. */
17555         uint64_t asidbits              : 4;  /**< [  7:  4](RO) Number of ASID bits.
17556                                                                  All other values are reserved.
17557                                                                  0x0 = 8 bits.
17558                                                                  0x2 = 16 bits.
17559 
17560                                                                  In CNXXXX, 16 bits. */
17561         uint64_t bigend                : 4;  /**< [ 11:  8](RO) Mixed-endian configuration support.
17562                                                                  All other values are reserved.
17563                                                                  0x0 = No mixed-endian support. The AP_SCTLR_ELx[EE] bits have a fixed
17564                                                                      value. See the BigEndEL0 field, bits[19:16], for whether EL0
17565                                                                      supports mixed-endian.
17566                                                                  0x1 = Mixed-endian support. The AP_SCTLR_ELx[EE] and AP_SCTLR_EL1[E0E] bits
17567                                                                      can be configured.
17568 
17569                                                                  In CNXXXX, supported. */
17570         uint64_t snsmem                : 4;  /**< [ 15: 12](RO) Secure versus nonsecure memory distinction.
17571                                                                  All other values are reserved.
17572                                                                  0x0 = Does not support a distinction between secure and nonsecure
17573                                                                      memory.
17574                                                                  0x1 = Does support a distinction between secure and nonsecure
17575                                                                      memory.
17576 
17577                                                                  In CNXXXX, supported. */
17578         uint64_t bigendel0             : 4;  /**< [ 19: 16](RO) Mixed-endian support at EL0 only.
17579                                                                  All other values are reserved.
17580                                                                  This field is invalid and is RES0 if the BigEnd field, bits
17581                                                                      [11:8], is not 0x0.
17582                                                                  0x0 = No mixed-endian support at EL0. The AP_SCTLR_EL1[E0E] bit has a
17583                                                                      fixed value.
17584                                                                  0x1 = Mixed-endian support at EL0. The AP_SCTLR_EL1[E0E] bit can be
17585                                                                      configured.
17586 
17587                                                                  In CNXXXX, supported. */
17588         uint64_t tgran16               : 4;  /**< [ 23: 20](RO) Support for 16KB memory translation granule size.
17589                                                                  All other values are reserved.
17590                                                                  0x0 = 16KB granule not supported.
17591                                                                  0x1 = 16KB granule supported.
17592 
17593                                                                  In CNXXXX, supported. */
17594         uint64_t tgran64               : 4;  /**< [ 27: 24](RO) Support for 64KB memory translation granule size.
17595                                                                  All other values are reserved.
17596                                                                  0x0 = 64KB granule supported.
17597                                                                  0xF = 64KB granule not supported.
17598 
17599                                                                  In CNXXXX, supported. */
17600         uint64_t tgran4                : 4;  /**< [ 31: 28](RO) Support for 4KB memory translation granule size.
17601                                                                  All other values are reserved.
17602                                                                  0x0 = 4KB granule supported.
17603                                                                  0xF = 4KB granule not supported.
17604 
17605                                                                  In CNXXXX, supported. */
17606         uint64_t reserved_32_63        : 32;
17607 #endif /* Word 0 - End */
17608     } s;
17609     /* struct bdk_ap_id_aa64mmfr0_el1_s cn8; */
17610     struct bdk_ap_id_aa64mmfr0_el1_cn9
17611     {
17612 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17613         uint64_t reserved_32_63        : 32;
17614         uint64_t tgran4                : 4;  /**< [ 31: 28](RO) Support for 4KB memory translation granule size.
17615                                                                  All other values are reserved.
17616                                                                  0x0 = 4KB granule supported.
17617                                                                  0xF = 4KB granule not supported.
17618 
17619                                                                  In CNXXXX, supported. */
17620         uint64_t tgran64               : 4;  /**< [ 27: 24](RO) Support for 64KB memory translation granule size.
17621                                                                  All other values are reserved.
17622                                                                  0x0 = 64KB granule supported.
17623                                                                  0xF = 64KB granule not supported.
17624 
17625                                                                  In CNXXXX, supported. */
17626         uint64_t tgran16               : 4;  /**< [ 23: 20](RO) Support for 16KB memory translation granule size.
17627                                                                  All other values are reserved.
17628                                                                  0x0 = 16KB granule not supported.
17629                                                                  0x1 = 16KB granule supported.
17630 
17631                                                                  In CNXXXX, supported. */
17632         uint64_t bigendel0             : 4;  /**< [ 19: 16](RO) Mixed-endian support at EL0 only.
17633                                                                  All other values are reserved.
17634                                                                  This field is invalid and is RES0 if the BigEnd field, bits
17635                                                                      [11:8], is not 0x0.
17636                                                                  0x0 = No mixed-endian support at EL0. The AP_SCTLR_EL1[E0E] bit has a
17637                                                                      fixed value.
17638                                                                  0x1 = Mixed-endian support at EL0. The AP_SCTLR_EL1[E0E] bit can be
17639                                                                      configured.
17640 
17641                                                                  In CNXXXX, supported. */
17642         uint64_t snsmem                : 4;  /**< [ 15: 12](RO) Secure versus nonsecure memory distinction.
17643                                                                  All other values are reserved.
17644                                                                  0x0 = Does not support a distinction between secure and nonsecure
17645                                                                      memory.
17646                                                                  0x1 = Does support a distinction between secure and nonsecure
17647                                                                      memory.
17648 
17649                                                                  In CNXXXX, supported. */
17650         uint64_t bigend                : 4;  /**< [ 11:  8](RO) Mixed-endian configuration support.
17651                                                                  All other values are reserved.
17652                                                                  0x0 = No mixed-endian support. The AP_SCTLR_ELx[EE] bits have a fixed
17653                                                                      value. See the BigEndEL0 field, bits[19:16], for whether EL0
17654                                                                      supports mixed-endian.
17655                                                                  0x1 = Mixed-endian support. The AP_SCTLR_ELx[EE] and AP_SCTLR_EL1[E0E] bits
17656                                                                      can be configured.
17657 
17658                                                                  In CNXXXX, supported. */
17659         uint64_t asidbits              : 4;  /**< [  7:  4](RO) Number of ASID bits.
17660                                                                  All other values are reserved.
17661                                                                  0x0 = 8 bits.
17662                                                                  0x2 = 16 bits.
17663 
17664                                                                  In CNXXXX, 16 bits. */
17665         uint64_t parange               : 4;  /**< [  3:  0](RO) Physical address range supported.
17666                                                                  All other values are reserved.
17667                                                                  0x0 = 32 bits, 4GB.
17668                                                                  0x1 = 36 bits, 64GB.
17669                                                                  0x2 = 40 bits, 1TB.
17670                                                                  0x3 = 42 bits, 4TB.
17671                                                                  0x4 = 44 bits, 16TB.
17672                                                                  0x5 = 48 bits, 256TB.
17673                                                                  0x6 = 52 bits, 4PB.
17674 
17675                                                                  In CN8XXX, 48 bits.
17676                                                                  In CN9XXX, 52 bits. */
17677 #else /* Word 0 - Little Endian */
17678         uint64_t parange               : 4;  /**< [  3:  0](RO) Physical address range supported.
17679                                                                  All other values are reserved.
17680                                                                  0x0 = 32 bits, 4GB.
17681                                                                  0x1 = 36 bits, 64GB.
17682                                                                  0x2 = 40 bits, 1TB.
17683                                                                  0x3 = 42 bits, 4TB.
17684                                                                  0x4 = 44 bits, 16TB.
17685                                                                  0x5 = 48 bits, 256TB.
17686                                                                  0x6 = 52 bits, 4PB.
17687 
17688                                                                  In CN8XXX, 48 bits.
17689                                                                  In CN9XXX, 52 bits. */
17690         uint64_t asidbits              : 4;  /**< [  7:  4](RO) Number of ASID bits.
17691                                                                  All other values are reserved.
17692                                                                  0x0 = 8 bits.
17693                                                                  0x2 = 16 bits.
17694 
17695                                                                  In CNXXXX, 16 bits. */
17696         uint64_t bigend                : 4;  /**< [ 11:  8](RO) Mixed-endian configuration support.
17697                                                                  All other values are reserved.
17698                                                                  0x0 = No mixed-endian support. The AP_SCTLR_ELx[EE] bits have a fixed
17699                                                                      value. See the BigEndEL0 field, bits[19:16], for whether EL0
17700                                                                      supports mixed-endian.
17701                                                                  0x1 = Mixed-endian support. The AP_SCTLR_ELx[EE] and AP_SCTLR_EL1[E0E] bits
17702                                                                      can be configured.
17703 
17704                                                                  In CNXXXX, supported. */
17705         uint64_t snsmem                : 4;  /**< [ 15: 12](RO) Secure versus nonsecure memory distinction.
17706                                                                  All other values are reserved.
17707                                                                  0x0 = Does not support a distinction between secure and nonsecure
17708                                                                      memory.
17709                                                                  0x1 = Does support a distinction between secure and nonsecure
17710                                                                      memory.
17711 
17712                                                                  In CNXXXX, supported. */
17713         uint64_t bigendel0             : 4;  /**< [ 19: 16](RO) Mixed-endian support at EL0 only.
17714                                                                  All other values are reserved.
17715                                                                  This field is invalid and is RES0 if the BigEnd field, bits
17716                                                                      [11:8], is not 0x0.
17717                                                                  0x0 = No mixed-endian support at EL0. The AP_SCTLR_EL1[E0E] bit has a
17718                                                                      fixed value.
17719                                                                  0x1 = Mixed-endian support at EL0. The AP_SCTLR_EL1[E0E] bit can be
17720                                                                      configured.
17721 
17722                                                                  In CNXXXX, supported. */
17723         uint64_t tgran16               : 4;  /**< [ 23: 20](RO) Support for 16KB memory translation granule size.
17724                                                                  All other values are reserved.
17725                                                                  0x0 = 16KB granule not supported.
17726                                                                  0x1 = 16KB granule supported.
17727 
17728                                                                  In CNXXXX, supported. */
17729         uint64_t tgran64               : 4;  /**< [ 27: 24](RO) Support for 64KB memory translation granule size.
17730                                                                  All other values are reserved.
17731                                                                  0x0 = 64KB granule supported.
17732                                                                  0xF = 64KB granule not supported.
17733 
17734                                                                  In CNXXXX, supported. */
17735         uint64_t tgran4                : 4;  /**< [ 31: 28](RO) Support for 4KB memory translation granule size.
17736                                                                  All other values are reserved.
17737                                                                  0x0 = 4KB granule supported.
17738                                                                  0xF = 4KB granule not supported.
17739 
17740                                                                  In CNXXXX, supported. */
17741         uint64_t reserved_32_63        : 32;
17742 #endif /* Word 0 - End */
17743     } cn9;
17744 };
17745 typedef union bdk_ap_id_aa64mmfr0_el1 bdk_ap_id_aa64mmfr0_el1_t;
17746 
17747 #define BDK_AP_ID_AA64MMFR0_EL1 BDK_AP_ID_AA64MMFR0_EL1_FUNC()
17748 static inline uint64_t BDK_AP_ID_AA64MMFR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64MMFR0_EL1_FUNC(void)17749 static inline uint64_t BDK_AP_ID_AA64MMFR0_EL1_FUNC(void)
17750 {
17751     return 0x30000070000ll;
17752 }
17753 
17754 #define typedef_BDK_AP_ID_AA64MMFR0_EL1 bdk_ap_id_aa64mmfr0_el1_t
17755 #define bustype_BDK_AP_ID_AA64MMFR0_EL1 BDK_CSR_TYPE_SYSREG
17756 #define basename_BDK_AP_ID_AA64MMFR0_EL1 "AP_ID_AA64MMFR0_EL1"
17757 #define busnum_BDK_AP_ID_AA64MMFR0_EL1 0
17758 #define arguments_BDK_AP_ID_AA64MMFR0_EL1 -1,-1,-1,-1
17759 
17760 /**
17761  * Register (SYSREG) ap_id_aa64mmfr1_el1
17762  *
17763  * AP AArch64 Memory Model Feature Register 1
17764  * This register contains additional information about the implemented memory model and
17765  * memory management support in AArch64.
17766  */
17767 union bdk_ap_id_aa64mmfr1_el1
17768 {
17769     uint64_t u;
17770     struct bdk_ap_id_aa64mmfr1_el1_s
17771     {
17772 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17773         uint64_t reserved_32_63        : 32;
17774         uint64_t xnx                   : 4;  /**< [ 31: 28](RO) 0x0 = EL0/EL1 execute control distinction at stage2 bit not supported.
17775                                                                  0x1 = EL0/EL1 execute control distinction at stage2 bit supported.
17776 
17777                                                                  All other values reserved. */
17778         uint64_t specsei               : 4;  /**< [ 27: 24](RO) Describes whether the PE can generate SError interrupt exceptions from speculative reads
17779                                                                  of memory, including speculative instruction fetches.
17780                                                                    0x0 = The PE never generates an SError interrupt due to an external abort on a
17781                                                                  speculative read.
17782                                                                    0x1 = The PE might generate an SError interrupt due to an external abort on a
17783                                                                  speculative
17784                                                                  read.
17785 
17786                                                                  All other values are reserved. Reserved values might be defined in a future version of the
17787                                                                  architecture.
17788 
17789                                                                  Valid only if AP_ID_AA64PFR0_EL1[RAS] is nonzero. RAZ otherwise.
17790 
17791                                                                  Note: Speculative reads include speculative instruction prefetches. The architecture
17792                                                                  places restrictions on the memory types a processor is permitted to speculatively read
17793                                                                  from. Software might use this to control how it initializes memory, and how it responds to
17794                                                                  errors reported by ESB operations. */
17795         uint64_t pan                   : 4;  /**< [ 23: 20](RO) V8.1: Privileged Access Never.
17796                                                                  0x0 = AP_PAN not supported.
17797                                                                  0x1 = AP_PAN supported.
17798                                                                  All other values reserved.
17799 
17800                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17801         uint64_t lo                    : 4;  /**< [ 19: 16](RO) V8.1: Limited order regions
17802                                                                  All other values reserved.
17803                                                                  0x0 = LORRegions not supported.
17804                                                                  0x1 = LORRegions supported.
17805 
17806                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17807         uint64_t reserved_12_15        : 4;
17808         uint64_t vh                    : 4;  /**< [ 11:  8](RO) V8.1:  Virtualization Host Extensions.
17809                                                                  All other values reserved.
17810                                                                  0x0 = Virtualization Host Extensions are not supported.
17811                                                                  0x1 = Virtualization Host Extensions supported.
17812 
17813                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17814         uint64_t vmidbits              : 4;  /**< [  7:  4](RO) V8.1: Number of VMID bits.
17815                                                                  Other values are reserved.
17816                                                                  0x0 = 8 bits.
17817                                                                  0x1 = Reserved.
17818                                                                  0x2 = 16 bits.
17819 
17820                                                                  In CNXXXX, 16 bits. */
17821         uint64_t hardware_access_dirty : 4;  /**< [  3:  0](RO) V8.1: Hardware updates of the Access and Dirty bits
17822                                                                  All other fields reserved.
17823                                                                  0x0 = no hardware update of the access and dirty bits supported in hardware.
17824                                                                  0x1 = hardware update of the access bit supported in hardware.
17825                                                                  0x2 = hardware update of both the access and dirty bits supported in hardware.
17826 
17827                                                                  In CNXXXX not supported. */
17828 #else /* Word 0 - Little Endian */
17829         uint64_t hardware_access_dirty : 4;  /**< [  3:  0](RO) V8.1: Hardware updates of the Access and Dirty bits
17830                                                                  All other fields reserved.
17831                                                                  0x0 = no hardware update of the access and dirty bits supported in hardware.
17832                                                                  0x1 = hardware update of the access bit supported in hardware.
17833                                                                  0x2 = hardware update of both the access and dirty bits supported in hardware.
17834 
17835                                                                  In CNXXXX not supported. */
17836         uint64_t vmidbits              : 4;  /**< [  7:  4](RO) V8.1: Number of VMID bits.
17837                                                                  Other values are reserved.
17838                                                                  0x0 = 8 bits.
17839                                                                  0x1 = Reserved.
17840                                                                  0x2 = 16 bits.
17841 
17842                                                                  In CNXXXX, 16 bits. */
17843         uint64_t vh                    : 4;  /**< [ 11:  8](RO) V8.1:  Virtualization Host Extensions.
17844                                                                  All other values reserved.
17845                                                                  0x0 = Virtualization Host Extensions are not supported.
17846                                                                  0x1 = Virtualization Host Extensions supported.
17847 
17848                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17849         uint64_t reserved_12_15        : 4;
17850         uint64_t lo                    : 4;  /**< [ 19: 16](RO) V8.1: Limited order regions
17851                                                                  All other values reserved.
17852                                                                  0x0 = LORRegions not supported.
17853                                                                  0x1 = LORRegions supported.
17854 
17855                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17856         uint64_t pan                   : 4;  /**< [ 23: 20](RO) V8.1: Privileged Access Never.
17857                                                                  0x0 = AP_PAN not supported.
17858                                                                  0x1 = AP_PAN supported.
17859                                                                  All other values reserved.
17860 
17861                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17862         uint64_t specsei               : 4;  /**< [ 27: 24](RO) Describes whether the PE can generate SError interrupt exceptions from speculative reads
17863                                                                  of memory, including speculative instruction fetches.
17864                                                                    0x0 = The PE never generates an SError interrupt due to an external abort on a
17865                                                                  speculative read.
17866                                                                    0x1 = The PE might generate an SError interrupt due to an external abort on a
17867                                                                  speculative
17868                                                                  read.
17869 
17870                                                                  All other values are reserved. Reserved values might be defined in a future version of the
17871                                                                  architecture.
17872 
17873                                                                  Valid only if AP_ID_AA64PFR0_EL1[RAS] is nonzero. RAZ otherwise.
17874 
17875                                                                  Note: Speculative reads include speculative instruction prefetches. The architecture
17876                                                                  places restrictions on the memory types a processor is permitted to speculatively read
17877                                                                  from. Software might use this to control how it initializes memory, and how it responds to
17878                                                                  errors reported by ESB operations. */
17879         uint64_t xnx                   : 4;  /**< [ 31: 28](RO) 0x0 = EL0/EL1 execute control distinction at stage2 bit not supported.
17880                                                                  0x1 = EL0/EL1 execute control distinction at stage2 bit supported.
17881 
17882                                                                  All other values reserved. */
17883         uint64_t reserved_32_63        : 32;
17884 #endif /* Word 0 - End */
17885     } s;
17886     struct bdk_ap_id_aa64mmfr1_el1_cn8
17887     {
17888 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17889         uint64_t reserved_24_63        : 40;
17890         uint64_t pan                   : 4;  /**< [ 23: 20](RO) V8.1: Privileged Access Never.
17891                                                                  0x0 = AP_PAN not supported.
17892                                                                  0x1 = AP_PAN supported.
17893                                                                  All other values reserved.
17894 
17895                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17896         uint64_t lo                    : 4;  /**< [ 19: 16](RO) V8.1: Limited order regions
17897                                                                  All other values reserved.
17898                                                                  0x0 = LORRegions not supported.
17899                                                                  0x1 = LORRegions supported.
17900 
17901                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17902         uint64_t hd                    : 4;  /**< [ 15: 12](RO) V8.1: Hierarchical Attribute Disables.
17903                                                                  All other values reserved.
17904                                                                  0x0 = Hierarchical Attribute Disables not supported.
17905                                                                  0x1 = Hierarchical Attribute Disables supported.
17906 
17907                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17908         uint64_t vh                    : 4;  /**< [ 11:  8](RO) V8.1:  Virtualization Host Extensions.
17909                                                                  All other values reserved.
17910                                                                  0x0 = Virtualization Host Extensions are not supported.
17911                                                                  0x1 = Virtualization Host Extensions supported.
17912 
17913                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17914         uint64_t vmidbits              : 4;  /**< [  7:  4](RO) V8.1: Number of VMID bits.
17915                                                                  Other values are reserved.
17916                                                                  0x0 = 8 bits.
17917                                                                  0x1 = Reserved.
17918                                                                  0x2 = 16 bits.
17919 
17920                                                                  In CNXXXX, 16 bits. */
17921         uint64_t hardware_access_dirty : 4;  /**< [  3:  0](RO) V8.1: Hardware updates of the Access and Dirty bits
17922                                                                  All other fields reserved.
17923                                                                  0x0 = no hardware update of the access and dirty bits supported in hardware.
17924                                                                  0x1 = hardware update of the access bit supported in hardware.
17925                                                                  0x2 = hardware update of both the access and dirty bits supported in hardware.
17926 
17927                                                                  In CNXXXX not supported. */
17928 #else /* Word 0 - Little Endian */
17929         uint64_t hardware_access_dirty : 4;  /**< [  3:  0](RO) V8.1: Hardware updates of the Access and Dirty bits
17930                                                                  All other fields reserved.
17931                                                                  0x0 = no hardware update of the access and dirty bits supported in hardware.
17932                                                                  0x1 = hardware update of the access bit supported in hardware.
17933                                                                  0x2 = hardware update of both the access and dirty bits supported in hardware.
17934 
17935                                                                  In CNXXXX not supported. */
17936         uint64_t vmidbits              : 4;  /**< [  7:  4](RO) V8.1: Number of VMID bits.
17937                                                                  Other values are reserved.
17938                                                                  0x0 = 8 bits.
17939                                                                  0x1 = Reserved.
17940                                                                  0x2 = 16 bits.
17941 
17942                                                                  In CNXXXX, 16 bits. */
17943         uint64_t vh                    : 4;  /**< [ 11:  8](RO) V8.1:  Virtualization Host Extensions.
17944                                                                  All other values reserved.
17945                                                                  0x0 = Virtualization Host Extensions are not supported.
17946                                                                  0x1 = Virtualization Host Extensions supported.
17947 
17948                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17949         uint64_t hd                    : 4;  /**< [ 15: 12](RO) V8.1: Hierarchical Attribute Disables.
17950                                                                  All other values reserved.
17951                                                                  0x0 = Hierarchical Attribute Disables not supported.
17952                                                                  0x1 = Hierarchical Attribute Disables supported.
17953 
17954                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17955         uint64_t lo                    : 4;  /**< [ 19: 16](RO) V8.1: Limited order regions
17956                                                                  All other values reserved.
17957                                                                  0x0 = LORRegions not supported.
17958                                                                  0x1 = LORRegions supported.
17959 
17960                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17961         uint64_t pan                   : 4;  /**< [ 23: 20](RO) V8.1: Privileged Access Never.
17962                                                                  0x0 = AP_PAN not supported.
17963                                                                  0x1 = AP_PAN supported.
17964                                                                  All other values reserved.
17965 
17966                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
17967         uint64_t reserved_24_63        : 40;
17968 #endif /* Word 0 - End */
17969     } cn8;
17970     struct bdk_ap_id_aa64mmfr1_el1_cn9
17971     {
17972 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
17973         uint64_t reserved_32_63        : 32;
17974         uint64_t xnx                   : 4;  /**< [ 31: 28](RO) 0x0 = EL0/EL1 execute control distinction at stage2 bit not supported.
17975                                                                  0x1 = EL0/EL1 execute control distinction at stage2 bit supported.
17976 
17977                                                                  All other values reserved. */
17978         uint64_t specsei               : 4;  /**< [ 27: 24](RO) Describes whether the PE can generate SError interrupt exceptions from speculative reads
17979                                                                  of memory, including speculative instruction fetches.
17980                                                                    0x0 = The PE never generates an SError interrupt due to an external abort on a
17981                                                                  speculative read.
17982                                                                    0x1 = The PE might generate an SError interrupt due to an external abort on a
17983                                                                  speculative
17984                                                                  read.
17985 
17986                                                                  All other values are reserved. Reserved values might be defined in a future version of the
17987                                                                  architecture.
17988 
17989                                                                  Valid only if AP_ID_AA64PFR0_EL1[RAS] is nonzero. RAZ otherwise.
17990 
17991                                                                  Note: Speculative reads include speculative instruction prefetches. The architecture
17992                                                                  places restrictions on the memory types a processor is permitted to speculatively read
17993                                                                  from. Software might use this to control how it initializes memory, and how it responds to
17994                                                                  errors reported by ESB operations. */
17995         uint64_t pan                   : 4;  /**< [ 23: 20](RO) V8.1: Privileged Access Never.
17996                                                                  0x0 = AP_PAN not supported.
17997                                                                  0x1 = AP_PAN supported.
17998                                                                  0x2 = PAN supported and new AT S1E1RP and AT S1E1WP instructions supported
17999 
18000                                                                  All other values reserved.
18001 
18002                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
18003         uint64_t lo                    : 4;  /**< [ 19: 16](RO) V8.1: Limited order regions
18004                                                                  All other values reserved.
18005                                                                  0x0 = LORRegions not supported.
18006                                                                  0x1 = LORRegions supported.
18007 
18008                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
18009         uint64_t hpds                  : 4;  /**< [ 15: 12](RO) V8.1: Hierarchical Permission Disables.
18010                                                                  All other values reserved.
18011                                                                  0x0 = Hierarchical Permission Disables not supported.
18012                                                                  0x1 = Hierarchical Permission Disables supported.
18013                                                                  0x2 = Hierarchical Permission Disables and hardware allocation of bits[62:59] supported.
18014 
18015                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
18016         uint64_t vh                    : 4;  /**< [ 11:  8](RO) V8.1:  Virtualization Host Extensions.
18017                                                                  All other values reserved.
18018                                                                  0x0 = Virtualization Host Extensions are not supported.
18019                                                                  0x1 = Virtualization Host Extensions supported.
18020 
18021                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
18022         uint64_t vmidbits              : 4;  /**< [  7:  4](RO) V8.1: Number of VMID bits.
18023                                                                  Other values are reserved.
18024                                                                  0x0 = 8 bits.
18025                                                                  0x1 = Reserved.
18026                                                                  0x2 = 16 bits.
18027 
18028                                                                  In CNXXXX, 16 bits. */
18029         uint64_t hardware_access_dirty : 4;  /**< [  3:  0](RO) V8.1: Hardware updates of the Access and Dirty bits
18030                                                                  All other fields reserved.
18031                                                                  0x0 = no hardware update of the access and dirty bits supported in hardware.
18032                                                                  0x1 = hardware update of the access bit supported in hardware.
18033                                                                  0x2 = hardware update of both the access and dirty bits supported in hardware.
18034 
18035                                                                  In CNXXXX not supported. */
18036 #else /* Word 0 - Little Endian */
18037         uint64_t hardware_access_dirty : 4;  /**< [  3:  0](RO) V8.1: Hardware updates of the Access and Dirty bits
18038                                                                  All other fields reserved.
18039                                                                  0x0 = no hardware update of the access and dirty bits supported in hardware.
18040                                                                  0x1 = hardware update of the access bit supported in hardware.
18041                                                                  0x2 = hardware update of both the access and dirty bits supported in hardware.
18042 
18043                                                                  In CNXXXX not supported. */
18044         uint64_t vmidbits              : 4;  /**< [  7:  4](RO) V8.1: Number of VMID bits.
18045                                                                  Other values are reserved.
18046                                                                  0x0 = 8 bits.
18047                                                                  0x1 = Reserved.
18048                                                                  0x2 = 16 bits.
18049 
18050                                                                  In CNXXXX, 16 bits. */
18051         uint64_t vh                    : 4;  /**< [ 11:  8](RO) V8.1:  Virtualization Host Extensions.
18052                                                                  All other values reserved.
18053                                                                  0x0 = Virtualization Host Extensions are not supported.
18054                                                                  0x1 = Virtualization Host Extensions supported.
18055 
18056                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
18057         uint64_t hpds                  : 4;  /**< [ 15: 12](RO) V8.1: Hierarchical Permission Disables.
18058                                                                  All other values reserved.
18059                                                                  0x0 = Hierarchical Permission Disables not supported.
18060                                                                  0x1 = Hierarchical Permission Disables supported.
18061                                                                  0x2 = Hierarchical Permission Disables and hardware allocation of bits[62:59] supported.
18062 
18063                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
18064         uint64_t lo                    : 4;  /**< [ 19: 16](RO) V8.1: Limited order regions
18065                                                                  All other values reserved.
18066                                                                  0x0 = LORRegions not supported.
18067                                                                  0x1 = LORRegions supported.
18068 
18069                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
18070         uint64_t pan                   : 4;  /**< [ 23: 20](RO) V8.1: Privileged Access Never.
18071                                                                  0x0 = AP_PAN not supported.
18072                                                                  0x1 = AP_PAN supported.
18073                                                                  0x2 = PAN supported and new AT S1E1RP and AT S1E1WP instructions supported
18074 
18075                                                                  All other values reserved.
18076 
18077                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
18078         uint64_t specsei               : 4;  /**< [ 27: 24](RO) Describes whether the PE can generate SError interrupt exceptions from speculative reads
18079                                                                  of memory, including speculative instruction fetches.
18080                                                                    0x0 = The PE never generates an SError interrupt due to an external abort on a
18081                                                                  speculative read.
18082                                                                    0x1 = The PE might generate an SError interrupt due to an external abort on a
18083                                                                  speculative
18084                                                                  read.
18085 
18086                                                                  All other values are reserved. Reserved values might be defined in a future version of the
18087                                                                  architecture.
18088 
18089                                                                  Valid only if AP_ID_AA64PFR0_EL1[RAS] is nonzero. RAZ otherwise.
18090 
18091                                                                  Note: Speculative reads include speculative instruction prefetches. The architecture
18092                                                                  places restrictions on the memory types a processor is permitted to speculatively read
18093                                                                  from. Software might use this to control how it initializes memory, and how it responds to
18094                                                                  errors reported by ESB operations. */
18095         uint64_t xnx                   : 4;  /**< [ 31: 28](RO) 0x0 = EL0/EL1 execute control distinction at stage2 bit not supported.
18096                                                                  0x1 = EL0/EL1 execute control distinction at stage2 bit supported.
18097 
18098                                                                  All other values reserved. */
18099         uint64_t reserved_32_63        : 32;
18100 #endif /* Word 0 - End */
18101     } cn9;
18102 };
18103 typedef union bdk_ap_id_aa64mmfr1_el1 bdk_ap_id_aa64mmfr1_el1_t;
18104 
18105 #define BDK_AP_ID_AA64MMFR1_EL1 BDK_AP_ID_AA64MMFR1_EL1_FUNC()
18106 static inline uint64_t BDK_AP_ID_AA64MMFR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64MMFR1_EL1_FUNC(void)18107 static inline uint64_t BDK_AP_ID_AA64MMFR1_EL1_FUNC(void)
18108 {
18109     return 0x30000070100ll;
18110 }
18111 
18112 #define typedef_BDK_AP_ID_AA64MMFR1_EL1 bdk_ap_id_aa64mmfr1_el1_t
18113 #define bustype_BDK_AP_ID_AA64MMFR1_EL1 BDK_CSR_TYPE_SYSREG
18114 #define basename_BDK_AP_ID_AA64MMFR1_EL1 "AP_ID_AA64MMFR1_EL1"
18115 #define busnum_BDK_AP_ID_AA64MMFR1_EL1 0
18116 #define arguments_BDK_AP_ID_AA64MMFR1_EL1 -1,-1,-1,-1
18117 
18118 /**
18119  * Register (SYSREG) ap_id_aa64mmfr2_el1
18120  *
18121  * AP AArch64 Memory Model Feature Register 2
18122  * This register contains additional information about the implemented memory model and
18123  * memory management support in AArch64.
18124  */
18125 union bdk_ap_id_aa64mmfr2_el1
18126 {
18127     uint64_t u;
18128     struct bdk_ap_id_aa64mmfr2_el1_s
18129     {
18130 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18131         uint64_t reserved_20_63        : 44;
18132         uint64_t varange               : 4;  /**< [ 19: 16](RO) 0x0 = 48 bits of VA for each translation table page register (for 64Kbyte
18133                                                                  stage1 pages) are supported.
18134                                                                  0x1 = 52 bits of VA for each translation table page register (for 64Kbyte
18135                                                                  stage1 pages) are supported. */
18136         uint64_t iesb                  : 4;  /**< [ 15: 12](RO) 0x0 = Not implemented.
18137                                                                  0x1 = SCTLR_ELx.IESB implicit error synchronization barrier control implemented. */
18138         uint64_t lsm                   : 4;  /**< [ 11:  8](RO) 0x0 = LSMAOE and nTLSMD bit not supported.
18139                                                                  0x1 = LSMAOE and nTLSMD bit supported.
18140 
18141                                                                  All other values reserved. */
18142         uint64_t uao                   : 4;  /**< [  7:  4](RO) 0x0 = UAO not supported.
18143                                                                  0x1 = UAO supported.
18144 
18145                                                                  All other values reserved. */
18146         uint64_t cnp                   : 4;  /**< [  3:  0](RO) 0x0 = CnP bit not supported.
18147                                                                  0x1 = CnP bit supported.
18148 
18149                                                                  All other values reserved. */
18150 #else /* Word 0 - Little Endian */
18151         uint64_t cnp                   : 4;  /**< [  3:  0](RO) 0x0 = CnP bit not supported.
18152                                                                  0x1 = CnP bit supported.
18153 
18154                                                                  All other values reserved. */
18155         uint64_t uao                   : 4;  /**< [  7:  4](RO) 0x0 = UAO not supported.
18156                                                                  0x1 = UAO supported.
18157 
18158                                                                  All other values reserved. */
18159         uint64_t lsm                   : 4;  /**< [ 11:  8](RO) 0x0 = LSMAOE and nTLSMD bit not supported.
18160                                                                  0x1 = LSMAOE and nTLSMD bit supported.
18161 
18162                                                                  All other values reserved. */
18163         uint64_t iesb                  : 4;  /**< [ 15: 12](RO) 0x0 = Not implemented.
18164                                                                  0x1 = SCTLR_ELx.IESB implicit error synchronization barrier control implemented. */
18165         uint64_t varange               : 4;  /**< [ 19: 16](RO) 0x0 = 48 bits of VA for each translation table page register (for 64Kbyte
18166                                                                  stage1 pages) are supported.
18167                                                                  0x1 = 52 bits of VA for each translation table page register (for 64Kbyte
18168                                                                  stage1 pages) are supported. */
18169         uint64_t reserved_20_63        : 44;
18170 #endif /* Word 0 - End */
18171     } s;
18172     /* struct bdk_ap_id_aa64mmfr2_el1_s cn; */
18173 };
18174 typedef union bdk_ap_id_aa64mmfr2_el1 bdk_ap_id_aa64mmfr2_el1_t;
18175 
18176 #define BDK_AP_ID_AA64MMFR2_EL1 BDK_AP_ID_AA64MMFR2_EL1_FUNC()
18177 static inline uint64_t BDK_AP_ID_AA64MMFR2_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64MMFR2_EL1_FUNC(void)18178 static inline uint64_t BDK_AP_ID_AA64MMFR2_EL1_FUNC(void)
18179 {
18180     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
18181         return 0x30000070200ll;
18182     __bdk_csr_fatal("AP_ID_AA64MMFR2_EL1", 0, 0, 0, 0, 0);
18183 }
18184 
18185 #define typedef_BDK_AP_ID_AA64MMFR2_EL1 bdk_ap_id_aa64mmfr2_el1_t
18186 #define bustype_BDK_AP_ID_AA64MMFR2_EL1 BDK_CSR_TYPE_SYSREG
18187 #define basename_BDK_AP_ID_AA64MMFR2_EL1 "AP_ID_AA64MMFR2_EL1"
18188 #define busnum_BDK_AP_ID_AA64MMFR2_EL1 0
18189 #define arguments_BDK_AP_ID_AA64MMFR2_EL1 -1,-1,-1,-1
18190 
18191 /**
18192  * Register (SYSREG) ap_id_aa64pfr#_el1_res0
18193  *
18194  * INTERNAL: AP AArch64 Reserved Register
18195  *
18196  * Reserved for future expansion of information about implemented
18197  *     processor features in AArch64. ARM doesn't actually assign
18198  *     a name to these registers, so CNXXXX made up one.
18199  */
18200 union bdk_ap_id_aa64pfrx_el1_res0
18201 {
18202     uint64_t u;
18203     struct bdk_ap_id_aa64pfrx_el1_res0_s
18204     {
18205 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18206         uint64_t reserved_0_63         : 64;
18207 #else /* Word 0 - Little Endian */
18208         uint64_t reserved_0_63         : 64;
18209 #endif /* Word 0 - End */
18210     } s;
18211     /* struct bdk_ap_id_aa64pfrx_el1_res0_s cn; */
18212 };
18213 typedef union bdk_ap_id_aa64pfrx_el1_res0 bdk_ap_id_aa64pfrx_el1_res0_t;
18214 
18215 static inline uint64_t BDK_AP_ID_AA64PFRX_EL1_RES0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64PFRX_EL1_RES0(unsigned long a)18216 static inline uint64_t BDK_AP_ID_AA64PFRX_EL1_RES0(unsigned long a)
18217 {
18218     if ((a>=2)&&(a<=7))
18219         return 0x30000040000ll + 0x100ll * ((a) & 0x7);
18220     __bdk_csr_fatal("AP_ID_AA64PFRX_EL1_RES0", 1, a, 0, 0, 0);
18221 }
18222 
18223 #define typedef_BDK_AP_ID_AA64PFRX_EL1_RES0(a) bdk_ap_id_aa64pfrx_el1_res0_t
18224 #define bustype_BDK_AP_ID_AA64PFRX_EL1_RES0(a) BDK_CSR_TYPE_SYSREG
18225 #define basename_BDK_AP_ID_AA64PFRX_EL1_RES0(a) "AP_ID_AA64PFRX_EL1_RES0"
18226 #define busnum_BDK_AP_ID_AA64PFRX_EL1_RES0(a) (a)
18227 #define arguments_BDK_AP_ID_AA64PFRX_EL1_RES0(a) (a),-1,-1,-1
18228 
18229 /**
18230  * Register (SYSREG) ap_id_aa64pfr0_el1
18231  *
18232  * AP AArch64 Processor Feature Register 0
18233  * This register provides additional information about implemented processor features
18234  * in AArch64.
18235  */
18236 union bdk_ap_id_aa64pfr0_el1
18237 {
18238     uint64_t u;
18239     struct bdk_ap_id_aa64pfr0_el1_s
18240     {
18241 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18242         uint64_t reserved_32_63        : 32;
18243         uint64_t ras                   : 4;  /**< [ 31: 28](RO) RAS extension version.
18244                                                                    0x0 = No RAS extension.
18245                                                                    0x1 = Version 1 of the RAS extension present.
18246 
18247                                                                  All other values are reserved. Reserved values might be defined in a future version of the
18248                                                                  architecture. */
18249         uint64_t gic                   : 4;  /**< [ 27: 24](RO) GIC system register interface.
18250                                                                  All other values are reserved.
18251                                                                  0x0 = No GIC system registers are supported.
18252                                                                  0x1 = GICv3 system registers are supported.
18253 
18254                                                                  In CNXXXX, supported. */
18255         uint64_t advsimd               : 4;  /**< [ 23: 20](RO) Advanced SIMD.
18256                                                                  All other values are reserved.
18257                                                                  0x0 = Advanced SIMD is implemented.
18258                                                                  0xF = Advanced SIMD is not implemented.
18259 
18260                                                                  In CNXXXX, supported. */
18261         uint64_t fp                    : 4;  /**< [ 19: 16](RO) Floating-point.
18262                                                                  All other values are reserved.
18263                                                                  0x0 = Floating-point is implemented.
18264                                                                  0xF = Floating-point is not implemented.
18265 
18266                                                                  In CNXXXX, supported. */
18267         uint64_t el3                   : 4;  /**< [ 15: 12](RO) EL3 Exception level handling.
18268                                                                  All other values are reserved.
18269                                                                  0x0 = EL3 is not implemented.
18270                                                                  0x1 = EL3 can be executed in AArch64 state only.
18271                                                                  0x2 = EL3 can be executed in either AArch64 or AArch32 state.
18272 
18273                                                                  In CNXXXX, supported in AArch64. */
18274         uint64_t el2                   : 4;  /**< [ 11:  8](RO) EL2 Exception level handling.
18275                                                                  All other values are reserved.
18276                                                                  0x0 = EL2 is not implemented.
18277                                                                  0x1 = EL2 can be executed in AArch64 state only.
18278                                                                  0x2 = EL2 can be executed in either AArch64 or AArch32 state.
18279 
18280                                                                  In CNXXXX, supported in AArch64. */
18281         uint64_t el1                   : 4;  /**< [  7:  4](RO) EL1 Exception level handling.
18282                                                                  All other values are reserved.
18283                                                                  0x0 = EL1 is not implemented.
18284                                                                  0x1 = EL1 can be executed in AArch64 state only.
18285                                                                  0x2 = EL1 can be executed in either AArch64 or AArch32 state.
18286 
18287                                                                  In CNXXXX, supported in AArch64. */
18288         uint64_t el0                   : 4;  /**< [  3:  0](RO) EL0 Exception level handling.
18289                                                                  All other values are reserved.
18290                                                                  0x0 = EL0 is not implemented.
18291                                                                  0x1 = EL0 can be executed in AArch64 state only.
18292                                                                  0x2 = EL0 can be executed in either AArch64 or AArch32 state.
18293 
18294                                                                  In CNXXXX, supported in AArch64. */
18295 #else /* Word 0 - Little Endian */
18296         uint64_t el0                   : 4;  /**< [  3:  0](RO) EL0 Exception level handling.
18297                                                                  All other values are reserved.
18298                                                                  0x0 = EL0 is not implemented.
18299                                                                  0x1 = EL0 can be executed in AArch64 state only.
18300                                                                  0x2 = EL0 can be executed in either AArch64 or AArch32 state.
18301 
18302                                                                  In CNXXXX, supported in AArch64. */
18303         uint64_t el1                   : 4;  /**< [  7:  4](RO) EL1 Exception level handling.
18304                                                                  All other values are reserved.
18305                                                                  0x0 = EL1 is not implemented.
18306                                                                  0x1 = EL1 can be executed in AArch64 state only.
18307                                                                  0x2 = EL1 can be executed in either AArch64 or AArch32 state.
18308 
18309                                                                  In CNXXXX, supported in AArch64. */
18310         uint64_t el2                   : 4;  /**< [ 11:  8](RO) EL2 Exception level handling.
18311                                                                  All other values are reserved.
18312                                                                  0x0 = EL2 is not implemented.
18313                                                                  0x1 = EL2 can be executed in AArch64 state only.
18314                                                                  0x2 = EL2 can be executed in either AArch64 or AArch32 state.
18315 
18316                                                                  In CNXXXX, supported in AArch64. */
18317         uint64_t el3                   : 4;  /**< [ 15: 12](RO) EL3 Exception level handling.
18318                                                                  All other values are reserved.
18319                                                                  0x0 = EL3 is not implemented.
18320                                                                  0x1 = EL3 can be executed in AArch64 state only.
18321                                                                  0x2 = EL3 can be executed in either AArch64 or AArch32 state.
18322 
18323                                                                  In CNXXXX, supported in AArch64. */
18324         uint64_t fp                    : 4;  /**< [ 19: 16](RO) Floating-point.
18325                                                                  All other values are reserved.
18326                                                                  0x0 = Floating-point is implemented.
18327                                                                  0xF = Floating-point is not implemented.
18328 
18329                                                                  In CNXXXX, supported. */
18330         uint64_t advsimd               : 4;  /**< [ 23: 20](RO) Advanced SIMD.
18331                                                                  All other values are reserved.
18332                                                                  0x0 = Advanced SIMD is implemented.
18333                                                                  0xF = Advanced SIMD is not implemented.
18334 
18335                                                                  In CNXXXX, supported. */
18336         uint64_t gic                   : 4;  /**< [ 27: 24](RO) GIC system register interface.
18337                                                                  All other values are reserved.
18338                                                                  0x0 = No GIC system registers are supported.
18339                                                                  0x1 = GICv3 system registers are supported.
18340 
18341                                                                  In CNXXXX, supported. */
18342         uint64_t ras                   : 4;  /**< [ 31: 28](RO) RAS extension version.
18343                                                                    0x0 = No RAS extension.
18344                                                                    0x1 = Version 1 of the RAS extension present.
18345 
18346                                                                  All other values are reserved. Reserved values might be defined in a future version of the
18347                                                                  architecture. */
18348         uint64_t reserved_32_63        : 32;
18349 #endif /* Word 0 - End */
18350     } s;
18351     struct bdk_ap_id_aa64pfr0_el1_cn8
18352     {
18353 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18354         uint64_t reserved_28_63        : 36;
18355         uint64_t gic                   : 4;  /**< [ 27: 24](RO) GIC system register interface.
18356                                                                  All other values are reserved.
18357                                                                  0x0 = No GIC system registers are supported.
18358                                                                  0x1 = GICv3 system registers are supported.
18359 
18360                                                                  In CNXXXX, supported. */
18361         uint64_t advsimd               : 4;  /**< [ 23: 20](RO) Advanced SIMD.
18362                                                                  All other values are reserved.
18363                                                                  0x0 = Advanced SIMD is implemented.
18364                                                                  0xF = Advanced SIMD is not implemented.
18365 
18366                                                                  In CNXXXX, supported. */
18367         uint64_t fp                    : 4;  /**< [ 19: 16](RO) Floating-point.
18368                                                                  All other values are reserved.
18369                                                                  0x0 = Floating-point is implemented.
18370                                                                  0xF = Floating-point is not implemented.
18371 
18372                                                                  In CNXXXX, supported. */
18373         uint64_t el3                   : 4;  /**< [ 15: 12](RO) EL3 Exception level handling.
18374                                                                  All other values are reserved.
18375                                                                  0x0 = EL3 is not implemented.
18376                                                                  0x1 = EL3 can be executed in AArch64 state only.
18377                                                                  0x2 = EL3 can be executed in either AArch64 or AArch32 state.
18378 
18379                                                                  In CNXXXX, supported in AArch64. */
18380         uint64_t el2                   : 4;  /**< [ 11:  8](RO) EL2 Exception level handling.
18381                                                                  All other values are reserved.
18382                                                                  0x0 = EL2 is not implemented.
18383                                                                  0x1 = EL2 can be executed in AArch64 state only.
18384                                                                  0x2 = EL2 can be executed in either AArch64 or AArch32 state.
18385 
18386                                                                  In CNXXXX, supported in AArch64. */
18387         uint64_t el1                   : 4;  /**< [  7:  4](RO) EL1 Exception level handling.
18388                                                                  All other values are reserved.
18389                                                                  0x0 = EL1 is not implemented.
18390                                                                  0x1 = EL1 can be executed in AArch64 state only.
18391                                                                  0x2 = EL1 can be executed in either AArch64 or AArch32 state.
18392 
18393                                                                  In CNXXXX, supported in AArch64. */
18394         uint64_t el0                   : 4;  /**< [  3:  0](RO) EL0 Exception level handling.
18395                                                                  All other values are reserved.
18396                                                                  0x0 = EL0 is not implemented.
18397                                                                  0x1 = EL0 can be executed in AArch64 state only.
18398                                                                  0x2 = EL0 can be executed in either AArch64 or AArch32 state.
18399 
18400                                                                  In CNXXXX, supported in AArch64. */
18401 #else /* Word 0 - Little Endian */
18402         uint64_t el0                   : 4;  /**< [  3:  0](RO) EL0 Exception level handling.
18403                                                                  All other values are reserved.
18404                                                                  0x0 = EL0 is not implemented.
18405                                                                  0x1 = EL0 can be executed in AArch64 state only.
18406                                                                  0x2 = EL0 can be executed in either AArch64 or AArch32 state.
18407 
18408                                                                  In CNXXXX, supported in AArch64. */
18409         uint64_t el1                   : 4;  /**< [  7:  4](RO) EL1 Exception level handling.
18410                                                                  All other values are reserved.
18411                                                                  0x0 = EL1 is not implemented.
18412                                                                  0x1 = EL1 can be executed in AArch64 state only.
18413                                                                  0x2 = EL1 can be executed in either AArch64 or AArch32 state.
18414 
18415                                                                  In CNXXXX, supported in AArch64. */
18416         uint64_t el2                   : 4;  /**< [ 11:  8](RO) EL2 Exception level handling.
18417                                                                  All other values are reserved.
18418                                                                  0x0 = EL2 is not implemented.
18419                                                                  0x1 = EL2 can be executed in AArch64 state only.
18420                                                                  0x2 = EL2 can be executed in either AArch64 or AArch32 state.
18421 
18422                                                                  In CNXXXX, supported in AArch64. */
18423         uint64_t el3                   : 4;  /**< [ 15: 12](RO) EL3 Exception level handling.
18424                                                                  All other values are reserved.
18425                                                                  0x0 = EL3 is not implemented.
18426                                                                  0x1 = EL3 can be executed in AArch64 state only.
18427                                                                  0x2 = EL3 can be executed in either AArch64 or AArch32 state.
18428 
18429                                                                  In CNXXXX, supported in AArch64. */
18430         uint64_t fp                    : 4;  /**< [ 19: 16](RO) Floating-point.
18431                                                                  All other values are reserved.
18432                                                                  0x0 = Floating-point is implemented.
18433                                                                  0xF = Floating-point is not implemented.
18434 
18435                                                                  In CNXXXX, supported. */
18436         uint64_t advsimd               : 4;  /**< [ 23: 20](RO) Advanced SIMD.
18437                                                                  All other values are reserved.
18438                                                                  0x0 = Advanced SIMD is implemented.
18439                                                                  0xF = Advanced SIMD is not implemented.
18440 
18441                                                                  In CNXXXX, supported. */
18442         uint64_t gic                   : 4;  /**< [ 27: 24](RO) GIC system register interface.
18443                                                                  All other values are reserved.
18444                                                                  0x0 = No GIC system registers are supported.
18445                                                                  0x1 = GICv3 system registers are supported.
18446 
18447                                                                  In CNXXXX, supported. */
18448         uint64_t reserved_28_63        : 36;
18449 #endif /* Word 0 - End */
18450     } cn8;
18451     /* struct bdk_ap_id_aa64pfr0_el1_s cn9; */
18452 };
18453 typedef union bdk_ap_id_aa64pfr0_el1 bdk_ap_id_aa64pfr0_el1_t;
18454 
18455 #define BDK_AP_ID_AA64PFR0_EL1 BDK_AP_ID_AA64PFR0_EL1_FUNC()
18456 static inline uint64_t BDK_AP_ID_AA64PFR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64PFR0_EL1_FUNC(void)18457 static inline uint64_t BDK_AP_ID_AA64PFR0_EL1_FUNC(void)
18458 {
18459     return 0x30000040000ll;
18460 }
18461 
18462 #define typedef_BDK_AP_ID_AA64PFR0_EL1 bdk_ap_id_aa64pfr0_el1_t
18463 #define bustype_BDK_AP_ID_AA64PFR0_EL1 BDK_CSR_TYPE_SYSREG
18464 #define basename_BDK_AP_ID_AA64PFR0_EL1 "AP_ID_AA64PFR0_EL1"
18465 #define busnum_BDK_AP_ID_AA64PFR0_EL1 0
18466 #define arguments_BDK_AP_ID_AA64PFR0_EL1 -1,-1,-1,-1
18467 
18468 /**
18469  * Register (SYSREG) ap_id_aa64pfr1_el1
18470  *
18471  * AP AArch64 Processor Feature Register 1
18472  * Reserved for future expansion of information about implemented
18473  *     processor features in AArch64.
18474  */
18475 union bdk_ap_id_aa64pfr1_el1
18476 {
18477     uint64_t u;
18478     struct bdk_ap_id_aa64pfr1_el1_s
18479     {
18480 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18481         uint64_t reserved_0_63         : 64;
18482 #else /* Word 0 - Little Endian */
18483         uint64_t reserved_0_63         : 64;
18484 #endif /* Word 0 - End */
18485     } s;
18486     /* struct bdk_ap_id_aa64pfr1_el1_s cn; */
18487 };
18488 typedef union bdk_ap_id_aa64pfr1_el1 bdk_ap_id_aa64pfr1_el1_t;
18489 
18490 #define BDK_AP_ID_AA64PFR1_EL1 BDK_AP_ID_AA64PFR1_EL1_FUNC()
18491 static inline uint64_t BDK_AP_ID_AA64PFR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AA64PFR1_EL1_FUNC(void)18492 static inline uint64_t BDK_AP_ID_AA64PFR1_EL1_FUNC(void)
18493 {
18494     return 0x30000040100ll;
18495 }
18496 
18497 #define typedef_BDK_AP_ID_AA64PFR1_EL1 bdk_ap_id_aa64pfr1_el1_t
18498 #define bustype_BDK_AP_ID_AA64PFR1_EL1 BDK_CSR_TYPE_SYSREG
18499 #define basename_BDK_AP_ID_AA64PFR1_EL1 "AP_ID_AA64PFR1_EL1"
18500 #define busnum_BDK_AP_ID_AA64PFR1_EL1 0
18501 #define arguments_BDK_AP_ID_AA64PFR1_EL1 -1,-1,-1,-1
18502 
18503 /**
18504  * Register (SYSREG) ap_id_afr0_el1
18505  *
18506  * AP AArch32 Auxiliary Feature Register 0
18507  * Provides information about the implementation defined features
18508  *     of the PE in AArch32.
18509  */
18510 union bdk_ap_id_afr0_el1
18511 {
18512     uint32_t u;
18513     struct bdk_ap_id_afr0_el1_s
18514     {
18515 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18516         uint32_t reserved_0_31         : 32;
18517 #else /* Word 0 - Little Endian */
18518         uint32_t reserved_0_31         : 32;
18519 #endif /* Word 0 - End */
18520     } s;
18521     /* struct bdk_ap_id_afr0_el1_s cn; */
18522 };
18523 typedef union bdk_ap_id_afr0_el1 bdk_ap_id_afr0_el1_t;
18524 
18525 #define BDK_AP_ID_AFR0_EL1 BDK_AP_ID_AFR0_EL1_FUNC()
18526 static inline uint64_t BDK_AP_ID_AFR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_AFR0_EL1_FUNC(void)18527 static inline uint64_t BDK_AP_ID_AFR0_EL1_FUNC(void)
18528 {
18529     return 0x30000010300ll;
18530 }
18531 
18532 #define typedef_BDK_AP_ID_AFR0_EL1 bdk_ap_id_afr0_el1_t
18533 #define bustype_BDK_AP_ID_AFR0_EL1 BDK_CSR_TYPE_SYSREG
18534 #define basename_BDK_AP_ID_AFR0_EL1 "AP_ID_AFR0_EL1"
18535 #define busnum_BDK_AP_ID_AFR0_EL1 0
18536 #define arguments_BDK_AP_ID_AFR0_EL1 -1,-1,-1,-1
18537 
18538 /**
18539  * Register (SYSREG) ap_id_dfr0_el1
18540  *
18541  * AP AArch32 Debug Feature Register 0
18542  * Provides top level information about the debug system in
18543  *     AArch32.
18544  * This register is RES0 on CNXXXX since we don't support 32bit,
18545  * but it still needs to exist per spec.
18546  */
18547 union bdk_ap_id_dfr0_el1
18548 {
18549     uint32_t u;
18550     struct bdk_ap_id_dfr0_el1_s
18551     {
18552 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18553         uint32_t reserved_0_31         : 32;
18554 #else /* Word 0 - Little Endian */
18555         uint32_t reserved_0_31         : 32;
18556 #endif /* Word 0 - End */
18557     } s;
18558     /* struct bdk_ap_id_dfr0_el1_s cn; */
18559 };
18560 typedef union bdk_ap_id_dfr0_el1 bdk_ap_id_dfr0_el1_t;
18561 
18562 #define BDK_AP_ID_DFR0_EL1 BDK_AP_ID_DFR0_EL1_FUNC()
18563 static inline uint64_t BDK_AP_ID_DFR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_DFR0_EL1_FUNC(void)18564 static inline uint64_t BDK_AP_ID_DFR0_EL1_FUNC(void)
18565 {
18566     return 0x30000010200ll;
18567 }
18568 
18569 #define typedef_BDK_AP_ID_DFR0_EL1 bdk_ap_id_dfr0_el1_t
18570 #define bustype_BDK_AP_ID_DFR0_EL1 BDK_CSR_TYPE_SYSREG
18571 #define basename_BDK_AP_ID_DFR0_EL1 "AP_ID_DFR0_EL1"
18572 #define busnum_BDK_AP_ID_DFR0_EL1 0
18573 #define arguments_BDK_AP_ID_DFR0_EL1 -1,-1,-1,-1
18574 
18575 /**
18576  * Register (SYSREG) ap_id_isar#_el1
18577  *
18578  * AP ARM32 Instruction Set Attribute Register
18579  * Instruction set attribute register
18580  */
18581 union bdk_ap_id_isarx_el1
18582 {
18583     uint32_t u;
18584     struct bdk_ap_id_isarx_el1_s
18585     {
18586 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18587         uint32_t reserved_0_31         : 32;
18588 #else /* Word 0 - Little Endian */
18589         uint32_t reserved_0_31         : 32;
18590 #endif /* Word 0 - End */
18591     } s;
18592     /* struct bdk_ap_id_isarx_el1_s cn; */
18593 };
18594 typedef union bdk_ap_id_isarx_el1 bdk_ap_id_isarx_el1_t;
18595 
18596 static inline uint64_t BDK_AP_ID_ISARX_EL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ID_ISARX_EL1(unsigned long a)18597 static inline uint64_t BDK_AP_ID_ISARX_EL1(unsigned long a)
18598 {
18599     if (a<=5)
18600         return 0x30000020000ll + 0x100ll * ((a) & 0x7);
18601     __bdk_csr_fatal("AP_ID_ISARX_EL1", 1, a, 0, 0, 0);
18602 }
18603 
18604 #define typedef_BDK_AP_ID_ISARX_EL1(a) bdk_ap_id_isarx_el1_t
18605 #define bustype_BDK_AP_ID_ISARX_EL1(a) BDK_CSR_TYPE_SYSREG
18606 #define basename_BDK_AP_ID_ISARX_EL1(a) "AP_ID_ISARX_EL1"
18607 #define busnum_BDK_AP_ID_ISARX_EL1(a) (a)
18608 #define arguments_BDK_AP_ID_ISARX_EL1(a) (a),-1,-1,-1
18609 
18610 /**
18611  * Register (SYSREG) ap_id_isar#_el1_res0
18612  *
18613  * INTERNAL: AP ARM32 Instruction Set Attribute Register
18614  *
18615  * Instruction set attribute register. ARM doesn't actually assign a name to these registers, so
18616  * CNXXXX made up one.
18617  */
18618 union bdk_ap_id_isarx_el1_res0
18619 {
18620     uint32_t u;
18621     struct bdk_ap_id_isarx_el1_res0_s
18622     {
18623 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18624         uint32_t reserved_0_31         : 32;
18625 #else /* Word 0 - Little Endian */
18626         uint32_t reserved_0_31         : 32;
18627 #endif /* Word 0 - End */
18628     } s;
18629     /* struct bdk_ap_id_isarx_el1_res0_s cn; */
18630 };
18631 typedef union bdk_ap_id_isarx_el1_res0 bdk_ap_id_isarx_el1_res0_t;
18632 
18633 static inline uint64_t BDK_AP_ID_ISARX_EL1_RES0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ID_ISARX_EL1_RES0(unsigned long a)18634 static inline uint64_t BDK_AP_ID_ISARX_EL1_RES0(unsigned long a)
18635 {
18636     if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && ((a>=6)&&(a<=7)))
18637         return 0x30000020000ll + 0x100ll * ((a) & 0x7);
18638     __bdk_csr_fatal("AP_ID_ISARX_EL1_RES0", 1, a, 0, 0, 0);
18639 }
18640 
18641 #define typedef_BDK_AP_ID_ISARX_EL1_RES0(a) bdk_ap_id_isarx_el1_res0_t
18642 #define bustype_BDK_AP_ID_ISARX_EL1_RES0(a) BDK_CSR_TYPE_SYSREG
18643 #define basename_BDK_AP_ID_ISARX_EL1_RES0(a) "AP_ID_ISARX_EL1_RES0"
18644 #define busnum_BDK_AP_ID_ISARX_EL1_RES0(a) (a)
18645 #define arguments_BDK_AP_ID_ISARX_EL1_RES0(a) (a),-1,-1,-1
18646 
18647 /**
18648  * Register (SYSREG) ap_id_isar7_el1_res0
18649  *
18650  * INTERNAL: AP ARM32 Instruction Set Attribute Register
18651  *
18652  * Instruction set attribute register. ARM doesn't actually assign a name to these registers, so
18653  * CNXXXX made up one.
18654  */
18655 union bdk_ap_id_isar7_el1_res0
18656 {
18657     uint32_t u;
18658     struct bdk_ap_id_isar7_el1_res0_s
18659     {
18660 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18661         uint32_t reserved_0_31         : 32;
18662 #else /* Word 0 - Little Endian */
18663         uint32_t reserved_0_31         : 32;
18664 #endif /* Word 0 - End */
18665     } s;
18666     /* struct bdk_ap_id_isar7_el1_res0_s cn; */
18667 };
18668 typedef union bdk_ap_id_isar7_el1_res0 bdk_ap_id_isar7_el1_res0_t;
18669 
18670 #define BDK_AP_ID_ISAR7_EL1_RES0 BDK_AP_ID_ISAR7_EL1_RES0_FUNC()
18671 static inline uint64_t BDK_AP_ID_ISAR7_EL1_RES0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_ISAR7_EL1_RES0_FUNC(void)18672 static inline uint64_t BDK_AP_ID_ISAR7_EL1_RES0_FUNC(void)
18673 {
18674     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
18675         return 0x30000020700ll;
18676     __bdk_csr_fatal("AP_ID_ISAR7_EL1_RES0", 0, 0, 0, 0, 0);
18677 }
18678 
18679 #define typedef_BDK_AP_ID_ISAR7_EL1_RES0 bdk_ap_id_isar7_el1_res0_t
18680 #define bustype_BDK_AP_ID_ISAR7_EL1_RES0 BDK_CSR_TYPE_SYSREG
18681 #define basename_BDK_AP_ID_ISAR7_EL1_RES0 "AP_ID_ISAR7_EL1_RES0"
18682 #define busnum_BDK_AP_ID_ISAR7_EL1_RES0 0
18683 #define arguments_BDK_AP_ID_ISAR7_EL1_RES0 -1,-1,-1,-1
18684 
18685 /**
18686  * Register (SYSREG) ap_id_mmfr#_el1
18687  *
18688  * AP ARM32 Memory Model Feature Register
18689  * ARM32 Memory model feature register
18690  */
18691 union bdk_ap_id_mmfrx_el1
18692 {
18693     uint32_t u;
18694     struct bdk_ap_id_mmfrx_el1_s
18695     {
18696 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18697         uint32_t reserved_0_31         : 32;
18698 #else /* Word 0 - Little Endian */
18699         uint32_t reserved_0_31         : 32;
18700 #endif /* Word 0 - End */
18701     } s;
18702     /* struct bdk_ap_id_mmfrx_el1_s cn; */
18703 };
18704 typedef union bdk_ap_id_mmfrx_el1 bdk_ap_id_mmfrx_el1_t;
18705 
18706 static inline uint64_t BDK_AP_ID_MMFRX_EL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_ID_MMFRX_EL1(unsigned long a)18707 static inline uint64_t BDK_AP_ID_MMFRX_EL1(unsigned long a)
18708 {
18709     if (a<=3)
18710         return 0x30000010400ll + 0x100ll * ((a) & 0x3);
18711     __bdk_csr_fatal("AP_ID_MMFRX_EL1", 1, a, 0, 0, 0);
18712 }
18713 
18714 #define typedef_BDK_AP_ID_MMFRX_EL1(a) bdk_ap_id_mmfrx_el1_t
18715 #define bustype_BDK_AP_ID_MMFRX_EL1(a) BDK_CSR_TYPE_SYSREG
18716 #define basename_BDK_AP_ID_MMFRX_EL1(a) "AP_ID_MMFRX_EL1"
18717 #define busnum_BDK_AP_ID_MMFRX_EL1(a) (a)
18718 #define arguments_BDK_AP_ID_MMFRX_EL1(a) (a),-1,-1,-1
18719 
18720 /**
18721  * Register (SYSREG) ap_id_mmfr4_el1
18722  *
18723  * AP AArch32 Memory Model Feature Register 4
18724  * Provides additional information about implemented memory model and memory management support
18725  * in AArch32.
18726  *
18727  * Usage constraints:
18728  *   ID_MMFR4_EL1 is UNDEFINED at EL0.
18729  *   If EL2 is implemented and HCR_EL2.TID3 == 1, then direct reads of ID_MMFR4_EL1 at Non-secure
18730  * EL1 generate a Trap exception to EL2.
18731  *
18732  * Configurations:
18733  *   AArch64 System register ID_MMFR4_EL1 is architecturally mapped to AArch32 System register
18734  * ID_MMFR4.
18735  *   In an implementation that does not include ACTLR2 and HACTLR2 this register is RAZ/WI.
18736  *   In an AArch64-only implementation, this register is UNKNOWN.
18737  */
18738 union bdk_ap_id_mmfr4_el1
18739 {
18740     uint32_t u;
18741     struct bdk_ap_id_mmfr4_el1_s
18742     {
18743 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18744         uint32_t reserved_24_31        : 8;
18745         uint32_t lsm                   : 4;  /**< [ 23: 20](RO) 0x0 = LSMAOE and nTLSMD bit not supported.
18746                                                                  0x1 = LSMAOE and nTLSMD bit supported.
18747 
18748                                                                  All other values reserved. */
18749         uint32_t hpds                  : 4;  /**< [ 19: 16](RO) V8.1: Hierarchical Permission Disables.
18750                                                                  0x0 = Hierarchical Permission Disables not supported.
18751                                                                  0x1 = Hierarchical Permission Disables supported.
18752                                                                  0x2 = Hierarchical Permission Disables and hardware allocation of bits[62:59] supported.
18753 
18754                                                                  All other values reserved.
18755 
18756                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
18757         uint32_t cnp                   : 4;  /**< [ 15: 12](RO) 0x0 = CnP bit not supported.
18758                                                                  0x1 = CnP bit supported.
18759 
18760                                                                  All other values reserved. */
18761         uint32_t xnx                   : 4;  /**< [ 11:  8](RO) 0x0 = EL0/EL1 execute control distinction at stage2 bit not supported.
18762                                                                  0x1 = EL0/EL1 execute control distinction at stage2 bit supported.
18763 
18764                                                                  All other values reserved. */
18765         uint32_t ac2                   : 4;  /**< [  7:  4](RO) Indicates the extension of the ACTLR and HACTLR registers using ACTLR2 and HACTLR2.
18766                                                                    0x0 = ACTLR2 and HACTLR2 are not implemented.
18767                                                                    0x1 = ACTLR2 and HACTLR2 are implemented.
18768 
18769                                                                  All other values are reserved. */
18770         uint32_t specsei               : 4;  /**< [  3:  0](RO) Describes whether the PE can generate SError interrupt exceptions from speculative reads
18771                                                                  of memory, including speculative instruction fetches.
18772                                                                    0x0 = The PE never generates an SError interrupt due to an external abort on a
18773                                                                  speculative read.
18774                                                                    0x1 = The PE might generate an SError interrupt due to an external abort on a
18775                                                                  speculative read. */
18776 #else /* Word 0 - Little Endian */
18777         uint32_t specsei               : 4;  /**< [  3:  0](RO) Describes whether the PE can generate SError interrupt exceptions from speculative reads
18778                                                                  of memory, including speculative instruction fetches.
18779                                                                    0x0 = The PE never generates an SError interrupt due to an external abort on a
18780                                                                  speculative read.
18781                                                                    0x1 = The PE might generate an SError interrupt due to an external abort on a
18782                                                                  speculative read. */
18783         uint32_t ac2                   : 4;  /**< [  7:  4](RO) Indicates the extension of the ACTLR and HACTLR registers using ACTLR2 and HACTLR2.
18784                                                                    0x0 = ACTLR2 and HACTLR2 are not implemented.
18785                                                                    0x1 = ACTLR2 and HACTLR2 are implemented.
18786 
18787                                                                  All other values are reserved. */
18788         uint32_t xnx                   : 4;  /**< [ 11:  8](RO) 0x0 = EL0/EL1 execute control distinction at stage2 bit not supported.
18789                                                                  0x1 = EL0/EL1 execute control distinction at stage2 bit supported.
18790 
18791                                                                  All other values reserved. */
18792         uint32_t cnp                   : 4;  /**< [ 15: 12](RO) 0x0 = CnP bit not supported.
18793                                                                  0x1 = CnP bit supported.
18794 
18795                                                                  All other values reserved. */
18796         uint32_t hpds                  : 4;  /**< [ 19: 16](RO) V8.1: Hierarchical Permission Disables.
18797                                                                  0x0 = Hierarchical Permission Disables not supported.
18798                                                                  0x1 = Hierarchical Permission Disables supported.
18799                                                                  0x2 = Hierarchical Permission Disables and hardware allocation of bits[62:59] supported.
18800 
18801                                                                  All other values reserved.
18802 
18803                                                                  For CNXXXX, if AP_CVMCTL_EL1[ENABLE_V81] is set 0x1, else 0x0. */
18804         uint32_t lsm                   : 4;  /**< [ 23: 20](RO) 0x0 = LSMAOE and nTLSMD bit not supported.
18805                                                                  0x1 = LSMAOE and nTLSMD bit supported.
18806 
18807                                                                  All other values reserved. */
18808         uint32_t reserved_24_31        : 8;
18809 #endif /* Word 0 - End */
18810     } s;
18811     /* struct bdk_ap_id_mmfr4_el1_s cn; */
18812 };
18813 typedef union bdk_ap_id_mmfr4_el1 bdk_ap_id_mmfr4_el1_t;
18814 
18815 #define BDK_AP_ID_MMFR4_EL1 BDK_AP_ID_MMFR4_EL1_FUNC()
18816 static inline uint64_t BDK_AP_ID_MMFR4_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_MMFR4_EL1_FUNC(void)18817 static inline uint64_t BDK_AP_ID_MMFR4_EL1_FUNC(void)
18818 {
18819     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
18820         return 0x30000020600ll;
18821     __bdk_csr_fatal("AP_ID_MMFR4_EL1", 0, 0, 0, 0, 0);
18822 }
18823 
18824 #define typedef_BDK_AP_ID_MMFR4_EL1 bdk_ap_id_mmfr4_el1_t
18825 #define bustype_BDK_AP_ID_MMFR4_EL1 BDK_CSR_TYPE_SYSREG
18826 #define basename_BDK_AP_ID_MMFR4_EL1 "AP_ID_MMFR4_EL1"
18827 #define busnum_BDK_AP_ID_MMFR4_EL1 0
18828 #define arguments_BDK_AP_ID_MMFR4_EL1 -1,-1,-1,-1
18829 
18830 /**
18831  * Register (SYSREG) ap_id_pfr0_el1
18832  *
18833  * AP AArch32 Processor Feature Register 0
18834  * Gives top-level information about the instruction sets
18835  *     supported by the processor in AArch32.
18836  */
18837 union bdk_ap_id_pfr0_el1
18838 {
18839     uint32_t u;
18840     struct bdk_ap_id_pfr0_el1_s
18841     {
18842 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18843         uint32_t ras                   : 4;  /**< [ 31: 28](RO) RAS extension version. The possible values of this field are:
18844                                                                    0x0 = No RAS extension.
18845                                                                    0x1 = Version 1 of the RAS extension present.
18846 
18847                                                                  All other values are reserved. Reserved values might be defined in a future version of the
18848                                                                  architecture. */
18849         uint32_t reserved_16_27        : 12;
18850         uint32_t state3                : 4;  /**< [ 15: 12](RO) T32EE instruction set support.
18851                                                                  All other values are reserved.
18852                                                                  0x0 = Not implemented.
18853                                                                  0x1 = T32EE instruction set implemented. */
18854         uint32_t state2                : 4;  /**< [ 11:  8](RO) Jazelle extension support.
18855                                                                  All other values are reserved.
18856                                                                  0x0 = Not implemented.
18857                                                                  0x1 = Jazelle extension implemented, without clearing of JOSCR[CV] on
18858                                                                      exception entry.
18859                                                                  0x2 = Jazelle extension implemented, with clearing of JOSCR[CV] on
18860                                                                      exception entry. */
18861         uint32_t state1                : 4;  /**< [  7:  4](RO) T32 instruction set support.
18862                                                                  All other values are reserved.
18863                                                                  0x0 = T32 instruction set not implemented.
18864 
18865                                                                  0x1 = T32 encodings before the introduction of Thumb-2 technology
18866                                                                      implemented:
18867                                                                   All instructions are 16-bit.
18868                                                                   A BL or BLX is a pair of 16-bit instructions.
18869                                                                   32-bit instructions other than BL and BLX cannot be encoded.
18870 
18871                                                                  0x3 = T32 encodings after the introduction of Thumb-2 technology
18872                                                                      implemented, for all 16-bit and 32-bit T32 basic instructions. */
18873         uint32_t state0                : 4;  /**< [  3:  0](RO) A32 instruction set support.
18874                                                                  All other values are reserved.
18875                                                                  0x0 = A32 instruction set not implemented.
18876                                                                  0x1 = A32 instruction set implemented. */
18877 #else /* Word 0 - Little Endian */
18878         uint32_t state0                : 4;  /**< [  3:  0](RO) A32 instruction set support.
18879                                                                  All other values are reserved.
18880                                                                  0x0 = A32 instruction set not implemented.
18881                                                                  0x1 = A32 instruction set implemented. */
18882         uint32_t state1                : 4;  /**< [  7:  4](RO) T32 instruction set support.
18883                                                                  All other values are reserved.
18884                                                                  0x0 = T32 instruction set not implemented.
18885 
18886                                                                  0x1 = T32 encodings before the introduction of Thumb-2 technology
18887                                                                      implemented:
18888                                                                   All instructions are 16-bit.
18889                                                                   A BL or BLX is a pair of 16-bit instructions.
18890                                                                   32-bit instructions other than BL and BLX cannot be encoded.
18891 
18892                                                                  0x3 = T32 encodings after the introduction of Thumb-2 technology
18893                                                                      implemented, for all 16-bit and 32-bit T32 basic instructions. */
18894         uint32_t state2                : 4;  /**< [ 11:  8](RO) Jazelle extension support.
18895                                                                  All other values are reserved.
18896                                                                  0x0 = Not implemented.
18897                                                                  0x1 = Jazelle extension implemented, without clearing of JOSCR[CV] on
18898                                                                      exception entry.
18899                                                                  0x2 = Jazelle extension implemented, with clearing of JOSCR[CV] on
18900                                                                      exception entry. */
18901         uint32_t state3                : 4;  /**< [ 15: 12](RO) T32EE instruction set support.
18902                                                                  All other values are reserved.
18903                                                                  0x0 = Not implemented.
18904                                                                  0x1 = T32EE instruction set implemented. */
18905         uint32_t reserved_16_27        : 12;
18906         uint32_t ras                   : 4;  /**< [ 31: 28](RO) RAS extension version. The possible values of this field are:
18907                                                                    0x0 = No RAS extension.
18908                                                                    0x1 = Version 1 of the RAS extension present.
18909 
18910                                                                  All other values are reserved. Reserved values might be defined in a future version of the
18911                                                                  architecture. */
18912 #endif /* Word 0 - End */
18913     } s;
18914     struct bdk_ap_id_pfr0_el1_cn8
18915     {
18916 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
18917         uint32_t reserved_16_31        : 16;
18918         uint32_t state3                : 4;  /**< [ 15: 12](RO) T32EE instruction set support.
18919                                                                  All other values are reserved.
18920                                                                  0x0 = Not implemented.
18921                                                                  0x1 = T32EE instruction set implemented. */
18922         uint32_t state2                : 4;  /**< [ 11:  8](RO) Jazelle extension support.
18923                                                                  All other values are reserved.
18924                                                                  0x0 = Not implemented.
18925                                                                  0x1 = Jazelle extension implemented, without clearing of JOSCR[CV] on
18926                                                                      exception entry.
18927                                                                  0x2 = Jazelle extension implemented, with clearing of JOSCR[CV] on
18928                                                                      exception entry. */
18929         uint32_t state1                : 4;  /**< [  7:  4](RO) T32 instruction set support.
18930                                                                  All other values are reserved.
18931                                                                  0x0 = T32 instruction set not implemented.
18932 
18933                                                                  0x1 = T32 encodings before the introduction of Thumb-2 technology
18934                                                                      implemented:
18935                                                                   All instructions are 16-bit.
18936                                                                   A BL or BLX is a pair of 16-bit instructions.
18937                                                                   32-bit instructions other than BL and BLX cannot be encoded.
18938 
18939                                                                  0x3 = T32 encodings after the introduction of Thumb-2 technology
18940                                                                      implemented, for all 16-bit and 32-bit T32 basic instructions. */
18941         uint32_t state0                : 4;  /**< [  3:  0](RO) A32 instruction set support.
18942                                                                  All other values are reserved.
18943                                                                  0x0 = A32 instruction set not implemented.
18944                                                                  0x1 = A32 instruction set implemented. */
18945 #else /* Word 0 - Little Endian */
18946         uint32_t state0                : 4;  /**< [  3:  0](RO) A32 instruction set support.
18947                                                                  All other values are reserved.
18948                                                                  0x0 = A32 instruction set not implemented.
18949                                                                  0x1 = A32 instruction set implemented. */
18950         uint32_t state1                : 4;  /**< [  7:  4](RO) T32 instruction set support.
18951                                                                  All other values are reserved.
18952                                                                  0x0 = T32 instruction set not implemented.
18953 
18954                                                                  0x1 = T32 encodings before the introduction of Thumb-2 technology
18955                                                                      implemented:
18956                                                                   All instructions are 16-bit.
18957                                                                   A BL or BLX is a pair of 16-bit instructions.
18958                                                                   32-bit instructions other than BL and BLX cannot be encoded.
18959 
18960                                                                  0x3 = T32 encodings after the introduction of Thumb-2 technology
18961                                                                      implemented, for all 16-bit and 32-bit T32 basic instructions. */
18962         uint32_t state2                : 4;  /**< [ 11:  8](RO) Jazelle extension support.
18963                                                                  All other values are reserved.
18964                                                                  0x0 = Not implemented.
18965                                                                  0x1 = Jazelle extension implemented, without clearing of JOSCR[CV] on
18966                                                                      exception entry.
18967                                                                  0x2 = Jazelle extension implemented, with clearing of JOSCR[CV] on
18968                                                                      exception entry. */
18969         uint32_t state3                : 4;  /**< [ 15: 12](RO) T32EE instruction set support.
18970                                                                  All other values are reserved.
18971                                                                  0x0 = Not implemented.
18972                                                                  0x1 = T32EE instruction set implemented. */
18973         uint32_t reserved_16_31        : 16;
18974 #endif /* Word 0 - End */
18975     } cn8;
18976     /* struct bdk_ap_id_pfr0_el1_s cn9; */
18977 };
18978 typedef union bdk_ap_id_pfr0_el1 bdk_ap_id_pfr0_el1_t;
18979 
18980 #define BDK_AP_ID_PFR0_EL1 BDK_AP_ID_PFR0_EL1_FUNC()
18981 static inline uint64_t BDK_AP_ID_PFR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_PFR0_EL1_FUNC(void)18982 static inline uint64_t BDK_AP_ID_PFR0_EL1_FUNC(void)
18983 {
18984     return 0x30000010000ll;
18985 }
18986 
18987 #define typedef_BDK_AP_ID_PFR0_EL1 bdk_ap_id_pfr0_el1_t
18988 #define bustype_BDK_AP_ID_PFR0_EL1 BDK_CSR_TYPE_SYSREG
18989 #define basename_BDK_AP_ID_PFR0_EL1 "AP_ID_PFR0_EL1"
18990 #define busnum_BDK_AP_ID_PFR0_EL1 0
18991 #define arguments_BDK_AP_ID_PFR0_EL1 -1,-1,-1,-1
18992 
18993 /**
18994  * Register (SYSREG) ap_id_pfr1_el1
18995  *
18996  * AP AArch32 Processor Feature Register 1
18997  * Gives information about the programmers' model and extensions
18998  *     support in AArch32.
18999  */
19000 union bdk_ap_id_pfr1_el1
19001 {
19002     uint32_t u;
19003     struct bdk_ap_id_pfr1_el1_s
19004     {
19005 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19006         uint32_t gic                   : 4;  /**< [ 31: 28](RO) GIC CP15 interface.
19007                                                                  All other values are reserved.
19008                                                                  0x0 = No GIC CP15 registers are supported.
19009                                                                  0x1 = GICv3 CP15 registers are supported. */
19010         uint32_t virt_frac             : 4;  /**< [ 27: 24](RO) Virtualization fractional field. When the Virtualization field
19011                                                                      is0b0000
19012                                                                  All other values are reserved.
19013                                                                  This field is only valid when AP_ID_PFR1_EL1[15:12] == 0,
19014                                                                      otherwise it holds the value0b0000
19015                                                                  0x0 = No features from the ARMv7 Virtualization Extensions are
19016                                                                      implemented.
19017                                                                  0x1 = The SCR[SIF] bit is implemented. The modifications to the
19018                                                                      SCR[AW] and SCR[FW] bits are part of the control of whether the
19019                                                                      CPSR[A] and CPSR[F] bits mask the corresponding aborts. The MSR
19020                                                                      (Banked register) and MRS (Banked register) instructions are
19021                                                                      implemented.
19022                                                                  This value is permitted only when AP_ID_PFR1_EL1[Security] is
19023                                                                      not0b0000 */
19024         uint32_t sec_frac              : 4;  /**< [ 23: 20](RO) Security fractional field. When the Security field is0b0000
19025                                                                  All other values are reserved.
19026                                                                  This field is only valid when AP_ID_PFR1_EL1[7:4] == 0, otherwise
19027                                                                      it holds the value0b0000
19028                                                                  0x0 = No features from the ARMv7 Security Extensions are
19029                                                                      implemented.
19030                                                                  0x1 = The implementation includes the VBAR, and the TCR[PD0] and
19031                                                                      TCR[PD1] bits.
19032                                                                  0x2 = As for 0x1. */
19033         uint32_t gentimer              : 4;  /**< [ 19: 16](RO) Generic Timer Extension support.
19034                                                                  All other values are reserved.
19035                                                                  0x0 = Not implemented.
19036                                                                  0x1 = Generic Timer Extension implemented. */
19037         uint32_t virtualization        : 4;  /**< [ 15: 12](RO) Virtualization support.
19038                                                                  All other values are reserved.
19039                                                                  A value of0b0001
19040                                                                  0x0 = EL2 not implemented.
19041                                                                  0x1 = EL2 implemented. */
19042         uint32_t mprogmod              : 4;  /**< [ 11:  8](RO) M profile programmers' model support.
19043                                                                  All other values are reserved.
19044                                                                  0x0 = Not supported.
19045                                                                  0x2 = Support for two-stack programmers' model. */
19046         uint32_t security              : 4;  /**< [  7:  4](RO) Security support.
19047                                                                  All other values are reserved.
19048                                                                  0x0 = EL3 not implemented.
19049                                                                  0x1 = EL3 implemented.
19050                                                                  This includes support for Monitor mode and the SMC
19051                                                                      instruction.
19052                                                                  0x2 = As for 0x1 NSACR[RFR] bit. Not permitted in ARMv8 as the
19053                                                                      NSACR[RFR] bit is RES0. */
19054         uint32_t progmod               : 4;  /**< [  3:  0](RO) Support for the standard programmers' model for ARMv4 and
19055                                                                      later. Model must support User, FIQ, IRQ, Supervisor, Abort,
19056                                                                      Undefined, and System modes.
19057                                                                  All other values are reserved.
19058                                                                  0x0 = Not supported.
19059                                                                  0x1 = Supported. */
19060 #else /* Word 0 - Little Endian */
19061         uint32_t progmod               : 4;  /**< [  3:  0](RO) Support for the standard programmers' model for ARMv4 and
19062                                                                      later. Model must support User, FIQ, IRQ, Supervisor, Abort,
19063                                                                      Undefined, and System modes.
19064                                                                  All other values are reserved.
19065                                                                  0x0 = Not supported.
19066                                                                  0x1 = Supported. */
19067         uint32_t security              : 4;  /**< [  7:  4](RO) Security support.
19068                                                                  All other values are reserved.
19069                                                                  0x0 = EL3 not implemented.
19070                                                                  0x1 = EL3 implemented.
19071                                                                  This includes support for Monitor mode and the SMC
19072                                                                      instruction.
19073                                                                  0x2 = As for 0x1 NSACR[RFR] bit. Not permitted in ARMv8 as the
19074                                                                      NSACR[RFR] bit is RES0. */
19075         uint32_t mprogmod              : 4;  /**< [ 11:  8](RO) M profile programmers' model support.
19076                                                                  All other values are reserved.
19077                                                                  0x0 = Not supported.
19078                                                                  0x2 = Support for two-stack programmers' model. */
19079         uint32_t virtualization        : 4;  /**< [ 15: 12](RO) Virtualization support.
19080                                                                  All other values are reserved.
19081                                                                  A value of0b0001
19082                                                                  0x0 = EL2 not implemented.
19083                                                                  0x1 = EL2 implemented. */
19084         uint32_t gentimer              : 4;  /**< [ 19: 16](RO) Generic Timer Extension support.
19085                                                                  All other values are reserved.
19086                                                                  0x0 = Not implemented.
19087                                                                  0x1 = Generic Timer Extension implemented. */
19088         uint32_t sec_frac              : 4;  /**< [ 23: 20](RO) Security fractional field. When the Security field is0b0000
19089                                                                  All other values are reserved.
19090                                                                  This field is only valid when AP_ID_PFR1_EL1[7:4] == 0, otherwise
19091                                                                      it holds the value0b0000
19092                                                                  0x0 = No features from the ARMv7 Security Extensions are
19093                                                                      implemented.
19094                                                                  0x1 = The implementation includes the VBAR, and the TCR[PD0] and
19095                                                                      TCR[PD1] bits.
19096                                                                  0x2 = As for 0x1. */
19097         uint32_t virt_frac             : 4;  /**< [ 27: 24](RO) Virtualization fractional field. When the Virtualization field
19098                                                                      is0b0000
19099                                                                  All other values are reserved.
19100                                                                  This field is only valid when AP_ID_PFR1_EL1[15:12] == 0,
19101                                                                      otherwise it holds the value0b0000
19102                                                                  0x0 = No features from the ARMv7 Virtualization Extensions are
19103                                                                      implemented.
19104                                                                  0x1 = The SCR[SIF] bit is implemented. The modifications to the
19105                                                                      SCR[AW] and SCR[FW] bits are part of the control of whether the
19106                                                                      CPSR[A] and CPSR[F] bits mask the corresponding aborts. The MSR
19107                                                                      (Banked register) and MRS (Banked register) instructions are
19108                                                                      implemented.
19109                                                                  This value is permitted only when AP_ID_PFR1_EL1[Security] is
19110                                                                      not0b0000 */
19111         uint32_t gic                   : 4;  /**< [ 31: 28](RO) GIC CP15 interface.
19112                                                                  All other values are reserved.
19113                                                                  0x0 = No GIC CP15 registers are supported.
19114                                                                  0x1 = GICv3 CP15 registers are supported. */
19115 #endif /* Word 0 - End */
19116     } s;
19117     /* struct bdk_ap_id_pfr1_el1_s cn; */
19118 };
19119 typedef union bdk_ap_id_pfr1_el1 bdk_ap_id_pfr1_el1_t;
19120 
19121 #define BDK_AP_ID_PFR1_EL1 BDK_AP_ID_PFR1_EL1_FUNC()
19122 static inline uint64_t BDK_AP_ID_PFR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ID_PFR1_EL1_FUNC(void)19123 static inline uint64_t BDK_AP_ID_PFR1_EL1_FUNC(void)
19124 {
19125     return 0x30000010100ll;
19126 }
19127 
19128 #define typedef_BDK_AP_ID_PFR1_EL1 bdk_ap_id_pfr1_el1_t
19129 #define bustype_BDK_AP_ID_PFR1_EL1 BDK_CSR_TYPE_SYSREG
19130 #define basename_BDK_AP_ID_PFR1_EL1 "AP_ID_PFR1_EL1"
19131 #define busnum_BDK_AP_ID_PFR1_EL1 0
19132 #define arguments_BDK_AP_ID_PFR1_EL1 -1,-1,-1,-1
19133 
19134 /**
19135  * Register (SYSREG) ap_ifsr32_el2
19136  *
19137  * AP Instruction Fault Status EL2 Register
19138  * Allows access to the AArch32 IFSR register from AArch64 state
19139  *     only. Its value has no effect on execution in AArch64 state.
19140  */
19141 union bdk_ap_ifsr32_el2
19142 {
19143     uint32_t u;
19144     struct bdk_ap_ifsr32_el2_s
19145     {
19146 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19147         uint32_t reserved_0_31         : 32;
19148 #else /* Word 0 - Little Endian */
19149         uint32_t reserved_0_31         : 32;
19150 #endif /* Word 0 - End */
19151     } s;
19152     struct bdk_ap_ifsr32_el2_cn
19153     {
19154 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19155         uint32_t reserved_13_31        : 19;
19156         uint32_t reserved_12           : 1;
19157         uint32_t reserved_11           : 1;
19158         uint32_t reserved_10           : 1;
19159         uint32_t reserved_9            : 1;
19160         uint32_t reserved_4_8          : 5;
19161         uint32_t reserved_0_3          : 4;
19162 #else /* Word 0 - Little Endian */
19163         uint32_t reserved_0_3          : 4;
19164         uint32_t reserved_4_8          : 5;
19165         uint32_t reserved_9            : 1;
19166         uint32_t reserved_10           : 1;
19167         uint32_t reserved_11           : 1;
19168         uint32_t reserved_12           : 1;
19169         uint32_t reserved_13_31        : 19;
19170 #endif /* Word 0 - End */
19171     } cn;
19172 };
19173 typedef union bdk_ap_ifsr32_el2 bdk_ap_ifsr32_el2_t;
19174 
19175 #define BDK_AP_IFSR32_EL2 BDK_AP_IFSR32_EL2_FUNC()
19176 static inline uint64_t BDK_AP_IFSR32_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_IFSR32_EL2_FUNC(void)19177 static inline uint64_t BDK_AP_IFSR32_EL2_FUNC(void)
19178 {
19179     return 0x30405000100ll;
19180 }
19181 
19182 #define typedef_BDK_AP_IFSR32_EL2 bdk_ap_ifsr32_el2_t
19183 #define bustype_BDK_AP_IFSR32_EL2 BDK_CSR_TYPE_SYSREG
19184 #define basename_BDK_AP_IFSR32_EL2 "AP_IFSR32_EL2"
19185 #define busnum_BDK_AP_IFSR32_EL2 0
19186 #define arguments_BDK_AP_IFSR32_EL2 -1,-1,-1,-1
19187 
19188 /**
19189  * Register (SYSREG) ap_isr_el1
19190  *
19191  * AP Interrupt Status Register
19192  * Shows whether an IRQ, FIQ, or SError interrupt is pending. If
19193  *     EL2 is implemented, an indicated pending interrupt might be a
19194  *     physical interrupt or a virtual interrupt.
19195  */
19196 union bdk_ap_isr_el1
19197 {
19198     uint32_t u;
19199     struct bdk_ap_isr_el1_s
19200     {
19201 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19202         uint32_t reserved_9_31         : 23;
19203         uint32_t aa                    : 1;  /**< [  8:  8](RO) SError pending bit:
19204                                                                  0 = No pending SError.
19205                                                                  1 = An SError interrupt is pending. */
19206         uint32_t i                     : 1;  /**< [  7:  7](RO) IRQ pending bit. Indicates whether an IRQ interrupt is
19207                                                                      pending:
19208                                                                  0 = No pending IRQ.
19209                                                                  1 = An IRQ interrupt is pending. */
19210         uint32_t f                     : 1;  /**< [  6:  6](RO) FIQ pending bit. Indicates whether an FIQ interrupt is
19211                                                                      pending.
19212                                                                  0 = No pending FIQ.
19213                                                                  1 = An FIQ interrupt is pending. */
19214         uint32_t reserved_0_5          : 6;
19215 #else /* Word 0 - Little Endian */
19216         uint32_t reserved_0_5          : 6;
19217         uint32_t f                     : 1;  /**< [  6:  6](RO) FIQ pending bit. Indicates whether an FIQ interrupt is
19218                                                                      pending.
19219                                                                  0 = No pending FIQ.
19220                                                                  1 = An FIQ interrupt is pending. */
19221         uint32_t i                     : 1;  /**< [  7:  7](RO) IRQ pending bit. Indicates whether an IRQ interrupt is
19222                                                                      pending:
19223                                                                  0 = No pending IRQ.
19224                                                                  1 = An IRQ interrupt is pending. */
19225         uint32_t aa                    : 1;  /**< [  8:  8](RO) SError pending bit:
19226                                                                  0 = No pending SError.
19227                                                                  1 = An SError interrupt is pending. */
19228         uint32_t reserved_9_31         : 23;
19229 #endif /* Word 0 - End */
19230     } s;
19231     /* struct bdk_ap_isr_el1_s cn; */
19232 };
19233 typedef union bdk_ap_isr_el1 bdk_ap_isr_el1_t;
19234 
19235 #define BDK_AP_ISR_EL1 BDK_AP_ISR_EL1_FUNC()
19236 static inline uint64_t BDK_AP_ISR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_ISR_EL1_FUNC(void)19237 static inline uint64_t BDK_AP_ISR_EL1_FUNC(void)
19238 {
19239     return 0x3000c010000ll;
19240 }
19241 
19242 #define typedef_BDK_AP_ISR_EL1 bdk_ap_isr_el1_t
19243 #define bustype_BDK_AP_ISR_EL1 BDK_CSR_TYPE_SYSREG
19244 #define basename_BDK_AP_ISR_EL1 "AP_ISR_EL1"
19245 #define busnum_BDK_AP_ISR_EL1 0
19246 #define arguments_BDK_AP_ISR_EL1 -1,-1,-1,-1
19247 
19248 /**
19249  * Register (SYSREG) ap_lorc_el1
19250  *
19251  * AP LORegion Control (v8.1) Register
19252  * v8.1: LORegion Control, being a 64-bit read/write register that is
19253  * accessible from EL1 or above.
19254  *
19255  * When the AP_LORC_EL1[EN] bit is 0, then no acceses match an LORegion
19256  * Note: this has the consequence that if the AP_LORID_EL1 indicates that no
19257  * LORegions are implemented, then the LoadLOAcquire and StoreLORelease
19258  * will therefore behave as LoadAcquire and StoreRelease.
19259  *
19260  * The AP_LORC_EL1[EN] bit is permitted to be cached within a TLB.
19261  * Note: In keeping with the other system registers in the ARMv8
19262  * architecture, the LORC register must be explicitly synchronised for
19263  * changes in the AP_LORC_EL1[DS] field to take effect.
19264  */
19265 union bdk_ap_lorc_el1
19266 {
19267     uint64_t u;
19268     struct bdk_ap_lorc_el1_s
19269     {
19270 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19271         uint64_t reserved_5_63         : 59;
19272         uint64_t ds                    : 3;  /**< [  4:  2](R/W) Descriptor Select, being a number that selects the current LOR
19273                                                                  Descriptor accessed by the AP_LORSA_EL1, AP_LOREA_EL1, AP_LORN_EL1
19274                                                                  registers; If the AP_LORC_EL1[DS] points to a LOR Descriptor that is
19275                                                                  not supported by an implementation then the AP_LOREA_EL1, AP_LORSA_EL1
19276                                                                  and AP_LORN_EL1 are RES0. */
19277         uint64_t reserved_1            : 1;
19278         uint64_t en                    : 1;  /**< [  0:  0](R/W) Enable.
19279                                                                  0 = Disabled (reset value).
19280                                                                  1 = Enabled. */
19281 #else /* Word 0 - Little Endian */
19282         uint64_t en                    : 1;  /**< [  0:  0](R/W) Enable.
19283                                                                  0 = Disabled (reset value).
19284                                                                  1 = Enabled. */
19285         uint64_t reserved_1            : 1;
19286         uint64_t ds                    : 3;  /**< [  4:  2](R/W) Descriptor Select, being a number that selects the current LOR
19287                                                                  Descriptor accessed by the AP_LORSA_EL1, AP_LOREA_EL1, AP_LORN_EL1
19288                                                                  registers; If the AP_LORC_EL1[DS] points to a LOR Descriptor that is
19289                                                                  not supported by an implementation then the AP_LOREA_EL1, AP_LORSA_EL1
19290                                                                  and AP_LORN_EL1 are RES0. */
19291         uint64_t reserved_5_63         : 59;
19292 #endif /* Word 0 - End */
19293     } s;
19294     /* struct bdk_ap_lorc_el1_s cn; */
19295 };
19296 typedef union bdk_ap_lorc_el1 bdk_ap_lorc_el1_t;
19297 
19298 #define BDK_AP_LORC_EL1 BDK_AP_LORC_EL1_FUNC()
19299 static inline uint64_t BDK_AP_LORC_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_LORC_EL1_FUNC(void)19300 static inline uint64_t BDK_AP_LORC_EL1_FUNC(void)
19301 {
19302     return 0x3000a040300ll;
19303 }
19304 
19305 #define typedef_BDK_AP_LORC_EL1 bdk_ap_lorc_el1_t
19306 #define bustype_BDK_AP_LORC_EL1 BDK_CSR_TYPE_SYSREG
19307 #define basename_BDK_AP_LORC_EL1 "AP_LORC_EL1"
19308 #define busnum_BDK_AP_LORC_EL1 0
19309 #define arguments_BDK_AP_LORC_EL1 -1,-1,-1,-1
19310 
19311 /**
19312  * Register (SYSREG) ap_lorea_el1
19313  *
19314  * AP LORegion End Address (v8.1) Register
19315  * v8.1: LORegion End Address being a 64 bit read/write register that is
19316  * accessible from EL1 or above.
19317  * The AP_LOREA_EL1 is permitted to be cached in a TLB.
19318  * If the AP_LORN_EL1[StartAddress] \> AP_LORN_EL1[EndAddress] for a LOR
19319  * Descriptor, then that LOR Descriptor does not match any LORegion.
19320  */
19321 union bdk_ap_lorea_el1
19322 {
19323     uint64_t u;
19324     struct bdk_ap_lorea_el1_s
19325     {
19326 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19327         uint64_t reserved_48_63        : 16;
19328         uint64_t ea                    : 32; /**< [ 47: 16](R/W) End physical address bits \<47:16\>. Bits\<15:0\> of the end address
19329                                                                  are defined to be 0xFFFF. */
19330         uint64_t reserved_0_15         : 16;
19331 #else /* Word 0 - Little Endian */
19332         uint64_t reserved_0_15         : 16;
19333         uint64_t ea                    : 32; /**< [ 47: 16](R/W) End physical address bits \<47:16\>. Bits\<15:0\> of the end address
19334                                                                  are defined to be 0xFFFF. */
19335         uint64_t reserved_48_63        : 16;
19336 #endif /* Word 0 - End */
19337     } s;
19338     /* struct bdk_ap_lorea_el1_s cn; */
19339 };
19340 typedef union bdk_ap_lorea_el1 bdk_ap_lorea_el1_t;
19341 
19342 #define BDK_AP_LOREA_EL1 BDK_AP_LOREA_EL1_FUNC()
19343 static inline uint64_t BDK_AP_LOREA_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_LOREA_EL1_FUNC(void)19344 static inline uint64_t BDK_AP_LOREA_EL1_FUNC(void)
19345 {
19346     return 0x3000a040100ll;
19347 }
19348 
19349 #define typedef_BDK_AP_LOREA_EL1 bdk_ap_lorea_el1_t
19350 #define bustype_BDK_AP_LOREA_EL1 BDK_CSR_TYPE_SYSREG
19351 #define basename_BDK_AP_LOREA_EL1 "AP_LOREA_EL1"
19352 #define busnum_BDK_AP_LOREA_EL1 0
19353 #define arguments_BDK_AP_LOREA_EL1 -1,-1,-1,-1
19354 
19355 /**
19356  * Register (SYSREG) ap_lorid_el1
19357  *
19358  * AP LORegionID (v8.1) Register
19359  * v8.1: The LORegion ID provides an ID register as to how many LORegions
19360  * and LOR Descriptors are supported by the system.
19361  * The AP_LORID_EL1 register is a 64-bit Read-only register accessible from
19362  * EL1 and above.
19363  * If no LOR Descriptors are implemented then the AP_LORC_EL1, AP_LORN_EL1,
19364  * AP_LORSA_EL1 and AP_LOREA_EL1 registers are RES0.
19365  */
19366 union bdk_ap_lorid_el1
19367 {
19368     uint64_t u;
19369     struct bdk_ap_lorid_el1_s
19370     {
19371 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19372         uint64_t reserved_24_63        : 40;
19373         uint64_t ld                    : 8;  /**< [ 23: 16](RO) Number of LOR Descriptors supported by the implementation,
19374                                                                  expressed as binary 8 bit number. */
19375         uint64_t reserved_8_15         : 8;
19376         uint64_t lr                    : 8;  /**< [  7:  0](RO) Number of LORegions supported by the implementation, expressed as
19377                                                                  binary 8 bit number. */
19378 #else /* Word 0 - Little Endian */
19379         uint64_t lr                    : 8;  /**< [  7:  0](RO) Number of LORegions supported by the implementation, expressed as
19380                                                                  binary 8 bit number. */
19381         uint64_t reserved_8_15         : 8;
19382         uint64_t ld                    : 8;  /**< [ 23: 16](RO) Number of LOR Descriptors supported by the implementation,
19383                                                                  expressed as binary 8 bit number. */
19384         uint64_t reserved_24_63        : 40;
19385 #endif /* Word 0 - End */
19386     } s;
19387     /* struct bdk_ap_lorid_el1_s cn; */
19388 };
19389 typedef union bdk_ap_lorid_el1 bdk_ap_lorid_el1_t;
19390 
19391 #define BDK_AP_LORID_EL1 BDK_AP_LORID_EL1_FUNC()
19392 static inline uint64_t BDK_AP_LORID_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_LORID_EL1_FUNC(void)19393 static inline uint64_t BDK_AP_LORID_EL1_FUNC(void)
19394 {
19395     return 0x3000a040700ll;
19396 }
19397 
19398 #define typedef_BDK_AP_LORID_EL1 bdk_ap_lorid_el1_t
19399 #define bustype_BDK_AP_LORID_EL1 BDK_CSR_TYPE_SYSREG
19400 #define basename_BDK_AP_LORID_EL1 "AP_LORID_EL1"
19401 #define busnum_BDK_AP_LORID_EL1 0
19402 #define arguments_BDK_AP_LORID_EL1 -1,-1,-1,-1
19403 
19404 /**
19405  * Register (SYSREG) ap_lorn_el1
19406  *
19407  * AP LORegion Number (v8.1) Register
19408  * v8.1: LORegion Number, being a 64-bit read/write register that is
19409  * accessible from EL1 or above.
19410  * The AP_LORN_EL1 is permitted to be cached in a TLB.
19411  * If the AP_LORN_EL1[Num] bit points to a LORegion that is not supported by
19412  * the implemented, then that LOR Descriptor does not match any LORegion.
19413  */
19414 union bdk_ap_lorn_el1
19415 {
19416     uint64_t u;
19417     struct bdk_ap_lorn_el1_s
19418     {
19419 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19420         uint64_t reserved_2_63         : 62;
19421         uint64_t num                   : 2;  /**< [  1:  0](R/W) LORegion Number.
19422 
19423                                                                  For CNXXXX region number 0 is special and matches all physical
19424                                                                  addresses. */
19425 #else /* Word 0 - Little Endian */
19426         uint64_t num                   : 2;  /**< [  1:  0](R/W) LORegion Number.
19427 
19428                                                                  For CNXXXX region number 0 is special and matches all physical
19429                                                                  addresses. */
19430         uint64_t reserved_2_63         : 62;
19431 #endif /* Word 0 - End */
19432     } s;
19433     /* struct bdk_ap_lorn_el1_s cn; */
19434 };
19435 typedef union bdk_ap_lorn_el1 bdk_ap_lorn_el1_t;
19436 
19437 #define BDK_AP_LORN_EL1 BDK_AP_LORN_EL1_FUNC()
19438 static inline uint64_t BDK_AP_LORN_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_LORN_EL1_FUNC(void)19439 static inline uint64_t BDK_AP_LORN_EL1_FUNC(void)
19440 {
19441     return 0x3000a040200ll;
19442 }
19443 
19444 #define typedef_BDK_AP_LORN_EL1 bdk_ap_lorn_el1_t
19445 #define bustype_BDK_AP_LORN_EL1 BDK_CSR_TYPE_SYSREG
19446 #define basename_BDK_AP_LORN_EL1 "AP_LORN_EL1"
19447 #define busnum_BDK_AP_LORN_EL1 0
19448 #define arguments_BDK_AP_LORN_EL1 -1,-1,-1,-1
19449 
19450 /**
19451  * Register (SYSREG) ap_lorsa_el1
19452  *
19453  * AP LORegion Start Address (v8.1) Register
19454  * v8.1: LORegion Start Address being a 64 bit read/write register that is
19455  * accessible from EL1 or above
19456  * The AP_LORSA_EL1 is permitted to be cached in a TLB.
19457  */
19458 union bdk_ap_lorsa_el1
19459 {
19460     uint64_t u;
19461     struct bdk_ap_lorsa_el1_s
19462     {
19463 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19464         uint64_t reserved_48_63        : 16;
19465         uint64_t sa                    : 32; /**< [ 47: 16](R/W) Start physical address bits \<47:16\>. Bits\<15:0\> of the start
19466                                                                  physical address are defined to be 0x0. */
19467         uint64_t reserved_1_15         : 15;
19468         uint64_t valid                 : 1;  /**< [  0:  0](R/W) indicates whether the LORegion Descriptor is enabled
19469                                                                  0 = Not valid (reset value).
19470                                                                  1 = Valid. */
19471 #else /* Word 0 - Little Endian */
19472         uint64_t valid                 : 1;  /**< [  0:  0](R/W) indicates whether the LORegion Descriptor is enabled
19473                                                                  0 = Not valid (reset value).
19474                                                                  1 = Valid. */
19475         uint64_t reserved_1_15         : 15;
19476         uint64_t sa                    : 32; /**< [ 47: 16](R/W) Start physical address bits \<47:16\>. Bits\<15:0\> of the start
19477                                                                  physical address are defined to be 0x0. */
19478         uint64_t reserved_48_63        : 16;
19479 #endif /* Word 0 - End */
19480     } s;
19481     /* struct bdk_ap_lorsa_el1_s cn; */
19482 };
19483 typedef union bdk_ap_lorsa_el1 bdk_ap_lorsa_el1_t;
19484 
19485 #define BDK_AP_LORSA_EL1 BDK_AP_LORSA_EL1_FUNC()
19486 static inline uint64_t BDK_AP_LORSA_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_LORSA_EL1_FUNC(void)19487 static inline uint64_t BDK_AP_LORSA_EL1_FUNC(void)
19488 {
19489     return 0x3000a040000ll;
19490 }
19491 
19492 #define typedef_BDK_AP_LORSA_EL1 bdk_ap_lorsa_el1_t
19493 #define bustype_BDK_AP_LORSA_EL1 BDK_CSR_TYPE_SYSREG
19494 #define basename_BDK_AP_LORSA_EL1 "AP_LORSA_EL1"
19495 #define busnum_BDK_AP_LORSA_EL1 0
19496 #define arguments_BDK_AP_LORSA_EL1 -1,-1,-1,-1
19497 
19498 /**
19499  * Register (SYSREG) ap_mair_el#
19500  *
19501  * AP Memory Attribute Indirection Register
19502  * Provides the memory attribute encodings corresponding to the
19503  *     possible AttrIndx values in a Long-descriptor format
19504  *     translation table entry for stage 1 translations at EL3.
19505  */
19506 union bdk_ap_mair_elx
19507 {
19508     uint64_t u;
19509     struct bdk_ap_mair_elx_s
19510     {
19511 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19512         uint64_t reserved_0_63         : 64;
19513 #else /* Word 0 - Little Endian */
19514         uint64_t reserved_0_63         : 64;
19515 #endif /* Word 0 - End */
19516     } s;
19517     struct bdk_ap_mair_elx_cn8
19518     {
19519 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19520         uint64_t attr_n                : 64; /**< [ 63:  0](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19521                                                                      Long descriptor format translation table entry, where
19522                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19523 
19524                                                                  Bits [7:4] are encoded as follows:
19525 
19526                                                                  Attr\<n\>[7:4]        Meaning
19527                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19528                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19529                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19530                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19531                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19532                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19533 
19534                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19535                                                                      Policy.
19536 
19537                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19538 
19539                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19540                                                                  not 0000
19541                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19542                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19543                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19544                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19545                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19546                                                                  (RW=00)
19547                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19548                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19549                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19550 
19551                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19552                                                                      Policy.
19553 
19554                                                                  ARMv7's Strongly-ordered and Device memory types have been
19555                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19556 
19557                                                                  The R and W bits in some Attr\<n\> fields have the following
19558                                                                      meanings:
19559 
19560                                                                  R or W      Meaning
19561                                                                  0 = Do not allocate.
19562                                                                  1 = Allocate. */
19563 #else /* Word 0 - Little Endian */
19564         uint64_t attr_n                : 64; /**< [ 63:  0](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19565                                                                      Long descriptor format translation table entry, where
19566                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19567 
19568                                                                  Bits [7:4] are encoded as follows:
19569 
19570                                                                  Attr\<n\>[7:4]        Meaning
19571                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19572                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19573                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19574                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19575                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19576                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19577 
19578                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19579                                                                      Policy.
19580 
19581                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19582 
19583                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19584                                                                  not 0000
19585                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19586                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19587                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19588                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19589                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19590                                                                  (RW=00)
19591                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19592                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19593                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19594 
19595                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19596                                                                      Policy.
19597 
19598                                                                  ARMv7's Strongly-ordered and Device memory types have been
19599                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19600 
19601                                                                  The R and W bits in some Attr\<n\> fields have the following
19602                                                                      meanings:
19603 
19604                                                                  R or W      Meaning
19605                                                                  0 = Do not allocate.
19606                                                                  1 = Allocate. */
19607 #endif /* Word 0 - End */
19608     } cn8;
19609     struct bdk_ap_mair_elx_cn9
19610     {
19611 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
19612         uint64_t attr7                 : 8;  /**< [ 63: 56](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19613                                                                      Long descriptor format translation table entry, where
19614                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19615 
19616                                                                  Bits [7:4] are encoded as follows:
19617 
19618                                                                  Attr\<n\>[7:4]        Meaning
19619                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19620                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19621                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19622                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19623                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19624                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19625 
19626                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19627                                                                      Policy.
19628 
19629                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19630 
19631                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19632                                                                  not 0000
19633                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19634                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19635                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19636                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19637                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19638                                                                  (RW=00)
19639                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19640                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19641                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19642 
19643                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19644                                                                      Policy.
19645 
19646                                                                  ARMv7's Strongly-ordered and Device memory types have been
19647                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19648 
19649                                                                  The R and W bits in some Attr\<n\> fields have the following
19650                                                                      meanings:
19651 
19652                                                                  R or W      Meaning
19653                                                                  0 = Do not allocate.
19654                                                                  1 = Allocate. */
19655         uint64_t attr6                 : 8;  /**< [ 55: 48](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19656                                                                      Long descriptor format translation table entry, where
19657                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19658 
19659                                                                  Bits [7:4] are encoded as follows:
19660 
19661                                                                  Attr\<n\>[7:4]        Meaning
19662                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19663                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19664                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19665                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19666                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19667                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19668 
19669                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19670                                                                      Policy.
19671 
19672                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19673 
19674                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19675                                                                  not 0000
19676                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19677                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19678                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19679                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19680                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19681                                                                  (RW=00)
19682                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19683                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19684                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19685 
19686                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19687                                                                      Policy.
19688 
19689                                                                  ARMv7's Strongly-ordered and Device memory types have been
19690                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19691 
19692                                                                  The R and W bits in some Attr\<n\> fields have the following
19693                                                                      meanings:
19694 
19695                                                                  R or W      Meaning
19696                                                                  0 = Do not allocate.
19697                                                                  1 = Allocate. */
19698         uint64_t attr5                 : 8;  /**< [ 47: 40](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19699                                                                      Long descriptor format translation table entry, where
19700                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19701 
19702                                                                  Bits [7:4] are encoded as follows:
19703 
19704                                                                  Attr\<n\>[7:4]        Meaning
19705                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19706                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19707                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19708                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19709                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19710                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19711 
19712                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19713                                                                      Policy.
19714 
19715                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19716 
19717                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19718                                                                  not 0000
19719                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19720                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19721                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19722                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19723                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19724                                                                  (RW=00)
19725                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19726                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19727                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19728 
19729                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19730                                                                      Policy.
19731 
19732                                                                  ARMv7's Strongly-ordered and Device memory types have been
19733                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19734 
19735                                                                  The R and W bits in some Attr\<n\> fields have the following
19736                                                                      meanings:
19737 
19738                                                                  R or W      Meaning
19739                                                                  0 = Do not allocate.
19740                                                                  1 = Allocate. */
19741         uint64_t attr4                 : 8;  /**< [ 39: 32](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19742                                                                      Long descriptor format translation table entry, where
19743                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19744 
19745                                                                  Bits [7:4] are encoded as follows:
19746 
19747                                                                  Attr\<n\>[7:4]        Meaning
19748                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19749                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19750                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19751                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19752                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19753                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19754 
19755                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19756                                                                      Policy.
19757 
19758                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19759 
19760                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19761                                                                  not 0000
19762                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19763                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19764                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19765                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19766                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19767                                                                  (RW=00)
19768                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19769                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19770                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19771 
19772                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19773                                                                      Policy.
19774 
19775                                                                  ARMv7's Strongly-ordered and Device memory types have been
19776                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19777 
19778                                                                  The R and W bits in some Attr\<n\> fields have the following
19779                                                                      meanings:
19780 
19781                                                                  R or W      Meaning
19782                                                                  0 = Do not allocate.
19783                                                                  1 = Allocate. */
19784         uint64_t attr3                 : 8;  /**< [ 31: 24](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19785                                                                      Long descriptor format translation table entry, where
19786                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19787 
19788                                                                  Bits [7:4] are encoded as follows:
19789 
19790                                                                  Attr\<n\>[7:4]        Meaning
19791                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19792                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19793                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19794                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19795                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19796                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19797 
19798                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19799                                                                      Policy.
19800 
19801                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19802 
19803                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19804                                                                  not 0000
19805                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19806                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19807                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19808                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19809                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19810                                                                  (RW=00)
19811                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19812                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19813                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19814 
19815                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19816                                                                      Policy.
19817 
19818                                                                  ARMv7's Strongly-ordered and Device memory types have been
19819                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19820 
19821                                                                  The R and W bits in some Attr\<n\> fields have the following
19822                                                                      meanings:
19823 
19824                                                                  R or W      Meaning
19825                                                                  0 = Do not allocate.
19826                                                                  1 = Allocate. */
19827         uint64_t attr2                 : 8;  /**< [ 23: 16](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19828                                                                      Long descriptor format translation table entry, where
19829                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19830 
19831                                                                  Bits [7:4] are encoded as follows:
19832 
19833                                                                  Attr\<n\>[7:4]        Meaning
19834                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19835                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19836                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19837                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19838                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19839                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19840 
19841                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19842                                                                      Policy.
19843 
19844                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19845 
19846                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19847                                                                  not 0000
19848                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19849                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19850                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19851                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19852                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19853                                                                  (RW=00)
19854                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19855                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19856                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19857 
19858                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19859                                                                      Policy.
19860 
19861                                                                  ARMv7's Strongly-ordered and Device memory types have been
19862                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19863 
19864                                                                  The R and W bits in some Attr\<n\> fields have the following
19865                                                                      meanings:
19866 
19867                                                                  R or W      Meaning
19868                                                                  0 = Do not allocate.
19869                                                                  1 = Allocate. */
19870         uint64_t attr1                 : 8;  /**< [ 15:  8](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19871                                                                      Long descriptor format translation table entry, where
19872                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19873 
19874                                                                  Bits [7:4] are encoded as follows:
19875 
19876                                                                  Attr\<n\>[7:4]        Meaning
19877                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19878                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19879                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19880                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19881                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19882                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19883 
19884                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19885                                                                      Policy.
19886 
19887                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19888 
19889                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19890                                                                  not 0000
19891                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19892                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19893                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19894                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19895                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19896                                                                  (RW=00)
19897                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19898                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19899                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19900 
19901                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19902                                                                      Policy.
19903 
19904                                                                  ARMv7's Strongly-ordered and Device memory types have been
19905                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19906 
19907                                                                  The R and W bits in some Attr\<n\> fields have the following
19908                                                                      meanings:
19909 
19910                                                                  R or W      Meaning
19911                                                                  0 = Do not allocate.
19912                                                                  1 = Allocate. */
19913         uint64_t attr0                 : 8;  /**< [  7:  0](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19914                                                                      Long descriptor format translation table entry, where
19915                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19916 
19917                                                                  Bits [7:4] are encoded as follows:
19918 
19919                                                                  Attr\<n\>[7:4]        Meaning
19920                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19921                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19922                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19923                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19924                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19925                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19926 
19927                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19928                                                                      Policy.
19929 
19930                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19931 
19932                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19933                                                                  not 0000
19934                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19935                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19936                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19937                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19938                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19939                                                                  (RW=00)
19940                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19941                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19942                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19943 
19944                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19945                                                                      Policy.
19946 
19947                                                                  ARMv7's Strongly-ordered and Device memory types have been
19948                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19949 
19950                                                                  The R and W bits in some Attr\<n\> fields have the following
19951                                                                      meanings:
19952 
19953                                                                  R or W      Meaning
19954                                                                  0 = Do not allocate.
19955                                                                  1 = Allocate. */
19956 #else /* Word 0 - Little Endian */
19957         uint64_t attr0                 : 8;  /**< [  7:  0](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
19958                                                                      Long descriptor format translation table entry, where
19959                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
19960 
19961                                                                  Bits [7:4] are encoded as follows:
19962 
19963                                                                  Attr\<n\>[7:4]        Meaning
19964                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
19965                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
19966                                                                  0b0100      Normal Memory, Outer Non-Cacheable
19967                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
19968                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
19969                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
19970 
19971                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
19972                                                                      Policy.
19973 
19974                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
19975 
19976                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
19977                                                                  not 0000
19978                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
19979                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
19980                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
19981                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
19982                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
19983                                                                  (RW=00)
19984                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
19985                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
19986                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
19987 
19988                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
19989                                                                      Policy.
19990 
19991                                                                  ARMv7's Strongly-ordered and Device memory types have been
19992                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
19993 
19994                                                                  The R and W bits in some Attr\<n\> fields have the following
19995                                                                      meanings:
19996 
19997                                                                  R or W      Meaning
19998                                                                  0 = Do not allocate.
19999                                                                  1 = Allocate. */
20000         uint64_t attr1                 : 8;  /**< [ 15:  8](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
20001                                                                      Long descriptor format translation table entry, where
20002                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
20003 
20004                                                                  Bits [7:4] are encoded as follows:
20005 
20006                                                                  Attr\<n\>[7:4]        Meaning
20007                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
20008                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
20009                                                                  0b0100      Normal Memory, Outer Non-Cacheable
20010                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
20011                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
20012                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
20013 
20014                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
20015                                                                      Policy.
20016 
20017                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
20018 
20019                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
20020                                                                  not 0000
20021                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
20022                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
20023                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
20024                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
20025                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
20026                                                                  (RW=00)
20027                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
20028                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
20029                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
20030 
20031                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
20032                                                                      Policy.
20033 
20034                                                                  ARMv7's Strongly-ordered and Device memory types have been
20035                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
20036 
20037                                                                  The R and W bits in some Attr\<n\> fields have the following
20038                                                                      meanings:
20039 
20040                                                                  R or W      Meaning
20041                                                                  0 = Do not allocate.
20042                                                                  1 = Allocate. */
20043         uint64_t attr2                 : 8;  /**< [ 23: 16](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
20044                                                                      Long descriptor format translation table entry, where
20045                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
20046 
20047                                                                  Bits [7:4] are encoded as follows:
20048 
20049                                                                  Attr\<n\>[7:4]        Meaning
20050                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
20051                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
20052                                                                  0b0100      Normal Memory, Outer Non-Cacheable
20053                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
20054                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
20055                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
20056 
20057                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
20058                                                                      Policy.
20059 
20060                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
20061 
20062                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
20063                                                                  not 0000
20064                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
20065                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
20066                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
20067                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
20068                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
20069                                                                  (RW=00)
20070                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
20071                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
20072                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
20073 
20074                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
20075                                                                      Policy.
20076 
20077                                                                  ARMv7's Strongly-ordered and Device memory types have been
20078                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
20079 
20080                                                                  The R and W bits in some Attr\<n\> fields have the following
20081                                                                      meanings:
20082 
20083                                                                  R or W      Meaning
20084                                                                  0 = Do not allocate.
20085                                                                  1 = Allocate. */
20086         uint64_t attr3                 : 8;  /**< [ 31: 24](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
20087                                                                      Long descriptor format translation table entry, where
20088                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
20089 
20090                                                                  Bits [7:4] are encoded as follows:
20091 
20092                                                                  Attr\<n\>[7:4]        Meaning
20093                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
20094                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
20095                                                                  0b0100      Normal Memory, Outer Non-Cacheable
20096                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
20097                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
20098                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
20099 
20100                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
20101                                                                      Policy.
20102 
20103                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
20104 
20105                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
20106                                                                  not 0000
20107                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
20108                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
20109                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
20110                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
20111                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
20112                                                                  (RW=00)
20113                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
20114                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
20115                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
20116 
20117                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
20118                                                                      Policy.
20119 
20120                                                                  ARMv7's Strongly-ordered and Device memory types have been
20121                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
20122 
20123                                                                  The R and W bits in some Attr\<n\> fields have the following
20124                                                                      meanings:
20125 
20126                                                                  R or W      Meaning
20127                                                                  0 = Do not allocate.
20128                                                                  1 = Allocate. */
20129         uint64_t attr4                 : 8;  /**< [ 39: 32](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
20130                                                                      Long descriptor format translation table entry, where
20131                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
20132 
20133                                                                  Bits [7:4] are encoded as follows:
20134 
20135                                                                  Attr\<n\>[7:4]        Meaning
20136                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
20137                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
20138                                                                  0b0100      Normal Memory, Outer Non-Cacheable
20139                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
20140                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
20141                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
20142 
20143                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
20144                                                                      Policy.
20145 
20146                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
20147 
20148                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
20149                                                                  not 0000
20150                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
20151                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
20152                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
20153                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
20154                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
20155                                                                  (RW=00)
20156                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
20157                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
20158                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
20159 
20160                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
20161                                                                      Policy.
20162 
20163                                                                  ARMv7's Strongly-ordered and Device memory types have been
20164                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
20165 
20166                                                                  The R and W bits in some Attr\<n\> fields have the following
20167                                                                      meanings:
20168 
20169                                                                  R or W      Meaning
20170                                                                  0 = Do not allocate.
20171                                                                  1 = Allocate. */
20172         uint64_t attr5                 : 8;  /**< [ 47: 40](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
20173                                                                      Long descriptor format translation table entry, where
20174                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
20175 
20176                                                                  Bits [7:4] are encoded as follows:
20177 
20178                                                                  Attr\<n\>[7:4]        Meaning
20179                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
20180                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
20181                                                                  0b0100      Normal Memory, Outer Non-Cacheable
20182                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
20183                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
20184                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
20185 
20186                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
20187                                                                      Policy.
20188 
20189                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
20190 
20191                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
20192                                                                  not 0000
20193                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
20194                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
20195                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
20196                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
20197                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
20198                                                                  (RW=00)
20199                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
20200                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
20201                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
20202 
20203                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
20204                                                                      Policy.
20205 
20206                                                                  ARMv7's Strongly-ordered and Device memory types have been
20207                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
20208 
20209                                                                  The R and W bits in some Attr\<n\> fields have the following
20210                                                                      meanings:
20211 
20212                                                                  R or W      Meaning
20213                                                                  0 = Do not allocate.
20214                                                                  1 = Allocate. */
20215         uint64_t attr6                 : 8;  /**< [ 55: 48](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
20216                                                                      Long descriptor format translation table entry, where
20217                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
20218 
20219                                                                  Bits [7:4] are encoded as follows:
20220 
20221                                                                  Attr\<n\>[7:4]        Meaning
20222                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
20223                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
20224                                                                  0b0100      Normal Memory, Outer Non-Cacheable
20225                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
20226                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
20227                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
20228 
20229                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
20230                                                                      Policy.
20231 
20232                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
20233 
20234                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
20235                                                                  not 0000
20236                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
20237                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
20238                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
20239                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
20240                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
20241                                                                  (RW=00)
20242                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
20243                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
20244                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
20245 
20246                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
20247                                                                      Policy.
20248 
20249                                                                  ARMv7's Strongly-ordered and Device memory types have been
20250                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
20251 
20252                                                                  The R and W bits in some Attr\<n\> fields have the following
20253                                                                      meanings:
20254 
20255                                                                  R or W      Meaning
20256                                                                  0 = Do not allocate.
20257                                                                  1 = Allocate. */
20258         uint64_t attr7                 : 8;  /**< [ 63: 56](R/W) The memory attribute encoding for an AttrIndx[2:0] entry in a
20259                                                                      Long descriptor format translation table entry, where
20260                                                                      AttrIndx[2:0] gives the value of \<n\> in Attr\<n\>.
20261 
20262                                                                  Bits [7:4] are encoded as follows:
20263 
20264                                                                  Attr\<n\>[7:4]        Meaning
20265                                                                  0b0000      Device memory. See encoding of Attr\<n\>[3:0] for the type of Device memory.
20266                                                                  0b00RW0b00  Normal Memory, Outer Write-through transient
20267                                                                  0b0100      Normal Memory, Outer Non-Cacheable
20268                                                                  0b01RW0b00  Normal Memory, Outer Write-back transient
20269                                                                  0b10RW      Normal Memory, Outer Write-through non-transient
20270                                                                  0b11RW      Normal Memory, Outer Write-back non-transient
20271 
20272                                                                  R = Outer Read Allocate Policy, W = Outer Write Allocate
20273                                                                      Policy.
20274 
20275                                                                  The meaning of bits [3:0] depends on the value of bits [7:4]:
20276 
20277                                                                  Attr\<n\>[3:0]        Meaning when Attr\<n\>[7:4] is 0000       Meaning when Attr\<n\>[7:4] is
20278                                                                  not 0000
20279                                                                  0b0000      Device-nGnRnE memory     UNPREDICTABLE
20280                                                                  0b00RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through transient
20281                                                                  0b0100      Device-nGnRE memory     Normal memory, Inner Non-Cacheable
20282                                                                  0b01RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back transient
20283                                                                  0b1000      Device-nGRE memory      Normal Memory, Inner Write-through non-transient
20284                                                                  (RW=00)
20285                                                                  0b10RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-through non-transient
20286                                                                  0b1100      Device-GRE memory       Normal Memory, Inner Write-back non-transient (RW=00)
20287                                                                  0b11RW0b00   UNPREDICTABLE  Normal Memory, Inner Write-back non-transient
20288 
20289                                                                  R = Inner Read Allocate Policy, W = Inner Write Allocate
20290                                                                      Policy.
20291 
20292                                                                  ARMv7's Strongly-ordered and Device memory types have been
20293                                                                      renamed to Device-nGnRnE and Device-nGnRE in ARMv8.
20294 
20295                                                                  The R and W bits in some Attr\<n\> fields have the following
20296                                                                      meanings:
20297 
20298                                                                  R or W      Meaning
20299                                                                  0 = Do not allocate.
20300                                                                  1 = Allocate. */
20301 #endif /* Word 0 - End */
20302     } cn9;
20303 };
20304 typedef union bdk_ap_mair_elx bdk_ap_mair_elx_t;
20305 
20306 static inline uint64_t BDK_AP_MAIR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_MAIR_ELX(unsigned long a)20307 static inline uint64_t BDK_AP_MAIR_ELX(unsigned long a)
20308 {
20309     if ((a>=1)&&(a<=3))
20310         return 0x3000a020000ll + 0ll * ((a) & 0x3);
20311     __bdk_csr_fatal("AP_MAIR_ELX", 1, a, 0, 0, 0);
20312 }
20313 
20314 #define typedef_BDK_AP_MAIR_ELX(a) bdk_ap_mair_elx_t
20315 #define bustype_BDK_AP_MAIR_ELX(a) BDK_CSR_TYPE_SYSREG
20316 #define basename_BDK_AP_MAIR_ELX(a) "AP_MAIR_ELX"
20317 #define busnum_BDK_AP_MAIR_ELX(a) (a)
20318 #define arguments_BDK_AP_MAIR_ELX(a) (a),-1,-1,-1
20319 
20320 /**
20321  * Register (SYSREG) ap_mair_el12
20322  *
20323  * AP Memory Attribute Indirection Register
20324  * Alias of ESR_EL1 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
20325  */
20326 union bdk_ap_mair_el12
20327 {
20328     uint64_t u;
20329     struct bdk_ap_mair_el12_s
20330     {
20331 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
20332         uint64_t reserved_0_63         : 64;
20333 #else /* Word 0 - Little Endian */
20334         uint64_t reserved_0_63         : 64;
20335 #endif /* Word 0 - End */
20336     } s;
20337     /* struct bdk_ap_mair_el12_s cn; */
20338 };
20339 typedef union bdk_ap_mair_el12 bdk_ap_mair_el12_t;
20340 
20341 #define BDK_AP_MAIR_EL12 BDK_AP_MAIR_EL12_FUNC()
20342 static inline uint64_t BDK_AP_MAIR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_MAIR_EL12_FUNC(void)20343 static inline uint64_t BDK_AP_MAIR_EL12_FUNC(void)
20344 {
20345     return 0x3050a020000ll;
20346 }
20347 
20348 #define typedef_BDK_AP_MAIR_EL12 bdk_ap_mair_el12_t
20349 #define bustype_BDK_AP_MAIR_EL12 BDK_CSR_TYPE_SYSREG
20350 #define basename_BDK_AP_MAIR_EL12 "AP_MAIR_EL12"
20351 #define busnum_BDK_AP_MAIR_EL12 0
20352 #define arguments_BDK_AP_MAIR_EL12 -1,-1,-1,-1
20353 
20354 /**
20355  * Register (SYSREG) ap_mdccint_el1
20356  *
20357  * AP Monitor Debug Comms Channel Interrupt Enable Register
20358  * Enables interrupt requests to be signaled based on the DCC
20359  *     status flags.
20360  */
20361 union bdk_ap_mdccint_el1
20362 {
20363     uint32_t u;
20364     struct bdk_ap_mdccint_el1_s
20365     {
20366 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
20367         uint32_t reserved_31           : 1;
20368         uint32_t rx                    : 1;  /**< [ 30: 30](R/W) DCC interrupt request enable control for DTRRX. Enables a
20369                                                                      common COMMIRQ interrupt request to be signaled based on the
20370                                                                      DCC status flags.
20371 
20372                                                                  If legacy COMMRX and COMMTX signals are implemented, then
20373                                                                      these are not affected by the value of this bit.
20374                                                                  0 = No interrupt request generated by DTRRX.
20375                                                                  1 = Interrupt request will be generated on RXfull == 1. */
20376         uint32_t tx                    : 1;  /**< [ 29: 29](R/W) DCC interrupt request enable control for DTRTX. Enables a
20377                                                                      common COMMIRQ interrupt request to be signaled based on the
20378                                                                      DCC status flags.
20379 
20380                                                                  If legacy COMMRX and COMMTX signals are implemented, then
20381                                                                      these are not affected by the value of this bit.
20382                                                                  0 = No interrupt request generated by DTRTX.
20383                                                                  1 = Interrupt request will be generated on TXfull == 0. */
20384         uint32_t reserved_0_28         : 29;
20385 #else /* Word 0 - Little Endian */
20386         uint32_t reserved_0_28         : 29;
20387         uint32_t tx                    : 1;  /**< [ 29: 29](R/W) DCC interrupt request enable control for DTRTX. Enables a
20388                                                                      common COMMIRQ interrupt request to be signaled based on the
20389                                                                      DCC status flags.
20390 
20391                                                                  If legacy COMMRX and COMMTX signals are implemented, then
20392                                                                      these are not affected by the value of this bit.
20393                                                                  0 = No interrupt request generated by DTRTX.
20394                                                                  1 = Interrupt request will be generated on TXfull == 0. */
20395         uint32_t rx                    : 1;  /**< [ 30: 30](R/W) DCC interrupt request enable control for DTRRX. Enables a
20396                                                                      common COMMIRQ interrupt request to be signaled based on the
20397                                                                      DCC status flags.
20398 
20399                                                                  If legacy COMMRX and COMMTX signals are implemented, then
20400                                                                      these are not affected by the value of this bit.
20401                                                                  0 = No interrupt request generated by DTRRX.
20402                                                                  1 = Interrupt request will be generated on RXfull == 1. */
20403         uint32_t reserved_31           : 1;
20404 #endif /* Word 0 - End */
20405     } s;
20406     /* struct bdk_ap_mdccint_el1_s cn; */
20407 };
20408 typedef union bdk_ap_mdccint_el1 bdk_ap_mdccint_el1_t;
20409 
20410 #define BDK_AP_MDCCINT_EL1 BDK_AP_MDCCINT_EL1_FUNC()
20411 static inline uint64_t BDK_AP_MDCCINT_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_MDCCINT_EL1_FUNC(void)20412 static inline uint64_t BDK_AP_MDCCINT_EL1_FUNC(void)
20413 {
20414     return 0x20000020000ll;
20415 }
20416 
20417 #define typedef_BDK_AP_MDCCINT_EL1 bdk_ap_mdccint_el1_t
20418 #define bustype_BDK_AP_MDCCINT_EL1 BDK_CSR_TYPE_SYSREG
20419 #define basename_BDK_AP_MDCCINT_EL1 "AP_MDCCINT_EL1"
20420 #define busnum_BDK_AP_MDCCINT_EL1 0
20421 #define arguments_BDK_AP_MDCCINT_EL1 -1,-1,-1,-1
20422 
20423 /**
20424  * Register (SYSREG) ap_mdccsr_el0
20425  *
20426  * AP Monitor Debug Comms Channel Status Register
20427  * Main control register for the debug implementation, containing
20428  *     flow-control flags for the DCC. This is an internal, read-only
20429  *     view.
20430  */
20431 union bdk_ap_mdccsr_el0
20432 {
20433     uint32_t u;
20434     struct bdk_ap_mdccsr_el0_s
20435     {
20436 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
20437         uint32_t reserved_31           : 1;
20438         uint32_t rxfull                : 1;  /**< [ 30: 30](RO) DTRRX full. Read-only view of the equivalent bit in the EDSCR. */
20439         uint32_t txfull                : 1;  /**< [ 29: 29](RO) DTRTX full. Read-only view of the equivalent bit in the EDSCR. */
20440         uint32_t reserved_0_28         : 29;
20441 #else /* Word 0 - Little Endian */
20442         uint32_t reserved_0_28         : 29;
20443         uint32_t txfull                : 1;  /**< [ 29: 29](RO) DTRTX full. Read-only view of the equivalent bit in the EDSCR. */
20444         uint32_t rxfull                : 1;  /**< [ 30: 30](RO) DTRRX full. Read-only view of the equivalent bit in the EDSCR. */
20445         uint32_t reserved_31           : 1;
20446 #endif /* Word 0 - End */
20447     } s;
20448     struct bdk_ap_mdccsr_el0_cn
20449     {
20450 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
20451         uint32_t reserved_31           : 1;
20452         uint32_t rxfull                : 1;  /**< [ 30: 30](RO) DTRRX full. Read-only view of the equivalent bit in the EDSCR. */
20453         uint32_t txfull                : 1;  /**< [ 29: 29](RO) DTRTX full. Read-only view of the equivalent bit in the EDSCR. */
20454         uint32_t reserved_19_28        : 10;
20455         uint32_t reserved_15_18        : 4;
20456         uint32_t reserved_13_14        : 2;
20457         uint32_t reserved_12           : 1;
20458         uint32_t reserved_6_11         : 6;
20459         uint32_t reserved_2_5          : 4;
20460         uint32_t reserved_0_1          : 2;
20461 #else /* Word 0 - Little Endian */
20462         uint32_t reserved_0_1          : 2;
20463         uint32_t reserved_2_5          : 4;
20464         uint32_t reserved_6_11         : 6;
20465         uint32_t reserved_12           : 1;
20466         uint32_t reserved_13_14        : 2;
20467         uint32_t reserved_15_18        : 4;
20468         uint32_t reserved_19_28        : 10;
20469         uint32_t txfull                : 1;  /**< [ 29: 29](RO) DTRTX full. Read-only view of the equivalent bit in the EDSCR. */
20470         uint32_t rxfull                : 1;  /**< [ 30: 30](RO) DTRRX full. Read-only view of the equivalent bit in the EDSCR. */
20471         uint32_t reserved_31           : 1;
20472 #endif /* Word 0 - End */
20473     } cn;
20474 };
20475 typedef union bdk_ap_mdccsr_el0 bdk_ap_mdccsr_el0_t;
20476 
20477 #define BDK_AP_MDCCSR_EL0 BDK_AP_MDCCSR_EL0_FUNC()
20478 static inline uint64_t BDK_AP_MDCCSR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_MDCCSR_EL0_FUNC(void)20479 static inline uint64_t BDK_AP_MDCCSR_EL0_FUNC(void)
20480 {
20481     return 0x20300010000ll;
20482 }
20483 
20484 #define typedef_BDK_AP_MDCCSR_EL0 bdk_ap_mdccsr_el0_t
20485 #define bustype_BDK_AP_MDCCSR_EL0 BDK_CSR_TYPE_SYSREG
20486 #define basename_BDK_AP_MDCCSR_EL0 "AP_MDCCSR_EL0"
20487 #define busnum_BDK_AP_MDCCSR_EL0 0
20488 #define arguments_BDK_AP_MDCCSR_EL0 -1,-1,-1,-1
20489 
20490 /**
20491  * Register (SYSREG) ap_mdcr_el2
20492  *
20493  * AP Monitor Debug Configuration EL2 Register
20494  * Provides configuration options for the Virtualization
20495  *     extensions to self-hosted debug and the Performance Monitors
20496  *     extension.
20497  */
20498 union bdk_ap_mdcr_el2
20499 {
20500     uint32_t u;
20501     struct bdk_ap_mdcr_el2_s
20502     {
20503 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
20504         uint32_t reserved_18_31        : 14;
20505         uint32_t hpmd                  : 1;  /**< [ 17: 17](R/W) v8.1: Hyp performance monitors disable. This prohibits event counting
20506                                                                  at EL2.
20507                                                                  0 = Event counting allowed at EL2.
20508                                                                  1 = Event counting prohibited at EL2, unless overridden by
20509                                                                          the authentication interface.
20510 
20511                                                                  Note: This behavior is independent of the value of the AP_HCR_EL2[E2H]
20512                                                                  bit.
20513                                                                  This control applies only to:
20514                                                                  The counters in the range [0.[HPMN]).
20515                                                                  If AP_PMCR_EL0[DP] is set to 1, AP_PMCCNTR_EL0.
20516                                                                  The other event counters and, if AP_PMCR_EL0[DP] is set to 0,
20517                                                                  AP_PMCCNTR_EL0 are unaffected.
20518 
20519                                                                  On Warm reset, the field resets to 0. */
20520         uint32_t reserved_15_16        : 2;
20521         uint32_t tpms                  : 1;  /**< [ 14: 14](R/W) Trap Performance Monitor Sampling. Controls access to Statistical Profiling control
20522                                                                  registers from Non-secure EL1 and EL0.
20523                                                                    0 = Do not trap statistical profiling controls to EL2.
20524                                                                    1 = Accesses to statistical profiling controls at nonsecure EL1 generate a Trap
20525                                                                  exception to EL2. */
20526         uint32_t e2pb                  : 2;  /**< [ 13: 12](R/W) EL2 Profiling Buffer. Controls the owning translation regime and access to Profiling
20527                                                                  Buffer control registers from nonsecure EL1.
20528                                                                    00 = Profiling Buffer uses the EL2 stage 1 translation regime. Accesses to Profiling
20529                                                                  Buffer controls at nonsecure EL1 generate a Trap exception to EL2.
20530                                                                    10 = Profiling Buffer uses the EL1&0 stage 1 translation regime. Accesses to Profiling
20531                                                                  Buffer controls at nonsecure EL1 generate a Trap exception to EL2.
20532                                                                    11 = Profiling Buffer uses the EL1&0 stage 1 translation regime. Accesses to Profiling
20533                                                                  Buffer controls at nonsecure EL1 are not trapped to EL2. */
20534         uint32_t tdra                  : 1;  /**< [ 11: 11](R/W) Trap debug ROM address register access.
20535 
20536                                                                  When this bit is set to 1, any access to the following
20537                                                                      registers from EL1 or EL0 is trapped to EL2:
20538 
20539                                                                  AArch32: DBGDRAR, DBGDSAR.
20540 
20541                                                                  AArch64: AP_MDRAR_EL1.
20542 
20543                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20544                                                                      ignored and treated as though it is 1 other than for the value
20545                                                                      read back from AP_MDCR_EL2.
20546 
20547                                                                  0 = Has no effect on accesses to debug ROM address registers from
20548                                                                      EL1 and EL0.
20549                                                                  1 = Trap valid EL1 and EL0 access to debug ROM address registers
20550                                                                      to EL2. */
20551         uint32_t tdosa                 : 1;  /**< [ 10: 10](R/W) Trap debug OS-related register access.
20552                                                                  When this bit is set to 1, any access to the following
20553                                                                      registers from EL1 or EL0 is trapped to EL2:
20554 
20555                                                                  AArch32: DBGOSLAR, DBGOSLSR, DBGOSDLR, DBGPRCR.
20556 
20557                                                                  AArch64: AP_OSLAR_EL1, AP_OSLSR_EL1, AP_OSDLR_EL1, AP_DBGPRCR_EL1.
20558 
20559                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20560                                                                      ignored and treated as though it is 1 other than for the value
20561                                                                      read back from AP_MDCR_EL2.
20562                                                                  0 = Has no effect on accesses to OS-related debug registers.
20563                                                                  1 = Trap valid accesses to OS-related debug registers to EL2. */
20564         uint32_t tda                   : 1;  /**< [  9:  9](R/W) Trap debug access.
20565 
20566                                                                  When this bit is set to 1, any valid nonsecure access to the
20567                                                                      debug registers from EL1 or EL0, other than the registers
20568                                                                      trapped by the TDRA and TDOSA bits, is trapped to EL2.
20569 
20570                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20571                                                                      ignored and treated as though it is 1 other than for the value
20572                                                                      read back from AP_MDCR_EL2.
20573                                                                  0 = Has no effect on accesses to debug registers.
20574                                                                  1 = Trap valid nonsecure accesses to debug registers to EL2. */
20575         uint32_t tde                   : 1;  /**< [  8:  8](R/W) Route Software debug exceptions from nonsecure EL1 and EL0 to
20576                                                                      EL2. Also enables traps on all debug register accesses to EL2.
20577                                                                  If AP_HCR_EL2[TGE] == 1, then this bit is ignored and treated as
20578                                                                      though it is 1 other than for the value read back from
20579                                                                      AP_MDCR_EL2. */
20580         uint32_t hpme                  : 1;  /**< [  7:  7](R/W) Hypervisor Performance Monitors Enable.
20581                                                                  When this bit is set to 1, the Performance Monitors counters
20582                                                                      that are reserved for use from EL2 or Secure state are
20583                                                                      enabled. For more information see the description of the HPMN
20584                                                                      field.
20585                                                                  If the Performance Monitors extension is not implemented, this
20586                                                                      field is RES0.
20587                                                                  0 = EL2 Performance Monitors disabled.
20588                                                                  1 = EL2 Performance Monitors enabled. */
20589         uint32_t tpm                   : 1;  /**< [  6:  6](R/W) Trap Performance Monitors accesses.
20590                                                                  If the Performance Monitors extension is not implemented, this
20591                                                                      field is RES0.
20592                                                                  0 = Has no effect on Performance Monitors accesses.
20593                                                                  1 = Trap nonsecure EL0 and EL1 accesses to Performance Monitors
20594                                                                      registers that are not unallocated to EL2. */
20595         uint32_t tpmcr                 : 1;  /**< [  5:  5](R/W) Trap AP_PMCR_EL0 accesses.
20596                                                                  If the Performance Monitors extension is not implemented, this
20597                                                                      field is RES0.
20598                                                                  0 = Has no effect on AP_PMCR_EL0 accesses.
20599                                                                  1 = Trap nonsecure EL0 and EL1 accesses to AP_PMCR_EL0 to EL2. */
20600         uint32_t hpmn                  : 5;  /**< [  4:  0](R/W) Defines the number of Performance Monitors counters that are
20601                                                                      accessible from nonsecure EL0 and EL1 modes.
20602 
20603                                                                  If the Performance Monitors extension is not implemented, this
20604                                                                      field is RES0.
20605 
20606                                                                  In nonsecure state, HPMN divides the Performance Monitors
20607                                                                      counters as follows. For counter n in nonsecure state:
20608 
20609                                                                   If n is in the range 0\<=n\<HPMN, the counter is accessible
20610                                                                      from EL1 and EL2, and from EL0 if permitted by AP_PMUSERENR_EL0.
20611                                                                      AP_PMCR_EL0[E] enables the operation of counters in this range.
20612 
20613                                                                   If n is in the range HPMN\<=n\< AP_PMCR_EL0[N], the counter is
20614                                                                      accessible only from EL2. AP_MDCR_EL2[HPME] enables the operation
20615                                                                      of counters in this range.
20616 
20617                                                                  If this field is set to 0, or to a value larger than
20618                                                                      AP_PMCR_EL0[N], then the behavior in nonsecure EL0 and EL1 is
20619                                                                      CONSTRAINED UNPREDICTABLE, and one of the following must
20620                                                                      happen:
20621 
20622                                                                   The number of counters accessible is an UNKNOWN nonzero
20623                                                                      value less than AP_PMCR_EL0[N].
20624 
20625                                                                   There is no access to any counters.
20626 
20627                                                                  For reads of AP_MDCR_EL2[HPMN] by EL2 or higher, if this field is
20628                                                                      set to 0 or to a value larger than AP_PMCR_EL0[N], the processor
20629                                                                      must return a CONSTRAINED UNPREDICTABLE value being one of:
20630                                                                    AP_PMCR_EL0[N].
20631 
20632                                                                   The value that was written to AP_MDCR_EL2[HPMN].
20633                                                                   (The value that was written to AP_MDCR_EL2[HPMN]) modulo
20634                                                                      22^(h), where h is the smallest number of bits required
20635                                                                      for a value in the range 0 to  AP_PMCR_EL0[N]. */
20636 #else /* Word 0 - Little Endian */
20637         uint32_t hpmn                  : 5;  /**< [  4:  0](R/W) Defines the number of Performance Monitors counters that are
20638                                                                      accessible from nonsecure EL0 and EL1 modes.
20639 
20640                                                                  If the Performance Monitors extension is not implemented, this
20641                                                                      field is RES0.
20642 
20643                                                                  In nonsecure state, HPMN divides the Performance Monitors
20644                                                                      counters as follows. For counter n in nonsecure state:
20645 
20646                                                                   If n is in the range 0\<=n\<HPMN, the counter is accessible
20647                                                                      from EL1 and EL2, and from EL0 if permitted by AP_PMUSERENR_EL0.
20648                                                                      AP_PMCR_EL0[E] enables the operation of counters in this range.
20649 
20650                                                                   If n is in the range HPMN\<=n\< AP_PMCR_EL0[N], the counter is
20651                                                                      accessible only from EL2. AP_MDCR_EL2[HPME] enables the operation
20652                                                                      of counters in this range.
20653 
20654                                                                  If this field is set to 0, or to a value larger than
20655                                                                      AP_PMCR_EL0[N], then the behavior in nonsecure EL0 and EL1 is
20656                                                                      CONSTRAINED UNPREDICTABLE, and one of the following must
20657                                                                      happen:
20658 
20659                                                                   The number of counters accessible is an UNKNOWN nonzero
20660                                                                      value less than AP_PMCR_EL0[N].
20661 
20662                                                                   There is no access to any counters.
20663 
20664                                                                  For reads of AP_MDCR_EL2[HPMN] by EL2 or higher, if this field is
20665                                                                      set to 0 or to a value larger than AP_PMCR_EL0[N], the processor
20666                                                                      must return a CONSTRAINED UNPREDICTABLE value being one of:
20667                                                                    AP_PMCR_EL0[N].
20668 
20669                                                                   The value that was written to AP_MDCR_EL2[HPMN].
20670                                                                   (The value that was written to AP_MDCR_EL2[HPMN]) modulo
20671                                                                      22^(h), where h is the smallest number of bits required
20672                                                                      for a value in the range 0 to  AP_PMCR_EL0[N]. */
20673         uint32_t tpmcr                 : 1;  /**< [  5:  5](R/W) Trap AP_PMCR_EL0 accesses.
20674                                                                  If the Performance Monitors extension is not implemented, this
20675                                                                      field is RES0.
20676                                                                  0 = Has no effect on AP_PMCR_EL0 accesses.
20677                                                                  1 = Trap nonsecure EL0 and EL1 accesses to AP_PMCR_EL0 to EL2. */
20678         uint32_t tpm                   : 1;  /**< [  6:  6](R/W) Trap Performance Monitors accesses.
20679                                                                  If the Performance Monitors extension is not implemented, this
20680                                                                      field is RES0.
20681                                                                  0 = Has no effect on Performance Monitors accesses.
20682                                                                  1 = Trap nonsecure EL0 and EL1 accesses to Performance Monitors
20683                                                                      registers that are not unallocated to EL2. */
20684         uint32_t hpme                  : 1;  /**< [  7:  7](R/W) Hypervisor Performance Monitors Enable.
20685                                                                  When this bit is set to 1, the Performance Monitors counters
20686                                                                      that are reserved for use from EL2 or Secure state are
20687                                                                      enabled. For more information see the description of the HPMN
20688                                                                      field.
20689                                                                  If the Performance Monitors extension is not implemented, this
20690                                                                      field is RES0.
20691                                                                  0 = EL2 Performance Monitors disabled.
20692                                                                  1 = EL2 Performance Monitors enabled. */
20693         uint32_t tde                   : 1;  /**< [  8:  8](R/W) Route Software debug exceptions from nonsecure EL1 and EL0 to
20694                                                                      EL2. Also enables traps on all debug register accesses to EL2.
20695                                                                  If AP_HCR_EL2[TGE] == 1, then this bit is ignored and treated as
20696                                                                      though it is 1 other than for the value read back from
20697                                                                      AP_MDCR_EL2. */
20698         uint32_t tda                   : 1;  /**< [  9:  9](R/W) Trap debug access.
20699 
20700                                                                  When this bit is set to 1, any valid nonsecure access to the
20701                                                                      debug registers from EL1 or EL0, other than the registers
20702                                                                      trapped by the TDRA and TDOSA bits, is trapped to EL2.
20703 
20704                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20705                                                                      ignored and treated as though it is 1 other than for the value
20706                                                                      read back from AP_MDCR_EL2.
20707                                                                  0 = Has no effect on accesses to debug registers.
20708                                                                  1 = Trap valid nonsecure accesses to debug registers to EL2. */
20709         uint32_t tdosa                 : 1;  /**< [ 10: 10](R/W) Trap debug OS-related register access.
20710                                                                  When this bit is set to 1, any access to the following
20711                                                                      registers from EL1 or EL0 is trapped to EL2:
20712 
20713                                                                  AArch32: DBGOSLAR, DBGOSLSR, DBGOSDLR, DBGPRCR.
20714 
20715                                                                  AArch64: AP_OSLAR_EL1, AP_OSLSR_EL1, AP_OSDLR_EL1, AP_DBGPRCR_EL1.
20716 
20717                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20718                                                                      ignored and treated as though it is 1 other than for the value
20719                                                                      read back from AP_MDCR_EL2.
20720                                                                  0 = Has no effect on accesses to OS-related debug registers.
20721                                                                  1 = Trap valid accesses to OS-related debug registers to EL2. */
20722         uint32_t tdra                  : 1;  /**< [ 11: 11](R/W) Trap debug ROM address register access.
20723 
20724                                                                  When this bit is set to 1, any access to the following
20725                                                                      registers from EL1 or EL0 is trapped to EL2:
20726 
20727                                                                  AArch32: DBGDRAR, DBGDSAR.
20728 
20729                                                                  AArch64: AP_MDRAR_EL1.
20730 
20731                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20732                                                                      ignored and treated as though it is 1 other than for the value
20733                                                                      read back from AP_MDCR_EL2.
20734 
20735                                                                  0 = Has no effect on accesses to debug ROM address registers from
20736                                                                      EL1 and EL0.
20737                                                                  1 = Trap valid EL1 and EL0 access to debug ROM address registers
20738                                                                      to EL2. */
20739         uint32_t e2pb                  : 2;  /**< [ 13: 12](R/W) EL2 Profiling Buffer. Controls the owning translation regime and access to Profiling
20740                                                                  Buffer control registers from nonsecure EL1.
20741                                                                    00 = Profiling Buffer uses the EL2 stage 1 translation regime. Accesses to Profiling
20742                                                                  Buffer controls at nonsecure EL1 generate a Trap exception to EL2.
20743                                                                    10 = Profiling Buffer uses the EL1&0 stage 1 translation regime. Accesses to Profiling
20744                                                                  Buffer controls at nonsecure EL1 generate a Trap exception to EL2.
20745                                                                    11 = Profiling Buffer uses the EL1&0 stage 1 translation regime. Accesses to Profiling
20746                                                                  Buffer controls at nonsecure EL1 are not trapped to EL2. */
20747         uint32_t tpms                  : 1;  /**< [ 14: 14](R/W) Trap Performance Monitor Sampling. Controls access to Statistical Profiling control
20748                                                                  registers from Non-secure EL1 and EL0.
20749                                                                    0 = Do not trap statistical profiling controls to EL2.
20750                                                                    1 = Accesses to statistical profiling controls at nonsecure EL1 generate a Trap
20751                                                                  exception to EL2. */
20752         uint32_t reserved_15_16        : 2;
20753         uint32_t hpmd                  : 1;  /**< [ 17: 17](R/W) v8.1: Hyp performance monitors disable. This prohibits event counting
20754                                                                  at EL2.
20755                                                                  0 = Event counting allowed at EL2.
20756                                                                  1 = Event counting prohibited at EL2, unless overridden by
20757                                                                          the authentication interface.
20758 
20759                                                                  Note: This behavior is independent of the value of the AP_HCR_EL2[E2H]
20760                                                                  bit.
20761                                                                  This control applies only to:
20762                                                                  The counters in the range [0.[HPMN]).
20763                                                                  If AP_PMCR_EL0[DP] is set to 1, AP_PMCCNTR_EL0.
20764                                                                  The other event counters and, if AP_PMCR_EL0[DP] is set to 0,
20765                                                                  AP_PMCCNTR_EL0 are unaffected.
20766 
20767                                                                  On Warm reset, the field resets to 0. */
20768         uint32_t reserved_18_31        : 14;
20769 #endif /* Word 0 - End */
20770     } s;
20771     struct bdk_ap_mdcr_el2_cn8
20772     {
20773 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
20774         uint32_t reserved_18_31        : 14;
20775         uint32_t hpmd                  : 1;  /**< [ 17: 17](R/W) v8.1: Hyp performance monitors disable. This prohibits event counting
20776                                                                  at EL2.
20777                                                                  0 = Event counting allowed at EL2.
20778                                                                  1 = Event counting prohibited at EL2, unless overridden by
20779                                                                          the authentication interface.
20780 
20781                                                                  Note: This behavior is independent of the value of the AP_HCR_EL2[E2H]
20782                                                                  bit.
20783                                                                  This control applies only to:
20784                                                                  The counters in the range [0.[HPMN]).
20785                                                                  If AP_PMCR_EL0[DP] is set to 1, AP_PMCCNTR_EL0.
20786                                                                  The other event counters and, if AP_PMCR_EL0[DP] is set to 0,
20787                                                                  AP_PMCCNTR_EL0 are unaffected.
20788 
20789                                                                  On Warm reset, the field resets to 0. */
20790         uint32_t reserved_12_16        : 5;
20791         uint32_t tdra                  : 1;  /**< [ 11: 11](R/W) Trap debug ROM address register access.
20792 
20793                                                                  When this bit is set to 1, any access to the following
20794                                                                      registers from EL1 or EL0 is trapped to EL2:
20795 
20796                                                                  AArch32: DBGDRAR, DBGDSAR.
20797 
20798                                                                  AArch64: AP_MDRAR_EL1.
20799 
20800                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20801                                                                      ignored and treated as though it is 1 other than for the value
20802                                                                      read back from AP_MDCR_EL2.
20803 
20804                                                                  0 = Has no effect on accesses to debug ROM address registers from
20805                                                                      EL1 and EL0.
20806                                                                  1 = Trap valid EL1 and EL0 access to debug ROM address registers
20807                                                                      to EL2. */
20808         uint32_t tdosa                 : 1;  /**< [ 10: 10](R/W) Trap debug OS-related register access.
20809                                                                  When this bit is set to 1, any access to the following
20810                                                                      registers from EL1 or EL0 is trapped to EL2:
20811 
20812                                                                  AArch32: DBGOSLAR, DBGOSLSR, DBGOSDLR, DBGPRCR.
20813 
20814                                                                  AArch64: AP_OSLAR_EL1, AP_OSLSR_EL1, AP_OSDLR_EL1, AP_DBGPRCR_EL1.
20815 
20816                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20817                                                                      ignored and treated as though it is 1 other than for the value
20818                                                                      read back from AP_MDCR_EL2.
20819                                                                  0 = Has no effect on accesses to OS-related debug registers.
20820                                                                  1 = Trap valid accesses to OS-related debug registers to EL2. */
20821         uint32_t tda                   : 1;  /**< [  9:  9](R/W) Trap debug access.
20822 
20823                                                                  When this bit is set to 1, any valid nonsecure access to the
20824                                                                      debug registers from EL1 or EL0, other than the registers
20825                                                                      trapped by the TDRA and TDOSA bits, is trapped to EL2.
20826 
20827                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20828                                                                      ignored and treated as though it is 1 other than for the value
20829                                                                      read back from AP_MDCR_EL2.
20830                                                                  0 = Has no effect on accesses to debug registers.
20831                                                                  1 = Trap valid nonsecure accesses to debug registers to EL2. */
20832         uint32_t tde                   : 1;  /**< [  8:  8](R/W) Route Software debug exceptions from nonsecure EL1 and EL0 to
20833                                                                      EL2. Also enables traps on all debug register accesses to EL2.
20834                                                                  If AP_HCR_EL2[TGE] == 1, then this bit is ignored and treated as
20835                                                                      though it is 1 other than for the value read back from
20836                                                                      AP_MDCR_EL2. */
20837         uint32_t hpme                  : 1;  /**< [  7:  7](R/W) Hypervisor Performance Monitors Enable.
20838                                                                  When this bit is set to 1, the Performance Monitors counters
20839                                                                      that are reserved for use from EL2 or Secure state are
20840                                                                      enabled. For more information see the description of the HPMN
20841                                                                      field.
20842                                                                  If the Performance Monitors extension is not implemented, this
20843                                                                      field is RES0.
20844                                                                  0 = EL2 Performance Monitors disabled.
20845                                                                  1 = EL2 Performance Monitors enabled. */
20846         uint32_t tpm                   : 1;  /**< [  6:  6](R/W) Trap Performance Monitors accesses.
20847                                                                  If the Performance Monitors extension is not implemented, this
20848                                                                      field is RES0.
20849                                                                  0 = Has no effect on Performance Monitors accesses.
20850                                                                  1 = Trap nonsecure EL0 and EL1 accesses to Performance Monitors
20851                                                                      registers that are not unallocated to EL2. */
20852         uint32_t tpmcr                 : 1;  /**< [  5:  5](R/W) Trap AP_PMCR_EL0 accesses.
20853                                                                  If the Performance Monitors extension is not implemented, this
20854                                                                      field is RES0.
20855                                                                  0 = Has no effect on AP_PMCR_EL0 accesses.
20856                                                                  1 = Trap nonsecure EL0 and EL1 accesses to AP_PMCR_EL0 to EL2. */
20857         uint32_t hpmn                  : 5;  /**< [  4:  0](R/W) Defines the number of Performance Monitors counters that are
20858                                                                      accessible from nonsecure EL0 and EL1 modes.
20859 
20860                                                                  If the Performance Monitors extension is not implemented, this
20861                                                                      field is RES0.
20862 
20863                                                                  In nonsecure state, HPMN divides the Performance Monitors
20864                                                                      counters as follows. For counter n in nonsecure state:
20865 
20866                                                                   If n is in the range 0\<=n\<HPMN, the counter is accessible
20867                                                                      from EL1 and EL2, and from EL0 if permitted by AP_PMUSERENR_EL0.
20868                                                                      AP_PMCR_EL0[E] enables the operation of counters in this range.
20869 
20870                                                                   If n is in the range HPMN\<=n\< AP_PMCR_EL0[N], the counter is
20871                                                                      accessible only from EL2. AP_MDCR_EL2[HPME] enables the operation
20872                                                                      of counters in this range.
20873 
20874                                                                  If this field is set to 0, or to a value larger than
20875                                                                      AP_PMCR_EL0[N], then the behavior in nonsecure EL0 and EL1 is
20876                                                                      CONSTRAINED UNPREDICTABLE, and one of the following must
20877                                                                      happen:
20878 
20879                                                                   The number of counters accessible is an UNKNOWN nonzero
20880                                                                      value less than AP_PMCR_EL0[N].
20881 
20882                                                                   There is no access to any counters.
20883 
20884                                                                  For reads of AP_MDCR_EL2[HPMN] by EL2 or higher, if this field is
20885                                                                      set to 0 or to a value larger than AP_PMCR_EL0[N], the processor
20886                                                                      must return a CONSTRAINED UNPREDICTABLE value being one of:
20887                                                                    AP_PMCR_EL0[N].
20888 
20889                                                                   The value that was written to AP_MDCR_EL2[HPMN].
20890                                                                   (The value that was written to AP_MDCR_EL2[HPMN]) modulo
20891                                                                      22^(h), where h is the smallest number of bits required
20892                                                                      for a value in the range 0 to  AP_PMCR_EL0[N]. */
20893 #else /* Word 0 - Little Endian */
20894         uint32_t hpmn                  : 5;  /**< [  4:  0](R/W) Defines the number of Performance Monitors counters that are
20895                                                                      accessible from nonsecure EL0 and EL1 modes.
20896 
20897                                                                  If the Performance Monitors extension is not implemented, this
20898                                                                      field is RES0.
20899 
20900                                                                  In nonsecure state, HPMN divides the Performance Monitors
20901                                                                      counters as follows. For counter n in nonsecure state:
20902 
20903                                                                   If n is in the range 0\<=n\<HPMN, the counter is accessible
20904                                                                      from EL1 and EL2, and from EL0 if permitted by AP_PMUSERENR_EL0.
20905                                                                      AP_PMCR_EL0[E] enables the operation of counters in this range.
20906 
20907                                                                   If n is in the range HPMN\<=n\< AP_PMCR_EL0[N], the counter is
20908                                                                      accessible only from EL2. AP_MDCR_EL2[HPME] enables the operation
20909                                                                      of counters in this range.
20910 
20911                                                                  If this field is set to 0, or to a value larger than
20912                                                                      AP_PMCR_EL0[N], then the behavior in nonsecure EL0 and EL1 is
20913                                                                      CONSTRAINED UNPREDICTABLE, and one of the following must
20914                                                                      happen:
20915 
20916                                                                   The number of counters accessible is an UNKNOWN nonzero
20917                                                                      value less than AP_PMCR_EL0[N].
20918 
20919                                                                   There is no access to any counters.
20920 
20921                                                                  For reads of AP_MDCR_EL2[HPMN] by EL2 or higher, if this field is
20922                                                                      set to 0 or to a value larger than AP_PMCR_EL0[N], the processor
20923                                                                      must return a CONSTRAINED UNPREDICTABLE value being one of:
20924                                                                    AP_PMCR_EL0[N].
20925 
20926                                                                   The value that was written to AP_MDCR_EL2[HPMN].
20927                                                                   (The value that was written to AP_MDCR_EL2[HPMN]) modulo
20928                                                                      22^(h), where h is the smallest number of bits required
20929                                                                      for a value in the range 0 to  AP_PMCR_EL0[N]. */
20930         uint32_t tpmcr                 : 1;  /**< [  5:  5](R/W) Trap AP_PMCR_EL0 accesses.
20931                                                                  If the Performance Monitors extension is not implemented, this
20932                                                                      field is RES0.
20933                                                                  0 = Has no effect on AP_PMCR_EL0 accesses.
20934                                                                  1 = Trap nonsecure EL0 and EL1 accesses to AP_PMCR_EL0 to EL2. */
20935         uint32_t tpm                   : 1;  /**< [  6:  6](R/W) Trap Performance Monitors accesses.
20936                                                                  If the Performance Monitors extension is not implemented, this
20937                                                                      field is RES0.
20938                                                                  0 = Has no effect on Performance Monitors accesses.
20939                                                                  1 = Trap nonsecure EL0 and EL1 accesses to Performance Monitors
20940                                                                      registers that are not unallocated to EL2. */
20941         uint32_t hpme                  : 1;  /**< [  7:  7](R/W) Hypervisor Performance Monitors Enable.
20942                                                                  When this bit is set to 1, the Performance Monitors counters
20943                                                                      that are reserved for use from EL2 or Secure state are
20944                                                                      enabled. For more information see the description of the HPMN
20945                                                                      field.
20946                                                                  If the Performance Monitors extension is not implemented, this
20947                                                                      field is RES0.
20948                                                                  0 = EL2 Performance Monitors disabled.
20949                                                                  1 = EL2 Performance Monitors enabled. */
20950         uint32_t tde                   : 1;  /**< [  8:  8](R/W) Route Software debug exceptions from nonsecure EL1 and EL0 to
20951                                                                      EL2. Also enables traps on all debug register accesses to EL2.
20952                                                                  If AP_HCR_EL2[TGE] == 1, then this bit is ignored and treated as
20953                                                                      though it is 1 other than for the value read back from
20954                                                                      AP_MDCR_EL2. */
20955         uint32_t tda                   : 1;  /**< [  9:  9](R/W) Trap debug access.
20956 
20957                                                                  When this bit is set to 1, any valid nonsecure access to the
20958                                                                      debug registers from EL1 or EL0, other than the registers
20959                                                                      trapped by the TDRA and TDOSA bits, is trapped to EL2.
20960 
20961                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20962                                                                      ignored and treated as though it is 1 other than for the value
20963                                                                      read back from AP_MDCR_EL2.
20964                                                                  0 = Has no effect on accesses to debug registers.
20965                                                                  1 = Trap valid nonsecure accesses to debug registers to EL2. */
20966         uint32_t tdosa                 : 1;  /**< [ 10: 10](R/W) Trap debug OS-related register access.
20967                                                                  When this bit is set to 1, any access to the following
20968                                                                      registers from EL1 or EL0 is trapped to EL2:
20969 
20970                                                                  AArch32: DBGOSLAR, DBGOSLSR, DBGOSDLR, DBGPRCR.
20971 
20972                                                                  AArch64: AP_OSLAR_EL1, AP_OSLSR_EL1, AP_OSDLR_EL1, AP_DBGPRCR_EL1.
20973 
20974                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20975                                                                      ignored and treated as though it is 1 other than for the value
20976                                                                      read back from AP_MDCR_EL2.
20977                                                                  0 = Has no effect on accesses to OS-related debug registers.
20978                                                                  1 = Trap valid accesses to OS-related debug registers to EL2. */
20979         uint32_t tdra                  : 1;  /**< [ 11: 11](R/W) Trap debug ROM address register access.
20980 
20981                                                                  When this bit is set to 1, any access to the following
20982                                                                      registers from EL1 or EL0 is trapped to EL2:
20983 
20984                                                                  AArch32: DBGDRAR, DBGDSAR.
20985 
20986                                                                  AArch64: AP_MDRAR_EL1.
20987 
20988                                                                  If AP_HCR_EL2[TGE] == 1 or AP_MDCR_EL2[TDE] == 1, then this bit is
20989                                                                      ignored and treated as though it is 1 other than for the value
20990                                                                      read back from AP_MDCR_EL2.
20991 
20992                                                                  0 = Has no effect on accesses to debug ROM address registers from
20993                                                                      EL1 and EL0.
20994                                                                  1 = Trap valid EL1 and EL0 access to debug ROM address registers
20995                                                                      to EL2. */
20996         uint32_t reserved_12_16        : 5;
20997         uint32_t hpmd                  : 1;  /**< [ 17: 17](R/W) v8.1: Hyp performance monitors disable. This prohibits event counting
20998                                                                  at EL2.
20999                                                                  0 = Event counting allowed at EL2.
21000                                                                  1 = Event counting prohibited at EL2, unless overridden by
21001                                                                          the authentication interface.
21002 
21003                                                                  Note: This behavior is independent of the value of the AP_HCR_EL2[E2H]
21004                                                                  bit.
21005                                                                  This control applies only to:
21006                                                                  The counters in the range [0.[HPMN]).
21007                                                                  If AP_PMCR_EL0[DP] is set to 1, AP_PMCCNTR_EL0.
21008                                                                  The other event counters and, if AP_PMCR_EL0[DP] is set to 0,
21009                                                                  AP_PMCCNTR_EL0 are unaffected.
21010 
21011                                                                  On Warm reset, the field resets to 0. */
21012         uint32_t reserved_18_31        : 14;
21013 #endif /* Word 0 - End */
21014     } cn8;
21015     /* struct bdk_ap_mdcr_el2_s cn9; */
21016 };
21017 typedef union bdk_ap_mdcr_el2 bdk_ap_mdcr_el2_t;
21018 
21019 #define BDK_AP_MDCR_EL2 BDK_AP_MDCR_EL2_FUNC()
21020 static inline uint64_t BDK_AP_MDCR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_MDCR_EL2_FUNC(void)21021 static inline uint64_t BDK_AP_MDCR_EL2_FUNC(void)
21022 {
21023     return 0x30401010100ll;
21024 }
21025 
21026 #define typedef_BDK_AP_MDCR_EL2 bdk_ap_mdcr_el2_t
21027 #define bustype_BDK_AP_MDCR_EL2 BDK_CSR_TYPE_SYSREG
21028 #define basename_BDK_AP_MDCR_EL2 "AP_MDCR_EL2"
21029 #define busnum_BDK_AP_MDCR_EL2 0
21030 #define arguments_BDK_AP_MDCR_EL2 -1,-1,-1,-1
21031 
21032 /**
21033  * Register (SYSREG) ap_mdcr_el3
21034  *
21035  * AP Monitor Debug Configuration EL3 Register
21036  * Provides configuration options for the Security extensions to
21037  *     self-hosted debug.
21038  */
21039 union bdk_ap_mdcr_el3
21040 {
21041     uint32_t u;
21042     struct bdk_ap_mdcr_el3_s
21043     {
21044 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
21045         uint32_t reserved_22_31        : 10;
21046         uint32_t epmad                 : 1;  /**< [ 21: 21](R/W) External debugger access to Performance Monitors registers
21047                                                                      disabled. This disables access to these registers by an
21048                                                                      external debugger:
21049                                                                  0 = Access to Performance Monitors registers from external
21050                                                                      debugger is permitted.
21051                                                                  1 = Access to Performance Monitors registers from external
21052                                                                      debugger is disabled, unless overridden by authentication
21053                                                                      interface. */
21054         uint32_t edad                  : 1;  /**< [ 20: 20](R/W) External debugger access to breakpoint and watchpoint
21055                                                                      registers disabled. This disables access to these registers by
21056                                                                      an external debugger:
21057                                                                  0 = Access to breakpoint and watchpoint registers from external
21058                                                                      debugger is permitted.
21059                                                                  1 = Access to breakpoint and watchpoint registers from external
21060                                                                      debugger is disabled, unless overridden by authentication
21061                                                                      interface. */
21062         uint32_t reserved_18_19        : 2;
21063         uint32_t spme                  : 1;  /**< [ 17: 17](R/W) Secure performance monitors enable. This allows event counting
21064                                                                      in Secure state:
21065                                                                  0 = Event counting prohibited in Secure state, unless overridden
21066                                                                      by the authentication interface.
21067                                                                  1 = Event counting allowed in Secure state. */
21068         uint32_t sdd                   : 1;  /**< [ 16: 16](R/W) AArch64 secure self-hosted invasive debug disable. Disables
21069                                                                      Software debug exceptions in Secure state, other than Software
21070                                                                      breakpoint instruction.
21071                                                                  SDD only applies when both of the following are true:
21072                                                                   The processor is executing in Secure state.
21073                                                                   Secure EL1 is using AArch64.
21074                                                                  0 = Taking Software debug events as debug exceptions is permitted
21075                                                                      from Secure EL0 and EL1, if enabled by the relevant AP_MDSCR_EL1
21076                                                                      and PSTATE[D] flags.
21077                                                                  1 = Software debug events, other than software breakpoint
21078                                                                      instruction debug events, are disabled from all Exception
21079                                                                      levels in Secure state. */
21080         uint32_t reserved_14_15        : 2;
21081         uint32_t nspb                  : 2;  /**< [ 13: 12](R/W) Non-secure profiling buffer. Controls the owning translation regime and accesses to
21082                                                                  Statistical
21083                                                                  Profiling and profiling buffer control registers.
21084                                                                    0x0 = Profiling buffer uses secure virtual addresses. Statistical profiling enabled in
21085                                                                  Secure state and disabled in Non-secure state. Accesses to Statistical profiling and
21086                                                                  Profiling Buffer controls at EL2 and EL1 in both security states generate Trap exceptions
21087                                                                  to EL3.
21088                                                                    0x1 = Profiling buffer uses secure virtual addresses. Statistical profiling enabled in
21089                                                                  Secure state and disabled in Non-secure state. Accesses to Statistical profiling and
21090                                                                  Profiling Buffer controls in Nonsecure state generate Trap exceptions to EL3.
21091                                                                    0x2 = Profiling buffer uses nonsecure virtual addresses. Statistical profiling enabled
21092                                                                  in Non-secure state and disabled in Secure state. Accesses to Statistical Profiling and
21093                                                                  Profiling Buffer controls at EL2 and EL1 in both security states generate Trap exceptions
21094                                                                  to EL3.
21095                                                                    0x3 = Profiling buffer uses nonsecure virtual addresses. Statistical profiling enabled
21096                                                                  in Non-secure state and disabled in secure state. Accesses to Statistical Profiling and
21097                                                                  Profiling Buffer controls at Secure EL1 generate Trap exceptions to EL3.
21098 
21099                                                                  If EL3 is not implemented and the PE executes in Non-secure state, the PE behaves as if
21100                                                                  NSPB = 0x3.
21101                                                                  If EL3 is not implemented and the PE executes in Secure state, the PE behaves as if NSPB
21102                                                                  = 0x1. */
21103         uint32_t reserved_11           : 1;
21104         uint32_t tdosa                 : 1;  /**< [ 10: 10](R/W) Trap debug OS-related register access.
21105                                                                  When this bit is set to 1, any access to the following
21106                                                                      registers from EL2 or below is trapped to EL3:
21107 
21108                                                                  AArch32: DBGOSLAR, DBGOSLSR, DBGOSDLR, DBGPRCR.
21109 
21110                                                                  AArch64: AP_OSLAR_EL1, AP_OSLSR_EL1, AP_OSDLR_EL1, AP_DBGPRCR_EL1.
21111 
21112                                                                  0 = Has no effect on accesses to OS-related debug registers.
21113                                                                  1 = Trap valid accesses to OS-related debug registers to EL3. */
21114         uint32_t tda                   : 1;  /**< [  9:  9](R/W) Trap debug access.
21115                                                                  When this bit is set to 1, any valid nonsecure access to the
21116                                                                      debug registers from EL2 or below, other than the registers
21117                                                                      trapped by the TDRA and TDOSA bits, is trapped to EL3.
21118                                                                  0 = Has no effect on accesses to debug registers.
21119                                                                  1 = Trap valid nonsecure accesses to debug registers to EL3. */
21120         uint32_t reserved_7_8          : 2;
21121         uint32_t tpm                   : 1;  /**< [  6:  6](R/W) Trap Performance Monitors accesses.
21122                                                                  If the Performance Monitors extension is not implemented, this
21123                                                                      field is RES0.
21124                                                                  0 = Has no effect on Performance Monitors accesses.
21125                                                                  1 = Trap nonsecure EL0, EL1 and EL2 accesses to Performance
21126                                                                      Monitors registers that are not unallocated, or trapped to a
21127                                                                      lower Exception level, to EL3. */
21128         uint32_t reserved_0_5          : 6;
21129 #else /* Word 0 - Little Endian */
21130         uint32_t reserved_0_5          : 6;
21131         uint32_t tpm                   : 1;  /**< [  6:  6](R/W) Trap Performance Monitors accesses.
21132                                                                  If the Performance Monitors extension is not implemented, this
21133                                                                      field is RES0.
21134                                                                  0 = Has no effect on Performance Monitors accesses.
21135                                                                  1 = Trap nonsecure EL0, EL1 and EL2 accesses to Performance
21136                                                                      Monitors registers that are not unallocated, or trapped to a
21137                                                                      lower Exception level, to EL3. */
21138         uint32_t reserved_7_8          : 2;
21139         uint32_t tda                   : 1;  /**< [  9:  9](R/W) Trap debug access.
21140                                                                  When this bit is set to 1, any valid nonsecure access to the
21141                                                                      debug registers from EL2 or below, other than the registers
21142                                                                      trapped by the TDRA and TDOSA bits, is trapped to EL3.
21143                                                                  0 = Has no effect on accesses to debug registers.
21144                                                                  1 = Trap valid nonsecure accesses to debug registers to EL3. */
21145         uint32_t tdosa                 : 1;  /**< [ 10: 10](R/W) Trap debug OS-related register access.
21146                                                                  When this bit is set to 1, any access to the following
21147                                                                      registers from EL2 or below is trapped to EL3:
21148 
21149                                                                  AArch32: DBGOSLAR, DBGOSLSR, DBGOSDLR, DBGPRCR.
21150 
21151                                                                  AArch64: AP_OSLAR_EL1, AP_OSLSR_EL1, AP_OSDLR_EL1, AP_DBGPRCR_EL1.
21152 
21153                                                                  0 = Has no effect on accesses to OS-related debug registers.
21154                                                                  1 = Trap valid accesses to OS-related debug registers to EL3. */
21155         uint32_t reserved_11           : 1;
21156         uint32_t nspb                  : 2;  /**< [ 13: 12](R/W) Non-secure profiling buffer. Controls the owning translation regime and accesses to
21157                                                                  Statistical
21158                                                                  Profiling and profiling buffer control registers.
21159                                                                    0x0 = Profiling buffer uses secure virtual addresses. Statistical profiling enabled in
21160                                                                  Secure state and disabled in Non-secure state. Accesses to Statistical profiling and
21161                                                                  Profiling Buffer controls at EL2 and EL1 in both security states generate Trap exceptions
21162                                                                  to EL3.
21163                                                                    0x1 = Profiling buffer uses secure virtual addresses. Statistical profiling enabled in
21164                                                                  Secure state and disabled in Non-secure state. Accesses to Statistical profiling and
21165                                                                  Profiling Buffer controls in Nonsecure state generate Trap exceptions to EL3.
21166                                                                    0x2 = Profiling buffer uses nonsecure virtual addresses. Statistical profiling enabled
21167                                                                  in Non-secure state and disabled in Secure state. Accesses to Statistical Profiling and
21168                                                                  Profiling Buffer controls at EL2 and EL1 in both security states generate Trap exceptions
21169                                                                  to EL3.
21170                                                                    0x3 = Profiling buffer uses nonsecure virtual addresses. Statistical profiling enabled
21171                                                                  in Non-secure state and disabled in secure state. Accesses to Statistical Profiling and
21172                                                                  Profiling Buffer controls at Secure EL1 generate Trap exceptions to EL3.
21173 
21174                                                                  If EL3 is not implemented and the PE executes in Non-secure state, the PE behaves as if
21175                                                                  NSPB = 0x3.
21176                                                                  If EL3 is not implemented and the PE executes in Secure state, the PE behaves as if NSPB
21177                                                                  = 0x1. */
21178         uint32_t reserved_14_15        : 2;
21179         uint32_t sdd                   : 1;  /**< [ 16: 16](R/W) AArch64 secure self-hosted invasive debug disable. Disables
21180                                                                      Software debug exceptions in Secure state, other than Software
21181                                                                      breakpoint instruction.
21182                                                                  SDD only applies when both of the following are true:
21183                                                                   The processor is executing in Secure state.
21184                                                                   Secure EL1 is using AArch64.
21185                                                                  0 = Taking Software debug events as debug exceptions is permitted
21186                                                                      from Secure EL0 and EL1, if enabled by the relevant AP_MDSCR_EL1
21187                                                                      and PSTATE[D] flags.
21188                                                                  1 = Software debug events, other than software breakpoint
21189                                                                      instruction debug events, are disabled from all Exception
21190                                                                      levels in Secure state. */
21191         uint32_t spme                  : 1;  /**< [ 17: 17](R/W) Secure performance monitors enable. This allows event counting
21192                                                                      in Secure state:
21193                                                                  0 = Event counting prohibited in Secure state, unless overridden
21194                                                                      by the authentication interface.
21195                                                                  1 = Event counting allowed in Secure state. */
21196         uint32_t reserved_18_19        : 2;
21197         uint32_t edad                  : 1;  /**< [ 20: 20](R/W) External debugger access to breakpoint and watchpoint
21198                                                                      registers disabled. This disables access to these registers by
21199                                                                      an external debugger:
21200                                                                  0 = Access to breakpoint and watchpoint registers from external
21201                                                                      debugger is permitted.
21202                                                                  1 = Access to breakpoint and watchpoint registers from external
21203                                                                      debugger is disabled, unless overridden by authentication
21204                                                                      interface. */
21205         uint32_t epmad                 : 1;  /**< [ 21: 21](R/W) External debugger access to Performance Monitors registers
21206                                                                      disabled. This disables access to these registers by an
21207                                                                      external debugger:
21208                                                                  0 = Access to Performance Monitors registers from external
21209                                                                      debugger is permitted.
21210                                                                  1 = Access to Performance Monitors registers from external
21211                                                                      debugger is disabled, unless overridden by authentication
21212                                                                      interface. */
21213         uint32_t reserved_22_31        : 10;
21214 #endif /* Word 0 - End */
21215     } s;
21216     struct bdk_ap_mdcr_el3_cn8
21217     {
21218 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
21219         uint32_t reserved_22_31        : 10;
21220         uint32_t epmad                 : 1;  /**< [ 21: 21](R/W) External debugger access to Performance Monitors registers
21221                                                                      disabled. This disables access to these registers by an
21222                                                                      external debugger:
21223                                                                  0 = Access to Performance Monitors registers from external
21224                                                                      debugger is permitted.
21225                                                                  1 = Access to Performance Monitors registers from external
21226                                                                      debugger is disabled, unless overridden by authentication
21227                                                                      interface. */
21228         uint32_t edad                  : 1;  /**< [ 20: 20](R/W) External debugger access to breakpoint and watchpoint
21229                                                                      registers disabled. This disables access to these registers by
21230                                                                      an external debugger:
21231                                                                  0 = Access to breakpoint and watchpoint registers from external
21232                                                                      debugger is permitted.
21233                                                                  1 = Access to breakpoint and watchpoint registers from external
21234                                                                      debugger is disabled, unless overridden by authentication
21235                                                                      interface. */
21236         uint32_t reserved_18_19        : 2;
21237         uint32_t spme                  : 1;  /**< [ 17: 17](R/W) Secure performance monitors enable. This allows event counting
21238                                                                      in Secure state:
21239                                                                  0 = Event counting prohibited in Secure state, unless overridden
21240                                                                      by the authentication interface.
21241                                                                  1 = Event counting allowed in Secure state. */
21242         uint32_t sdd                   : 1;  /**< [ 16: 16](R/W) AArch64 secure self-hosted invasive debug disable. Disables
21243                                                                      Software debug exceptions in Secure state, other than Software
21244                                                                      breakpoint instruction.
21245                                                                  SDD only applies when both of the following are true:
21246                                                                   The processor is executing in Secure state.
21247                                                                   Secure EL1 is using AArch64.
21248                                                                  0 = Taking Software debug events as debug exceptions is permitted
21249                                                                      from Secure EL0 and EL1, if enabled by the relevant AP_MDSCR_EL1
21250                                                                      and PSTATE[D] flags.
21251                                                                  1 = Software debug events, other than software breakpoint
21252                                                                      instruction debug events, are disabled from all Exception
21253                                                                      levels in Secure state. */
21254         uint32_t reserved_14_15        : 2;
21255         uint32_t reserved_11_13        : 3;
21256         uint32_t tdosa                 : 1;  /**< [ 10: 10](R/W) Trap debug OS-related register access.
21257                                                                  When this bit is set to 1, any access to the following
21258                                                                      registers from EL2 or below is trapped to EL3:
21259 
21260                                                                  AArch32: DBGOSLAR, DBGOSLSR, DBGOSDLR, DBGPRCR.
21261 
21262                                                                  AArch64: AP_OSLAR_EL1, AP_OSLSR_EL1, AP_OSDLR_EL1, AP_DBGPRCR_EL1.
21263 
21264                                                                  0 = Has no effect on accesses to OS-related debug registers.
21265                                                                  1 = Trap valid accesses to OS-related debug registers to EL3. */
21266         uint32_t tda                   : 1;  /**< [  9:  9](R/W) Trap debug access.
21267                                                                  When this bit is set to 1, any valid nonsecure access to the
21268                                                                      debug registers from EL2 or below, other than the registers
21269                                                                      trapped by the TDRA and TDOSA bits, is trapped to EL3.
21270                                                                  0 = Has no effect on accesses to debug registers.
21271                                                                  1 = Trap valid nonsecure accesses to debug registers to EL3. */
21272         uint32_t reserved_7_8          : 2;
21273         uint32_t tpm                   : 1;  /**< [  6:  6](R/W) Trap Performance Monitors accesses.
21274                                                                  If the Performance Monitors extension is not implemented, this
21275                                                                      field is RES0.
21276                                                                  0 = Has no effect on Performance Monitors accesses.
21277                                                                  1 = Trap nonsecure EL0, EL1 and EL2 accesses to Performance
21278                                                                      Monitors registers that are not unallocated, or trapped to a
21279                                                                      lower Exception level, to EL3. */
21280         uint32_t reserved_0_5          : 6;
21281 #else /* Word 0 - Little Endian */
21282         uint32_t reserved_0_5          : 6;
21283         uint32_t tpm                   : 1;  /**< [  6:  6](R/W) Trap Performance Monitors accesses.
21284                                                                  If the Performance Monitors extension is not implemented, this
21285                                                                      field is RES0.
21286                                                                  0 = Has no effect on Performance Monitors accesses.
21287                                                                  1 = Trap nonsecure EL0, EL1 and EL2 accesses to Performance
21288                                                                      Monitors registers that are not unallocated, or trapped to a
21289                                                                      lower Exception level, to EL3. */
21290         uint32_t reserved_7_8          : 2;
21291         uint32_t tda                   : 1;  /**< [  9:  9](R/W) Trap debug access.
21292                                                                  When this bit is set to 1, any valid nonsecure access to the
21293                                                                      debug registers from EL2 or below, other than the registers
21294                                                                      trapped by the TDRA and TDOSA bits, is trapped to EL3.
21295                                                                  0 = Has no effect on accesses to debug registers.
21296                                                                  1 = Trap valid nonsecure accesses to debug registers to EL3. */
21297         uint32_t tdosa                 : 1;  /**< [ 10: 10](R/W) Trap debug OS-related register access.
21298                                                                  When this bit is set to 1, any access to the following
21299                                                                      registers from EL2 or below is trapped to EL3:
21300 
21301                                                                  AArch32: DBGOSLAR, DBGOSLSR, DBGOSDLR, DBGPRCR.
21302 
21303                                                                  AArch64: AP_OSLAR_EL1, AP_OSLSR_EL1, AP_OSDLR_EL1, AP_DBGPRCR_EL1.
21304 
21305                                                                  0 = Has no effect on accesses to OS-related debug registers.
21306                                                                  1 = Trap valid accesses to OS-related debug registers to EL3. */
21307         uint32_t reserved_11_13        : 3;
21308         uint32_t reserved_14_15        : 2;
21309         uint32_t sdd                   : 1;  /**< [ 16: 16](R/W) AArch64 secure self-hosted invasive debug disable. Disables
21310                                                                      Software debug exceptions in Secure state, other than Software
21311                                                                      breakpoint instruction.
21312                                                                  SDD only applies when both of the following are true:
21313                                                                   The processor is executing in Secure state.
21314                                                                   Secure EL1 is using AArch64.
21315                                                                  0 = Taking Software debug events as debug exceptions is permitted
21316                                                                      from Secure EL0 and EL1, if enabled by the relevant AP_MDSCR_EL1
21317                                                                      and PSTATE[D] flags.
21318                                                                  1 = Software debug events, other than software breakpoint
21319                                                                      instruction debug events, are disabled from all Exception
21320                                                                      levels in Secure state. */
21321         uint32_t spme                  : 1;  /**< [ 17: 17](R/W) Secure performance monitors enable. This allows event counting
21322                                                                      in Secure state:
21323                                                                  0 = Event counting prohibited in Secure state, unless overridden
21324                                                                      by the authentication interface.
21325                                                                  1 = Event counting allowed in Secure state. */
21326         uint32_t reserved_18_19        : 2;
21327         uint32_t edad                  : 1;  /**< [ 20: 20](R/W) External debugger access to breakpoint and watchpoint
21328                                                                      registers disabled. This disables access to these registers by
21329                                                                      an external debugger:
21330                                                                  0 = Access to breakpoint and watchpoint registers from external
21331                                                                      debugger is permitted.
21332                                                                  1 = Access to breakpoint and watchpoint registers from external
21333                                                                      debugger is disabled, unless overridden by authentication
21334                                                                      interface. */
21335         uint32_t epmad                 : 1;  /**< [ 21: 21](R/W) External debugger access to Performance Monitors registers
21336                                                                      disabled. This disables access to these registers by an
21337                                                                      external debugger:
21338                                                                  0 = Access to Performance Monitors registers from external
21339                                                                      debugger is permitted.
21340                                                                  1 = Access to Performance Monitors registers from external
21341                                                                      debugger is disabled, unless overridden by authentication
21342                                                                      interface. */
21343         uint32_t reserved_22_31        : 10;
21344 #endif /* Word 0 - End */
21345     } cn8;
21346     /* struct bdk_ap_mdcr_el3_s cn9; */
21347 };
21348 typedef union bdk_ap_mdcr_el3 bdk_ap_mdcr_el3_t;
21349 
21350 #define BDK_AP_MDCR_EL3 BDK_AP_MDCR_EL3_FUNC()
21351 static inline uint64_t BDK_AP_MDCR_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_MDCR_EL3_FUNC(void)21352 static inline uint64_t BDK_AP_MDCR_EL3_FUNC(void)
21353 {
21354     return 0x30601030100ll;
21355 }
21356 
21357 #define typedef_BDK_AP_MDCR_EL3 bdk_ap_mdcr_el3_t
21358 #define bustype_BDK_AP_MDCR_EL3 BDK_CSR_TYPE_SYSREG
21359 #define basename_BDK_AP_MDCR_EL3 "AP_MDCR_EL3"
21360 #define busnum_BDK_AP_MDCR_EL3 0
21361 #define arguments_BDK_AP_MDCR_EL3 -1,-1,-1,-1
21362 
21363 /**
21364  * Register (SYSREG) ap_mdrar_el1
21365  *
21366  * AP Monitor Debug ROM Address Register
21367  * Defines the base physical address of a 4KB-aligned memory-
21368  *     mapped debug component, usually a ROM table that locates and
21369  *     describes the memory-mapped debug components in the system.
21370  */
21371 union bdk_ap_mdrar_el1
21372 {
21373     uint64_t u;
21374     struct bdk_ap_mdrar_el1_s
21375     {
21376 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
21377         uint64_t reserved_48_63        : 16;
21378         uint64_t romaddr               : 36; /**< [ 47: 12](RO) Bits[P-1:12] of the ROM table physical address, where P is the
21379                                                                      physical address size in bits (up to 48 bits) as stored in
21380                                                                      AP_ID_AA64MMFR0_EL1. If P is less than 48, bits[47:P] of this
21381                                                                      register are RES0.
21382 
21383                                                                  Bits [11:0] of the ROM table physical address are zero.
21384 
21385                                                                  If EL3 is implemented, ROMADDR is an address in nonsecure
21386                                                                      memory. Whether the ROM table is also accessible in Secure
21387                                                                      memory is implementation defined. */
21388         uint64_t reserved_2_11         : 10;
21389         uint64_t valid                 : 2;  /**< [  1:  0](RO) This field indicates whether the ROM Table address is valid.
21390 
21391                                                                  0x0 = ROM Table address is not valid
21392                                                                  0x3 = ROM Table address is valid. */
21393 #else /* Word 0 - Little Endian */
21394         uint64_t valid                 : 2;  /**< [  1:  0](RO) This field indicates whether the ROM Table address is valid.
21395 
21396                                                                  0x0 = ROM Table address is not valid
21397                                                                  0x3 = ROM Table address is valid. */
21398         uint64_t reserved_2_11         : 10;
21399         uint64_t romaddr               : 36; /**< [ 47: 12](RO) Bits[P-1:12] of the ROM table physical address, where P is the
21400                                                                      physical address size in bits (up to 48 bits) as stored in
21401                                                                      AP_ID_AA64MMFR0_EL1. If P is less than 48, bits[47:P] of this
21402                                                                      register are RES0.
21403 
21404                                                                  Bits [11:0] of the ROM table physical address are zero.
21405 
21406                                                                  If EL3 is implemented, ROMADDR is an address in nonsecure
21407                                                                      memory. Whether the ROM table is also accessible in Secure
21408                                                                      memory is implementation defined. */
21409         uint64_t reserved_48_63        : 16;
21410 #endif /* Word 0 - End */
21411     } s;
21412     /* struct bdk_ap_mdrar_el1_s cn; */
21413 };
21414 typedef union bdk_ap_mdrar_el1 bdk_ap_mdrar_el1_t;
21415 
21416 #define BDK_AP_MDRAR_EL1 BDK_AP_MDRAR_EL1_FUNC()
21417 static inline uint64_t BDK_AP_MDRAR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_MDRAR_EL1_FUNC(void)21418 static inline uint64_t BDK_AP_MDRAR_EL1_FUNC(void)
21419 {
21420     return 0x20001000000ll;
21421 }
21422 
21423 #define typedef_BDK_AP_MDRAR_EL1 bdk_ap_mdrar_el1_t
21424 #define bustype_BDK_AP_MDRAR_EL1 BDK_CSR_TYPE_SYSREG
21425 #define basename_BDK_AP_MDRAR_EL1 "AP_MDRAR_EL1"
21426 #define busnum_BDK_AP_MDRAR_EL1 0
21427 #define arguments_BDK_AP_MDRAR_EL1 -1,-1,-1,-1
21428 
21429 /**
21430  * Register (SYSREG) ap_mdscr_el1
21431  *
21432  * AP Monitor Debug System Control Register
21433  * Main control register for the debug implementation.
21434  */
21435 union bdk_ap_mdscr_el1
21436 {
21437     uint32_t u;
21438     struct bdk_ap_mdscr_el1_s
21439     {
21440 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
21441         uint32_t reserved_31           : 1;
21442         uint32_t rxfull                : 1;  /**< [ 30: 30](R/W) Used for save/restore of EDSCR[RXfull].
21443                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21444                                                                      is RO, and software must treat it as UNK/SBZP.
21445 
21446                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21447                                                                      RW. */
21448         uint32_t txfull                : 1;  /**< [ 29: 29](R/W) Used for save/restore of EDSCR[TXfull].
21449                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21450                                                                      is RO, and software must treat it as UNK/SBZP.
21451 
21452                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21453                                                                      RW. */
21454         uint32_t reserved_28           : 1;
21455         uint32_t rxo                   : 1;  /**< [ 27: 27](R/W) Used for save/restore of EDSCR[RXO].
21456                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21457                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21458                                                                      policy for writes.
21459 
21460                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21461                                                                      RW. */
21462         uint32_t txu                   : 1;  /**< [ 26: 26](R/W) Used for save/restore of EDSCR[TXU].
21463                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21464                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21465                                                                      policy for writes.
21466 
21467                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21468                                                                      RW. */
21469         uint32_t reserved_24_25        : 2;
21470         uint32_t intdis                : 2;  /**< [ 23: 22](R/W) Used for save/restore of EDSCR[INTdis].
21471                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this field
21472                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21473                                                                      policy for writes.
21474 
21475                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this field
21476                                                                      is RW. */
21477         uint32_t tda                   : 1;  /**< [ 21: 21](R/W) Used for save/restore of EDSCR[TDA].
21478                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21479                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21480                                                                      policy for writes.
21481 
21482                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21483                                                                      RW. */
21484         uint32_t reserved_20           : 1;
21485         uint32_t sc2                   : 1;  /**< [ 19: 19](R/W) Used for save/restore of EDSCR[SC2].
21486 
21487                                                                  When AP_OSLSR_EL1[OSLK] = 0 (the OS lock is unlocked), this bit is
21488                                                                  read-only. Software must treat it as unknown and use an SBZP policy for writes.
21489 
21490                                                                  When AP_OSLSR_EL1[OSLK] = 1 (the OS lock is locked), this bit is R/W. */
21491         uint32_t reserved_16_18        : 3;
21492         uint32_t mde                   : 1;  /**< [ 15: 15](R/W) Monitor debug events. Enable Breakpoint, Watchpoint, and
21493                                                                      Vector catch debug exceptions.
21494                                                                  0 = Breakpoint, Watchpoint, and Vector catch debug exceptions
21495                                                                      disabled.
21496                                                                  1 = Breakpoint, Watchpoint, and Vector catch debug exceptions
21497                                                                      enabled. */
21498         uint32_t hde                   : 1;  /**< [ 14: 14](R/W) Used for save/restore of EDSCR[HDE].
21499 
21500                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21501                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21502                                                                      policy for writes.
21503 
21504                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21505                                                                      RW. */
21506         uint32_t kde                   : 1;  /**< [ 13: 13](R/W) Local (kernel) debug enable. If EL{d} is using
21507                                                                      AArch64, enable Software debug events within EL{d}.
21508 
21509                                                                  RES0 if EL{d} is using AArch32.
21510                                                                  0 = Software debug events, other than Software breakpoint
21511                                                                      instructions, disabled within EL{d}.
21512                                                                  1 = Software debug events enabled within EL{d}. */
21513         uint32_t tdcc                  : 1;  /**< [ 12: 12](R/W) Trap Debug Communications Channel access. When set, any EL0
21514                                                                      access to the following registers is trapped to EL1:
21515 
21516                                                                  AArch32: DBGDIDR, DBGDRAR, DBGDSAR, DBGDSCRint, DBGDTRTXint,
21517                                                                      DBGDTRRXint.
21518 
21519                                                                  AArch64: AP_MDCCSR_EL0, AP_DBGDTR_EL0, AP_DBGDTRTX_EL0, AP_DBGDTRRX_EL0. */
21520         uint32_t reserved_7_11         : 5;
21521         uint32_t err                   : 1;  /**< [  6:  6](R/W) Used for save/restore of EDSCR[ERR].
21522 
21523                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21524                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21525                                                                      policy for writes.
21526 
21527                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21528                                                                      RW. */
21529         uint32_t reserved_1_5          : 5;
21530         uint32_t ss                    : 1;  /**< [  0:  0](R/W) Software step control bit. If EL{d} is using AArch64,
21531                                                                      enable Software step.
21532                                                                  RES0 if EL{d} is using AArch32.
21533                                                                  0 = Software step disabled
21534                                                                  1 = Software step enabled. */
21535 #else /* Word 0 - Little Endian */
21536         uint32_t ss                    : 1;  /**< [  0:  0](R/W) Software step control bit. If EL{d} is using AArch64,
21537                                                                      enable Software step.
21538                                                                  RES0 if EL{d} is using AArch32.
21539                                                                  0 = Software step disabled
21540                                                                  1 = Software step enabled. */
21541         uint32_t reserved_1_5          : 5;
21542         uint32_t err                   : 1;  /**< [  6:  6](R/W) Used for save/restore of EDSCR[ERR].
21543 
21544                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21545                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21546                                                                      policy for writes.
21547 
21548                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21549                                                                      RW. */
21550         uint32_t reserved_7_11         : 5;
21551         uint32_t tdcc                  : 1;  /**< [ 12: 12](R/W) Trap Debug Communications Channel access. When set, any EL0
21552                                                                      access to the following registers is trapped to EL1:
21553 
21554                                                                  AArch32: DBGDIDR, DBGDRAR, DBGDSAR, DBGDSCRint, DBGDTRTXint,
21555                                                                      DBGDTRRXint.
21556 
21557                                                                  AArch64: AP_MDCCSR_EL0, AP_DBGDTR_EL0, AP_DBGDTRTX_EL0, AP_DBGDTRRX_EL0. */
21558         uint32_t kde                   : 1;  /**< [ 13: 13](R/W) Local (kernel) debug enable. If EL{d} is using
21559                                                                      AArch64, enable Software debug events within EL{d}.
21560 
21561                                                                  RES0 if EL{d} is using AArch32.
21562                                                                  0 = Software debug events, other than Software breakpoint
21563                                                                      instructions, disabled within EL{d}.
21564                                                                  1 = Software debug events enabled within EL{d}. */
21565         uint32_t hde                   : 1;  /**< [ 14: 14](R/W) Used for save/restore of EDSCR[HDE].
21566 
21567                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21568                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21569                                                                      policy for writes.
21570 
21571                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21572                                                                      RW. */
21573         uint32_t mde                   : 1;  /**< [ 15: 15](R/W) Monitor debug events. Enable Breakpoint, Watchpoint, and
21574                                                                      Vector catch debug exceptions.
21575                                                                  0 = Breakpoint, Watchpoint, and Vector catch debug exceptions
21576                                                                      disabled.
21577                                                                  1 = Breakpoint, Watchpoint, and Vector catch debug exceptions
21578                                                                      enabled. */
21579         uint32_t reserved_16_18        : 3;
21580         uint32_t sc2                   : 1;  /**< [ 19: 19](R/W) Used for save/restore of EDSCR[SC2].
21581 
21582                                                                  When AP_OSLSR_EL1[OSLK] = 0 (the OS lock is unlocked), this bit is
21583                                                                  read-only. Software must treat it as unknown and use an SBZP policy for writes.
21584 
21585                                                                  When AP_OSLSR_EL1[OSLK] = 1 (the OS lock is locked), this bit is R/W. */
21586         uint32_t reserved_20           : 1;
21587         uint32_t tda                   : 1;  /**< [ 21: 21](R/W) Used for save/restore of EDSCR[TDA].
21588                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21589                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21590                                                                      policy for writes.
21591 
21592                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21593                                                                      RW. */
21594         uint32_t intdis                : 2;  /**< [ 23: 22](R/W) Used for save/restore of EDSCR[INTdis].
21595                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this field
21596                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21597                                                                      policy for writes.
21598 
21599                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this field
21600                                                                      is RW. */
21601         uint32_t reserved_24_25        : 2;
21602         uint32_t txu                   : 1;  /**< [ 26: 26](R/W) Used for save/restore of EDSCR[TXU].
21603                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21604                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21605                                                                      policy for writes.
21606 
21607                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21608                                                                      RW. */
21609         uint32_t rxo                   : 1;  /**< [ 27: 27](R/W) Used for save/restore of EDSCR[RXO].
21610                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21611                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21612                                                                      policy for writes.
21613 
21614                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21615                                                                      RW. */
21616         uint32_t reserved_28           : 1;
21617         uint32_t txfull                : 1;  /**< [ 29: 29](R/W) Used for save/restore of EDSCR[TXfull].
21618                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21619                                                                      is RO, and software must treat it as UNK/SBZP.
21620 
21621                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21622                                                                      RW. */
21623         uint32_t rxfull                : 1;  /**< [ 30: 30](R/W) Used for save/restore of EDSCR[RXfull].
21624                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21625                                                                      is RO, and software must treat it as UNK/SBZP.
21626 
21627                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21628                                                                      RW. */
21629         uint32_t reserved_31           : 1;
21630 #endif /* Word 0 - End */
21631     } s;
21632     struct bdk_ap_mdscr_el1_cn88xxp1
21633     {
21634 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
21635         uint32_t reserved_31           : 1;
21636         uint32_t rxfull                : 1;  /**< [ 30: 30](R/W) Used for save/restore of EDSCR[RXfull].
21637                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21638                                                                      is RO, and software must treat it as UNK/SBZP.
21639 
21640                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21641                                                                      RW. */
21642         uint32_t txfull                : 1;  /**< [ 29: 29](R/W) Used for save/restore of EDSCR[TXfull].
21643                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21644                                                                      is RO, and software must treat it as UNK/SBZP.
21645 
21646                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21647                                                                      RW. */
21648         uint32_t reserved_28           : 1;
21649         uint32_t rxo                   : 1;  /**< [ 27: 27](R/W) Used for save/restore of EDSCR[RXO].
21650                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21651                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21652                                                                      policy for writes.
21653 
21654                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21655                                                                      RW. */
21656         uint32_t txu                   : 1;  /**< [ 26: 26](R/W) Used for save/restore of EDSCR[TXU].
21657                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21658                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21659                                                                      policy for writes.
21660 
21661                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21662                                                                      RW. */
21663         uint32_t reserved_24_25        : 2;
21664         uint32_t intdis                : 2;  /**< [ 23: 22](R/W) Used for save/restore of EDSCR[INTdis].
21665                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this field
21666                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21667                                                                      policy for writes.
21668 
21669                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this field
21670                                                                      is RW. */
21671         uint32_t tda                   : 1;  /**< [ 21: 21](R/W) Used for save/restore of EDSCR[TDA].
21672                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21673                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21674                                                                      policy for writes.
21675 
21676                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21677                                                                      RW. */
21678         uint32_t reserved_20           : 1;
21679         uint32_t reserved_19           : 1;
21680         uint32_t reserved_16_18        : 3;
21681         uint32_t mde                   : 1;  /**< [ 15: 15](R/W) Monitor debug events. Enable Breakpoint, Watchpoint, and
21682                                                                      Vector catch debug exceptions.
21683                                                                  0 = Breakpoint, Watchpoint, and Vector catch debug exceptions
21684                                                                      disabled.
21685                                                                  1 = Breakpoint, Watchpoint, and Vector catch debug exceptions
21686                                                                      enabled. */
21687         uint32_t hde                   : 1;  /**< [ 14: 14](R/W) Used for save/restore of EDSCR[HDE].
21688 
21689                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21690                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21691                                                                      policy for writes.
21692 
21693                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21694                                                                      RW. */
21695         uint32_t kde                   : 1;  /**< [ 13: 13](R/W) Local (kernel) debug enable. If EL{d} is using
21696                                                                      AArch64, enable Software debug events within EL{d}.
21697 
21698                                                                  RES0 if EL{d} is using AArch32.
21699                                                                  0 = Software debug events, other than Software breakpoint
21700                                                                      instructions, disabled within EL{d}.
21701                                                                  1 = Software debug events enabled within EL{d}. */
21702         uint32_t tdcc                  : 1;  /**< [ 12: 12](R/W) Trap Debug Communications Channel access. When set, any EL0
21703                                                                      access to the following registers is trapped to EL1:
21704 
21705                                                                  AArch32: DBGDIDR, DBGDRAR, DBGDSAR, DBGDSCRint, DBGDTRTXint,
21706                                                                      DBGDTRRXint.
21707 
21708                                                                  AArch64: AP_MDCCSR_EL0, AP_DBGDTR_EL0, AP_DBGDTRTX_EL0, AP_DBGDTRRX_EL0. */
21709         uint32_t reserved_7_11         : 5;
21710         uint32_t err                   : 1;  /**< [  6:  6](R/W) Used for save/restore of EDSCR[ERR].
21711 
21712                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21713                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21714                                                                      policy for writes.
21715 
21716                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21717                                                                      RW. */
21718         uint32_t reserved_1_5          : 5;
21719         uint32_t ss                    : 1;  /**< [  0:  0](R/W) Software step control bit. If EL{d} is using AArch64,
21720                                                                      enable Software step.
21721                                                                  RES0 if EL{d} is using AArch32.
21722                                                                  0 = Software step disabled
21723                                                                  1 = Software step enabled. */
21724 #else /* Word 0 - Little Endian */
21725         uint32_t ss                    : 1;  /**< [  0:  0](R/W) Software step control bit. If EL{d} is using AArch64,
21726                                                                      enable Software step.
21727                                                                  RES0 if EL{d} is using AArch32.
21728                                                                  0 = Software step disabled
21729                                                                  1 = Software step enabled. */
21730         uint32_t reserved_1_5          : 5;
21731         uint32_t err                   : 1;  /**< [  6:  6](R/W) Used for save/restore of EDSCR[ERR].
21732 
21733                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21734                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21735                                                                      policy for writes.
21736 
21737                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21738                                                                      RW. */
21739         uint32_t reserved_7_11         : 5;
21740         uint32_t tdcc                  : 1;  /**< [ 12: 12](R/W) Trap Debug Communications Channel access. When set, any EL0
21741                                                                      access to the following registers is trapped to EL1:
21742 
21743                                                                  AArch32: DBGDIDR, DBGDRAR, DBGDSAR, DBGDSCRint, DBGDTRTXint,
21744                                                                      DBGDTRRXint.
21745 
21746                                                                  AArch64: AP_MDCCSR_EL0, AP_DBGDTR_EL0, AP_DBGDTRTX_EL0, AP_DBGDTRRX_EL0. */
21747         uint32_t kde                   : 1;  /**< [ 13: 13](R/W) Local (kernel) debug enable. If EL{d} is using
21748                                                                      AArch64, enable Software debug events within EL{d}.
21749 
21750                                                                  RES0 if EL{d} is using AArch32.
21751                                                                  0 = Software debug events, other than Software breakpoint
21752                                                                      instructions, disabled within EL{d}.
21753                                                                  1 = Software debug events enabled within EL{d}. */
21754         uint32_t hde                   : 1;  /**< [ 14: 14](R/W) Used for save/restore of EDSCR[HDE].
21755 
21756                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21757                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21758                                                                      policy for writes.
21759 
21760                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21761                                                                      RW. */
21762         uint32_t mde                   : 1;  /**< [ 15: 15](R/W) Monitor debug events. Enable Breakpoint, Watchpoint, and
21763                                                                      Vector catch debug exceptions.
21764                                                                  0 = Breakpoint, Watchpoint, and Vector catch debug exceptions
21765                                                                      disabled.
21766                                                                  1 = Breakpoint, Watchpoint, and Vector catch debug exceptions
21767                                                                      enabled. */
21768         uint32_t reserved_16_18        : 3;
21769         uint32_t reserved_19           : 1;
21770         uint32_t reserved_20           : 1;
21771         uint32_t tda                   : 1;  /**< [ 21: 21](R/W) Used for save/restore of EDSCR[TDA].
21772                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21773                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21774                                                                      policy for writes.
21775 
21776                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21777                                                                      RW. */
21778         uint32_t intdis                : 2;  /**< [ 23: 22](R/W) Used for save/restore of EDSCR[INTdis].
21779                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this field
21780                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21781                                                                      policy for writes.
21782 
21783                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this field
21784                                                                      is RW. */
21785         uint32_t reserved_24_25        : 2;
21786         uint32_t txu                   : 1;  /**< [ 26: 26](R/W) Used for save/restore of EDSCR[TXU].
21787                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21788                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21789                                                                      policy for writes.
21790 
21791                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21792                                                                      RW. */
21793         uint32_t rxo                   : 1;  /**< [ 27: 27](R/W) Used for save/restore of EDSCR[RXO].
21794                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21795                                                                      is RO. Software must treat it as UNKNOWN and use an SBZP
21796                                                                      policy for writes.
21797 
21798                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21799                                                                      RW. */
21800         uint32_t reserved_28           : 1;
21801         uint32_t txfull                : 1;  /**< [ 29: 29](R/W) Used for save/restore of EDSCR[TXfull].
21802                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21803                                                                      is RO, and software must treat it as UNK/SBZP.
21804 
21805                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21806                                                                      RW. */
21807         uint32_t rxfull                : 1;  /**< [ 30: 30](R/W) Used for save/restore of EDSCR[RXfull].
21808                                                                  When AP_OSLSR_EL1[OSLK] == 0 (the OS lock is unlocked), this bit
21809                                                                      is RO, and software must treat it as UNK/SBZP.
21810 
21811                                                                  When AP_OSLSR_EL1[OSLK] == 1 (the OS lock is locked), this bit is
21812                                                                      RW. */
21813         uint32_t reserved_31           : 1;
21814 #endif /* Word 0 - End */
21815     } cn88xxp1;
21816     /* struct bdk_ap_mdscr_el1_s cn9; */
21817     /* struct bdk_ap_mdscr_el1_s cn81xx; */
21818     /* struct bdk_ap_mdscr_el1_s cn83xx; */
21819     /* struct bdk_ap_mdscr_el1_s cn88xxp2; */
21820 };
21821 typedef union bdk_ap_mdscr_el1 bdk_ap_mdscr_el1_t;
21822 
21823 #define BDK_AP_MDSCR_EL1 BDK_AP_MDSCR_EL1_FUNC()
21824 static inline uint64_t BDK_AP_MDSCR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_MDSCR_EL1_FUNC(void)21825 static inline uint64_t BDK_AP_MDSCR_EL1_FUNC(void)
21826 {
21827     return 0x20000020200ll;
21828 }
21829 
21830 #define typedef_BDK_AP_MDSCR_EL1 bdk_ap_mdscr_el1_t
21831 #define bustype_BDK_AP_MDSCR_EL1 BDK_CSR_TYPE_SYSREG
21832 #define basename_BDK_AP_MDSCR_EL1 "AP_MDSCR_EL1"
21833 #define busnum_BDK_AP_MDSCR_EL1 0
21834 #define arguments_BDK_AP_MDSCR_EL1 -1,-1,-1,-1
21835 
21836 /**
21837  * Register (SYSREG) ap_midr_el1
21838  *
21839  * AP Main ID Register
21840  * This register provides identification information for the PE, including an
21841  * implementer code for the device and a device ID number.
21842  */
21843 union bdk_ap_midr_el1
21844 {
21845     uint32_t u;
21846     struct bdk_ap_midr_el1_s
21847     {
21848 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
21849         uint32_t implementer           : 8;  /**< [ 31: 24](RO) Implementer code that has been assigned by ARM. Assigned codes include the
21850                                                                  following:
21851                                                                  0x41 = 'A' = ARM Limited.
21852                                                                  0x42 = 'B' = Broadcom Corporation.
21853                                                                  0x43 = 'C' = Cavium Inc.
21854                                                                  0x44 = 'D' = Digital Equipment Corporation.
21855                                                                  0x49 = 'I' = Infineon Technologies AG.
21856                                                                  0x4D = 'M' = Motorola or Freescale Semiconductor Inc.
21857                                                                  0x4E = 'N' = NVIDIA Corporation.
21858                                                                  0x50 = 'P' = Applied Micro Circuits Corporation.
21859                                                                  0x51 = 'Q' = Qualcomm Inc.
21860                                                                  0x56 = 'V' = Marvell International Ltd.
21861                                                                  0x69 = 'i' = Intel Corporation.
21862 
21863                                                                  For CNXXXX, 'C'. */
21864         uint32_t variant               : 4;  /**< [ 23: 20](RO) An implementation defined variant number. Typically, this
21865                                                                      field is used to distinguish between different product
21866                                                                      variants, or major revisions of a product.
21867 
21868                                                                  For CNXXXX this is the major revision field.
21869                                                                  See MIO_FUS_DAT2[CHIP_ID] bits 21..19 for more information. */
21870         uint32_t architecture          : 4;  /**< [ 19: 16](RO) 0x1 = ARMv4.
21871                                                                  0x2 = ARMv4T.
21872                                                                  0x3 = ARMv5 (obsolete).
21873                                                                  0x4 = ARMv5T.
21874                                                                  0x5 = ARMv5TE.
21875                                                                  0x6 = ARMv5TEJ.
21876                                                                  0x7 = ARMv6.
21877                                                                  0xF = Defined by CPUID scheme.
21878 
21879                                                                  For CNXXXX, CPUID scheme. */
21880         uint32_t partnum               : 12; /**< [ 15:  4](RO) An implementation defined primary part number for the device.
21881                                                                  On processors implemented by ARM, if the top four bits of the
21882                                                                      primary part number are 0x00x7.
21883                                                                  Processors implemented by ARM have an Implementer code of 0x41.
21884 
21885                                                                  For CNXXXX, the chip ID. Enumerated by PCC_PROD_E. */
21886         uint32_t revision              : 4;  /**< [  3:  0](RO) An implementation defined revision number for the device.
21887 
21888                                                                  For CNXXXX this is the minor revision field.
21889                                                                  See MIO_FUS_DAT2[CHIP_ID] bits 18..16 for more information. */
21890 #else /* Word 0 - Little Endian */
21891         uint32_t revision              : 4;  /**< [  3:  0](RO) An implementation defined revision number for the device.
21892 
21893                                                                  For CNXXXX this is the minor revision field.
21894                                                                  See MIO_FUS_DAT2[CHIP_ID] bits 18..16 for more information. */
21895         uint32_t partnum               : 12; /**< [ 15:  4](RO) An implementation defined primary part number for the device.
21896                                                                  On processors implemented by ARM, if the top four bits of the
21897                                                                      primary part number are 0x00x7.
21898                                                                  Processors implemented by ARM have an Implementer code of 0x41.
21899 
21900                                                                  For CNXXXX, the chip ID. Enumerated by PCC_PROD_E. */
21901         uint32_t architecture          : 4;  /**< [ 19: 16](RO) 0x1 = ARMv4.
21902                                                                  0x2 = ARMv4T.
21903                                                                  0x3 = ARMv5 (obsolete).
21904                                                                  0x4 = ARMv5T.
21905                                                                  0x5 = ARMv5TE.
21906                                                                  0x6 = ARMv5TEJ.
21907                                                                  0x7 = ARMv6.
21908                                                                  0xF = Defined by CPUID scheme.
21909 
21910                                                                  For CNXXXX, CPUID scheme. */
21911         uint32_t variant               : 4;  /**< [ 23: 20](RO) An implementation defined variant number. Typically, this
21912                                                                      field is used to distinguish between different product
21913                                                                      variants, or major revisions of a product.
21914 
21915                                                                  For CNXXXX this is the major revision field.
21916                                                                  See MIO_FUS_DAT2[CHIP_ID] bits 21..19 for more information. */
21917         uint32_t implementer           : 8;  /**< [ 31: 24](RO) Implementer code that has been assigned by ARM. Assigned codes include the
21918                                                                  following:
21919                                                                  0x41 = 'A' = ARM Limited.
21920                                                                  0x42 = 'B' = Broadcom Corporation.
21921                                                                  0x43 = 'C' = Cavium Inc.
21922                                                                  0x44 = 'D' = Digital Equipment Corporation.
21923                                                                  0x49 = 'I' = Infineon Technologies AG.
21924                                                                  0x4D = 'M' = Motorola or Freescale Semiconductor Inc.
21925                                                                  0x4E = 'N' = NVIDIA Corporation.
21926                                                                  0x50 = 'P' = Applied Micro Circuits Corporation.
21927                                                                  0x51 = 'Q' = Qualcomm Inc.
21928                                                                  0x56 = 'V' = Marvell International Ltd.
21929                                                                  0x69 = 'i' = Intel Corporation.
21930 
21931                                                                  For CNXXXX, 'C'. */
21932 #endif /* Word 0 - End */
21933     } s;
21934     /* struct bdk_ap_midr_el1_s cn; */
21935 };
21936 typedef union bdk_ap_midr_el1 bdk_ap_midr_el1_t;
21937 
21938 #define BDK_AP_MIDR_EL1 BDK_AP_MIDR_EL1_FUNC()
21939 static inline uint64_t BDK_AP_MIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_MIDR_EL1_FUNC(void)21940 static inline uint64_t BDK_AP_MIDR_EL1_FUNC(void)
21941 {
21942     return 0x30000000000ll;
21943 }
21944 
21945 #define typedef_BDK_AP_MIDR_EL1 bdk_ap_midr_el1_t
21946 #define bustype_BDK_AP_MIDR_EL1 BDK_CSR_TYPE_SYSREG
21947 #define basename_BDK_AP_MIDR_EL1 "AP_MIDR_EL1"
21948 #define busnum_BDK_AP_MIDR_EL1 0
21949 #define arguments_BDK_AP_MIDR_EL1 -1,-1,-1,-1
21950 
21951 /**
21952  * Register (SYSREG) ap_mpidr_el1
21953  *
21954  * AP Multiprocessor Affinity Register
21955  * This register in a multiprocessor system provides an additional PE identification
21956  * mechanism for scheduling purposes, and indicates whether the implementation includes
21957  * the multiprocessing extensions.
21958  */
21959 union bdk_ap_mpidr_el1
21960 {
21961     uint64_t u;
21962     struct bdk_ap_mpidr_el1_s
21963     {
21964 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
21965         uint64_t reserved_40_63        : 24;
21966         uint64_t aff3                  : 8;  /**< [ 39: 32](RO) Affinity level 3. Highest level affinity field.
21967 
21968                                                                  Always zero on CNXXXX. */
21969         uint64_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
21970         uint64_t u                     : 1;  /**< [ 30: 30](RO) Indicates a uniprocessor system, as distinct from PE 0 in a
21971                                                                      multiprocessor system.
21972                                                                  0 = Processor is part of a multiprocessor system.
21973                                                                  1 = Processor is part of a uniprocessor system. */
21974         uint64_t reserved_25_29        : 5;
21975         uint64_t mt                    : 1;  /**< [ 24: 24](RO) Indicates whether the lowest level of affinity consists of
21976                                                                      logical PEs that are implemented using a multi-threading type
21977                                                                      approach.
21978                                                                  0 = Performance of PEs at the lowest affinity level is largely
21979                                                                      independent.
21980                                                                  1 = Performance of PEs at the lowest affinity level is very
21981                                                                      interdependent. */
21982         uint64_t aff2                  : 8;  /**< [ 23: 16](RO) Affinity level 2. Second highest level affinity field.
21983 
21984                                                                  For CNXXXX, the socket number. */
21985         uint64_t aff1                  : 8;  /**< [ 15:  8](RO) Affinity level 1. Third highest level affinity field.
21986 
21987                                                                  For CNXXXX the processor number upper 2 bits. */
21988         uint64_t aff0                  : 8;  /**< [  7:  0](RO) Affinity level 0. Lowest level affinity field.
21989                                                                  WARNING: The GIC register ICC_SGI{0,1}R_EL1 limits this
21990                                                                  to 0-15 as its a 16 bit mask.
21991 
21992                                                                  For CNXXXX the processor number lower 4 bits. */
21993 #else /* Word 0 - Little Endian */
21994         uint64_t aff0                  : 8;  /**< [  7:  0](RO) Affinity level 0. Lowest level affinity field.
21995                                                                  WARNING: The GIC register ICC_SGI{0,1}R_EL1 limits this
21996                                                                  to 0-15 as its a 16 bit mask.
21997 
21998                                                                  For CNXXXX the processor number lower 4 bits. */
21999         uint64_t aff1                  : 8;  /**< [ 15:  8](RO) Affinity level 1. Third highest level affinity field.
22000 
22001                                                                  For CNXXXX the processor number upper 2 bits. */
22002         uint64_t aff2                  : 8;  /**< [ 23: 16](RO) Affinity level 2. Second highest level affinity field.
22003 
22004                                                                  For CNXXXX, the socket number. */
22005         uint64_t mt                    : 1;  /**< [ 24: 24](RO) Indicates whether the lowest level of affinity consists of
22006                                                                      logical PEs that are implemented using a multi-threading type
22007                                                                      approach.
22008                                                                  0 = Performance of PEs at the lowest affinity level is largely
22009                                                                      independent.
22010                                                                  1 = Performance of PEs at the lowest affinity level is very
22011                                                                      interdependent. */
22012         uint64_t reserved_25_29        : 5;
22013         uint64_t u                     : 1;  /**< [ 30: 30](RO) Indicates a uniprocessor system, as distinct from PE 0 in a
22014                                                                      multiprocessor system.
22015                                                                  0 = Processor is part of a multiprocessor system.
22016                                                                  1 = Processor is part of a uniprocessor system. */
22017         uint64_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
22018         uint64_t aff3                  : 8;  /**< [ 39: 32](RO) Affinity level 3. Highest level affinity field.
22019 
22020                                                                  Always zero on CNXXXX. */
22021         uint64_t reserved_40_63        : 24;
22022 #endif /* Word 0 - End */
22023     } s;
22024     /* struct bdk_ap_mpidr_el1_s cn8; */
22025     struct bdk_ap_mpidr_el1_cn9
22026     {
22027 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22028         uint64_t reserved_40_63        : 24;
22029         uint64_t aff3                  : 8;  /**< [ 39: 32](RO) Affinity level 3. Highest level affinity field.
22030 
22031                                                                  Always zero on CNXXXX. */
22032         uint64_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
22033         uint64_t u                     : 1;  /**< [ 30: 30](RO) Indicates a uniprocessor system, as distinct from PE 0 in a
22034                                                                      multiprocessor system.
22035                                                                  0 = Processor is part of a multiprocessor system.
22036                                                                  1 = Processor is part of a uniprocessor system. */
22037         uint64_t reserved_25_29        : 5;
22038         uint64_t mt                    : 1;  /**< [ 24: 24](RO) Indicates whether the lowest level of affinity consists of
22039                                                                      logical PEs that are implemented using a multi-threading type
22040                                                                      approach.
22041                                                                  0 = Performance of PEs at the lowest affinity level is largely
22042                                                                      independent.
22043                                                                  1 = Performance of PEs at the lowest affinity level is very
22044                                                                      interdependent. */
22045         uint64_t aff2                  : 8;  /**< [ 23: 16](RO) Affinity level 2. Second highest level affinity field.
22046 
22047                                                                  For CNXXXX, the socket number. */
22048         uint64_t aff1                  : 8;  /**< [ 15:  8](RO) Affinity level 1. Third highest level affinity field.
22049 
22050                                                                  For CN93XX the processor number lower 2 bits. */
22051         uint64_t aff0                  : 8;  /**< [  7:  0](RO) Affinity level 0. Lowest level affinity field.
22052                                                                  WARNING: The GIC register ICC_SGI{0,1}R_EL1 limits this
22053                                                                  to 0-15 as its a 16 bit mask.
22054 
22055                                                                  For CN93XX the processor number upper 3 bits. */
22056 #else /* Word 0 - Little Endian */
22057         uint64_t aff0                  : 8;  /**< [  7:  0](RO) Affinity level 0. Lowest level affinity field.
22058                                                                  WARNING: The GIC register ICC_SGI{0,1}R_EL1 limits this
22059                                                                  to 0-15 as its a 16 bit mask.
22060 
22061                                                                  For CN93XX the processor number upper 3 bits. */
22062         uint64_t aff1                  : 8;  /**< [ 15:  8](RO) Affinity level 1. Third highest level affinity field.
22063 
22064                                                                  For CN93XX the processor number lower 2 bits. */
22065         uint64_t aff2                  : 8;  /**< [ 23: 16](RO) Affinity level 2. Second highest level affinity field.
22066 
22067                                                                  For CNXXXX, the socket number. */
22068         uint64_t mt                    : 1;  /**< [ 24: 24](RO) Indicates whether the lowest level of affinity consists of
22069                                                                      logical PEs that are implemented using a multi-threading type
22070                                                                      approach.
22071                                                                  0 = Performance of PEs at the lowest affinity level is largely
22072                                                                      independent.
22073                                                                  1 = Performance of PEs at the lowest affinity level is very
22074                                                                      interdependent. */
22075         uint64_t reserved_25_29        : 5;
22076         uint64_t u                     : 1;  /**< [ 30: 30](RO) Indicates a uniprocessor system, as distinct from PE 0 in a
22077                                                                      multiprocessor system.
22078                                                                  0 = Processor is part of a multiprocessor system.
22079                                                                  1 = Processor is part of a uniprocessor system. */
22080         uint64_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
22081         uint64_t aff3                  : 8;  /**< [ 39: 32](RO) Affinity level 3. Highest level affinity field.
22082 
22083                                                                  Always zero on CNXXXX. */
22084         uint64_t reserved_40_63        : 24;
22085 #endif /* Word 0 - End */
22086     } cn9;
22087 };
22088 typedef union bdk_ap_mpidr_el1 bdk_ap_mpidr_el1_t;
22089 
22090 #define BDK_AP_MPIDR_EL1 BDK_AP_MPIDR_EL1_FUNC()
22091 static inline uint64_t BDK_AP_MPIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_MPIDR_EL1_FUNC(void)22092 static inline uint64_t BDK_AP_MPIDR_EL1_FUNC(void)
22093 {
22094     return 0x30000000500ll;
22095 }
22096 
22097 #define typedef_BDK_AP_MPIDR_EL1 bdk_ap_mpidr_el1_t
22098 #define bustype_BDK_AP_MPIDR_EL1 BDK_CSR_TYPE_SYSREG
22099 #define basename_BDK_AP_MPIDR_EL1 "AP_MPIDR_EL1"
22100 #define busnum_BDK_AP_MPIDR_EL1 0
22101 #define arguments_BDK_AP_MPIDR_EL1 -1,-1,-1,-1
22102 
22103 /**
22104  * Register (SYSREG) ap_mvfr#_el1
22105  *
22106  * AP ARM32 Media and VFP Feature Register
22107  * Describes the features provided by the Advanced SIMD and Floating-point Extensions.
22108  */
22109 union bdk_ap_mvfrx_el1
22110 {
22111     uint32_t u;
22112     struct bdk_ap_mvfrx_el1_s
22113     {
22114 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22115         uint32_t reserved_0_31         : 32;
22116 #else /* Word 0 - Little Endian */
22117         uint32_t reserved_0_31         : 32;
22118 #endif /* Word 0 - End */
22119     } s;
22120     /* struct bdk_ap_mvfrx_el1_s cn; */
22121 };
22122 typedef union bdk_ap_mvfrx_el1 bdk_ap_mvfrx_el1_t;
22123 
22124 static inline uint64_t BDK_AP_MVFRX_EL1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_MVFRX_EL1(unsigned long a)22125 static inline uint64_t BDK_AP_MVFRX_EL1(unsigned long a)
22126 {
22127     if (a<=2)
22128         return 0x30000030000ll + 0x100ll * ((a) & 0x3);
22129     __bdk_csr_fatal("AP_MVFRX_EL1", 1, a, 0, 0, 0);
22130 }
22131 
22132 #define typedef_BDK_AP_MVFRX_EL1(a) bdk_ap_mvfrx_el1_t
22133 #define bustype_BDK_AP_MVFRX_EL1(a) BDK_CSR_TYPE_SYSREG
22134 #define basename_BDK_AP_MVFRX_EL1(a) "AP_MVFRX_EL1"
22135 #define busnum_BDK_AP_MVFRX_EL1(a) (a)
22136 #define arguments_BDK_AP_MVFRX_EL1(a) (a),-1,-1,-1
22137 
22138 /**
22139  * Register (SYSREG) ap_nzcv
22140  *
22141  * AP Condition Flags Register
22142  * Allows access to the condition flags.
22143  */
22144 union bdk_ap_nzcv
22145 {
22146     uint32_t u;
22147     struct bdk_ap_nzcv_s
22148     {
22149 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22150         uint32_t n                     : 1;  /**< [ 31: 31](R/W) Negative condition flag. Set to bit[31] of the result of the
22151                                                                      last flag-setting instruction. If the result is regarded as a
22152                                                                      two's complement signed integer, then the processor sets N to
22153                                                                      1 if the result was negative, and sets N to 0 if it was
22154                                                                      positive or zero. */
22155         uint32_t z                     : 1;  /**< [ 30: 30](R/W) Zero condition flag. Set to 1 if the result of the last flag-
22156                                                                      setting instruction was zero, and to 0 otherwise. A result of
22157                                                                      zero often indicates an equal result from a comparison. */
22158         uint32_t cc                    : 1;  /**< [ 29: 29](R/W) Carry condition flag. Set to 1 if the last flag-setting
22159                                                                      instruction resulted in a carry condition, for example an
22160                                                                      unsigned overflow on an addition. */
22161         uint32_t v                     : 1;  /**< [ 28: 28](R/W) Overflow condition flag. Set to 1 if the last flag-setting
22162                                                                      instruction resulted in an overflow condition, for example a
22163                                                                      signed overflow on an addition. */
22164         uint32_t reserved_0_27         : 28;
22165 #else /* Word 0 - Little Endian */
22166         uint32_t reserved_0_27         : 28;
22167         uint32_t v                     : 1;  /**< [ 28: 28](R/W) Overflow condition flag. Set to 1 if the last flag-setting
22168                                                                      instruction resulted in an overflow condition, for example a
22169                                                                      signed overflow on an addition. */
22170         uint32_t cc                    : 1;  /**< [ 29: 29](R/W) Carry condition flag. Set to 1 if the last flag-setting
22171                                                                      instruction resulted in a carry condition, for example an
22172                                                                      unsigned overflow on an addition. */
22173         uint32_t z                     : 1;  /**< [ 30: 30](R/W) Zero condition flag. Set to 1 if the result of the last flag-
22174                                                                      setting instruction was zero, and to 0 otherwise. A result of
22175                                                                      zero often indicates an equal result from a comparison. */
22176         uint32_t n                     : 1;  /**< [ 31: 31](R/W) Negative condition flag. Set to bit[31] of the result of the
22177                                                                      last flag-setting instruction. If the result is regarded as a
22178                                                                      two's complement signed integer, then the processor sets N to
22179                                                                      1 if the result was negative, and sets N to 0 if it was
22180                                                                      positive or zero. */
22181 #endif /* Word 0 - End */
22182     } s;
22183     /* struct bdk_ap_nzcv_s cn; */
22184 };
22185 typedef union bdk_ap_nzcv bdk_ap_nzcv_t;
22186 
22187 #define BDK_AP_NZCV BDK_AP_NZCV_FUNC()
22188 static inline uint64_t BDK_AP_NZCV_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_NZCV_FUNC(void)22189 static inline uint64_t BDK_AP_NZCV_FUNC(void)
22190 {
22191     return 0x30304020000ll;
22192 }
22193 
22194 #define typedef_BDK_AP_NZCV bdk_ap_nzcv_t
22195 #define bustype_BDK_AP_NZCV BDK_CSR_TYPE_SYSREG
22196 #define basename_BDK_AP_NZCV "AP_NZCV"
22197 #define busnum_BDK_AP_NZCV 0
22198 #define arguments_BDK_AP_NZCV -1,-1,-1,-1
22199 
22200 /**
22201  * Register (SYSREG) ap_osdlr_el1
22202  *
22203  * AP OS Double Lock Register
22204  * Used to control the OS Double Lock.
22205  */
22206 union bdk_ap_osdlr_el1
22207 {
22208     uint32_t u;
22209     struct bdk_ap_osdlr_el1_s
22210     {
22211 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22212         uint32_t reserved_1_31         : 31;
22213         uint32_t dlk                   : 1;  /**< [  0:  0](R/W) OS Double Lock control bit.
22214                                                                  0 = OS Double Lock unlocked.
22215                                                                  1 = OS Double Lock locked, if AP_DBGPRCR_EL1[CORENPDRQ] (Core no
22216                                                                      power-down request) bit is set to 0 and the processor is in
22217                                                                      Non-debug state. */
22218 #else /* Word 0 - Little Endian */
22219         uint32_t dlk                   : 1;  /**< [  0:  0](R/W) OS Double Lock control bit.
22220                                                                  0 = OS Double Lock unlocked.
22221                                                                  1 = OS Double Lock locked, if AP_DBGPRCR_EL1[CORENPDRQ] (Core no
22222                                                                      power-down request) bit is set to 0 and the processor is in
22223                                                                      Non-debug state. */
22224         uint32_t reserved_1_31         : 31;
22225 #endif /* Word 0 - End */
22226     } s;
22227     /* struct bdk_ap_osdlr_el1_s cn; */
22228 };
22229 typedef union bdk_ap_osdlr_el1 bdk_ap_osdlr_el1_t;
22230 
22231 #define BDK_AP_OSDLR_EL1 BDK_AP_OSDLR_EL1_FUNC()
22232 static inline uint64_t BDK_AP_OSDLR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_OSDLR_EL1_FUNC(void)22233 static inline uint64_t BDK_AP_OSDLR_EL1_FUNC(void)
22234 {
22235     return 0x20001030400ll;
22236 }
22237 
22238 #define typedef_BDK_AP_OSDLR_EL1 bdk_ap_osdlr_el1_t
22239 #define bustype_BDK_AP_OSDLR_EL1 BDK_CSR_TYPE_SYSREG
22240 #define basename_BDK_AP_OSDLR_EL1 "AP_OSDLR_EL1"
22241 #define busnum_BDK_AP_OSDLR_EL1 0
22242 #define arguments_BDK_AP_OSDLR_EL1 -1,-1,-1,-1
22243 
22244 /**
22245  * Register (SYSREG) ap_osdtrrx_el1
22246  *
22247  * AP OS Lock Data Transfer Receive Register
22248  * Used for save/restore of AP_DBGDTRRX_EL0. It is a component of
22249  *     the Debug Communications Channel.
22250  */
22251 union bdk_ap_osdtrrx_el1
22252 {
22253     uint32_t u;
22254     struct bdk_ap_osdtrrx_el1_s
22255     {
22256 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22257         uint32_t data                  : 32; /**< [ 31:  0](R/W) Host to target data. One word of data for transfer from the
22258                                                                      debug host to the debug target.
22259                                                                  For the full behavior of the Debug Communications Channel,
22260                                                                      see. */
22261 #else /* Word 0 - Little Endian */
22262         uint32_t data                  : 32; /**< [ 31:  0](R/W) Host to target data. One word of data for transfer from the
22263                                                                      debug host to the debug target.
22264                                                                  For the full behavior of the Debug Communications Channel,
22265                                                                      see. */
22266 #endif /* Word 0 - End */
22267     } s;
22268     /* struct bdk_ap_osdtrrx_el1_s cn; */
22269 };
22270 typedef union bdk_ap_osdtrrx_el1 bdk_ap_osdtrrx_el1_t;
22271 
22272 #define BDK_AP_OSDTRRX_EL1 BDK_AP_OSDTRRX_EL1_FUNC()
22273 static inline uint64_t BDK_AP_OSDTRRX_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_OSDTRRX_EL1_FUNC(void)22274 static inline uint64_t BDK_AP_OSDTRRX_EL1_FUNC(void)
22275 {
22276     return 0x20000000200ll;
22277 }
22278 
22279 #define typedef_BDK_AP_OSDTRRX_EL1 bdk_ap_osdtrrx_el1_t
22280 #define bustype_BDK_AP_OSDTRRX_EL1 BDK_CSR_TYPE_SYSREG
22281 #define basename_BDK_AP_OSDTRRX_EL1 "AP_OSDTRRX_EL1"
22282 #define busnum_BDK_AP_OSDTRRX_EL1 0
22283 #define arguments_BDK_AP_OSDTRRX_EL1 -1,-1,-1,-1
22284 
22285 /**
22286  * Register (SYSREG) ap_osdtrtx_el1
22287  *
22288  * AP OS Lock Data Transfer Transmit Register
22289  * Used for save/restore of AP_DBGDTRTX_EL0. It is a component of
22290  *     the Debug Communications Channel.
22291  */
22292 union bdk_ap_osdtrtx_el1
22293 {
22294     uint32_t u;
22295     struct bdk_ap_osdtrtx_el1_s
22296     {
22297 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22298         uint32_t data                  : 32; /**< [ 31:  0](R/W) Target to host data. One word of data for transfer from the
22299                                                                      debug target to the debug host.
22300                                                                  For the full behavior of the Debug Communications Channel,
22301                                                                      see. */
22302 #else /* Word 0 - Little Endian */
22303         uint32_t data                  : 32; /**< [ 31:  0](R/W) Target to host data. One word of data for transfer from the
22304                                                                      debug target to the debug host.
22305                                                                  For the full behavior of the Debug Communications Channel,
22306                                                                      see. */
22307 #endif /* Word 0 - End */
22308     } s;
22309     /* struct bdk_ap_osdtrtx_el1_s cn; */
22310 };
22311 typedef union bdk_ap_osdtrtx_el1 bdk_ap_osdtrtx_el1_t;
22312 
22313 #define BDK_AP_OSDTRTX_EL1 BDK_AP_OSDTRTX_EL1_FUNC()
22314 static inline uint64_t BDK_AP_OSDTRTX_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_OSDTRTX_EL1_FUNC(void)22315 static inline uint64_t BDK_AP_OSDTRTX_EL1_FUNC(void)
22316 {
22317     return 0x20000030200ll;
22318 }
22319 
22320 #define typedef_BDK_AP_OSDTRTX_EL1 bdk_ap_osdtrtx_el1_t
22321 #define bustype_BDK_AP_OSDTRTX_EL1 BDK_CSR_TYPE_SYSREG
22322 #define basename_BDK_AP_OSDTRTX_EL1 "AP_OSDTRTX_EL1"
22323 #define busnum_BDK_AP_OSDTRTX_EL1 0
22324 #define arguments_BDK_AP_OSDTRTX_EL1 -1,-1,-1,-1
22325 
22326 /**
22327  * Register (SYSREG) ap_oseccr_el1
22328  *
22329  * AP OS Lock Exception Catch Control Register
22330  * Provides a mechanism for an operating system to access the
22331  *     contents of EDECCR that are otherwise invisible to software,
22332  *     so it can save/restore the contents of EDECCR over powerdown
22333  *     on behalf of the external debugger.
22334  */
22335 union bdk_ap_oseccr_el1
22336 {
22337     uint32_t u;
22338     struct bdk_ap_oseccr_el1_s
22339     {
22340 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22341         uint32_t edeccr                : 32; /**< [ 31:  0](R/W) Used for save/restore to EDECCR over powerdown. */
22342 #else /* Word 0 - Little Endian */
22343         uint32_t edeccr                : 32; /**< [ 31:  0](R/W) Used for save/restore to EDECCR over powerdown. */
22344 #endif /* Word 0 - End */
22345     } s;
22346     /* struct bdk_ap_oseccr_el1_s cn; */
22347 };
22348 typedef union bdk_ap_oseccr_el1 bdk_ap_oseccr_el1_t;
22349 
22350 #define BDK_AP_OSECCR_EL1 BDK_AP_OSECCR_EL1_FUNC()
22351 static inline uint64_t BDK_AP_OSECCR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_OSECCR_EL1_FUNC(void)22352 static inline uint64_t BDK_AP_OSECCR_EL1_FUNC(void)
22353 {
22354     return 0x20000060200ll;
22355 }
22356 
22357 #define typedef_BDK_AP_OSECCR_EL1 bdk_ap_oseccr_el1_t
22358 #define bustype_BDK_AP_OSECCR_EL1 BDK_CSR_TYPE_SYSREG
22359 #define basename_BDK_AP_OSECCR_EL1 "AP_OSECCR_EL1"
22360 #define busnum_BDK_AP_OSECCR_EL1 0
22361 #define arguments_BDK_AP_OSECCR_EL1 -1,-1,-1,-1
22362 
22363 /**
22364  * Register (SYSREG) ap_oslar_el1
22365  *
22366  * AP OS Lock Access Register
22367  * Used to lock or unlock the OS lock.
22368  */
22369 union bdk_ap_oslar_el1
22370 {
22371     uint32_t u;
22372     struct bdk_ap_oslar_el1_s
22373     {
22374 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22375         uint32_t reserved_1_31         : 31;
22376         uint32_t oslk                  : 1;  /**< [  0:  0](RO) On writes to AP_OSLAR_EL1, bit[0] is copied to the OS lock.
22377                                                                  Use AP_OSLSR_EL1[OSLK] to check the current status of the lock. */
22378 #else /* Word 0 - Little Endian */
22379         uint32_t oslk                  : 1;  /**< [  0:  0](RO) On writes to AP_OSLAR_EL1, bit[0] is copied to the OS lock.
22380                                                                  Use AP_OSLSR_EL1[OSLK] to check the current status of the lock. */
22381         uint32_t reserved_1_31         : 31;
22382 #endif /* Word 0 - End */
22383     } s;
22384     /* struct bdk_ap_oslar_el1_s cn8; */
22385     struct bdk_ap_oslar_el1_cn9
22386     {
22387 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22388         uint32_t reserved_1_31         : 31;
22389         uint32_t oslk                  : 1;  /**< [  0:  0](WO) On writes to AP_OSLAR_EL1, bit[0] is copied to the OS lock.
22390                                                                  Use AP_OSLSR_EL1[OSLK] to check the current status of the lock. */
22391 #else /* Word 0 - Little Endian */
22392         uint32_t oslk                  : 1;  /**< [  0:  0](WO) On writes to AP_OSLAR_EL1, bit[0] is copied to the OS lock.
22393                                                                  Use AP_OSLSR_EL1[OSLK] to check the current status of the lock. */
22394         uint32_t reserved_1_31         : 31;
22395 #endif /* Word 0 - End */
22396     } cn9;
22397 };
22398 typedef union bdk_ap_oslar_el1 bdk_ap_oslar_el1_t;
22399 
22400 #define BDK_AP_OSLAR_EL1 BDK_AP_OSLAR_EL1_FUNC()
22401 static inline uint64_t BDK_AP_OSLAR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_OSLAR_EL1_FUNC(void)22402 static inline uint64_t BDK_AP_OSLAR_EL1_FUNC(void)
22403 {
22404     return 0x20001000400ll;
22405 }
22406 
22407 #define typedef_BDK_AP_OSLAR_EL1 bdk_ap_oslar_el1_t
22408 #define bustype_BDK_AP_OSLAR_EL1 BDK_CSR_TYPE_SYSREG
22409 #define basename_BDK_AP_OSLAR_EL1 "AP_OSLAR_EL1"
22410 #define busnum_BDK_AP_OSLAR_EL1 0
22411 #define arguments_BDK_AP_OSLAR_EL1 -1,-1,-1,-1
22412 
22413 /**
22414  * Register (SYSREG) ap_oslsr_el1
22415  *
22416  * AP OS Lock Status Register
22417  * Provides the status of the OS lock.
22418  */
22419 union bdk_ap_oslsr_el1
22420 {
22421     uint32_t u;
22422     struct bdk_ap_oslsr_el1_s
22423     {
22424 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22425         uint32_t reserved_4_31         : 28;
22426         uint32_t oslm_high             : 1;  /**< [  3:  3](RO) See below for description of the OSLM field. */
22427         uint32_t ntt                   : 1;  /**< [  2:  2](RO) Not 32-bit access. This bit is always 0. It indicates that a
22428                                                                      32-bit access is needed to write the key to the OS lock access
22429                                                                      register. */
22430         uint32_t oslk                  : 1;  /**< [  1:  1](RO) OS Lock Status.
22431                                                                  The OS Lock is locked and unlocked by writing to the OS Lock
22432                                                                      Access Register.
22433                                                                  0 = OS lock unlocked.
22434                                                                  1 = OS lock locked. */
22435         uint32_t oslm_low              : 1;  /**< [  0:  0](RO) OS lock model implemented. Identifies the form of OS save and
22436                                                                      restore mechanism implemented. In ARMv8 these bits are as
22437                                                                      follows:
22438                                                                  All other values are reserved.
22439                                                                  OSLM0x2 = OS lock implemented. DBGOSSRR not implemented. */
22440 #else /* Word 0 - Little Endian */
22441         uint32_t oslm_low              : 1;  /**< [  0:  0](RO) OS lock model implemented. Identifies the form of OS save and
22442                                                                      restore mechanism implemented. In ARMv8 these bits are as
22443                                                                      follows:
22444                                                                  All other values are reserved.
22445                                                                  OSLM0x2 = OS lock implemented. DBGOSSRR not implemented. */
22446         uint32_t oslk                  : 1;  /**< [  1:  1](RO) OS Lock Status.
22447                                                                  The OS Lock is locked and unlocked by writing to the OS Lock
22448                                                                      Access Register.
22449                                                                  0 = OS lock unlocked.
22450                                                                  1 = OS lock locked. */
22451         uint32_t ntt                   : 1;  /**< [  2:  2](RO) Not 32-bit access. This bit is always 0. It indicates that a
22452                                                                      32-bit access is needed to write the key to the OS lock access
22453                                                                      register. */
22454         uint32_t oslm_high             : 1;  /**< [  3:  3](RO) See below for description of the OSLM field. */
22455         uint32_t reserved_4_31         : 28;
22456 #endif /* Word 0 - End */
22457     } s;
22458     /* struct bdk_ap_oslsr_el1_s cn; */
22459 };
22460 typedef union bdk_ap_oslsr_el1 bdk_ap_oslsr_el1_t;
22461 
22462 #define BDK_AP_OSLSR_EL1 BDK_AP_OSLSR_EL1_FUNC()
22463 static inline uint64_t BDK_AP_OSLSR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_OSLSR_EL1_FUNC(void)22464 static inline uint64_t BDK_AP_OSLSR_EL1_FUNC(void)
22465 {
22466     return 0x20001010400ll;
22467 }
22468 
22469 #define typedef_BDK_AP_OSLSR_EL1 bdk_ap_oslsr_el1_t
22470 #define bustype_BDK_AP_OSLSR_EL1 BDK_CSR_TYPE_SYSREG
22471 #define basename_BDK_AP_OSLSR_EL1 "AP_OSLSR_EL1"
22472 #define busnum_BDK_AP_OSLSR_EL1 0
22473 #define arguments_BDK_AP_OSLSR_EL1 -1,-1,-1,-1
22474 
22475 /**
22476  * Register (SYSREG) ap_pan
22477  *
22478  * AP Privileged Access Never Register
22479  * v8.1: Privileged Access Never bit.
22480  *
22481  * When 0, this bit has no effect on the translation system compared with
22482  * the situation in ARMv8.
22483  *
22484  * When 1, this bit disables data read or data write access from EL1 (or
22485  * EL2 when AP_HCR_EL2[E2H]==1) to a virtual address where access to the
22486  * virtual address at EL0 is permitted at stage 1 by the combination of
22487  * the AP[1] bit and the APTable[0] bits(if appropriate). That is, when
22488  * AP[1]==1 && APTable[0]==0, for all APTable bits associated with that
22489  * virtual address.
22490  *
22491  * The AP_PAN bit has no effect on instruction accesses.
22492  *
22493  * If access is disabled, then the access will give rise to a stage 1
22494  * permission fault, taken in the same way as all other stage 1
22495  * permission faults.
22496  *
22497  * PSTATE[AP_PAN] is copied to SPSR[AP_PAN] on an exception taken from AArch64
22498  * SPSR[AP_PAN] is copied to PSTATE[AP_PAN] on an exception return to AArch64
22499  */
22500 union bdk_ap_pan
22501 {
22502     uint64_t u;
22503     struct bdk_ap_pan_s
22504     {
22505 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22506         uint64_t reserved_23_63        : 41;
22507         uint64_t pan                   : 1;  /**< [ 22: 22](R/W) Privileged Access Never bit. */
22508         uint64_t reserved_0_21         : 22;
22509 #else /* Word 0 - Little Endian */
22510         uint64_t reserved_0_21         : 22;
22511         uint64_t pan                   : 1;  /**< [ 22: 22](R/W) Privileged Access Never bit. */
22512         uint64_t reserved_23_63        : 41;
22513 #endif /* Word 0 - End */
22514     } s;
22515     /* struct bdk_ap_pan_s cn; */
22516 };
22517 typedef union bdk_ap_pan bdk_ap_pan_t;
22518 
22519 #define BDK_AP_PAN BDK_AP_PAN_FUNC()
22520 static inline uint64_t BDK_AP_PAN_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PAN_FUNC(void)22521 static inline uint64_t BDK_AP_PAN_FUNC(void)
22522 {
22523     return 0x30004020300ll;
22524 }
22525 
22526 #define typedef_BDK_AP_PAN bdk_ap_pan_t
22527 #define bustype_BDK_AP_PAN BDK_CSR_TYPE_SYSREG
22528 #define basename_BDK_AP_PAN "AP_PAN"
22529 #define busnum_BDK_AP_PAN 0
22530 #define arguments_BDK_AP_PAN -1,-1,-1,-1
22531 
22532 /**
22533  * Register (SYSREG) ap_par_el1
22534  *
22535  * AP Physical Address Register
22536  * Receives the PA from any address translation operation.
22537  */
22538 union bdk_ap_par_el1
22539 {
22540     uint64_t u;
22541     struct bdk_ap_par_el1_s
22542     {
22543 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22544         uint64_t mair                  : 8;  /**< [ 63: 56](R/W) On success (f=0): Memory Attributes, following the encodings for the MAIR.
22545                                                                  On failure (f=1): Zero. */
22546         uint64_t reserved_52_55        : 4;
22547         uint64_t pa                    : 40; /**< [ 51: 12](R/W) Physical Address. The physical address corresponding to the
22548                                                                      supplied virtual address. This field returns address
22549                                                                      bits \<47:12\>. */
22550         uint64_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
22551         uint64_t reserved_10           : 1;
22552         uint64_t nsec                  : 1;  /**< [  9:  9](R/W) Nonsecure. The NS attribute for a translation table entry
22553                                                                      read from Secure state.
22554                                                                  This bit is UNKNOWN for a translation table entry read from
22555                                                                      nonsecure state. */
22556         uint64_t sha                   : 2;  /**< [  8:  7](R/W) Shareability attribute, from the translation table entry for
22557                                                                      the returned PA.
22558                                                                  0x0 = Non-shareable.
22559                                                                  0x2 = Outer Shareable.
22560                                                                  0x3 = Inner Shareable. */
22561         uint64_t fs                    : 6;  /**< [  6:  1](R/W) On success (f=0): Zero.
22562                                                                  On failure (f=1): Fault Status code shown in the Data Abort. */
22563         uint64_t f                     : 1;  /**< [  0:  0](R/W) Indicates whether the conversion completed successfully.
22564                                                                  0 = VA to PA conversion completed successfully. */
22565 #else /* Word 0 - Little Endian */
22566         uint64_t f                     : 1;  /**< [  0:  0](R/W) Indicates whether the conversion completed successfully.
22567                                                                  0 = VA to PA conversion completed successfully. */
22568         uint64_t fs                    : 6;  /**< [  6:  1](R/W) On success (f=0): Zero.
22569                                                                  On failure (f=1): Fault Status code shown in the Data Abort. */
22570         uint64_t sha                   : 2;  /**< [  8:  7](R/W) Shareability attribute, from the translation table entry for
22571                                                                      the returned PA.
22572                                                                  0x0 = Non-shareable.
22573                                                                  0x2 = Outer Shareable.
22574                                                                  0x3 = Inner Shareable. */
22575         uint64_t nsec                  : 1;  /**< [  9:  9](R/W) Nonsecure. The NS attribute for a translation table entry
22576                                                                      read from Secure state.
22577                                                                  This bit is UNKNOWN for a translation table entry read from
22578                                                                      nonsecure state. */
22579         uint64_t reserved_10           : 1;
22580         uint64_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
22581         uint64_t pa                    : 40; /**< [ 51: 12](R/W) Physical Address. The physical address corresponding to the
22582                                                                      supplied virtual address. This field returns address
22583                                                                      bits \<47:12\>. */
22584         uint64_t reserved_52_55        : 4;
22585         uint64_t mair                  : 8;  /**< [ 63: 56](R/W) On success (f=0): Memory Attributes, following the encodings for the MAIR.
22586                                                                  On failure (f=1): Zero. */
22587 #endif /* Word 0 - End */
22588     } s;
22589     struct bdk_ap_par_el1_cn8
22590     {
22591 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22592         uint64_t mair                  : 8;  /**< [ 63: 56](R/W) On success (f=0): Memory Attributes, following the encodings for the MAIR.
22593                                                                  On failure (f=1): Zero. */
22594         uint64_t reserved_48_55        : 8;
22595         uint64_t pa                    : 36; /**< [ 47: 12](R/W) Physical Address. The physical address corresponding to the
22596                                                                      supplied virtual address. This field returns address
22597                                                                      bits \<47:12\>. */
22598         uint64_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
22599         uint64_t reserved_10           : 1;
22600         uint64_t nsec                  : 1;  /**< [  9:  9](R/W) Nonsecure. The NS attribute for a translation table entry
22601                                                                      read from Secure state.
22602                                                                  This bit is UNKNOWN for a translation table entry read from
22603                                                                      nonsecure state. */
22604         uint64_t sha                   : 2;  /**< [  8:  7](R/W) Shareability attribute, from the translation table entry for
22605                                                                      the returned PA.
22606                                                                  0x0 = Non-shareable.
22607                                                                  0x2 = Outer Shareable.
22608                                                                  0x3 = Inner Shareable. */
22609         uint64_t fs                    : 6;  /**< [  6:  1](R/W) On success (f=0): Zero.
22610                                                                  On failure (f=1): Fault Status code shown in the Data Abort. */
22611         uint64_t f                     : 1;  /**< [  0:  0](R/W) Indicates whether the conversion completed successfully.
22612                                                                  0 = VA to PA conversion completed successfully. */
22613 #else /* Word 0 - Little Endian */
22614         uint64_t f                     : 1;  /**< [  0:  0](R/W) Indicates whether the conversion completed successfully.
22615                                                                  0 = VA to PA conversion completed successfully. */
22616         uint64_t fs                    : 6;  /**< [  6:  1](R/W) On success (f=0): Zero.
22617                                                                  On failure (f=1): Fault Status code shown in the Data Abort. */
22618         uint64_t sha                   : 2;  /**< [  8:  7](R/W) Shareability attribute, from the translation table entry for
22619                                                                      the returned PA.
22620                                                                  0x0 = Non-shareable.
22621                                                                  0x2 = Outer Shareable.
22622                                                                  0x3 = Inner Shareable. */
22623         uint64_t nsec                  : 1;  /**< [  9:  9](R/W) Nonsecure. The NS attribute for a translation table entry
22624                                                                      read from Secure state.
22625                                                                  This bit is UNKNOWN for a translation table entry read from
22626                                                                      nonsecure state. */
22627         uint64_t reserved_10           : 1;
22628         uint64_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
22629         uint64_t pa                    : 36; /**< [ 47: 12](R/W) Physical Address. The physical address corresponding to the
22630                                                                      supplied virtual address. This field returns address
22631                                                                      bits \<47:12\>. */
22632         uint64_t reserved_48_55        : 8;
22633         uint64_t mair                  : 8;  /**< [ 63: 56](R/W) On success (f=0): Memory Attributes, following the encodings for the MAIR.
22634                                                                  On failure (f=1): Zero. */
22635 #endif /* Word 0 - End */
22636     } cn8;
22637     struct bdk_ap_par_el1_cn9
22638     {
22639 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22640         uint64_t mair                  : 8;  /**< [ 63: 56](R/W) On success (f=0): Memory Attributes, following the encodings for the MAIR.
22641                                                                  On failure (f=1): Zero. */
22642         uint64_t reserved_52_55        : 4;
22643         uint64_t pa                    : 40; /**< [ 51: 12](R/W) Physical address. The physical address corresponding to the
22644                                                                  supplied virtual address. This field returns address bits \<51:12\>. */
22645         uint64_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
22646         uint64_t reserved_10           : 1;
22647         uint64_t nsec                  : 1;  /**< [  9:  9](R/W) Nonsecure. The NS attribute for a translation table entry
22648                                                                      read from Secure state.
22649                                                                  This bit is UNKNOWN for a translation table entry read from
22650                                                                      nonsecure state. */
22651         uint64_t sha                   : 2;  /**< [  8:  7](R/W) Shareability attribute, from the translation table entry for
22652                                                                      the returned PA.
22653                                                                  0x0 = Non-shareable.
22654                                                                  0x2 = Outer Shareable.
22655                                                                  0x3 = Inner Shareable. */
22656         uint64_t fs                    : 6;  /**< [  6:  1](R/W) On success (f=0): Zero.
22657                                                                  On failure (f=1): Fault Status code shown in the Data Abort. */
22658         uint64_t f                     : 1;  /**< [  0:  0](R/W) Indicates whether the conversion completed successfully.
22659                                                                  0 = VA to PA conversion completed successfully. */
22660 #else /* Word 0 - Little Endian */
22661         uint64_t f                     : 1;  /**< [  0:  0](R/W) Indicates whether the conversion completed successfully.
22662                                                                  0 = VA to PA conversion completed successfully. */
22663         uint64_t fs                    : 6;  /**< [  6:  1](R/W) On success (f=0): Zero.
22664                                                                  On failure (f=1): Fault Status code shown in the Data Abort. */
22665         uint64_t sha                   : 2;  /**< [  8:  7](R/W) Shareability attribute, from the translation table entry for
22666                                                                      the returned PA.
22667                                                                  0x0 = Non-shareable.
22668                                                                  0x2 = Outer Shareable.
22669                                                                  0x3 = Inner Shareable. */
22670         uint64_t nsec                  : 1;  /**< [  9:  9](R/W) Nonsecure. The NS attribute for a translation table entry
22671                                                                      read from Secure state.
22672                                                                  This bit is UNKNOWN for a translation table entry read from
22673                                                                      nonsecure state. */
22674         uint64_t reserved_10           : 1;
22675         uint64_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
22676         uint64_t pa                    : 40; /**< [ 51: 12](R/W) Physical address. The physical address corresponding to the
22677                                                                  supplied virtual address. This field returns address bits \<51:12\>. */
22678         uint64_t reserved_52_55        : 4;
22679         uint64_t mair                  : 8;  /**< [ 63: 56](R/W) On success (f=0): Memory Attributes, following the encodings for the MAIR.
22680                                                                  On failure (f=1): Zero. */
22681 #endif /* Word 0 - End */
22682     } cn9;
22683 };
22684 typedef union bdk_ap_par_el1 bdk_ap_par_el1_t;
22685 
22686 #define BDK_AP_PAR_EL1 BDK_AP_PAR_EL1_FUNC()
22687 static inline uint64_t BDK_AP_PAR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PAR_EL1_FUNC(void)22688 static inline uint64_t BDK_AP_PAR_EL1_FUNC(void)
22689 {
22690     return 0x30007040000ll;
22691 }
22692 
22693 #define typedef_BDK_AP_PAR_EL1 bdk_ap_par_el1_t
22694 #define bustype_BDK_AP_PAR_EL1 BDK_CSR_TYPE_SYSREG
22695 #define basename_BDK_AP_PAR_EL1 "AP_PAR_EL1"
22696 #define busnum_BDK_AP_PAR_EL1 0
22697 #define arguments_BDK_AP_PAR_EL1 -1,-1,-1,-1
22698 
22699 /**
22700  * Register (SYSREG) ap_pmbidr_el1
22701  *
22702  * AP Profiling Buffer ID Register
22703  * Provides information to software as to whether the buffer can be programmed at the current
22704  * Exception level.
22705  */
22706 union bdk_ap_pmbidr_el1
22707 {
22708     uint64_t u;
22709     struct bdk_ap_pmbidr_el1_s
22710     {
22711 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22712         uint64_t reserved_6_63         : 58;
22713         uint64_t f                     : 1;  /**< [  5:  5](RO) Flag Updates. Defines whether the address translation performed by the profiling buffer
22714                                                                  manages the access flag and dirty bit.
22715                                                                    0 = Accesses to pages not marked with Access Flag and not with dirty bit set will
22716                                                                  generate an Unsupported Access fault if hardware management of those flags is enabled.
22717                                                                    1 = Profiling Buffer address translation manages the access flag and dirty bit in the
22718                                                                  same way as the MMU on this PE. */
22719         uint64_t p                     : 1;  /**< [  4:  4](RO) Prohibited. The profiling buffer is owned by the current or a lower exception level in the
22720                                                                  current security state.
22721                                                                    0 = Profiling buffer is owned by the current or a lower exception level in the current
22722                                                                  security state. This does not mean an access will not be trapped to a higher exception
22723                                                                  level.
22724                                                                    1 = Profiling buffer is owned by a higher exception level or the other security state. */
22725         uint64_t align                 : 4;  /**< [  3:  0](RO) Defines the minimum alignment constraint for PMBPTR_EL1. If this field is non-zero, then
22726                                                                  the PE must pad every record up to a multiple of this size.
22727                                                                    0x0 = Byte.
22728                                                                    0x1 = Halfword. PMBPTR_EL1[0] is RES0.
22729                                                                    0x2 = Word. PMBPTR_EL1[1:0] is RES0.
22730                                                                    0x3 = Doubleword. PMBPTR_EL1[2:0] is RES0.
22731                                                                    ... ...
22732                                                                    0xB = 2KB. PMBPTR_EL1[10:0] is RES0.
22733 
22734                                                                    All other values are reserved. Reserved values might be defined in a future version of
22735                                                                  the architecture. */
22736 #else /* Word 0 - Little Endian */
22737         uint64_t align                 : 4;  /**< [  3:  0](RO) Defines the minimum alignment constraint for PMBPTR_EL1. If this field is non-zero, then
22738                                                                  the PE must pad every record up to a multiple of this size.
22739                                                                    0x0 = Byte.
22740                                                                    0x1 = Halfword. PMBPTR_EL1[0] is RES0.
22741                                                                    0x2 = Word. PMBPTR_EL1[1:0] is RES0.
22742                                                                    0x3 = Doubleword. PMBPTR_EL1[2:0] is RES0.
22743                                                                    ... ...
22744                                                                    0xB = 2KB. PMBPTR_EL1[10:0] is RES0.
22745 
22746                                                                    All other values are reserved. Reserved values might be defined in a future version of
22747                                                                  the architecture. */
22748         uint64_t p                     : 1;  /**< [  4:  4](RO) Prohibited. The profiling buffer is owned by the current or a lower exception level in the
22749                                                                  current security state.
22750                                                                    0 = Profiling buffer is owned by the current or a lower exception level in the current
22751                                                                  security state. This does not mean an access will not be trapped to a higher exception
22752                                                                  level.
22753                                                                    1 = Profiling buffer is owned by a higher exception level or the other security state. */
22754         uint64_t f                     : 1;  /**< [  5:  5](RO) Flag Updates. Defines whether the address translation performed by the profiling buffer
22755                                                                  manages the access flag and dirty bit.
22756                                                                    0 = Accesses to pages not marked with Access Flag and not with dirty bit set will
22757                                                                  generate an Unsupported Access fault if hardware management of those flags is enabled.
22758                                                                    1 = Profiling Buffer address translation manages the access flag and dirty bit in the
22759                                                                  same way as the MMU on this PE. */
22760         uint64_t reserved_6_63         : 58;
22761 #endif /* Word 0 - End */
22762     } s;
22763     /* struct bdk_ap_pmbidr_el1_s cn; */
22764 };
22765 typedef union bdk_ap_pmbidr_el1 bdk_ap_pmbidr_el1_t;
22766 
22767 #define BDK_AP_PMBIDR_EL1 BDK_AP_PMBIDR_EL1_FUNC()
22768 static inline uint64_t BDK_AP_PMBIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMBIDR_EL1_FUNC(void)22769 static inline uint64_t BDK_AP_PMBIDR_EL1_FUNC(void)
22770 {
22771     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
22772         return 0x300090a0700ll;
22773     __bdk_csr_fatal("AP_PMBIDR_EL1", 0, 0, 0, 0, 0);
22774 }
22775 
22776 #define typedef_BDK_AP_PMBIDR_EL1 bdk_ap_pmbidr_el1_t
22777 #define bustype_BDK_AP_PMBIDR_EL1 BDK_CSR_TYPE_SYSREG
22778 #define basename_BDK_AP_PMBIDR_EL1 "AP_PMBIDR_EL1"
22779 #define busnum_BDK_AP_PMBIDR_EL1 0
22780 #define arguments_BDK_AP_PMBIDR_EL1 -1,-1,-1,-1
22781 
22782 /**
22783  * Register (SYSREG) ap_pmblimitr_el1
22784  *
22785  * AP Profiling Buffer Limit Address Register
22786  * Defines the upper limit for the profiling buffer, and enables the profiling buffer.
22787  */
22788 union bdk_ap_pmblimitr_el1
22789 {
22790     uint64_t u;
22791     struct bdk_ap_pmblimitr_el1_s
22792     {
22793 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22794         uint64_t limit                 : 52; /**< [ 63: 12](R/W) Limit address, plus one. Read/write. Defines the limit of the buffer. If the smallest
22795                                                                  implemented translation granule is not 4KB, then bits [N-1:12] are RES0, where N is the
22796                                                                  IMPLEMENTATION DEFINED value, Log2(smallest implemented translation granule). */
22797         uint64_t reserved_3_11         : 9;
22798         uint64_t fm                    : 2;  /**< [  2:  1](R/W) Fill mode.
22799                                                                    0x0 = Stop collection and raise maintenance interrupt on buffer fill.
22800 
22801                                                                  All other values are reserved. If this field is programmed with a reserved value, the PE
22802                                                                  behaves as if this field has a defined value, other than for a direct read of the
22803                                                                  register. Software must not rely on the behavior of reserved values, as they might change
22804                                                                  in a future version of the architecture. */
22805         uint64_t ee                    : 1;  /**< [  0:  0](R/W) Profiling buffer enable.
22806                                                                    0 = All output is discarded.
22807                                                                    1 = Enabled.
22808 
22809                                                                  This bit resets to zero. */
22810 #else /* Word 0 - Little Endian */
22811         uint64_t ee                    : 1;  /**< [  0:  0](R/W) Profiling buffer enable.
22812                                                                    0 = All output is discarded.
22813                                                                    1 = Enabled.
22814 
22815                                                                  This bit resets to zero. */
22816         uint64_t fm                    : 2;  /**< [  2:  1](R/W) Fill mode.
22817                                                                    0x0 = Stop collection and raise maintenance interrupt on buffer fill.
22818 
22819                                                                  All other values are reserved. If this field is programmed with a reserved value, the PE
22820                                                                  behaves as if this field has a defined value, other than for a direct read of the
22821                                                                  register. Software must not rely on the behavior of reserved values, as they might change
22822                                                                  in a future version of the architecture. */
22823         uint64_t reserved_3_11         : 9;
22824         uint64_t limit                 : 52; /**< [ 63: 12](R/W) Limit address, plus one. Read/write. Defines the limit of the buffer. If the smallest
22825                                                                  implemented translation granule is not 4KB, then bits [N-1:12] are RES0, where N is the
22826                                                                  IMPLEMENTATION DEFINED value, Log2(smallest implemented translation granule). */
22827 #endif /* Word 0 - End */
22828     } s;
22829     /* struct bdk_ap_pmblimitr_el1_s cn; */
22830 };
22831 typedef union bdk_ap_pmblimitr_el1 bdk_ap_pmblimitr_el1_t;
22832 
22833 #define BDK_AP_PMBLIMITR_EL1 BDK_AP_PMBLIMITR_EL1_FUNC()
22834 static inline uint64_t BDK_AP_PMBLIMITR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMBLIMITR_EL1_FUNC(void)22835 static inline uint64_t BDK_AP_PMBLIMITR_EL1_FUNC(void)
22836 {
22837     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
22838         return 0x300090a0000ll;
22839     __bdk_csr_fatal("AP_PMBLIMITR_EL1", 0, 0, 0, 0, 0);
22840 }
22841 
22842 #define typedef_BDK_AP_PMBLIMITR_EL1 bdk_ap_pmblimitr_el1_t
22843 #define bustype_BDK_AP_PMBLIMITR_EL1 BDK_CSR_TYPE_SYSREG
22844 #define basename_BDK_AP_PMBLIMITR_EL1 "AP_PMBLIMITR_EL1"
22845 #define busnum_BDK_AP_PMBLIMITR_EL1 0
22846 #define arguments_BDK_AP_PMBLIMITR_EL1 -1,-1,-1,-1
22847 
22848 /**
22849  * Register (SYSREG) ap_pmbptr_el1
22850  *
22851  * AP Profiling Buffer Write Pointer Register
22852  * Defines the current write pointer for the profiling buffer.
22853  */
22854 union bdk_ap_pmbptr_el1
22855 {
22856     uint64_t u;
22857     struct bdk_ap_pmbptr_el1_s
22858     {
22859 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22860         uint64_t ptr                   : 64; /**< [ 63:  0](R/W) Current write address. Defines the virtual address of the next entry to be written to the
22861                                                                  buffer.
22862                                                                  Software must treat bits [M:0] of this register as RES0, where M is defined by
22863                                                                  PMBIDR_EL1.Align. If
22864                                                                  synchronous reporting of external aborts is not supported, then hardware also treats these
22865                                                                  bits as
22866                                                                  RES0. Otherwise, bits [M:0] might contain part of a fault address on a synchronous
22867                                                                  external abort.
22868                                                                  On a management interrupt, PMBPTR_EL1 is frozen. */
22869 #else /* Word 0 - Little Endian */
22870         uint64_t ptr                   : 64; /**< [ 63:  0](R/W) Current write address. Defines the virtual address of the next entry to be written to the
22871                                                                  buffer.
22872                                                                  Software must treat bits [M:0] of this register as RES0, where M is defined by
22873                                                                  PMBIDR_EL1.Align. If
22874                                                                  synchronous reporting of external aborts is not supported, then hardware also treats these
22875                                                                  bits as
22876                                                                  RES0. Otherwise, bits [M:0] might contain part of a fault address on a synchronous
22877                                                                  external abort.
22878                                                                  On a management interrupt, PMBPTR_EL1 is frozen. */
22879 #endif /* Word 0 - End */
22880     } s;
22881     /* struct bdk_ap_pmbptr_el1_s cn; */
22882 };
22883 typedef union bdk_ap_pmbptr_el1 bdk_ap_pmbptr_el1_t;
22884 
22885 #define BDK_AP_PMBPTR_EL1 BDK_AP_PMBPTR_EL1_FUNC()
22886 static inline uint64_t BDK_AP_PMBPTR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMBPTR_EL1_FUNC(void)22887 static inline uint64_t BDK_AP_PMBPTR_EL1_FUNC(void)
22888 {
22889     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
22890         return 0x300090a0100ll;
22891     __bdk_csr_fatal("AP_PMBPTR_EL1", 0, 0, 0, 0, 0);
22892 }
22893 
22894 #define typedef_BDK_AP_PMBPTR_EL1 bdk_ap_pmbptr_el1_t
22895 #define bustype_BDK_AP_PMBPTR_EL1 BDK_CSR_TYPE_SYSREG
22896 #define basename_BDK_AP_PMBPTR_EL1 "AP_PMBPTR_EL1"
22897 #define busnum_BDK_AP_PMBPTR_EL1 0
22898 #define arguments_BDK_AP_PMBPTR_EL1 -1,-1,-1,-1
22899 
22900 /**
22901  * Register (SYSREG) ap_pmbsr_el1
22902  *
22903  * AP Profiling Buffer Status/syndrome Register
22904  * Provides syndrome information to software when the buffer is disabled because the management
22905  * interrupt has been raised.
22906  */
22907 union bdk_ap_pmbsr_el1
22908 {
22909     uint64_t u;
22910     struct bdk_ap_pmbsr_el1_s
22911     {
22912 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
22913         uint64_t reserved_32_63        : 32;
22914         uint64_t ec                    : 6;  /**< [ 31: 26](R/W) Exception class.
22915                                                                    000000 = Buffer management event.
22916                                                                    100100 = Data abort on write to buffer.
22917                                                                    100101 = Stage 2 data abort on write to buffer.
22918 
22919                                                                  All other values are reserved. Reserved values might be defined in a future version of the
22920                                                                  architecture. */
22921         uint64_t reserved_20_25        : 6;
22922         uint64_t dl                    : 1;  /**< [ 19: 19](R/W) Partial record lost.
22923                                                                    0 = PMBPTR_EL1 points to the first byte after the last complete record written to the
22924                                                                  buffer.
22925                                                                    1 = Part of a record was lost due to a service event or external abort. PMBPTR_EL1 might
22926                                                                  not point to
22927                                                                    the first byte after the last complete record written to the buffer, and so restarting
22928                                                                  collection might
22929                                                                    result in a data record stream that software cannot parse. All records prior to the last
22930                                                                  record have
22931                                                                    been written to the buffer. */
22932         uint64_t ea                    : 1;  /**< [ 18: 18](R/W) External abort.
22933                                                                    0 = An external abort has not been asserted.
22934                                                                    1 = An external abort has been asserted. */
22935         uint64_t s                     : 1;  /**< [ 17: 17](R/W) Service.
22936                                                                    0 = PMBIRQ has not been asserted.
22937                                                                    1 = PMBIRQ has been asserted. All profiling data has either been written to the buffer
22938                                                                  or discarded. */
22939         uint64_t coll                  : 1;  /**< [ 16: 16](R/W) Collision detected.
22940                                                                    0 = No collision events detected.
22941                                                                    1 = At least one collision event was recorded. */
22942         uint64_t reserved_6_15         : 10;
22943         uint64_t bsc_fsc               : 6;  /**< [  5:  0](R/W) BSC when EC == 0b000000.
22944 
22945                                                                  BSC, bits [5:0], when EC == 0b000000.
22946                                                                  Buffer status code.
22947                                                                    0x0 = Buffer not filled.
22948                                                                    0x1 = Buffer filled.
22949 
22950                                                                  FSC when EC == 0b10010x.
22951                                                                  Fault status code.
22952                                                                    0000xx = Address Size fault, bits [1:0] encode the level.
22953                                                                    0001xx = Translation fault, bits [1:0] encode the level.
22954                                                                    0010xx = Access Flag fault, bits [1:0] encode the level.
22955                                                                    0011xx = Permission fault, bits [1:0] encode the level.
22956                                                                    010000 = Synchronous external abort on write.
22957                                                                    0101xx = Synchronous external abort on page table walk, bits [1:0] encode the level.
22958                                                                    010001 = Asynchronous external abort on write.
22959                                                                    100001 = Alignment fault.
22960                                                                    110000 = TLB Conflict fault.
22961                                                                    110101 = Unsupported Access fault.
22962 
22963                                                                  All other values are reserved. Reserved values might be defined in a future version of
22964                                                                  the architecture. */
22965 #else /* Word 0 - Little Endian */
22966         uint64_t bsc_fsc               : 6;  /**< [  5:  0](R/W) BSC when EC == 0b000000.
22967 
22968                                                                  BSC, bits [5:0], when EC == 0b000000.
22969                                                                  Buffer status code.
22970                                                                    0x0 = Buffer not filled.
22971                                                                    0x1 = Buffer filled.
22972 
22973                                                                  FSC when EC == 0b10010x.
22974                                                                  Fault status code.
22975                                                                    0000xx = Address Size fault, bits [1:0] encode the level.
22976                                                                    0001xx = Translation fault, bits [1:0] encode the level.
22977                                                                    0010xx = Access Flag fault, bits [1:0] encode the level.
22978                                                                    0011xx = Permission fault, bits [1:0] encode the level.
22979                                                                    010000 = Synchronous external abort on write.
22980                                                                    0101xx = Synchronous external abort on page table walk, bits [1:0] encode the level.
22981                                                                    010001 = Asynchronous external abort on write.
22982                                                                    100001 = Alignment fault.
22983                                                                    110000 = TLB Conflict fault.
22984                                                                    110101 = Unsupported Access fault.
22985 
22986                                                                  All other values are reserved. Reserved values might be defined in a future version of
22987                                                                  the architecture. */
22988         uint64_t reserved_6_15         : 10;
22989         uint64_t coll                  : 1;  /**< [ 16: 16](R/W) Collision detected.
22990                                                                    0 = No collision events detected.
22991                                                                    1 = At least one collision event was recorded. */
22992         uint64_t s                     : 1;  /**< [ 17: 17](R/W) Service.
22993                                                                    0 = PMBIRQ has not been asserted.
22994                                                                    1 = PMBIRQ has been asserted. All profiling data has either been written to the buffer
22995                                                                  or discarded. */
22996         uint64_t ea                    : 1;  /**< [ 18: 18](R/W) External abort.
22997                                                                    0 = An external abort has not been asserted.
22998                                                                    1 = An external abort has been asserted. */
22999         uint64_t dl                    : 1;  /**< [ 19: 19](R/W) Partial record lost.
23000                                                                    0 = PMBPTR_EL1 points to the first byte after the last complete record written to the
23001                                                                  buffer.
23002                                                                    1 = Part of a record was lost due to a service event or external abort. PMBPTR_EL1 might
23003                                                                  not point to
23004                                                                    the first byte after the last complete record written to the buffer, and so restarting
23005                                                                  collection might
23006                                                                    result in a data record stream that software cannot parse. All records prior to the last
23007                                                                  record have
23008                                                                    been written to the buffer. */
23009         uint64_t reserved_20_25        : 6;
23010         uint64_t ec                    : 6;  /**< [ 31: 26](R/W) Exception class.
23011                                                                    000000 = Buffer management event.
23012                                                                    100100 = Data abort on write to buffer.
23013                                                                    100101 = Stage 2 data abort on write to buffer.
23014 
23015                                                                  All other values are reserved. Reserved values might be defined in a future version of the
23016                                                                  architecture. */
23017         uint64_t reserved_32_63        : 32;
23018 #endif /* Word 0 - End */
23019     } s;
23020     /* struct bdk_ap_pmbsr_el1_s cn; */
23021 };
23022 typedef union bdk_ap_pmbsr_el1 bdk_ap_pmbsr_el1_t;
23023 
23024 #define BDK_AP_PMBSR_EL1 BDK_AP_PMBSR_EL1_FUNC()
23025 static inline uint64_t BDK_AP_PMBSR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMBSR_EL1_FUNC(void)23026 static inline uint64_t BDK_AP_PMBSR_EL1_FUNC(void)
23027 {
23028     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
23029         return 0x300090a0300ll;
23030     __bdk_csr_fatal("AP_PMBSR_EL1", 0, 0, 0, 0, 0);
23031 }
23032 
23033 #define typedef_BDK_AP_PMBSR_EL1 bdk_ap_pmbsr_el1_t
23034 #define bustype_BDK_AP_PMBSR_EL1 BDK_CSR_TYPE_SYSREG
23035 #define basename_BDK_AP_PMBSR_EL1 "AP_PMBSR_EL1"
23036 #define busnum_BDK_AP_PMBSR_EL1 0
23037 #define arguments_BDK_AP_PMBSR_EL1 -1,-1,-1,-1
23038 
23039 /**
23040  * Register (SYSREG) ap_pmccfiltr_el0
23041  *
23042  * AP Performance Monitors Cycle Count Filter Register
23043  * Determines the modes in which the Cycle Counter, AP_PMCCNTR_EL0,
23044  *     increments.
23045  */
23046 union bdk_ap_pmccfiltr_el0
23047 {
23048     uint32_t u;
23049     struct bdk_ap_pmccfiltr_el0_s
23050     {
23051 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23052         uint32_t p                     : 1;  /**< [ 31: 31](R/W) EL1 modes filtering bit. Controls counting in EL1. If EL3 is
23053                                                                      implemented, then counting in nonsecure EL1 is further
23054                                                                      controlled by the NSK bit.
23055                                                                  0 = Count cycles in EL1.
23056                                                                  1 = Do not count cycles in EL1. */
23057         uint32_t u                     : 1;  /**< [ 30: 30](R/W) EL0 filtering bit. Controls counting in EL0. If EL3 is
23058                                                                      implemented, then counting in nonsecure EL0 is further
23059                                                                      controlled by the NSU bit.
23060                                                                  0 = Count cycles in EL0.
23061                                                                  1 = Do not count cycles in EL0. */
23062         uint32_t nsk                   : 1;  /**< [ 29: 29](R/W) Nonsecure kernel modes filtering bit. Controls counting in
23063                                                                      nonsecure EL1. If EL3 is not implemented, this bit is RES0.
23064                                                                  If the value of this bit is equal to the value of P, cycles in
23065                                                                      nonsecure EL1 are counted.
23066                                                                  Otherwise, cycles in nonsecure EL1 are not counted. */
23067         uint32_t nsu                   : 1;  /**< [ 28: 28](R/W) Nonsecure user modes filtering bit. Controls counting in Non-
23068                                                                      secure EL0. If EL3 is not implemented, this bit is RES0.
23069                                                                  If the value of this bit is equal to the value of U, cycles in
23070                                                                      nonsecure EL0 are counted.
23071                                                                  Otherwise, cycles in nonsecure EL0 are not counted. */
23072         uint32_t nsh                   : 1;  /**< [ 27: 27](R/W) Nonsecure Hyp modes filtering bit. Controls counting in Non-
23073                                                                      secure EL2. If EL2 is not implemented, this bit is RES0.
23074                                                                  0 = Do not count cycles in EL2.
23075                                                                  1 = Count cycles in EL2. */
23076         uint32_t m                     : 1;  /**< [ 26: 26](R/W) Secure EL3 filtering bit. Most applications can ignore this
23077                                                                      bit and set the value to zero. If EL3 is not implemented, this
23078                                                                      bit is RES0.
23079 
23080                                                                  If the value of this bit is equal to the value of P, cycles in
23081                                                                      Secure EL3 are counted.
23082 
23083                                                                  Otherwise, cycles in Secure EL3 are not counted. */
23084         uint32_t reserved_0_25         : 26;
23085 #else /* Word 0 - Little Endian */
23086         uint32_t reserved_0_25         : 26;
23087         uint32_t m                     : 1;  /**< [ 26: 26](R/W) Secure EL3 filtering bit. Most applications can ignore this
23088                                                                      bit and set the value to zero. If EL3 is not implemented, this
23089                                                                      bit is RES0.
23090 
23091                                                                  If the value of this bit is equal to the value of P, cycles in
23092                                                                      Secure EL3 are counted.
23093 
23094                                                                  Otherwise, cycles in Secure EL3 are not counted. */
23095         uint32_t nsh                   : 1;  /**< [ 27: 27](R/W) Nonsecure Hyp modes filtering bit. Controls counting in Non-
23096                                                                      secure EL2. If EL2 is not implemented, this bit is RES0.
23097                                                                  0 = Do not count cycles in EL2.
23098                                                                  1 = Count cycles in EL2. */
23099         uint32_t nsu                   : 1;  /**< [ 28: 28](R/W) Nonsecure user modes filtering bit. Controls counting in Non-
23100                                                                      secure EL0. If EL3 is not implemented, this bit is RES0.
23101                                                                  If the value of this bit is equal to the value of U, cycles in
23102                                                                      nonsecure EL0 are counted.
23103                                                                  Otherwise, cycles in nonsecure EL0 are not counted. */
23104         uint32_t nsk                   : 1;  /**< [ 29: 29](R/W) Nonsecure kernel modes filtering bit. Controls counting in
23105                                                                      nonsecure EL1. If EL3 is not implemented, this bit is RES0.
23106                                                                  If the value of this bit is equal to the value of P, cycles in
23107                                                                      nonsecure EL1 are counted.
23108                                                                  Otherwise, cycles in nonsecure EL1 are not counted. */
23109         uint32_t u                     : 1;  /**< [ 30: 30](R/W) EL0 filtering bit. Controls counting in EL0. If EL3 is
23110                                                                      implemented, then counting in nonsecure EL0 is further
23111                                                                      controlled by the NSU bit.
23112                                                                  0 = Count cycles in EL0.
23113                                                                  1 = Do not count cycles in EL0. */
23114         uint32_t p                     : 1;  /**< [ 31: 31](R/W) EL1 modes filtering bit. Controls counting in EL1. If EL3 is
23115                                                                      implemented, then counting in nonsecure EL1 is further
23116                                                                      controlled by the NSK bit.
23117                                                                  0 = Count cycles in EL1.
23118                                                                  1 = Do not count cycles in EL1. */
23119 #endif /* Word 0 - End */
23120     } s;
23121     /* struct bdk_ap_pmccfiltr_el0_s cn; */
23122 };
23123 typedef union bdk_ap_pmccfiltr_el0 bdk_ap_pmccfiltr_el0_t;
23124 
23125 #define BDK_AP_PMCCFILTR_EL0 BDK_AP_PMCCFILTR_EL0_FUNC()
23126 static inline uint64_t BDK_AP_PMCCFILTR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMCCFILTR_EL0_FUNC(void)23127 static inline uint64_t BDK_AP_PMCCFILTR_EL0_FUNC(void)
23128 {
23129     return 0x3030e0f0700ll;
23130 }
23131 
23132 #define typedef_BDK_AP_PMCCFILTR_EL0 bdk_ap_pmccfiltr_el0_t
23133 #define bustype_BDK_AP_PMCCFILTR_EL0 BDK_CSR_TYPE_SYSREG
23134 #define basename_BDK_AP_PMCCFILTR_EL0 "AP_PMCCFILTR_EL0"
23135 #define busnum_BDK_AP_PMCCFILTR_EL0 0
23136 #define arguments_BDK_AP_PMCCFILTR_EL0 -1,-1,-1,-1
23137 
23138 /**
23139  * Register (SYSREG) ap_pmccntr_el0
23140  *
23141  * AP Performance Monitors Cycle Count Register
23142  * Holds the value of the processor Cycle Counter, CCNT, that
23143  *     counts processor clock cycles.
23144  */
23145 union bdk_ap_pmccntr_el0
23146 {
23147     uint64_t u;
23148     struct bdk_ap_pmccntr_el0_s
23149     {
23150 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23151         uint64_t ccnt                  : 64; /**< [ 63:  0](R/W) Cycle count. Depending on the values of AP_PMCR_EL0.{LC,D}, this
23152                                                                      field increments in one of the following ways:
23153                                                                   Every processor clock cycle.
23154                                                                   Every 64th processor clock cycle.
23155                                                                  This field can be reset to zero by writing 1 to AP_PMCR_EL0[C]. */
23156 #else /* Word 0 - Little Endian */
23157         uint64_t ccnt                  : 64; /**< [ 63:  0](R/W) Cycle count. Depending on the values of AP_PMCR_EL0.{LC,D}, this
23158                                                                      field increments in one of the following ways:
23159                                                                   Every processor clock cycle.
23160                                                                   Every 64th processor clock cycle.
23161                                                                  This field can be reset to zero by writing 1 to AP_PMCR_EL0[C]. */
23162 #endif /* Word 0 - End */
23163     } s;
23164     /* struct bdk_ap_pmccntr_el0_s cn; */
23165 };
23166 typedef union bdk_ap_pmccntr_el0 bdk_ap_pmccntr_el0_t;
23167 
23168 #define BDK_AP_PMCCNTR_EL0 BDK_AP_PMCCNTR_EL0_FUNC()
23169 static inline uint64_t BDK_AP_PMCCNTR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMCCNTR_EL0_FUNC(void)23170 static inline uint64_t BDK_AP_PMCCNTR_EL0_FUNC(void)
23171 {
23172     return 0x303090d0000ll;
23173 }
23174 
23175 #define typedef_BDK_AP_PMCCNTR_EL0 bdk_ap_pmccntr_el0_t
23176 #define bustype_BDK_AP_PMCCNTR_EL0 BDK_CSR_TYPE_SYSREG
23177 #define basename_BDK_AP_PMCCNTR_EL0 "AP_PMCCNTR_EL0"
23178 #define busnum_BDK_AP_PMCCNTR_EL0 0
23179 #define arguments_BDK_AP_PMCCNTR_EL0 -1,-1,-1,-1
23180 
23181 /**
23182  * Register (SYSREG) ap_pmceid0_el0
23183  *
23184  * AP Performance Monitors Common Event Identification Register 0
23185  * Defines which common architectural and common
23186  *     microarchitectural feature events are implemented. If a
23187  *     particular bit is set to 1, then the event for that bit is
23188  *     implemented.
23189  */
23190 union bdk_ap_pmceid0_el0
23191 {
23192     uint64_t u;
23193     struct bdk_ap_pmceid0_el0_s
23194     {
23195 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23196         uint64_t ce                    : 64; /**< [ 63:  0](RO) Common architectural and microarchitectural feature events
23197                                                                      that can be counted by the PMU event counters.
23198                                                                  For each bit described in the following table, the event is
23199                                                                      implemented if the bit is set to 1, or not implemented if the
23200                                                                      bit is set to 0.
23201 
23202                                                                  \<pre\>
23203                                                                  Bit Event number    Event mnemonic
23204                                                                  31  0x01F   L1D_CACHE_ALLOCATE
23205                                                                  30  0x01E   CHAIN
23206                                                                  29  0x01D   BUS_CYCLES
23207                                                                  28  0x01C   TTBR_WRITE_RETIRED
23208                                                                  27  0x01B   INST_SPEC
23209                                                                  26  0x01A   MEMORY_ERROR
23210                                                                  25  0x019   BUS_ACCESS
23211                                                                  24  0x018   L2D_CACHE_WB
23212                                                                  23  0x017   L2D_CACHE_REFILL
23213                                                                  22  0x016   L2D_CACHE
23214                                                                  21  0x015   L1D_CACHE_WB
23215                                                                  20  0x014   L1I_CACHE
23216                                                                  19  0x013   MEM_ACCESS
23217                                                                  18  0x012   BR_PRED
23218                                                                  17  0x011   CPU_CYCLES
23219                                                                  16  0x010   BR_MIS_PRED
23220                                                                  15  0x00F   UNALIGNED_LDST_RETIRED
23221                                                                  14  0x00E   BR_RETURN_RETIRED
23222                                                                  13  0x00D   BR_IMMED_RETIRED
23223                                                                  12  0x00C   PC_WRITE_RETIRED
23224                                                                  11  0x00B   CID_WRITE_RETIRED
23225                                                                  10  0x00A   EXC_RETURN
23226                                                                  9   0x009   EXC_TAKEN
23227                                                                  8   0x008   INST_RETIRED
23228                                                                  7   0x007   ST_RETIRED
23229                                                                  6   0x006   LD_RETIRED
23230                                                                  5   0x005   L1D_TLB_REFILL
23231                                                                  4   0x004   L1D_CACHE
23232                                                                  3   0x003   L1D_CACHE_REFILL
23233                                                                  2   0x002   L1I_TLB_REFILL
23234                                                                  1   0x001   L1I_CACHE_REFILL
23235                                                                  0   0x000   SW_INCR
23236                                                                  \</pre\> */
23237 #else /* Word 0 - Little Endian */
23238         uint64_t ce                    : 64; /**< [ 63:  0](RO) Common architectural and microarchitectural feature events
23239                                                                      that can be counted by the PMU event counters.
23240                                                                  For each bit described in the following table, the event is
23241                                                                      implemented if the bit is set to 1, or not implemented if the
23242                                                                      bit is set to 0.
23243 
23244                                                                  \<pre\>
23245                                                                  Bit Event number    Event mnemonic
23246                                                                  31  0x01F   L1D_CACHE_ALLOCATE
23247                                                                  30  0x01E   CHAIN
23248                                                                  29  0x01D   BUS_CYCLES
23249                                                                  28  0x01C   TTBR_WRITE_RETIRED
23250                                                                  27  0x01B   INST_SPEC
23251                                                                  26  0x01A   MEMORY_ERROR
23252                                                                  25  0x019   BUS_ACCESS
23253                                                                  24  0x018   L2D_CACHE_WB
23254                                                                  23  0x017   L2D_CACHE_REFILL
23255                                                                  22  0x016   L2D_CACHE
23256                                                                  21  0x015   L1D_CACHE_WB
23257                                                                  20  0x014   L1I_CACHE
23258                                                                  19  0x013   MEM_ACCESS
23259                                                                  18  0x012   BR_PRED
23260                                                                  17  0x011   CPU_CYCLES
23261                                                                  16  0x010   BR_MIS_PRED
23262                                                                  15  0x00F   UNALIGNED_LDST_RETIRED
23263                                                                  14  0x00E   BR_RETURN_RETIRED
23264                                                                  13  0x00D   BR_IMMED_RETIRED
23265                                                                  12  0x00C   PC_WRITE_RETIRED
23266                                                                  11  0x00B   CID_WRITE_RETIRED
23267                                                                  10  0x00A   EXC_RETURN
23268                                                                  9   0x009   EXC_TAKEN
23269                                                                  8   0x008   INST_RETIRED
23270                                                                  7   0x007   ST_RETIRED
23271                                                                  6   0x006   LD_RETIRED
23272                                                                  5   0x005   L1D_TLB_REFILL
23273                                                                  4   0x004   L1D_CACHE
23274                                                                  3   0x003   L1D_CACHE_REFILL
23275                                                                  2   0x002   L1I_TLB_REFILL
23276                                                                  1   0x001   L1I_CACHE_REFILL
23277                                                                  0   0x000   SW_INCR
23278                                                                  \</pre\> */
23279 #endif /* Word 0 - End */
23280     } s;
23281     /* struct bdk_ap_pmceid0_el0_s cn8; */
23282     struct bdk_ap_pmceid0_el0_cn9
23283     {
23284 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23285         uint64_t ce                    : 64; /**< [ 63:  0](RO) Common architectural and microarchitectural feature events
23286                                                                      that can be counted by the PMU event counters.
23287                                                                  For each bit described in the following table, the event is
23288                                                                      implemented if the bit is set to 1, or not implemented if the
23289                                                                      bit is set to 0.
23290 
23291                                                                  \<pre\>
23292                                                                  Bit Event number    Event mnemonic
23293                                                                  35  0x4003  SAMPLE_COLLISION.
23294                                                                  34  0x4002  SAMPLE_FILTRATE.
23295                                                                  33  0x4001  SAMPLE_FEED.
23296                                                                  32  0x4000  SAMPLE_POP.
23297                                                                  31  0x01F   L1D_CACHE_ALLOCATE
23298                                                                  30  0x01E   CHAIN
23299                                                                  29  0x01D   BUS_CYCLES
23300                                                                  28  0x01C   TTBR_WRITE_RETIRED
23301                                                                  27  0x01B   INST_SPEC
23302                                                                  26  0x01A   MEMORY_ERROR
23303                                                                  25  0x019   BUS_ACCESS
23304                                                                  24  0x018   L2D_CACHE_WB
23305                                                                  23  0x017   L2D_CACHE_REFILL
23306                                                                  22  0x016   L2D_CACHE
23307                                                                  21  0x015   L1D_CACHE_WB
23308                                                                  20  0x014   L1I_CACHE
23309                                                                  19  0x013   MEM_ACCESS
23310                                                                  18  0x012   BR_PRED
23311                                                                  17  0x011   CPU_CYCLES
23312                                                                  16  0x010   BR_MIS_PRED
23313                                                                  15  0x00F   UNALIGNED_LDST_RETIRED
23314                                                                  14  0x00E   BR_RETURN_RETIRED
23315                                                                  13  0x00D   BR_IMMED_RETIRED
23316                                                                  12  0x00C   PC_WRITE_RETIRED
23317                                                                  11  0x00B   CID_WRITE_RETIRED
23318                                                                  10  0x00A   EXC_RETURN
23319                                                                  9   0x009   EXC_TAKEN
23320                                                                  8   0x008   INST_RETIRED
23321                                                                  7   0x007   ST_RETIRED
23322                                                                  6   0x006   LD_RETIRED
23323                                                                  5   0x005   L1D_TLB_REFILL
23324                                                                  4   0x004   L1D_CACHE
23325                                                                  3   0x003   L1D_CACHE_REFILL
23326                                                                  2   0x002   L1I_TLB_REFILL
23327                                                                  1   0x001   L1I_CACHE_REFILL
23328                                                                  0   0x000   SW_INCR
23329                                                                  \</pre\> */
23330 #else /* Word 0 - Little Endian */
23331         uint64_t ce                    : 64; /**< [ 63:  0](RO) Common architectural and microarchitectural feature events
23332                                                                      that can be counted by the PMU event counters.
23333                                                                  For each bit described in the following table, the event is
23334                                                                      implemented if the bit is set to 1, or not implemented if the
23335                                                                      bit is set to 0.
23336 
23337                                                                  \<pre\>
23338                                                                  Bit Event number    Event mnemonic
23339                                                                  35  0x4003  SAMPLE_COLLISION.
23340                                                                  34  0x4002  SAMPLE_FILTRATE.
23341                                                                  33  0x4001  SAMPLE_FEED.
23342                                                                  32  0x4000  SAMPLE_POP.
23343                                                                  31  0x01F   L1D_CACHE_ALLOCATE
23344                                                                  30  0x01E   CHAIN
23345                                                                  29  0x01D   BUS_CYCLES
23346                                                                  28  0x01C   TTBR_WRITE_RETIRED
23347                                                                  27  0x01B   INST_SPEC
23348                                                                  26  0x01A   MEMORY_ERROR
23349                                                                  25  0x019   BUS_ACCESS
23350                                                                  24  0x018   L2D_CACHE_WB
23351                                                                  23  0x017   L2D_CACHE_REFILL
23352                                                                  22  0x016   L2D_CACHE
23353                                                                  21  0x015   L1D_CACHE_WB
23354                                                                  20  0x014   L1I_CACHE
23355                                                                  19  0x013   MEM_ACCESS
23356                                                                  18  0x012   BR_PRED
23357                                                                  17  0x011   CPU_CYCLES
23358                                                                  16  0x010   BR_MIS_PRED
23359                                                                  15  0x00F   UNALIGNED_LDST_RETIRED
23360                                                                  14  0x00E   BR_RETURN_RETIRED
23361                                                                  13  0x00D   BR_IMMED_RETIRED
23362                                                                  12  0x00C   PC_WRITE_RETIRED
23363                                                                  11  0x00B   CID_WRITE_RETIRED
23364                                                                  10  0x00A   EXC_RETURN
23365                                                                  9   0x009   EXC_TAKEN
23366                                                                  8   0x008   INST_RETIRED
23367                                                                  7   0x007   ST_RETIRED
23368                                                                  6   0x006   LD_RETIRED
23369                                                                  5   0x005   L1D_TLB_REFILL
23370                                                                  4   0x004   L1D_CACHE
23371                                                                  3   0x003   L1D_CACHE_REFILL
23372                                                                  2   0x002   L1I_TLB_REFILL
23373                                                                  1   0x001   L1I_CACHE_REFILL
23374                                                                  0   0x000   SW_INCR
23375                                                                  \</pre\> */
23376 #endif /* Word 0 - End */
23377     } cn9;
23378 };
23379 typedef union bdk_ap_pmceid0_el0 bdk_ap_pmceid0_el0_t;
23380 
23381 #define BDK_AP_PMCEID0_EL0 BDK_AP_PMCEID0_EL0_FUNC()
23382 static inline uint64_t BDK_AP_PMCEID0_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMCEID0_EL0_FUNC(void)23383 static inline uint64_t BDK_AP_PMCEID0_EL0_FUNC(void)
23384 {
23385     return 0x303090c0600ll;
23386 }
23387 
23388 #define typedef_BDK_AP_PMCEID0_EL0 bdk_ap_pmceid0_el0_t
23389 #define bustype_BDK_AP_PMCEID0_EL0 BDK_CSR_TYPE_SYSREG
23390 #define basename_BDK_AP_PMCEID0_EL0 "AP_PMCEID0_EL0"
23391 #define busnum_BDK_AP_PMCEID0_EL0 0
23392 #define arguments_BDK_AP_PMCEID0_EL0 -1,-1,-1,-1
23393 
23394 /**
23395  * Register (SYSREG) ap_pmceid1_el0
23396  *
23397  * AP Performance Monitors Common Event Identification Register 1
23398  * Reserved for future indication of which common architectural
23399  *     and common microarchitectural feature events are implemented.
23400  */
23401 union bdk_ap_pmceid1_el0
23402 {
23403     uint64_t u;
23404     struct bdk_ap_pmceid1_el0_s
23405     {
23406 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23407         uint64_t ce                    : 64; /**< [ 63:  0](RO) Common architectural and microarchitectural feature events
23408                                                                      that can be counted by the PMU event counters.
23409 
23410                                                                  For the bit described in the following table, the event is
23411                                                                      implemented if the bit is set to 1, or not implemented if the
23412                                                                      bit is set to 0.
23413 
23414                                                                  \<pre\>
23415                                                                  Bit Event number    Event mnemonic
23416                                                                  0   0x020   L2D_CACHE_ALLOCATE
23417                                                                  \</pre\> */
23418 #else /* Word 0 - Little Endian */
23419         uint64_t ce                    : 64; /**< [ 63:  0](RO) Common architectural and microarchitectural feature events
23420                                                                      that can be counted by the PMU event counters.
23421 
23422                                                                  For the bit described in the following table, the event is
23423                                                                      implemented if the bit is set to 1, or not implemented if the
23424                                                                      bit is set to 0.
23425 
23426                                                                  \<pre\>
23427                                                                  Bit Event number    Event mnemonic
23428                                                                  0   0x020   L2D_CACHE_ALLOCATE
23429                                                                  \</pre\> */
23430 #endif /* Word 0 - End */
23431     } s;
23432     /* struct bdk_ap_pmceid1_el0_s cn8; */
23433     struct bdk_ap_pmceid1_el0_cn9
23434     {
23435 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23436         uint64_t ce                    : 64; /**< [ 63:  0](RO) Common architectural and microarchitectural feature events
23437                                                                      that can be counted by the PMU event counters.
23438 
23439                                                                  For the bit described in the following table, the event is
23440                                                                      implemented if the bit is set to 1, or not implemented if the
23441                                                                      bit is set to 0.
23442 
23443                                                                  \<pre\>
23444                                                                  Bit Event number    Event mnemonic
23445                                                                    24  0x0038 = REMOTE_ACCESS_RD.
23446                                                                    23  0x0037 = LL_CACHE_MISS_RD.
23447                                                                    22  0x0036 = LL_CACHE_RD.
23448                                                                    21  0x0035 = ITLB_WALK.
23449                                                                    20  0x0034 = DTLB_WALK.
23450                                                                    19  0x0033 = LL_CACHE MISS.
23451                                                                    18  0x0032 = LL_CACHE.
23452                                                                    17  0x0031 = REMOTE_ACCESS.
23453                                                                    16  RAZ
23454                                                                    15  0x002f = L2D_TLB.
23455                                                                    14  0x002e = L2I_TLB_REFILL.
23456                                                                    13  0x002d = L2D_TLB_REFILL.
23457                                                                    8   0x0028 = L2I_CACHE_REFILL.
23458                                                                    7   0x0027 = L2I_CACHE.
23459                                                                    6   0x0026 = L1I_TLB.
23460                                                                    5   0x0025 = L1D_TLB.
23461                                                                    4   0x0024 = STALL_BACKEND.
23462                                                                    3   0x0023 = STALL_FRONTEND.
23463                                                                    2   0x0022 = BR_MIS_PRED_RETIRED.
23464                                                                    1   0x0021 = BR_RETIRED.
23465                                                                    0   0x020   L2D_CACHE_ALLOCATE.
23466                                                                  \</pre\> */
23467 #else /* Word 0 - Little Endian */
23468         uint64_t ce                    : 64; /**< [ 63:  0](RO) Common architectural and microarchitectural feature events
23469                                                                      that can be counted by the PMU event counters.
23470 
23471                                                                  For the bit described in the following table, the event is
23472                                                                      implemented if the bit is set to 1, or not implemented if the
23473                                                                      bit is set to 0.
23474 
23475                                                                  \<pre\>
23476                                                                  Bit Event number    Event mnemonic
23477                                                                    24  0x0038 = REMOTE_ACCESS_RD.
23478                                                                    23  0x0037 = LL_CACHE_MISS_RD.
23479                                                                    22  0x0036 = LL_CACHE_RD.
23480                                                                    21  0x0035 = ITLB_WALK.
23481                                                                    20  0x0034 = DTLB_WALK.
23482                                                                    19  0x0033 = LL_CACHE MISS.
23483                                                                    18  0x0032 = LL_CACHE.
23484                                                                    17  0x0031 = REMOTE_ACCESS.
23485                                                                    16  RAZ
23486                                                                    15  0x002f = L2D_TLB.
23487                                                                    14  0x002e = L2I_TLB_REFILL.
23488                                                                    13  0x002d = L2D_TLB_REFILL.
23489                                                                    8   0x0028 = L2I_CACHE_REFILL.
23490                                                                    7   0x0027 = L2I_CACHE.
23491                                                                    6   0x0026 = L1I_TLB.
23492                                                                    5   0x0025 = L1D_TLB.
23493                                                                    4   0x0024 = STALL_BACKEND.
23494                                                                    3   0x0023 = STALL_FRONTEND.
23495                                                                    2   0x0022 = BR_MIS_PRED_RETIRED.
23496                                                                    1   0x0021 = BR_RETIRED.
23497                                                                    0   0x020   L2D_CACHE_ALLOCATE.
23498                                                                  \</pre\> */
23499 #endif /* Word 0 - End */
23500     } cn9;
23501 };
23502 typedef union bdk_ap_pmceid1_el0 bdk_ap_pmceid1_el0_t;
23503 
23504 #define BDK_AP_PMCEID1_EL0 BDK_AP_PMCEID1_EL0_FUNC()
23505 static inline uint64_t BDK_AP_PMCEID1_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMCEID1_EL0_FUNC(void)23506 static inline uint64_t BDK_AP_PMCEID1_EL0_FUNC(void)
23507 {
23508     return 0x303090c0700ll;
23509 }
23510 
23511 #define typedef_BDK_AP_PMCEID1_EL0 bdk_ap_pmceid1_el0_t
23512 #define bustype_BDK_AP_PMCEID1_EL0 BDK_CSR_TYPE_SYSREG
23513 #define basename_BDK_AP_PMCEID1_EL0 "AP_PMCEID1_EL0"
23514 #define busnum_BDK_AP_PMCEID1_EL0 0
23515 #define arguments_BDK_AP_PMCEID1_EL0 -1,-1,-1,-1
23516 
23517 /**
23518  * Register (SYSREG) ap_pmcntenclr_el0
23519  *
23520  * AP Performance Monitors Count Enable Clear Register
23521  * Disables the Cycle Count Register, AP_PMCCNTR_EL0, and any
23522  *     implemented event counters PMEVCNTR\<x\>. Reading this register
23523  *     shows which counters are enabled.
23524  */
23525 union bdk_ap_pmcntenclr_el0
23526 {
23527     uint32_t u;
23528     struct bdk_ap_pmcntenclr_el0_s
23529     {
23530 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23531         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 disable bit. Disables the cycle counter register.
23532                                                                  0 = When read, means the cycle counter is disabled. When written,
23533                                                                      has no effect.
23534                                                                  1 = When read, means the cycle counter is enabled. When written,
23535                                                                      disables the cycle counter. */
23536         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter disable bit for PMEVCNTR\<x\>.
23537                                                                  Bits [30:N] are RAZ/WI.
23538                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
23539                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
23540                                                                      AP_PMCR_EL0[N].
23541 
23542                                                                  0 = When read, means that PMEVCNTR\<x\> is disabled. When written,
23543                                                                      has no effect.
23544                                                                  1 = When read, means that PMEVCNTR\<x\> is enabled. When written,
23545                                                                      disables PMEVCNTR\<x\>. */
23546 #else /* Word 0 - Little Endian */
23547         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter disable bit for PMEVCNTR\<x\>.
23548                                                                  Bits [30:N] are RAZ/WI.
23549                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
23550                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
23551                                                                      AP_PMCR_EL0[N].
23552 
23553                                                                  0 = When read, means that PMEVCNTR\<x\> is disabled. When written,
23554                                                                      has no effect.
23555                                                                  1 = When read, means that PMEVCNTR\<x\> is enabled. When written,
23556                                                                      disables PMEVCNTR\<x\>. */
23557         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 disable bit. Disables the cycle counter register.
23558                                                                  0 = When read, means the cycle counter is disabled. When written,
23559                                                                      has no effect.
23560                                                                  1 = When read, means the cycle counter is enabled. When written,
23561                                                                      disables the cycle counter. */
23562 #endif /* Word 0 - End */
23563     } s;
23564     /* struct bdk_ap_pmcntenclr_el0_s cn; */
23565 };
23566 typedef union bdk_ap_pmcntenclr_el0 bdk_ap_pmcntenclr_el0_t;
23567 
23568 #define BDK_AP_PMCNTENCLR_EL0 BDK_AP_PMCNTENCLR_EL0_FUNC()
23569 static inline uint64_t BDK_AP_PMCNTENCLR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMCNTENCLR_EL0_FUNC(void)23570 static inline uint64_t BDK_AP_PMCNTENCLR_EL0_FUNC(void)
23571 {
23572     return 0x303090c0200ll;
23573 }
23574 
23575 #define typedef_BDK_AP_PMCNTENCLR_EL0 bdk_ap_pmcntenclr_el0_t
23576 #define bustype_BDK_AP_PMCNTENCLR_EL0 BDK_CSR_TYPE_SYSREG
23577 #define basename_BDK_AP_PMCNTENCLR_EL0 "AP_PMCNTENCLR_EL0"
23578 #define busnum_BDK_AP_PMCNTENCLR_EL0 0
23579 #define arguments_BDK_AP_PMCNTENCLR_EL0 -1,-1,-1,-1
23580 
23581 /**
23582  * Register (SYSREG) ap_pmcntenset_el0
23583  *
23584  * AP Performance Monitors Count Enable Set Register
23585  * Enables the Cycle Count Register, AP_PMCCNTR_EL0, and any
23586  *     implemented event counters PMEVCNTR\<x\>. Reading this register
23587  *     shows which counters are enabled.
23588  */
23589 union bdk_ap_pmcntenset_el0
23590 {
23591     uint32_t u;
23592     struct bdk_ap_pmcntenset_el0_s
23593     {
23594 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23595         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 enable bit. Enables the cycle counter register.
23596                                                                  0 = When read, means the cycle counter is disabled. When written,
23597                                                                      has no effect.
23598                                                                  1 = When read, means the cycle counter is enabled. When written,
23599                                                                      enables the cycle counter. */
23600         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter enable bit for PMEVCNTR\<x\>.
23601                                                                  Bits [30:N] are RAZ/WI.
23602                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
23603                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
23604                                                                      AP_PMCR_EL0[N].
23605 
23606                                                                  0 = When read, means that PMEVCNTR\<x\> is disabled. When written,
23607                                                                      has no effect.
23608                                                                  1 = When read, means that PMEVCNTR\<x\> event counter is enabled.
23609                                                                      When written, enables PMEVCNTR\<x\>. */
23610 #else /* Word 0 - Little Endian */
23611         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter enable bit for PMEVCNTR\<x\>.
23612                                                                  Bits [30:N] are RAZ/WI.
23613                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
23614                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
23615                                                                      AP_PMCR_EL0[N].
23616 
23617                                                                  0 = When read, means that PMEVCNTR\<x\> is disabled. When written,
23618                                                                      has no effect.
23619                                                                  1 = When read, means that PMEVCNTR\<x\> event counter is enabled.
23620                                                                      When written, enables PMEVCNTR\<x\>. */
23621         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 enable bit. Enables the cycle counter register.
23622                                                                  0 = When read, means the cycle counter is disabled. When written,
23623                                                                      has no effect.
23624                                                                  1 = When read, means the cycle counter is enabled. When written,
23625                                                                      enables the cycle counter. */
23626 #endif /* Word 0 - End */
23627     } s;
23628     /* struct bdk_ap_pmcntenset_el0_s cn; */
23629 };
23630 typedef union bdk_ap_pmcntenset_el0 bdk_ap_pmcntenset_el0_t;
23631 
23632 #define BDK_AP_PMCNTENSET_EL0 BDK_AP_PMCNTENSET_EL0_FUNC()
23633 static inline uint64_t BDK_AP_PMCNTENSET_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMCNTENSET_EL0_FUNC(void)23634 static inline uint64_t BDK_AP_PMCNTENSET_EL0_FUNC(void)
23635 {
23636     return 0x303090c0100ll;
23637 }
23638 
23639 #define typedef_BDK_AP_PMCNTENSET_EL0 bdk_ap_pmcntenset_el0_t
23640 #define bustype_BDK_AP_PMCNTENSET_EL0 BDK_CSR_TYPE_SYSREG
23641 #define basename_BDK_AP_PMCNTENSET_EL0 "AP_PMCNTENSET_EL0"
23642 #define busnum_BDK_AP_PMCNTENSET_EL0 0
23643 #define arguments_BDK_AP_PMCNTENSET_EL0 -1,-1,-1,-1
23644 
23645 /**
23646  * Register (SYSREG) ap_pmcr_el0
23647  *
23648  * AP Performance Monitors Control Register
23649  * Provides details of the Performance Monitors implementation,
23650  *     including the number of counters implemented, and configures
23651  *     and controls the counters.
23652  */
23653 union bdk_ap_pmcr_el0
23654 {
23655     uint32_t u;
23656     struct bdk_ap_pmcr_el0_s
23657     {
23658 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23659         uint32_t imp                   : 8;  /**< [ 31: 24](RO) Implementer code. This field is RO with an implementation
23660                                                                      defined value.
23661                                                                  The implementer codes are allocated by ARM. Values have the
23662                                                                      same interpretation as bits [31:24] of the MIDR. */
23663         uint32_t idcode                : 8;  /**< [ 23: 16](RO) Identification code. This field is RO with an implementation
23664                                                                      defined value.
23665                                                                  Each implementer must maintain a list of identification codes
23666                                                                      that is specific to the implementer. A specific implementation
23667                                                                      is identified by the combination of the implementer code and
23668                                                                      the identification code. */
23669         uint32_t n                     : 5;  /**< [ 15: 11](RO) Number of event counters. This field is RO with an
23670                                                                      implementation defined value that indicates the number of
23671                                                                      counters implemented.
23672                                                                  The value of this field is the number of counters implemented.
23673 
23674                                                                  An implementation can implement only the Cycle Count Register,
23675                                                                      AP_PMCCNTR_EL0. This is indicated by a value of0b00000
23676 
23677                                                                  CNXXXX has 6 counters. */
23678         uint32_t reserved_7_10         : 4;
23679         uint32_t lc                    : 1;  /**< [  6:  6](RO) Long cycle counter enable. Determines which AP_PMCCNTR_EL0 bit
23680                                                                      generates an overflow recorded by PMOVSR[31].
23681                                                                  ARM deprecates use of AP_PMCR_EL0[LC] = 0.
23682                                                                  0 = Cycle counter overflow on increment that changes
23683                                                                      AP_PMCCNTR_EL0[31] from 1 to 0.
23684                                                                  1 = Cycle counter overflow on increment that changes
23685                                                                      AP_PMCCNTR_EL0[63] from 1 to 0.
23686 
23687                                                                  CNXXXX doesn't support 32 bit, so this bit is RAO / WI. */
23688         uint32_t dp                    : 1;  /**< [  5:  5](R/W) Disable cycle counter when event counting is prohibited.
23689                                                                  Event counting is prohibited when
23690                                                                      ProfilingProhibited(IsSecure(),PSTATE[EL]) == TRUE.
23691                                                                  0 =  AP_PMCCNTR_EL0, if enabled, counts when event counting is
23692                                                                      prohibited.
23693                                                                  1 =  AP_PMCCNTR_EL0 does not count when event counting is prohibited. */
23694         uint32_t x                     : 1;  /**< [  4:  4](RO) Enable export of events in an implementation defined event
23695                                                                      stream.
23696                                                                  This bit is used to permit events to be exported to another
23697                                                                      debug device, such as an OPTIONAL trace extension, over an
23698                                                                      event bus. If the implementation does not include such an
23699                                                                      event bus, this bit is RAZ/WI.
23700 
23701                                                                  This bit does not affect the generation of Performance
23702                                                                      Monitors overflow interrupt requests or signaling to a cross-
23703                                                                      trigger interface (CTI) that can be implemented as signals
23704                                                                      exported from the processor.
23705 
23706                                                                  If the implementation does not include an exported event
23707                                                                      stream, this bit is RAZ/WI. Otherwise this bit is RW.
23708                                                                  0 = Do not export events.
23709                                                                  1 = Export events where not prohibited.
23710 
23711                                                                  CNXXXX doesn't support export of events. */
23712         uint32_t dd                    : 1;  /**< [  3:  3](RO) Clock divider.
23713                                                                  If AP_PMCR_EL0[LC] == 1, this bit is ignored and the cycle counter
23714                                                                      counts every clock cycle.
23715                                                                  ARM deprecates use of PMCR[D] = 1.
23716                                                                  0 = When enabled, AP_PMCCNTR_EL0 counts every clock cycle.
23717                                                                  1 = When enabled, AP_PMCCNTR_EL0 counts once every 64 clock cycles.
23718 
23719                                                                  CNXXXX doesn't support 32-bit, so this bit is RAZ/WI. */
23720         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cycle counter reset. This bit is WO. The effects of writing to
23721                                                                      this bit are:
23722                                                                  This bit reads as zero.
23723                                                                  Resetting AP_PMCCNTR_EL0 does not clear the AP_PMCCNTR_EL0 overflow
23724                                                                      bit to 0.
23725                                                                  0 = No action.
23726                                                                  1 = Reset AP_PMCCNTR_EL0 to zero. */
23727         uint32_t p                     : 1;  /**< [  1:  1](R/W) Event counter reset. This bit is WO. The effects of writing to
23728                                                                      this bit are:
23729                                                                  This bit reads as zero.
23730                                                                  In nonsecure EL0 and EL1, if EL2 is implemented, a write of 1
23731                                                                      to this bit does not reset event counters that AP_MDCR_EL2[HPMN]
23732                                                                      reserves for EL2 use.
23733                                                                  In EL2 and EL3, a write of 1 to this bit resets all the event
23734                                                                      counters.
23735                                                                  Resetting the event counters does not clear any overflow bits
23736                                                                      to 0.
23737                                                                  0 = No action.
23738                                                                  1 = Reset all event counters accessible in the current EL, not
23739                                                                      including AP_PMCCNTR_EL0, to zero. */
23740         uint32_t ee                    : 1;  /**< [  0:  0](R/W) Enable.
23741                                                                  This bit is RW.
23742                                                                  In nonsecure EL0 and EL1, if EL2 is implemented, this bit
23743                                                                      does not affect the operation of event counters that
23744                                                                      AP_MDCR_EL2[HPMN] reserves for EL2 use.
23745                                                                  0 = All counters, including AP_PMCCNTR_EL0, are disabled.
23746                                                                  1 = All counters are enabled by AP_PMCNTENSET_EL0. */
23747 #else /* Word 0 - Little Endian */
23748         uint32_t ee                    : 1;  /**< [  0:  0](R/W) Enable.
23749                                                                  This bit is RW.
23750                                                                  In nonsecure EL0 and EL1, if EL2 is implemented, this bit
23751                                                                      does not affect the operation of event counters that
23752                                                                      AP_MDCR_EL2[HPMN] reserves for EL2 use.
23753                                                                  0 = All counters, including AP_PMCCNTR_EL0, are disabled.
23754                                                                  1 = All counters are enabled by AP_PMCNTENSET_EL0. */
23755         uint32_t p                     : 1;  /**< [  1:  1](R/W) Event counter reset. This bit is WO. The effects of writing to
23756                                                                      this bit are:
23757                                                                  This bit reads as zero.
23758                                                                  In nonsecure EL0 and EL1, if EL2 is implemented, a write of 1
23759                                                                      to this bit does not reset event counters that AP_MDCR_EL2[HPMN]
23760                                                                      reserves for EL2 use.
23761                                                                  In EL2 and EL3, a write of 1 to this bit resets all the event
23762                                                                      counters.
23763                                                                  Resetting the event counters does not clear any overflow bits
23764                                                                      to 0.
23765                                                                  0 = No action.
23766                                                                  1 = Reset all event counters accessible in the current EL, not
23767                                                                      including AP_PMCCNTR_EL0, to zero. */
23768         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cycle counter reset. This bit is WO. The effects of writing to
23769                                                                      this bit are:
23770                                                                  This bit reads as zero.
23771                                                                  Resetting AP_PMCCNTR_EL0 does not clear the AP_PMCCNTR_EL0 overflow
23772                                                                      bit to 0.
23773                                                                  0 = No action.
23774                                                                  1 = Reset AP_PMCCNTR_EL0 to zero. */
23775         uint32_t dd                    : 1;  /**< [  3:  3](RO) Clock divider.
23776                                                                  If AP_PMCR_EL0[LC] == 1, this bit is ignored and the cycle counter
23777                                                                      counts every clock cycle.
23778                                                                  ARM deprecates use of PMCR[D] = 1.
23779                                                                  0 = When enabled, AP_PMCCNTR_EL0 counts every clock cycle.
23780                                                                  1 = When enabled, AP_PMCCNTR_EL0 counts once every 64 clock cycles.
23781 
23782                                                                  CNXXXX doesn't support 32-bit, so this bit is RAZ/WI. */
23783         uint32_t x                     : 1;  /**< [  4:  4](RO) Enable export of events in an implementation defined event
23784                                                                      stream.
23785                                                                  This bit is used to permit events to be exported to another
23786                                                                      debug device, such as an OPTIONAL trace extension, over an
23787                                                                      event bus. If the implementation does not include such an
23788                                                                      event bus, this bit is RAZ/WI.
23789 
23790                                                                  This bit does not affect the generation of Performance
23791                                                                      Monitors overflow interrupt requests or signaling to a cross-
23792                                                                      trigger interface (CTI) that can be implemented as signals
23793                                                                      exported from the processor.
23794 
23795                                                                  If the implementation does not include an exported event
23796                                                                      stream, this bit is RAZ/WI. Otherwise this bit is RW.
23797                                                                  0 = Do not export events.
23798                                                                  1 = Export events where not prohibited.
23799 
23800                                                                  CNXXXX doesn't support export of events. */
23801         uint32_t dp                    : 1;  /**< [  5:  5](R/W) Disable cycle counter when event counting is prohibited.
23802                                                                  Event counting is prohibited when
23803                                                                      ProfilingProhibited(IsSecure(),PSTATE[EL]) == TRUE.
23804                                                                  0 =  AP_PMCCNTR_EL0, if enabled, counts when event counting is
23805                                                                      prohibited.
23806                                                                  1 =  AP_PMCCNTR_EL0 does not count when event counting is prohibited. */
23807         uint32_t lc                    : 1;  /**< [  6:  6](RO) Long cycle counter enable. Determines which AP_PMCCNTR_EL0 bit
23808                                                                      generates an overflow recorded by PMOVSR[31].
23809                                                                  ARM deprecates use of AP_PMCR_EL0[LC] = 0.
23810                                                                  0 = Cycle counter overflow on increment that changes
23811                                                                      AP_PMCCNTR_EL0[31] from 1 to 0.
23812                                                                  1 = Cycle counter overflow on increment that changes
23813                                                                      AP_PMCCNTR_EL0[63] from 1 to 0.
23814 
23815                                                                  CNXXXX doesn't support 32 bit, so this bit is RAO / WI. */
23816         uint32_t reserved_7_10         : 4;
23817         uint32_t n                     : 5;  /**< [ 15: 11](RO) Number of event counters. This field is RO with an
23818                                                                      implementation defined value that indicates the number of
23819                                                                      counters implemented.
23820                                                                  The value of this field is the number of counters implemented.
23821 
23822                                                                  An implementation can implement only the Cycle Count Register,
23823                                                                      AP_PMCCNTR_EL0. This is indicated by a value of0b00000
23824 
23825                                                                  CNXXXX has 6 counters. */
23826         uint32_t idcode                : 8;  /**< [ 23: 16](RO) Identification code. This field is RO with an implementation
23827                                                                      defined value.
23828                                                                  Each implementer must maintain a list of identification codes
23829                                                                      that is specific to the implementer. A specific implementation
23830                                                                      is identified by the combination of the implementer code and
23831                                                                      the identification code. */
23832         uint32_t imp                   : 8;  /**< [ 31: 24](RO) Implementer code. This field is RO with an implementation
23833                                                                      defined value.
23834                                                                  The implementer codes are allocated by ARM. Values have the
23835                                                                      same interpretation as bits [31:24] of the MIDR. */
23836 #endif /* Word 0 - End */
23837     } s;
23838     /* struct bdk_ap_pmcr_el0_s cn; */
23839 };
23840 typedef union bdk_ap_pmcr_el0 bdk_ap_pmcr_el0_t;
23841 
23842 #define BDK_AP_PMCR_EL0 BDK_AP_PMCR_EL0_FUNC()
23843 static inline uint64_t BDK_AP_PMCR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMCR_EL0_FUNC(void)23844 static inline uint64_t BDK_AP_PMCR_EL0_FUNC(void)
23845 {
23846     return 0x303090c0000ll;
23847 }
23848 
23849 #define typedef_BDK_AP_PMCR_EL0 bdk_ap_pmcr_el0_t
23850 #define bustype_BDK_AP_PMCR_EL0 BDK_CSR_TYPE_SYSREG
23851 #define basename_BDK_AP_PMCR_EL0 "AP_PMCR_EL0"
23852 #define busnum_BDK_AP_PMCR_EL0 0
23853 #define arguments_BDK_AP_PMCR_EL0 -1,-1,-1,-1
23854 
23855 /**
23856  * Register (SYSREG) ap_pmevcntr#_el0
23857  *
23858  * AP Performance Monitors Event Count Registers
23859  * Holds event counter n, which counts events, where n is 0 to
23860  *     30.
23861  */
23862 union bdk_ap_pmevcntrx_el0
23863 {
23864     uint32_t u;
23865     struct bdk_ap_pmevcntrx_el0_s
23866     {
23867 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23868         uint32_t data                  : 32; /**< [ 31:  0](R/W) Event counter n. Value of event counter n, where n is the
23869                                                                      number of this register and is a number from 0 to 30. */
23870 #else /* Word 0 - Little Endian */
23871         uint32_t data                  : 32; /**< [ 31:  0](R/W) Event counter n. Value of event counter n, where n is the
23872                                                                      number of this register and is a number from 0 to 30. */
23873 #endif /* Word 0 - End */
23874     } s;
23875     /* struct bdk_ap_pmevcntrx_el0_s cn; */
23876 };
23877 typedef union bdk_ap_pmevcntrx_el0 bdk_ap_pmevcntrx_el0_t;
23878 
23879 static inline uint64_t BDK_AP_PMEVCNTRX_EL0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_PMEVCNTRX_EL0(unsigned long a)23880 static inline uint64_t BDK_AP_PMEVCNTRX_EL0(unsigned long a)
23881 {
23882     if (a<=30)
23883         return 0x3030e080000ll + 0x100ll * ((a) & 0x1f);
23884     __bdk_csr_fatal("AP_PMEVCNTRX_EL0", 1, a, 0, 0, 0);
23885 }
23886 
23887 #define typedef_BDK_AP_PMEVCNTRX_EL0(a) bdk_ap_pmevcntrx_el0_t
23888 #define bustype_BDK_AP_PMEVCNTRX_EL0(a) BDK_CSR_TYPE_SYSREG
23889 #define basename_BDK_AP_PMEVCNTRX_EL0(a) "AP_PMEVCNTRX_EL0"
23890 #define busnum_BDK_AP_PMEVCNTRX_EL0(a) (a)
23891 #define arguments_BDK_AP_PMEVCNTRX_EL0(a) (a),-1,-1,-1
23892 
23893 /**
23894  * Register (SYSREG) ap_pmevtyper#_el0
23895  *
23896  * AP Performance Monitors Event Type Registers
23897  * Configures event counter n, where n is 0 to 30.
23898  */
23899 union bdk_ap_pmevtyperx_el0
23900 {
23901     uint32_t u;
23902     struct bdk_ap_pmevtyperx_el0_s
23903     {
23904 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
23905         uint32_t p                     : 1;  /**< [ 31: 31](R/W) EL1 modes filtering bit. Controls counting in EL1. If EL3 is
23906                                                                      implemented, then counting in nonsecure EL1 is further
23907                                                                      controlled by the NSK bit.
23908                                                                  0 = Count events in EL1.
23909                                                                  1 = Do not count events in EL1. */
23910         uint32_t u                     : 1;  /**< [ 30: 30](R/W) EL0 filtering bit. Controls counting in EL0. If EL3 is
23911                                                                      implemented, then counting in nonsecure EL0 is further
23912                                                                      controlled by the NSU bit.
23913                                                                  0 = Count events in EL0.
23914                                                                  1 = Do not count events in EL0. */
23915         uint32_t nsk                   : 1;  /**< [ 29: 29](R/W) Nonsecure kernel modes filtering bit. Controls counting in
23916                                                                      nonsecure EL1. If EL3 is not implemented, this bit is RES0.
23917                                                                  If the value of this bit is equal to the value of P, events in
23918                                                                      nonsecure EL1 are counted.
23919                                                                  Otherwise, events in nonsecure EL1 are not counted. */
23920         uint32_t nsu                   : 1;  /**< [ 28: 28](R/W) Nonsecure user modes filtering bit. Controls counting in Non-
23921                                                                      secure EL0. If EL3 is not implemented, this bit is RES0.
23922                                                                  If the value of this bit is equal to the value of U, events in
23923                                                                      nonsecure EL0 are counted.
23924                                                                  Otherwise, events in nonsecure EL0 are not counted. */
23925         uint32_t nsh                   : 1;  /**< [ 27: 27](R/W) Nonsecure Hyp modes filtering bit. Controls counting in Non-
23926                                                                      secure EL2. If EL2 is not implemented, this bit is RES0.
23927                                                                  0 = Do not count events in EL2.
23928                                                                  1 = Count events in EL2. */
23929         uint32_t m                     : 1;  /**< [ 26: 26](R/W) Secure EL3 filtering bit. Most applications can ignore this
23930                                                                      bit and set the value to zero. If EL3 is not implemented, this
23931                                                                      bit is RES0.
23932                                                                  If the value of this bit is equal to the value of P, events in
23933                                                                      Secure EL3 are counted.
23934                                                                  Otherwise, events in Secure EL3 are not counted. */
23935         uint32_t reserved_16_25        : 10;
23936         uint32_t evtcount              : 16; /**< [ 15:  0](R/W) Event to count. The event number of the event that is counted
23937                                                                      by event counter PMEVCNTR\<n\>_EL0.
23938                                                                  Software must program this field with an event defined by the
23939                                                                      processor or a common event defined by the architecture.
23940                                                                  If evtCount is programmed to an event that is reserved or not
23941                                                                      implemented, the behavior depends on the event type.
23942 
23943                                                                  For common architectural and microarchitectural events:
23944                                                                   No events are counted.
23945                                                                   The value read back on evtCount is the value written.
23946 
23947                                                                  For implementation defined events:
23948 
23949                                                                   It is UNPREDICTABLE what event, if any, is counted.
23950                                                                      UNPREDICTABLE in this case means the event must not expose
23951                                                                      privileged information.
23952 
23953                                                                   The value read back on evtCount is an UNKNOWN value with the
23954                                                                      same effect.
23955 
23956                                                                  ARM recommends that the behavior across a family of
23957                                                                      implementations is defined such that if a given implementation
23958                                                                      does not include an event from a set of common implementation
23959                                                                      defined events, then no event is counted and the value read
23960                                                                      back on evtCount is the value written.
23961 
23962                                                                  v8.1: Width was extended to 16 bits. */
23963 #else /* Word 0 - Little Endian */
23964         uint32_t evtcount              : 16; /**< [ 15:  0](R/W) Event to count. The event number of the event that is counted
23965                                                                      by event counter PMEVCNTR\<n\>_EL0.
23966                                                                  Software must program this field with an event defined by the
23967                                                                      processor or a common event defined by the architecture.
23968                                                                  If evtCount is programmed to an event that is reserved or not
23969                                                                      implemented, the behavior depends on the event type.
23970 
23971                                                                  For common architectural and microarchitectural events:
23972                                                                   No events are counted.
23973                                                                   The value read back on evtCount is the value written.
23974 
23975                                                                  For implementation defined events:
23976 
23977                                                                   It is UNPREDICTABLE what event, if any, is counted.
23978                                                                      UNPREDICTABLE in this case means the event must not expose
23979                                                                      privileged information.
23980 
23981                                                                   The value read back on evtCount is an UNKNOWN value with the
23982                                                                      same effect.
23983 
23984                                                                  ARM recommends that the behavior across a family of
23985                                                                      implementations is defined such that if a given implementation
23986                                                                      does not include an event from a set of common implementation
23987                                                                      defined events, then no event is counted and the value read
23988                                                                      back on evtCount is the value written.
23989 
23990                                                                  v8.1: Width was extended to 16 bits. */
23991         uint32_t reserved_16_25        : 10;
23992         uint32_t m                     : 1;  /**< [ 26: 26](R/W) Secure EL3 filtering bit. Most applications can ignore this
23993                                                                      bit and set the value to zero. If EL3 is not implemented, this
23994                                                                      bit is RES0.
23995                                                                  If the value of this bit is equal to the value of P, events in
23996                                                                      Secure EL3 are counted.
23997                                                                  Otherwise, events in Secure EL3 are not counted. */
23998         uint32_t nsh                   : 1;  /**< [ 27: 27](R/W) Nonsecure Hyp modes filtering bit. Controls counting in Non-
23999                                                                      secure EL2. If EL2 is not implemented, this bit is RES0.
24000                                                                  0 = Do not count events in EL2.
24001                                                                  1 = Count events in EL2. */
24002         uint32_t nsu                   : 1;  /**< [ 28: 28](R/W) Nonsecure user modes filtering bit. Controls counting in Non-
24003                                                                      secure EL0. If EL3 is not implemented, this bit is RES0.
24004                                                                  If the value of this bit is equal to the value of U, events in
24005                                                                      nonsecure EL0 are counted.
24006                                                                  Otherwise, events in nonsecure EL0 are not counted. */
24007         uint32_t nsk                   : 1;  /**< [ 29: 29](R/W) Nonsecure kernel modes filtering bit. Controls counting in
24008                                                                      nonsecure EL1. If EL3 is not implemented, this bit is RES0.
24009                                                                  If the value of this bit is equal to the value of P, events in
24010                                                                      nonsecure EL1 are counted.
24011                                                                  Otherwise, events in nonsecure EL1 are not counted. */
24012         uint32_t u                     : 1;  /**< [ 30: 30](R/W) EL0 filtering bit. Controls counting in EL0. If EL3 is
24013                                                                      implemented, then counting in nonsecure EL0 is further
24014                                                                      controlled by the NSU bit.
24015                                                                  0 = Count events in EL0.
24016                                                                  1 = Do not count events in EL0. */
24017         uint32_t p                     : 1;  /**< [ 31: 31](R/W) EL1 modes filtering bit. Controls counting in EL1. If EL3 is
24018                                                                      implemented, then counting in nonsecure EL1 is further
24019                                                                      controlled by the NSK bit.
24020                                                                  0 = Count events in EL1.
24021                                                                  1 = Do not count events in EL1. */
24022 #endif /* Word 0 - End */
24023     } s;
24024     /* struct bdk_ap_pmevtyperx_el0_s cn; */
24025 };
24026 typedef union bdk_ap_pmevtyperx_el0 bdk_ap_pmevtyperx_el0_t;
24027 
24028 static inline uint64_t BDK_AP_PMEVTYPERX_EL0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_PMEVTYPERX_EL0(unsigned long a)24029 static inline uint64_t BDK_AP_PMEVTYPERX_EL0(unsigned long a)
24030 {
24031     if (a<=30)
24032         return 0x3030e0c0000ll + 0x100ll * ((a) & 0x1f);
24033     __bdk_csr_fatal("AP_PMEVTYPERX_EL0", 1, a, 0, 0, 0);
24034 }
24035 
24036 #define typedef_BDK_AP_PMEVTYPERX_EL0(a) bdk_ap_pmevtyperx_el0_t
24037 #define bustype_BDK_AP_PMEVTYPERX_EL0(a) BDK_CSR_TYPE_SYSREG
24038 #define basename_BDK_AP_PMEVTYPERX_EL0(a) "AP_PMEVTYPERX_EL0"
24039 #define busnum_BDK_AP_PMEVTYPERX_EL0(a) (a)
24040 #define arguments_BDK_AP_PMEVTYPERX_EL0(a) (a),-1,-1,-1
24041 
24042 /**
24043  * Register (SYSREG) ap_pmintenclr_el1
24044  *
24045  * AP Performance Monitors Interrupt Enable Clear Register
24046  * Disables the generation of interrupt requests on overflows
24047  *     from the Cycle Count Register, AP_PMCCNTR_EL0, and the event
24048  *     counters PMEVCNTR\<n\>_EL0. Reading the register shows which
24049  *     overflow interrupt requests are enabled.
24050  */
24051 union bdk_ap_pmintenclr_el1
24052 {
24053     uint32_t u;
24054     struct bdk_ap_pmintenclr_el1_s
24055     {
24056 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24057         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow interrupt request disable bit. Possible
24058                                                                      values are:
24059                                                                  0 = When read, means the cycle counter overflow interrupt request
24060                                                                      is disabled. When written, has no effect.
24061                                                                  1 = When read, means the cycle counter overflow interrupt request
24062                                                                      is enabled. When written, disables the cycle count overflow
24063                                                                      interrupt request. */
24064         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow interrupt request disable bit for
24065                                                                      PMEVCNTR\<x\>_EL0.
24066                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24067                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24068                                                                      AP_PMCR_EL0[N].
24069                                                                  Bits [30:N] are RAZ/WI.
24070                                                                  0 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24071                                                                      interrupt request is disabled. When written, has no effect.
24072                                                                  1 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24073                                                                      interrupt request is enabled. When written, disables the
24074                                                                      PMEVCNTR\<x\>_EL0 interrupt request. */
24075 #else /* Word 0 - Little Endian */
24076         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow interrupt request disable bit for
24077                                                                      PMEVCNTR\<x\>_EL0.
24078                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24079                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24080                                                                      AP_PMCR_EL0[N].
24081                                                                  Bits [30:N] are RAZ/WI.
24082                                                                  0 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24083                                                                      interrupt request is disabled. When written, has no effect.
24084                                                                  1 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24085                                                                      interrupt request is enabled. When written, disables the
24086                                                                      PMEVCNTR\<x\>_EL0 interrupt request. */
24087         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow interrupt request disable bit. Possible
24088                                                                      values are:
24089                                                                  0 = When read, means the cycle counter overflow interrupt request
24090                                                                      is disabled. When written, has no effect.
24091                                                                  1 = When read, means the cycle counter overflow interrupt request
24092                                                                      is enabled. When written, disables the cycle count overflow
24093                                                                      interrupt request. */
24094 #endif /* Word 0 - End */
24095     } s;
24096     /* struct bdk_ap_pmintenclr_el1_s cn8; */
24097     struct bdk_ap_pmintenclr_el1_cn9
24098     {
24099 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24100         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow interrupt request disable bit.
24101                                                                  0 = When read, means the cycle counter overflow interrupt request
24102                                                                      is disabled. When written, has no effect.
24103                                                                  1 = When read, means the cycle counter overflow interrupt request
24104                                                                      is enabled. When written, disables the cycle count overflow
24105                                                                      interrupt request. */
24106         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow interrupt request disable bit for
24107                                                                      PMEVCNTR\<x\>_EL0.
24108                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24109                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24110                                                                      AP_PMCR_EL0[N].
24111                                                                  Bits [30:N] are RAZ/WI.
24112                                                                  0 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24113                                                                      interrupt request is disabled. When written, has no effect.
24114                                                                  1 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24115                                                                      interrupt request is enabled. When written, disables the
24116                                                                      PMEVCNTR\<x\>_EL0 interrupt request. */
24117 #else /* Word 0 - Little Endian */
24118         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow interrupt request disable bit for
24119                                                                      PMEVCNTR\<x\>_EL0.
24120                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24121                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24122                                                                      AP_PMCR_EL0[N].
24123                                                                  Bits [30:N] are RAZ/WI.
24124                                                                  0 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24125                                                                      interrupt request is disabled. When written, has no effect.
24126                                                                  1 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24127                                                                      interrupt request is enabled. When written, disables the
24128                                                                      PMEVCNTR\<x\>_EL0 interrupt request. */
24129         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow interrupt request disable bit.
24130                                                                  0 = When read, means the cycle counter overflow interrupt request
24131                                                                      is disabled. When written, has no effect.
24132                                                                  1 = When read, means the cycle counter overflow interrupt request
24133                                                                      is enabled. When written, disables the cycle count overflow
24134                                                                      interrupt request. */
24135 #endif /* Word 0 - End */
24136     } cn9;
24137 };
24138 typedef union bdk_ap_pmintenclr_el1 bdk_ap_pmintenclr_el1_t;
24139 
24140 #define BDK_AP_PMINTENCLR_EL1 BDK_AP_PMINTENCLR_EL1_FUNC()
24141 static inline uint64_t BDK_AP_PMINTENCLR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMINTENCLR_EL1_FUNC(void)24142 static inline uint64_t BDK_AP_PMINTENCLR_EL1_FUNC(void)
24143 {
24144     return 0x300090e0200ll;
24145 }
24146 
24147 #define typedef_BDK_AP_PMINTENCLR_EL1 bdk_ap_pmintenclr_el1_t
24148 #define bustype_BDK_AP_PMINTENCLR_EL1 BDK_CSR_TYPE_SYSREG
24149 #define basename_BDK_AP_PMINTENCLR_EL1 "AP_PMINTENCLR_EL1"
24150 #define busnum_BDK_AP_PMINTENCLR_EL1 0
24151 #define arguments_BDK_AP_PMINTENCLR_EL1 -1,-1,-1,-1
24152 
24153 /**
24154  * Register (SYSREG) ap_pmintenset_el1
24155  *
24156  * AP Performance Monitors Interrupt Enable Set Register
24157  * Enables the generation of interrupt requests on overflows from
24158  *     the Cycle Count Register, AP_PMCCNTR_EL0, and the event counters
24159  *     PMEVCNTR\<n\>_EL0. Reading the register shows which overflow
24160  *     interrupt requests are enabled.
24161  */
24162 union bdk_ap_pmintenset_el1
24163 {
24164     uint32_t u;
24165     struct bdk_ap_pmintenset_el1_s
24166     {
24167 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24168         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow interrupt request enable bit. Possible
24169                                                                      values are:
24170                                                                  0 = When read, means the cycle counter overflow interrupt request
24171                                                                      is disabled. When written, has no effect.
24172                                                                  1 = When read, means the cycle counter overflow interrupt request
24173                                                                      is enabled. When written, enables the cycle count overflow
24174                                                                      interrupt request. */
24175         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow interrupt request enable bit for
24176                                                                      PMEVCNTR\<x\>_EL0.
24177 
24178                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24179                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24180                                                                      AP_PMCR_EL0[N].
24181 
24182                                                                  Bits [30:N] are RAZ/WI.
24183 
24184                                                                  0 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24185                                                                      interrupt request is disabled. When written, has no effect.
24186                                                                  1 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24187                                                                      interrupt request is enabled. When written, enables the
24188                                                                      PMEVCNTR\<x\>_EL0 interrupt request. */
24189 #else /* Word 0 - Little Endian */
24190         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow interrupt request enable bit for
24191                                                                      PMEVCNTR\<x\>_EL0.
24192 
24193                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24194                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24195                                                                      AP_PMCR_EL0[N].
24196 
24197                                                                  Bits [30:N] are RAZ/WI.
24198 
24199                                                                  0 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24200                                                                      interrupt request is disabled. When written, has no effect.
24201                                                                  1 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24202                                                                      interrupt request is enabled. When written, enables the
24203                                                                      PMEVCNTR\<x\>_EL0 interrupt request. */
24204         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow interrupt request enable bit. Possible
24205                                                                      values are:
24206                                                                  0 = When read, means the cycle counter overflow interrupt request
24207                                                                      is disabled. When written, has no effect.
24208                                                                  1 = When read, means the cycle counter overflow interrupt request
24209                                                                      is enabled. When written, enables the cycle count overflow
24210                                                                      interrupt request. */
24211 #endif /* Word 0 - End */
24212     } s;
24213     /* struct bdk_ap_pmintenset_el1_s cn8; */
24214     struct bdk_ap_pmintenset_el1_cn9
24215     {
24216 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24217         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow interrupt request enable bit.
24218                                                                  0 = When read, means the cycle counter overflow interrupt request
24219                                                                      is disabled. When written, has no effect.
24220                                                                  1 = When read, means the cycle counter overflow interrupt request
24221                                                                      is enabled. When written, enables the cycle count overflow
24222                                                                      interrupt request. */
24223         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow interrupt request enable bit for
24224                                                                      PMEVCNTR\<x\>_EL0.
24225 
24226                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24227                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24228                                                                      AP_PMCR_EL0[N].
24229 
24230                                                                  Bits [30:N] are RAZ/WI.
24231 
24232                                                                  0 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24233                                                                      interrupt request is disabled. When written, has no effect.
24234                                                                  1 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24235                                                                      interrupt request is enabled. When written, enables the
24236                                                                      PMEVCNTR\<x\>_EL0 interrupt request. */
24237 #else /* Word 0 - Little Endian */
24238         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow interrupt request enable bit for
24239                                                                      PMEVCNTR\<x\>_EL0.
24240 
24241                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24242                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24243                                                                      AP_PMCR_EL0[N].
24244 
24245                                                                  Bits [30:N] are RAZ/WI.
24246 
24247                                                                  0 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24248                                                                      interrupt request is disabled. When written, has no effect.
24249                                                                  1 = When read, means that the PMEVCNTR\<x\>_EL0 event counter
24250                                                                      interrupt request is enabled. When written, enables the
24251                                                                      PMEVCNTR\<x\>_EL0 interrupt request. */
24252         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow interrupt request enable bit.
24253                                                                  0 = When read, means the cycle counter overflow interrupt request
24254                                                                      is disabled. When written, has no effect.
24255                                                                  1 = When read, means the cycle counter overflow interrupt request
24256                                                                      is enabled. When written, enables the cycle count overflow
24257                                                                      interrupt request. */
24258 #endif /* Word 0 - End */
24259     } cn9;
24260 };
24261 typedef union bdk_ap_pmintenset_el1 bdk_ap_pmintenset_el1_t;
24262 
24263 #define BDK_AP_PMINTENSET_EL1 BDK_AP_PMINTENSET_EL1_FUNC()
24264 static inline uint64_t BDK_AP_PMINTENSET_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMINTENSET_EL1_FUNC(void)24265 static inline uint64_t BDK_AP_PMINTENSET_EL1_FUNC(void)
24266 {
24267     return 0x300090e0100ll;
24268 }
24269 
24270 #define typedef_BDK_AP_PMINTENSET_EL1 bdk_ap_pmintenset_el1_t
24271 #define bustype_BDK_AP_PMINTENSET_EL1 BDK_CSR_TYPE_SYSREG
24272 #define basename_BDK_AP_PMINTENSET_EL1 "AP_PMINTENSET_EL1"
24273 #define busnum_BDK_AP_PMINTENSET_EL1 0
24274 #define arguments_BDK_AP_PMINTENSET_EL1 -1,-1,-1,-1
24275 
24276 /**
24277  * Register (SYSREG) ap_pmovsclr_el0
24278  *
24279  * AP Performance Monitors Overflow Flag Status Clear Register
24280  * Contains the state of the overflow bit for the Cycle Count
24281  *     Register, AP_PMCCNTR_EL0, and each of the implemented event
24282  *     counters PMEVCNTR\<x\>. Writing to this register clears these
24283  *     bits.
24284  */
24285 union bdk_ap_pmovsclr_el0
24286 {
24287     uint32_t u;
24288     struct bdk_ap_pmovsclr_el0_s
24289     {
24290 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24291         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow bit.
24292                                                                  AP_PMCR_EL0[LC] is used to control from which bit of AP_PMCCNTR_EL0
24293                                                                      (bit 31 or bit 63) an overflow is detected.
24294                                                                  0 = When read, means the cycle counter has not overflowed. When
24295                                                                      written, has no effect.
24296                                                                  1 = When read, means the cycle counter has overflowed. When
24297                                                                      written, clears the overflow bit to 0. */
24298         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow clear bit for PMEVCNTR\<x\>.
24299                                                                  Bits [30:N] are RAZ/WI.
24300                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24301                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24302                                                                      AP_PMCR_EL0[N].
24303 
24304                                                                  0 = When read, means that PMEVCNTR\<x\> has not overflowed. When
24305                                                                      written, has no effect.
24306                                                                  1 = When read, means that PMEVCNTR\<x\> has overflowed. When
24307                                                                      written, clears the PMEVCNTR\<x\> overflow bit to 0. */
24308 #else /* Word 0 - Little Endian */
24309         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow clear bit for PMEVCNTR\<x\>.
24310                                                                  Bits [30:N] are RAZ/WI.
24311                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24312                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24313                                                                      AP_PMCR_EL0[N].
24314 
24315                                                                  0 = When read, means that PMEVCNTR\<x\> has not overflowed. When
24316                                                                      written, has no effect.
24317                                                                  1 = When read, means that PMEVCNTR\<x\> has overflowed. When
24318                                                                      written, clears the PMEVCNTR\<x\> overflow bit to 0. */
24319         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow bit.
24320                                                                  AP_PMCR_EL0[LC] is used to control from which bit of AP_PMCCNTR_EL0
24321                                                                      (bit 31 or bit 63) an overflow is detected.
24322                                                                  0 = When read, means the cycle counter has not overflowed. When
24323                                                                      written, has no effect.
24324                                                                  1 = When read, means the cycle counter has overflowed. When
24325                                                                      written, clears the overflow bit to 0. */
24326 #endif /* Word 0 - End */
24327     } s;
24328     /* struct bdk_ap_pmovsclr_el0_s cn; */
24329 };
24330 typedef union bdk_ap_pmovsclr_el0 bdk_ap_pmovsclr_el0_t;
24331 
24332 #define BDK_AP_PMOVSCLR_EL0 BDK_AP_PMOVSCLR_EL0_FUNC()
24333 static inline uint64_t BDK_AP_PMOVSCLR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMOVSCLR_EL0_FUNC(void)24334 static inline uint64_t BDK_AP_PMOVSCLR_EL0_FUNC(void)
24335 {
24336     return 0x303090c0300ll;
24337 }
24338 
24339 #define typedef_BDK_AP_PMOVSCLR_EL0 bdk_ap_pmovsclr_el0_t
24340 #define bustype_BDK_AP_PMOVSCLR_EL0 BDK_CSR_TYPE_SYSREG
24341 #define basename_BDK_AP_PMOVSCLR_EL0 "AP_PMOVSCLR_EL0"
24342 #define busnum_BDK_AP_PMOVSCLR_EL0 0
24343 #define arguments_BDK_AP_PMOVSCLR_EL0 -1,-1,-1,-1
24344 
24345 /**
24346  * Register (SYSREG) ap_pmovsset_el0
24347  *
24348  * AP Performance Monitors Overflow Flag Status Set Register
24349  * Sets the state of the overflow bit for the Cycle Count
24350  *     Register, AP_PMCCNTR_EL0, and each of the implemented event
24351  *     counters PMEVCNTR\<x\>.
24352  */
24353 union bdk_ap_pmovsset_el0
24354 {
24355     uint32_t u;
24356     struct bdk_ap_pmovsset_el0_s
24357     {
24358 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24359         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow bit.
24360                                                                  0 = When read, means the cycle counter has not overflowed. When
24361                                                                      written, has no effect.
24362                                                                  1 = When read, means the cycle counter has overflowed. When
24363                                                                      written, sets the overflow bit to 1. */
24364         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow set bit for PMEVCNTR\<x\>.
24365                                                                  Bits [30:N] are RAZ/WI.
24366                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24367                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24368                                                                      AP_PMCR_EL0[N].
24369                                                                  0 = When read, means that PMEVCNTR\<x\> has not overflowed. When
24370                                                                      written, has no effect.
24371                                                                  1 = When read, means that PMEVCNTR\<x\> has overflowed. When
24372                                                                      written, sets the PMEVCNTR\<x\> overflow bit to 1. */
24373 #else /* Word 0 - Little Endian */
24374         uint32_t p                     : 31; /**< [ 30:  0](R/W) Event counter overflow set bit for PMEVCNTR\<x\>.
24375                                                                  Bits [30:N] are RAZ/WI.
24376                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
24377                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in
24378                                                                      AP_PMCR_EL0[N].
24379                                                                  0 = When read, means that PMEVCNTR\<x\> has not overflowed. When
24380                                                                      written, has no effect.
24381                                                                  1 = When read, means that PMEVCNTR\<x\> has overflowed. When
24382                                                                      written, sets the PMEVCNTR\<x\> overflow bit to 1. */
24383         uint32_t cc                    : 1;  /**< [ 31: 31](R/W) AP_PMCCNTR_EL0 overflow bit.
24384                                                                  0 = When read, means the cycle counter has not overflowed. When
24385                                                                      written, has no effect.
24386                                                                  1 = When read, means the cycle counter has overflowed. When
24387                                                                      written, sets the overflow bit to 1. */
24388 #endif /* Word 0 - End */
24389     } s;
24390     /* struct bdk_ap_pmovsset_el0_s cn; */
24391 };
24392 typedef union bdk_ap_pmovsset_el0 bdk_ap_pmovsset_el0_t;
24393 
24394 #define BDK_AP_PMOVSSET_EL0 BDK_AP_PMOVSSET_EL0_FUNC()
24395 static inline uint64_t BDK_AP_PMOVSSET_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMOVSSET_EL0_FUNC(void)24396 static inline uint64_t BDK_AP_PMOVSSET_EL0_FUNC(void)
24397 {
24398     return 0x303090e0300ll;
24399 }
24400 
24401 #define typedef_BDK_AP_PMOVSSET_EL0 bdk_ap_pmovsset_el0_t
24402 #define bustype_BDK_AP_PMOVSSET_EL0 BDK_CSR_TYPE_SYSREG
24403 #define basename_BDK_AP_PMOVSSET_EL0 "AP_PMOVSSET_EL0"
24404 #define busnum_BDK_AP_PMOVSSET_EL0 0
24405 #define arguments_BDK_AP_PMOVSSET_EL0 -1,-1,-1,-1
24406 
24407 /**
24408  * Register (SYSREG) ap_pmscr_el1
24409  *
24410  * AP Statistical Profiling Control Register
24411  * Provides EL1 controls for Statistical Profiling..
24412  */
24413 union bdk_ap_pmscr_el1
24414 {
24415     uint64_t u;
24416     struct bdk_ap_pmscr_el1_s
24417     {
24418 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24419         uint64_t reserved_7_63         : 57;
24420         uint64_t pct                   : 1;  /**< [  6:  6](R/W) Physical timestamp.
24421                                                                    0 = Virtual counter, CNTVCT_EL0, is collected.
24422                                                                    1 = Physical counter, CNTPCT_EL0, is collected.
24423 
24424                                                                  Ignored when the TS bit is 0, at EL2, and in nonsecure state when HCR_EL2[TGE] = 1.
24425                                                                  RES0 in nonsecure state when MDCR_EL2[E2DB] != 0x0 and PMSCR_EL2[PCT ]= 0. */
24426         uint64_t ts                    : 1;  /**< [  5:  5](R/W) Timestamp enable.
24427                                                                    0 = Timestamp sampling disabled.
24428                                                                    1 = Timestamp sampling enabled.
24429 
24430                                                                  Ignored at EL2 and in nonsecure state when HCR_EL2[TGE] = 1. */
24431         uint64_t pa                    : 1;  /**< [  4:  4](R/W) Physical address sample enable.
24432                                                                    0 = Physical addresses are not collected.
24433                                                                    1 = Physical addresses are collected.
24434 
24435                                                                  Ignored at EL2 and in nonsecure state when HCR_EL2[TGE] = 1.
24436                                                                  RES0 in nonsecure state when MDCR_EL2[E2DB] = 0x0 and PMSCR_EL2[PA] = 0. */
24437         uint64_t cx                    : 1;  /**< [  3:  3](R/W) CONTEXTIDR_EL1 sample enable.
24438                                                                    0 = CONTEXTIDR_EL1 is not collected.
24439                                                                    1 = CONTEXTIDR_EL1 is collected.
24440 
24441                                                                  RES0 at EL2 and in nonsecure state when HCR_EL2.TGE = 1. */
24442         uint64_t reserved_2            : 1;
24443         uint64_t e1spe                 : 1;  /**< [  1:  1](R/W) EL1 statistical profiling enable.
24444                                                                    0 = Sampling disabled at EL1.
24445                                                                    1 = Sampling enabled at EL1.
24446 
24447                                                                  Ignored in nonsecure state when HCR_EL2[TGE] = 1. */
24448         uint64_t e0spe                 : 1;  /**< [  0:  0](R/W) EL0 statistical profiling enable.
24449                                                                    0 = Sampling disabled at EL0 when HCR_EL2[TGE] = 0.
24450                                                                    1 = Sampling enabled at EL0 when HCR_EL2[TGE] = 0.
24451 
24452                                                                  Ignored in nonsecure state when HCR_EL2[TGE] = 1. */
24453 #else /* Word 0 - Little Endian */
24454         uint64_t e0spe                 : 1;  /**< [  0:  0](R/W) EL0 statistical profiling enable.
24455                                                                    0 = Sampling disabled at EL0 when HCR_EL2[TGE] = 0.
24456                                                                    1 = Sampling enabled at EL0 when HCR_EL2[TGE] = 0.
24457 
24458                                                                  Ignored in nonsecure state when HCR_EL2[TGE] = 1. */
24459         uint64_t e1spe                 : 1;  /**< [  1:  1](R/W) EL1 statistical profiling enable.
24460                                                                    0 = Sampling disabled at EL1.
24461                                                                    1 = Sampling enabled at EL1.
24462 
24463                                                                  Ignored in nonsecure state when HCR_EL2[TGE] = 1. */
24464         uint64_t reserved_2            : 1;
24465         uint64_t cx                    : 1;  /**< [  3:  3](R/W) CONTEXTIDR_EL1 sample enable.
24466                                                                    0 = CONTEXTIDR_EL1 is not collected.
24467                                                                    1 = CONTEXTIDR_EL1 is collected.
24468 
24469                                                                  RES0 at EL2 and in nonsecure state when HCR_EL2.TGE = 1. */
24470         uint64_t pa                    : 1;  /**< [  4:  4](R/W) Physical address sample enable.
24471                                                                    0 = Physical addresses are not collected.
24472                                                                    1 = Physical addresses are collected.
24473 
24474                                                                  Ignored at EL2 and in nonsecure state when HCR_EL2[TGE] = 1.
24475                                                                  RES0 in nonsecure state when MDCR_EL2[E2DB] = 0x0 and PMSCR_EL2[PA] = 0. */
24476         uint64_t ts                    : 1;  /**< [  5:  5](R/W) Timestamp enable.
24477                                                                    0 = Timestamp sampling disabled.
24478                                                                    1 = Timestamp sampling enabled.
24479 
24480                                                                  Ignored at EL2 and in nonsecure state when HCR_EL2[TGE] = 1. */
24481         uint64_t pct                   : 1;  /**< [  6:  6](R/W) Physical timestamp.
24482                                                                    0 = Virtual counter, CNTVCT_EL0, is collected.
24483                                                                    1 = Physical counter, CNTPCT_EL0, is collected.
24484 
24485                                                                  Ignored when the TS bit is 0, at EL2, and in nonsecure state when HCR_EL2[TGE] = 1.
24486                                                                  RES0 in nonsecure state when MDCR_EL2[E2DB] != 0x0 and PMSCR_EL2[PCT ]= 0. */
24487         uint64_t reserved_7_63         : 57;
24488 #endif /* Word 0 - End */
24489     } s;
24490     /* struct bdk_ap_pmscr_el1_s cn; */
24491 };
24492 typedef union bdk_ap_pmscr_el1 bdk_ap_pmscr_el1_t;
24493 
24494 #define BDK_AP_PMSCR_EL1 BDK_AP_PMSCR_EL1_FUNC()
24495 static inline uint64_t BDK_AP_PMSCR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSCR_EL1_FUNC(void)24496 static inline uint64_t BDK_AP_PMSCR_EL1_FUNC(void)
24497 {
24498     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
24499         return 0x30009090000ll;
24500     __bdk_csr_fatal("AP_PMSCR_EL1", 0, 0, 0, 0, 0);
24501 }
24502 
24503 #define typedef_BDK_AP_PMSCR_EL1 bdk_ap_pmscr_el1_t
24504 #define bustype_BDK_AP_PMSCR_EL1 BDK_CSR_TYPE_SYSREG
24505 #define basename_BDK_AP_PMSCR_EL1 "AP_PMSCR_EL1"
24506 #define busnum_BDK_AP_PMSCR_EL1 0
24507 #define arguments_BDK_AP_PMSCR_EL1 -1,-1,-1,-1
24508 
24509 /**
24510  * Register (SYSREG) ap_pmscr_el12
24511  *
24512  * AP Statistical Profiling Control Register
24513  * Alias of AP_PMSCR_EL1 when accessed at EL2 and AP_HCR_EL2[E2H] is set.
24514  */
24515 union bdk_ap_pmscr_el12
24516 {
24517     uint64_t u;
24518     struct bdk_ap_pmscr_el12_s
24519     {
24520 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24521         uint64_t reserved_0_63         : 64;
24522 #else /* Word 0 - Little Endian */
24523         uint64_t reserved_0_63         : 64;
24524 #endif /* Word 0 - End */
24525     } s;
24526     /* struct bdk_ap_pmscr_el12_s cn; */
24527 };
24528 typedef union bdk_ap_pmscr_el12 bdk_ap_pmscr_el12_t;
24529 
24530 #define BDK_AP_PMSCR_EL12 BDK_AP_PMSCR_EL12_FUNC()
24531 static inline uint64_t BDK_AP_PMSCR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSCR_EL12_FUNC(void)24532 static inline uint64_t BDK_AP_PMSCR_EL12_FUNC(void)
24533 {
24534     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
24535         return 0x30509090000ll;
24536     __bdk_csr_fatal("AP_PMSCR_EL12", 0, 0, 0, 0, 0);
24537 }
24538 
24539 #define typedef_BDK_AP_PMSCR_EL12 bdk_ap_pmscr_el12_t
24540 #define bustype_BDK_AP_PMSCR_EL12 BDK_CSR_TYPE_SYSREG
24541 #define basename_BDK_AP_PMSCR_EL12 "AP_PMSCR_EL12"
24542 #define busnum_BDK_AP_PMSCR_EL12 0
24543 #define arguments_BDK_AP_PMSCR_EL12 -1,-1,-1,-1
24544 
24545 /**
24546  * Register (SYSREG) ap_pmscr_el2
24547  *
24548  * AP Statistical Profiling Control Register
24549  * Provides EL2 controls for Statistical Profiling.
24550  */
24551 union bdk_ap_pmscr_el2
24552 {
24553     uint64_t u;
24554     struct bdk_ap_pmscr_el2_s
24555     {
24556 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24557         uint64_t reserved_7_63         : 57;
24558         uint64_t pct                   : 1;  /**< [  6:  6](R/W) Physical Timestamp.
24559                                                                    0 = Virtual counter, CNTVCT_EL0, is collected.
24560                                                                    1 = Physical counter, CNTPCT_EL0, is collected.
24561 
24562                                                                  Ignored when the TS bit is 0 and in Secure state.
24563                                                                  If MDCR_EL2.E2DB != 0b00, this bit is combined with PMSCR_EL1.PCT to determine which
24564                                                                  counter is collected. See CollectTimeStamp.
24565                                                                  If EL2 is not implemented, the PE behaves as if PCT == 1, other than for a direct read of
24566                                                                  the register. */
24567         uint64_t ts                    : 1;  /**< [  5:  5](R/W) Timestamp Enable.
24568                                                                    0 = Timestamp sampling disabled.
24569                                                                    1 = Timestamp sampling enabled.
24570 
24571                                                                  Ignored in Secure state, and at EL1 and EL0 when HCR_EL2.TGE == 0.
24572                                                                  See CollectTimeStamp. */
24573         uint64_t pa                    : 1;  /**< [  4:  4](R/W) Physical Address Sample Enable.
24574                                                                    0 = Physical addresses are not collected.
24575                                                                    1 = Physical addresses are collected.
24576 
24577                                                                  Ignored when the TS bit is 0 and in Secure state.
24578                                                                  If MDCR_EL2.E2DB != 0b00, this bit is combined with PMSCR_EL1.PA to determine which
24579                                                                  counter is collected. See CollectPhysicalAddress.
24580                                                                  If EL2 is not implemented, the PE behaves as if PA == 1, other than for a direct read of
24581                                                                  the register. */
24582         uint64_t cx                    : 1;  /**< [  3:  3](R/W) CONTEXTIDR_EL2 Sample Enable.
24583                                                                    0 = CONTEXTIDR_EL2 is not collected.
24584                                                                    1 = CONTEXTIDR_EL2 is collected.
24585 
24586                                                                  RES0 in secure state. */
24587         uint64_t reserved_2            : 1;
24588         uint64_t e2spe                 : 1;  /**< [  1:  1](R/W) EL2 statistical profiling enable.
24589                                                                    0 = Sampling disabled at EL2.
24590                                                                    1 = Sampling enabled at EL2.
24591 
24592                                                                  RES0 if MDCR_EL2[E2PB] != 0x0. Ignored in Secure state. */
24593         uint64_t e0hspe                : 1;  /**< [  0:  0](R/W) EL0 statistical profiling enable.
24594                                                                    0 = Sampling disabled at EL0 when HCR_EL2.TGE == 1.
24595                                                                    1 = Sampling enabled at EL0 when HCR_EL2.TGE == 1.
24596 
24597                                                                  RES0 if MDCR_EL2.E2PB != 0x0. Ignored in Secure state and when HCR_EL2[TGE] = 0. */
24598 #else /* Word 0 - Little Endian */
24599         uint64_t e0hspe                : 1;  /**< [  0:  0](R/W) EL0 statistical profiling enable.
24600                                                                    0 = Sampling disabled at EL0 when HCR_EL2.TGE == 1.
24601                                                                    1 = Sampling enabled at EL0 when HCR_EL2.TGE == 1.
24602 
24603                                                                  RES0 if MDCR_EL2.E2PB != 0x0. Ignored in Secure state and when HCR_EL2[TGE] = 0. */
24604         uint64_t e2spe                 : 1;  /**< [  1:  1](R/W) EL2 statistical profiling enable.
24605                                                                    0 = Sampling disabled at EL2.
24606                                                                    1 = Sampling enabled at EL2.
24607 
24608                                                                  RES0 if MDCR_EL2[E2PB] != 0x0. Ignored in Secure state. */
24609         uint64_t reserved_2            : 1;
24610         uint64_t cx                    : 1;  /**< [  3:  3](R/W) CONTEXTIDR_EL2 Sample Enable.
24611                                                                    0 = CONTEXTIDR_EL2 is not collected.
24612                                                                    1 = CONTEXTIDR_EL2 is collected.
24613 
24614                                                                  RES0 in secure state. */
24615         uint64_t pa                    : 1;  /**< [  4:  4](R/W) Physical Address Sample Enable.
24616                                                                    0 = Physical addresses are not collected.
24617                                                                    1 = Physical addresses are collected.
24618 
24619                                                                  Ignored when the TS bit is 0 and in Secure state.
24620                                                                  If MDCR_EL2.E2DB != 0b00, this bit is combined with PMSCR_EL1.PA to determine which
24621                                                                  counter is collected. See CollectPhysicalAddress.
24622                                                                  If EL2 is not implemented, the PE behaves as if PA == 1, other than for a direct read of
24623                                                                  the register. */
24624         uint64_t ts                    : 1;  /**< [  5:  5](R/W) Timestamp Enable.
24625                                                                    0 = Timestamp sampling disabled.
24626                                                                    1 = Timestamp sampling enabled.
24627 
24628                                                                  Ignored in Secure state, and at EL1 and EL0 when HCR_EL2.TGE == 0.
24629                                                                  See CollectTimeStamp. */
24630         uint64_t pct                   : 1;  /**< [  6:  6](R/W) Physical Timestamp.
24631                                                                    0 = Virtual counter, CNTVCT_EL0, is collected.
24632                                                                    1 = Physical counter, CNTPCT_EL0, is collected.
24633 
24634                                                                  Ignored when the TS bit is 0 and in Secure state.
24635                                                                  If MDCR_EL2.E2DB != 0b00, this bit is combined with PMSCR_EL1.PCT to determine which
24636                                                                  counter is collected. See CollectTimeStamp.
24637                                                                  If EL2 is not implemented, the PE behaves as if PCT == 1, other than for a direct read of
24638                                                                  the register. */
24639         uint64_t reserved_7_63         : 57;
24640 #endif /* Word 0 - End */
24641     } s;
24642     /* struct bdk_ap_pmscr_el2_s cn; */
24643 };
24644 typedef union bdk_ap_pmscr_el2 bdk_ap_pmscr_el2_t;
24645 
24646 #define BDK_AP_PMSCR_EL2 BDK_AP_PMSCR_EL2_FUNC()
24647 static inline uint64_t BDK_AP_PMSCR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSCR_EL2_FUNC(void)24648 static inline uint64_t BDK_AP_PMSCR_EL2_FUNC(void)
24649 {
24650     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
24651         return 0x30409090000ll;
24652     __bdk_csr_fatal("AP_PMSCR_EL2", 0, 0, 0, 0, 0);
24653 }
24654 
24655 #define typedef_BDK_AP_PMSCR_EL2 bdk_ap_pmscr_el2_t
24656 #define bustype_BDK_AP_PMSCR_EL2 BDK_CSR_TYPE_SYSREG
24657 #define basename_BDK_AP_PMSCR_EL2 "AP_PMSCR_EL2"
24658 #define busnum_BDK_AP_PMSCR_EL2 0
24659 #define arguments_BDK_AP_PMSCR_EL2 -1,-1,-1,-1
24660 
24661 /**
24662  * Register (SYSREG) ap_pmselr_el0
24663  *
24664  * AP Performance Monitors Event Counter Selection Register
24665  * Selects the current event counter PMEVCNTR\<x\> or the cycle
24666  *     counter, CCNT.
24667  */
24668 union bdk_ap_pmselr_el0
24669 {
24670     uint32_t u;
24671     struct bdk_ap_pmselr_el0_s
24672     {
24673 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24674         uint32_t reserved_5_31         : 27;
24675         uint32_t sel                   : 5;  /**< [  4:  0](R/W) Selects event counter, PMEVCNTR\<x\>, where x is the value held
24676                                                                      in this field. This value identifies which event counter is
24677                                                                      accessed when a subsequent access to AP_PMXEVTYPER_EL0 or
24678                                                                      AP_PMXEVCNTR_EL0 occurs.
24679                                                                  When AP_PMSELR_EL0[SEL] is 0b11111:
24680 
24681                                                                   A read of the AP_PMXEVTYPER_EL0 returns the value of
24682                                                                      AP_PMCCFILTR_EL0.
24683 
24684                                                                   A write of the AP_PMXEVTYPER_EL0 writes to AP_PMCCFILTR_EL0.
24685 
24686                                                                   A read or write of AP_PMXEVCNTR_EL0 has CONSTRAINED
24687                                                                      UNPREDICTABLE effects, that can be one of the following:
24688                                                                      Access to AP_PMXEVCNTR_EL0 is UNdefined.  Access to AP_PMXEVCNTR_EL0
24689                                                                      behaves as a NOP.  Access to AP_PMXEVCNTR_EL0 behaves as if the
24690                                                                      register is RAZ/WI.  Access to AP_PMXEVCNTR_EL0 behaves as if the
24691                                                                      AP_PMSELR_EL0[SEL]     field contains an UNKNOWN value.
24692 
24693                                                                  If this field is set to a value greater than or equal to the
24694                                                                      number of implemented counters, but not equal to 31, the
24695                                                                      results of access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 are
24696                                                                      CONSTRAINED UNPREDICTABLE, and can be one of the following:
24697 
24698                                                                   Access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 is UNdefined.
24699 
24700                                                                   Access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 behaves as a NOP.
24701 
24702                                                                   Access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 behaves as if the
24703                                                                      register is RAZ/WI.
24704 
24705                                                                   Access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 behaves as if the
24706                                                                      AP_PMSELR_EL0[SEL] field contains an UNKNOWN value.
24707 
24708                                                                   Access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 behaves as if the
24709                                                                      AP_PMSELR_EL0[SEL] field contains0b11111 */
24710 #else /* Word 0 - Little Endian */
24711         uint32_t sel                   : 5;  /**< [  4:  0](R/W) Selects event counter, PMEVCNTR\<x\>, where x is the value held
24712                                                                      in this field. This value identifies which event counter is
24713                                                                      accessed when a subsequent access to AP_PMXEVTYPER_EL0 or
24714                                                                      AP_PMXEVCNTR_EL0 occurs.
24715                                                                  When AP_PMSELR_EL0[SEL] is 0b11111:
24716 
24717                                                                   A read of the AP_PMXEVTYPER_EL0 returns the value of
24718                                                                      AP_PMCCFILTR_EL0.
24719 
24720                                                                   A write of the AP_PMXEVTYPER_EL0 writes to AP_PMCCFILTR_EL0.
24721 
24722                                                                   A read or write of AP_PMXEVCNTR_EL0 has CONSTRAINED
24723                                                                      UNPREDICTABLE effects, that can be one of the following:
24724                                                                      Access to AP_PMXEVCNTR_EL0 is UNdefined.  Access to AP_PMXEVCNTR_EL0
24725                                                                      behaves as a NOP.  Access to AP_PMXEVCNTR_EL0 behaves as if the
24726                                                                      register is RAZ/WI.  Access to AP_PMXEVCNTR_EL0 behaves as if the
24727                                                                      AP_PMSELR_EL0[SEL]     field contains an UNKNOWN value.
24728 
24729                                                                  If this field is set to a value greater than or equal to the
24730                                                                      number of implemented counters, but not equal to 31, the
24731                                                                      results of access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 are
24732                                                                      CONSTRAINED UNPREDICTABLE, and can be one of the following:
24733 
24734                                                                   Access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 is UNdefined.
24735 
24736                                                                   Access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 behaves as a NOP.
24737 
24738                                                                   Access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 behaves as if the
24739                                                                      register is RAZ/WI.
24740 
24741                                                                   Access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 behaves as if the
24742                                                                      AP_PMSELR_EL0[SEL] field contains an UNKNOWN value.
24743 
24744                                                                   Access to AP_PMXEVTYPER_EL0 or AP_PMXEVCNTR_EL0 behaves as if the
24745                                                                      AP_PMSELR_EL0[SEL] field contains0b11111 */
24746         uint32_t reserved_5_31         : 27;
24747 #endif /* Word 0 - End */
24748     } s;
24749     /* struct bdk_ap_pmselr_el0_s cn; */
24750 };
24751 typedef union bdk_ap_pmselr_el0 bdk_ap_pmselr_el0_t;
24752 
24753 #define BDK_AP_PMSELR_EL0 BDK_AP_PMSELR_EL0_FUNC()
24754 static inline uint64_t BDK_AP_PMSELR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSELR_EL0_FUNC(void)24755 static inline uint64_t BDK_AP_PMSELR_EL0_FUNC(void)
24756 {
24757     return 0x303090c0500ll;
24758 }
24759 
24760 #define typedef_BDK_AP_PMSELR_EL0 bdk_ap_pmselr_el0_t
24761 #define bustype_BDK_AP_PMSELR_EL0 BDK_CSR_TYPE_SYSREG
24762 #define basename_BDK_AP_PMSELR_EL0 "AP_PMSELR_EL0"
24763 #define busnum_BDK_AP_PMSELR_EL0 0
24764 #define arguments_BDK_AP_PMSELR_EL0 -1,-1,-1,-1
24765 
24766 /**
24767  * Register (SYSREG) ap_pmsevfr_el1
24768  *
24769  * AP Sampling Event Filter Register
24770  * Controls sample filtering by events. The overall filter is the logical AND of these filters.
24771  * For example, if
24772  * E[3] and E[5] are both set to 1, only samples that have both event 3 (Level 1 unified or data
24773  * cache
24774  * refill) and event 5 set (TLB walk) are recorded.
24775  */
24776 union bdk_ap_pmsevfr_el1
24777 {
24778     uint64_t u;
24779     struct bdk_ap_pmsevfr_el1_s
24780     {
24781 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24782         uint64_t e_48_63               : 16; /**< [ 63: 48](R/W) E[\<n\>] is the event filter for event \<n\>. If event \<n\> is not implemented, or filtering on
24783                                                                  event \<n\> is not supported, the corresponding bit is RES0.
24784                                                                    0 = Event \<n\> is ignored.
24785                                                                    1 = Record samples that have event \<n\> == 1.
24786 
24787                                                                  Ignored if PMSCR_EL1[FE] = 0.
24788 
24789                                                                  An implementation defined event might be recorded as a multi-bit field. In this case, if
24790                                                                  the corresponding bits of PMSEVFR_EL1 define an implementation defined filter for the
24791                                                                  event. */
24792         uint64_t reserved_32_47        : 16;
24793         uint64_t e_24_31               : 8;  /**< [ 31: 24](R/W) E[\<n\>] is the event filter for event \<n\>. If event \<n\> is not implemented, or filtering on
24794                                                                  event \<n\> is not supported, the corresponding bit is RES0.
24795                                                                    0 = Event \<n\> is ignored.
24796                                                                    1 = Record samples that have event \<n\> == 1.
24797 
24798                                                                  Ignored if PMSCR_EL1[FE] = 0.
24799 
24800                                                                  An implementation defined event might be recorded as a multi-bit field. In this case, if
24801                                                                  the corresponding bits of PMSEVFR_EL1 define an implementation defined filter for the
24802                                                                  event. */
24803         uint64_t reserved_16_23        : 8;
24804         uint64_t e_12_15               : 4;  /**< [ 15: 12](R/W) E[\<n\>] is the event filter for event \<n\>. If event \<n\> is not implemented, or filtering on
24805                                                                  event \<n\> is not supported, the corresponding bit is RES0.
24806                                                                    0 = Event \<n\> is ignored.
24807                                                                    1 = Record samples that have event \<n\> = 1.
24808 
24809                                                                  Ignored if PMSCR_EL1[FE] = 0.
24810 
24811                                                                  An implementation defined event might be recorded as a multi-bit field. In this case, if
24812                                                                  the corresponding bits of PMSEVFR_EL1 define an implementation defined filter for the
24813                                                                  event. */
24814         uint64_t reserved_8_11         : 4;
24815         uint64_t e_7                   : 1;  /**< [  7:  7](R/W) Mispredicted.
24816                                                                    0 = Mispredicted event is ignored.
24817                                                                    1 = Record samples that have event 7 (Mispredicted) == 1.
24818 
24819                                                                  Ignored if PMSCR_EL1[FE] = 0. */
24820         uint64_t reserved_6            : 1;
24821         uint64_t e_5                   : 1;  /**< [  5:  5](R/W) TLB walk.
24822                                                                    0 = TLB walk event is ignored.
24823                                                                    1 = Record samples that have event 5 (TLB walk) = 1.
24824 
24825                                                                  Ignored if PMSCR_EL1[FE] = 0. */
24826         uint64_t reserved_4            : 1;
24827         uint64_t e_3                   : 1;  /**< [  3:  3](R/W) Level 1 data or unified cache refill.
24828                                                                    0 = Level 1 data or unified cache refill event is ignored.
24829                                                                    1 = Record samples that have event 3 (Level 1 data or unified cache refill) == 1.
24830 
24831                                                                  Ignored if PMSCR_EL1[FE] = 0. */
24832         uint64_t reserved_2            : 1;
24833         uint64_t e_1                   : 1;  /**< [  1:  1](R/W) Architecturally retired.
24834                                                                    0 = Architecturally retired event is ignored.
24835                                                                    1 = Record samples that have event 1 (Architecturally retired) == 1.
24836 
24837                                                                  Ignored if PMSCR_EL1[FE] = 0.
24838 
24839                                                                  If the PE does not support sampling of speculative instructions, E[1] is RES1. */
24840         uint64_t reserved_0            : 1;
24841 #else /* Word 0 - Little Endian */
24842         uint64_t reserved_0            : 1;
24843         uint64_t e_1                   : 1;  /**< [  1:  1](R/W) Architecturally retired.
24844                                                                    0 = Architecturally retired event is ignored.
24845                                                                    1 = Record samples that have event 1 (Architecturally retired) == 1.
24846 
24847                                                                  Ignored if PMSCR_EL1[FE] = 0.
24848 
24849                                                                  If the PE does not support sampling of speculative instructions, E[1] is RES1. */
24850         uint64_t reserved_2            : 1;
24851         uint64_t e_3                   : 1;  /**< [  3:  3](R/W) Level 1 data or unified cache refill.
24852                                                                    0 = Level 1 data or unified cache refill event is ignored.
24853                                                                    1 = Record samples that have event 3 (Level 1 data or unified cache refill) == 1.
24854 
24855                                                                  Ignored if PMSCR_EL1[FE] = 0. */
24856         uint64_t reserved_4            : 1;
24857         uint64_t e_5                   : 1;  /**< [  5:  5](R/W) TLB walk.
24858                                                                    0 = TLB walk event is ignored.
24859                                                                    1 = Record samples that have event 5 (TLB walk) = 1.
24860 
24861                                                                  Ignored if PMSCR_EL1[FE] = 0. */
24862         uint64_t reserved_6            : 1;
24863         uint64_t e_7                   : 1;  /**< [  7:  7](R/W) Mispredicted.
24864                                                                    0 = Mispredicted event is ignored.
24865                                                                    1 = Record samples that have event 7 (Mispredicted) == 1.
24866 
24867                                                                  Ignored if PMSCR_EL1[FE] = 0. */
24868         uint64_t reserved_8_11         : 4;
24869         uint64_t e_12_15               : 4;  /**< [ 15: 12](R/W) E[\<n\>] is the event filter for event \<n\>. If event \<n\> is not implemented, or filtering on
24870                                                                  event \<n\> is not supported, the corresponding bit is RES0.
24871                                                                    0 = Event \<n\> is ignored.
24872                                                                    1 = Record samples that have event \<n\> = 1.
24873 
24874                                                                  Ignored if PMSCR_EL1[FE] = 0.
24875 
24876                                                                  An implementation defined event might be recorded as a multi-bit field. In this case, if
24877                                                                  the corresponding bits of PMSEVFR_EL1 define an implementation defined filter for the
24878                                                                  event. */
24879         uint64_t reserved_16_23        : 8;
24880         uint64_t e_24_31               : 8;  /**< [ 31: 24](R/W) E[\<n\>] is the event filter for event \<n\>. If event \<n\> is not implemented, or filtering on
24881                                                                  event \<n\> is not supported, the corresponding bit is RES0.
24882                                                                    0 = Event \<n\> is ignored.
24883                                                                    1 = Record samples that have event \<n\> == 1.
24884 
24885                                                                  Ignored if PMSCR_EL1[FE] = 0.
24886 
24887                                                                  An implementation defined event might be recorded as a multi-bit field. In this case, if
24888                                                                  the corresponding bits of PMSEVFR_EL1 define an implementation defined filter for the
24889                                                                  event. */
24890         uint64_t reserved_32_47        : 16;
24891         uint64_t e_48_63               : 16; /**< [ 63: 48](R/W) E[\<n\>] is the event filter for event \<n\>. If event \<n\> is not implemented, or filtering on
24892                                                                  event \<n\> is not supported, the corresponding bit is RES0.
24893                                                                    0 = Event \<n\> is ignored.
24894                                                                    1 = Record samples that have event \<n\> == 1.
24895 
24896                                                                  Ignored if PMSCR_EL1[FE] = 0.
24897 
24898                                                                  An implementation defined event might be recorded as a multi-bit field. In this case, if
24899                                                                  the corresponding bits of PMSEVFR_EL1 define an implementation defined filter for the
24900                                                                  event. */
24901 #endif /* Word 0 - End */
24902     } s;
24903     /* struct bdk_ap_pmsevfr_el1_s cn; */
24904 };
24905 typedef union bdk_ap_pmsevfr_el1 bdk_ap_pmsevfr_el1_t;
24906 
24907 #define BDK_AP_PMSEVFR_EL1 BDK_AP_PMSEVFR_EL1_FUNC()
24908 static inline uint64_t BDK_AP_PMSEVFR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSEVFR_EL1_FUNC(void)24909 static inline uint64_t BDK_AP_PMSEVFR_EL1_FUNC(void)
24910 {
24911     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
24912         return 0x30009090500ll;
24913     __bdk_csr_fatal("AP_PMSEVFR_EL1", 0, 0, 0, 0, 0);
24914 }
24915 
24916 #define typedef_BDK_AP_PMSEVFR_EL1 bdk_ap_pmsevfr_el1_t
24917 #define bustype_BDK_AP_PMSEVFR_EL1 BDK_CSR_TYPE_SYSREG
24918 #define basename_BDK_AP_PMSEVFR_EL1 "AP_PMSEVFR_EL1"
24919 #define busnum_BDK_AP_PMSEVFR_EL1 0
24920 #define arguments_BDK_AP_PMSEVFR_EL1 -1,-1,-1,-1
24921 
24922 /**
24923  * Register (SYSREG) ap_pmsfcr_el1
24924  *
24925  * AP Sampling Filter Control Register
24926  * Controls sample filtering. The filter is the logical AND of the FL, FT and FE bits. For
24927  * example, if FE == 1 and FT == 1 only samples including the selected instruction types and the
24928  * selected events will be recorded.
24929  */
24930 union bdk_ap_pmsfcr_el1
24931 {
24932     uint64_t u;
24933     struct bdk_ap_pmsfcr_el1_s
24934     {
24935 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
24936         uint64_t reserved_19_63        : 45;
24937         uint64_t st                    : 1;  /**< [ 18: 18](R/W) Store filter enable.
24938                                                                    0 = Do not record store instructions.
24939                                                                    1 = Record all store instructions, including vector stores and all atomic operations.
24940 
24941                                                                  Ignored if [FT] = 0. */
24942         uint64_t ld                    : 1;  /**< [ 17: 17](R/W) Load filter enable.
24943                                                                    0 = Do not record load instructions.
24944                                                                    1 = Record all load instructions, including vector loads and atomic operations that
24945                                                                  return data.
24946 
24947                                                                  Ignored if [FT] = 0. */
24948         uint64_t bb                    : 1;  /**< [ 16: 16](R/W) Branch filter enable.
24949                                                                    0 = Do not record branch instructions.
24950                                                                    1 = Record all branch instructions.
24951 
24952                                                                  Ignored if [FT] = 0. */
24953         uint64_t reserved_3_15         : 13;
24954         uint64_t fl                    : 1;  /**< [  2:  2](R/W) Filter by latency.
24955                                                                    0 = Latency filtering disabled.
24956                                                                    1 = Latency filtering enabled. Samples with a total latency less than
24957                                                                  PMSLATFR_EL1.MINLAT will not be recorded.
24958                                                                  If this bit is set to 1 and PMSLATFR_EL1.MINLAT is zero, it is CONSTRAINED UNPREDICTABLE
24959                                                                  whether no samples are recorded or the FL bit is ignored. */
24960         uint64_t ft                    : 1;  /**< [  1:  1](R/W) Filter by type. The filter is the logical OR of the ST, LD and B bits. For example, if LD
24961                                                                  and ST are both
24962                                                                  set, both load and store instructions are recorded.
24963                                                                    0 = Type filtering disabled.
24964                                                                    1 = Type filtering enabled. Samples not one of the selected instruction types will not
24965                                                                  be recorded.
24966 
24967                                                                  If this bit is set to 1 and the ST, LD, and B bits are all zero, it is constrained
24968                                                                  unpredictable whether no samples are recorded or the FT bit is ignored. */
24969         uint64_t fe                    : 1;  /**< [  0:  0](R/W) Filter by event.
24970                                                                    0 = Event filtering disabled.
24971                                                                    1 = Event filtering enabled. Samples not including the events selected by PMSEVFR_EL1
24972                                                                  will not be recorded.
24973 
24974                                                                  If this bit is set to 1 and PMSEVFR_EL1 is zero, it is constrained unpredictable whether
24975                                                                  no samples are recorded or the FE. */
24976 #else /* Word 0 - Little Endian */
24977         uint64_t fe                    : 1;  /**< [  0:  0](R/W) Filter by event.
24978                                                                    0 = Event filtering disabled.
24979                                                                    1 = Event filtering enabled. Samples not including the events selected by PMSEVFR_EL1
24980                                                                  will not be recorded.
24981 
24982                                                                  If this bit is set to 1 and PMSEVFR_EL1 is zero, it is constrained unpredictable whether
24983                                                                  no samples are recorded or the FE. */
24984         uint64_t ft                    : 1;  /**< [  1:  1](R/W) Filter by type. The filter is the logical OR of the ST, LD and B bits. For example, if LD
24985                                                                  and ST are both
24986                                                                  set, both load and store instructions are recorded.
24987                                                                    0 = Type filtering disabled.
24988                                                                    1 = Type filtering enabled. Samples not one of the selected instruction types will not
24989                                                                  be recorded.
24990 
24991                                                                  If this bit is set to 1 and the ST, LD, and B bits are all zero, it is constrained
24992                                                                  unpredictable whether no samples are recorded or the FT bit is ignored. */
24993         uint64_t fl                    : 1;  /**< [  2:  2](R/W) Filter by latency.
24994                                                                    0 = Latency filtering disabled.
24995                                                                    1 = Latency filtering enabled. Samples with a total latency less than
24996                                                                  PMSLATFR_EL1.MINLAT will not be recorded.
24997                                                                  If this bit is set to 1 and PMSLATFR_EL1.MINLAT is zero, it is CONSTRAINED UNPREDICTABLE
24998                                                                  whether no samples are recorded or the FL bit is ignored. */
24999         uint64_t reserved_3_15         : 13;
25000         uint64_t bb                    : 1;  /**< [ 16: 16](R/W) Branch filter enable.
25001                                                                    0 = Do not record branch instructions.
25002                                                                    1 = Record all branch instructions.
25003 
25004                                                                  Ignored if [FT] = 0. */
25005         uint64_t ld                    : 1;  /**< [ 17: 17](R/W) Load filter enable.
25006                                                                    0 = Do not record load instructions.
25007                                                                    1 = Record all load instructions, including vector loads and atomic operations that
25008                                                                  return data.
25009 
25010                                                                  Ignored if [FT] = 0. */
25011         uint64_t st                    : 1;  /**< [ 18: 18](R/W) Store filter enable.
25012                                                                    0 = Do not record store instructions.
25013                                                                    1 = Record all store instructions, including vector stores and all atomic operations.
25014 
25015                                                                  Ignored if [FT] = 0. */
25016         uint64_t reserved_19_63        : 45;
25017 #endif /* Word 0 - End */
25018     } s;
25019     /* struct bdk_ap_pmsfcr_el1_s cn; */
25020 };
25021 typedef union bdk_ap_pmsfcr_el1 bdk_ap_pmsfcr_el1_t;
25022 
25023 #define BDK_AP_PMSFCR_EL1 BDK_AP_PMSFCR_EL1_FUNC()
25024 static inline uint64_t BDK_AP_PMSFCR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSFCR_EL1_FUNC(void)25025 static inline uint64_t BDK_AP_PMSFCR_EL1_FUNC(void)
25026 {
25027     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
25028         return 0x30009090400ll;
25029     __bdk_csr_fatal("AP_PMSFCR_EL1", 0, 0, 0, 0, 0);
25030 }
25031 
25032 #define typedef_BDK_AP_PMSFCR_EL1 bdk_ap_pmsfcr_el1_t
25033 #define bustype_BDK_AP_PMSFCR_EL1 BDK_CSR_TYPE_SYSREG
25034 #define basename_BDK_AP_PMSFCR_EL1 "AP_PMSFCR_EL1"
25035 #define busnum_BDK_AP_PMSFCR_EL1 0
25036 #define arguments_BDK_AP_PMSFCR_EL1 -1,-1,-1,-1
25037 
25038 /**
25039  * Register (SYSREG) ap_pmsicr_el1
25040  *
25041  * AP Sampling Interval Control Register
25042  * Software must write zero to PMSICR_EL1 before enabling sample profiling for a sampling
25043  * session.
25044  * Software must then treat PMSICR_EL1 as an opaque, 64-bit, read/write register used for context
25045  * switches only.
25046  */
25047 union bdk_ap_pmsicr_el1
25048 {
25049     uint64_t u;
25050     struct bdk_ap_pmsicr_el1_s
25051     {
25052 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25053         uint64_t reserved_0_63         : 64;
25054 #else /* Word 0 - Little Endian */
25055         uint64_t reserved_0_63         : 64;
25056 #endif /* Word 0 - End */
25057     } s;
25058     /* struct bdk_ap_pmsicr_el1_s cn; */
25059 };
25060 typedef union bdk_ap_pmsicr_el1 bdk_ap_pmsicr_el1_t;
25061 
25062 #define BDK_AP_PMSICR_EL1 BDK_AP_PMSICR_EL1_FUNC()
25063 static inline uint64_t BDK_AP_PMSICR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSICR_EL1_FUNC(void)25064 static inline uint64_t BDK_AP_PMSICR_EL1_FUNC(void)
25065 {
25066     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
25067         return 0x30009090200ll;
25068     __bdk_csr_fatal("AP_PMSICR_EL1", 0, 0, 0, 0, 0);
25069 }
25070 
25071 #define typedef_BDK_AP_PMSICR_EL1 bdk_ap_pmsicr_el1_t
25072 #define bustype_BDK_AP_PMSICR_EL1 BDK_CSR_TYPE_SYSREG
25073 #define basename_BDK_AP_PMSICR_EL1 "AP_PMSICR_EL1"
25074 #define busnum_BDK_AP_PMSICR_EL1 0
25075 #define arguments_BDK_AP_PMSICR_EL1 -1,-1,-1,-1
25076 
25077 /**
25078  * Register (SYSREG) ap_pmsidr_el1
25079  *
25080  * AP Sampling Profiling ID Register
25081  * Describes the Statistical Profiling implementation to software.
25082  */
25083 union bdk_ap_pmsidr_el1
25084 {
25085     uint64_t u;
25086     struct bdk_ap_pmsidr_el1_s
25087     {
25088 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25089         uint64_t reserved_20_63        : 44;
25090         uint64_t countsize             : 4;  /**< [ 19: 16](RO) Defines the size of the counters.
25091                                                                    0x2 = 12-bit saturating counters.
25092 
25093                                                                  All other values are reserved. Reserved values might be defined in a future version of the
25094                                                                  architecture. */
25095         uint64_t maxsize               : 4;  /**< [ 15: 12](RO) Defines the largest size for a single record, rounded up to a power-of-two. If this is the
25096                                                                  same as the minimum alignment (PMBIDR_EL1.Align), then each record is exactly this size.
25097                                                                    0x4 = 16 bytes.
25098                                                                    0x5 = 32 bytes.
25099                                                                    0x6 = 64 bytes.
25100                                                                    0x7 = 128 bytes.
25101                                                                    ... .
25102                                                                    0xB = 2 KB.
25103 
25104                                                                  All other values are reserved. Reserved values might be defined in a future version of the
25105                                                                  architecture. */
25106         uint64_t interval              : 4;  /**< [ 11:  8](RO) Recommended minimum sampling interval. This provides guidance from the implementer to the
25107                                                                  smallest minimum sampling interval, N. It is encoded as floor((Log2(N)-8)*2).
25108                                                                    0x0 = 256.
25109                                                                    0x2 = 512.
25110                                                                    0x3 = 724.
25111                                                                    0x4 = 1024.
25112                                                                    0x5 = 1448.
25113                                                                    0x6 = 2048.
25114                                                                    0x7 = 2896.
25115                                                                    0x8 = 4096.
25116 
25117                                                                  All other values are reserved. Reserved values might be defined in a future version of the
25118                                                                  architecture. */
25119         uint64_t llnw                  : 1;  /**< [  7:  7](RO) Last level cache write events. Defines whether Last Level Cache events in the Event packet
25120                                                                  are valid on write operations.
25121                                                                    0 = Last level cache events are valid for write operations.
25122                                                                    1 = Last level cache events are not valid for write operations. */
25123         uint64_t llnr                  : 1;  /**< [  6:  6](RO) Last level cache read events. Defines whether Last Level Cache events in the Event packet
25124                                                                  are valid on read operations.
25125                                                                    0 = Last level cache events are valid for read operations.
25126                                                                    1 = Last level cache events are not valid for read operations. */
25127         uint64_t ernd                  : 1;  /**< [  5:  5](RO) Defines how the random number generator is used in determining the interval between
25128                                                                  samples, when enabled by PMSIRR_EL1[RND].
25129                                                                    0 = The random number is added at the start of the interval, and the sample is taken and
25130                                                                  a new interval started when the combined interval expires.
25131                                                                    1 = The random number is added and the new interval started after the interval
25132                                                                  programmed in PMSIRR_EL1[INTERVAL] expires, and the sample is taken when the random
25133                                                                  interval expires. */
25134         uint64_t lds                   : 1;  /**< [  4:  4](RO) Data source indicator for sampled load instructions.
25135                                                                    0 = Loaded data source not implemented.
25136                                                                    1 = Loaded data source implemented. */
25137         uint64_t archinst              : 1;  /**< [  3:  3](RO) Architectural instruction profiling.
25138                                                                    0 = Micro-op sampling implemented.
25139                                                                    1 = Architecture instruction sampling implemented. */
25140         uint64_t fl                    : 1;  /**< [  2:  2](RO) Filtering by latency. This bit reads as one. */
25141         uint64_t ft                    : 1;  /**< [  1:  1](RO) Filtering by operation type. This bit reads as one. */
25142         uint64_t fe                    : 1;  /**< [  0:  0](RO) Filtering by events. This bit reads as one. */
25143 #else /* Word 0 - Little Endian */
25144         uint64_t fe                    : 1;  /**< [  0:  0](RO) Filtering by events. This bit reads as one. */
25145         uint64_t ft                    : 1;  /**< [  1:  1](RO) Filtering by operation type. This bit reads as one. */
25146         uint64_t fl                    : 1;  /**< [  2:  2](RO) Filtering by latency. This bit reads as one. */
25147         uint64_t archinst              : 1;  /**< [  3:  3](RO) Architectural instruction profiling.
25148                                                                    0 = Micro-op sampling implemented.
25149                                                                    1 = Architecture instruction sampling implemented. */
25150         uint64_t lds                   : 1;  /**< [  4:  4](RO) Data source indicator for sampled load instructions.
25151                                                                    0 = Loaded data source not implemented.
25152                                                                    1 = Loaded data source implemented. */
25153         uint64_t ernd                  : 1;  /**< [  5:  5](RO) Defines how the random number generator is used in determining the interval between
25154                                                                  samples, when enabled by PMSIRR_EL1[RND].
25155                                                                    0 = The random number is added at the start of the interval, and the sample is taken and
25156                                                                  a new interval started when the combined interval expires.
25157                                                                    1 = The random number is added and the new interval started after the interval
25158                                                                  programmed in PMSIRR_EL1[INTERVAL] expires, and the sample is taken when the random
25159                                                                  interval expires. */
25160         uint64_t llnr                  : 1;  /**< [  6:  6](RO) Last level cache read events. Defines whether Last Level Cache events in the Event packet
25161                                                                  are valid on read operations.
25162                                                                    0 = Last level cache events are valid for read operations.
25163                                                                    1 = Last level cache events are not valid for read operations. */
25164         uint64_t llnw                  : 1;  /**< [  7:  7](RO) Last level cache write events. Defines whether Last Level Cache events in the Event packet
25165                                                                  are valid on write operations.
25166                                                                    0 = Last level cache events are valid for write operations.
25167                                                                    1 = Last level cache events are not valid for write operations. */
25168         uint64_t interval              : 4;  /**< [ 11:  8](RO) Recommended minimum sampling interval. This provides guidance from the implementer to the
25169                                                                  smallest minimum sampling interval, N. It is encoded as floor((Log2(N)-8)*2).
25170                                                                    0x0 = 256.
25171                                                                    0x2 = 512.
25172                                                                    0x3 = 724.
25173                                                                    0x4 = 1024.
25174                                                                    0x5 = 1448.
25175                                                                    0x6 = 2048.
25176                                                                    0x7 = 2896.
25177                                                                    0x8 = 4096.
25178 
25179                                                                  All other values are reserved. Reserved values might be defined in a future version of the
25180                                                                  architecture. */
25181         uint64_t maxsize               : 4;  /**< [ 15: 12](RO) Defines the largest size for a single record, rounded up to a power-of-two. If this is the
25182                                                                  same as the minimum alignment (PMBIDR_EL1.Align), then each record is exactly this size.
25183                                                                    0x4 = 16 bytes.
25184                                                                    0x5 = 32 bytes.
25185                                                                    0x6 = 64 bytes.
25186                                                                    0x7 = 128 bytes.
25187                                                                    ... .
25188                                                                    0xB = 2 KB.
25189 
25190                                                                  All other values are reserved. Reserved values might be defined in a future version of the
25191                                                                  architecture. */
25192         uint64_t countsize             : 4;  /**< [ 19: 16](RO) Defines the size of the counters.
25193                                                                    0x2 = 12-bit saturating counters.
25194 
25195                                                                  All other values are reserved. Reserved values might be defined in a future version of the
25196                                                                  architecture. */
25197         uint64_t reserved_20_63        : 44;
25198 #endif /* Word 0 - End */
25199     } s;
25200     /* struct bdk_ap_pmsidr_el1_s cn; */
25201 };
25202 typedef union bdk_ap_pmsidr_el1 bdk_ap_pmsidr_el1_t;
25203 
25204 #define BDK_AP_PMSIDR_EL1 BDK_AP_PMSIDR_EL1_FUNC()
25205 static inline uint64_t BDK_AP_PMSIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSIDR_EL1_FUNC(void)25206 static inline uint64_t BDK_AP_PMSIDR_EL1_FUNC(void)
25207 {
25208     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
25209         return 0x30009090700ll;
25210     __bdk_csr_fatal("AP_PMSIDR_EL1", 0, 0, 0, 0, 0);
25211 }
25212 
25213 #define typedef_BDK_AP_PMSIDR_EL1 bdk_ap_pmsidr_el1_t
25214 #define bustype_BDK_AP_PMSIDR_EL1 BDK_CSR_TYPE_SYSREG
25215 #define basename_BDK_AP_PMSIDR_EL1 "AP_PMSIDR_EL1"
25216 #define busnum_BDK_AP_PMSIDR_EL1 0
25217 #define arguments_BDK_AP_PMSIDR_EL1 -1,-1,-1,-1
25218 
25219 /**
25220  * Register (SYSREG) ap_pmsirr_el1
25221  *
25222  * AP Sampling Interval Reload Register
25223  * Defines the interval between samples.
25224  */
25225 union bdk_ap_pmsirr_el1
25226 {
25227     uint64_t u;
25228     struct bdk_ap_pmsirr_el1_s
25229     {
25230 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25231         uint64_t reserved_32_63        : 32;
25232         uint64_t interval              : 24; /**< [ 31:  8](R/W) Bits [31:8] of the PMSICR_EL1 interval counter reload value. Software must set this to a
25233                                                                  non-zero
25234                                                                  value. If software sets this to zero, an UNKNOWN sampling interval is used. Software
25235                                                                  should set this to
25236                                                                  a value greater than the minimum indicated by PMSIDR_EL1.Interval. */
25237         uint64_t reserved_1_7          : 7;
25238         uint64_t rnd                   : 1;  /**< [  0:  0](R/W) Controls randomization of the sampling interval.
25239                                                                    0 = Disable randomization of sampling interval.
25240                                                                    1 = Add (pseudo-)random jitter to sampling interval.
25241 
25242                                                                  The random number generator is not architected. */
25243 #else /* Word 0 - Little Endian */
25244         uint64_t rnd                   : 1;  /**< [  0:  0](R/W) Controls randomization of the sampling interval.
25245                                                                    0 = Disable randomization of sampling interval.
25246                                                                    1 = Add (pseudo-)random jitter to sampling interval.
25247 
25248                                                                  The random number generator is not architected. */
25249         uint64_t reserved_1_7          : 7;
25250         uint64_t interval              : 24; /**< [ 31:  8](R/W) Bits [31:8] of the PMSICR_EL1 interval counter reload value. Software must set this to a
25251                                                                  non-zero
25252                                                                  value. If software sets this to zero, an UNKNOWN sampling interval is used. Software
25253                                                                  should set this to
25254                                                                  a value greater than the minimum indicated by PMSIDR_EL1.Interval. */
25255         uint64_t reserved_32_63        : 32;
25256 #endif /* Word 0 - End */
25257     } s;
25258     /* struct bdk_ap_pmsirr_el1_s cn; */
25259 };
25260 typedef union bdk_ap_pmsirr_el1 bdk_ap_pmsirr_el1_t;
25261 
25262 #define BDK_AP_PMSIRR_EL1 BDK_AP_PMSIRR_EL1_FUNC()
25263 static inline uint64_t BDK_AP_PMSIRR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSIRR_EL1_FUNC(void)25264 static inline uint64_t BDK_AP_PMSIRR_EL1_FUNC(void)
25265 {
25266     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
25267         return 0x30009090300ll;
25268     __bdk_csr_fatal("AP_PMSIRR_EL1", 0, 0, 0, 0, 0);
25269 }
25270 
25271 #define typedef_BDK_AP_PMSIRR_EL1 bdk_ap_pmsirr_el1_t
25272 #define bustype_BDK_AP_PMSIRR_EL1 BDK_CSR_TYPE_SYSREG
25273 #define basename_BDK_AP_PMSIRR_EL1 "AP_PMSIRR_EL1"
25274 #define busnum_BDK_AP_PMSIRR_EL1 0
25275 #define arguments_BDK_AP_PMSIRR_EL1 -1,-1,-1,-1
25276 
25277 /**
25278  * Register (SYSREG) ap_pmslatfr_el1
25279  *
25280  * AP Sampling Latency Filter Register
25281  * Controls sample filtering by latency.
25282  */
25283 union bdk_ap_pmslatfr_el1
25284 {
25285     uint64_t u;
25286     struct bdk_ap_pmslatfr_el1_s
25287     {
25288 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25289         uint64_t reserved_12_63        : 52;
25290         uint64_t minlat                : 12; /**< [ 11:  0](R/W) Minimum latency. When PMSFCR_EL1.FL == 1, defines the minimum total latency for filtered
25291                                                                  operations. Samples with a total latency less than MINLAT will not be recorded.
25292                                                                  Ignored if PMSFCR_EL1.FL == 0. */
25293 #else /* Word 0 - Little Endian */
25294         uint64_t minlat                : 12; /**< [ 11:  0](R/W) Minimum latency. When PMSFCR_EL1.FL == 1, defines the minimum total latency for filtered
25295                                                                  operations. Samples with a total latency less than MINLAT will not be recorded.
25296                                                                  Ignored if PMSFCR_EL1.FL == 0. */
25297         uint64_t reserved_12_63        : 52;
25298 #endif /* Word 0 - End */
25299     } s;
25300     /* struct bdk_ap_pmslatfr_el1_s cn; */
25301 };
25302 typedef union bdk_ap_pmslatfr_el1 bdk_ap_pmslatfr_el1_t;
25303 
25304 #define BDK_AP_PMSLATFR_EL1 BDK_AP_PMSLATFR_EL1_FUNC()
25305 static inline uint64_t BDK_AP_PMSLATFR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSLATFR_EL1_FUNC(void)25306 static inline uint64_t BDK_AP_PMSLATFR_EL1_FUNC(void)
25307 {
25308     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
25309         return 0x30009090600ll;
25310     __bdk_csr_fatal("AP_PMSLATFR_EL1", 0, 0, 0, 0, 0);
25311 }
25312 
25313 #define typedef_BDK_AP_PMSLATFR_EL1 bdk_ap_pmslatfr_el1_t
25314 #define bustype_BDK_AP_PMSLATFR_EL1 BDK_CSR_TYPE_SYSREG
25315 #define basename_BDK_AP_PMSLATFR_EL1 "AP_PMSLATFR_EL1"
25316 #define busnum_BDK_AP_PMSLATFR_EL1 0
25317 #define arguments_BDK_AP_PMSLATFR_EL1 -1,-1,-1,-1
25318 
25319 /**
25320  * Register (SYSREG) ap_pmswinc_el0
25321  *
25322  * AP Performance Monitors Software Increment Register
25323  * Increments a counter that is configured to count the Software
25324  *     increment event, event 0x0.
25325  */
25326 union bdk_ap_pmswinc_el0
25327 {
25328     uint32_t u;
25329     struct bdk_ap_pmswinc_el0_s
25330     {
25331 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25332         uint32_t reserved_31           : 1;
25333         uint32_t p                     : 31; /**< [ 30:  0](RO) Event counter software increment bit for PMEVCNTR\<x\>.
25334                                                                  Bits [30:N] are RAZ/WI.
25335                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
25336                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in PMCR[N].
25337                                                                  The effects of writing to this bit are:
25338                                                                  0 = No action. The write to this bit is ignored.
25339                                                                  1 = If PMEVCNTR\<x\> is enabled and configured to count the software
25340                                                                      increment event, increments PMEVCNTR\<x\> by 1. If PMEVCNTR\<x\>
25341                                                                      is disabled, or not configured to count the software increment
25342                                                                      event, the write to this bit is ignored. */
25343 #else /* Word 0 - Little Endian */
25344         uint32_t p                     : 31; /**< [ 30:  0](RO) Event counter software increment bit for PMEVCNTR\<x\>.
25345                                                                  Bits [30:N] are RAZ/WI.
25346                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
25347                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in PMCR[N].
25348                                                                  The effects of writing to this bit are:
25349                                                                  0 = No action. The write to this bit is ignored.
25350                                                                  1 = If PMEVCNTR\<x\> is enabled and configured to count the software
25351                                                                      increment event, increments PMEVCNTR\<x\> by 1. If PMEVCNTR\<x\>
25352                                                                      is disabled, or not configured to count the software increment
25353                                                                      event, the write to this bit is ignored. */
25354         uint32_t reserved_31           : 1;
25355 #endif /* Word 0 - End */
25356     } s;
25357     /* struct bdk_ap_pmswinc_el0_s cn8; */
25358     struct bdk_ap_pmswinc_el0_cn9
25359     {
25360 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25361         uint32_t reserved_31           : 1;
25362         uint32_t p                     : 31; /**< [ 30:  0](WO) Event counter software increment bit for PMEVCNTR\<x\>.
25363                                                                  Bits [30:N] are RAZ/WI.
25364                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
25365                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in PMCR[N].
25366                                                                  The effects of writing to this bit are:
25367                                                                  0 = No action. The write to this bit is ignored.
25368                                                                  1 = If PMEVCNTR\<x\> is enabled and configured to count the software
25369                                                                      increment event, increments PMEVCNTR\<x\> by 1. If PMEVCNTR\<x\>
25370                                                                      is disabled, or not configured to count the software increment
25371                                                                      event, the write to this bit is ignored. */
25372 #else /* Word 0 - Little Endian */
25373         uint32_t p                     : 31; /**< [ 30:  0](WO) Event counter software increment bit for PMEVCNTR\<x\>.
25374                                                                  Bits [30:N] are RAZ/WI.
25375                                                                  When EL2 is implemented, in nonsecure EL1 and EL0, N is the
25376                                                                      value in AP_MDCR_EL2[HPMN]. Otherwise, N is the value in PMCR[N].
25377                                                                  The effects of writing to this bit are:
25378                                                                  0 = No action. The write to this bit is ignored.
25379                                                                  1 = If PMEVCNTR\<x\> is enabled and configured to count the software
25380                                                                      increment event, increments PMEVCNTR\<x\> by 1. If PMEVCNTR\<x\>
25381                                                                      is disabled, or not configured to count the software increment
25382                                                                      event, the write to this bit is ignored. */
25383         uint32_t reserved_31           : 1;
25384 #endif /* Word 0 - End */
25385     } cn9;
25386 };
25387 typedef union bdk_ap_pmswinc_el0 bdk_ap_pmswinc_el0_t;
25388 
25389 #define BDK_AP_PMSWINC_EL0 BDK_AP_PMSWINC_EL0_FUNC()
25390 static inline uint64_t BDK_AP_PMSWINC_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMSWINC_EL0_FUNC(void)25391 static inline uint64_t BDK_AP_PMSWINC_EL0_FUNC(void)
25392 {
25393     return 0x303090c0400ll;
25394 }
25395 
25396 #define typedef_BDK_AP_PMSWINC_EL0 bdk_ap_pmswinc_el0_t
25397 #define bustype_BDK_AP_PMSWINC_EL0 BDK_CSR_TYPE_SYSREG
25398 #define basename_BDK_AP_PMSWINC_EL0 "AP_PMSWINC_EL0"
25399 #define busnum_BDK_AP_PMSWINC_EL0 0
25400 #define arguments_BDK_AP_PMSWINC_EL0 -1,-1,-1,-1
25401 
25402 /**
25403  * Register (SYSREG) ap_pmuserenr_el0
25404  *
25405  * AP Performance Monitors User Enable Register
25406  * Enables or disables EL0 access to the Performance Monitors.
25407  */
25408 union bdk_ap_pmuserenr_el0
25409 {
25410     uint32_t u;
25411     struct bdk_ap_pmuserenr_el0_s
25412     {
25413 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25414         uint32_t reserved_4_31         : 28;
25415         uint32_t er                    : 1;  /**< [  3:  3](R/W) Event counter read enable.
25416                                                                  0 = EL0 read access to AP_PMXEVCNTR_EL0 / PMEVCNTR\<n\>_EL0 and
25417                                                                      read/write access to AP_PMSELR_EL0 disabled if AP_PMUSERENR_EL0[EN]
25418                                                                      is also 0.
25419                                                                  1 = EL0 read access to AP_PMXEVCNTR_EL0 / PMEVCNTR\<n\>_EL0 and
25420                                                                      read/write access to AP_PMSELR_EL0 enabled. */
25421         uint32_t cr                    : 1;  /**< [  2:  2](R/W) Cycle counter read enable.
25422                                                                  0 = EL0 read access to AP_PMCCNTR_EL0 disabled if AP_PMUSERENR_EL0[EN] is
25423                                                                      also 0.
25424                                                                  1 = EL0 read access to AP_PMCCNTR_EL0 enabled. */
25425         uint32_t sw                    : 1;  /**< [  1:  1](R/W) Software Increment write enable.
25426                                                                  0 = EL0 write access to AP_PMSWINC_EL0 disabled if AP_PMUSERENR_EL0[EN]
25427                                                                      is also 0.
25428                                                                  1 = EL0 write access to AP_PMSWINC_EL0 enabled. */
25429         uint32_t en                    : 1;  /**< [  0:  0](R/W) EL0 access enable bit.
25430                                                                  0 = EL0 access to the Performance Monitors disabled.
25431                                                                  1 = EL0 access to the Performance Monitors enabled. Can access all
25432                                                                      PMU registers at EL0, except for writes to AP_PMUSERENR_EL0 and
25433                                                                      reads/writes of AP_PMINTENSET_EL1 and AP_PMINTENCLR_EL1. */
25434 #else /* Word 0 - Little Endian */
25435         uint32_t en                    : 1;  /**< [  0:  0](R/W) EL0 access enable bit.
25436                                                                  0 = EL0 access to the Performance Monitors disabled.
25437                                                                  1 = EL0 access to the Performance Monitors enabled. Can access all
25438                                                                      PMU registers at EL0, except for writes to AP_PMUSERENR_EL0 and
25439                                                                      reads/writes of AP_PMINTENSET_EL1 and AP_PMINTENCLR_EL1. */
25440         uint32_t sw                    : 1;  /**< [  1:  1](R/W) Software Increment write enable.
25441                                                                  0 = EL0 write access to AP_PMSWINC_EL0 disabled if AP_PMUSERENR_EL0[EN]
25442                                                                      is also 0.
25443                                                                  1 = EL0 write access to AP_PMSWINC_EL0 enabled. */
25444         uint32_t cr                    : 1;  /**< [  2:  2](R/W) Cycle counter read enable.
25445                                                                  0 = EL0 read access to AP_PMCCNTR_EL0 disabled if AP_PMUSERENR_EL0[EN] is
25446                                                                      also 0.
25447                                                                  1 = EL0 read access to AP_PMCCNTR_EL0 enabled. */
25448         uint32_t er                    : 1;  /**< [  3:  3](R/W) Event counter read enable.
25449                                                                  0 = EL0 read access to AP_PMXEVCNTR_EL0 / PMEVCNTR\<n\>_EL0 and
25450                                                                      read/write access to AP_PMSELR_EL0 disabled if AP_PMUSERENR_EL0[EN]
25451                                                                      is also 0.
25452                                                                  1 = EL0 read access to AP_PMXEVCNTR_EL0 / PMEVCNTR\<n\>_EL0 and
25453                                                                      read/write access to AP_PMSELR_EL0 enabled. */
25454         uint32_t reserved_4_31         : 28;
25455 #endif /* Word 0 - End */
25456     } s;
25457     /* struct bdk_ap_pmuserenr_el0_s cn; */
25458 };
25459 typedef union bdk_ap_pmuserenr_el0 bdk_ap_pmuserenr_el0_t;
25460 
25461 #define BDK_AP_PMUSERENR_EL0 BDK_AP_PMUSERENR_EL0_FUNC()
25462 static inline uint64_t BDK_AP_PMUSERENR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMUSERENR_EL0_FUNC(void)25463 static inline uint64_t BDK_AP_PMUSERENR_EL0_FUNC(void)
25464 {
25465     return 0x303090e0000ll;
25466 }
25467 
25468 #define typedef_BDK_AP_PMUSERENR_EL0 bdk_ap_pmuserenr_el0_t
25469 #define bustype_BDK_AP_PMUSERENR_EL0 BDK_CSR_TYPE_SYSREG
25470 #define basename_BDK_AP_PMUSERENR_EL0 "AP_PMUSERENR_EL0"
25471 #define busnum_BDK_AP_PMUSERENR_EL0 0
25472 #define arguments_BDK_AP_PMUSERENR_EL0 -1,-1,-1,-1
25473 
25474 /**
25475  * Register (SYSREG) ap_pmxevcntr_el0
25476  *
25477  * AP Performance Monitors Selected Event Count Register
25478  * Reads or writes the value of the selected event counter,
25479  *     PMEVCNTR\<x\>_EL0. AP_PMSELR_EL0[SEL] determines which event counter
25480  *     is selected.
25481  */
25482 union bdk_ap_pmxevcntr_el0
25483 {
25484     uint32_t u;
25485     struct bdk_ap_pmxevcntr_el0_s
25486     {
25487 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25488         uint32_t pmevcntr              : 32; /**< [ 31:  0](R/W) Value of the selected event counter, PMEVCNTR\<x\>_EL0, where x
25489                                                                      is the value stored in AP_PMSELR_EL0[SEL]. */
25490 #else /* Word 0 - Little Endian */
25491         uint32_t pmevcntr              : 32; /**< [ 31:  0](R/W) Value of the selected event counter, PMEVCNTR\<x\>_EL0, where x
25492                                                                      is the value stored in AP_PMSELR_EL0[SEL]. */
25493 #endif /* Word 0 - End */
25494     } s;
25495     /* struct bdk_ap_pmxevcntr_el0_s cn; */
25496 };
25497 typedef union bdk_ap_pmxevcntr_el0 bdk_ap_pmxevcntr_el0_t;
25498 
25499 #define BDK_AP_PMXEVCNTR_EL0 BDK_AP_PMXEVCNTR_EL0_FUNC()
25500 static inline uint64_t BDK_AP_PMXEVCNTR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMXEVCNTR_EL0_FUNC(void)25501 static inline uint64_t BDK_AP_PMXEVCNTR_EL0_FUNC(void)
25502 {
25503     return 0x303090d0200ll;
25504 }
25505 
25506 #define typedef_BDK_AP_PMXEVCNTR_EL0 bdk_ap_pmxevcntr_el0_t
25507 #define bustype_BDK_AP_PMXEVCNTR_EL0 BDK_CSR_TYPE_SYSREG
25508 #define basename_BDK_AP_PMXEVCNTR_EL0 "AP_PMXEVCNTR_EL0"
25509 #define busnum_BDK_AP_PMXEVCNTR_EL0 0
25510 #define arguments_BDK_AP_PMXEVCNTR_EL0 -1,-1,-1,-1
25511 
25512 /**
25513  * Register (SYSREG) ap_pmxevtyper_el0
25514  *
25515  * AP Performance Monitors Selected Event Type Register
25516  * When AP_PMSELR_EL0[SEL] selects an event counter, this accesses a
25517  *     PMEVTYPER\<n\>_EL0 register. When AP_PMSELR_EL0[SEL] selects the
25518  *     cycle counter, this accesses AP_PMCCFILTR_EL0.
25519  */
25520 union bdk_ap_pmxevtyper_el0
25521 {
25522     uint32_t u;
25523     struct bdk_ap_pmxevtyper_el0_s
25524     {
25525 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25526         uint32_t data                  : 32; /**< [ 31:  0](R/W) Event type register or AP_PMCCFILTR_EL0.
25527                                                                  When AP_PMSELR_EL0[SEL] == 31, this register accesses
25528                                                                      AP_PMCCFILTR_EL0.
25529                                                                  Otherwise, this register accesses PMEVTYPER\<n\>_EL0 where n is
25530                                                                      the value in AP_PMSELR_EL0[SEL]. */
25531 #else /* Word 0 - Little Endian */
25532         uint32_t data                  : 32; /**< [ 31:  0](R/W) Event type register or AP_PMCCFILTR_EL0.
25533                                                                  When AP_PMSELR_EL0[SEL] == 31, this register accesses
25534                                                                      AP_PMCCFILTR_EL0.
25535                                                                  Otherwise, this register accesses PMEVTYPER\<n\>_EL0 where n is
25536                                                                      the value in AP_PMSELR_EL0[SEL]. */
25537 #endif /* Word 0 - End */
25538     } s;
25539     /* struct bdk_ap_pmxevtyper_el0_s cn; */
25540 };
25541 typedef union bdk_ap_pmxevtyper_el0 bdk_ap_pmxevtyper_el0_t;
25542 
25543 #define BDK_AP_PMXEVTYPER_EL0 BDK_AP_PMXEVTYPER_EL0_FUNC()
25544 static inline uint64_t BDK_AP_PMXEVTYPER_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_PMXEVTYPER_EL0_FUNC(void)25545 static inline uint64_t BDK_AP_PMXEVTYPER_EL0_FUNC(void)
25546 {
25547     return 0x303090d0100ll;
25548 }
25549 
25550 #define typedef_BDK_AP_PMXEVTYPER_EL0 bdk_ap_pmxevtyper_el0_t
25551 #define bustype_BDK_AP_PMXEVTYPER_EL0 BDK_CSR_TYPE_SYSREG
25552 #define basename_BDK_AP_PMXEVTYPER_EL0 "AP_PMXEVTYPER_EL0"
25553 #define busnum_BDK_AP_PMXEVTYPER_EL0 0
25554 #define arguments_BDK_AP_PMXEVTYPER_EL0 -1,-1,-1,-1
25555 
25556 /**
25557  * Register (SYSREG) ap_revidr_el1
25558  *
25559  * AP Revision ID Register
25560  * This register provides implementation-specific minor revision information
25561  * that can only be interpreted in conjunction with AP_MIDR_EL1.
25562  */
25563 union bdk_ap_revidr_el1
25564 {
25565     uint32_t u;
25566     struct bdk_ap_revidr_el1_s
25567     {
25568 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25569         uint32_t reserved_0_31         : 32;
25570 #else /* Word 0 - Little Endian */
25571         uint32_t reserved_0_31         : 32;
25572 #endif /* Word 0 - End */
25573     } s;
25574     /* struct bdk_ap_revidr_el1_s cn; */
25575 };
25576 typedef union bdk_ap_revidr_el1 bdk_ap_revidr_el1_t;
25577 
25578 #define BDK_AP_REVIDR_EL1 BDK_AP_REVIDR_EL1_FUNC()
25579 static inline uint64_t BDK_AP_REVIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_REVIDR_EL1_FUNC(void)25580 static inline uint64_t BDK_AP_REVIDR_EL1_FUNC(void)
25581 {
25582     return 0x30000000600ll;
25583 }
25584 
25585 #define typedef_BDK_AP_REVIDR_EL1 bdk_ap_revidr_el1_t
25586 #define bustype_BDK_AP_REVIDR_EL1 BDK_CSR_TYPE_SYSREG
25587 #define basename_BDK_AP_REVIDR_EL1 "AP_REVIDR_EL1"
25588 #define busnum_BDK_AP_REVIDR_EL1 0
25589 #define arguments_BDK_AP_REVIDR_EL1 -1,-1,-1,-1
25590 
25591 /**
25592  * Register (SYSREG) ap_rmr_el#
25593  *
25594  * AP Reset Management non-EL3 Register
25595  * Reset control for EL1 or EL2. Doesn't exists since EL3 exists.
25596  */
25597 union bdk_ap_rmr_elx
25598 {
25599     uint32_t u;
25600     struct bdk_ap_rmr_elx_s
25601     {
25602 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25603         uint32_t reserved_0_31         : 32;
25604 #else /* Word 0 - Little Endian */
25605         uint32_t reserved_0_31         : 32;
25606 #endif /* Word 0 - End */
25607     } s;
25608     /* struct bdk_ap_rmr_elx_s cn; */
25609 };
25610 typedef union bdk_ap_rmr_elx bdk_ap_rmr_elx_t;
25611 
25612 static inline uint64_t BDK_AP_RMR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_RMR_ELX(unsigned long a)25613 static inline uint64_t BDK_AP_RMR_ELX(unsigned long a)
25614 {
25615     if ((a>=1)&&(a<=2))
25616         return 0x3000c000200ll + 0ll * ((a) & 0x3);
25617     __bdk_csr_fatal("AP_RMR_ELX", 1, a, 0, 0, 0);
25618 }
25619 
25620 #define typedef_BDK_AP_RMR_ELX(a) bdk_ap_rmr_elx_t
25621 #define bustype_BDK_AP_RMR_ELX(a) BDK_CSR_TYPE_SYSREG
25622 #define basename_BDK_AP_RMR_ELX(a) "AP_RMR_ELX"
25623 #define busnum_BDK_AP_RMR_ELX(a) (a)
25624 #define arguments_BDK_AP_RMR_ELX(a) (a),-1,-1,-1
25625 
25626 /**
25627  * Register (SYSREG) ap_rmr_el3
25628  *
25629  * AP Reset Management EL3 Register
25630  * If EL3 is the highest Exception level implemented, and is
25631  *     capable of using both AArch32 and AArch64, controls the
25632  *     Execution state that the processor boots into and allows
25633  *     request of a Warm reset.
25634  *
25635  * Not implemented on CNXXXX - no 32 bit support.
25636  */
25637 union bdk_ap_rmr_el3
25638 {
25639     uint32_t u;
25640     struct bdk_ap_rmr_el3_s
25641     {
25642 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25643         uint32_t reserved_2_31         : 30;
25644         uint32_t rr                    : 1;  /**< [  1:  1](R/W) When set to 1 this bit requests a Warm reset. The bit is
25645                                                                      strictly a request. */
25646         uint32_t aa64                  : 1;  /**< [  0:  0](R/W) Determines which Execution state the processor boots into
25647                                                                      after a Warm reset:
25648                                                                  The reset vector address on reset takes a choice between two
25649                                                                      IMP DEF values, depending on the value in the AA64 bit.
25650                                                                  0 = AArch32.
25651                                                                  1 = AArch64. */
25652 #else /* Word 0 - Little Endian */
25653         uint32_t aa64                  : 1;  /**< [  0:  0](R/W) Determines which Execution state the processor boots into
25654                                                                      after a Warm reset:
25655                                                                  The reset vector address on reset takes a choice between two
25656                                                                      IMP DEF values, depending on the value in the AA64 bit.
25657                                                                  0 = AArch32.
25658                                                                  1 = AArch64. */
25659         uint32_t rr                    : 1;  /**< [  1:  1](R/W) When set to 1 this bit requests a Warm reset. The bit is
25660                                                                      strictly a request. */
25661         uint32_t reserved_2_31         : 30;
25662 #endif /* Word 0 - End */
25663     } s;
25664     /* struct bdk_ap_rmr_el3_s cn8; */
25665     struct bdk_ap_rmr_el3_cn9
25666     {
25667 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25668         uint32_t reserved_2_31         : 30;
25669         uint32_t rr                    : 1;  /**< [  1:  1](RAZ) When set to 1 this bit requests a Warm reset. The bit is
25670                                                                      strictly a request. */
25671         uint32_t aa64                  : 1;  /**< [  0:  0](RAZ) Determines which Execution state the processor boots into
25672                                                                      after a Warm reset:
25673                                                                  The reset vector address on reset takes a choice between two
25674                                                                      IMP DEF values, depending on the value in the AA64 bit.
25675                                                                  0 = AArch32.
25676                                                                  1 = AArch64. */
25677 #else /* Word 0 - Little Endian */
25678         uint32_t aa64                  : 1;  /**< [  0:  0](RAZ) Determines which Execution state the processor boots into
25679                                                                      after a Warm reset:
25680                                                                  The reset vector address on reset takes a choice between two
25681                                                                      IMP DEF values, depending on the value in the AA64 bit.
25682                                                                  0 = AArch32.
25683                                                                  1 = AArch64. */
25684         uint32_t rr                    : 1;  /**< [  1:  1](RAZ) When set to 1 this bit requests a Warm reset. The bit is
25685                                                                      strictly a request. */
25686         uint32_t reserved_2_31         : 30;
25687 #endif /* Word 0 - End */
25688     } cn9;
25689 };
25690 typedef union bdk_ap_rmr_el3 bdk_ap_rmr_el3_t;
25691 
25692 #define BDK_AP_RMR_EL3 BDK_AP_RMR_EL3_FUNC()
25693 static inline uint64_t BDK_AP_RMR_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_RMR_EL3_FUNC(void)25694 static inline uint64_t BDK_AP_RMR_EL3_FUNC(void)
25695 {
25696     return 0x3060c000200ll;
25697 }
25698 
25699 #define typedef_BDK_AP_RMR_EL3 bdk_ap_rmr_el3_t
25700 #define bustype_BDK_AP_RMR_EL3 BDK_CSR_TYPE_SYSREG
25701 #define basename_BDK_AP_RMR_EL3 "AP_RMR_EL3"
25702 #define busnum_BDK_AP_RMR_EL3 0
25703 #define arguments_BDK_AP_RMR_EL3 -1,-1,-1,-1
25704 
25705 /**
25706  * Register (SYSREG) ap_rvbar_el#
25707  *
25708  * AP Reset Vector Base Address non-EL3 Register
25709  * Reset vector for EL1 or EL2. Doesn't exists since EL3 exists.
25710  */
25711 union bdk_ap_rvbar_elx
25712 {
25713     uint64_t u;
25714     struct bdk_ap_rvbar_elx_s
25715     {
25716 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25717         uint64_t reserved_0_63         : 64;
25718 #else /* Word 0 - Little Endian */
25719         uint64_t reserved_0_63         : 64;
25720 #endif /* Word 0 - End */
25721     } s;
25722     /* struct bdk_ap_rvbar_elx_s cn; */
25723 };
25724 typedef union bdk_ap_rvbar_elx bdk_ap_rvbar_elx_t;
25725 
25726 static inline uint64_t BDK_AP_RVBAR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_RVBAR_ELX(unsigned long a)25727 static inline uint64_t BDK_AP_RVBAR_ELX(unsigned long a)
25728 {
25729     if ((a>=1)&&(a<=2))
25730         return 0x3000c000100ll + 0ll * ((a) & 0x3);
25731     __bdk_csr_fatal("AP_RVBAR_ELX", 1, a, 0, 0, 0);
25732 }
25733 
25734 #define typedef_BDK_AP_RVBAR_ELX(a) bdk_ap_rvbar_elx_t
25735 #define bustype_BDK_AP_RVBAR_ELX(a) BDK_CSR_TYPE_SYSREG
25736 #define basename_BDK_AP_RVBAR_ELX(a) "AP_RVBAR_ELX"
25737 #define busnum_BDK_AP_RVBAR_ELX(a) (a)
25738 #define arguments_BDK_AP_RVBAR_ELX(a) (a),-1,-1,-1
25739 
25740 /**
25741  * Register (SYSREG) ap_rvbar_el3
25742  *
25743  * AP Reset Vector Base Address EL3 Register
25744  * If EL3 is the highest exception level implemented, contains
25745  *     the implementation defined address that execution starts from
25746  *     after reset when executing in AArch64 state.
25747  */
25748 union bdk_ap_rvbar_el3
25749 {
25750     uint64_t u;
25751     struct bdk_ap_rvbar_el3_s
25752     {
25753 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25754         uint64_t data                  : 64; /**< [ 63:  0](RO) Reset Vector Base Address. If this Exception level is the
25755                                                                      highest one implemented, this field contains the
25756                                                                      implementation defined address that execution starts from
25757                                                                      after reset when executing in 64-bit state. Bits[1:0] of this
25758                                                                      register are 00, as this address must be aligned, and the
25759                                                                      address must be within the physical address size supported by
25760                                                                      the processor.
25761 
25762                                                                  If this Exception level is not the highest one implemented,
25763                                                                      then this register is not implemented and its encoding is
25764                                                                      UNdefined. */
25765 #else /* Word 0 - Little Endian */
25766         uint64_t data                  : 64; /**< [ 63:  0](RO) Reset Vector Base Address. If this Exception level is the
25767                                                                      highest one implemented, this field contains the
25768                                                                      implementation defined address that execution starts from
25769                                                                      after reset when executing in 64-bit state. Bits[1:0] of this
25770                                                                      register are 00, as this address must be aligned, and the
25771                                                                      address must be within the physical address size supported by
25772                                                                      the processor.
25773 
25774                                                                  If this Exception level is not the highest one implemented,
25775                                                                      then this register is not implemented and its encoding is
25776                                                                      UNdefined. */
25777 #endif /* Word 0 - End */
25778     } s;
25779     /* struct bdk_ap_rvbar_el3_s cn; */
25780 };
25781 typedef union bdk_ap_rvbar_el3 bdk_ap_rvbar_el3_t;
25782 
25783 #define BDK_AP_RVBAR_EL3 BDK_AP_RVBAR_EL3_FUNC()
25784 static inline uint64_t BDK_AP_RVBAR_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_RVBAR_EL3_FUNC(void)25785 static inline uint64_t BDK_AP_RVBAR_EL3_FUNC(void)
25786 {
25787     return 0x3060c000100ll;
25788 }
25789 
25790 #define typedef_BDK_AP_RVBAR_EL3 bdk_ap_rvbar_el3_t
25791 #define bustype_BDK_AP_RVBAR_EL3 BDK_CSR_TYPE_SYSREG
25792 #define basename_BDK_AP_RVBAR_EL3 "AP_RVBAR_EL3"
25793 #define busnum_BDK_AP_RVBAR_EL3 0
25794 #define arguments_BDK_AP_RVBAR_EL3 -1,-1,-1,-1
25795 
25796 /**
25797  * Register (SYSREG) ap_scr_el3
25798  *
25799  * AP Secure Configuration Register
25800  * Defines the configuration of the current Security state. It
25801  *     specifies:
25802  *  The Security state of EL0 and EL1, either Secure or Non-
25803  *     secure.
25804  *  The Execution state at lower Exception levels.
25805  *  Whether IRQ, FIQ, and External Abort interrupts are taken to
25806  *     EL3.
25807  */
25808 union bdk_ap_scr_el3
25809 {
25810     uint32_t u;
25811     struct bdk_ap_scr_el3_s
25812     {
25813 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
25814         uint32_t reserved_16_31        : 16;
25815         uint32_t terr                  : 1;  /**< [ 15: 15](R/W) Trap Error record accesses.
25816                                                                    0 = Do not trap accesses to error record registers from EL1 and EL2 to EL3.
25817                                                                    1 = Accesses to the ER* registers from EL1 and EL2 generate a Trap exception to EL3. */
25818         uint32_t tlor                  : 1;  /**< [ 14: 14](R/W) v8.1: Trap access to the LOR
25819                                                                  Registers from EL1 and EL2 to EL3, unless the access has been
25820                                                                  trapped to EL2:
25821                                                                  0 = EL1 and EL2 accesses to the LOR Registers are not trapped to EL3.
25822                                                                  1 = EL1 and EL2 accesses to the LOR Registers are trapped to EL3
25823                                                                      unless the access has been trapped to EL2 as a result of the
25824                                                                      AP_HCR_EL2[TLOR]. */
25825         uint32_t twe                   : 1;  /**< [ 13: 13](R/W) Trap WFE.
25826                                                                  0 = WFE instructions not trapped.
25827                                                                  1 = WFE instructions executed in AArch32 or AArch64 at EL2, EL1,
25828                                                                      or EL0 are trapped to EL3 if the instruction would otherwise
25829                                                                      cause suspension of execution, i.e. if there is not a pending
25830                                                                      WFI wakeup event and the instruciton does not cause another
25831                                                                      exception. */
25832         uint32_t twi                   : 1;  /**< [ 12: 12](R/W) Trap WFI.
25833                                                                  0 = WFI instructions not trapped.
25834                                                                  1 = WFI instructions executed in AArch32 or AArch64 at EL2, EL1,
25835                                                                      or EL0 are trapped to EL3 if the instruction would otherwise
25836                                                                      cause suspension of execution. */
25837         uint32_t st                    : 1;  /**< [ 11: 11](R/W) Enables Secure EL1 access to the AP_CNTPS_TVAL_EL1,
25838                                                                      AP_CNTPS_CTL_EL1, and AP_CNTPS_CVAL_EL1 registers.
25839 
25840                                                                  If this bit is 0 and there is a Secure EL1 access to one of
25841                                                                      the CNTPS registers:
25842                                                                   An exception is taken to EL3.
25843                                                                   The exception class for this exception, as returned in
25844                                                                      ESR_EL3[EC], is 0x18
25845                                                                  0 = These registers are only accessible in EL3.
25846                                                                  1 = These registers are accessible in EL3 and also in EL1 when
25847                                                                      AP_SCR_EL3[NS]==0. */
25848         uint32_t rsvd_10               : 1;  /**< [ 10: 10](RO) Execution state control for lower Exception levels.
25849                                                                  This bit is permitted to be cached in a TLB.
25850                                                                  0 = Lower levels are all AArch32.
25851                                                                  1 = The next lower level is AArch64.
25852 
25853                                                                  If EL2 is present:
25854                                                                   EL2 is AArch64.
25855                                                                   EL2 controls EL1 and EL0 behaviors.
25856 
25857                                                                  If EL2 is not present:
25858                                                                   EL1 is AArch64.
25859                                                                   EL0 is determined by the Execution state described in the
25860                                                                      current process state when executing at EL0. */
25861         uint32_t sif                   : 1;  /**< [  9:  9](R/W) Secure instruction fetch. When the processor is in Secure
25862                                                                      state, this bit disables instruction fetch from nonsecure
25863                                                                      memory.
25864                                                                  This bit is permitted to be cached in a TLB.
25865                                                                  0 = Secure state instruction fetches from nonsecure memory are
25866                                                                      permitted.
25867                                                                  1 = Secure state instruction fetches from nonsecure memory are
25868                                                                      not permitted. */
25869         uint32_t hce                   : 1;  /**< [  8:  8](R/W) Hypervisor Call enable. This bit enables use of the HVC
25870                                                                      instruction from nonsecure EL1 modes.
25871 
25872                                                                  If EL3 is implemented but EL2 is not implemented, this bit is
25873                                                                      RES0.
25874                                                                  0 = HVC instruction is UNdefined in nonsecure EL1 modes, and
25875                                                                      either UNdefined or a NOP in Hyp mode, depending on the
25876                                                                      implementation.
25877                                                                  1 = HVC instruction is enabled in nonsecure EL1 modes, and
25878                                                                      performs a Hypervisor Call. */
25879         uint32_t smd                   : 1;  /**< [  7:  7](R/W) SMC Disable.
25880                                                                  0 = SMC is enabled at EL1, EL2, or EL3.
25881                                                                  1 = SMC is UNdefined at all Exception levels. At EL1 in the Non-
25882                                                                      secure state, the AP_HCR_EL2[TSC] bit has priority over this
25883                                                                      control. */
25884         uint32_t reserved_6            : 1;
25885         uint32_t rsvd_4_5              : 2;  /**< [  5:  4](RO) Reserved 1. */
25886         uint32_t ea                    : 1;  /**< [  3:  3](R/W) External Abort and SError Interrupt Routing.
25887                                                                  0 = External Aborts and SError Interrupts while executing at
25888                                                                      exception levels other than EL3 are not taken in EL3.
25889                                                                  1 = External Aborts and SError Interrupts while executing at all
25890                                                                      exception levels are taken in EL3. */
25891         uint32_t fiq                   : 1;  /**< [  2:  2](R/W) Physical FIQ Routing.
25892                                                                  0 = Physical FIQ while executing at exception levels other than
25893                                                                      EL3 are not taken in EL3.
25894                                                                  1 = Physical FIQ while executing at all exception levels are taken
25895                                                                      in EL3. */
25896         uint32_t irq                   : 1;  /**< [  1:  1](R/W) Physical IRQ Routing.
25897                                                                  0 = Physical IRQ while executing at exception levels other than
25898                                                                      EL3 are not taken in EL3.
25899                                                                  1 = Physical IRQ while executing at all exception levels are taken
25900                                                                      in EL3. */
25901         uint32_t nsec                  : 1;  /**< [  0:  0](R/W) Nonsecure bit.
25902                                                                  0 = Indicates that EL0 and EL1 are in Secure state, and so memory
25903                                                                      accesses from those Exception levels can access Secure memory.
25904                                                                  1 = Indicates that EL0 and EL1 are in nonsecure state, and so
25905                                                                      memory accesses from those Exception levels cannot access
25906                                                                      Secure memory. */
25907 #else /* Word 0 - Little Endian */
25908         uint32_t nsec                  : 1;  /**< [  0:  0](R/W) Nonsecure bit.
25909                                                                  0 = Indicates that EL0 and EL1 are in Secure state, and so memory
25910                                                                      accesses from those Exception levels can access Secure memory.
25911                                                                  1 = Indicates that EL0 and EL1 are in nonsecure state, and so
25912                                                                      memory accesses from those Exception levels cannot access
25913                                                                      Secure memory. */
25914         uint32_t irq                   : 1;  /**< [  1:  1](R/W) Physical IRQ Routing.
25915                                                                  0 = Physical IRQ while executing at exception levels other than
25916                                                                      EL3 are not taken in EL3.
25917                                                                  1 = Physical IRQ while executing at all exception levels are taken
25918                                                                      in EL3. */
25919         uint32_t fiq                   : 1;  /**< [  2:  2](R/W) Physical FIQ Routing.
25920                                                                  0 = Physical FIQ while executing at exception levels other than
25921                                                                      EL3 are not taken in EL3.
25922                                                                  1 = Physical FIQ while executing at all exception levels are taken
25923                                                                      in EL3. */
25924         uint32_t ea                    : 1;  /**< [  3:  3](R/W) External Abort and SError Interrupt Routing.
25925                                                                  0 = External Aborts and SError Interrupts while executing at
25926                                                                      exception levels other than EL3 are not taken in EL3.
25927                                                                  1 = External Aborts and SError Interrupts while executing at all
25928                                                                      exception levels are taken in EL3. */
25929         uint32_t rsvd_4_5              : 2;  /**< [  5:  4](RO) Reserved 1. */
25930         uint32_t reserved_6            : 1;
25931         uint32_t smd                   : 1;  /**< [  7:  7](R/W) SMC Disable.
25932                                                                  0 = SMC is enabled at EL1, EL2, or EL3.
25933                                                                  1 = SMC is UNdefined at all Exception levels. At EL1 in the Non-
25934                                                                      secure state, the AP_HCR_EL2[TSC] bit has priority over this
25935                                                                      control. */
25936         uint32_t hce                   : 1;  /**< [  8:  8](R/W) Hypervisor Call enable. This bit enables use of the HVC
25937                                                                      instruction from nonsecure EL1 modes.
25938 
25939                                                                  If EL3 is implemented but EL2 is not implemented, this bit is
25940                                                                      RES0.
25941                                                                  0 = HVC instruction is UNdefined in nonsecure EL1 modes, and
25942                                                                      either UNdefined or a NOP in Hyp mode, depending on the
25943                                                                      implementation.
25944                                                                  1 = HVC instruction is enabled in nonsecure EL1 modes, and
25945                                                                      performs a Hypervisor Call. */
25946         uint32_t sif                   : 1;  /**< [  9:  9](R/W) Secure instruction fetch. When the processor is in Secure
25947                                                                      state, this bit disables instruction fetch from nonsecure
25948                                                                      memory.
25949                                                                  This bit is permitted to be cached in a TLB.
25950                                                                  0 = Secure state instruction fetches from nonsecure memory are
25951                                                                      permitted.
25952                                                                  1 = Secure state instruction fetches from nonsecure memory are
25953                                                                      not permitted. */
25954         uint32_t rsvd_10               : 1;  /**< [ 10: 10](RO) Execution state control for lower Exception levels.
25955                                                                  This bit is permitted to be cached in a TLB.
25956                                                                  0 = Lower levels are all AArch32.
25957                                                                  1 = The next lower level is AArch64.
25958 
25959                                                                  If EL2 is present:
25960                                                                   EL2 is AArch64.
25961                                                                   EL2 controls EL1 and EL0 behaviors.
25962 
25963                                                                  If EL2 is not present:
25964                                                                   EL1 is AArch64.
25965                                                                   EL0 is determined by the Execution state described in the
25966                                                                      current process state when executing at EL0. */
25967         uint32_t st                    : 1;  /**< [ 11: 11](R/W) Enables Secure EL1 access to the AP_CNTPS_TVAL_EL1,
25968                                                                      AP_CNTPS_CTL_EL1, and AP_CNTPS_CVAL_EL1 registers.
25969 
25970                                                                  If this bit is 0 and there is a Secure EL1 access to one of
25971                                                                      the CNTPS registers:
25972                                                                   An exception is taken to EL3.
25973                                                                   The exception class for this exception, as returned in
25974                                                                      ESR_EL3[EC], is 0x18
25975                                                                  0 = These registers are only accessible in EL3.
25976                                                                  1 = These registers are accessible in EL3 and also in EL1 when
25977                                                                      AP_SCR_EL3[NS]==0. */
25978         uint32_t twi                   : 1;  /**< [ 12: 12](R/W) Trap WFI.
25979                                                                  0 = WFI instructions not trapped.
25980                                                                  1 = WFI instructions executed in AArch32 or AArch64 at EL2, EL1,
25981                                                                      or EL0 are trapped to EL3 if the instruction would otherwise
25982                                                                      cause suspension of execution. */
25983         uint32_t twe                   : 1;  /**< [ 13: 13](R/W) Trap WFE.
25984                                                                  0 = WFE instructions not trapped.
25985                                                                  1 = WFE instructions executed in AArch32 or AArch64 at EL2, EL1,
25986                                                                      or EL0 are trapped to EL3 if the instruction would otherwise
25987                                                                      cause suspension of execution, i.e. if there is not a pending
25988                                                                      WFI wakeup event and the instruciton does not cause another
25989                                                                      exception. */
25990         uint32_t tlor                  : 1;  /**< [ 14: 14](R/W) v8.1: Trap access to the LOR
25991                                                                  Registers from EL1 and EL2 to EL3, unless the access has been
25992                                                                  trapped to EL2:
25993                                                                  0 = EL1 and EL2 accesses to the LOR Registers are not trapped to EL3.
25994                                                                  1 = EL1 and EL2 accesses to the LOR Registers are trapped to EL3
25995                                                                      unless the access has been trapped to EL2 as a result of the
25996                                                                      AP_HCR_EL2[TLOR]. */
25997         uint32_t terr                  : 1;  /**< [ 15: 15](R/W) Trap Error record accesses.
25998                                                                    0 = Do not trap accesses to error record registers from EL1 and EL2 to EL3.
25999                                                                    1 = Accesses to the ER* registers from EL1 and EL2 generate a Trap exception to EL3. */
26000         uint32_t reserved_16_31        : 16;
26001 #endif /* Word 0 - End */
26002     } s;
26003     struct bdk_ap_scr_el3_cn8
26004     {
26005 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
26006         uint32_t reserved_15_31        : 17;
26007         uint32_t tlor                  : 1;  /**< [ 14: 14](R/W) v8.1: Trap access to the LOR
26008                                                                  Registers from EL1 and EL2 to EL3, unless the access has been
26009                                                                  trapped to EL2:
26010                                                                  0 = EL1 and EL2 accesses to the LOR Registers are not trapped to EL3.
26011                                                                  1 = EL1 and EL2 accesses to the LOR Registers are trapped to EL3
26012                                                                      unless the access has been trapped to EL2 as a result of the
26013                                                                      AP_HCR_EL2[TLOR]. */
26014         uint32_t twe                   : 1;  /**< [ 13: 13](R/W) Trap WFE.
26015                                                                  0 = WFE instructions not trapped.
26016                                                                  1 = WFE instructions executed in AArch32 or AArch64 at EL2, EL1,
26017                                                                      or EL0 are trapped to EL3 if the instruction would otherwise
26018                                                                      cause suspension of execution, i.e. if there is not a pending
26019                                                                      WFI wakeup event and the instruciton does not cause another
26020                                                                      exception. */
26021         uint32_t twi                   : 1;  /**< [ 12: 12](R/W) Trap WFI.
26022                                                                  0 = WFI instructions not trapped.
26023                                                                  1 = WFI instructions executed in AArch32 or AArch64 at EL2, EL1,
26024                                                                      or EL0 are trapped to EL3 if the instruction would otherwise
26025                                                                      cause suspension of execution. */
26026         uint32_t st                    : 1;  /**< [ 11: 11](R/W) Enables Secure EL1 access to the AP_CNTPS_TVAL_EL1,
26027                                                                      AP_CNTPS_CTL_EL1, and AP_CNTPS_CVAL_EL1 registers.
26028 
26029                                                                  If this bit is 0 and there is a Secure EL1 access to one of
26030                                                                      the CNTPS registers:
26031                                                                   An exception is taken to EL3.
26032                                                                   The exception class for this exception, as returned in
26033                                                                      ESR_EL3[EC], is 0x18
26034                                                                  0 = These registers are only accessible in EL3.
26035                                                                  1 = These registers are accessible in EL3 and also in EL1 when
26036                                                                      AP_SCR_EL3[NS]==0. */
26037         uint32_t rsvd_10               : 1;  /**< [ 10: 10](RO) Execution state control for lower Exception levels.
26038                                                                  This bit is permitted to be cached in a TLB.
26039                                                                  0 = Lower levels are all AArch32.
26040                                                                  1 = The next lower level is AArch64.
26041 
26042                                                                  If EL2 is present:
26043                                                                   EL2 is AArch64.
26044                                                                   EL2 controls EL1 and EL0 behaviors.
26045 
26046                                                                  If EL2 is not present:
26047                                                                   EL1 is AArch64.
26048                                                                   EL0 is determined by the Execution state described in the
26049                                                                      current process state when executing at EL0. */
26050         uint32_t sif                   : 1;  /**< [  9:  9](R/W) Secure instruction fetch. When the processor is in Secure
26051                                                                      state, this bit disables instruction fetch from nonsecure
26052                                                                      memory.
26053                                                                  This bit is permitted to be cached in a TLB.
26054                                                                  0 = Secure state instruction fetches from nonsecure memory are
26055                                                                      permitted.
26056                                                                  1 = Secure state instruction fetches from nonsecure memory are
26057                                                                      not permitted. */
26058         uint32_t hce                   : 1;  /**< [  8:  8](R/W) Hypervisor Call enable. This bit enables use of the HVC
26059                                                                      instruction from nonsecure EL1 modes.
26060 
26061                                                                  If EL3 is implemented but EL2 is not implemented, this bit is
26062                                                                      RES0.
26063                                                                  0 = HVC instruction is UNdefined in nonsecure EL1 modes, and
26064                                                                      either UNdefined or a NOP in Hyp mode, depending on the
26065                                                                      implementation.
26066                                                                  1 = HVC instruction is enabled in nonsecure EL1 modes, and
26067                                                                      performs a Hypervisor Call. */
26068         uint32_t smd                   : 1;  /**< [  7:  7](R/W) SMC Disable.
26069                                                                  0 = SMC is enabled at EL1, EL2, or EL3.
26070                                                                  1 = SMC is UNdefined at all Exception levels. At EL1 in the Non-
26071                                                                      secure state, the AP_HCR_EL2[TSC] bit has priority over this
26072                                                                      control. */
26073         uint32_t reserved_6            : 1;
26074         uint32_t rsvd_4_5              : 2;  /**< [  5:  4](RO) Reserved 1. */
26075         uint32_t ea                    : 1;  /**< [  3:  3](R/W) External Abort and SError Interrupt Routing.
26076                                                                  0 = External Aborts and SError Interrupts while executing at
26077                                                                      exception levels other than EL3 are not taken in EL3.
26078                                                                  1 = External Aborts and SError Interrupts while executing at all
26079                                                                      exception levels are taken in EL3. */
26080         uint32_t fiq                   : 1;  /**< [  2:  2](R/W) Physical FIQ Routing.
26081                                                                  0 = Physical FIQ while executing at exception levels other than
26082                                                                      EL3 are not taken in EL3.
26083                                                                  1 = Physical FIQ while executing at all exception levels are taken
26084                                                                      in EL3. */
26085         uint32_t irq                   : 1;  /**< [  1:  1](R/W) Physical IRQ Routing.
26086                                                                  0 = Physical IRQ while executing at exception levels other than
26087                                                                      EL3 are not taken in EL3.
26088                                                                  1 = Physical IRQ while executing at all exception levels are taken
26089                                                                      in EL3. */
26090         uint32_t nsec                  : 1;  /**< [  0:  0](R/W) Nonsecure bit.
26091                                                                  0 = Indicates that EL0 and EL1 are in Secure state, and so memory
26092                                                                      accesses from those Exception levels can access Secure memory.
26093                                                                  1 = Indicates that EL0 and EL1 are in nonsecure state, and so
26094                                                                      memory accesses from those Exception levels cannot access
26095                                                                      Secure memory. */
26096 #else /* Word 0 - Little Endian */
26097         uint32_t nsec                  : 1;  /**< [  0:  0](R/W) Nonsecure bit.
26098                                                                  0 = Indicates that EL0 and EL1 are in Secure state, and so memory
26099                                                                      accesses from those Exception levels can access Secure memory.
26100                                                                  1 = Indicates that EL0 and EL1 are in nonsecure state, and so
26101                                                                      memory accesses from those Exception levels cannot access
26102                                                                      Secure memory. */
26103         uint32_t irq                   : 1;  /**< [  1:  1](R/W) Physical IRQ Routing.
26104                                                                  0 = Physical IRQ while executing at exception levels other than
26105                                                                      EL3 are not taken in EL3.
26106                                                                  1 = Physical IRQ while executing at all exception levels are taken
26107                                                                      in EL3. */
26108         uint32_t fiq                   : 1;  /**< [  2:  2](R/W) Physical FIQ Routing.
26109                                                                  0 = Physical FIQ while executing at exception levels other than
26110                                                                      EL3 are not taken in EL3.
26111                                                                  1 = Physical FIQ while executing at all exception levels are taken
26112                                                                      in EL3. */
26113         uint32_t ea                    : 1;  /**< [  3:  3](R/W) External Abort and SError Interrupt Routing.
26114                                                                  0 = External Aborts and SError Interrupts while executing at
26115                                                                      exception levels other than EL3 are not taken in EL3.
26116                                                                  1 = External Aborts and SError Interrupts while executing at all
26117                                                                      exception levels are taken in EL3. */
26118         uint32_t rsvd_4_5              : 2;  /**< [  5:  4](RO) Reserved 1. */
26119         uint32_t reserved_6            : 1;
26120         uint32_t smd                   : 1;  /**< [  7:  7](R/W) SMC Disable.
26121                                                                  0 = SMC is enabled at EL1, EL2, or EL3.
26122                                                                  1 = SMC is UNdefined at all Exception levels. At EL1 in the Non-
26123                                                                      secure state, the AP_HCR_EL2[TSC] bit has priority over this
26124                                                                      control. */
26125         uint32_t hce                   : 1;  /**< [  8:  8](R/W) Hypervisor Call enable. This bit enables use of the HVC
26126                                                                      instruction from nonsecure EL1 modes.
26127 
26128                                                                  If EL3 is implemented but EL2 is not implemented, this bit is
26129                                                                      RES0.
26130                                                                  0 = HVC instruction is UNdefined in nonsecure EL1 modes, and
26131                                                                      either UNdefined or a NOP in Hyp mode, depending on the
26132                                                                      implementation.
26133                                                                  1 = HVC instruction is enabled in nonsecure EL1 modes, and
26134                                                                      performs a Hypervisor Call. */
26135         uint32_t sif                   : 1;  /**< [  9:  9](R/W) Secure instruction fetch. When the processor is in Secure
26136                                                                      state, this bit disables instruction fetch from nonsecure
26137                                                                      memory.
26138                                                                  This bit is permitted to be cached in a TLB.
26139                                                                  0 = Secure state instruction fetches from nonsecure memory are
26140                                                                      permitted.
26141                                                                  1 = Secure state instruction fetches from nonsecure memory are
26142                                                                      not permitted. */
26143         uint32_t rsvd_10               : 1;  /**< [ 10: 10](RO) Execution state control for lower Exception levels.
26144                                                                  This bit is permitted to be cached in a TLB.
26145                                                                  0 = Lower levels are all AArch32.
26146                                                                  1 = The next lower level is AArch64.
26147 
26148                                                                  If EL2 is present:
26149                                                                   EL2 is AArch64.
26150                                                                   EL2 controls EL1 and EL0 behaviors.
26151 
26152                                                                  If EL2 is not present:
26153                                                                   EL1 is AArch64.
26154                                                                   EL0 is determined by the Execution state described in the
26155                                                                      current process state when executing at EL0. */
26156         uint32_t st                    : 1;  /**< [ 11: 11](R/W) Enables Secure EL1 access to the AP_CNTPS_TVAL_EL1,
26157                                                                      AP_CNTPS_CTL_EL1, and AP_CNTPS_CVAL_EL1 registers.
26158 
26159                                                                  If this bit is 0 and there is a Secure EL1 access to one of
26160                                                                      the CNTPS registers:
26161                                                                   An exception is taken to EL3.
26162                                                                   The exception class for this exception, as returned in
26163                                                                      ESR_EL3[EC], is 0x18
26164                                                                  0 = These registers are only accessible in EL3.
26165                                                                  1 = These registers are accessible in EL3 and also in EL1 when
26166                                                                      AP_SCR_EL3[NS]==0. */
26167         uint32_t twi                   : 1;  /**< [ 12: 12](R/W) Trap WFI.
26168                                                                  0 = WFI instructions not trapped.
26169                                                                  1 = WFI instructions executed in AArch32 or AArch64 at EL2, EL1,
26170                                                                      or EL0 are trapped to EL3 if the instruction would otherwise
26171                                                                      cause suspension of execution. */
26172         uint32_t twe                   : 1;  /**< [ 13: 13](R/W) Trap WFE.
26173                                                                  0 = WFE instructions not trapped.
26174                                                                  1 = WFE instructions executed in AArch32 or AArch64 at EL2, EL1,
26175                                                                      or EL0 are trapped to EL3 if the instruction would otherwise
26176                                                                      cause suspension of execution, i.e. if there is not a pending
26177                                                                      WFI wakeup event and the instruciton does not cause another
26178                                                                      exception. */
26179         uint32_t tlor                  : 1;  /**< [ 14: 14](R/W) v8.1: Trap access to the LOR
26180                                                                  Registers from EL1 and EL2 to EL3, unless the access has been
26181                                                                  trapped to EL2:
26182                                                                  0 = EL1 and EL2 accesses to the LOR Registers are not trapped to EL3.
26183                                                                  1 = EL1 and EL2 accesses to the LOR Registers are trapped to EL3
26184                                                                      unless the access has been trapped to EL2 as a result of the
26185                                                                      AP_HCR_EL2[TLOR]. */
26186         uint32_t reserved_15_31        : 17;
26187 #endif /* Word 0 - End */
26188     } cn8;
26189     /* struct bdk_ap_scr_el3_s cn9; */
26190 };
26191 typedef union bdk_ap_scr_el3 bdk_ap_scr_el3_t;
26192 
26193 #define BDK_AP_SCR_EL3 BDK_AP_SCR_EL3_FUNC()
26194 static inline uint64_t BDK_AP_SCR_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SCR_EL3_FUNC(void)26195 static inline uint64_t BDK_AP_SCR_EL3_FUNC(void)
26196 {
26197     return 0x30601010000ll;
26198 }
26199 
26200 #define typedef_BDK_AP_SCR_EL3 bdk_ap_scr_el3_t
26201 #define bustype_BDK_AP_SCR_EL3 BDK_CSR_TYPE_SYSREG
26202 #define basename_BDK_AP_SCR_EL3 "AP_SCR_EL3"
26203 #define busnum_BDK_AP_SCR_EL3 0
26204 #define arguments_BDK_AP_SCR_EL3 -1,-1,-1,-1
26205 
26206 /**
26207  * Register (SYSREG) ap_sctlr_el1
26208  *
26209  * AP System Control EL1 Register
26210  * Provides top level control of the system, including its memory
26211  *     system, at EL1.
26212  */
26213 union bdk_ap_sctlr_el1
26214 {
26215     uint32_t u;
26216     struct bdk_ap_sctlr_el1_s
26217     {
26218 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
26219         uint32_t reserved_30_31        : 2;
26220         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
26221         uint32_t reserved_27           : 1;
26222         uint32_t uci                   : 1;  /**< [ 26: 26](R/W) When set, enables EL0 access in AArch64 for DC CVAU, DC CIVAC,
26223                                                                      DC CVAC, and IC IVAU instructions. */
26224         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
26225                                                                   Explicit data accesses at EL1.
26226                                                                   Stage 1 translation table walks at EL1 and EL0.
26227 
26228                                                                  If an implementation does not provide Big-endian support, this
26229                                                                      bit is RES0. If it does not provide Little-endian support,
26230                                                                      this bit is RES1.
26231                                                                  The EE bit is permitted to be cached in a TLB.
26232                                                                  0 = Little-endian.
26233                                                                  1 = Big-endian. */
26234         uint32_t e0e                   : 1;  /**< [ 24: 24](R/W) Endianness of explicit data accesses at EL0.
26235 
26236                                                                  If an implementation only supports Little-endian accesses at
26237                                                                      EL0 then this bit is RES0.
26238                                                                  If an implementation only supports Big-endian accesses at EL0
26239                                                                      then this bit is RES1.
26240                                                                  This bit has no effect on the endianness of LDTR* and STTR*
26241                                                                      instructions executed at EL1.
26242                                                                  0 = Explicit data accesses at EL0 are little-endian.
26243                                                                  1 = Explicit data accesses at EL0 are big-endian. */
26244         uint32_t span                  : 1;  /**< [ 23: 23](R/W) v8.1: Bit[23]: SPAN set PSTATE/CPSR[AP_PAN] bit on taking an exception
26245                                                                  to the EL1 exception level.
26246                                                                  0 = PSTATE/CPSR[AP_PAN] is set on taking an exception to the EL1 exception level.
26247                                                                  1 = PSTATE/CPSR[AP_PAN] is left unchanged on taking an exception to the EL1 exception
26248                                                                  level.
26249 
26250                                                                  This bit has no effect on the PSTATE/CPSR[AP_PAN] when taking exceptions to any other
26251                                                                  exception level. */
26252         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
26253         uint32_t reserved_21           : 1;
26254         uint32_t rsvd_20               : 1;  /**< [ 20: 20](RO) Reserved 1. */
26255         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
26256                                                                      used to require all memory regions with write permission to be
26257                                                                      treated as XN.
26258                                                                  The WXN bit is permitted to be cached in a TLB.
26259                                                                  0 = Regions with write permission are not forced to XN.
26260                                                                  1 = Regions with write permission are forced to XN. */
26261         uint32_t ntwe                  : 1;  /**< [ 18: 18](R/W) Not trap WFE.
26262                                                                  Conditional WFE instructions that fail their condition do not
26263                                                                      cause an exception if this bit is 0.
26264                                                                  0 = If a WFE instruction executed at EL0 would cause execution to
26265                                                                      be suspended, such as if the event register is not set and
26266                                                                      there is not a pending WFE wakeup event, it is taken as an
26267                                                                      exception to EL1 using the0x1
26268                                                                  1 = WFE instructions are executed as normal. */
26269         uint32_t reserved_17           : 1;
26270         uint32_t ntwi                  : 1;  /**< [ 16: 16](R/W) Not trap WFI.
26271                                                                  Conditional WFI instructions that fail their condition do not
26272                                                                      cause an exception if this bit is 0.
26273                                                                  0 = If a WFI instruction executed at EL0 would cause execution to
26274                                                                      be suspended, such as if there is not a pending WFI wakeup
26275                                                                      event, it is taken as an exception to EL1 using the0x1
26276                                                                  1 = WFI instructions are executed as normal. */
26277         uint32_t uct                   : 1;  /**< [ 15: 15](R/W) When set, enables EL0 access in AArch64 to the AP_CTR_EL0
26278                                                                      register. */
26279         uint32_t dze                   : 1;  /**< [ 14: 14](R/W) Access to DC ZVA instruction at EL0.
26280                                                                  0 = Execution of the DC ZVA instruction is prohibited at EL0, and
26281                                                                      it is treated as UNdefined at EL0.
26282                                                                  1 = Execution of the DC ZVA instruction is allowed at EL0. */
26283         uint32_t reserved_13           : 1;
26284         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
26285                                                                      instruction caches at EL0 and EL1:
26286                                                                  When this bit is 0, all EL1 and EL0 Normal memory instruction
26287                                                                      accesses are Non-cacheable.
26288                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
26289                                                                      EL1&0 translation regime is Cacheable regardless of the value
26290                                                                      of this bit.
26291                                                                  0 = Instruction caches disabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
26292                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
26293                                                                      translation regime are to Normal memory, Outer Shareable,
26294                                                                      Inner Non-cacheable, Outer Non-cacheable.
26295                                                                  1 = Instruction caches enabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
26296                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
26297                                                                      translation regime are to Normal memory, Outer Shareable,
26298                                                                      Inner Write-Through, Outer Write-Through. */
26299         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
26300         uint32_t reserved_10           : 1;
26301         uint32_t uma                   : 1;  /**< [  9:  9](R/W) User Mask Access. Controls access to interrupt masks from EL0,
26302                                                                      when EL0 is using AArch64.
26303                                                                  0 = Disable access to the interrupt masks from EL0.
26304                                                                  1 = Enable access to the interrupt masks from EL0. */
26305         uint32_t rsvd_8                : 1;  /**< [  8:  8](RO) SETEND Disable.
26306                                                                  If an implementation does not support mixed endian operation,
26307                                                                      this bit is RES1.
26308                                                                  0 = The SETEND instruction is available.
26309                                                                  1 = The SETEND instruction is UNALLOCATED.
26310 
26311                                                                  SED: SETEND Disable - Only supported with 32 bit. */
26312         uint32_t rsvd_7                : 1;  /**< [  7:  7](RO) "IT Disable.
26313                                                                  0 = The IT instruction functionality is available.
26314                                                                  1 = It is implementation defined whether the IT instruction is
26315                                                                      treated as either:
26316 
26317                                                                   A 16-bit instruction, which can only be followed by another
26318                                                                      16-bit instruction.
26319 
26320                                                                   The first half of a 32-bit instruction.
26321 
26322                                                                  An implementation might vary dynamically as to whether IT is
26323                                                                      treated as a 16-bit instruction or the first half of a 32-bit
26324                                                                      instruction.
26325                                                                  All encodings of the IT instruction with hw1[3:0]!=1000 are
26326                                                                      UNdefined and treated as unallocated.
26327                                                                  All encodings of the subsequent instruction with the following
26328                                                                      values for hw1 are UNdefined (and treated as unallocated):
26329 
26330                                                                  - 0b11xxxxxxxxxxxxxx: All 32-bit instructions, and the 16-bit
26331                                                                      instructions B, UDF, SVC, LDM, and STM.
26332                                                                  - 0b1x11xxxxxxxxxxxx: All instructions in.
26333                                                                  - 0b1x100xxxxxxxxxxx: ADD Rd, PC, #imm
26334                                                                  - 0b01001xxxxxxxxxxx: LDR Rd, [PC, #imm]
26335                                                                  - 0b0100x1xxx1111xxx: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX
26336                                                                      PC; BLX PC.
26337                                                                  - 0b010001xx1xxxx111: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This
26338                                                                      pattern also covers UNPREDICTABLE cases with BLX Rn.
26339 
26340                                                                  Contrary to the standard treatment of conditional UNdefined
26341                                                                      instructions in the ARM architecture, in this case these
26342                                                                      instructions are always treated as UNdefined, regardless of
26343                                                                      whether the instruction would pass or fail its condition codes
26344                                                                      as a result of being in an IT block.
26345 
26346                                                                  ITD: IT Disable - Only supported with 32 bit." */
26347         uint32_t reserved_5_6          : 2;
26348         uint32_t sa0                   : 1;  /**< [  4:  4](R/W) Stack Alignment Check Enable for EL0. When set, use of the
26349                                                                      stack pointer as the base address in a load/store instruction
26350                                                                      at EL0 must be aligned to a 16-byte boundary, or a Stack
26351                                                                      Alignment Fault exception will be raised. */
26352         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack Alignment Check Enable. When set, use of the stack
26353                                                                      pointer as the base address in a load/store instruction at
26354                                                                      this register's Exception level must be aligned to a 16-byte
26355                                                                      boundary, or a Stack Alignment Fault exception will be raised. */
26356         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
26357                                                                      caches at EL0 and EL1:
26358                                                                  When this bit is 0, all EL0 and EL1 Normal memory data
26359                                                                      accesses and all accesses to the EL1&0 stage 1 translation
26360                                                                      tables are Non-cacheable.
26361                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
26362                                                                      EL1&0 translation regime is Cacheable regardless of the value
26363                                                                      of the AP_SCTLR_EL1[C] bit.
26364                                                                  0 = Data and unified caches disabled.
26365                                                                  1 = Data and unified caches enabled. */
26366         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
26367                                                                      fault checking:
26368                                                                  Load/store exclusive and load-acquire/store-release
26369                                                                      instructions have an alignment check regardless of the value
26370                                                                      of the A bit.
26371                                                                  0 = Alignment fault checking disabled.
26372                                                                  Instructions that load or store one or more registers, other
26373                                                                      than load/store exclusive and load-acquire/store-release, do
26374                                                                      not check that the address being accessed is aligned to the
26375                                                                      size of the data element(s) being accessed.
26376                                                                  1 = Alignment fault checking enabled.
26377                                                                  All instructions that load or store one or more registers have
26378                                                                      an alignment check that the address being accessed is aligned
26379                                                                      to the size of the data element(s) being accessed. If this
26380                                                                      check fails it causes an Alignment fault, which is taken as a
26381                                                                      Data Abort exception. */
26382         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL1 and EL0 stage 1 address translation.
26383 
26384                                                                  If AP_HCR_EL2[DC] is set to 1, then in nonsecure state the
26385                                                                      AP_SCTLR_EL1[M] bit behaves as 0 for all purposes other than
26386                                                                      reading the value of the bit.
26387                                                                  0 = EL1 and EL0 stage 1 address translation disabled.
26388                                                                  1 = EL1 and EL0 stage 1 address translation enabled. */
26389 #else /* Word 0 - Little Endian */
26390         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL1 and EL0 stage 1 address translation.
26391 
26392                                                                  If AP_HCR_EL2[DC] is set to 1, then in nonsecure state the
26393                                                                      AP_SCTLR_EL1[M] bit behaves as 0 for all purposes other than
26394                                                                      reading the value of the bit.
26395                                                                  0 = EL1 and EL0 stage 1 address translation disabled.
26396                                                                  1 = EL1 and EL0 stage 1 address translation enabled. */
26397         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
26398                                                                      fault checking:
26399                                                                  Load/store exclusive and load-acquire/store-release
26400                                                                      instructions have an alignment check regardless of the value
26401                                                                      of the A bit.
26402                                                                  0 = Alignment fault checking disabled.
26403                                                                  Instructions that load or store one or more registers, other
26404                                                                      than load/store exclusive and load-acquire/store-release, do
26405                                                                      not check that the address being accessed is aligned to the
26406                                                                      size of the data element(s) being accessed.
26407                                                                  1 = Alignment fault checking enabled.
26408                                                                  All instructions that load or store one or more registers have
26409                                                                      an alignment check that the address being accessed is aligned
26410                                                                      to the size of the data element(s) being accessed. If this
26411                                                                      check fails it causes an Alignment fault, which is taken as a
26412                                                                      Data Abort exception. */
26413         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
26414                                                                      caches at EL0 and EL1:
26415                                                                  When this bit is 0, all EL0 and EL1 Normal memory data
26416                                                                      accesses and all accesses to the EL1&0 stage 1 translation
26417                                                                      tables are Non-cacheable.
26418                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
26419                                                                      EL1&0 translation regime is Cacheable regardless of the value
26420                                                                      of the AP_SCTLR_EL1[C] bit.
26421                                                                  0 = Data and unified caches disabled.
26422                                                                  1 = Data and unified caches enabled. */
26423         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack Alignment Check Enable. When set, use of the stack
26424                                                                      pointer as the base address in a load/store instruction at
26425                                                                      this register's Exception level must be aligned to a 16-byte
26426                                                                      boundary, or a Stack Alignment Fault exception will be raised. */
26427         uint32_t sa0                   : 1;  /**< [  4:  4](R/W) Stack Alignment Check Enable for EL0. When set, use of the
26428                                                                      stack pointer as the base address in a load/store instruction
26429                                                                      at EL0 must be aligned to a 16-byte boundary, or a Stack
26430                                                                      Alignment Fault exception will be raised. */
26431         uint32_t reserved_5_6          : 2;
26432         uint32_t rsvd_7                : 1;  /**< [  7:  7](RO) "IT Disable.
26433                                                                  0 = The IT instruction functionality is available.
26434                                                                  1 = It is implementation defined whether the IT instruction is
26435                                                                      treated as either:
26436 
26437                                                                   A 16-bit instruction, which can only be followed by another
26438                                                                      16-bit instruction.
26439 
26440                                                                   The first half of a 32-bit instruction.
26441 
26442                                                                  An implementation might vary dynamically as to whether IT is
26443                                                                      treated as a 16-bit instruction or the first half of a 32-bit
26444                                                                      instruction.
26445                                                                  All encodings of the IT instruction with hw1[3:0]!=1000 are
26446                                                                      UNdefined and treated as unallocated.
26447                                                                  All encodings of the subsequent instruction with the following
26448                                                                      values for hw1 are UNdefined (and treated as unallocated):
26449 
26450                                                                  - 0b11xxxxxxxxxxxxxx: All 32-bit instructions, and the 16-bit
26451                                                                      instructions B, UDF, SVC, LDM, and STM.
26452                                                                  - 0b1x11xxxxxxxxxxxx: All instructions in.
26453                                                                  - 0b1x100xxxxxxxxxxx: ADD Rd, PC, #imm
26454                                                                  - 0b01001xxxxxxxxxxx: LDR Rd, [PC, #imm]
26455                                                                  - 0b0100x1xxx1111xxx: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX
26456                                                                      PC; BLX PC.
26457                                                                  - 0b010001xx1xxxx111: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This
26458                                                                      pattern also covers UNPREDICTABLE cases with BLX Rn.
26459 
26460                                                                  Contrary to the standard treatment of conditional UNdefined
26461                                                                      instructions in the ARM architecture, in this case these
26462                                                                      instructions are always treated as UNdefined, regardless of
26463                                                                      whether the instruction would pass or fail its condition codes
26464                                                                      as a result of being in an IT block.
26465 
26466                                                                  ITD: IT Disable - Only supported with 32 bit." */
26467         uint32_t rsvd_8                : 1;  /**< [  8:  8](RO) SETEND Disable.
26468                                                                  If an implementation does not support mixed endian operation,
26469                                                                      this bit is RES1.
26470                                                                  0 = The SETEND instruction is available.
26471                                                                  1 = The SETEND instruction is UNALLOCATED.
26472 
26473                                                                  SED: SETEND Disable - Only supported with 32 bit. */
26474         uint32_t uma                   : 1;  /**< [  9:  9](R/W) User Mask Access. Controls access to interrupt masks from EL0,
26475                                                                      when EL0 is using AArch64.
26476                                                                  0 = Disable access to the interrupt masks from EL0.
26477                                                                  1 = Enable access to the interrupt masks from EL0. */
26478         uint32_t reserved_10           : 1;
26479         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
26480         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
26481                                                                      instruction caches at EL0 and EL1:
26482                                                                  When this bit is 0, all EL1 and EL0 Normal memory instruction
26483                                                                      accesses are Non-cacheable.
26484                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
26485                                                                      EL1&0 translation regime is Cacheable regardless of the value
26486                                                                      of this bit.
26487                                                                  0 = Instruction caches disabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
26488                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
26489                                                                      translation regime are to Normal memory, Outer Shareable,
26490                                                                      Inner Non-cacheable, Outer Non-cacheable.
26491                                                                  1 = Instruction caches enabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
26492                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
26493                                                                      translation regime are to Normal memory, Outer Shareable,
26494                                                                      Inner Write-Through, Outer Write-Through. */
26495         uint32_t reserved_13           : 1;
26496         uint32_t dze                   : 1;  /**< [ 14: 14](R/W) Access to DC ZVA instruction at EL0.
26497                                                                  0 = Execution of the DC ZVA instruction is prohibited at EL0, and
26498                                                                      it is treated as UNdefined at EL0.
26499                                                                  1 = Execution of the DC ZVA instruction is allowed at EL0. */
26500         uint32_t uct                   : 1;  /**< [ 15: 15](R/W) When set, enables EL0 access in AArch64 to the AP_CTR_EL0
26501                                                                      register. */
26502         uint32_t ntwi                  : 1;  /**< [ 16: 16](R/W) Not trap WFI.
26503                                                                  Conditional WFI instructions that fail their condition do not
26504                                                                      cause an exception if this bit is 0.
26505                                                                  0 = If a WFI instruction executed at EL0 would cause execution to
26506                                                                      be suspended, such as if there is not a pending WFI wakeup
26507                                                                      event, it is taken as an exception to EL1 using the0x1
26508                                                                  1 = WFI instructions are executed as normal. */
26509         uint32_t reserved_17           : 1;
26510         uint32_t ntwe                  : 1;  /**< [ 18: 18](R/W) Not trap WFE.
26511                                                                  Conditional WFE instructions that fail their condition do not
26512                                                                      cause an exception if this bit is 0.
26513                                                                  0 = If a WFE instruction executed at EL0 would cause execution to
26514                                                                      be suspended, such as if the event register is not set and
26515                                                                      there is not a pending WFE wakeup event, it is taken as an
26516                                                                      exception to EL1 using the0x1
26517                                                                  1 = WFE instructions are executed as normal. */
26518         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
26519                                                                      used to require all memory regions with write permission to be
26520                                                                      treated as XN.
26521                                                                  The WXN bit is permitted to be cached in a TLB.
26522                                                                  0 = Regions with write permission are not forced to XN.
26523                                                                  1 = Regions with write permission are forced to XN. */
26524         uint32_t rsvd_20               : 1;  /**< [ 20: 20](RO) Reserved 1. */
26525         uint32_t reserved_21           : 1;
26526         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
26527         uint32_t span                  : 1;  /**< [ 23: 23](R/W) v8.1: Bit[23]: SPAN set PSTATE/CPSR[AP_PAN] bit on taking an exception
26528                                                                  to the EL1 exception level.
26529                                                                  0 = PSTATE/CPSR[AP_PAN] is set on taking an exception to the EL1 exception level.
26530                                                                  1 = PSTATE/CPSR[AP_PAN] is left unchanged on taking an exception to the EL1 exception
26531                                                                  level.
26532 
26533                                                                  This bit has no effect on the PSTATE/CPSR[AP_PAN] when taking exceptions to any other
26534                                                                  exception level. */
26535         uint32_t e0e                   : 1;  /**< [ 24: 24](R/W) Endianness of explicit data accesses at EL0.
26536 
26537                                                                  If an implementation only supports Little-endian accesses at
26538                                                                      EL0 then this bit is RES0.
26539                                                                  If an implementation only supports Big-endian accesses at EL0
26540                                                                      then this bit is RES1.
26541                                                                  This bit has no effect on the endianness of LDTR* and STTR*
26542                                                                      instructions executed at EL1.
26543                                                                  0 = Explicit data accesses at EL0 are little-endian.
26544                                                                  1 = Explicit data accesses at EL0 are big-endian. */
26545         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
26546                                                                   Explicit data accesses at EL1.
26547                                                                   Stage 1 translation table walks at EL1 and EL0.
26548 
26549                                                                  If an implementation does not provide Big-endian support, this
26550                                                                      bit is RES0. If it does not provide Little-endian support,
26551                                                                      this bit is RES1.
26552                                                                  The EE bit is permitted to be cached in a TLB.
26553                                                                  0 = Little-endian.
26554                                                                  1 = Big-endian. */
26555         uint32_t uci                   : 1;  /**< [ 26: 26](R/W) When set, enables EL0 access in AArch64 for DC CVAU, DC CIVAC,
26556                                                                      DC CVAC, and IC IVAU instructions. */
26557         uint32_t reserved_27           : 1;
26558         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
26559         uint32_t reserved_30_31        : 2;
26560 #endif /* Word 0 - End */
26561     } s;
26562     struct bdk_ap_sctlr_el1_cn
26563     {
26564 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
26565         uint32_t reserved_30_31        : 2;
26566         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
26567         uint32_t reserved_27           : 1;
26568         uint32_t uci                   : 1;  /**< [ 26: 26](R/W) When set, enables EL0 access in AArch64 for DC CVAU, DC CIVAC,
26569                                                                      DC CVAC, and IC IVAU instructions. */
26570         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
26571                                                                   Explicit data accesses at EL1.
26572                                                                   Stage 1 translation table walks at EL1 and EL0.
26573 
26574                                                                  If an implementation does not provide Big-endian support, this
26575                                                                      bit is RES0. If it does not provide Little-endian support,
26576                                                                      this bit is RES1.
26577                                                                  The EE bit is permitted to be cached in a TLB.
26578                                                                  0 = Little-endian.
26579                                                                  1 = Big-endian. */
26580         uint32_t e0e                   : 1;  /**< [ 24: 24](R/W) Endianness of explicit data accesses at EL0.
26581 
26582                                                                  If an implementation only supports Little-endian accesses at
26583                                                                      EL0 then this bit is RES0.
26584                                                                  If an implementation only supports Big-endian accesses at EL0
26585                                                                      then this bit is RES1.
26586                                                                  This bit has no effect on the endianness of LDTR* and STTR*
26587                                                                      instructions executed at EL1.
26588                                                                  0 = Explicit data accesses at EL0 are little-endian.
26589                                                                  1 = Explicit data accesses at EL0 are big-endian. */
26590         uint32_t span                  : 1;  /**< [ 23: 23](R/W) v8.1: Bit[23]: SPAN set PSTATE/CPSR[AP_PAN] bit on taking an exception
26591                                                                  to the EL1 exception level.
26592                                                                  0 = PSTATE/CPSR[AP_PAN] is set on taking an exception to the EL1 exception level.
26593                                                                  1 = PSTATE/CPSR[AP_PAN] is left unchanged on taking an exception to the EL1 exception
26594                                                                  level.
26595 
26596                                                                  This bit has no effect on the PSTATE/CPSR[AP_PAN] when taking exceptions to any other
26597                                                                  exception level. */
26598         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
26599         uint32_t reserved_21           : 1;
26600         uint32_t rsvd_20               : 1;  /**< [ 20: 20](RO) Reserved 1. */
26601         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
26602                                                                      used to require all memory regions with write permission to be
26603                                                                      treated as XN.
26604                                                                  The WXN bit is permitted to be cached in a TLB.
26605                                                                  0 = Regions with write permission are not forced to XN.
26606                                                                  1 = Regions with write permission are forced to XN. */
26607         uint32_t ntwe                  : 1;  /**< [ 18: 18](R/W) Not trap WFE.
26608                                                                  Conditional WFE instructions that fail their condition do not
26609                                                                      cause an exception if this bit is 0.
26610                                                                  0 = If a WFE instruction executed at EL0 would cause execution to
26611                                                                      be suspended, such as if the event register is not set and
26612                                                                      there is not a pending WFE wakeup event, it is taken as an
26613                                                                      exception to EL1 using the0x1
26614                                                                  1 = WFE instructions are executed as normal. */
26615         uint32_t reserved_17           : 1;
26616         uint32_t ntwi                  : 1;  /**< [ 16: 16](R/W) Not trap WFI.
26617                                                                  Conditional WFI instructions that fail their condition do not
26618                                                                      cause an exception if this bit is 0.
26619                                                                  0 = If a WFI instruction executed at EL0 would cause execution to
26620                                                                      be suspended, such as if there is not a pending WFI wakeup
26621                                                                      event, it is taken as an exception to EL1 using the0x1
26622                                                                  1 = WFI instructions are executed as normal. */
26623         uint32_t uct                   : 1;  /**< [ 15: 15](R/W) When set, enables EL0 access in AArch64 to the AP_CTR_EL0
26624                                                                      register. */
26625         uint32_t dze                   : 1;  /**< [ 14: 14](R/W) Access to DC ZVA instruction at EL0.
26626                                                                  0 = Execution of the DC ZVA instruction is prohibited at EL0, and
26627                                                                      it is treated as UNdefined at EL0.
26628                                                                  1 = Execution of the DC ZVA instruction is allowed at EL0. */
26629         uint32_t reserved_13           : 1;
26630         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
26631                                                                      instruction caches at EL0 and EL1:
26632                                                                  When this bit is 0, all EL1 and EL0 Normal memory instruction
26633                                                                      accesses are Non-cacheable.
26634                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
26635                                                                      EL1&0 translation regime is Cacheable regardless of the value
26636                                                                      of this bit.
26637                                                                  0 = Instruction caches disabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
26638                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
26639                                                                      translation regime are to Normal memory, Outer Shareable,
26640                                                                      Inner Non-cacheable, Outer Non-cacheable.
26641                                                                  1 = Instruction caches enabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
26642                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
26643                                                                      translation regime are to Normal memory, Outer Shareable,
26644                                                                      Inner Write-Through, Outer Write-Through. */
26645         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
26646         uint32_t reserved_10           : 1;
26647         uint32_t uma                   : 1;  /**< [  9:  9](R/W) User Mask Access. Controls access to interrupt masks from EL0,
26648                                                                      when EL0 is using AArch64.
26649                                                                  0 = Disable access to the interrupt masks from EL0.
26650                                                                  1 = Enable access to the interrupt masks from EL0. */
26651         uint32_t rsvd_8                : 1;  /**< [  8:  8](RO) SETEND Disable.
26652                                                                  If an implementation does not support mixed endian operation,
26653                                                                      this bit is RES1.
26654                                                                  0 = The SETEND instruction is available.
26655                                                                  1 = The SETEND instruction is UNALLOCATED.
26656 
26657                                                                  SED: SETEND Disable - Only supported with 32 bit. */
26658         uint32_t rsvd_7                : 1;  /**< [  7:  7](RO) "IT Disable.
26659                                                                  0 = The IT instruction functionality is available.
26660                                                                  1 = It is implementation defined whether the IT instruction is
26661                                                                      treated as either:
26662 
26663                                                                   A 16-bit instruction, which can only be followed by another
26664                                                                      16-bit instruction.
26665 
26666                                                                   The first half of a 32-bit instruction.
26667 
26668                                                                  An implementation might vary dynamically as to whether IT is
26669                                                                      treated as a 16-bit instruction or the first half of a 32-bit
26670                                                                      instruction.
26671                                                                  All encodings of the IT instruction with hw1[3:0]!=1000 are
26672                                                                      UNdefined and treated as unallocated.
26673                                                                  All encodings of the subsequent instruction with the following
26674                                                                      values for hw1 are UNdefined (and treated as unallocated):
26675 
26676                                                                  - 0b11xxxxxxxxxxxxxx: All 32-bit instructions, and the 16-bit
26677                                                                      instructions B, UDF, SVC, LDM, and STM.
26678                                                                  - 0b1x11xxxxxxxxxxxx: All instructions in.
26679                                                                  - 0b1x100xxxxxxxxxxx: ADD Rd, PC, #imm
26680                                                                  - 0b01001xxxxxxxxxxx: LDR Rd, [PC, #imm]
26681                                                                  - 0b0100x1xxx1111xxx: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX
26682                                                                      PC; BLX PC.
26683                                                                  - 0b010001xx1xxxx111: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This
26684                                                                      pattern also covers UNPREDICTABLE cases with BLX Rn.
26685 
26686                                                                  Contrary to the standard treatment of conditional UNdefined
26687                                                                      instructions in the ARM architecture, in this case these
26688                                                                      instructions are always treated as UNdefined, regardless of
26689                                                                      whether the instruction would pass or fail its condition codes
26690                                                                      as a result of being in an IT block.
26691 
26692                                                                  ITD: IT Disable - Only supported with 32 bit." */
26693         uint32_t reserved_6            : 1;
26694         uint32_t reserved_5            : 1;
26695         uint32_t sa0                   : 1;  /**< [  4:  4](R/W) Stack Alignment Check Enable for EL0. When set, use of the
26696                                                                      stack pointer as the base address in a load/store instruction
26697                                                                      at EL0 must be aligned to a 16-byte boundary, or a Stack
26698                                                                      Alignment Fault exception will be raised. */
26699         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack Alignment Check Enable. When set, use of the stack
26700                                                                      pointer as the base address in a load/store instruction at
26701                                                                      this register's Exception level must be aligned to a 16-byte
26702                                                                      boundary, or a Stack Alignment Fault exception will be raised. */
26703         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
26704                                                                      caches at EL0 and EL1:
26705                                                                  When this bit is 0, all EL0 and EL1 Normal memory data
26706                                                                      accesses and all accesses to the EL1&0 stage 1 translation
26707                                                                      tables are Non-cacheable.
26708                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
26709                                                                      EL1&0 translation regime is Cacheable regardless of the value
26710                                                                      of the AP_SCTLR_EL1[C] bit.
26711                                                                  0 = Data and unified caches disabled.
26712                                                                  1 = Data and unified caches enabled. */
26713         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
26714                                                                      fault checking:
26715                                                                  Load/store exclusive and load-acquire/store-release
26716                                                                      instructions have an alignment check regardless of the value
26717                                                                      of the A bit.
26718                                                                  0 = Alignment fault checking disabled.
26719                                                                  Instructions that load or store one or more registers, other
26720                                                                      than load/store exclusive and load-acquire/store-release, do
26721                                                                      not check that the address being accessed is aligned to the
26722                                                                      size of the data element(s) being accessed.
26723                                                                  1 = Alignment fault checking enabled.
26724                                                                  All instructions that load or store one or more registers have
26725                                                                      an alignment check that the address being accessed is aligned
26726                                                                      to the size of the data element(s) being accessed. If this
26727                                                                      check fails it causes an Alignment fault, which is taken as a
26728                                                                      Data Abort exception. */
26729         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL1 and EL0 stage 1 address translation.
26730 
26731                                                                  If AP_HCR_EL2[DC] is set to 1, then in nonsecure state the
26732                                                                      AP_SCTLR_EL1[M] bit behaves as 0 for all purposes other than
26733                                                                      reading the value of the bit.
26734                                                                  0 = EL1 and EL0 stage 1 address translation disabled.
26735                                                                  1 = EL1 and EL0 stage 1 address translation enabled. */
26736 #else /* Word 0 - Little Endian */
26737         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL1 and EL0 stage 1 address translation.
26738 
26739                                                                  If AP_HCR_EL2[DC] is set to 1, then in nonsecure state the
26740                                                                      AP_SCTLR_EL1[M] bit behaves as 0 for all purposes other than
26741                                                                      reading the value of the bit.
26742                                                                  0 = EL1 and EL0 stage 1 address translation disabled.
26743                                                                  1 = EL1 and EL0 stage 1 address translation enabled. */
26744         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
26745                                                                      fault checking:
26746                                                                  Load/store exclusive and load-acquire/store-release
26747                                                                      instructions have an alignment check regardless of the value
26748                                                                      of the A bit.
26749                                                                  0 = Alignment fault checking disabled.
26750                                                                  Instructions that load or store one or more registers, other
26751                                                                      than load/store exclusive and load-acquire/store-release, do
26752                                                                      not check that the address being accessed is aligned to the
26753                                                                      size of the data element(s) being accessed.
26754                                                                  1 = Alignment fault checking enabled.
26755                                                                  All instructions that load or store one or more registers have
26756                                                                      an alignment check that the address being accessed is aligned
26757                                                                      to the size of the data element(s) being accessed. If this
26758                                                                      check fails it causes an Alignment fault, which is taken as a
26759                                                                      Data Abort exception. */
26760         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
26761                                                                      caches at EL0 and EL1:
26762                                                                  When this bit is 0, all EL0 and EL1 Normal memory data
26763                                                                      accesses and all accesses to the EL1&0 stage 1 translation
26764                                                                      tables are Non-cacheable.
26765                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
26766                                                                      EL1&0 translation regime is Cacheable regardless of the value
26767                                                                      of the AP_SCTLR_EL1[C] bit.
26768                                                                  0 = Data and unified caches disabled.
26769                                                                  1 = Data and unified caches enabled. */
26770         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack Alignment Check Enable. When set, use of the stack
26771                                                                      pointer as the base address in a load/store instruction at
26772                                                                      this register's Exception level must be aligned to a 16-byte
26773                                                                      boundary, or a Stack Alignment Fault exception will be raised. */
26774         uint32_t sa0                   : 1;  /**< [  4:  4](R/W) Stack Alignment Check Enable for EL0. When set, use of the
26775                                                                      stack pointer as the base address in a load/store instruction
26776                                                                      at EL0 must be aligned to a 16-byte boundary, or a Stack
26777                                                                      Alignment Fault exception will be raised. */
26778         uint32_t reserved_5            : 1;
26779         uint32_t reserved_6            : 1;
26780         uint32_t rsvd_7                : 1;  /**< [  7:  7](RO) "IT Disable.
26781                                                                  0 = The IT instruction functionality is available.
26782                                                                  1 = It is implementation defined whether the IT instruction is
26783                                                                      treated as either:
26784 
26785                                                                   A 16-bit instruction, which can only be followed by another
26786                                                                      16-bit instruction.
26787 
26788                                                                   The first half of a 32-bit instruction.
26789 
26790                                                                  An implementation might vary dynamically as to whether IT is
26791                                                                      treated as a 16-bit instruction or the first half of a 32-bit
26792                                                                      instruction.
26793                                                                  All encodings of the IT instruction with hw1[3:0]!=1000 are
26794                                                                      UNdefined and treated as unallocated.
26795                                                                  All encodings of the subsequent instruction with the following
26796                                                                      values for hw1 are UNdefined (and treated as unallocated):
26797 
26798                                                                  - 0b11xxxxxxxxxxxxxx: All 32-bit instructions, and the 16-bit
26799                                                                      instructions B, UDF, SVC, LDM, and STM.
26800                                                                  - 0b1x11xxxxxxxxxxxx: All instructions in.
26801                                                                  - 0b1x100xxxxxxxxxxx: ADD Rd, PC, #imm
26802                                                                  - 0b01001xxxxxxxxxxx: LDR Rd, [PC, #imm]
26803                                                                  - 0b0100x1xxx1111xxx: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX
26804                                                                      PC; BLX PC.
26805                                                                  - 0b010001xx1xxxx111: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This
26806                                                                      pattern also covers UNPREDICTABLE cases with BLX Rn.
26807 
26808                                                                  Contrary to the standard treatment of conditional UNdefined
26809                                                                      instructions in the ARM architecture, in this case these
26810                                                                      instructions are always treated as UNdefined, regardless of
26811                                                                      whether the instruction would pass or fail its condition codes
26812                                                                      as a result of being in an IT block.
26813 
26814                                                                  ITD: IT Disable - Only supported with 32 bit." */
26815         uint32_t rsvd_8                : 1;  /**< [  8:  8](RO) SETEND Disable.
26816                                                                  If an implementation does not support mixed endian operation,
26817                                                                      this bit is RES1.
26818                                                                  0 = The SETEND instruction is available.
26819                                                                  1 = The SETEND instruction is UNALLOCATED.
26820 
26821                                                                  SED: SETEND Disable - Only supported with 32 bit. */
26822         uint32_t uma                   : 1;  /**< [  9:  9](R/W) User Mask Access. Controls access to interrupt masks from EL0,
26823                                                                      when EL0 is using AArch64.
26824                                                                  0 = Disable access to the interrupt masks from EL0.
26825                                                                  1 = Enable access to the interrupt masks from EL0. */
26826         uint32_t reserved_10           : 1;
26827         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
26828         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
26829                                                                      instruction caches at EL0 and EL1:
26830                                                                  When this bit is 0, all EL1 and EL0 Normal memory instruction
26831                                                                      accesses are Non-cacheable.
26832                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
26833                                                                      EL1&0 translation regime is Cacheable regardless of the value
26834                                                                      of this bit.
26835                                                                  0 = Instruction caches disabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
26836                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
26837                                                                      translation regime are to Normal memory, Outer Shareable,
26838                                                                      Inner Non-cacheable, Outer Non-cacheable.
26839                                                                  1 = Instruction caches enabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
26840                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
26841                                                                      translation regime are to Normal memory, Outer Shareable,
26842                                                                      Inner Write-Through, Outer Write-Through. */
26843         uint32_t reserved_13           : 1;
26844         uint32_t dze                   : 1;  /**< [ 14: 14](R/W) Access to DC ZVA instruction at EL0.
26845                                                                  0 = Execution of the DC ZVA instruction is prohibited at EL0, and
26846                                                                      it is treated as UNdefined at EL0.
26847                                                                  1 = Execution of the DC ZVA instruction is allowed at EL0. */
26848         uint32_t uct                   : 1;  /**< [ 15: 15](R/W) When set, enables EL0 access in AArch64 to the AP_CTR_EL0
26849                                                                      register. */
26850         uint32_t ntwi                  : 1;  /**< [ 16: 16](R/W) Not trap WFI.
26851                                                                  Conditional WFI instructions that fail their condition do not
26852                                                                      cause an exception if this bit is 0.
26853                                                                  0 = If a WFI instruction executed at EL0 would cause execution to
26854                                                                      be suspended, such as if there is not a pending WFI wakeup
26855                                                                      event, it is taken as an exception to EL1 using the0x1
26856                                                                  1 = WFI instructions are executed as normal. */
26857         uint32_t reserved_17           : 1;
26858         uint32_t ntwe                  : 1;  /**< [ 18: 18](R/W) Not trap WFE.
26859                                                                  Conditional WFE instructions that fail their condition do not
26860                                                                      cause an exception if this bit is 0.
26861                                                                  0 = If a WFE instruction executed at EL0 would cause execution to
26862                                                                      be suspended, such as if the event register is not set and
26863                                                                      there is not a pending WFE wakeup event, it is taken as an
26864                                                                      exception to EL1 using the0x1
26865                                                                  1 = WFE instructions are executed as normal. */
26866         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
26867                                                                      used to require all memory regions with write permission to be
26868                                                                      treated as XN.
26869                                                                  The WXN bit is permitted to be cached in a TLB.
26870                                                                  0 = Regions with write permission are not forced to XN.
26871                                                                  1 = Regions with write permission are forced to XN. */
26872         uint32_t rsvd_20               : 1;  /**< [ 20: 20](RO) Reserved 1. */
26873         uint32_t reserved_21           : 1;
26874         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
26875         uint32_t span                  : 1;  /**< [ 23: 23](R/W) v8.1: Bit[23]: SPAN set PSTATE/CPSR[AP_PAN] bit on taking an exception
26876                                                                  to the EL1 exception level.
26877                                                                  0 = PSTATE/CPSR[AP_PAN] is set on taking an exception to the EL1 exception level.
26878                                                                  1 = PSTATE/CPSR[AP_PAN] is left unchanged on taking an exception to the EL1 exception
26879                                                                  level.
26880 
26881                                                                  This bit has no effect on the PSTATE/CPSR[AP_PAN] when taking exceptions to any other
26882                                                                  exception level. */
26883         uint32_t e0e                   : 1;  /**< [ 24: 24](R/W) Endianness of explicit data accesses at EL0.
26884 
26885                                                                  If an implementation only supports Little-endian accesses at
26886                                                                      EL0 then this bit is RES0.
26887                                                                  If an implementation only supports Big-endian accesses at EL0
26888                                                                      then this bit is RES1.
26889                                                                  This bit has no effect on the endianness of LDTR* and STTR*
26890                                                                      instructions executed at EL1.
26891                                                                  0 = Explicit data accesses at EL0 are little-endian.
26892                                                                  1 = Explicit data accesses at EL0 are big-endian. */
26893         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
26894                                                                   Explicit data accesses at EL1.
26895                                                                   Stage 1 translation table walks at EL1 and EL0.
26896 
26897                                                                  If an implementation does not provide Big-endian support, this
26898                                                                      bit is RES0. If it does not provide Little-endian support,
26899                                                                      this bit is RES1.
26900                                                                  The EE bit is permitted to be cached in a TLB.
26901                                                                  0 = Little-endian.
26902                                                                  1 = Big-endian. */
26903         uint32_t uci                   : 1;  /**< [ 26: 26](R/W) When set, enables EL0 access in AArch64 for DC CVAU, DC CIVAC,
26904                                                                      DC CVAC, and IC IVAU instructions. */
26905         uint32_t reserved_27           : 1;
26906         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
26907         uint32_t reserved_30_31        : 2;
26908 #endif /* Word 0 - End */
26909     } cn;
26910 };
26911 typedef union bdk_ap_sctlr_el1 bdk_ap_sctlr_el1_t;
26912 
26913 #define BDK_AP_SCTLR_EL1 BDK_AP_SCTLR_EL1_FUNC()
26914 static inline uint64_t BDK_AP_SCTLR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SCTLR_EL1_FUNC(void)26915 static inline uint64_t BDK_AP_SCTLR_EL1_FUNC(void)
26916 {
26917     return 0x30001000000ll;
26918 }
26919 
26920 #define typedef_BDK_AP_SCTLR_EL1 bdk_ap_sctlr_el1_t
26921 #define bustype_BDK_AP_SCTLR_EL1 BDK_CSR_TYPE_SYSREG
26922 #define basename_BDK_AP_SCTLR_EL1 "AP_SCTLR_EL1"
26923 #define busnum_BDK_AP_SCTLR_EL1 0
26924 #define arguments_BDK_AP_SCTLR_EL1 -1,-1,-1,-1
26925 
26926 /**
26927  * Register (SYSREG) ap_sctlr_el12
26928  *
26929  * AP System Control EL1/2 Register
26930  * Alias to allow access to AP_SCTLR_EL1 from EL2 when AP_HCR_EL2[E2H] is set.
26931  */
26932 union bdk_ap_sctlr_el12
26933 {
26934     uint32_t u;
26935     struct bdk_ap_sctlr_el12_s
26936     {
26937 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
26938         uint32_t reserved_0_31         : 32;
26939 #else /* Word 0 - Little Endian */
26940         uint32_t reserved_0_31         : 32;
26941 #endif /* Word 0 - End */
26942     } s;
26943     /* struct bdk_ap_sctlr_el12_s cn; */
26944 };
26945 typedef union bdk_ap_sctlr_el12 bdk_ap_sctlr_el12_t;
26946 
26947 #define BDK_AP_SCTLR_EL12 BDK_AP_SCTLR_EL12_FUNC()
26948 static inline uint64_t BDK_AP_SCTLR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SCTLR_EL12_FUNC(void)26949 static inline uint64_t BDK_AP_SCTLR_EL12_FUNC(void)
26950 {
26951     return 0x30501000000ll;
26952 }
26953 
26954 #define typedef_BDK_AP_SCTLR_EL12 bdk_ap_sctlr_el12_t
26955 #define bustype_BDK_AP_SCTLR_EL12 BDK_CSR_TYPE_SYSREG
26956 #define basename_BDK_AP_SCTLR_EL12 "AP_SCTLR_EL12"
26957 #define busnum_BDK_AP_SCTLR_EL12 0
26958 #define arguments_BDK_AP_SCTLR_EL12 -1,-1,-1,-1
26959 
26960 /**
26961  * Register (SYSREG) ap_sctlr_el2
26962  *
26963  * AP System Control Non-E2H Register
26964  * Provides top level control of the system, including its memory
26965  *     system, at EL2.
26966  *
26967  * This register is at the same select as AP_SCTLR_EL2_E2H and is used when E2H=0.
26968  */
26969 union bdk_ap_sctlr_el2
26970 {
26971     uint32_t u;
26972     struct bdk_ap_sctlr_el2_s
26973     {
26974 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
26975         uint32_t reserved_30_31        : 2;
26976         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
26977         uint32_t reserved_26_27        : 2;
26978         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
26979                                                                   Explicit data accesses at EL3.
26980                                                                   Stage 1 translation table walks at EL3.
26981 
26982                                                                  If an implementation does not provide Big-endian support, this
26983                                                                      bit is RES0. If it does not provide Little-endian support,
26984                                                                      this bit is RES1.
26985                                                                  The EE bit is permitted to be cached in a TLB.
26986                                                                  0 = Little-endian.
26987                                                                  1 = Big-endian. */
26988         uint32_t reserved_24           : 1;
26989         uint32_t span                  : 1;  /**< [ 23: 23](R/W) v8.1: Bit[23]: SPAN set PSTATE/CPSR[AP_PAN] bit on taking an exception
26990                                                                  to the EL* exception level.
26991                                                                  0 = PSTATE/CPSR[AP_PAN] is set on taking an exception to the EL* exception level.
26992                                                                  1 = PSTATE/CPSR[AP_PAN] is left unchanged on taking an exception to the EL* exception level.
26993 
26994                                                                  This bit has no effect on the PSTATE/CPSR[AP_PAN] when taking exceptions to any other
26995                                                                  exception level. */
26996         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
26997         uint32_t reserved_20_21        : 2;
26998         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
26999                                                                      used to require all memory regions with write permission to be
27000                                                                      treated as XN.
27001                                                                  The WXN bit is permitted to be cached in a TLB.
27002                                                                  0 = Regions with write permission are not forced to XN.
27003                                                                  1 = Regions with write permission are forced to XN. */
27004         uint32_t rsvd_18               : 1;  /**< [ 18: 18](RO) Reserved 1. */
27005         uint32_t reserved_17           : 1;
27006         uint32_t rsvd_16               : 1;  /**< [ 16: 16](RO) Reserved 1. */
27007         uint32_t reserved_13_15        : 3;
27008         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
27009                                                                      instruction caches at EL3.
27010                                                                  When this bit is 0, all EL3 Normal memory instruction accesses
27011                                                                      are Non-cacheable. This bit has no effect on the EL1&0 or EL2
27012                                                                      translation regimes.
27013                                                                  0 = Instruction caches disabled at EL3. If AP_SCTLR_EL3[M] is set to
27014                                                                      0, instruction accesses from stage 1 of the EL3 translation
27015                                                                      regime are to Normal memory, Outer Shareable, Inner Non-
27016                                                                      cacheable, Outer Non-cacheable.
27017                                                                  1 = Instruction caches enabled at EL3. If AP_SCTLR_EL3[M] is set to 0,
27018                                                                      instruction accesses from stage 1 of the EL3 translation
27019                                                                      regime are to Normal memory, Outer Shareable, Inner Write-
27020                                                                      Through, Outer Write-Through. */
27021         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
27022         uint32_t reserved_6_10         : 5;
27023         uint32_t rsvd_4_5              : 2;  /**< [  5:  4](RO) Reserved 1. */
27024         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack Alignment Check Enable. When set, use of the stack
27025                                                                      pointer as the base address in a load/store instruction at
27026                                                                      this register's Exception level must be aligned to a 16-byte
27027                                                                      boundary, or a Stack Alignment Fault exception will be raised. */
27028         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
27029                                                                      caches at EL3:
27030 
27031                                                                  When this bit is 0, all EL3 Normal memory data accesses and
27032                                                                      all accesses to the EL3 translation tables are Non-cacheable.
27033                                                                      This bit has no effect on the EL1&0 or EL2 translation
27034                                                                      regimes.
27035                                                                  0 = Data and unified caches disabled at EL3.
27036                                                                  1 = Data and unified caches enabled at EL3. */
27037         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
27038                                                                      fault checking:
27039 
27040                                                                  Load/store exclusive and load-acquire/store-release
27041                                                                      instructions have an alignment check regardless of the value
27042                                                                      of the A bit.
27043 
27044                                                                  0 = Alignment fault checking disabled.
27045                                                                  Instructions that load or store one or more registers, other
27046                                                                      than load/store exclusive and load-acquire/store-release, do
27047                                                                      not check that the address being accessed is aligned to the
27048                                                                      size of the data element(s) being accessed.
27049 
27050                                                                  1 = Alignment fault checking enabled.
27051                                                                  All instructions that load or store one or more registers have
27052                                                                      an alignment check that the address being accessed is aligned
27053                                                                      to the size of the data element(s) being accessed. If this
27054                                                                      check fails it causes an Alignment fault, which is taken as a
27055                                                                      Data Abort exception. */
27056         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL3 stage 1 address translation.
27057                                                                  0 = EL3 stage 1 address translation disabled.
27058                                                                  1 = EL3 stage 1 address translation enabled. */
27059 #else /* Word 0 - Little Endian */
27060         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL3 stage 1 address translation.
27061                                                                  0 = EL3 stage 1 address translation disabled.
27062                                                                  1 = EL3 stage 1 address translation enabled. */
27063         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
27064                                                                      fault checking:
27065 
27066                                                                  Load/store exclusive and load-acquire/store-release
27067                                                                      instructions have an alignment check regardless of the value
27068                                                                      of the A bit.
27069 
27070                                                                  0 = Alignment fault checking disabled.
27071                                                                  Instructions that load or store one or more registers, other
27072                                                                      than load/store exclusive and load-acquire/store-release, do
27073                                                                      not check that the address being accessed is aligned to the
27074                                                                      size of the data element(s) being accessed.
27075 
27076                                                                  1 = Alignment fault checking enabled.
27077                                                                  All instructions that load or store one or more registers have
27078                                                                      an alignment check that the address being accessed is aligned
27079                                                                      to the size of the data element(s) being accessed. If this
27080                                                                      check fails it causes an Alignment fault, which is taken as a
27081                                                                      Data Abort exception. */
27082         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
27083                                                                      caches at EL3:
27084 
27085                                                                  When this bit is 0, all EL3 Normal memory data accesses and
27086                                                                      all accesses to the EL3 translation tables are Non-cacheable.
27087                                                                      This bit has no effect on the EL1&0 or EL2 translation
27088                                                                      regimes.
27089                                                                  0 = Data and unified caches disabled at EL3.
27090                                                                  1 = Data and unified caches enabled at EL3. */
27091         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack Alignment Check Enable. When set, use of the stack
27092                                                                      pointer as the base address in a load/store instruction at
27093                                                                      this register's Exception level must be aligned to a 16-byte
27094                                                                      boundary, or a Stack Alignment Fault exception will be raised. */
27095         uint32_t rsvd_4_5              : 2;  /**< [  5:  4](RO) Reserved 1. */
27096         uint32_t reserved_6_10         : 5;
27097         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
27098         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
27099                                                                      instruction caches at EL3.
27100                                                                  When this bit is 0, all EL3 Normal memory instruction accesses
27101                                                                      are Non-cacheable. This bit has no effect on the EL1&0 or EL2
27102                                                                      translation regimes.
27103                                                                  0 = Instruction caches disabled at EL3. If AP_SCTLR_EL3[M] is set to
27104                                                                      0, instruction accesses from stage 1 of the EL3 translation
27105                                                                      regime are to Normal memory, Outer Shareable, Inner Non-
27106                                                                      cacheable, Outer Non-cacheable.
27107                                                                  1 = Instruction caches enabled at EL3. If AP_SCTLR_EL3[M] is set to 0,
27108                                                                      instruction accesses from stage 1 of the EL3 translation
27109                                                                      regime are to Normal memory, Outer Shareable, Inner Write-
27110                                                                      Through, Outer Write-Through. */
27111         uint32_t reserved_13_15        : 3;
27112         uint32_t rsvd_16               : 1;  /**< [ 16: 16](RO) Reserved 1. */
27113         uint32_t reserved_17           : 1;
27114         uint32_t rsvd_18               : 1;  /**< [ 18: 18](RO) Reserved 1. */
27115         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
27116                                                                      used to require all memory regions with write permission to be
27117                                                                      treated as XN.
27118                                                                  The WXN bit is permitted to be cached in a TLB.
27119                                                                  0 = Regions with write permission are not forced to XN.
27120                                                                  1 = Regions with write permission are forced to XN. */
27121         uint32_t reserved_20_21        : 2;
27122         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
27123         uint32_t span                  : 1;  /**< [ 23: 23](R/W) v8.1: Bit[23]: SPAN set PSTATE/CPSR[AP_PAN] bit on taking an exception
27124                                                                  to the EL* exception level.
27125                                                                  0 = PSTATE/CPSR[AP_PAN] is set on taking an exception to the EL* exception level.
27126                                                                  1 = PSTATE/CPSR[AP_PAN] is left unchanged on taking an exception to the EL* exception level.
27127 
27128                                                                  This bit has no effect on the PSTATE/CPSR[AP_PAN] when taking exceptions to any other
27129                                                                  exception level. */
27130         uint32_t reserved_24           : 1;
27131         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
27132                                                                   Explicit data accesses at EL3.
27133                                                                   Stage 1 translation table walks at EL3.
27134 
27135                                                                  If an implementation does not provide Big-endian support, this
27136                                                                      bit is RES0. If it does not provide Little-endian support,
27137                                                                      this bit is RES1.
27138                                                                  The EE bit is permitted to be cached in a TLB.
27139                                                                  0 = Little-endian.
27140                                                                  1 = Big-endian. */
27141         uint32_t reserved_26_27        : 2;
27142         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
27143         uint32_t reserved_30_31        : 2;
27144 #endif /* Word 0 - End */
27145     } s;
27146     /* struct bdk_ap_sctlr_el2_s cn; */
27147 };
27148 typedef union bdk_ap_sctlr_el2 bdk_ap_sctlr_el2_t;
27149 
27150 #define BDK_AP_SCTLR_EL2 BDK_AP_SCTLR_EL2_FUNC()
27151 static inline uint64_t BDK_AP_SCTLR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SCTLR_EL2_FUNC(void)27152 static inline uint64_t BDK_AP_SCTLR_EL2_FUNC(void)
27153 {
27154     return 0x30401000000ll;
27155 }
27156 
27157 #define typedef_BDK_AP_SCTLR_EL2 bdk_ap_sctlr_el2_t
27158 #define bustype_BDK_AP_SCTLR_EL2 BDK_CSR_TYPE_SYSREG
27159 #define basename_BDK_AP_SCTLR_EL2 "AP_SCTLR_EL2"
27160 #define busnum_BDK_AP_SCTLR_EL2 0
27161 #define arguments_BDK_AP_SCTLR_EL2 -1,-1,-1,-1
27162 
27163 /**
27164  * Register (SYSREG) ap_sctlr_el2_e2h
27165  *
27166  * AP System Control E2H Register
27167  * Provides top level control of the system, including its memory
27168  *     system, at EL2.
27169  *
27170  * This register is at the same select as AP_SCTLR_EL2 and is used when E2H=1.
27171  */
27172 union bdk_ap_sctlr_el2_e2h
27173 {
27174     uint32_t u;
27175     struct bdk_ap_sctlr_el2_e2h_s
27176     {
27177 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
27178         uint32_t reserved_30_31        : 2;
27179         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
27180         uint32_t reserved_27           : 1;
27181         uint32_t uci                   : 1;  /**< [ 26: 26](R/W) When set, enables EL0 access in AArch64 for DC CVAU, DC CIVAC,
27182                                                                      DC CVAC, and IC IVAU instructions. */
27183         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
27184                                                                   Explicit data accesses at EL1.
27185                                                                   Stage 1 translation table walks at EL1 and EL0.
27186 
27187                                                                  If an implementation does not provide Big-endian support, this
27188                                                                      bit is RES0. If it does not provide Little-endian support,
27189                                                                      this bit is RES1.
27190 
27191                                                                  The EE bit is permitted to be cached in a TLB.
27192 
27193                                                                  0 = Little-endian.
27194                                                                  1 = Big-endian. */
27195         uint32_t e0e                   : 1;  /**< [ 24: 24](R/W) Endianness of explicit data accesses at EL0.
27196 
27197                                                                  If an implementation only supports Little-endian accesses at
27198                                                                      EL0 then this bit is RES0.
27199 
27200                                                                  If an implementation only supports Big-endian accesses at EL0
27201                                                                      then this bit is RES1.
27202 
27203                                                                  This bit has no effect on the endianness of LDTR* and STTR*
27204                                                                      instructions executed at EL1.
27205 
27206                                                                  0 = Explicit data accesses at EL0 are little-endian.
27207                                                                  1 = Explicit data accesses at EL0 are big-endian. */
27208         uint32_t span                  : 1;  /**< [ 23: 23](R/W) v8.1: Bit[23]: SPAN set PSTATE/CPSR[AP_PAN] bit on taking an exception
27209                                                                  to the EL1 exception level.
27210                                                                  0 = PSTATE/CPSR[AP_PAN] is set on taking an exception to the EL1 exception level
27211                                                                  1 = PSTATE/CPSR[AP_PAN] is left unchanged on taking an exception to the EL1 exception
27212                                                                  level
27213 
27214                                                                  This bit has no effect on the PSTATE/CPSR[AP_PAN] when taking exceptions to any other
27215                                                                  exception level. */
27216         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
27217         uint32_t reserved_21           : 1;
27218         uint32_t rsvd_20               : 1;  /**< [ 20: 20](RO) Reserved 1. */
27219         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
27220                                                                      used to require all memory regions with write permission to be
27221                                                                      treated as XN.
27222 
27223                                                                  The WXN bit is permitted to be cached in a TLB.
27224 
27225                                                                  0 = Regions with write permission are not forced to XN.
27226                                                                  1 = Regions with write permission are forced to XN. */
27227         uint32_t ntwe                  : 1;  /**< [ 18: 18](R/W) Not trap WFE.
27228                                                                  Conditional WFE instructions that fail their condition do not
27229                                                                      cause an exception if this bit is 0.
27230                                                                  0 = If a WFE instruction executed at EL0 would cause execution to
27231                                                                      be suspended, such as if the event register is not set and
27232                                                                      there is not a pending WFE wakeup event, it is taken as an
27233                                                                      exception to EL1 using the0x1
27234                                                                  1 = WFE instructions are executed as normal. */
27235         uint32_t reserved_17           : 1;
27236         uint32_t ntwi                  : 1;  /**< [ 16: 16](R/W) Not trap WFI.
27237                                                                  Conditional WFI instructions that fail their condition do not
27238                                                                      cause an exception if this bit is 0.
27239                                                                  0 = If a WFI instruction executed at EL0 would cause execution to
27240                                                                      be suspended, such as if there is not a pending WFI wakeup
27241                                                                      event, it is taken as an exception to EL1 using the0x1
27242                                                                  1 = WFI instructions are executed as normal. */
27243         uint32_t uct                   : 1;  /**< [ 15: 15](R/W) When set, enables EL0 access in AArch64 to the AP_CTR_EL0
27244                                                                      register. */
27245         uint32_t dze                   : 1;  /**< [ 14: 14](R/W) Access to DC ZVA instruction at EL0.
27246                                                                  0 = Execution of the DC ZVA instruction is prohibited at EL0, and
27247                                                                      it is treated as undefined at EL0.
27248                                                                  1 = Execution of the DC ZVA instruction is allowed at EL0. */
27249         uint32_t reserved_13           : 1;
27250         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
27251                                                                      instruction caches at EL0 and EL1:
27252                                                                  When this bit is 0, all EL1 and EL0 Normal memory instruction
27253                                                                      accesses are Non-cacheable.
27254                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
27255                                                                      EL1&0 translation regime is Cacheable regardless of the value
27256                                                                      of this bit.
27257                                                                  0 = Instruction caches disabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
27258                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
27259                                                                      translation regime are to Normal memory, Outer Shareable,
27260                                                                      Inner Non-cacheable, Outer Non-cacheable.
27261                                                                  1 = Instruction caches enabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
27262                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
27263                                                                      translation regime are to Normal memory, Outer Shareable,
27264                                                                      Inner Write-Through, Outer Write-Through. */
27265         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
27266         uint32_t reserved_10           : 1;
27267         uint32_t uma                   : 1;  /**< [  9:  9](R/W) User Mask Access. Controls access to interrupt masks from EL0,
27268                                                                      when EL0 is using AArch64.
27269                                                                  0 = Disable access to the interrupt masks from EL0.
27270                                                                  1 = Enable access to the interrupt masks from EL0. */
27271         uint32_t rsvd_8                : 1;  /**< [  8:  8](RO) SETEND disable.
27272                                                                  If an implementation does not support mixed endian operation,
27273                                                                      this bit is RES1.
27274                                                                  0 = The SETEND instruction is available.
27275                                                                  1 = The SETEND instruction is UNALLOCATED.
27276 
27277                                                                  SED: SETEND Disable - Only supported with 32 bit */
27278         uint32_t rsvd_7                : 1;  /**< [  7:  7](RO) "IT Disable.
27279                                                                  0 = The IT instruction functionality is available.
27280                                                                  1 = It is implementation defined whether the IT instruction is
27281                                                                      treated as either:
27282                                                                  * A 16-bit instruction, which can only be followed by another
27283                                                                      16-bit instruction.
27284                                                                  * The first half of a 32-bit instruction.
27285 
27286                                                                  An implementation might vary dynamically as to whether IT is
27287                                                                      treated as a 16-bit instruction or the first half of a 32-bit
27288                                                                      instruction.
27289 
27290                                                                  All encodings of the IT instruction with hw1[3:0]!=1000 are
27291                                                                      UNdefined and treated as unallocated.
27292 
27293                                                                  All encodings of the subsequent instruction with the following
27294                                                                      values for hw1 are UNdefined (and treated as unallocated):
27295 
27296                                                                  - 0b11xxxxxxxxxxxxxx: All 32-bit instructions, and the 16-bit
27297                                                                      instructions B, UDF, SVC, LDM, and STM.
27298 
27299                                                                  - 0b1x11xxxxxxxxxxxx: All instructions in.
27300 
27301                                                                  - 0b1x100xxxxxxxxxxx: ADD Rd, PC, #imm
27302 
27303                                                                  - 0b01001xxxxxxxxxxx: LDR Rd, [PC, #imm]
27304 
27305                                                                  - 0b0100x1xxx1111xxx: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX
27306                                                                      PC; BLX PC.
27307 
27308                                                                  - 0b010001xx1xxxx111: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This
27309                                                                      pattern also covers UNPREDICTABLE cases with BLX Rn.
27310 
27311                                                                  Contrary to the standard treatment of conditional UNdefined
27312                                                                      instructions in the ARM architecture, in this case these
27313                                                                      instructions are always treated as UNdefined, regardless of
27314                                                                      whether the instruction would pass or fail its condition codes
27315                                                                      as a result of being in an IT block.
27316 
27317                                                                  ITD: IT Disable - Only supported with 32 bit" */
27318         uint32_t reserved_5_6          : 2;
27319         uint32_t sa0                   : 1;  /**< [  4:  4](R/W) Stack Alignment Check Enable for EL0. When set, use of the
27320                                                                      stack pointer as the base address in a load/store instruction
27321                                                                      at EL0 must be aligned to a 16-byte boundary, or a Stack
27322                                                                      Alignment Fault exception will be raised. */
27323         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack Alignment Check Enable. When set, use of the stack
27324                                                                      pointer as the base address in a load/store instruction at
27325                                                                      this register's Exception level must be aligned to a 16-byte
27326                                                                      boundary, or a Stack Alignment Fault exception will be raised. */
27327         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
27328                                                                      caches at EL0 and EL1:
27329                                                                  When this bit is 0, all EL0 and EL1 Normal memory data
27330                                                                      accesses and all accesses to the EL1&0 stage 1 translation
27331                                                                      tables are Non-cacheable.
27332                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
27333                                                                      EL1&0 translation regime is Cacheable regardless of the value
27334                                                                      of the AP_SCTLR_EL1[C] bit.
27335                                                                  0 = Data and unified caches disabled.
27336                                                                  1 = Data and unified caches enabled. */
27337         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
27338                                                                      fault checking.
27339 
27340                                                                  Load/store exclusive and load-acquire/store-release
27341                                                                      instructions have an alignment check regardless of the value
27342                                                                      of the A bit.
27343 
27344                                                                  0 = Alignment fault checking disabled.
27345                                                                  Instructions that load or store one or more registers, other
27346                                                                      than load/store exclusive and load-acquire/store-release, do
27347                                                                      not check that the address being accessed is aligned to the
27348                                                                      size of the data element(s) being accessed.
27349 
27350                                                                  1 = Alignment fault checking enabled.
27351                                                                  All instructions that load or store one or more registers have
27352                                                                      an alignment check that the address being accessed is aligned
27353                                                                      to the size of the data element(s) being accessed. If this
27354                                                                      check fails it causes an Alignment fault, which is taken as a
27355                                                                      Data Abort exception. */
27356         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL1 and EL0 stage 1 address translation.
27357 
27358                                                                  If AP_HCR_EL2[DC] is set to 1, then in nonsecure state the
27359                                                                      AP_SCTLR_EL1[M] bit behaves as 0 for all purposes other than
27360                                                                      reading the value of the bit.
27361                                                                  0 = EL1 and EL0 stage 1 address translation disabled.
27362                                                                  1 = EL1 and EL0 stage 1 address translation enabled. */
27363 #else /* Word 0 - Little Endian */
27364         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL1 and EL0 stage 1 address translation.
27365 
27366                                                                  If AP_HCR_EL2[DC] is set to 1, then in nonsecure state the
27367                                                                      AP_SCTLR_EL1[M] bit behaves as 0 for all purposes other than
27368                                                                      reading the value of the bit.
27369                                                                  0 = EL1 and EL0 stage 1 address translation disabled.
27370                                                                  1 = EL1 and EL0 stage 1 address translation enabled. */
27371         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
27372                                                                      fault checking.
27373 
27374                                                                  Load/store exclusive and load-acquire/store-release
27375                                                                      instructions have an alignment check regardless of the value
27376                                                                      of the A bit.
27377 
27378                                                                  0 = Alignment fault checking disabled.
27379                                                                  Instructions that load or store one or more registers, other
27380                                                                      than load/store exclusive and load-acquire/store-release, do
27381                                                                      not check that the address being accessed is aligned to the
27382                                                                      size of the data element(s) being accessed.
27383 
27384                                                                  1 = Alignment fault checking enabled.
27385                                                                  All instructions that load or store one or more registers have
27386                                                                      an alignment check that the address being accessed is aligned
27387                                                                      to the size of the data element(s) being accessed. If this
27388                                                                      check fails it causes an Alignment fault, which is taken as a
27389                                                                      Data Abort exception. */
27390         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
27391                                                                      caches at EL0 and EL1:
27392                                                                  When this bit is 0, all EL0 and EL1 Normal memory data
27393                                                                      accesses and all accesses to the EL1&0 stage 1 translation
27394                                                                      tables are Non-cacheable.
27395                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
27396                                                                      EL1&0 translation regime is Cacheable regardless of the value
27397                                                                      of the AP_SCTLR_EL1[C] bit.
27398                                                                  0 = Data and unified caches disabled.
27399                                                                  1 = Data and unified caches enabled. */
27400         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack Alignment Check Enable. When set, use of the stack
27401                                                                      pointer as the base address in a load/store instruction at
27402                                                                      this register's Exception level must be aligned to a 16-byte
27403                                                                      boundary, or a Stack Alignment Fault exception will be raised. */
27404         uint32_t sa0                   : 1;  /**< [  4:  4](R/W) Stack Alignment Check Enable for EL0. When set, use of the
27405                                                                      stack pointer as the base address in a load/store instruction
27406                                                                      at EL0 must be aligned to a 16-byte boundary, or a Stack
27407                                                                      Alignment Fault exception will be raised. */
27408         uint32_t reserved_5_6          : 2;
27409         uint32_t rsvd_7                : 1;  /**< [  7:  7](RO) "IT Disable.
27410                                                                  0 = The IT instruction functionality is available.
27411                                                                  1 = It is implementation defined whether the IT instruction is
27412                                                                      treated as either:
27413                                                                  * A 16-bit instruction, which can only be followed by another
27414                                                                      16-bit instruction.
27415                                                                  * The first half of a 32-bit instruction.
27416 
27417                                                                  An implementation might vary dynamically as to whether IT is
27418                                                                      treated as a 16-bit instruction or the first half of a 32-bit
27419                                                                      instruction.
27420 
27421                                                                  All encodings of the IT instruction with hw1[3:0]!=1000 are
27422                                                                      UNdefined and treated as unallocated.
27423 
27424                                                                  All encodings of the subsequent instruction with the following
27425                                                                      values for hw1 are UNdefined (and treated as unallocated):
27426 
27427                                                                  - 0b11xxxxxxxxxxxxxx: All 32-bit instructions, and the 16-bit
27428                                                                      instructions B, UDF, SVC, LDM, and STM.
27429 
27430                                                                  - 0b1x11xxxxxxxxxxxx: All instructions in.
27431 
27432                                                                  - 0b1x100xxxxxxxxxxx: ADD Rd, PC, #imm
27433 
27434                                                                  - 0b01001xxxxxxxxxxx: LDR Rd, [PC, #imm]
27435 
27436                                                                  - 0b0100x1xxx1111xxx: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX
27437                                                                      PC; BLX PC.
27438 
27439                                                                  - 0b010001xx1xxxx111: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This
27440                                                                      pattern also covers UNPREDICTABLE cases with BLX Rn.
27441 
27442                                                                  Contrary to the standard treatment of conditional UNdefined
27443                                                                      instructions in the ARM architecture, in this case these
27444                                                                      instructions are always treated as UNdefined, regardless of
27445                                                                      whether the instruction would pass or fail its condition codes
27446                                                                      as a result of being in an IT block.
27447 
27448                                                                  ITD: IT Disable - Only supported with 32 bit" */
27449         uint32_t rsvd_8                : 1;  /**< [  8:  8](RO) SETEND disable.
27450                                                                  If an implementation does not support mixed endian operation,
27451                                                                      this bit is RES1.
27452                                                                  0 = The SETEND instruction is available.
27453                                                                  1 = The SETEND instruction is UNALLOCATED.
27454 
27455                                                                  SED: SETEND Disable - Only supported with 32 bit */
27456         uint32_t uma                   : 1;  /**< [  9:  9](R/W) User Mask Access. Controls access to interrupt masks from EL0,
27457                                                                      when EL0 is using AArch64.
27458                                                                  0 = Disable access to the interrupt masks from EL0.
27459                                                                  1 = Enable access to the interrupt masks from EL0. */
27460         uint32_t reserved_10           : 1;
27461         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
27462         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
27463                                                                      instruction caches at EL0 and EL1:
27464                                                                  When this bit is 0, all EL1 and EL0 Normal memory instruction
27465                                                                      accesses are Non-cacheable.
27466                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
27467                                                                      EL1&0 translation regime is Cacheable regardless of the value
27468                                                                      of this bit.
27469                                                                  0 = Instruction caches disabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
27470                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
27471                                                                      translation regime are to Normal memory, Outer Shareable,
27472                                                                      Inner Non-cacheable, Outer Non-cacheable.
27473                                                                  1 = Instruction caches enabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
27474                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
27475                                                                      translation regime are to Normal memory, Outer Shareable,
27476                                                                      Inner Write-Through, Outer Write-Through. */
27477         uint32_t reserved_13           : 1;
27478         uint32_t dze                   : 1;  /**< [ 14: 14](R/W) Access to DC ZVA instruction at EL0.
27479                                                                  0 = Execution of the DC ZVA instruction is prohibited at EL0, and
27480                                                                      it is treated as undefined at EL0.
27481                                                                  1 = Execution of the DC ZVA instruction is allowed at EL0. */
27482         uint32_t uct                   : 1;  /**< [ 15: 15](R/W) When set, enables EL0 access in AArch64 to the AP_CTR_EL0
27483                                                                      register. */
27484         uint32_t ntwi                  : 1;  /**< [ 16: 16](R/W) Not trap WFI.
27485                                                                  Conditional WFI instructions that fail their condition do not
27486                                                                      cause an exception if this bit is 0.
27487                                                                  0 = If a WFI instruction executed at EL0 would cause execution to
27488                                                                      be suspended, such as if there is not a pending WFI wakeup
27489                                                                      event, it is taken as an exception to EL1 using the0x1
27490                                                                  1 = WFI instructions are executed as normal. */
27491         uint32_t reserved_17           : 1;
27492         uint32_t ntwe                  : 1;  /**< [ 18: 18](R/W) Not trap WFE.
27493                                                                  Conditional WFE instructions that fail their condition do not
27494                                                                      cause an exception if this bit is 0.
27495                                                                  0 = If a WFE instruction executed at EL0 would cause execution to
27496                                                                      be suspended, such as if the event register is not set and
27497                                                                      there is not a pending WFE wakeup event, it is taken as an
27498                                                                      exception to EL1 using the0x1
27499                                                                  1 = WFE instructions are executed as normal. */
27500         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
27501                                                                      used to require all memory regions with write permission to be
27502                                                                      treated as XN.
27503 
27504                                                                  The WXN bit is permitted to be cached in a TLB.
27505 
27506                                                                  0 = Regions with write permission are not forced to XN.
27507                                                                  1 = Regions with write permission are forced to XN. */
27508         uint32_t rsvd_20               : 1;  /**< [ 20: 20](RO) Reserved 1. */
27509         uint32_t reserved_21           : 1;
27510         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
27511         uint32_t span                  : 1;  /**< [ 23: 23](R/W) v8.1: Bit[23]: SPAN set PSTATE/CPSR[AP_PAN] bit on taking an exception
27512                                                                  to the EL1 exception level.
27513                                                                  0 = PSTATE/CPSR[AP_PAN] is set on taking an exception to the EL1 exception level
27514                                                                  1 = PSTATE/CPSR[AP_PAN] is left unchanged on taking an exception to the EL1 exception
27515                                                                  level
27516 
27517                                                                  This bit has no effect on the PSTATE/CPSR[AP_PAN] when taking exceptions to any other
27518                                                                  exception level. */
27519         uint32_t e0e                   : 1;  /**< [ 24: 24](R/W) Endianness of explicit data accesses at EL0.
27520 
27521                                                                  If an implementation only supports Little-endian accesses at
27522                                                                      EL0 then this bit is RES0.
27523 
27524                                                                  If an implementation only supports Big-endian accesses at EL0
27525                                                                      then this bit is RES1.
27526 
27527                                                                  This bit has no effect on the endianness of LDTR* and STTR*
27528                                                                      instructions executed at EL1.
27529 
27530                                                                  0 = Explicit data accesses at EL0 are little-endian.
27531                                                                  1 = Explicit data accesses at EL0 are big-endian. */
27532         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
27533                                                                   Explicit data accesses at EL1.
27534                                                                   Stage 1 translation table walks at EL1 and EL0.
27535 
27536                                                                  If an implementation does not provide Big-endian support, this
27537                                                                      bit is RES0. If it does not provide Little-endian support,
27538                                                                      this bit is RES1.
27539 
27540                                                                  The EE bit is permitted to be cached in a TLB.
27541 
27542                                                                  0 = Little-endian.
27543                                                                  1 = Big-endian. */
27544         uint32_t uci                   : 1;  /**< [ 26: 26](R/W) When set, enables EL0 access in AArch64 for DC CVAU, DC CIVAC,
27545                                                                      DC CVAC, and IC IVAU instructions. */
27546         uint32_t reserved_27           : 1;
27547         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
27548         uint32_t reserved_30_31        : 2;
27549 #endif /* Word 0 - End */
27550     } s;
27551     struct bdk_ap_sctlr_el2_e2h_cn
27552     {
27553 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
27554         uint32_t reserved_30_31        : 2;
27555         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
27556         uint32_t reserved_27           : 1;
27557         uint32_t uci                   : 1;  /**< [ 26: 26](R/W) When set, enables EL0 access in AArch64 for DC CVAU, DC CIVAC,
27558                                                                      DC CVAC, and IC IVAU instructions. */
27559         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
27560                                                                   Explicit data accesses at EL1.
27561                                                                   Stage 1 translation table walks at EL1 and EL0.
27562 
27563                                                                  If an implementation does not provide Big-endian support, this
27564                                                                      bit is RES0. If it does not provide Little-endian support,
27565                                                                      this bit is RES1.
27566 
27567                                                                  The EE bit is permitted to be cached in a TLB.
27568 
27569                                                                  0 = Little-endian.
27570                                                                  1 = Big-endian. */
27571         uint32_t e0e                   : 1;  /**< [ 24: 24](R/W) Endianness of explicit data accesses at EL0.
27572 
27573                                                                  If an implementation only supports Little-endian accesses at
27574                                                                      EL0 then this bit is RES0.
27575 
27576                                                                  If an implementation only supports Big-endian accesses at EL0
27577                                                                      then this bit is RES1.
27578 
27579                                                                  This bit has no effect on the endianness of LDTR* and STTR*
27580                                                                      instructions executed at EL1.
27581 
27582                                                                  0 = Explicit data accesses at EL0 are little-endian.
27583                                                                  1 = Explicit data accesses at EL0 are big-endian. */
27584         uint32_t span                  : 1;  /**< [ 23: 23](R/W) v8.1: Bit[23]: SPAN set PSTATE/CPSR[AP_PAN] bit on taking an exception
27585                                                                  to the EL1 exception level.
27586                                                                  0 = PSTATE/CPSR[AP_PAN] is set on taking an exception to the EL1 exception level
27587                                                                  1 = PSTATE/CPSR[AP_PAN] is left unchanged on taking an exception to the EL1 exception
27588                                                                  level
27589 
27590                                                                  This bit has no effect on the PSTATE/CPSR[AP_PAN] when taking exceptions to any other
27591                                                                  exception level. */
27592         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
27593         uint32_t reserved_21           : 1;
27594         uint32_t rsvd_20               : 1;  /**< [ 20: 20](RO) Reserved 1. */
27595         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
27596                                                                      used to require all memory regions with write permission to be
27597                                                                      treated as XN.
27598 
27599                                                                  The WXN bit is permitted to be cached in a TLB.
27600 
27601                                                                  0 = Regions with write permission are not forced to XN.
27602                                                                  1 = Regions with write permission are forced to XN. */
27603         uint32_t ntwe                  : 1;  /**< [ 18: 18](R/W) Not trap WFE.
27604                                                                  Conditional WFE instructions that fail their condition do not
27605                                                                      cause an exception if this bit is 0.
27606                                                                  0 = If a WFE instruction executed at EL0 would cause execution to
27607                                                                      be suspended, such as if the event register is not set and
27608                                                                      there is not a pending WFE wakeup event, it is taken as an
27609                                                                      exception to EL1 using the0x1
27610                                                                  1 = WFE instructions are executed as normal. */
27611         uint32_t reserved_17           : 1;
27612         uint32_t ntwi                  : 1;  /**< [ 16: 16](R/W) Not trap WFI.
27613                                                                  Conditional WFI instructions that fail their condition do not
27614                                                                      cause an exception if this bit is 0.
27615                                                                  0 = If a WFI instruction executed at EL0 would cause execution to
27616                                                                      be suspended, such as if there is not a pending WFI wakeup
27617                                                                      event, it is taken as an exception to EL1 using the0x1
27618                                                                  1 = WFI instructions are executed as normal. */
27619         uint32_t uct                   : 1;  /**< [ 15: 15](R/W) When set, enables EL0 access in AArch64 to the AP_CTR_EL0
27620                                                                      register. */
27621         uint32_t dze                   : 1;  /**< [ 14: 14](R/W) Access to DC ZVA instruction at EL0.
27622                                                                  0 = Execution of the DC ZVA instruction is prohibited at EL0, and
27623                                                                      it is treated as undefined at EL0.
27624                                                                  1 = Execution of the DC ZVA instruction is allowed at EL0. */
27625         uint32_t reserved_13           : 1;
27626         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
27627                                                                      instruction caches at EL0 and EL1:
27628                                                                  When this bit is 0, all EL1 and EL0 Normal memory instruction
27629                                                                      accesses are Non-cacheable.
27630                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
27631                                                                      EL1&0 translation regime is Cacheable regardless of the value
27632                                                                      of this bit.
27633                                                                  0 = Instruction caches disabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
27634                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
27635                                                                      translation regime are to Normal memory, Outer Shareable,
27636                                                                      Inner Non-cacheable, Outer Non-cacheable.
27637                                                                  1 = Instruction caches enabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
27638                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
27639                                                                      translation regime are to Normal memory, Outer Shareable,
27640                                                                      Inner Write-Through, Outer Write-Through. */
27641         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
27642         uint32_t reserved_10           : 1;
27643         uint32_t uma                   : 1;  /**< [  9:  9](R/W) User Mask Access. Controls access to interrupt masks from EL0,
27644                                                                      when EL0 is using AArch64.
27645                                                                  0 = Disable access to the interrupt masks from EL0.
27646                                                                  1 = Enable access to the interrupt masks from EL0. */
27647         uint32_t rsvd_8                : 1;  /**< [  8:  8](RO) SETEND disable.
27648                                                                  If an implementation does not support mixed endian operation,
27649                                                                      this bit is RES1.
27650                                                                  0 = The SETEND instruction is available.
27651                                                                  1 = The SETEND instruction is UNALLOCATED.
27652 
27653                                                                  SED: SETEND Disable - Only supported with 32 bit */
27654         uint32_t rsvd_7                : 1;  /**< [  7:  7](RO) "IT Disable.
27655                                                                  0 = The IT instruction functionality is available.
27656                                                                  1 = It is implementation defined whether the IT instruction is
27657                                                                      treated as either:
27658                                                                  * A 16-bit instruction, which can only be followed by another
27659                                                                      16-bit instruction.
27660                                                                  * The first half of a 32-bit instruction.
27661 
27662                                                                  An implementation might vary dynamically as to whether IT is
27663                                                                      treated as a 16-bit instruction or the first half of a 32-bit
27664                                                                      instruction.
27665 
27666                                                                  All encodings of the IT instruction with hw1[3:0]!=1000 are
27667                                                                      UNdefined and treated as unallocated.
27668 
27669                                                                  All encodings of the subsequent instruction with the following
27670                                                                      values for hw1 are UNdefined (and treated as unallocated):
27671 
27672                                                                  - 0b11xxxxxxxxxxxxxx: All 32-bit instructions, and the 16-bit
27673                                                                      instructions B, UDF, SVC, LDM, and STM.
27674 
27675                                                                  - 0b1x11xxxxxxxxxxxx: All instructions in.
27676 
27677                                                                  - 0b1x100xxxxxxxxxxx: ADD Rd, PC, #imm
27678 
27679                                                                  - 0b01001xxxxxxxxxxx: LDR Rd, [PC, #imm]
27680 
27681                                                                  - 0b0100x1xxx1111xxx: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX
27682                                                                      PC; BLX PC.
27683 
27684                                                                  - 0b010001xx1xxxx111: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This
27685                                                                      pattern also covers UNPREDICTABLE cases with BLX Rn.
27686 
27687                                                                  Contrary to the standard treatment of conditional UNdefined
27688                                                                      instructions in the ARM architecture, in this case these
27689                                                                      instructions are always treated as UNdefined, regardless of
27690                                                                      whether the instruction would pass or fail its condition codes
27691                                                                      as a result of being in an IT block.
27692 
27693                                                                  ITD: IT Disable - Only supported with 32 bit" */
27694         uint32_t reserved_6            : 1;
27695         uint32_t reserved_5            : 1;
27696         uint32_t sa0                   : 1;  /**< [  4:  4](R/W) Stack Alignment Check Enable for EL0. When set, use of the
27697                                                                      stack pointer as the base address in a load/store instruction
27698                                                                      at EL0 must be aligned to a 16-byte boundary, or a Stack
27699                                                                      Alignment Fault exception will be raised. */
27700         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack Alignment Check Enable. When set, use of the stack
27701                                                                      pointer as the base address in a load/store instruction at
27702                                                                      this register's Exception level must be aligned to a 16-byte
27703                                                                      boundary, or a Stack Alignment Fault exception will be raised. */
27704         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
27705                                                                      caches at EL0 and EL1:
27706                                                                  When this bit is 0, all EL0 and EL1 Normal memory data
27707                                                                      accesses and all accesses to the EL1&0 stage 1 translation
27708                                                                      tables are Non-cacheable.
27709                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
27710                                                                      EL1&0 translation regime is Cacheable regardless of the value
27711                                                                      of the AP_SCTLR_EL1[C] bit.
27712                                                                  0 = Data and unified caches disabled.
27713                                                                  1 = Data and unified caches enabled. */
27714         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
27715                                                                      fault checking.
27716 
27717                                                                  Load/store exclusive and load-acquire/store-release
27718                                                                      instructions have an alignment check regardless of the value
27719                                                                      of the A bit.
27720 
27721                                                                  0 = Alignment fault checking disabled.
27722                                                                  Instructions that load or store one or more registers, other
27723                                                                      than load/store exclusive and load-acquire/store-release, do
27724                                                                      not check that the address being accessed is aligned to the
27725                                                                      size of the data element(s) being accessed.
27726 
27727                                                                  1 = Alignment fault checking enabled.
27728                                                                  All instructions that load or store one or more registers have
27729                                                                      an alignment check that the address being accessed is aligned
27730                                                                      to the size of the data element(s) being accessed. If this
27731                                                                      check fails it causes an Alignment fault, which is taken as a
27732                                                                      Data Abort exception. */
27733         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL1 and EL0 stage 1 address translation.
27734 
27735                                                                  If AP_HCR_EL2[DC] is set to 1, then in nonsecure state the
27736                                                                      AP_SCTLR_EL1[M] bit behaves as 0 for all purposes other than
27737                                                                      reading the value of the bit.
27738                                                                  0 = EL1 and EL0 stage 1 address translation disabled.
27739                                                                  1 = EL1 and EL0 stage 1 address translation enabled. */
27740 #else /* Word 0 - Little Endian */
27741         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL1 and EL0 stage 1 address translation.
27742 
27743                                                                  If AP_HCR_EL2[DC] is set to 1, then in nonsecure state the
27744                                                                      AP_SCTLR_EL1[M] bit behaves as 0 for all purposes other than
27745                                                                      reading the value of the bit.
27746                                                                  0 = EL1 and EL0 stage 1 address translation disabled.
27747                                                                  1 = EL1 and EL0 stage 1 address translation enabled. */
27748         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
27749                                                                      fault checking.
27750 
27751                                                                  Load/store exclusive and load-acquire/store-release
27752                                                                      instructions have an alignment check regardless of the value
27753                                                                      of the A bit.
27754 
27755                                                                  0 = Alignment fault checking disabled.
27756                                                                  Instructions that load or store one or more registers, other
27757                                                                      than load/store exclusive and load-acquire/store-release, do
27758                                                                      not check that the address being accessed is aligned to the
27759                                                                      size of the data element(s) being accessed.
27760 
27761                                                                  1 = Alignment fault checking enabled.
27762                                                                  All instructions that load or store one or more registers have
27763                                                                      an alignment check that the address being accessed is aligned
27764                                                                      to the size of the data element(s) being accessed. If this
27765                                                                      check fails it causes an Alignment fault, which is taken as a
27766                                                                      Data Abort exception. */
27767         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
27768                                                                      caches at EL0 and EL1:
27769                                                                  When this bit is 0, all EL0 and EL1 Normal memory data
27770                                                                      accesses and all accesses to the EL1&0 stage 1 translation
27771                                                                      tables are Non-cacheable.
27772                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
27773                                                                      EL1&0 translation regime is Cacheable regardless of the value
27774                                                                      of the AP_SCTLR_EL1[C] bit.
27775                                                                  0 = Data and unified caches disabled.
27776                                                                  1 = Data and unified caches enabled. */
27777         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack Alignment Check Enable. When set, use of the stack
27778                                                                      pointer as the base address in a load/store instruction at
27779                                                                      this register's Exception level must be aligned to a 16-byte
27780                                                                      boundary, or a Stack Alignment Fault exception will be raised. */
27781         uint32_t sa0                   : 1;  /**< [  4:  4](R/W) Stack Alignment Check Enable for EL0. When set, use of the
27782                                                                      stack pointer as the base address in a load/store instruction
27783                                                                      at EL0 must be aligned to a 16-byte boundary, or a Stack
27784                                                                      Alignment Fault exception will be raised. */
27785         uint32_t reserved_5            : 1;
27786         uint32_t reserved_6            : 1;
27787         uint32_t rsvd_7                : 1;  /**< [  7:  7](RO) "IT Disable.
27788                                                                  0 = The IT instruction functionality is available.
27789                                                                  1 = It is implementation defined whether the IT instruction is
27790                                                                      treated as either:
27791                                                                  * A 16-bit instruction, which can only be followed by another
27792                                                                      16-bit instruction.
27793                                                                  * The first half of a 32-bit instruction.
27794 
27795                                                                  An implementation might vary dynamically as to whether IT is
27796                                                                      treated as a 16-bit instruction or the first half of a 32-bit
27797                                                                      instruction.
27798 
27799                                                                  All encodings of the IT instruction with hw1[3:0]!=1000 are
27800                                                                      UNdefined and treated as unallocated.
27801 
27802                                                                  All encodings of the subsequent instruction with the following
27803                                                                      values for hw1 are UNdefined (and treated as unallocated):
27804 
27805                                                                  - 0b11xxxxxxxxxxxxxx: All 32-bit instructions, and the 16-bit
27806                                                                      instructions B, UDF, SVC, LDM, and STM.
27807 
27808                                                                  - 0b1x11xxxxxxxxxxxx: All instructions in.
27809 
27810                                                                  - 0b1x100xxxxxxxxxxx: ADD Rd, PC, #imm
27811 
27812                                                                  - 0b01001xxxxxxxxxxx: LDR Rd, [PC, #imm]
27813 
27814                                                                  - 0b0100x1xxx1111xxx: ADD Rdn, PC; CMP Rn, PC; MOV Rd, PC; BX
27815                                                                      PC; BLX PC.
27816 
27817                                                                  - 0b010001xx1xxxx111: ADD PC, Rm; CMP PC, Rm; MOV PC, Rm. This
27818                                                                      pattern also covers UNPREDICTABLE cases with BLX Rn.
27819 
27820                                                                  Contrary to the standard treatment of conditional UNdefined
27821                                                                      instructions in the ARM architecture, in this case these
27822                                                                      instructions are always treated as UNdefined, regardless of
27823                                                                      whether the instruction would pass or fail its condition codes
27824                                                                      as a result of being in an IT block.
27825 
27826                                                                  ITD: IT Disable - Only supported with 32 bit" */
27827         uint32_t rsvd_8                : 1;  /**< [  8:  8](RO) SETEND disable.
27828                                                                  If an implementation does not support mixed endian operation,
27829                                                                      this bit is RES1.
27830                                                                  0 = The SETEND instruction is available.
27831                                                                  1 = The SETEND instruction is UNALLOCATED.
27832 
27833                                                                  SED: SETEND Disable - Only supported with 32 bit */
27834         uint32_t uma                   : 1;  /**< [  9:  9](R/W) User Mask Access. Controls access to interrupt masks from EL0,
27835                                                                      when EL0 is using AArch64.
27836                                                                  0 = Disable access to the interrupt masks from EL0.
27837                                                                  1 = Enable access to the interrupt masks from EL0. */
27838         uint32_t reserved_10           : 1;
27839         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
27840         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
27841                                                                      instruction caches at EL0 and EL1:
27842                                                                  When this bit is 0, all EL1 and EL0 Normal memory instruction
27843                                                                      accesses are Non-cacheable.
27844                                                                  If the AP_HCR_EL2[DC] bit is set to 1, then the nonsecure stage 1
27845                                                                      EL1&0 translation regime is Cacheable regardless of the value
27846                                                                      of this bit.
27847                                                                  0 = Instruction caches disabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
27848                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
27849                                                                      translation regime are to Normal memory, Outer Shareable,
27850                                                                      Inner Non-cacheable, Outer Non-cacheable.
27851                                                                  1 = Instruction caches enabled at EL0 and EL1. If AP_SCTLR_EL1[M] is
27852                                                                      set to 0, instruction accesses from stage 1 of the EL1&0
27853                                                                      translation regime are to Normal memory, Outer Shareable,
27854                                                                      Inner Write-Through, Outer Write-Through. */
27855         uint32_t reserved_13           : 1;
27856         uint32_t dze                   : 1;  /**< [ 14: 14](R/W) Access to DC ZVA instruction at EL0.
27857                                                                  0 = Execution of the DC ZVA instruction is prohibited at EL0, and
27858                                                                      it is treated as undefined at EL0.
27859                                                                  1 = Execution of the DC ZVA instruction is allowed at EL0. */
27860         uint32_t uct                   : 1;  /**< [ 15: 15](R/W) When set, enables EL0 access in AArch64 to the AP_CTR_EL0
27861                                                                      register. */
27862         uint32_t ntwi                  : 1;  /**< [ 16: 16](R/W) Not trap WFI.
27863                                                                  Conditional WFI instructions that fail their condition do not
27864                                                                      cause an exception if this bit is 0.
27865                                                                  0 = If a WFI instruction executed at EL0 would cause execution to
27866                                                                      be suspended, such as if there is not a pending WFI wakeup
27867                                                                      event, it is taken as an exception to EL1 using the0x1
27868                                                                  1 = WFI instructions are executed as normal. */
27869         uint32_t reserved_17           : 1;
27870         uint32_t ntwe                  : 1;  /**< [ 18: 18](R/W) Not trap WFE.
27871                                                                  Conditional WFE instructions that fail their condition do not
27872                                                                      cause an exception if this bit is 0.
27873                                                                  0 = If a WFE instruction executed at EL0 would cause execution to
27874                                                                      be suspended, such as if the event register is not set and
27875                                                                      there is not a pending WFE wakeup event, it is taken as an
27876                                                                      exception to EL1 using the0x1
27877                                                                  1 = WFE instructions are executed as normal. */
27878         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
27879                                                                      used to require all memory regions with write permission to be
27880                                                                      treated as XN.
27881 
27882                                                                  The WXN bit is permitted to be cached in a TLB.
27883 
27884                                                                  0 = Regions with write permission are not forced to XN.
27885                                                                  1 = Regions with write permission are forced to XN. */
27886         uint32_t rsvd_20               : 1;  /**< [ 20: 20](RO) Reserved 1. */
27887         uint32_t reserved_21           : 1;
27888         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
27889         uint32_t span                  : 1;  /**< [ 23: 23](R/W) v8.1: Bit[23]: SPAN set PSTATE/CPSR[AP_PAN] bit on taking an exception
27890                                                                  to the EL1 exception level.
27891                                                                  0 = PSTATE/CPSR[AP_PAN] is set on taking an exception to the EL1 exception level
27892                                                                  1 = PSTATE/CPSR[AP_PAN] is left unchanged on taking an exception to the EL1 exception
27893                                                                  level
27894 
27895                                                                  This bit has no effect on the PSTATE/CPSR[AP_PAN] when taking exceptions to any other
27896                                                                  exception level. */
27897         uint32_t e0e                   : 1;  /**< [ 24: 24](R/W) Endianness of explicit data accesses at EL0.
27898 
27899                                                                  If an implementation only supports Little-endian accesses at
27900                                                                      EL0 then this bit is RES0.
27901 
27902                                                                  If an implementation only supports Big-endian accesses at EL0
27903                                                                      then this bit is RES1.
27904 
27905                                                                  This bit has no effect on the endianness of LDTR* and STTR*
27906                                                                      instructions executed at EL1.
27907 
27908                                                                  0 = Explicit data accesses at EL0 are little-endian.
27909                                                                  1 = Explicit data accesses at EL0 are big-endian. */
27910         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
27911                                                                   Explicit data accesses at EL1.
27912                                                                   Stage 1 translation table walks at EL1 and EL0.
27913 
27914                                                                  If an implementation does not provide Big-endian support, this
27915                                                                      bit is RES0. If it does not provide Little-endian support,
27916                                                                      this bit is RES1.
27917 
27918                                                                  The EE bit is permitted to be cached in a TLB.
27919 
27920                                                                  0 = Little-endian.
27921                                                                  1 = Big-endian. */
27922         uint32_t uci                   : 1;  /**< [ 26: 26](R/W) When set, enables EL0 access in AArch64 for DC CVAU, DC CIVAC,
27923                                                                      DC CVAC, and IC IVAU instructions. */
27924         uint32_t reserved_27           : 1;
27925         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
27926         uint32_t reserved_30_31        : 2;
27927 #endif /* Word 0 - End */
27928     } cn;
27929 };
27930 typedef union bdk_ap_sctlr_el2_e2h bdk_ap_sctlr_el2_e2h_t;
27931 
27932 #define BDK_AP_SCTLR_EL2_E2H BDK_AP_SCTLR_EL2_E2H_FUNC()
27933 static inline uint64_t BDK_AP_SCTLR_EL2_E2H_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SCTLR_EL2_E2H_FUNC(void)27934 static inline uint64_t BDK_AP_SCTLR_EL2_E2H_FUNC(void)
27935 {
27936     return 0x30401000010ll;
27937 }
27938 
27939 #define typedef_BDK_AP_SCTLR_EL2_E2H bdk_ap_sctlr_el2_e2h_t
27940 #define bustype_BDK_AP_SCTLR_EL2_E2H BDK_CSR_TYPE_SYSREG
27941 #define basename_BDK_AP_SCTLR_EL2_E2H "AP_SCTLR_EL2_E2H"
27942 #define busnum_BDK_AP_SCTLR_EL2_E2H 0
27943 #define arguments_BDK_AP_SCTLR_EL2_E2H -1,-1,-1,-1
27944 
27945 /**
27946  * Register (SYSREG) ap_sctlr_el3
27947  *
27948  * AP System Control Register
27949  * Provides top level control of the system, including its memory
27950  *     system, at EL3.
27951  */
27952 union bdk_ap_sctlr_el3
27953 {
27954     uint32_t u;
27955     struct bdk_ap_sctlr_el3_s
27956     {
27957 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
27958         uint32_t reserved_30_31        : 2;
27959         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
27960         uint32_t reserved_26_27        : 2;
27961         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
27962                                                                   Explicit data accesses at EL3.
27963                                                                   Stage 1 translation table walks at EL3.
27964 
27965                                                                  If an implementation does not provide Big-endian support, this
27966                                                                      bit is RES0. If it does not provide Little-endian support,
27967                                                                      this bit is RES1.
27968 
27969                                                                  The EE bit is permitted to be cached in a TLB.
27970                                                                  0 = Little-endian.
27971                                                                  1 = Big-endian. */
27972         uint32_t reserved_24           : 1;
27973         uint32_t rsvd_23               : 1;  /**< [ 23: 23](RO) Reserved 1. */
27974         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
27975         uint32_t reserved_20_21        : 2;
27976         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
27977                                                                      used to require all memory regions with write permission to be
27978                                                                      treated as XN.
27979                                                                  The WXN bit is permitted to be cached in a TLB.
27980                                                                  0 = Regions with write permission are not forced to XN.
27981                                                                  1 = Regions with write permission are forced to XN. */
27982         uint32_t rsvd_18               : 1;  /**< [ 18: 18](RO) Reserved 1. */
27983         uint32_t reserved_17           : 1;
27984         uint32_t rsvd_16               : 1;  /**< [ 16: 16](RO) Reserved 1. */
27985         uint32_t reserved_13_15        : 3;
27986         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
27987                                                                      instruction caches at EL3:
27988 
27989                                                                  When this bit is 0, all EL3 Normal memory instruction accesses
27990                                                                      are Non-cacheable. This bit has no effect on the EL1&0 or EL2
27991                                                                      translation regimes.
27992 
27993                                                                  0 = Instruction caches disabled at EL3. If AP_SCTLR_EL3[M] is set to
27994                                                                      0, instruction accesses from stage 1 of the EL3 translation
27995                                                                      regime are to Normal memory, Outer Shareable, Inner Non-
27996                                                                      cacheable, Outer Non-cacheable.
27997                                                                  1 = Instruction caches enabled at EL3. If AP_SCTLR_EL3[M] is set to 0,
27998                                                                      instruction accesses from stage 1 of the EL3 translation
27999                                                                      regime are to Normal memory, Outer Shareable, Inner Write-
28000                                                                      Through, Outer Write-Through. */
28001         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
28002         uint32_t reserved_6_10         : 5;
28003         uint32_t rsvd_4_5              : 2;  /**< [  5:  4](RO) Reserved 1. */
28004         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack alignment check enable. When set, use of the stack
28005                                                                      pointer as the base address in a load/store instruction at
28006                                                                      this register's exception level must be aligned to a 16-byte
28007                                                                      boundary, or a stack alignment fault exception will be raised. */
28008         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
28009                                                                      caches at EL3.
28010 
28011                                                                  When this bit is 0, all EL3 normal memory data accesses and
28012                                                                      all accesses to the EL3 translation tables are Non-cacheable.
28013                                                                      This bit has no effect on the EL1&0 or EL2 translation
28014                                                                      regimes.
28015 
28016                                                                  0 = Data and unified caches disabled at EL3.
28017                                                                  1 = Data and unified caches enabled at EL3. */
28018         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
28019                                                                      fault checking:
28020 
28021                                                                  Load/store exclusive and load-acquire/store-release
28022                                                                      instructions have an alignment check regardless of the value
28023                                                                      of the A bit.
28024 
28025                                                                  0 = Alignment fault checking disabled.
28026                                                                  Instructions that load or store one or more registers, other
28027                                                                      than load/store exclusive and load-acquire/store-release, do
28028                                                                      not check that the address being accessed is aligned to the
28029                                                                      size of the data element(s) being accessed.
28030 
28031                                                                  1 = Alignment fault checking enabled.
28032                                                                  All instructions that load or store one or more registers have
28033                                                                      an alignment check that the address being accessed is aligned
28034                                                                      to the size of the data element(s) being accessed. If this
28035                                                                      check fails it causes an Alignment fault, which is taken as a
28036                                                                      Data Abort exception. */
28037         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL3 stage 1 address translation.
28038                                                                  0 = EL3 stage 1 address translation disabled.
28039                                                                  1 = EL3 stage 1 address translation enabled. */
28040 #else /* Word 0 - Little Endian */
28041         uint32_t m                     : 1;  /**< [  0:  0](R/W) MMU enable for EL3 stage 1 address translation.
28042                                                                  0 = EL3 stage 1 address translation disabled.
28043                                                                  1 = EL3 stage 1 address translation enabled. */
28044         uint32_t aa                    : 1;  /**< [  1:  1](R/W) Alignment check enable. This is the enable bit for Alignment
28045                                                                      fault checking:
28046 
28047                                                                  Load/store exclusive and load-acquire/store-release
28048                                                                      instructions have an alignment check regardless of the value
28049                                                                      of the A bit.
28050 
28051                                                                  0 = Alignment fault checking disabled.
28052                                                                  Instructions that load or store one or more registers, other
28053                                                                      than load/store exclusive and load-acquire/store-release, do
28054                                                                      not check that the address being accessed is aligned to the
28055                                                                      size of the data element(s) being accessed.
28056 
28057                                                                  1 = Alignment fault checking enabled.
28058                                                                  All instructions that load or store one or more registers have
28059                                                                      an alignment check that the address being accessed is aligned
28060                                                                      to the size of the data element(s) being accessed. If this
28061                                                                      check fails it causes an Alignment fault, which is taken as a
28062                                                                      Data Abort exception. */
28063         uint32_t cc                    : 1;  /**< [  2:  2](R/W) Cache enable. This is an enable bit for data and unified
28064                                                                      caches at EL3.
28065 
28066                                                                  When this bit is 0, all EL3 normal memory data accesses and
28067                                                                      all accesses to the EL3 translation tables are Non-cacheable.
28068                                                                      This bit has no effect on the EL1&0 or EL2 translation
28069                                                                      regimes.
28070 
28071                                                                  0 = Data and unified caches disabled at EL3.
28072                                                                  1 = Data and unified caches enabled at EL3. */
28073         uint32_t sa                    : 1;  /**< [  3:  3](R/W) Stack alignment check enable. When set, use of the stack
28074                                                                      pointer as the base address in a load/store instruction at
28075                                                                      this register's exception level must be aligned to a 16-byte
28076                                                                      boundary, or a stack alignment fault exception will be raised. */
28077         uint32_t rsvd_4_5              : 2;  /**< [  5:  4](RO) Reserved 1. */
28078         uint32_t reserved_6_10         : 5;
28079         uint32_t rsvd_11               : 1;  /**< [ 11: 11](RO) Reserved 1. */
28080         uint32_t i                     : 1;  /**< [ 12: 12](R/W) Instruction cache enable. This is an enable bit for
28081                                                                      instruction caches at EL3:
28082 
28083                                                                  When this bit is 0, all EL3 Normal memory instruction accesses
28084                                                                      are Non-cacheable. This bit has no effect on the EL1&0 or EL2
28085                                                                      translation regimes.
28086 
28087                                                                  0 = Instruction caches disabled at EL3. If AP_SCTLR_EL3[M] is set to
28088                                                                      0, instruction accesses from stage 1 of the EL3 translation
28089                                                                      regime are to Normal memory, Outer Shareable, Inner Non-
28090                                                                      cacheable, Outer Non-cacheable.
28091                                                                  1 = Instruction caches enabled at EL3. If AP_SCTLR_EL3[M] is set to 0,
28092                                                                      instruction accesses from stage 1 of the EL3 translation
28093                                                                      regime are to Normal memory, Outer Shareable, Inner Write-
28094                                                                      Through, Outer Write-Through. */
28095         uint32_t reserved_13_15        : 3;
28096         uint32_t rsvd_16               : 1;  /**< [ 16: 16](RO) Reserved 1. */
28097         uint32_t reserved_17           : 1;
28098         uint32_t rsvd_18               : 1;  /**< [ 18: 18](RO) Reserved 1. */
28099         uint32_t wxn                   : 1;  /**< [ 19: 19](R/W) Write permission implies XN (Execute Never). This bit can be
28100                                                                      used to require all memory regions with write permission to be
28101                                                                      treated as XN.
28102                                                                  The WXN bit is permitted to be cached in a TLB.
28103                                                                  0 = Regions with write permission are not forced to XN.
28104                                                                  1 = Regions with write permission are forced to XN. */
28105         uint32_t reserved_20_21        : 2;
28106         uint32_t rsvd_22               : 1;  /**< [ 22: 22](RO) Reserved 1. */
28107         uint32_t rsvd_23               : 1;  /**< [ 23: 23](RO) Reserved 1. */
28108         uint32_t reserved_24           : 1;
28109         uint32_t ee                    : 1;  /**< [ 25: 25](R/W) Exception Endianness. This bit controls the endianness for:
28110                                                                   Explicit data accesses at EL3.
28111                                                                   Stage 1 translation table walks at EL3.
28112 
28113                                                                  If an implementation does not provide Big-endian support, this
28114                                                                      bit is RES0. If it does not provide Little-endian support,
28115                                                                      this bit is RES1.
28116 
28117                                                                  The EE bit is permitted to be cached in a TLB.
28118                                                                  0 = Little-endian.
28119                                                                  1 = Big-endian. */
28120         uint32_t reserved_26_27        : 2;
28121         uint32_t rsvd_28_29            : 2;  /**< [ 29: 28](RO) Reserved 1. */
28122         uint32_t reserved_30_31        : 2;
28123 #endif /* Word 0 - End */
28124     } s;
28125     /* struct bdk_ap_sctlr_el3_s cn; */
28126 };
28127 typedef union bdk_ap_sctlr_el3 bdk_ap_sctlr_el3_t;
28128 
28129 #define BDK_AP_SCTLR_EL3 BDK_AP_SCTLR_EL3_FUNC()
28130 static inline uint64_t BDK_AP_SCTLR_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SCTLR_EL3_FUNC(void)28131 static inline uint64_t BDK_AP_SCTLR_EL3_FUNC(void)
28132 {
28133     return 0x30601000000ll;
28134 }
28135 
28136 #define typedef_BDK_AP_SCTLR_EL3 bdk_ap_sctlr_el3_t
28137 #define bustype_BDK_AP_SCTLR_EL3 BDK_CSR_TYPE_SYSREG
28138 #define basename_BDK_AP_SCTLR_EL3 "AP_SCTLR_EL3"
28139 #define busnum_BDK_AP_SCTLR_EL3 0
28140 #define arguments_BDK_AP_SCTLR_EL3 -1,-1,-1,-1
28141 
28142 /**
28143  * Register (SYSREG) ap_sder32_el3
28144  *
28145  * AP AArch32 Secure Debug Enable Register
28146  * Allows access to the AArch32 register SDER from AArch64 state
28147  *     only. Its value has no effect on execution in AArch64 state.
28148  */
28149 union bdk_ap_sder32_el3
28150 {
28151     uint32_t u;
28152     struct bdk_ap_sder32_el3_s
28153     {
28154 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28155         uint32_t reserved_2_31         : 30;
28156         uint32_t suniden               : 1;  /**< [  1:  1](R/W) Secure User Non-Invasive Debug Enable:
28157                                                                  0 = Non-invasive debug not permitted in Secure EL0 mode.
28158                                                                  1 = Non-invasive debug permitted in Secure EL0 mode. */
28159         uint32_t suiden                : 1;  /**< [  0:  0](R/W) Secure User Invasive Debug Enable:
28160                                                                  0 = Invasive debug not permitted in Secure EL0 mode.
28161                                                                  1 = Invasive debug permitted in Secure EL0 mode. */
28162 #else /* Word 0 - Little Endian */
28163         uint32_t suiden                : 1;  /**< [  0:  0](R/W) Secure User Invasive Debug Enable:
28164                                                                  0 = Invasive debug not permitted in Secure EL0 mode.
28165                                                                  1 = Invasive debug permitted in Secure EL0 mode. */
28166         uint32_t suniden               : 1;  /**< [  1:  1](R/W) Secure User Non-Invasive Debug Enable:
28167                                                                  0 = Non-invasive debug not permitted in Secure EL0 mode.
28168                                                                  1 = Non-invasive debug permitted in Secure EL0 mode. */
28169         uint32_t reserved_2_31         : 30;
28170 #endif /* Word 0 - End */
28171     } s;
28172     /* struct bdk_ap_sder32_el3_s cn8; */
28173     struct bdk_ap_sder32_el3_cn9
28174     {
28175 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28176         uint32_t reserved_2_31         : 30;
28177         uint32_t suniden               : 1;  /**< [  1:  1](RAZ) Secure User Non-Invasive Debug Enable:
28178                                                                  0 = Non-invasive debug not permitted in Secure EL0 mode.
28179                                                                  1 = Non-invasive debug permitted in Secure EL0 mode. */
28180         uint32_t suiden                : 1;  /**< [  0:  0](RAZ) Secure User Invasive Debug Enable:
28181                                                                  0 = Invasive debug not permitted in Secure EL0 mode.
28182                                                                  1 = Invasive debug permitted in Secure EL0 mode. */
28183 #else /* Word 0 - Little Endian */
28184         uint32_t suiden                : 1;  /**< [  0:  0](RAZ) Secure User Invasive Debug Enable:
28185                                                                  0 = Invasive debug not permitted in Secure EL0 mode.
28186                                                                  1 = Invasive debug permitted in Secure EL0 mode. */
28187         uint32_t suniden               : 1;  /**< [  1:  1](RAZ) Secure User Non-Invasive Debug Enable:
28188                                                                  0 = Non-invasive debug not permitted in Secure EL0 mode.
28189                                                                  1 = Non-invasive debug permitted in Secure EL0 mode. */
28190         uint32_t reserved_2_31         : 30;
28191 #endif /* Word 0 - End */
28192     } cn9;
28193 };
28194 typedef union bdk_ap_sder32_el3 bdk_ap_sder32_el3_t;
28195 
28196 #define BDK_AP_SDER32_EL3 BDK_AP_SDER32_EL3_FUNC()
28197 static inline uint64_t BDK_AP_SDER32_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SDER32_EL3_FUNC(void)28198 static inline uint64_t BDK_AP_SDER32_EL3_FUNC(void)
28199 {
28200     return 0x30601010100ll;
28201 }
28202 
28203 #define typedef_BDK_AP_SDER32_EL3 bdk_ap_sder32_el3_t
28204 #define bustype_BDK_AP_SDER32_EL3 BDK_CSR_TYPE_SYSREG
28205 #define basename_BDK_AP_SDER32_EL3 "AP_SDER32_EL3"
28206 #define busnum_BDK_AP_SDER32_EL3 0
28207 #define arguments_BDK_AP_SDER32_EL3 -1,-1,-1,-1
28208 
28209 /**
28210  * Register (SYSREG) ap_sp_el0
28211  *
28212  * AP Stack Pointer EL0 Register
28213  * Holds the stack pointer if AP_SPSel[SP] is 0, or the stack pointer
28214  *     for EL0 if AP_SPSel[SP] is 1.
28215  */
28216 union bdk_ap_sp_el0
28217 {
28218     uint64_t u;
28219     struct bdk_ap_sp_el0_s
28220     {
28221 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28222         uint64_t data                  : 64; /**< [ 63:  0](R/W) Stack pointer. */
28223 #else /* Word 0 - Little Endian */
28224         uint64_t data                  : 64; /**< [ 63:  0](R/W) Stack pointer. */
28225 #endif /* Word 0 - End */
28226     } s;
28227     /* struct bdk_ap_sp_el0_s cn; */
28228 };
28229 typedef union bdk_ap_sp_el0 bdk_ap_sp_el0_t;
28230 
28231 #define BDK_AP_SP_EL0 BDK_AP_SP_EL0_FUNC()
28232 static inline uint64_t BDK_AP_SP_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SP_EL0_FUNC(void)28233 static inline uint64_t BDK_AP_SP_EL0_FUNC(void)
28234 {
28235     return 0x30004010000ll;
28236 }
28237 
28238 #define typedef_BDK_AP_SP_EL0 bdk_ap_sp_el0_t
28239 #define bustype_BDK_AP_SP_EL0 BDK_CSR_TYPE_SYSREG
28240 #define basename_BDK_AP_SP_EL0 "AP_SP_EL0"
28241 #define busnum_BDK_AP_SP_EL0 0
28242 #define arguments_BDK_AP_SP_EL0 -1,-1,-1,-1
28243 
28244 /**
28245  * Register (SYSREG) ap_sp_el1
28246  *
28247  * AP Stack Pointer EL1 Register
28248  * Holds the stack pointer for EL1 if AP_SPSel[SP] is 1 (the stack
28249  *     pointer selected is SP_ELx).
28250  */
28251 union bdk_ap_sp_el1
28252 {
28253     uint64_t u;
28254     struct bdk_ap_sp_el1_s
28255     {
28256 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28257         uint64_t data                  : 64; /**< [ 63:  0](R/W) Stack pointer. */
28258 #else /* Word 0 - Little Endian */
28259         uint64_t data                  : 64; /**< [ 63:  0](R/W) Stack pointer. */
28260 #endif /* Word 0 - End */
28261     } s;
28262     /* struct bdk_ap_sp_el1_s cn; */
28263 };
28264 typedef union bdk_ap_sp_el1 bdk_ap_sp_el1_t;
28265 
28266 #define BDK_AP_SP_EL1 BDK_AP_SP_EL1_FUNC()
28267 static inline uint64_t BDK_AP_SP_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SP_EL1_FUNC(void)28268 static inline uint64_t BDK_AP_SP_EL1_FUNC(void)
28269 {
28270     return 0x30404010000ll;
28271 }
28272 
28273 #define typedef_BDK_AP_SP_EL1 bdk_ap_sp_el1_t
28274 #define bustype_BDK_AP_SP_EL1 BDK_CSR_TYPE_SYSREG
28275 #define basename_BDK_AP_SP_EL1 "AP_SP_EL1"
28276 #define busnum_BDK_AP_SP_EL1 0
28277 #define arguments_BDK_AP_SP_EL1 -1,-1,-1,-1
28278 
28279 /**
28280  * Register (SYSREG) ap_sp_el2
28281  *
28282  * AP Stack Pointer EL2 Register
28283  * Holds the stack pointer for EL2 if AP_SPSel[SP] is 1 (the stack
28284  *     pointer selected is SP_ELx).
28285  */
28286 union bdk_ap_sp_el2
28287 {
28288     uint64_t u;
28289     struct bdk_ap_sp_el2_s
28290     {
28291 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28292         uint64_t data                  : 64; /**< [ 63:  0](R/W) Stack pointer. */
28293 #else /* Word 0 - Little Endian */
28294         uint64_t data                  : 64; /**< [ 63:  0](R/W) Stack pointer. */
28295 #endif /* Word 0 - End */
28296     } s;
28297     /* struct bdk_ap_sp_el2_s cn; */
28298 };
28299 typedef union bdk_ap_sp_el2 bdk_ap_sp_el2_t;
28300 
28301 #define BDK_AP_SP_EL2 BDK_AP_SP_EL2_FUNC()
28302 static inline uint64_t BDK_AP_SP_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SP_EL2_FUNC(void)28303 static inline uint64_t BDK_AP_SP_EL2_FUNC(void)
28304 {
28305     return 0x30604010000ll;
28306 }
28307 
28308 #define typedef_BDK_AP_SP_EL2 bdk_ap_sp_el2_t
28309 #define bustype_BDK_AP_SP_EL2 BDK_CSR_TYPE_SYSREG
28310 #define basename_BDK_AP_SP_EL2 "AP_SP_EL2"
28311 #define busnum_BDK_AP_SP_EL2 0
28312 #define arguments_BDK_AP_SP_EL2 -1,-1,-1,-1
28313 
28314 /**
28315  * Register (SYSREG) ap_spsel
28316  *
28317  * AP Stack Pointer Select Register
28318  * Allows the Stack Pointer to be selected between AP_SP_EL0 and
28319  *     SP_ELx.
28320  */
28321 union bdk_ap_spsel
28322 {
28323     uint32_t u;
28324     struct bdk_ap_spsel_s
28325     {
28326 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28327         uint32_t reserved_1_31         : 31;
28328         uint32_t sp                    : 1;  /**< [  0:  0](R/W) Stack pointer to use.
28329                                                                  0 = Use AP_SP_EL0 at all Exception levels.
28330                                                                  1 = Use SP_ELx for Exception level ELx. */
28331 #else /* Word 0 - Little Endian */
28332         uint32_t sp                    : 1;  /**< [  0:  0](R/W) Stack pointer to use.
28333                                                                  0 = Use AP_SP_EL0 at all Exception levels.
28334                                                                  1 = Use SP_ELx for Exception level ELx. */
28335         uint32_t reserved_1_31         : 31;
28336 #endif /* Word 0 - End */
28337     } s;
28338     /* struct bdk_ap_spsel_s cn; */
28339 };
28340 typedef union bdk_ap_spsel bdk_ap_spsel_t;
28341 
28342 #define BDK_AP_SPSEL BDK_AP_SPSEL_FUNC()
28343 static inline uint64_t BDK_AP_SPSEL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SPSEL_FUNC(void)28344 static inline uint64_t BDK_AP_SPSEL_FUNC(void)
28345 {
28346     return 0x30004020000ll;
28347 }
28348 
28349 #define typedef_BDK_AP_SPSEL bdk_ap_spsel_t
28350 #define bustype_BDK_AP_SPSEL BDK_CSR_TYPE_SYSREG
28351 #define basename_BDK_AP_SPSEL "AP_SPSEL"
28352 #define busnum_BDK_AP_SPSEL 0
28353 #define arguments_BDK_AP_SPSEL -1,-1,-1,-1
28354 
28355 /**
28356  * Register (SYSREG) ap_spsr_abt
28357  *
28358  * AP Saved Program Status Abort-mode Register
28359  * Holds the saved processor state when an exception is taken to
28360  *     Abort mode.
28361  * If EL1 does not support execution in AArch32, this register is RES0.
28362  */
28363 union bdk_ap_spsr_abt
28364 {
28365     uint32_t u;
28366     struct bdk_ap_spsr_abt_s
28367     {
28368 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28369         uint32_t reserved_0_31         : 32;
28370 #else /* Word 0 - Little Endian */
28371         uint32_t reserved_0_31         : 32;
28372 #endif /* Word 0 - End */
28373     } s;
28374     /* struct bdk_ap_spsr_abt_s cn; */
28375 };
28376 typedef union bdk_ap_spsr_abt bdk_ap_spsr_abt_t;
28377 
28378 #define BDK_AP_SPSR_ABT BDK_AP_SPSR_ABT_FUNC()
28379 static inline uint64_t BDK_AP_SPSR_ABT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SPSR_ABT_FUNC(void)28380 static inline uint64_t BDK_AP_SPSR_ABT_FUNC(void)
28381 {
28382     return 0x30404030100ll;
28383 }
28384 
28385 #define typedef_BDK_AP_SPSR_ABT bdk_ap_spsr_abt_t
28386 #define bustype_BDK_AP_SPSR_ABT BDK_CSR_TYPE_SYSREG
28387 #define basename_BDK_AP_SPSR_ABT "AP_SPSR_ABT"
28388 #define busnum_BDK_AP_SPSR_ABT 0
28389 #define arguments_BDK_AP_SPSR_ABT -1,-1,-1,-1
28390 
28391 /**
28392  * Register (SYSREG) ap_spsr_el#
28393  *
28394  * AP Saved Processor State Register
28395  * Holds the saved processor state when an exception is taken to
28396  *     EL*.
28397  */
28398 union bdk_ap_spsr_elx
28399 {
28400     uint32_t u;
28401     struct bdk_ap_spsr_elx_s
28402     {
28403 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28404         uint32_t n                     : 1;  /**< [ 31: 31](R/W) Set to the value of CPSR[N] on taking an exception to Monitor
28405                                                                      mode, and copied to CPSR[N] on executing an exception return
28406                                                                      operation in Monitor mode. */
28407         uint32_t z                     : 1;  /**< [ 30: 30](R/W) Set to the value of CPSR[Z] on taking an exception to Monitor
28408                                                                      mode, and copied to CPSR[Z] on executing an exception return
28409                                                                      operation in Monitor mode. */
28410         uint32_t cc                    : 1;  /**< [ 29: 29](R/W) Set to the value of CPSR[C] on taking an exception to Monitor
28411                                                                      mode, and copied to CPSR[C] on executing an exception return
28412                                                                      operation in Monitor mode. */
28413         uint32_t v                     : 1;  /**< [ 28: 28](R/W) Set to the value of CPSR[V] on taking an exception to Monitor
28414                                                                      mode, and copied to CPSR[V] on executing an exception return
28415                                                                      operation in Monitor mode. */
28416         uint32_t reserved_24_27        : 4;
28417         uint32_t uao                   : 1;  /**< [ 23: 23](R/W) User access override. SPSR_EL[23] only. */
28418         uint32_t pan                   : 1;  /**< [ 22: 22](R/W) 0 = Has no effect on the translation system.
28419                                                                  1 = Disables data read or data write access from EL1 (or EL2
28420                                                                     when AP_HCR_EL2[E2H] == 1 && AP_HCR_EL2[TGE] == 1) to a virtual
28421                                                                     address where access to the virtual address at EL0 is
28422                                                                     permitted at stage 1 by the combination of the AP[1] bit
28423                                                                     and the APTable[0] bits (if appropriate).  That is, when
28424                                                                     AP[1] == 1 && APTable[0] == 0 for all APTable bits
28425                                                                     associated with that virtual address.
28426 
28427                                                                     The AP_PAN bit has no effect on instruction accesses.
28428 
28429                                                                     If access is disabled, then the access will give rise to
28430                                                                     a stage 1 permission fault, taken in the same way as all
28431                                                                     other stage 1 permission faults. */
28432         uint32_t ss                    : 1;  /**< [ 21: 21](R/W) Software step. Indicates whether software step was
28433                                                                  enabled when an exception was taken. */
28434         uint32_t il                    : 1;  /**< [ 20: 20](R/W) The IL bit is added to process state to indicate that on
28435                                                                  exception return or as a result of an explicit change of the
28436                                                                  CPSR mode field in AArch32, an illegal state or mode was
28437                                                                  indicated, as described in section 3.5.6.3. Its value is
28438                                                                  reflected in the SPSR when it is set at a time when the
28439                                                                  process state IL bit was set either:
28440 
28441                                                                  - As a result of an UNdefined exception caused by the process
28442                                                                      state IL bit being set, or
28443 
28444                                                                  - Where execution was pre-empted between setting the process
28445                                                                      state IL bit and an UNdefined exception being taken.
28446 
28447                                                                  The IL bit is added as part of the ARMv8 architecture, but
28448                                                                  applies to execution in both AArch32 and AArch64. It is
28449                                                                  allocated into bit[20] of the SPSR. It is impossible for
28450                                                                  software to observe the value 1 in the CPSR in AArch32, or
28451                                                                  to observe the current Process State value in AArch64. */
28452         uint32_t reserved_10_19        : 10;
28453         uint32_t dd                    : 1;  /**< [  9:  9](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28454         uint32_t aa                    : 1;  /**< [  8:  8](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28455         uint32_t i                     : 1;  /**< [  7:  7](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28456         uint32_t f                     : 1;  /**< [  6:  6](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28457         uint32_t reserved_5            : 1;
28458         uint32_t from32                : 1;  /**< [  4:  4](R/W) 0 = Exception came from 64bit
28459                                                                  1 = Exception came from 32bit
28460                                                                  If 32bit is not implemented, then this causes an illegal state
28461                                                                  exception. */
28462         uint32_t el                    : 2;  /**< [  3:  2](R/W) Current exception level 00 - EL0 01 -EL1, 10 - EL2, 11 - EL3. */
28463         uint32_t reserved_1            : 1;
28464         uint32_t sp                    : 1;  /**< [  0:  0](R/W) AArch64 only - Stack Pointer selection - 0 - SP0, 1 - SPx. */
28465 #else /* Word 0 - Little Endian */
28466         uint32_t sp                    : 1;  /**< [  0:  0](R/W) AArch64 only - Stack Pointer selection - 0 - SP0, 1 - SPx. */
28467         uint32_t reserved_1            : 1;
28468         uint32_t el                    : 2;  /**< [  3:  2](R/W) Current exception level 00 - EL0 01 -EL1, 10 - EL2, 11 - EL3. */
28469         uint32_t from32                : 1;  /**< [  4:  4](R/W) 0 = Exception came from 64bit
28470                                                                  1 = Exception came from 32bit
28471                                                                  If 32bit is not implemented, then this causes an illegal state
28472                                                                  exception. */
28473         uint32_t reserved_5            : 1;
28474         uint32_t f                     : 1;  /**< [  6:  6](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28475         uint32_t i                     : 1;  /**< [  7:  7](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28476         uint32_t aa                    : 1;  /**< [  8:  8](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28477         uint32_t dd                    : 1;  /**< [  9:  9](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28478         uint32_t reserved_10_19        : 10;
28479         uint32_t il                    : 1;  /**< [ 20: 20](R/W) The IL bit is added to process state to indicate that on
28480                                                                  exception return or as a result of an explicit change of the
28481                                                                  CPSR mode field in AArch32, an illegal state or mode was
28482                                                                  indicated, as described in section 3.5.6.3. Its value is
28483                                                                  reflected in the SPSR when it is set at a time when the
28484                                                                  process state IL bit was set either:
28485 
28486                                                                  - As a result of an UNdefined exception caused by the process
28487                                                                      state IL bit being set, or
28488 
28489                                                                  - Where execution was pre-empted between setting the process
28490                                                                      state IL bit and an UNdefined exception being taken.
28491 
28492                                                                  The IL bit is added as part of the ARMv8 architecture, but
28493                                                                  applies to execution in both AArch32 and AArch64. It is
28494                                                                  allocated into bit[20] of the SPSR. It is impossible for
28495                                                                  software to observe the value 1 in the CPSR in AArch32, or
28496                                                                  to observe the current Process State value in AArch64. */
28497         uint32_t ss                    : 1;  /**< [ 21: 21](R/W) Software step. Indicates whether software step was
28498                                                                  enabled when an exception was taken. */
28499         uint32_t pan                   : 1;  /**< [ 22: 22](R/W) 0 = Has no effect on the translation system.
28500                                                                  1 = Disables data read or data write access from EL1 (or EL2
28501                                                                     when AP_HCR_EL2[E2H] == 1 && AP_HCR_EL2[TGE] == 1) to a virtual
28502                                                                     address where access to the virtual address at EL0 is
28503                                                                     permitted at stage 1 by the combination of the AP[1] bit
28504                                                                     and the APTable[0] bits (if appropriate).  That is, when
28505                                                                     AP[1] == 1 && APTable[0] == 0 for all APTable bits
28506                                                                     associated with that virtual address.
28507 
28508                                                                     The AP_PAN bit has no effect on instruction accesses.
28509 
28510                                                                     If access is disabled, then the access will give rise to
28511                                                                     a stage 1 permission fault, taken in the same way as all
28512                                                                     other stage 1 permission faults. */
28513         uint32_t uao                   : 1;  /**< [ 23: 23](R/W) User access override. SPSR_EL[23] only. */
28514         uint32_t reserved_24_27        : 4;
28515         uint32_t v                     : 1;  /**< [ 28: 28](R/W) Set to the value of CPSR[V] on taking an exception to Monitor
28516                                                                      mode, and copied to CPSR[V] on executing an exception return
28517                                                                      operation in Monitor mode. */
28518         uint32_t cc                    : 1;  /**< [ 29: 29](R/W) Set to the value of CPSR[C] on taking an exception to Monitor
28519                                                                      mode, and copied to CPSR[C] on executing an exception return
28520                                                                      operation in Monitor mode. */
28521         uint32_t z                     : 1;  /**< [ 30: 30](R/W) Set to the value of CPSR[Z] on taking an exception to Monitor
28522                                                                      mode, and copied to CPSR[Z] on executing an exception return
28523                                                                      operation in Monitor mode. */
28524         uint32_t n                     : 1;  /**< [ 31: 31](R/W) Set to the value of CPSR[N] on taking an exception to Monitor
28525                                                                      mode, and copied to CPSR[N] on executing an exception return
28526                                                                      operation in Monitor mode. */
28527 #endif /* Word 0 - End */
28528     } s;
28529     struct bdk_ap_spsr_elx_cn8
28530     {
28531 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28532         uint32_t n                     : 1;  /**< [ 31: 31](R/W) Set to the value of CPSR[N] on taking an exception to Monitor
28533                                                                      mode, and copied to CPSR[N] on executing an exception return
28534                                                                      operation in Monitor mode. */
28535         uint32_t z                     : 1;  /**< [ 30: 30](R/W) Set to the value of CPSR[Z] on taking an exception to Monitor
28536                                                                      mode, and copied to CPSR[Z] on executing an exception return
28537                                                                      operation in Monitor mode. */
28538         uint32_t cc                    : 1;  /**< [ 29: 29](R/W) Set to the value of CPSR[C] on taking an exception to Monitor
28539                                                                      mode, and copied to CPSR[C] on executing an exception return
28540                                                                      operation in Monitor mode. */
28541         uint32_t v                     : 1;  /**< [ 28: 28](R/W) Set to the value of CPSR[V] on taking an exception to Monitor
28542                                                                      mode, and copied to CPSR[V] on executing an exception return
28543                                                                      operation in Monitor mode. */
28544         uint32_t reserved_23_27        : 5;
28545         uint32_t pan                   : 1;  /**< [ 22: 22](R/W) 0 = Has no effect on the translation system.
28546                                                                  1 = Disables data read or data write access from EL1 (or EL2
28547                                                                     when AP_HCR_EL2[E2H] == 1 && AP_HCR_EL2[TGE] == 1) to a virtual
28548                                                                     address where access to the virtual address at EL0 is
28549                                                                     permitted at stage 1 by the combination of the AP[1] bit
28550                                                                     and the APTable[0] bits (if appropriate).  That is, when
28551                                                                     AP[1] == 1 && APTable[0] == 0 for all APTable bits
28552                                                                     associated with that virtual address.
28553 
28554                                                                     The AP_PAN bit has no effect on instruction accesses.
28555 
28556                                                                     If access is disabled, then the access will give rise to
28557                                                                     a stage 1 permission fault, taken in the same way as all
28558                                                                     other stage 1 permission faults. */
28559         uint32_t ss                    : 1;  /**< [ 21: 21](R/W) Software step. Indicates whether software step was
28560                                                                  enabled when an exception was taken. */
28561         uint32_t il                    : 1;  /**< [ 20: 20](R/W) The IL bit is added to process state to indicate that on
28562                                                                  exception return or as a result of an explicit change of the
28563                                                                  CPSR mode field in AArch32, an illegal state or mode was
28564                                                                  indicated, as described in section 3.5.6.3. Its value is
28565                                                                  reflected in the SPSR when it is set at a time when the
28566                                                                  process state IL bit was set either:
28567 
28568                                                                  - As a result of an UNdefined exception caused by the process
28569                                                                      state IL bit being set, or
28570 
28571                                                                  - Where execution was pre-empted between setting the process
28572                                                                      state IL bit and an UNdefined exception being taken.
28573 
28574                                                                  The IL bit is added as part of the ARMv8 architecture, but
28575                                                                  applies to execution in both AArch32 and AArch64. It is
28576                                                                  allocated into bit[20] of the SPSR. It is impossible for
28577                                                                  software to observe the value 1 in the CPSR in AArch32, or
28578                                                                  to observe the current Process State value in AArch64. */
28579         uint32_t reserved_10_19        : 10;
28580         uint32_t dd                    : 1;  /**< [  9:  9](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28581         uint32_t aa                    : 1;  /**< [  8:  8](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28582         uint32_t i                     : 1;  /**< [  7:  7](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28583         uint32_t f                     : 1;  /**< [  6:  6](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28584         uint32_t reserved_5            : 1;
28585         uint32_t from32                : 1;  /**< [  4:  4](R/W) 0 = Exception came from 64bit
28586                                                                  1 = Exception came from 32bit
28587                                                                  If 32bit is not implemented, then this causes an illegal state
28588                                                                  exception. */
28589         uint32_t el                    : 2;  /**< [  3:  2](R/W) Current exception level 00 - EL0 01 -EL1, 10 - EL2, 11 - EL3. */
28590         uint32_t reserved_1            : 1;
28591         uint32_t sp                    : 1;  /**< [  0:  0](R/W) AArch64 only - Stack Pointer selection - 0 - SP0, 1 - SPx. */
28592 #else /* Word 0 - Little Endian */
28593         uint32_t sp                    : 1;  /**< [  0:  0](R/W) AArch64 only - Stack Pointer selection - 0 - SP0, 1 - SPx. */
28594         uint32_t reserved_1            : 1;
28595         uint32_t el                    : 2;  /**< [  3:  2](R/W) Current exception level 00 - EL0 01 -EL1, 10 - EL2, 11 - EL3. */
28596         uint32_t from32                : 1;  /**< [  4:  4](R/W) 0 = Exception came from 64bit
28597                                                                  1 = Exception came from 32bit
28598                                                                  If 32bit is not implemented, then this causes an illegal state
28599                                                                  exception. */
28600         uint32_t reserved_5            : 1;
28601         uint32_t f                     : 1;  /**< [  6:  6](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28602         uint32_t i                     : 1;  /**< [  7:  7](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28603         uint32_t aa                    : 1;  /**< [  8:  8](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28604         uint32_t dd                    : 1;  /**< [  9:  9](R/W) Interrupt masks - can also be accessed as PSTATE[D,A,I,F]. */
28605         uint32_t reserved_10_19        : 10;
28606         uint32_t il                    : 1;  /**< [ 20: 20](R/W) The IL bit is added to process state to indicate that on
28607                                                                  exception return or as a result of an explicit change of the
28608                                                                  CPSR mode field in AArch32, an illegal state or mode was
28609                                                                  indicated, as described in section 3.5.6.3. Its value is
28610                                                                  reflected in the SPSR when it is set at a time when the
28611                                                                  process state IL bit was set either:
28612 
28613                                                                  - As a result of an UNdefined exception caused by the process
28614                                                                      state IL bit being set, or
28615 
28616                                                                  - Where execution was pre-empted between setting the process
28617                                                                      state IL bit and an UNdefined exception being taken.
28618 
28619                                                                  The IL bit is added as part of the ARMv8 architecture, but
28620                                                                  applies to execution in both AArch32 and AArch64. It is
28621                                                                  allocated into bit[20] of the SPSR. It is impossible for
28622                                                                  software to observe the value 1 in the CPSR in AArch32, or
28623                                                                  to observe the current Process State value in AArch64. */
28624         uint32_t ss                    : 1;  /**< [ 21: 21](R/W) Software step. Indicates whether software step was
28625                                                                  enabled when an exception was taken. */
28626         uint32_t pan                   : 1;  /**< [ 22: 22](R/W) 0 = Has no effect on the translation system.
28627                                                                  1 = Disables data read or data write access from EL1 (or EL2
28628                                                                     when AP_HCR_EL2[E2H] == 1 && AP_HCR_EL2[TGE] == 1) to a virtual
28629                                                                     address where access to the virtual address at EL0 is
28630                                                                     permitted at stage 1 by the combination of the AP[1] bit
28631                                                                     and the APTable[0] bits (if appropriate).  That is, when
28632                                                                     AP[1] == 1 && APTable[0] == 0 for all APTable bits
28633                                                                     associated with that virtual address.
28634 
28635                                                                     The AP_PAN bit has no effect on instruction accesses.
28636 
28637                                                                     If access is disabled, then the access will give rise to
28638                                                                     a stage 1 permission fault, taken in the same way as all
28639                                                                     other stage 1 permission faults. */
28640         uint32_t reserved_23_27        : 5;
28641         uint32_t v                     : 1;  /**< [ 28: 28](R/W) Set to the value of CPSR[V] on taking an exception to Monitor
28642                                                                      mode, and copied to CPSR[V] on executing an exception return
28643                                                                      operation in Monitor mode. */
28644         uint32_t cc                    : 1;  /**< [ 29: 29](R/W) Set to the value of CPSR[C] on taking an exception to Monitor
28645                                                                      mode, and copied to CPSR[C] on executing an exception return
28646                                                                      operation in Monitor mode. */
28647         uint32_t z                     : 1;  /**< [ 30: 30](R/W) Set to the value of CPSR[Z] on taking an exception to Monitor
28648                                                                      mode, and copied to CPSR[Z] on executing an exception return
28649                                                                      operation in Monitor mode. */
28650         uint32_t n                     : 1;  /**< [ 31: 31](R/W) Set to the value of CPSR[N] on taking an exception to Monitor
28651                                                                      mode, and copied to CPSR[N] on executing an exception return
28652                                                                      operation in Monitor mode. */
28653 #endif /* Word 0 - End */
28654     } cn8;
28655     /* struct bdk_ap_spsr_elx_s cn9; */
28656 };
28657 typedef union bdk_ap_spsr_elx bdk_ap_spsr_elx_t;
28658 
28659 static inline uint64_t BDK_AP_SPSR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_SPSR_ELX(unsigned long a)28660 static inline uint64_t BDK_AP_SPSR_ELX(unsigned long a)
28661 {
28662     if ((a>=1)&&(a<=3))
28663         return 0x30004000000ll + 0ll * ((a) & 0x3);
28664     __bdk_csr_fatal("AP_SPSR_ELX", 1, a, 0, 0, 0);
28665 }
28666 
28667 #define typedef_BDK_AP_SPSR_ELX(a) bdk_ap_spsr_elx_t
28668 #define bustype_BDK_AP_SPSR_ELX(a) BDK_CSR_TYPE_SYSREG
28669 #define basename_BDK_AP_SPSR_ELX(a) "AP_SPSR_ELX"
28670 #define busnum_BDK_AP_SPSR_ELX(a) (a)
28671 #define arguments_BDK_AP_SPSR_ELX(a) (a),-1,-1,-1
28672 
28673 /**
28674  * Register (SYSREG) ap_spsr_el12
28675  *
28676  * AP Saved Processor State EL2/3 Alias Register
28677  * Allows EL2 and EL3 access to SPSR_EL1 when AP_HCR_EL2[E2H]==1.
28678  */
28679 union bdk_ap_spsr_el12
28680 {
28681     uint32_t u;
28682     struct bdk_ap_spsr_el12_s
28683     {
28684 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28685         uint32_t reserved_0_31         : 32;
28686 #else /* Word 0 - Little Endian */
28687         uint32_t reserved_0_31         : 32;
28688 #endif /* Word 0 - End */
28689     } s;
28690     /* struct bdk_ap_spsr_el12_s cn; */
28691 };
28692 typedef union bdk_ap_spsr_el12 bdk_ap_spsr_el12_t;
28693 
28694 #define BDK_AP_SPSR_EL12 BDK_AP_SPSR_EL12_FUNC()
28695 static inline uint64_t BDK_AP_SPSR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SPSR_EL12_FUNC(void)28696 static inline uint64_t BDK_AP_SPSR_EL12_FUNC(void)
28697 {
28698     return 0x30504000000ll;
28699 }
28700 
28701 #define typedef_BDK_AP_SPSR_EL12 bdk_ap_spsr_el12_t
28702 #define bustype_BDK_AP_SPSR_EL12 BDK_CSR_TYPE_SYSREG
28703 #define basename_BDK_AP_SPSR_EL12 "AP_SPSR_EL12"
28704 #define busnum_BDK_AP_SPSR_EL12 0
28705 #define arguments_BDK_AP_SPSR_EL12 -1,-1,-1,-1
28706 
28707 /**
28708  * Register (SYSREG) ap_spsr_fiq
28709  *
28710  * AP Saved Program Status FIQ-mode Register
28711  * Holds the saved processor state when an exception is taken to
28712  *     FIQ mode.
28713  * If EL1 does not support execution in AArch32, this register is RES0.
28714  */
28715 union bdk_ap_spsr_fiq
28716 {
28717     uint32_t u;
28718     struct bdk_ap_spsr_fiq_s
28719     {
28720 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28721         uint32_t reserved_0_31         : 32;
28722 #else /* Word 0 - Little Endian */
28723         uint32_t reserved_0_31         : 32;
28724 #endif /* Word 0 - End */
28725     } s;
28726     /* struct bdk_ap_spsr_fiq_s cn; */
28727 };
28728 typedef union bdk_ap_spsr_fiq bdk_ap_spsr_fiq_t;
28729 
28730 #define BDK_AP_SPSR_FIQ BDK_AP_SPSR_FIQ_FUNC()
28731 static inline uint64_t BDK_AP_SPSR_FIQ_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SPSR_FIQ_FUNC(void)28732 static inline uint64_t BDK_AP_SPSR_FIQ_FUNC(void)
28733 {
28734     return 0x30404030300ll;
28735 }
28736 
28737 #define typedef_BDK_AP_SPSR_FIQ bdk_ap_spsr_fiq_t
28738 #define bustype_BDK_AP_SPSR_FIQ BDK_CSR_TYPE_SYSREG
28739 #define basename_BDK_AP_SPSR_FIQ "AP_SPSR_FIQ"
28740 #define busnum_BDK_AP_SPSR_FIQ 0
28741 #define arguments_BDK_AP_SPSR_FIQ -1,-1,-1,-1
28742 
28743 /**
28744  * Register (SYSREG) ap_spsr_irq
28745  *
28746  * AP Saved Program Status IRQ-mode Register
28747  * Holds the saved processor state when an exception is taken to
28748  *     IRQ mode.
28749  * If EL1 does not support execution in AArch32, this register is RES0.
28750  */
28751 union bdk_ap_spsr_irq
28752 {
28753     uint32_t u;
28754     struct bdk_ap_spsr_irq_s
28755     {
28756 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28757         uint32_t reserved_0_31         : 32;
28758 #else /* Word 0 - Little Endian */
28759         uint32_t reserved_0_31         : 32;
28760 #endif /* Word 0 - End */
28761     } s;
28762     /* struct bdk_ap_spsr_irq_s cn; */
28763 };
28764 typedef union bdk_ap_spsr_irq bdk_ap_spsr_irq_t;
28765 
28766 #define BDK_AP_SPSR_IRQ BDK_AP_SPSR_IRQ_FUNC()
28767 static inline uint64_t BDK_AP_SPSR_IRQ_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SPSR_IRQ_FUNC(void)28768 static inline uint64_t BDK_AP_SPSR_IRQ_FUNC(void)
28769 {
28770     return 0x30404030000ll;
28771 }
28772 
28773 #define typedef_BDK_AP_SPSR_IRQ bdk_ap_spsr_irq_t
28774 #define bustype_BDK_AP_SPSR_IRQ BDK_CSR_TYPE_SYSREG
28775 #define basename_BDK_AP_SPSR_IRQ "AP_SPSR_IRQ"
28776 #define busnum_BDK_AP_SPSR_IRQ 0
28777 #define arguments_BDK_AP_SPSR_IRQ -1,-1,-1,-1
28778 
28779 /**
28780  * Register (SYSREG) ap_spsr_und
28781  *
28782  * AP Saved Program Status Undefined-mode Register
28783  * Holds the saved processor state when an exception is taken to
28784  *     Undefined mode.
28785  * If EL1 does not support execution in AArch32, this register is RES0.
28786  */
28787 union bdk_ap_spsr_und
28788 {
28789     uint32_t u;
28790     struct bdk_ap_spsr_und_s
28791     {
28792 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28793         uint32_t reserved_0_31         : 32;
28794 #else /* Word 0 - Little Endian */
28795         uint32_t reserved_0_31         : 32;
28796 #endif /* Word 0 - End */
28797     } s;
28798     /* struct bdk_ap_spsr_und_s cn; */
28799 };
28800 typedef union bdk_ap_spsr_und bdk_ap_spsr_und_t;
28801 
28802 #define BDK_AP_SPSR_UND BDK_AP_SPSR_UND_FUNC()
28803 static inline uint64_t BDK_AP_SPSR_UND_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_SPSR_UND_FUNC(void)28804 static inline uint64_t BDK_AP_SPSR_UND_FUNC(void)
28805 {
28806     return 0x30404030200ll;
28807 }
28808 
28809 #define typedef_BDK_AP_SPSR_UND bdk_ap_spsr_und_t
28810 #define bustype_BDK_AP_SPSR_UND BDK_CSR_TYPE_SYSREG
28811 #define basename_BDK_AP_SPSR_UND "AP_SPSR_UND"
28812 #define busnum_BDK_AP_SPSR_UND 0
28813 #define arguments_BDK_AP_SPSR_UND -1,-1,-1,-1
28814 
28815 /**
28816  * Register (SYSREG) ap_tcr_el1
28817  *
28818  * AP Translation Control EL1 Register
28819  * Determines which of the Translation Table Base Registers
28820  *     defined the base address for a translation table walk required
28821  *     for the stage 1 translation of a memory access from EL0 or
28822  *     EL1. Also controls the translation table format and holds
28823  *     cacheability and shareability information.
28824  */
28825 union bdk_ap_tcr_el1
28826 {
28827     uint64_t u;
28828     struct bdk_ap_tcr_el1_s
28829     {
28830 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
28831         uint64_t reserved_43_63        : 21;
28832         uint64_t had1                  : 1;  /**< [ 42: 42](R/W) V8.1: Hierarchical Attribute Disable.
28833                                                                  HAD1(bit[42]): Hierarchical Attribute Disable for the TTBR1 region.
28834                                                                  0 = Hierarchical Attributes are enabled.
28835                                                                  1 = Hierarchical Attributes are disabled. */
28836         uint64_t had0                  : 1;  /**< [ 41: 41](R/W) V8.1: Hierarchical Attribute Disable.
28837                                                                  HAD0(bit[41]): Hierarchical Attribute Disable for the TTBR0 region.
28838                                                                  0 = Hierarchical Attributes are enabled.
28839                                                                  1 = Hierarchical Attributes are disabled. */
28840         uint64_t reserved_39_40        : 2;
28841         uint64_t tbi1                  : 1;  /**< [ 38: 38](R/W) Top Byte ignored - indicates whether the top byte of an
28842                                                                      address is used for address match for the AP_TTBR1_EL1 region, or
28843                                                                      ignored and used for tagged addresses.
28844 
28845                                                                  This affects addresses generated in EL0 and EL1 using AArch64
28846                                                                      where the address would be translated by tables pointed to by
28847                                                                      AP_TTBR1_EL1. It has an effect whether the EL1&0 translation
28848                                                                      regime is enabled or not.
28849 
28850                                                                  Additionally, this affects changes to the program counter,
28851                                                                      when TBI1 is 1 and bit [55] of the target address is 1, caused
28852                                                                      by:
28853 
28854                                                                   A branch or procedure return within EL0 or EL1.
28855 
28856                                                                   An exception taken to EL1.
28857 
28858                                                                   An exception return to EL0 or EL1.
28859 
28860                                                                  In these cases bits [63:56] of the address are also set to 1
28861                                                                      before it is stored in the PC.
28862                                                                  0 = Top Byte used in the address calculation.
28863                                                                  1 = Top Byte ignored in the address calculation. */
28864         uint64_t tbi0                  : 1;  /**< [ 37: 37](R/W) Top Byte ignored - indicates whether the top byte of an
28865                                                                      address is used for address match for the AP_TTBR0_EL1 region, or
28866                                                                      ignored and used for tagged addresses.
28867 
28868                                                                  This affects addresses generated in EL0 and EL1 using AArch64
28869                                                                      where the address would be translated by tables pointed to by
28870                                                                      AP_TTBR0_EL1. It has an effect whether the EL1&0 translation
28871                                                                      regime is enabled or not.
28872 
28873                                                                  Additionally, this affects changes to the program counter,
28874                                                                      when TBI0 is 1 and bit [55] of the target address is 0, caused
28875                                                                      by:
28876 
28877                                                                   A branch or procedure return within EL0 or EL1.
28878 
28879                                                                   An exception taken to EL1.
28880 
28881                                                                   An exception return to EL0 or EL1.
28882 
28883                                                                  In these cases bits [63:56] of the address are also set to 0
28884                                                                      before it is stored in the PC.
28885                                                                  0 = Top Byte used in the address calculation.
28886                                                                  1 = Top Byte ignored in the address calculation. */
28887         uint64_t as                    : 1;  /**< [ 36: 36](R/W) ASID Size.
28888                                                                  If the implementation has only 8 bits of ASID, this field is
28889                                                                      RES0.
28890                                                                  0 = 8 bit - the upper 8 bits of AP_TTBR0_EL1 and AP_TTBR1_EL1 are
28891                                                                      ignored by hardware for every purpose except reading back the
28892                                                                      register, and are treated as if they are all zeros for when
28893                                                                      used for allocation and matching entries in the TLB.
28894                                                                  1 = 16 bit - the upper 16 bits of AP_TTBR0_EL1 and AP_TTBR1_EL1 are used
28895                                                                      for allocation and matching in the TLB. */
28896         uint64_t reserved_35           : 1;
28897         uint64_t ips                   : 3;  /**< [ 34: 32](R/W) Intermediate Physical Address Size.
28898                                                                  0x0 = 32 bits, 4GB.
28899                                                                  0x1 = 36 bits, 64GB.
28900                                                                  0x2 = 40 bits, 1TB.
28901                                                                  0x3 = 42 bits, 4TB.
28902                                                                  0x4 = 44 bits, 16TB.
28903                                                                  0x5 = 48 bits, 256TB. */
28904         uint64_t tg1                   : 2;  /**< [ 31: 30](R/W) AP_TTBR1_EL1 Granule size.
28905 
28906                                                                  If the value is programmed to either a reserved value, or a
28907                                                                      size that has not been implemented, then the hardware will
28908                                                                      treat the field as if it has been programmed to an
28909                                                                      implementation defined choice of the sizes that has been
28910                                                                      implemented for all purposes other than the value read back
28911                                                                      from this register.
28912 
28913                                                                  It is implementation defined whether the value read back is
28914                                                                      the value programmed or the value that corresponds to the size
28915                                                                      chosen.
28916 
28917                                                                  0x1 = 16KB
28918                                                                  0x2 = 4KB
28919                                                                  0x3 = 64KB */
28920         uint64_t sh1                   : 2;  /**< [ 29: 28](R/W) Shareability attribute for memory associated with translation
28921                                                                      table walks using AP_TTBR1_EL1.
28922                                                                  0x0 = Non-shareable
28923                                                                  0x2 = Outer Shareable
28924                                                                  0x3 = Inner Shareable */
28925         uint64_t orgn1                 : 2;  /**< [ 27: 26](R/W) Outer cacheability attribute for memory associated with
28926                                                                      translation table walks using AP_TTBR1_EL1.
28927                                                                  0x0 = Normal memory, Outer Non-cacheable
28928                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable
28929                                                                  0x2 = Normal memory, Outer Write-Through Cacheable
28930                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable */
28931         uint64_t irgn1                 : 2;  /**< [ 25: 24](R/W) Inner cacheability attribute for memory associated with
28932                                                                      translation table walks using AP_TTBR1_EL1.
28933                                                                  0x0 = Normal memory, Inner Non-cacheable
28934                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable
28935                                                                  0x2 = Normal memory, Inner Write-Through Cacheable
28936                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable */
28937         uint64_t epd1                  : 1;  /**< [ 23: 23](R/W) Translation table walk disable for translations using
28938                                                                      AP_TTBR1_EL1. This bit controls whether a translation table walk
28939                                                                      is performed on a TLB miss, for an address that is translated
28940                                                                      using AP_TTBR1_EL1. The encoding of this bit is:
28941                                                                  0 = Perform translation table walks using AP_TTBR1_EL1.
28942                                                                  1 = A TLB miss on an address that is translated using AP_TTBR1_EL1
28943                                                                      generates a Translation fault. No translation table walk is
28944                                                                      performed. */
28945         uint64_t a1                    : 1;  /**< [ 22: 22](R/W) Selects whether AP_TTBR0_EL1 or AP_TTBR1_EL1 defines the ASID.
28946                                                                  0 =  AP_TTBR0_EL1[ASID] defines the ASID.
28947                                                                  1 =  AP_TTBR1_EL1[ASID] defines the ASID. */
28948         uint64_t t1sz                  : 6;  /**< [ 21: 16](R/W) The size offset of the memory region addressed by AP_TTBR1_EL1.
28949                                                                      The region size is 22^(64-T1SZ) bytes.
28950                                                                  The maximum and minimum possible values for T1SZ depend on the
28951                                                                      level of translation table and the memory translation granule
28952                                                                      size, as described in the AArch64 Virtual Memory System
28953                                                                      Architecture chapter. */
28954         uint64_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
28955                                                                      address register.
28956 
28957                                                                  If the value is programmed to either a reserved value, or a
28958                                                                      size that has not been implemented, then the hardware will
28959                                                                      treat the field as if it has been programmed to an
28960                                                                      implementation defined choice of the sizes that has been
28961                                                                      implemented for all purposes other than the value read back
28962                                                                      from this register.
28963 
28964                                                                  It is implementation defined whether the value read back is
28965                                                                      the value programmed or the value that corresponds to the size
28966                                                                      chosen.
28967 
28968                                                                  0x0 = 4KB.
28969                                                                  0x1 = 64KB.
28970                                                                  0x2 = 16KB. */
28971         uint64_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
28972                                                                      table walks using AP_TTBR0_EL1.
28973                                                                  0x0 = Non-shareable.
28974                                                                  0x2 = Outer Shareable.
28975                                                                  0x3 = Inner Shareable. */
28976         uint64_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
28977                                                                      translation table walks using AP_TTBR0_EL1.
28978                                                                  0x0 = Normal memory, Outer Non-cacheable.
28979                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
28980                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
28981                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
28982         uint64_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
28983                                                                      translation table walks using AP_TTBR0_EL1.
28984                                                                  0x0 = Normal memory, Inner Non-cacheable.
28985                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
28986                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
28987                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
28988         uint64_t epd0                  : 1;  /**< [  7:  7](R/W) Translation table walk disable for translations using TTBR0.
28989                                                                      This bit controls whether a translation table walk is
28990                                                                      performed on a TLB miss, for an address that is translated
28991                                                                      using TTBR0.
28992                                                                  0 = Perform translation table walks using TTBR0.
28993                                                                  1 = A TLB miss on an address that is translated using TTBR0
28994                                                                      generates a Translation fault. No translation table walk is
28995                                                                      performed. */
28996         uint64_t reserved_6            : 1;
28997         uint64_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL1.
28998                                                                      The region size is 2^(64-T0SZ) bytes.
28999 
29000                                                                  The maximum and minimum possible values for T0SZ depend on the
29001                                                                      level of translation table and the memory translation granule
29002                                                                      size, as described in the AArch64 Virtual Memory System
29003                                                                      Architecture chapter. */
29004 #else /* Word 0 - Little Endian */
29005         uint64_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL1.
29006                                                                      The region size is 2^(64-T0SZ) bytes.
29007 
29008                                                                  The maximum and minimum possible values for T0SZ depend on the
29009                                                                      level of translation table and the memory translation granule
29010                                                                      size, as described in the AArch64 Virtual Memory System
29011                                                                      Architecture chapter. */
29012         uint64_t reserved_6            : 1;
29013         uint64_t epd0                  : 1;  /**< [  7:  7](R/W) Translation table walk disable for translations using TTBR0.
29014                                                                      This bit controls whether a translation table walk is
29015                                                                      performed on a TLB miss, for an address that is translated
29016                                                                      using TTBR0.
29017                                                                  0 = Perform translation table walks using TTBR0.
29018                                                                  1 = A TLB miss on an address that is translated using TTBR0
29019                                                                      generates a Translation fault. No translation table walk is
29020                                                                      performed. */
29021         uint64_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
29022                                                                      translation table walks using AP_TTBR0_EL1.
29023                                                                  0x0 = Normal memory, Inner Non-cacheable.
29024                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
29025                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
29026                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
29027         uint64_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
29028                                                                      translation table walks using AP_TTBR0_EL1.
29029                                                                  0x0 = Normal memory, Outer Non-cacheable.
29030                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
29031                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
29032                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
29033         uint64_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
29034                                                                      table walks using AP_TTBR0_EL1.
29035                                                                  0x0 = Non-shareable.
29036                                                                  0x2 = Outer Shareable.
29037                                                                  0x3 = Inner Shareable. */
29038         uint64_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
29039                                                                      address register.
29040 
29041                                                                  If the value is programmed to either a reserved value, or a
29042                                                                      size that has not been implemented, then the hardware will
29043                                                                      treat the field as if it has been programmed to an
29044                                                                      implementation defined choice of the sizes that has been
29045                                                                      implemented for all purposes other than the value read back
29046                                                                      from this register.
29047 
29048                                                                  It is implementation defined whether the value read back is
29049                                                                      the value programmed or the value that corresponds to the size
29050                                                                      chosen.
29051 
29052                                                                  0x0 = 4KB.
29053                                                                  0x1 = 64KB.
29054                                                                  0x2 = 16KB. */
29055         uint64_t t1sz                  : 6;  /**< [ 21: 16](R/W) The size offset of the memory region addressed by AP_TTBR1_EL1.
29056                                                                      The region size is 22^(64-T1SZ) bytes.
29057                                                                  The maximum and minimum possible values for T1SZ depend on the
29058                                                                      level of translation table and the memory translation granule
29059                                                                      size, as described in the AArch64 Virtual Memory System
29060                                                                      Architecture chapter. */
29061         uint64_t a1                    : 1;  /**< [ 22: 22](R/W) Selects whether AP_TTBR0_EL1 or AP_TTBR1_EL1 defines the ASID.
29062                                                                  0 =  AP_TTBR0_EL1[ASID] defines the ASID.
29063                                                                  1 =  AP_TTBR1_EL1[ASID] defines the ASID. */
29064         uint64_t epd1                  : 1;  /**< [ 23: 23](R/W) Translation table walk disable for translations using
29065                                                                      AP_TTBR1_EL1. This bit controls whether a translation table walk
29066                                                                      is performed on a TLB miss, for an address that is translated
29067                                                                      using AP_TTBR1_EL1. The encoding of this bit is:
29068                                                                  0 = Perform translation table walks using AP_TTBR1_EL1.
29069                                                                  1 = A TLB miss on an address that is translated using AP_TTBR1_EL1
29070                                                                      generates a Translation fault. No translation table walk is
29071                                                                      performed. */
29072         uint64_t irgn1                 : 2;  /**< [ 25: 24](R/W) Inner cacheability attribute for memory associated with
29073                                                                      translation table walks using AP_TTBR1_EL1.
29074                                                                  0x0 = Normal memory, Inner Non-cacheable
29075                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable
29076                                                                  0x2 = Normal memory, Inner Write-Through Cacheable
29077                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable */
29078         uint64_t orgn1                 : 2;  /**< [ 27: 26](R/W) Outer cacheability attribute for memory associated with
29079                                                                      translation table walks using AP_TTBR1_EL1.
29080                                                                  0x0 = Normal memory, Outer Non-cacheable
29081                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable
29082                                                                  0x2 = Normal memory, Outer Write-Through Cacheable
29083                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable */
29084         uint64_t sh1                   : 2;  /**< [ 29: 28](R/W) Shareability attribute for memory associated with translation
29085                                                                      table walks using AP_TTBR1_EL1.
29086                                                                  0x0 = Non-shareable
29087                                                                  0x2 = Outer Shareable
29088                                                                  0x3 = Inner Shareable */
29089         uint64_t tg1                   : 2;  /**< [ 31: 30](R/W) AP_TTBR1_EL1 Granule size.
29090 
29091                                                                  If the value is programmed to either a reserved value, or a
29092                                                                      size that has not been implemented, then the hardware will
29093                                                                      treat the field as if it has been programmed to an
29094                                                                      implementation defined choice of the sizes that has been
29095                                                                      implemented for all purposes other than the value read back
29096                                                                      from this register.
29097 
29098                                                                  It is implementation defined whether the value read back is
29099                                                                      the value programmed or the value that corresponds to the size
29100                                                                      chosen.
29101 
29102                                                                  0x1 = 16KB
29103                                                                  0x2 = 4KB
29104                                                                  0x3 = 64KB */
29105         uint64_t ips                   : 3;  /**< [ 34: 32](R/W) Intermediate Physical Address Size.
29106                                                                  0x0 = 32 bits, 4GB.
29107                                                                  0x1 = 36 bits, 64GB.
29108                                                                  0x2 = 40 bits, 1TB.
29109                                                                  0x3 = 42 bits, 4TB.
29110                                                                  0x4 = 44 bits, 16TB.
29111                                                                  0x5 = 48 bits, 256TB. */
29112         uint64_t reserved_35           : 1;
29113         uint64_t as                    : 1;  /**< [ 36: 36](R/W) ASID Size.
29114                                                                  If the implementation has only 8 bits of ASID, this field is
29115                                                                      RES0.
29116                                                                  0 = 8 bit - the upper 8 bits of AP_TTBR0_EL1 and AP_TTBR1_EL1 are
29117                                                                      ignored by hardware for every purpose except reading back the
29118                                                                      register, and are treated as if they are all zeros for when
29119                                                                      used for allocation and matching entries in the TLB.
29120                                                                  1 = 16 bit - the upper 16 bits of AP_TTBR0_EL1 and AP_TTBR1_EL1 are used
29121                                                                      for allocation and matching in the TLB. */
29122         uint64_t tbi0                  : 1;  /**< [ 37: 37](R/W) Top Byte ignored - indicates whether the top byte of an
29123                                                                      address is used for address match for the AP_TTBR0_EL1 region, or
29124                                                                      ignored and used for tagged addresses.
29125 
29126                                                                  This affects addresses generated in EL0 and EL1 using AArch64
29127                                                                      where the address would be translated by tables pointed to by
29128                                                                      AP_TTBR0_EL1. It has an effect whether the EL1&0 translation
29129                                                                      regime is enabled or not.
29130 
29131                                                                  Additionally, this affects changes to the program counter,
29132                                                                      when TBI0 is 1 and bit [55] of the target address is 0, caused
29133                                                                      by:
29134 
29135                                                                   A branch or procedure return within EL0 or EL1.
29136 
29137                                                                   An exception taken to EL1.
29138 
29139                                                                   An exception return to EL0 or EL1.
29140 
29141                                                                  In these cases bits [63:56] of the address are also set to 0
29142                                                                      before it is stored in the PC.
29143                                                                  0 = Top Byte used in the address calculation.
29144                                                                  1 = Top Byte ignored in the address calculation. */
29145         uint64_t tbi1                  : 1;  /**< [ 38: 38](R/W) Top Byte ignored - indicates whether the top byte of an
29146                                                                      address is used for address match for the AP_TTBR1_EL1 region, or
29147                                                                      ignored and used for tagged addresses.
29148 
29149                                                                  This affects addresses generated in EL0 and EL1 using AArch64
29150                                                                      where the address would be translated by tables pointed to by
29151                                                                      AP_TTBR1_EL1. It has an effect whether the EL1&0 translation
29152                                                                      regime is enabled or not.
29153 
29154                                                                  Additionally, this affects changes to the program counter,
29155                                                                      when TBI1 is 1 and bit [55] of the target address is 1, caused
29156                                                                      by:
29157 
29158                                                                   A branch or procedure return within EL0 or EL1.
29159 
29160                                                                   An exception taken to EL1.
29161 
29162                                                                   An exception return to EL0 or EL1.
29163 
29164                                                                  In these cases bits [63:56] of the address are also set to 1
29165                                                                      before it is stored in the PC.
29166                                                                  0 = Top Byte used in the address calculation.
29167                                                                  1 = Top Byte ignored in the address calculation. */
29168         uint64_t reserved_39_40        : 2;
29169         uint64_t had0                  : 1;  /**< [ 41: 41](R/W) V8.1: Hierarchical Attribute Disable.
29170                                                                  HAD0(bit[41]): Hierarchical Attribute Disable for the TTBR0 region.
29171                                                                  0 = Hierarchical Attributes are enabled.
29172                                                                  1 = Hierarchical Attributes are disabled. */
29173         uint64_t had1                  : 1;  /**< [ 42: 42](R/W) V8.1: Hierarchical Attribute Disable.
29174                                                                  HAD1(bit[42]): Hierarchical Attribute Disable for the TTBR1 region.
29175                                                                  0 = Hierarchical Attributes are enabled.
29176                                                                  1 = Hierarchical Attributes are disabled. */
29177         uint64_t reserved_43_63        : 21;
29178 #endif /* Word 0 - End */
29179     } s;
29180     struct bdk_ap_tcr_el1_cn
29181     {
29182 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
29183         uint64_t reserved_43_63        : 21;
29184         uint64_t had1                  : 1;  /**< [ 42: 42](R/W) V8.1: Hierarchical Attribute Disable.
29185                                                                  HAD1(bit[42]): Hierarchical Attribute Disable for the TTBR1 region.
29186                                                                  0 = Hierarchical Attributes are enabled.
29187                                                                  1 = Hierarchical Attributes are disabled. */
29188         uint64_t had0                  : 1;  /**< [ 41: 41](R/W) V8.1: Hierarchical Attribute Disable.
29189                                                                  HAD0(bit[41]): Hierarchical Attribute Disable for the TTBR0 region.
29190                                                                  0 = Hierarchical Attributes are enabled.
29191                                                                  1 = Hierarchical Attributes are disabled. */
29192         uint64_t reserved_40           : 1;
29193         uint64_t reserved_39           : 1;
29194         uint64_t tbi1                  : 1;  /**< [ 38: 38](R/W) Top Byte ignored - indicates whether the top byte of an
29195                                                                      address is used for address match for the AP_TTBR1_EL1 region, or
29196                                                                      ignored and used for tagged addresses.
29197 
29198                                                                  This affects addresses generated in EL0 and EL1 using AArch64
29199                                                                      where the address would be translated by tables pointed to by
29200                                                                      AP_TTBR1_EL1. It has an effect whether the EL1&0 translation
29201                                                                      regime is enabled or not.
29202 
29203                                                                  Additionally, this affects changes to the program counter,
29204                                                                      when TBI1 is 1 and bit [55] of the target address is 1, caused
29205                                                                      by:
29206 
29207                                                                   A branch or procedure return within EL0 or EL1.
29208 
29209                                                                   An exception taken to EL1.
29210 
29211                                                                   An exception return to EL0 or EL1.
29212 
29213                                                                  In these cases bits [63:56] of the address are also set to 1
29214                                                                      before it is stored in the PC.
29215                                                                  0 = Top Byte used in the address calculation.
29216                                                                  1 = Top Byte ignored in the address calculation. */
29217         uint64_t tbi0                  : 1;  /**< [ 37: 37](R/W) Top Byte ignored - indicates whether the top byte of an
29218                                                                      address is used for address match for the AP_TTBR0_EL1 region, or
29219                                                                      ignored and used for tagged addresses.
29220 
29221                                                                  This affects addresses generated in EL0 and EL1 using AArch64
29222                                                                      where the address would be translated by tables pointed to by
29223                                                                      AP_TTBR0_EL1. It has an effect whether the EL1&0 translation
29224                                                                      regime is enabled or not.
29225 
29226                                                                  Additionally, this affects changes to the program counter,
29227                                                                      when TBI0 is 1 and bit [55] of the target address is 0, caused
29228                                                                      by:
29229 
29230                                                                   A branch or procedure return within EL0 or EL1.
29231 
29232                                                                   An exception taken to EL1.
29233 
29234                                                                   An exception return to EL0 or EL1.
29235 
29236                                                                  In these cases bits [63:56] of the address are also set to 0
29237                                                                      before it is stored in the PC.
29238                                                                  0 = Top Byte used in the address calculation.
29239                                                                  1 = Top Byte ignored in the address calculation. */
29240         uint64_t as                    : 1;  /**< [ 36: 36](R/W) ASID Size.
29241                                                                  If the implementation has only 8 bits of ASID, this field is
29242                                                                      RES0.
29243                                                                  0 = 8 bit - the upper 8 bits of AP_TTBR0_EL1 and AP_TTBR1_EL1 are
29244                                                                      ignored by hardware for every purpose except reading back the
29245                                                                      register, and are treated as if they are all zeros for when
29246                                                                      used for allocation and matching entries in the TLB.
29247                                                                  1 = 16 bit - the upper 16 bits of AP_TTBR0_EL1 and AP_TTBR1_EL1 are used
29248                                                                      for allocation and matching in the TLB. */
29249         uint64_t reserved_35           : 1;
29250         uint64_t ips                   : 3;  /**< [ 34: 32](R/W) Intermediate Physical Address Size.
29251                                                                  0x0 = 32 bits, 4GB.
29252                                                                  0x1 = 36 bits, 64GB.
29253                                                                  0x2 = 40 bits, 1TB.
29254                                                                  0x3 = 42 bits, 4TB.
29255                                                                  0x4 = 44 bits, 16TB.
29256                                                                  0x5 = 48 bits, 256TB. */
29257         uint64_t tg1                   : 2;  /**< [ 31: 30](R/W) AP_TTBR1_EL1 Granule size.
29258 
29259                                                                  If the value is programmed to either a reserved value, or a
29260                                                                      size that has not been implemented, then the hardware will
29261                                                                      treat the field as if it has been programmed to an
29262                                                                      implementation defined choice of the sizes that has been
29263                                                                      implemented for all purposes other than the value read back
29264                                                                      from this register.
29265 
29266                                                                  It is implementation defined whether the value read back is
29267                                                                      the value programmed or the value that corresponds to the size
29268                                                                      chosen.
29269 
29270                                                                  0x1 = 16KB
29271                                                                  0x2 = 4KB
29272                                                                  0x3 = 64KB */
29273         uint64_t sh1                   : 2;  /**< [ 29: 28](R/W) Shareability attribute for memory associated with translation
29274                                                                      table walks using AP_TTBR1_EL1.
29275                                                                  0x0 = Non-shareable
29276                                                                  0x2 = Outer Shareable
29277                                                                  0x3 = Inner Shareable */
29278         uint64_t orgn1                 : 2;  /**< [ 27: 26](R/W) Outer cacheability attribute for memory associated with
29279                                                                      translation table walks using AP_TTBR1_EL1.
29280                                                                  0x0 = Normal memory, Outer Non-cacheable
29281                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable
29282                                                                  0x2 = Normal memory, Outer Write-Through Cacheable
29283                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable */
29284         uint64_t irgn1                 : 2;  /**< [ 25: 24](R/W) Inner cacheability attribute for memory associated with
29285                                                                      translation table walks using AP_TTBR1_EL1.
29286                                                                  0x0 = Normal memory, Inner Non-cacheable
29287                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable
29288                                                                  0x2 = Normal memory, Inner Write-Through Cacheable
29289                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable */
29290         uint64_t epd1                  : 1;  /**< [ 23: 23](R/W) Translation table walk disable for translations using
29291                                                                      AP_TTBR1_EL1. This bit controls whether a translation table walk
29292                                                                      is performed on a TLB miss, for an address that is translated
29293                                                                      using AP_TTBR1_EL1. The encoding of this bit is:
29294                                                                  0 = Perform translation table walks using AP_TTBR1_EL1.
29295                                                                  1 = A TLB miss on an address that is translated using AP_TTBR1_EL1
29296                                                                      generates a Translation fault. No translation table walk is
29297                                                                      performed. */
29298         uint64_t a1                    : 1;  /**< [ 22: 22](R/W) Selects whether AP_TTBR0_EL1 or AP_TTBR1_EL1 defines the ASID.
29299                                                                  0 =  AP_TTBR0_EL1[ASID] defines the ASID.
29300                                                                  1 =  AP_TTBR1_EL1[ASID] defines the ASID. */
29301         uint64_t t1sz                  : 6;  /**< [ 21: 16](R/W) The size offset of the memory region addressed by AP_TTBR1_EL1.
29302                                                                      The region size is 22^(64-T1SZ) bytes.
29303                                                                  The maximum and minimum possible values for T1SZ depend on the
29304                                                                      level of translation table and the memory translation granule
29305                                                                      size, as described in the AArch64 Virtual Memory System
29306                                                                      Architecture chapter. */
29307         uint64_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
29308                                                                      address register.
29309 
29310                                                                  If the value is programmed to either a reserved value, or a
29311                                                                      size that has not been implemented, then the hardware will
29312                                                                      treat the field as if it has been programmed to an
29313                                                                      implementation defined choice of the sizes that has been
29314                                                                      implemented for all purposes other than the value read back
29315                                                                      from this register.
29316 
29317                                                                  It is implementation defined whether the value read back is
29318                                                                      the value programmed or the value that corresponds to the size
29319                                                                      chosen.
29320 
29321                                                                  0x0 = 4KB.
29322                                                                  0x1 = 64KB.
29323                                                                  0x2 = 16KB. */
29324         uint64_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
29325                                                                      table walks using AP_TTBR0_EL1.
29326                                                                  0x0 = Non-shareable.
29327                                                                  0x2 = Outer Shareable.
29328                                                                  0x3 = Inner Shareable. */
29329         uint64_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
29330                                                                      translation table walks using AP_TTBR0_EL1.
29331                                                                  0x0 = Normal memory, Outer Non-cacheable.
29332                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
29333                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
29334                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
29335         uint64_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
29336                                                                      translation table walks using AP_TTBR0_EL1.
29337                                                                  0x0 = Normal memory, Inner Non-cacheable.
29338                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
29339                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
29340                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
29341         uint64_t epd0                  : 1;  /**< [  7:  7](R/W) Translation table walk disable for translations using TTBR0.
29342                                                                      This bit controls whether a translation table walk is
29343                                                                      performed on a TLB miss, for an address that is translated
29344                                                                      using TTBR0.
29345                                                                  0 = Perform translation table walks using TTBR0.
29346                                                                  1 = A TLB miss on an address that is translated using TTBR0
29347                                                                      generates a Translation fault. No translation table walk is
29348                                                                      performed. */
29349         uint64_t reserved_6            : 1;
29350         uint64_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL1.
29351                                                                      The region size is 2^(64-T0SZ) bytes.
29352 
29353                                                                  The maximum and minimum possible values for T0SZ depend on the
29354                                                                      level of translation table and the memory translation granule
29355                                                                      size, as described in the AArch64 Virtual Memory System
29356                                                                      Architecture chapter. */
29357 #else /* Word 0 - Little Endian */
29358         uint64_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL1.
29359                                                                      The region size is 2^(64-T0SZ) bytes.
29360 
29361                                                                  The maximum and minimum possible values for T0SZ depend on the
29362                                                                      level of translation table and the memory translation granule
29363                                                                      size, as described in the AArch64 Virtual Memory System
29364                                                                      Architecture chapter. */
29365         uint64_t reserved_6            : 1;
29366         uint64_t epd0                  : 1;  /**< [  7:  7](R/W) Translation table walk disable for translations using TTBR0.
29367                                                                      This bit controls whether a translation table walk is
29368                                                                      performed on a TLB miss, for an address that is translated
29369                                                                      using TTBR0.
29370                                                                  0 = Perform translation table walks using TTBR0.
29371                                                                  1 = A TLB miss on an address that is translated using TTBR0
29372                                                                      generates a Translation fault. No translation table walk is
29373                                                                      performed. */
29374         uint64_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
29375                                                                      translation table walks using AP_TTBR0_EL1.
29376                                                                  0x0 = Normal memory, Inner Non-cacheable.
29377                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
29378                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
29379                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
29380         uint64_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
29381                                                                      translation table walks using AP_TTBR0_EL1.
29382                                                                  0x0 = Normal memory, Outer Non-cacheable.
29383                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
29384                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
29385                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
29386         uint64_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
29387                                                                      table walks using AP_TTBR0_EL1.
29388                                                                  0x0 = Non-shareable.
29389                                                                  0x2 = Outer Shareable.
29390                                                                  0x3 = Inner Shareable. */
29391         uint64_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
29392                                                                      address register.
29393 
29394                                                                  If the value is programmed to either a reserved value, or a
29395                                                                      size that has not been implemented, then the hardware will
29396                                                                      treat the field as if it has been programmed to an
29397                                                                      implementation defined choice of the sizes that has been
29398                                                                      implemented for all purposes other than the value read back
29399                                                                      from this register.
29400 
29401                                                                  It is implementation defined whether the value read back is
29402                                                                      the value programmed or the value that corresponds to the size
29403                                                                      chosen.
29404 
29405                                                                  0x0 = 4KB.
29406                                                                  0x1 = 64KB.
29407                                                                  0x2 = 16KB. */
29408         uint64_t t1sz                  : 6;  /**< [ 21: 16](R/W) The size offset of the memory region addressed by AP_TTBR1_EL1.
29409                                                                      The region size is 22^(64-T1SZ) bytes.
29410                                                                  The maximum and minimum possible values for T1SZ depend on the
29411                                                                      level of translation table and the memory translation granule
29412                                                                      size, as described in the AArch64 Virtual Memory System
29413                                                                      Architecture chapter. */
29414         uint64_t a1                    : 1;  /**< [ 22: 22](R/W) Selects whether AP_TTBR0_EL1 or AP_TTBR1_EL1 defines the ASID.
29415                                                                  0 =  AP_TTBR0_EL1[ASID] defines the ASID.
29416                                                                  1 =  AP_TTBR1_EL1[ASID] defines the ASID. */
29417         uint64_t epd1                  : 1;  /**< [ 23: 23](R/W) Translation table walk disable for translations using
29418                                                                      AP_TTBR1_EL1. This bit controls whether a translation table walk
29419                                                                      is performed on a TLB miss, for an address that is translated
29420                                                                      using AP_TTBR1_EL1. The encoding of this bit is:
29421                                                                  0 = Perform translation table walks using AP_TTBR1_EL1.
29422                                                                  1 = A TLB miss on an address that is translated using AP_TTBR1_EL1
29423                                                                      generates a Translation fault. No translation table walk is
29424                                                                      performed. */
29425         uint64_t irgn1                 : 2;  /**< [ 25: 24](R/W) Inner cacheability attribute for memory associated with
29426                                                                      translation table walks using AP_TTBR1_EL1.
29427                                                                  0x0 = Normal memory, Inner Non-cacheable
29428                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable
29429                                                                  0x2 = Normal memory, Inner Write-Through Cacheable
29430                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable */
29431         uint64_t orgn1                 : 2;  /**< [ 27: 26](R/W) Outer cacheability attribute for memory associated with
29432                                                                      translation table walks using AP_TTBR1_EL1.
29433                                                                  0x0 = Normal memory, Outer Non-cacheable
29434                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable
29435                                                                  0x2 = Normal memory, Outer Write-Through Cacheable
29436                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable */
29437         uint64_t sh1                   : 2;  /**< [ 29: 28](R/W) Shareability attribute for memory associated with translation
29438                                                                      table walks using AP_TTBR1_EL1.
29439                                                                  0x0 = Non-shareable
29440                                                                  0x2 = Outer Shareable
29441                                                                  0x3 = Inner Shareable */
29442         uint64_t tg1                   : 2;  /**< [ 31: 30](R/W) AP_TTBR1_EL1 Granule size.
29443 
29444                                                                  If the value is programmed to either a reserved value, or a
29445                                                                      size that has not been implemented, then the hardware will
29446                                                                      treat the field as if it has been programmed to an
29447                                                                      implementation defined choice of the sizes that has been
29448                                                                      implemented for all purposes other than the value read back
29449                                                                      from this register.
29450 
29451                                                                  It is implementation defined whether the value read back is
29452                                                                      the value programmed or the value that corresponds to the size
29453                                                                      chosen.
29454 
29455                                                                  0x1 = 16KB
29456                                                                  0x2 = 4KB
29457                                                                  0x3 = 64KB */
29458         uint64_t ips                   : 3;  /**< [ 34: 32](R/W) Intermediate Physical Address Size.
29459                                                                  0x0 = 32 bits, 4GB.
29460                                                                  0x1 = 36 bits, 64GB.
29461                                                                  0x2 = 40 bits, 1TB.
29462                                                                  0x3 = 42 bits, 4TB.
29463                                                                  0x4 = 44 bits, 16TB.
29464                                                                  0x5 = 48 bits, 256TB. */
29465         uint64_t reserved_35           : 1;
29466         uint64_t as                    : 1;  /**< [ 36: 36](R/W) ASID Size.
29467                                                                  If the implementation has only 8 bits of ASID, this field is
29468                                                                      RES0.
29469                                                                  0 = 8 bit - the upper 8 bits of AP_TTBR0_EL1 and AP_TTBR1_EL1 are
29470                                                                      ignored by hardware for every purpose except reading back the
29471                                                                      register, and are treated as if they are all zeros for when
29472                                                                      used for allocation and matching entries in the TLB.
29473                                                                  1 = 16 bit - the upper 16 bits of AP_TTBR0_EL1 and AP_TTBR1_EL1 are used
29474                                                                      for allocation and matching in the TLB. */
29475         uint64_t tbi0                  : 1;  /**< [ 37: 37](R/W) Top Byte ignored - indicates whether the top byte of an
29476                                                                      address is used for address match for the AP_TTBR0_EL1 region, or
29477                                                                      ignored and used for tagged addresses.
29478 
29479                                                                  This affects addresses generated in EL0 and EL1 using AArch64
29480                                                                      where the address would be translated by tables pointed to by
29481                                                                      AP_TTBR0_EL1. It has an effect whether the EL1&0 translation
29482                                                                      regime is enabled or not.
29483 
29484                                                                  Additionally, this affects changes to the program counter,
29485                                                                      when TBI0 is 1 and bit [55] of the target address is 0, caused
29486                                                                      by:
29487 
29488                                                                   A branch or procedure return within EL0 or EL1.
29489 
29490                                                                   An exception taken to EL1.
29491 
29492                                                                   An exception return to EL0 or EL1.
29493 
29494                                                                  In these cases bits [63:56] of the address are also set to 0
29495                                                                      before it is stored in the PC.
29496                                                                  0 = Top Byte used in the address calculation.
29497                                                                  1 = Top Byte ignored in the address calculation. */
29498         uint64_t tbi1                  : 1;  /**< [ 38: 38](R/W) Top Byte ignored - indicates whether the top byte of an
29499                                                                      address is used for address match for the AP_TTBR1_EL1 region, or
29500                                                                      ignored and used for tagged addresses.
29501 
29502                                                                  This affects addresses generated in EL0 and EL1 using AArch64
29503                                                                      where the address would be translated by tables pointed to by
29504                                                                      AP_TTBR1_EL1. It has an effect whether the EL1&0 translation
29505                                                                      regime is enabled or not.
29506 
29507                                                                  Additionally, this affects changes to the program counter,
29508                                                                      when TBI1 is 1 and bit [55] of the target address is 1, caused
29509                                                                      by:
29510 
29511                                                                   A branch or procedure return within EL0 or EL1.
29512 
29513                                                                   An exception taken to EL1.
29514 
29515                                                                   An exception return to EL0 or EL1.
29516 
29517                                                                  In these cases bits [63:56] of the address are also set to 1
29518                                                                      before it is stored in the PC.
29519                                                                  0 = Top Byte used in the address calculation.
29520                                                                  1 = Top Byte ignored in the address calculation. */
29521         uint64_t reserved_39           : 1;
29522         uint64_t reserved_40           : 1;
29523         uint64_t had0                  : 1;  /**< [ 41: 41](R/W) V8.1: Hierarchical Attribute Disable.
29524                                                                  HAD0(bit[41]): Hierarchical Attribute Disable for the TTBR0 region.
29525                                                                  0 = Hierarchical Attributes are enabled.
29526                                                                  1 = Hierarchical Attributes are disabled. */
29527         uint64_t had1                  : 1;  /**< [ 42: 42](R/W) V8.1: Hierarchical Attribute Disable.
29528                                                                  HAD1(bit[42]): Hierarchical Attribute Disable for the TTBR1 region.
29529                                                                  0 = Hierarchical Attributes are enabled.
29530                                                                  1 = Hierarchical Attributes are disabled. */
29531         uint64_t reserved_43_63        : 21;
29532 #endif /* Word 0 - End */
29533     } cn;
29534 };
29535 typedef union bdk_ap_tcr_el1 bdk_ap_tcr_el1_t;
29536 
29537 #define BDK_AP_TCR_EL1 BDK_AP_TCR_EL1_FUNC()
29538 static inline uint64_t BDK_AP_TCR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TCR_EL1_FUNC(void)29539 static inline uint64_t BDK_AP_TCR_EL1_FUNC(void)
29540 {
29541     return 0x30002000200ll;
29542 }
29543 
29544 #define typedef_BDK_AP_TCR_EL1 bdk_ap_tcr_el1_t
29545 #define bustype_BDK_AP_TCR_EL1 BDK_CSR_TYPE_SYSREG
29546 #define basename_BDK_AP_TCR_EL1 "AP_TCR_EL1"
29547 #define busnum_BDK_AP_TCR_EL1 0
29548 #define arguments_BDK_AP_TCR_EL1 -1,-1,-1,-1
29549 
29550 /**
29551  * Register (SYSREG) ap_tcr_el12
29552  *
29553  * AP Translation Control EL1/2 Register
29554  * Alias of AP_TCR_EL1 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
29555  */
29556 union bdk_ap_tcr_el12
29557 {
29558     uint64_t u;
29559     struct bdk_ap_tcr_el12_s
29560     {
29561 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
29562         uint64_t reserved_0_63         : 64;
29563 #else /* Word 0 - Little Endian */
29564         uint64_t reserved_0_63         : 64;
29565 #endif /* Word 0 - End */
29566     } s;
29567     /* struct bdk_ap_tcr_el12_s cn; */
29568 };
29569 typedef union bdk_ap_tcr_el12 bdk_ap_tcr_el12_t;
29570 
29571 #define BDK_AP_TCR_EL12 BDK_AP_TCR_EL12_FUNC()
29572 static inline uint64_t BDK_AP_TCR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TCR_EL12_FUNC(void)29573 static inline uint64_t BDK_AP_TCR_EL12_FUNC(void)
29574 {
29575     return 0x30502000200ll;
29576 }
29577 
29578 #define typedef_BDK_AP_TCR_EL12 bdk_ap_tcr_el12_t
29579 #define bustype_BDK_AP_TCR_EL12 BDK_CSR_TYPE_SYSREG
29580 #define basename_BDK_AP_TCR_EL12 "AP_TCR_EL12"
29581 #define busnum_BDK_AP_TCR_EL12 0
29582 #define arguments_BDK_AP_TCR_EL12 -1,-1,-1,-1
29583 
29584 /**
29585  * Register (SYSREG) ap_tcr_el2
29586  *
29587  * AP Translation Control Non-E2H (EL2) Register
29588  * Controls translation table walks required for the stage 1
29589  *     translation of memory accesses from EL2, and holds
29590  *     cacheability and shareability information for the accesses.
29591  *
29592  * This register is at the same select as AP_TCR_EL2_E2H and is used when E2H=0.
29593  */
29594 union bdk_ap_tcr_el2
29595 {
29596     uint32_t u;
29597     struct bdk_ap_tcr_el2_s
29598     {
29599 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
29600         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
29601         uint32_t reserved_25_30        : 6;
29602         uint32_t had                   : 1;  /**< [ 24: 24](R/W) V8.1: Hierarchical Attribute Disable.
29603                                                                  HAD (bit[24]): Hierarchical Attribute Disable.
29604                                                                  0 = Hierarchical Attributes are enabled.
29605                                                                  1 = Hierarchical Attributes are disabled. */
29606         uint32_t rsvd_23               : 1;  /**< [ 23: 23](RO) Reserved 1. */
29607         uint32_t reserved_21_22        : 2;
29608         uint32_t tbi                   : 1;  /**< [ 20: 20](R/W) Top Byte ignored - indicates whether the top byte of an
29609                                                                      address is used for address match for the AP_TTBR0_EL3 region, or
29610                                                                      ignored and used for tagged addresses.
29611 
29612                                                                  This affects addresses generated in EL3 using AArch64 where
29613                                                                      the address would be translated by tables pointed to by
29614                                                                      AP_TTBR0_EL3. It has an effect whether the EL3 translation regime
29615                                                                      is enabled or not.
29616 
29617                                                                  Additionally, this affects changes to the program counter,
29618                                                                      when TBI is 1, caused by:
29619                                                                  * A branch or procedure return within EL3.
29620                                                                  * A exception taken to EL3.
29621                                                                  * An exception return to EL3.
29622 
29623                                                                  In these cases bits [63:56] of the address are set to 0 before
29624                                                                      it is stored in the PC.
29625                                                                  0 = Top Byte used in the address calculation.
29626                                                                  1 = Top Byte ignored in the address calculation. */
29627         uint32_t reserved_19           : 1;
29628         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
29629 
29630                                                                  The reserved values behave in the same way as the0b101
29631                                                                  0x0 = 32 bits, 4GB.
29632                                                                  0x1 = 36 bits, 64GB.
29633                                                                  0x2 = 40 bits, 1TB.
29634                                                                  0x3 = 42 bits, 4TB.
29635                                                                  0x4 = 44 bits, 16TB.
29636                                                                  0x5 = 48 bits, 256TB. */
29637         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
29638                                                                      address register.
29639 
29640                                                                  If the value is programmed to either a reserved value, or a
29641                                                                      size that has not been implemented, then the hardware will
29642                                                                      treat the field as if it has been programmed to an
29643                                                                      implementation defined choice of the sizes that has been
29644                                                                      implemented for all purposes other than the value read back
29645                                                                      from this register.
29646 
29647                                                                  It is implementation defined whether the value read back is
29648                                                                      the value programmed or the value that corresponds to the size
29649                                                                      chosen.
29650 
29651                                                                  0x0 = 4KB.
29652                                                                  0x1 = 64KB.
29653                                                                  0x2 = 16KB. */
29654         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
29655                                                                      table walks using AP_TTBR0_EL3.
29656 
29657                                                                  0x0 = Non-shareable.
29658                                                                  0x2 = Outer Shareable.
29659                                                                  0x3 = Inner Shareable. */
29660         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
29661                                                                      translation table walks using AP_TTBR0_EL3.
29662                                                                  0x0 = Normal memory, Outer Non-cacheable.
29663                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
29664                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
29665                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
29666         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
29667                                                                      translation table walks using AP_TTBR0_EL3.
29668                                                                  0x0 = Normal memory, Inner Non-cacheable.
29669                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
29670                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
29671                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
29672         uint32_t reserved_6_7          : 2;
29673         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL3.
29674                                                                      The region size is 22^(64-T0SZ) bytes.
29675 
29676                                                                  The maximum and minimum possible values for T0SZ depend on the
29677                                                                      level of translation table and the memory translation granule
29678                                                                      size, as described in the AArch64 Virtual Memory System
29679                                                                      Architecture chapter. */
29680 #else /* Word 0 - Little Endian */
29681         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL3.
29682                                                                      The region size is 22^(64-T0SZ) bytes.
29683 
29684                                                                  The maximum and minimum possible values for T0SZ depend on the
29685                                                                      level of translation table and the memory translation granule
29686                                                                      size, as described in the AArch64 Virtual Memory System
29687                                                                      Architecture chapter. */
29688         uint32_t reserved_6_7          : 2;
29689         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
29690                                                                      translation table walks using AP_TTBR0_EL3.
29691                                                                  0x0 = Normal memory, Inner Non-cacheable.
29692                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
29693                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
29694                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
29695         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
29696                                                                      translation table walks using AP_TTBR0_EL3.
29697                                                                  0x0 = Normal memory, Outer Non-cacheable.
29698                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
29699                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
29700                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
29701         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
29702                                                                      table walks using AP_TTBR0_EL3.
29703 
29704                                                                  0x0 = Non-shareable.
29705                                                                  0x2 = Outer Shareable.
29706                                                                  0x3 = Inner Shareable. */
29707         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
29708                                                                      address register.
29709 
29710                                                                  If the value is programmed to either a reserved value, or a
29711                                                                      size that has not been implemented, then the hardware will
29712                                                                      treat the field as if it has been programmed to an
29713                                                                      implementation defined choice of the sizes that has been
29714                                                                      implemented for all purposes other than the value read back
29715                                                                      from this register.
29716 
29717                                                                  It is implementation defined whether the value read back is
29718                                                                      the value programmed or the value that corresponds to the size
29719                                                                      chosen.
29720 
29721                                                                  0x0 = 4KB.
29722                                                                  0x1 = 64KB.
29723                                                                  0x2 = 16KB. */
29724         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
29725 
29726                                                                  The reserved values behave in the same way as the0b101
29727                                                                  0x0 = 32 bits, 4GB.
29728                                                                  0x1 = 36 bits, 64GB.
29729                                                                  0x2 = 40 bits, 1TB.
29730                                                                  0x3 = 42 bits, 4TB.
29731                                                                  0x4 = 44 bits, 16TB.
29732                                                                  0x5 = 48 bits, 256TB. */
29733         uint32_t reserved_19           : 1;
29734         uint32_t tbi                   : 1;  /**< [ 20: 20](R/W) Top Byte ignored - indicates whether the top byte of an
29735                                                                      address is used for address match for the AP_TTBR0_EL3 region, or
29736                                                                      ignored and used for tagged addresses.
29737 
29738                                                                  This affects addresses generated in EL3 using AArch64 where
29739                                                                      the address would be translated by tables pointed to by
29740                                                                      AP_TTBR0_EL3. It has an effect whether the EL3 translation regime
29741                                                                      is enabled or not.
29742 
29743                                                                  Additionally, this affects changes to the program counter,
29744                                                                      when TBI is 1, caused by:
29745                                                                  * A branch or procedure return within EL3.
29746                                                                  * A exception taken to EL3.
29747                                                                  * An exception return to EL3.
29748 
29749                                                                  In these cases bits [63:56] of the address are set to 0 before
29750                                                                      it is stored in the PC.
29751                                                                  0 = Top Byte used in the address calculation.
29752                                                                  1 = Top Byte ignored in the address calculation. */
29753         uint32_t reserved_21_22        : 2;
29754         uint32_t rsvd_23               : 1;  /**< [ 23: 23](RO) Reserved 1. */
29755         uint32_t had                   : 1;  /**< [ 24: 24](R/W) V8.1: Hierarchical Attribute Disable.
29756                                                                  HAD (bit[24]): Hierarchical Attribute Disable.
29757                                                                  0 = Hierarchical Attributes are enabled.
29758                                                                  1 = Hierarchical Attributes are disabled. */
29759         uint32_t reserved_25_30        : 6;
29760         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
29761 #endif /* Word 0 - End */
29762     } s;
29763     struct bdk_ap_tcr_el2_cn
29764     {
29765 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
29766         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
29767         uint32_t reserved_25_30        : 6;
29768         uint32_t had                   : 1;  /**< [ 24: 24](R/W) V8.1: Hierarchical Attribute Disable.
29769                                                                  HAD (bit[24]): Hierarchical Attribute Disable.
29770                                                                  0 = Hierarchical Attributes are enabled.
29771                                                                  1 = Hierarchical Attributes are disabled. */
29772         uint32_t rsvd_23               : 1;  /**< [ 23: 23](RO) Reserved 1. */
29773         uint32_t reserved_22           : 1;
29774         uint32_t reserved_21           : 1;
29775         uint32_t tbi                   : 1;  /**< [ 20: 20](R/W) Top Byte ignored - indicates whether the top byte of an
29776                                                                      address is used for address match for the AP_TTBR0_EL3 region, or
29777                                                                      ignored and used for tagged addresses.
29778 
29779                                                                  This affects addresses generated in EL3 using AArch64 where
29780                                                                      the address would be translated by tables pointed to by
29781                                                                      AP_TTBR0_EL3. It has an effect whether the EL3 translation regime
29782                                                                      is enabled or not.
29783 
29784                                                                  Additionally, this affects changes to the program counter,
29785                                                                      when TBI is 1, caused by:
29786                                                                  * A branch or procedure return within EL3.
29787                                                                  * A exception taken to EL3.
29788                                                                  * An exception return to EL3.
29789 
29790                                                                  In these cases bits [63:56] of the address are set to 0 before
29791                                                                      it is stored in the PC.
29792                                                                  0 = Top Byte used in the address calculation.
29793                                                                  1 = Top Byte ignored in the address calculation. */
29794         uint32_t reserved_19           : 1;
29795         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
29796 
29797                                                                  The reserved values behave in the same way as the0b101
29798                                                                  0x0 = 32 bits, 4GB.
29799                                                                  0x1 = 36 bits, 64GB.
29800                                                                  0x2 = 40 bits, 1TB.
29801                                                                  0x3 = 42 bits, 4TB.
29802                                                                  0x4 = 44 bits, 16TB.
29803                                                                  0x5 = 48 bits, 256TB. */
29804         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
29805                                                                      address register.
29806 
29807                                                                  If the value is programmed to either a reserved value, or a
29808                                                                      size that has not been implemented, then the hardware will
29809                                                                      treat the field as if it has been programmed to an
29810                                                                      implementation defined choice of the sizes that has been
29811                                                                      implemented for all purposes other than the value read back
29812                                                                      from this register.
29813 
29814                                                                  It is implementation defined whether the value read back is
29815                                                                      the value programmed or the value that corresponds to the size
29816                                                                      chosen.
29817 
29818                                                                  0x0 = 4KB.
29819                                                                  0x1 = 64KB.
29820                                                                  0x2 = 16KB. */
29821         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
29822                                                                      table walks using AP_TTBR0_EL3.
29823 
29824                                                                  0x0 = Non-shareable.
29825                                                                  0x2 = Outer Shareable.
29826                                                                  0x3 = Inner Shareable. */
29827         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
29828                                                                      translation table walks using AP_TTBR0_EL3.
29829                                                                  0x0 = Normal memory, Outer Non-cacheable.
29830                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
29831                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
29832                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
29833         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
29834                                                                      translation table walks using AP_TTBR0_EL3.
29835                                                                  0x0 = Normal memory, Inner Non-cacheable.
29836                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
29837                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
29838                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
29839         uint32_t reserved_6_7          : 2;
29840         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL3.
29841                                                                      The region size is 22^(64-T0SZ) bytes.
29842 
29843                                                                  The maximum and minimum possible values for T0SZ depend on the
29844                                                                      level of translation table and the memory translation granule
29845                                                                      size, as described in the AArch64 Virtual Memory System
29846                                                                      Architecture chapter. */
29847 #else /* Word 0 - Little Endian */
29848         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL3.
29849                                                                      The region size is 22^(64-T0SZ) bytes.
29850 
29851                                                                  The maximum and minimum possible values for T0SZ depend on the
29852                                                                      level of translation table and the memory translation granule
29853                                                                      size, as described in the AArch64 Virtual Memory System
29854                                                                      Architecture chapter. */
29855         uint32_t reserved_6_7          : 2;
29856         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
29857                                                                      translation table walks using AP_TTBR0_EL3.
29858                                                                  0x0 = Normal memory, Inner Non-cacheable.
29859                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
29860                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
29861                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
29862         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
29863                                                                      translation table walks using AP_TTBR0_EL3.
29864                                                                  0x0 = Normal memory, Outer Non-cacheable.
29865                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
29866                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
29867                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
29868         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
29869                                                                      table walks using AP_TTBR0_EL3.
29870 
29871                                                                  0x0 = Non-shareable.
29872                                                                  0x2 = Outer Shareable.
29873                                                                  0x3 = Inner Shareable. */
29874         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
29875                                                                      address register.
29876 
29877                                                                  If the value is programmed to either a reserved value, or a
29878                                                                      size that has not been implemented, then the hardware will
29879                                                                      treat the field as if it has been programmed to an
29880                                                                      implementation defined choice of the sizes that has been
29881                                                                      implemented for all purposes other than the value read back
29882                                                                      from this register.
29883 
29884                                                                  It is implementation defined whether the value read back is
29885                                                                      the value programmed or the value that corresponds to the size
29886                                                                      chosen.
29887 
29888                                                                  0x0 = 4KB.
29889                                                                  0x1 = 64KB.
29890                                                                  0x2 = 16KB. */
29891         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
29892 
29893                                                                  The reserved values behave in the same way as the0b101
29894                                                                  0x0 = 32 bits, 4GB.
29895                                                                  0x1 = 36 bits, 64GB.
29896                                                                  0x2 = 40 bits, 1TB.
29897                                                                  0x3 = 42 bits, 4TB.
29898                                                                  0x4 = 44 bits, 16TB.
29899                                                                  0x5 = 48 bits, 256TB. */
29900         uint32_t reserved_19           : 1;
29901         uint32_t tbi                   : 1;  /**< [ 20: 20](R/W) Top Byte ignored - indicates whether the top byte of an
29902                                                                      address is used for address match for the AP_TTBR0_EL3 region, or
29903                                                                      ignored and used for tagged addresses.
29904 
29905                                                                  This affects addresses generated in EL3 using AArch64 where
29906                                                                      the address would be translated by tables pointed to by
29907                                                                      AP_TTBR0_EL3. It has an effect whether the EL3 translation regime
29908                                                                      is enabled or not.
29909 
29910                                                                  Additionally, this affects changes to the program counter,
29911                                                                      when TBI is 1, caused by:
29912                                                                  * A branch or procedure return within EL3.
29913                                                                  * A exception taken to EL3.
29914                                                                  * An exception return to EL3.
29915 
29916                                                                  In these cases bits [63:56] of the address are set to 0 before
29917                                                                      it is stored in the PC.
29918                                                                  0 = Top Byte used in the address calculation.
29919                                                                  1 = Top Byte ignored in the address calculation. */
29920         uint32_t reserved_21           : 1;
29921         uint32_t reserved_22           : 1;
29922         uint32_t rsvd_23               : 1;  /**< [ 23: 23](RO) Reserved 1. */
29923         uint32_t had                   : 1;  /**< [ 24: 24](R/W) V8.1: Hierarchical Attribute Disable.
29924                                                                  HAD (bit[24]): Hierarchical Attribute Disable.
29925                                                                  0 = Hierarchical Attributes are enabled.
29926                                                                  1 = Hierarchical Attributes are disabled. */
29927         uint32_t reserved_25_30        : 6;
29928         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
29929 #endif /* Word 0 - End */
29930     } cn;
29931 };
29932 typedef union bdk_ap_tcr_el2 bdk_ap_tcr_el2_t;
29933 
29934 #define BDK_AP_TCR_EL2 BDK_AP_TCR_EL2_FUNC()
29935 static inline uint64_t BDK_AP_TCR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TCR_EL2_FUNC(void)29936 static inline uint64_t BDK_AP_TCR_EL2_FUNC(void)
29937 {
29938     return 0x30402000200ll;
29939 }
29940 
29941 #define typedef_BDK_AP_TCR_EL2 bdk_ap_tcr_el2_t
29942 #define bustype_BDK_AP_TCR_EL2 BDK_CSR_TYPE_SYSREG
29943 #define basename_BDK_AP_TCR_EL2 "AP_TCR_EL2"
29944 #define busnum_BDK_AP_TCR_EL2 0
29945 #define arguments_BDK_AP_TCR_EL2 -1,-1,-1,-1
29946 
29947 /**
29948  * Register (SYSREG) ap_tcr_el2_e2h
29949  *
29950  * AP Translation Control EL2 E2H (v8.1) Register
29951  * [v8.1] Determines which of the Translation Table Base Registers
29952  *     defined the base address for a translation table walk required
29953  *     for the stage 1 translation of a memory access from EL2.  Also
29954  *     controls the translation table format and holds cacheability and
29955  *     shareability information.
29956  *
29957  * This register is at the same select as AP_TCR_EL2 and is used when E2H=1.
29958  */
29959 union bdk_ap_tcr_el2_e2h
29960 {
29961     uint64_t u;
29962     struct bdk_ap_tcr_el2_e2h_s
29963     {
29964 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
29965         uint64_t reserved_43_63        : 21;
29966         uint64_t had1                  : 1;  /**< [ 42: 42](R/W) V8.1: Hierarchical Attribute Disable.
29967                                                                  HAD1(bit[42]): Hierarchical Attribute Disable for the TTBR1 region.
29968                                                                  0 = Hierarchical Attributes are enabled.
29969                                                                  1 = Hierarchical Attributes are disabled. */
29970         uint64_t had0                  : 1;  /**< [ 41: 41](R/W) V8.1: Hierarchical Attribute Disable.
29971                                                                  HAD0(bit[41]): Hierarchical Attribute Disable for the TTBR0 region.
29972                                                                  0 = Hierarchical Attributes are enabled.
29973                                                                  1 = Hierarchical Attributes are disabled. */
29974         uint64_t reserved_39_40        : 2;
29975         uint64_t tbi1                  : 1;  /**< [ 38: 38](R/W) Top Byte ignored - indicates whether the top byte of an
29976                                                                      address is used for address match for the AP_TTBR1_EL2 region, or
29977                                                                      ignored and used for tagged addresses.
29978 
29979                                                                  This affects addresses generated in EL2 using AArch64
29980                                                                      where the address would be translated by tables pointed to by
29981                                                                      AP_TTBR1_EL2. It has an effect whether the EL2 translation
29982                                                                      regime is enabled or not.
29983 
29984                                                                  Additionally, this affects changes to the program counter,
29985                                                                      when TBI1 is 1 and bit [55] of the target address is 1, caused
29986                                                                      by:
29987                                                                  * A branch or procedure return within EL2.
29988                                                                  * An exception taken to EL2.
29989                                                                  * An exception return to EL2.
29990 
29991                                                                  In these cases bits [63:56] of the address are also set to 1
29992                                                                      before it is stored in the PC.
29993                                                                  0 = Top Byte used in the address calculation.
29994                                                                  1 = Top Byte ignored in the address calculation. */
29995         uint64_t tbi0                  : 1;  /**< [ 37: 37](R/W) Top Byte ignored - indicates whether the top byte of an
29996                                                                      address is used for address match for the AP_TTBR0_EL2 region, or
29997                                                                      ignored and used for tagged addresses.
29998 
29999                                                                  This affects addresses generated in EL2 using AArch64
30000                                                                      where the address would be translated by tables pointed to by
30001                                                                      AP_TTBR0_EL2. It has an effect whether the EL2 translation
30002                                                                      regime is enabled or not.
30003 
30004                                                                  Additionally, this affects changes to the program counter,
30005                                                                      when TBI0 is 1 and bit [55] of the target address is 0, caused
30006                                                                      by:
30007                                                                  * A branch or procedure return within EL2.
30008                                                                  * An exception taken to EL2.
30009                                                                  * An exception return to EL2.
30010 
30011                                                                  In these cases bits [63:56] of the address are also set to 0
30012                                                                      before it is stored in the PC.
30013                                                                  0 = Top Byte used in the address calculation.
30014                                                                  1 = Top Byte ignored in the address calculation. */
30015         uint64_t as                    : 1;  /**< [ 36: 36](R/W) ASID Size.
30016                                                                  If the implementation has only 8 bits of ASID, this field is
30017                                                                      RES0.
30018                                                                  0 = 8 bit - the upper 8 bits of AP_TTBR0_EL2 and AP_TTBR1_EL2 are
30019                                                                      ignored by hardware for every purpose except reading back the
30020                                                                      register, and are treated as if they are all zeros for when
30021                                                                      used for allocation and matching entries in the TLB.
30022                                                                  1 = 16 bit - the upper 16 bits of AP_TTBR0_EL2 and AP_TTBR1_EL2 are used
30023                                                                      for allocation and matching in the TLB. */
30024         uint64_t reserved_35           : 1;
30025         uint64_t ips                   : 3;  /**< [ 34: 32](R/W) Intermediate Physical Address Size.
30026                                                                  0x0 = 32 bits, 4GB.
30027                                                                  0x1 = 36 bits, 64GB.
30028                                                                  0x2 = 40 bits, 1TB.
30029                                                                  0x3 = 42 bits, 4TB.
30030                                                                  0x4 = 44 bits, 16TB.
30031                                                                  0x5 = 48 bits, 256TB. */
30032         uint64_t tg1                   : 2;  /**< [ 31: 30](R/W) AP_TTBR1_EL2 Granule size.
30033 
30034                                                                  If the value is programmed to either a reserved value, or a
30035                                                                      size that has not been implemented, then the hardware will
30036                                                                      treat the field as if it has been programmed to an
30037                                                                      implementation defined choice of the sizes that has been
30038                                                                      implemented for all purposes other than the value read back
30039                                                                      from this register.
30040 
30041                                                                  It is implementation defined whether the value read back is
30042                                                                      the value programmed or the value that corresponds to the size
30043                                                                      chosen.
30044 
30045                                                                  0x1 = 16KB.
30046                                                                  0x2 = 4KB.
30047                                                                  0x3 = 64KB. */
30048         uint64_t sh1                   : 2;  /**< [ 29: 28](R/W) Shareability attribute for memory associated with translation
30049                                                                      table walks using AP_TTBR1_EL2.
30050 
30051                                                                  0x0 = Non-shareable.
30052                                                                  0x2 = Outer Shareable.
30053                                                                  0x3 = Inner Shareable. */
30054         uint64_t orgn1                 : 2;  /**< [ 27: 26](R/W) Outer cacheability attribute for memory associated with
30055                                                                      translation table walks using AP_TTBR1_EL2.
30056                                                                  0x0 = Normal memory, Outer Non-cacheable.
30057                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30058                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30059                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30060         uint64_t irgn1                 : 2;  /**< [ 25: 24](R/W) Inner cacheability attribute for memory associated with
30061                                                                      translation table walks using AP_TTBR1_EL2.
30062                                                                  0x0 = Normal memory, Inner Non-cacheable.
30063                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30064                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30065                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30066         uint64_t epd1                  : 1;  /**< [ 23: 23](R/W) Translation table walk disable for translations using
30067                                                                      AP_TTBR1_EL2. This bit controls whether a translation table walk
30068                                                                      is performed on a TLB miss, for an address that is translated
30069                                                                      using AP_TTBR1_EL2. The encoding of this bit is:
30070                                                                  0 = Perform translation table walks using AP_TTBR1_EL2.
30071                                                                  1 = A TLB miss on an address that is translated using AP_TTBR1_EL2
30072                                                                      generates a Translation fault. No translation table walk is
30073                                                                      performed. */
30074         uint64_t a1                    : 1;  /**< [ 22: 22](R/W) Selects whether AP_TTBR0_EL2 or AP_TTBR1_EL2 defines the ASID. The
30075                                                                      encoding of this bit is:
30076                                                                  0 =  AP_TTBR0_EL2[ASID] defines the ASID.
30077                                                                  1 =  AP_TTBR1_EL2[ASID] defines the ASID. */
30078         uint64_t t1sz                  : 6;  /**< [ 21: 16](R/W) The size offset of the memory region addressed by AP_TTBR1_EL2.
30079                                                                      The region size is 22^(64-T1SZ) bytes.
30080                                                                  The maximum and minimum possible values for T1SZ depend on the
30081                                                                      level of translation table and the memory translation granule
30082                                                                      size, as described in the AArch64 Virtual Memory System
30083                                                                      Architecture chapter. */
30084         uint64_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
30085                                                                      address register.
30086 
30087                                                                  If the value is programmed to either a reserved value, or a
30088                                                                      size that has not been implemented, then the hardware will
30089                                                                      treat the field as if it has been programmed to an
30090                                                                      implementation defined choice of the sizes that has been
30091                                                                      implemented for all purposes other than the value read back
30092                                                                      from this register.
30093 
30094                                                                  It is implementation defined whether the value read back is
30095                                                                      the value programmed or the value that corresponds to the size
30096                                                                      chosen.
30097 
30098                                                                  0x0 = 4KB.
30099                                                                  0x1 = 64KB.
30100                                                                  0x2 = 16KB. */
30101         uint64_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
30102                                                                      table walks using AP_TTBR0_EL2.
30103 
30104                                                                  0x0 = Non-shareable.
30105                                                                  0x2 = Outer Shareable.
30106                                                                  0x3 = Inner Shareable. */
30107         uint64_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
30108                                                                      translation table walks using AP_TTBR0_EL2.
30109                                                                  0x0 = Normal memory, Outer Non-cacheable.
30110                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30111                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30112                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30113         uint64_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
30114                                                                      translation table walks using AP_TTBR0_EL2.
30115                                                                  0x0 = Normal memory, Inner Non-cacheable.
30116                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30117                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30118                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30119         uint64_t epd0                  : 1;  /**< [  7:  7](R/W) Translation table walk disable for translations using TTBR0.
30120                                                                      This bit controls whether a translation table walk is
30121                                                                      performed on a TLB miss, for an address that is translated
30122                                                                      using TTBR0. The encoding of this bit is:
30123                                                                  0 = Perform translation table walks using TTBR0.
30124                                                                  1 = A TLB miss on an address that is translated using TTBR0
30125                                                                      generates a Translation fault. No translation table walk is
30126                                                                      performed. */
30127         uint64_t reserved_6            : 1;
30128         uint64_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL2.
30129                                                                      The region size is 22^(64-T0SZ) bytes.
30130                                                                  The maximum and minimum possible values for T0SZ depend on the
30131                                                                      level of translation table and the memory translation granule
30132                                                                      size, as described in the AArch64 Virtual Memory System
30133                                                                      Architecture chapter. */
30134 #else /* Word 0 - Little Endian */
30135         uint64_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL2.
30136                                                                      The region size is 22^(64-T0SZ) bytes.
30137                                                                  The maximum and minimum possible values for T0SZ depend on the
30138                                                                      level of translation table and the memory translation granule
30139                                                                      size, as described in the AArch64 Virtual Memory System
30140                                                                      Architecture chapter. */
30141         uint64_t reserved_6            : 1;
30142         uint64_t epd0                  : 1;  /**< [  7:  7](R/W) Translation table walk disable for translations using TTBR0.
30143                                                                      This bit controls whether a translation table walk is
30144                                                                      performed on a TLB miss, for an address that is translated
30145                                                                      using TTBR0. The encoding of this bit is:
30146                                                                  0 = Perform translation table walks using TTBR0.
30147                                                                  1 = A TLB miss on an address that is translated using TTBR0
30148                                                                      generates a Translation fault. No translation table walk is
30149                                                                      performed. */
30150         uint64_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
30151                                                                      translation table walks using AP_TTBR0_EL2.
30152                                                                  0x0 = Normal memory, Inner Non-cacheable.
30153                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30154                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30155                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30156         uint64_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
30157                                                                      translation table walks using AP_TTBR0_EL2.
30158                                                                  0x0 = Normal memory, Outer Non-cacheable.
30159                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30160                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30161                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30162         uint64_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
30163                                                                      table walks using AP_TTBR0_EL2.
30164 
30165                                                                  0x0 = Non-shareable.
30166                                                                  0x2 = Outer Shareable.
30167                                                                  0x3 = Inner Shareable. */
30168         uint64_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
30169                                                                      address register.
30170 
30171                                                                  If the value is programmed to either a reserved value, or a
30172                                                                      size that has not been implemented, then the hardware will
30173                                                                      treat the field as if it has been programmed to an
30174                                                                      implementation defined choice of the sizes that has been
30175                                                                      implemented for all purposes other than the value read back
30176                                                                      from this register.
30177 
30178                                                                  It is implementation defined whether the value read back is
30179                                                                      the value programmed or the value that corresponds to the size
30180                                                                      chosen.
30181 
30182                                                                  0x0 = 4KB.
30183                                                                  0x1 = 64KB.
30184                                                                  0x2 = 16KB. */
30185         uint64_t t1sz                  : 6;  /**< [ 21: 16](R/W) The size offset of the memory region addressed by AP_TTBR1_EL2.
30186                                                                      The region size is 22^(64-T1SZ) bytes.
30187                                                                  The maximum and minimum possible values for T1SZ depend on the
30188                                                                      level of translation table and the memory translation granule
30189                                                                      size, as described in the AArch64 Virtual Memory System
30190                                                                      Architecture chapter. */
30191         uint64_t a1                    : 1;  /**< [ 22: 22](R/W) Selects whether AP_TTBR0_EL2 or AP_TTBR1_EL2 defines the ASID. The
30192                                                                      encoding of this bit is:
30193                                                                  0 =  AP_TTBR0_EL2[ASID] defines the ASID.
30194                                                                  1 =  AP_TTBR1_EL2[ASID] defines the ASID. */
30195         uint64_t epd1                  : 1;  /**< [ 23: 23](R/W) Translation table walk disable for translations using
30196                                                                      AP_TTBR1_EL2. This bit controls whether a translation table walk
30197                                                                      is performed on a TLB miss, for an address that is translated
30198                                                                      using AP_TTBR1_EL2. The encoding of this bit is:
30199                                                                  0 = Perform translation table walks using AP_TTBR1_EL2.
30200                                                                  1 = A TLB miss on an address that is translated using AP_TTBR1_EL2
30201                                                                      generates a Translation fault. No translation table walk is
30202                                                                      performed. */
30203         uint64_t irgn1                 : 2;  /**< [ 25: 24](R/W) Inner cacheability attribute for memory associated with
30204                                                                      translation table walks using AP_TTBR1_EL2.
30205                                                                  0x0 = Normal memory, Inner Non-cacheable.
30206                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30207                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30208                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30209         uint64_t orgn1                 : 2;  /**< [ 27: 26](R/W) Outer cacheability attribute for memory associated with
30210                                                                      translation table walks using AP_TTBR1_EL2.
30211                                                                  0x0 = Normal memory, Outer Non-cacheable.
30212                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30213                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30214                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30215         uint64_t sh1                   : 2;  /**< [ 29: 28](R/W) Shareability attribute for memory associated with translation
30216                                                                      table walks using AP_TTBR1_EL2.
30217 
30218                                                                  0x0 = Non-shareable.
30219                                                                  0x2 = Outer Shareable.
30220                                                                  0x3 = Inner Shareable. */
30221         uint64_t tg1                   : 2;  /**< [ 31: 30](R/W) AP_TTBR1_EL2 Granule size.
30222 
30223                                                                  If the value is programmed to either a reserved value, or a
30224                                                                      size that has not been implemented, then the hardware will
30225                                                                      treat the field as if it has been programmed to an
30226                                                                      implementation defined choice of the sizes that has been
30227                                                                      implemented for all purposes other than the value read back
30228                                                                      from this register.
30229 
30230                                                                  It is implementation defined whether the value read back is
30231                                                                      the value programmed or the value that corresponds to the size
30232                                                                      chosen.
30233 
30234                                                                  0x1 = 16KB.
30235                                                                  0x2 = 4KB.
30236                                                                  0x3 = 64KB. */
30237         uint64_t ips                   : 3;  /**< [ 34: 32](R/W) Intermediate Physical Address Size.
30238                                                                  0x0 = 32 bits, 4GB.
30239                                                                  0x1 = 36 bits, 64GB.
30240                                                                  0x2 = 40 bits, 1TB.
30241                                                                  0x3 = 42 bits, 4TB.
30242                                                                  0x4 = 44 bits, 16TB.
30243                                                                  0x5 = 48 bits, 256TB. */
30244         uint64_t reserved_35           : 1;
30245         uint64_t as                    : 1;  /**< [ 36: 36](R/W) ASID Size.
30246                                                                  If the implementation has only 8 bits of ASID, this field is
30247                                                                      RES0.
30248                                                                  0 = 8 bit - the upper 8 bits of AP_TTBR0_EL2 and AP_TTBR1_EL2 are
30249                                                                      ignored by hardware for every purpose except reading back the
30250                                                                      register, and are treated as if they are all zeros for when
30251                                                                      used for allocation and matching entries in the TLB.
30252                                                                  1 = 16 bit - the upper 16 bits of AP_TTBR0_EL2 and AP_TTBR1_EL2 are used
30253                                                                      for allocation and matching in the TLB. */
30254         uint64_t tbi0                  : 1;  /**< [ 37: 37](R/W) Top Byte ignored - indicates whether the top byte of an
30255                                                                      address is used for address match for the AP_TTBR0_EL2 region, or
30256                                                                      ignored and used for tagged addresses.
30257 
30258                                                                  This affects addresses generated in EL2 using AArch64
30259                                                                      where the address would be translated by tables pointed to by
30260                                                                      AP_TTBR0_EL2. It has an effect whether the EL2 translation
30261                                                                      regime is enabled or not.
30262 
30263                                                                  Additionally, this affects changes to the program counter,
30264                                                                      when TBI0 is 1 and bit [55] of the target address is 0, caused
30265                                                                      by:
30266                                                                  * A branch or procedure return within EL2.
30267                                                                  * An exception taken to EL2.
30268                                                                  * An exception return to EL2.
30269 
30270                                                                  In these cases bits [63:56] of the address are also set to 0
30271                                                                      before it is stored in the PC.
30272                                                                  0 = Top Byte used in the address calculation.
30273                                                                  1 = Top Byte ignored in the address calculation. */
30274         uint64_t tbi1                  : 1;  /**< [ 38: 38](R/W) Top Byte ignored - indicates whether the top byte of an
30275                                                                      address is used for address match for the AP_TTBR1_EL2 region, or
30276                                                                      ignored and used for tagged addresses.
30277 
30278                                                                  This affects addresses generated in EL2 using AArch64
30279                                                                      where the address would be translated by tables pointed to by
30280                                                                      AP_TTBR1_EL2. It has an effect whether the EL2 translation
30281                                                                      regime is enabled or not.
30282 
30283                                                                  Additionally, this affects changes to the program counter,
30284                                                                      when TBI1 is 1 and bit [55] of the target address is 1, caused
30285                                                                      by:
30286                                                                  * A branch or procedure return within EL2.
30287                                                                  * An exception taken to EL2.
30288                                                                  * An exception return to EL2.
30289 
30290                                                                  In these cases bits [63:56] of the address are also set to 1
30291                                                                      before it is stored in the PC.
30292                                                                  0 = Top Byte used in the address calculation.
30293                                                                  1 = Top Byte ignored in the address calculation. */
30294         uint64_t reserved_39_40        : 2;
30295         uint64_t had0                  : 1;  /**< [ 41: 41](R/W) V8.1: Hierarchical Attribute Disable.
30296                                                                  HAD0(bit[41]): Hierarchical Attribute Disable for the TTBR0 region.
30297                                                                  0 = Hierarchical Attributes are enabled.
30298                                                                  1 = Hierarchical Attributes are disabled. */
30299         uint64_t had1                  : 1;  /**< [ 42: 42](R/W) V8.1: Hierarchical Attribute Disable.
30300                                                                  HAD1(bit[42]): Hierarchical Attribute Disable for the TTBR1 region.
30301                                                                  0 = Hierarchical Attributes are enabled.
30302                                                                  1 = Hierarchical Attributes are disabled. */
30303         uint64_t reserved_43_63        : 21;
30304 #endif /* Word 0 - End */
30305     } s;
30306     struct bdk_ap_tcr_el2_e2h_cn
30307     {
30308 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
30309         uint64_t reserved_43_63        : 21;
30310         uint64_t had1                  : 1;  /**< [ 42: 42](R/W) V8.1: Hierarchical Attribute Disable.
30311                                                                  HAD1(bit[42]): Hierarchical Attribute Disable for the TTBR1 region.
30312                                                                  0 = Hierarchical Attributes are enabled.
30313                                                                  1 = Hierarchical Attributes are disabled. */
30314         uint64_t had0                  : 1;  /**< [ 41: 41](R/W) V8.1: Hierarchical Attribute Disable.
30315                                                                  HAD0(bit[41]): Hierarchical Attribute Disable for the TTBR0 region.
30316                                                                  0 = Hierarchical Attributes are enabled.
30317                                                                  1 = Hierarchical Attributes are disabled. */
30318         uint64_t reserved_40           : 1;
30319         uint64_t reserved_39           : 1;
30320         uint64_t tbi1                  : 1;  /**< [ 38: 38](R/W) Top Byte ignored - indicates whether the top byte of an
30321                                                                      address is used for address match for the AP_TTBR1_EL2 region, or
30322                                                                      ignored and used for tagged addresses.
30323 
30324                                                                  This affects addresses generated in EL2 using AArch64
30325                                                                      where the address would be translated by tables pointed to by
30326                                                                      AP_TTBR1_EL2. It has an effect whether the EL2 translation
30327                                                                      regime is enabled or not.
30328 
30329                                                                  Additionally, this affects changes to the program counter,
30330                                                                      when TBI1 is 1 and bit [55] of the target address is 1, caused
30331                                                                      by:
30332                                                                  * A branch or procedure return within EL2.
30333                                                                  * An exception taken to EL2.
30334                                                                  * An exception return to EL2.
30335 
30336                                                                  In these cases bits [63:56] of the address are also set to 1
30337                                                                      before it is stored in the PC.
30338                                                                  0 = Top Byte used in the address calculation.
30339                                                                  1 = Top Byte ignored in the address calculation. */
30340         uint64_t tbi0                  : 1;  /**< [ 37: 37](R/W) Top Byte ignored - indicates whether the top byte of an
30341                                                                      address is used for address match for the AP_TTBR0_EL2 region, or
30342                                                                      ignored and used for tagged addresses.
30343 
30344                                                                  This affects addresses generated in EL2 using AArch64
30345                                                                      where the address would be translated by tables pointed to by
30346                                                                      AP_TTBR0_EL2. It has an effect whether the EL2 translation
30347                                                                      regime is enabled or not.
30348 
30349                                                                  Additionally, this affects changes to the program counter,
30350                                                                      when TBI0 is 1 and bit [55] of the target address is 0, caused
30351                                                                      by:
30352                                                                  * A branch or procedure return within EL2.
30353                                                                  * An exception taken to EL2.
30354                                                                  * An exception return to EL2.
30355 
30356                                                                  In these cases bits [63:56] of the address are also set to 0
30357                                                                      before it is stored in the PC.
30358                                                                  0 = Top Byte used in the address calculation.
30359                                                                  1 = Top Byte ignored in the address calculation. */
30360         uint64_t as                    : 1;  /**< [ 36: 36](R/W) ASID Size.
30361                                                                  If the implementation has only 8 bits of ASID, this field is
30362                                                                      RES0.
30363                                                                  0 = 8 bit - the upper 8 bits of AP_TTBR0_EL2 and AP_TTBR1_EL2 are
30364                                                                      ignored by hardware for every purpose except reading back the
30365                                                                      register, and are treated as if they are all zeros for when
30366                                                                      used for allocation and matching entries in the TLB.
30367                                                                  1 = 16 bit - the upper 16 bits of AP_TTBR0_EL2 and AP_TTBR1_EL2 are used
30368                                                                      for allocation and matching in the TLB. */
30369         uint64_t reserved_35           : 1;
30370         uint64_t ips                   : 3;  /**< [ 34: 32](R/W) Intermediate Physical Address Size.
30371                                                                  0x0 = 32 bits, 4GB.
30372                                                                  0x1 = 36 bits, 64GB.
30373                                                                  0x2 = 40 bits, 1TB.
30374                                                                  0x3 = 42 bits, 4TB.
30375                                                                  0x4 = 44 bits, 16TB.
30376                                                                  0x5 = 48 bits, 256TB. */
30377         uint64_t tg1                   : 2;  /**< [ 31: 30](R/W) AP_TTBR1_EL2 Granule size.
30378 
30379                                                                  If the value is programmed to either a reserved value, or a
30380                                                                      size that has not been implemented, then the hardware will
30381                                                                      treat the field as if it has been programmed to an
30382                                                                      implementation defined choice of the sizes that has been
30383                                                                      implemented for all purposes other than the value read back
30384                                                                      from this register.
30385 
30386                                                                  It is implementation defined whether the value read back is
30387                                                                      the value programmed or the value that corresponds to the size
30388                                                                      chosen.
30389 
30390                                                                  0x1 = 16KB.
30391                                                                  0x2 = 4KB.
30392                                                                  0x3 = 64KB. */
30393         uint64_t sh1                   : 2;  /**< [ 29: 28](R/W) Shareability attribute for memory associated with translation
30394                                                                      table walks using AP_TTBR1_EL2.
30395 
30396                                                                  0x0 = Non-shareable.
30397                                                                  0x2 = Outer Shareable.
30398                                                                  0x3 = Inner Shareable. */
30399         uint64_t orgn1                 : 2;  /**< [ 27: 26](R/W) Outer cacheability attribute for memory associated with
30400                                                                      translation table walks using AP_TTBR1_EL2.
30401                                                                  0x0 = Normal memory, Outer Non-cacheable.
30402                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30403                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30404                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30405         uint64_t irgn1                 : 2;  /**< [ 25: 24](R/W) Inner cacheability attribute for memory associated with
30406                                                                      translation table walks using AP_TTBR1_EL2.
30407                                                                  0x0 = Normal memory, Inner Non-cacheable.
30408                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30409                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30410                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30411         uint64_t epd1                  : 1;  /**< [ 23: 23](R/W) Translation table walk disable for translations using
30412                                                                      AP_TTBR1_EL2. This bit controls whether a translation table walk
30413                                                                      is performed on a TLB miss, for an address that is translated
30414                                                                      using AP_TTBR1_EL2. The encoding of this bit is:
30415                                                                  0 = Perform translation table walks using AP_TTBR1_EL2.
30416                                                                  1 = A TLB miss on an address that is translated using AP_TTBR1_EL2
30417                                                                      generates a Translation fault. No translation table walk is
30418                                                                      performed. */
30419         uint64_t a1                    : 1;  /**< [ 22: 22](R/W) Selects whether AP_TTBR0_EL2 or AP_TTBR1_EL2 defines the ASID. The
30420                                                                      encoding of this bit is:
30421                                                                  0 =  AP_TTBR0_EL2[ASID] defines the ASID.
30422                                                                  1 =  AP_TTBR1_EL2[ASID] defines the ASID. */
30423         uint64_t t1sz                  : 6;  /**< [ 21: 16](R/W) The size offset of the memory region addressed by AP_TTBR1_EL2.
30424                                                                      The region size is 22^(64-T1SZ) bytes.
30425                                                                  The maximum and minimum possible values for T1SZ depend on the
30426                                                                      level of translation table and the memory translation granule
30427                                                                      size, as described in the AArch64 Virtual Memory System
30428                                                                      Architecture chapter. */
30429         uint64_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
30430                                                                      address register.
30431 
30432                                                                  If the value is programmed to either a reserved value, or a
30433                                                                      size that has not been implemented, then the hardware will
30434                                                                      treat the field as if it has been programmed to an
30435                                                                      implementation defined choice of the sizes that has been
30436                                                                      implemented for all purposes other than the value read back
30437                                                                      from this register.
30438 
30439                                                                  It is implementation defined whether the value read back is
30440                                                                      the value programmed or the value that corresponds to the size
30441                                                                      chosen.
30442 
30443                                                                  0x0 = 4KB.
30444                                                                  0x1 = 64KB.
30445                                                                  0x2 = 16KB. */
30446         uint64_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
30447                                                                      table walks using AP_TTBR0_EL2.
30448 
30449                                                                  0x0 = Non-shareable.
30450                                                                  0x2 = Outer Shareable.
30451                                                                  0x3 = Inner Shareable. */
30452         uint64_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
30453                                                                      translation table walks using AP_TTBR0_EL2.
30454                                                                  0x0 = Normal memory, Outer Non-cacheable.
30455                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30456                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30457                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30458         uint64_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
30459                                                                      translation table walks using AP_TTBR0_EL2.
30460                                                                  0x0 = Normal memory, Inner Non-cacheable.
30461                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30462                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30463                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30464         uint64_t epd0                  : 1;  /**< [  7:  7](R/W) Translation table walk disable for translations using TTBR0.
30465                                                                      This bit controls whether a translation table walk is
30466                                                                      performed on a TLB miss, for an address that is translated
30467                                                                      using TTBR0. The encoding of this bit is:
30468                                                                  0 = Perform translation table walks using TTBR0.
30469                                                                  1 = A TLB miss on an address that is translated using TTBR0
30470                                                                      generates a Translation fault. No translation table walk is
30471                                                                      performed. */
30472         uint64_t reserved_6            : 1;
30473         uint64_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL2.
30474                                                                      The region size is 22^(64-T0SZ) bytes.
30475                                                                  The maximum and minimum possible values for T0SZ depend on the
30476                                                                      level of translation table and the memory translation granule
30477                                                                      size, as described in the AArch64 Virtual Memory System
30478                                                                      Architecture chapter. */
30479 #else /* Word 0 - Little Endian */
30480         uint64_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL2.
30481                                                                      The region size is 22^(64-T0SZ) bytes.
30482                                                                  The maximum and minimum possible values for T0SZ depend on the
30483                                                                      level of translation table and the memory translation granule
30484                                                                      size, as described in the AArch64 Virtual Memory System
30485                                                                      Architecture chapter. */
30486         uint64_t reserved_6            : 1;
30487         uint64_t epd0                  : 1;  /**< [  7:  7](R/W) Translation table walk disable for translations using TTBR0.
30488                                                                      This bit controls whether a translation table walk is
30489                                                                      performed on a TLB miss, for an address that is translated
30490                                                                      using TTBR0. The encoding of this bit is:
30491                                                                  0 = Perform translation table walks using TTBR0.
30492                                                                  1 = A TLB miss on an address that is translated using TTBR0
30493                                                                      generates a Translation fault. No translation table walk is
30494                                                                      performed. */
30495         uint64_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
30496                                                                      translation table walks using AP_TTBR0_EL2.
30497                                                                  0x0 = Normal memory, Inner Non-cacheable.
30498                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30499                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30500                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30501         uint64_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
30502                                                                      translation table walks using AP_TTBR0_EL2.
30503                                                                  0x0 = Normal memory, Outer Non-cacheable.
30504                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30505                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30506                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30507         uint64_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
30508                                                                      table walks using AP_TTBR0_EL2.
30509 
30510                                                                  0x0 = Non-shareable.
30511                                                                  0x2 = Outer Shareable.
30512                                                                  0x3 = Inner Shareable. */
30513         uint64_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
30514                                                                      address register.
30515 
30516                                                                  If the value is programmed to either a reserved value, or a
30517                                                                      size that has not been implemented, then the hardware will
30518                                                                      treat the field as if it has been programmed to an
30519                                                                      implementation defined choice of the sizes that has been
30520                                                                      implemented for all purposes other than the value read back
30521                                                                      from this register.
30522 
30523                                                                  It is implementation defined whether the value read back is
30524                                                                      the value programmed or the value that corresponds to the size
30525                                                                      chosen.
30526 
30527                                                                  0x0 = 4KB.
30528                                                                  0x1 = 64KB.
30529                                                                  0x2 = 16KB. */
30530         uint64_t t1sz                  : 6;  /**< [ 21: 16](R/W) The size offset of the memory region addressed by AP_TTBR1_EL2.
30531                                                                      The region size is 22^(64-T1SZ) bytes.
30532                                                                  The maximum and minimum possible values for T1SZ depend on the
30533                                                                      level of translation table and the memory translation granule
30534                                                                      size, as described in the AArch64 Virtual Memory System
30535                                                                      Architecture chapter. */
30536         uint64_t a1                    : 1;  /**< [ 22: 22](R/W) Selects whether AP_TTBR0_EL2 or AP_TTBR1_EL2 defines the ASID. The
30537                                                                      encoding of this bit is:
30538                                                                  0 =  AP_TTBR0_EL2[ASID] defines the ASID.
30539                                                                  1 =  AP_TTBR1_EL2[ASID] defines the ASID. */
30540         uint64_t epd1                  : 1;  /**< [ 23: 23](R/W) Translation table walk disable for translations using
30541                                                                      AP_TTBR1_EL2. This bit controls whether a translation table walk
30542                                                                      is performed on a TLB miss, for an address that is translated
30543                                                                      using AP_TTBR1_EL2. The encoding of this bit is:
30544                                                                  0 = Perform translation table walks using AP_TTBR1_EL2.
30545                                                                  1 = A TLB miss on an address that is translated using AP_TTBR1_EL2
30546                                                                      generates a Translation fault. No translation table walk is
30547                                                                      performed. */
30548         uint64_t irgn1                 : 2;  /**< [ 25: 24](R/W) Inner cacheability attribute for memory associated with
30549                                                                      translation table walks using AP_TTBR1_EL2.
30550                                                                  0x0 = Normal memory, Inner Non-cacheable.
30551                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30552                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30553                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30554         uint64_t orgn1                 : 2;  /**< [ 27: 26](R/W) Outer cacheability attribute for memory associated with
30555                                                                      translation table walks using AP_TTBR1_EL2.
30556                                                                  0x0 = Normal memory, Outer Non-cacheable.
30557                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30558                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30559                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30560         uint64_t sh1                   : 2;  /**< [ 29: 28](R/W) Shareability attribute for memory associated with translation
30561                                                                      table walks using AP_TTBR1_EL2.
30562 
30563                                                                  0x0 = Non-shareable.
30564                                                                  0x2 = Outer Shareable.
30565                                                                  0x3 = Inner Shareable. */
30566         uint64_t tg1                   : 2;  /**< [ 31: 30](R/W) AP_TTBR1_EL2 Granule size.
30567 
30568                                                                  If the value is programmed to either a reserved value, or a
30569                                                                      size that has not been implemented, then the hardware will
30570                                                                      treat the field as if it has been programmed to an
30571                                                                      implementation defined choice of the sizes that has been
30572                                                                      implemented for all purposes other than the value read back
30573                                                                      from this register.
30574 
30575                                                                  It is implementation defined whether the value read back is
30576                                                                      the value programmed or the value that corresponds to the size
30577                                                                      chosen.
30578 
30579                                                                  0x1 = 16KB.
30580                                                                  0x2 = 4KB.
30581                                                                  0x3 = 64KB. */
30582         uint64_t ips                   : 3;  /**< [ 34: 32](R/W) Intermediate Physical Address Size.
30583                                                                  0x0 = 32 bits, 4GB.
30584                                                                  0x1 = 36 bits, 64GB.
30585                                                                  0x2 = 40 bits, 1TB.
30586                                                                  0x3 = 42 bits, 4TB.
30587                                                                  0x4 = 44 bits, 16TB.
30588                                                                  0x5 = 48 bits, 256TB. */
30589         uint64_t reserved_35           : 1;
30590         uint64_t as                    : 1;  /**< [ 36: 36](R/W) ASID Size.
30591                                                                  If the implementation has only 8 bits of ASID, this field is
30592                                                                      RES0.
30593                                                                  0 = 8 bit - the upper 8 bits of AP_TTBR0_EL2 and AP_TTBR1_EL2 are
30594                                                                      ignored by hardware for every purpose except reading back the
30595                                                                      register, and are treated as if they are all zeros for when
30596                                                                      used for allocation and matching entries in the TLB.
30597                                                                  1 = 16 bit - the upper 16 bits of AP_TTBR0_EL2 and AP_TTBR1_EL2 are used
30598                                                                      for allocation and matching in the TLB. */
30599         uint64_t tbi0                  : 1;  /**< [ 37: 37](R/W) Top Byte ignored - indicates whether the top byte of an
30600                                                                      address is used for address match for the AP_TTBR0_EL2 region, or
30601                                                                      ignored and used for tagged addresses.
30602 
30603                                                                  This affects addresses generated in EL2 using AArch64
30604                                                                      where the address would be translated by tables pointed to by
30605                                                                      AP_TTBR0_EL2. It has an effect whether the EL2 translation
30606                                                                      regime is enabled or not.
30607 
30608                                                                  Additionally, this affects changes to the program counter,
30609                                                                      when TBI0 is 1 and bit [55] of the target address is 0, caused
30610                                                                      by:
30611                                                                  * A branch or procedure return within EL2.
30612                                                                  * An exception taken to EL2.
30613                                                                  * An exception return to EL2.
30614 
30615                                                                  In these cases bits [63:56] of the address are also set to 0
30616                                                                      before it is stored in the PC.
30617                                                                  0 = Top Byte used in the address calculation.
30618                                                                  1 = Top Byte ignored in the address calculation. */
30619         uint64_t tbi1                  : 1;  /**< [ 38: 38](R/W) Top Byte ignored - indicates whether the top byte of an
30620                                                                      address is used for address match for the AP_TTBR1_EL2 region, or
30621                                                                      ignored and used for tagged addresses.
30622 
30623                                                                  This affects addresses generated in EL2 using AArch64
30624                                                                      where the address would be translated by tables pointed to by
30625                                                                      AP_TTBR1_EL2. It has an effect whether the EL2 translation
30626                                                                      regime is enabled or not.
30627 
30628                                                                  Additionally, this affects changes to the program counter,
30629                                                                      when TBI1 is 1 and bit [55] of the target address is 1, caused
30630                                                                      by:
30631                                                                  * A branch or procedure return within EL2.
30632                                                                  * An exception taken to EL2.
30633                                                                  * An exception return to EL2.
30634 
30635                                                                  In these cases bits [63:56] of the address are also set to 1
30636                                                                      before it is stored in the PC.
30637                                                                  0 = Top Byte used in the address calculation.
30638                                                                  1 = Top Byte ignored in the address calculation. */
30639         uint64_t reserved_39           : 1;
30640         uint64_t reserved_40           : 1;
30641         uint64_t had0                  : 1;  /**< [ 41: 41](R/W) V8.1: Hierarchical Attribute Disable.
30642                                                                  HAD0(bit[41]): Hierarchical Attribute Disable for the TTBR0 region.
30643                                                                  0 = Hierarchical Attributes are enabled.
30644                                                                  1 = Hierarchical Attributes are disabled. */
30645         uint64_t had1                  : 1;  /**< [ 42: 42](R/W) V8.1: Hierarchical Attribute Disable.
30646                                                                  HAD1(bit[42]): Hierarchical Attribute Disable for the TTBR1 region.
30647                                                                  0 = Hierarchical Attributes are enabled.
30648                                                                  1 = Hierarchical Attributes are disabled. */
30649         uint64_t reserved_43_63        : 21;
30650 #endif /* Word 0 - End */
30651     } cn;
30652 };
30653 typedef union bdk_ap_tcr_el2_e2h bdk_ap_tcr_el2_e2h_t;
30654 
30655 #define BDK_AP_TCR_EL2_E2H BDK_AP_TCR_EL2_E2H_FUNC()
30656 static inline uint64_t BDK_AP_TCR_EL2_E2H_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TCR_EL2_E2H_FUNC(void)30657 static inline uint64_t BDK_AP_TCR_EL2_E2H_FUNC(void)
30658 {
30659     return 0x30402000210ll;
30660 }
30661 
30662 #define typedef_BDK_AP_TCR_EL2_E2H bdk_ap_tcr_el2_e2h_t
30663 #define bustype_BDK_AP_TCR_EL2_E2H BDK_CSR_TYPE_SYSREG
30664 #define basename_BDK_AP_TCR_EL2_E2H "AP_TCR_EL2_E2H"
30665 #define busnum_BDK_AP_TCR_EL2_E2H 0
30666 #define arguments_BDK_AP_TCR_EL2_E2H -1,-1,-1,-1
30667 
30668 /**
30669  * Register (SYSREG) ap_tcr_el3
30670  *
30671  * AP Translation Control EL3 Registers
30672  * Controls translation table walks required for the stage 1
30673  *     translation of memory accesses from EL3, and holds
30674  *     cacheability and shareability information for the accesses.
30675  */
30676 union bdk_ap_tcr_el3
30677 {
30678     uint32_t u;
30679     struct bdk_ap_tcr_el3_s
30680     {
30681 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
30682         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
30683         uint32_t reserved_25_30        : 6;
30684         uint32_t had                   : 1;  /**< [ 24: 24](R/W) V8.1: Hierarchical Attribute Disable.
30685                                                                  HAD (bit[24]): Hierarchical Attribute Disable.
30686                                                                  0 = Hierarchical Attributes are enabled.
30687                                                                  1 = Hierarchical Attributes are disabled. */
30688         uint32_t rsvd_23               : 1;  /**< [ 23: 23](RO) Reserved 1. */
30689         uint32_t reserved_21_22        : 2;
30690         uint32_t tbi                   : 1;  /**< [ 20: 20](R/W) Top Byte ignored - indicates whether the top byte of an
30691                                                                      address is used for address match for the AP_TTBR0_EL3 region, or
30692                                                                      ignored and used for tagged addresses.
30693 
30694                                                                  This affects addresses generated in EL3 using AArch64 where
30695                                                                      the address would be translated by tables pointed to by
30696                                                                      AP_TTBR0_EL3. It has an effect whether the EL3 translation regime
30697                                                                      is enabled or not.
30698 
30699                                                                  Additionally, this affects changes to the program counter,
30700                                                                      when TBI is 1, caused by:
30701                                                                  * A branch or procedure return within EL3.
30702                                                                  * A exception taken to EL3.
30703                                                                  * An exception return to EL3.
30704 
30705                                                                  In these cases bits [63:56] of the address are set to 0 before
30706                                                                      it is stored in the PC.
30707                                                                  0 = Top Byte used in the address calculation.
30708                                                                  1 = Top Byte ignored in the address calculation. */
30709         uint32_t reserved_19           : 1;
30710         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
30711 
30712                                                                  The reserved values behave in the same way as the0b101
30713                                                                  0x0 = 32 bits, 4GB.
30714                                                                  0x1 = 36 bits, 64GB.
30715                                                                  0x2 = 40 bits, 1TB.
30716                                                                  0x3 = 42 bits, 4TB.
30717                                                                  0x4 = 44 bits, 16TB.
30718                                                                  0x5 = 48 bits, 256TB. */
30719         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
30720                                                                      address register.
30721 
30722                                                                  If the value is programmed to either a reserved value, or a
30723                                                                      size that has not been implemented, then the hardware will
30724                                                                      treat the field as if it has been programmed to an
30725                                                                      implementation defined choice of the sizes that has been
30726                                                                      implemented for all purposes other than the value read back
30727                                                                      from this register.
30728 
30729                                                                  It is implementation defined whether the value read back is
30730                                                                      the value programmed or the value that corresponds to the size
30731                                                                      chosen.
30732                                                                  0x0 = 4KB.
30733                                                                  0x1 = 64KB.
30734                                                                  0x2 = 16KB. */
30735         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
30736                                                                      table walks using AP_TTBR0_EL3.
30737                                                                  0x0 = Non-shareable.
30738                                                                  0x2 = Outer Shareable.
30739                                                                  0x3 = Inner Shareable. */
30740         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
30741                                                                      translation table walks using AP_TTBR0_EL3.
30742                                                                  0x0 = Normal memory, Outer Non-cacheable.
30743                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30744                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30745                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30746         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
30747                                                                      translation table walks using AP_TTBR0_EL3.
30748                                                                  0x0 = Normal memory, Inner Non-cacheable.
30749                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30750                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30751                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30752         uint32_t reserved_6_7          : 2;
30753         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL3.
30754                                                                      The region size is 22^(64-T0SZ) bytes.
30755                                                                  The maximum and minimum possible values for T0SZ depend on the
30756                                                                      level of translation table and the memory translation granule
30757                                                                      size, as described in the AArch64 Virtual Memory System
30758                                                                      Architecture chapter. */
30759 #else /* Word 0 - Little Endian */
30760         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL3.
30761                                                                      The region size is 22^(64-T0SZ) bytes.
30762                                                                  The maximum and minimum possible values for T0SZ depend on the
30763                                                                      level of translation table and the memory translation granule
30764                                                                      size, as described in the AArch64 Virtual Memory System
30765                                                                      Architecture chapter. */
30766         uint32_t reserved_6_7          : 2;
30767         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
30768                                                                      translation table walks using AP_TTBR0_EL3.
30769                                                                  0x0 = Normal memory, Inner Non-cacheable.
30770                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30771                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30772                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30773         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
30774                                                                      translation table walks using AP_TTBR0_EL3.
30775                                                                  0x0 = Normal memory, Outer Non-cacheable.
30776                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30777                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30778                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30779         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
30780                                                                      table walks using AP_TTBR0_EL3.
30781                                                                  0x0 = Non-shareable.
30782                                                                  0x2 = Outer Shareable.
30783                                                                  0x3 = Inner Shareable. */
30784         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
30785                                                                      address register.
30786 
30787                                                                  If the value is programmed to either a reserved value, or a
30788                                                                      size that has not been implemented, then the hardware will
30789                                                                      treat the field as if it has been programmed to an
30790                                                                      implementation defined choice of the sizes that has been
30791                                                                      implemented for all purposes other than the value read back
30792                                                                      from this register.
30793 
30794                                                                  It is implementation defined whether the value read back is
30795                                                                      the value programmed or the value that corresponds to the size
30796                                                                      chosen.
30797                                                                  0x0 = 4KB.
30798                                                                  0x1 = 64KB.
30799                                                                  0x2 = 16KB. */
30800         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
30801 
30802                                                                  The reserved values behave in the same way as the0b101
30803                                                                  0x0 = 32 bits, 4GB.
30804                                                                  0x1 = 36 bits, 64GB.
30805                                                                  0x2 = 40 bits, 1TB.
30806                                                                  0x3 = 42 bits, 4TB.
30807                                                                  0x4 = 44 bits, 16TB.
30808                                                                  0x5 = 48 bits, 256TB. */
30809         uint32_t reserved_19           : 1;
30810         uint32_t tbi                   : 1;  /**< [ 20: 20](R/W) Top Byte ignored - indicates whether the top byte of an
30811                                                                      address is used for address match for the AP_TTBR0_EL3 region, or
30812                                                                      ignored and used for tagged addresses.
30813 
30814                                                                  This affects addresses generated in EL3 using AArch64 where
30815                                                                      the address would be translated by tables pointed to by
30816                                                                      AP_TTBR0_EL3. It has an effect whether the EL3 translation regime
30817                                                                      is enabled or not.
30818 
30819                                                                  Additionally, this affects changes to the program counter,
30820                                                                      when TBI is 1, caused by:
30821                                                                  * A branch or procedure return within EL3.
30822                                                                  * A exception taken to EL3.
30823                                                                  * An exception return to EL3.
30824 
30825                                                                  In these cases bits [63:56] of the address are set to 0 before
30826                                                                      it is stored in the PC.
30827                                                                  0 = Top Byte used in the address calculation.
30828                                                                  1 = Top Byte ignored in the address calculation. */
30829         uint32_t reserved_21_22        : 2;
30830         uint32_t rsvd_23               : 1;  /**< [ 23: 23](RO) Reserved 1. */
30831         uint32_t had                   : 1;  /**< [ 24: 24](R/W) V8.1: Hierarchical Attribute Disable.
30832                                                                  HAD (bit[24]): Hierarchical Attribute Disable.
30833                                                                  0 = Hierarchical Attributes are enabled.
30834                                                                  1 = Hierarchical Attributes are disabled. */
30835         uint32_t reserved_25_30        : 6;
30836         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
30837 #endif /* Word 0 - End */
30838     } s;
30839     struct bdk_ap_tcr_el3_cn
30840     {
30841 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
30842         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
30843         uint32_t reserved_25_30        : 6;
30844         uint32_t had                   : 1;  /**< [ 24: 24](R/W) V8.1: Hierarchical Attribute Disable.
30845                                                                  HAD (bit[24]): Hierarchical Attribute Disable.
30846                                                                  0 = Hierarchical Attributes are enabled.
30847                                                                  1 = Hierarchical Attributes are disabled. */
30848         uint32_t rsvd_23               : 1;  /**< [ 23: 23](RO) Reserved 1. */
30849         uint32_t reserved_22           : 1;
30850         uint32_t reserved_21           : 1;
30851         uint32_t tbi                   : 1;  /**< [ 20: 20](R/W) Top Byte ignored - indicates whether the top byte of an
30852                                                                      address is used for address match for the AP_TTBR0_EL3 region, or
30853                                                                      ignored and used for tagged addresses.
30854 
30855                                                                  This affects addresses generated in EL3 using AArch64 where
30856                                                                      the address would be translated by tables pointed to by
30857                                                                      AP_TTBR0_EL3. It has an effect whether the EL3 translation regime
30858                                                                      is enabled or not.
30859 
30860                                                                  Additionally, this affects changes to the program counter,
30861                                                                      when TBI is 1, caused by:
30862                                                                  * A branch or procedure return within EL3.
30863                                                                  * A exception taken to EL3.
30864                                                                  * An exception return to EL3.
30865 
30866                                                                  In these cases bits [63:56] of the address are set to 0 before
30867                                                                      it is stored in the PC.
30868                                                                  0 = Top Byte used in the address calculation.
30869                                                                  1 = Top Byte ignored in the address calculation. */
30870         uint32_t reserved_19           : 1;
30871         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
30872 
30873                                                                  The reserved values behave in the same way as the0b101
30874                                                                  0x0 = 32 bits, 4GB.
30875                                                                  0x1 = 36 bits, 64GB.
30876                                                                  0x2 = 40 bits, 1TB.
30877                                                                  0x3 = 42 bits, 4TB.
30878                                                                  0x4 = 44 bits, 16TB.
30879                                                                  0x5 = 48 bits, 256TB. */
30880         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
30881                                                                      address register.
30882 
30883                                                                  If the value is programmed to either a reserved value, or a
30884                                                                      size that has not been implemented, then the hardware will
30885                                                                      treat the field as if it has been programmed to an
30886                                                                      implementation defined choice of the sizes that has been
30887                                                                      implemented for all purposes other than the value read back
30888                                                                      from this register.
30889 
30890                                                                  It is implementation defined whether the value read back is
30891                                                                      the value programmed or the value that corresponds to the size
30892                                                                      chosen.
30893                                                                  0x0 = 4KB.
30894                                                                  0x1 = 64KB.
30895                                                                  0x2 = 16KB. */
30896         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
30897                                                                      table walks using AP_TTBR0_EL3.
30898                                                                  0x0 = Non-shareable.
30899                                                                  0x2 = Outer Shareable.
30900                                                                  0x3 = Inner Shareable. */
30901         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
30902                                                                      translation table walks using AP_TTBR0_EL3.
30903                                                                  0x0 = Normal memory, Outer Non-cacheable.
30904                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30905                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30906                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30907         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
30908                                                                      translation table walks using AP_TTBR0_EL3.
30909                                                                  0x0 = Normal memory, Inner Non-cacheable.
30910                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30911                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30912                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30913         uint32_t reserved_6_7          : 2;
30914         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL3.
30915                                                                      The region size is 22^(64-T0SZ) bytes.
30916                                                                  The maximum and minimum possible values for T0SZ depend on the
30917                                                                      level of translation table and the memory translation granule
30918                                                                      size, as described in the AArch64 Virtual Memory System
30919                                                                      Architecture chapter. */
30920 #else /* Word 0 - Little Endian */
30921         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_TTBR0_EL3.
30922                                                                      The region size is 22^(64-T0SZ) bytes.
30923                                                                  The maximum and minimum possible values for T0SZ depend on the
30924                                                                      level of translation table and the memory translation granule
30925                                                                      size, as described in the AArch64 Virtual Memory System
30926                                                                      Architecture chapter. */
30927         uint32_t reserved_6_7          : 2;
30928         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
30929                                                                      translation table walks using AP_TTBR0_EL3.
30930                                                                  0x0 = Normal memory, Inner Non-cacheable.
30931                                                                  0x1 = Normal memory, Inner Write-Back Write-Allocate Cacheable.
30932                                                                  0x2 = Normal memory, Inner Write-Through Cacheable.
30933                                                                  0x3 = Normal memory, Inner Write-Back no Write-Allocate Cacheable. */
30934         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
30935                                                                      translation table walks using AP_TTBR0_EL3.
30936                                                                  0x0 = Normal memory, Outer Non-cacheable.
30937                                                                  0x1 = Normal memory, Outer Write-Back Write-Allocate Cacheable.
30938                                                                  0x2 = Normal memory, Outer Write-Through Cacheable.
30939                                                                  0x3 = Normal memory, Outer Write-Back no Write-Allocate Cacheable. */
30940         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
30941                                                                      table walks using AP_TTBR0_EL3.
30942                                                                  0x0 = Non-shareable.
30943                                                                  0x2 = Outer Shareable.
30944                                                                  0x3 = Inner Shareable. */
30945         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
30946                                                                      address register.
30947 
30948                                                                  If the value is programmed to either a reserved value, or a
30949                                                                      size that has not been implemented, then the hardware will
30950                                                                      treat the field as if it has been programmed to an
30951                                                                      implementation defined choice of the sizes that has been
30952                                                                      implemented for all purposes other than the value read back
30953                                                                      from this register.
30954 
30955                                                                  It is implementation defined whether the value read back is
30956                                                                      the value programmed or the value that corresponds to the size
30957                                                                      chosen.
30958                                                                  0x0 = 4KB.
30959                                                                  0x1 = 64KB.
30960                                                                  0x2 = 16KB. */
30961         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
30962 
30963                                                                  The reserved values behave in the same way as the0b101
30964                                                                  0x0 = 32 bits, 4GB.
30965                                                                  0x1 = 36 bits, 64GB.
30966                                                                  0x2 = 40 bits, 1TB.
30967                                                                  0x3 = 42 bits, 4TB.
30968                                                                  0x4 = 44 bits, 16TB.
30969                                                                  0x5 = 48 bits, 256TB. */
30970         uint32_t reserved_19           : 1;
30971         uint32_t tbi                   : 1;  /**< [ 20: 20](R/W) Top Byte ignored - indicates whether the top byte of an
30972                                                                      address is used for address match for the AP_TTBR0_EL3 region, or
30973                                                                      ignored and used for tagged addresses.
30974 
30975                                                                  This affects addresses generated in EL3 using AArch64 where
30976                                                                      the address would be translated by tables pointed to by
30977                                                                      AP_TTBR0_EL3. It has an effect whether the EL3 translation regime
30978                                                                      is enabled or not.
30979 
30980                                                                  Additionally, this affects changes to the program counter,
30981                                                                      when TBI is 1, caused by:
30982                                                                  * A branch or procedure return within EL3.
30983                                                                  * A exception taken to EL3.
30984                                                                  * An exception return to EL3.
30985 
30986                                                                  In these cases bits [63:56] of the address are set to 0 before
30987                                                                      it is stored in the PC.
30988                                                                  0 = Top Byte used in the address calculation.
30989                                                                  1 = Top Byte ignored in the address calculation. */
30990         uint32_t reserved_21           : 1;
30991         uint32_t reserved_22           : 1;
30992         uint32_t rsvd_23               : 1;  /**< [ 23: 23](RO) Reserved 1. */
30993         uint32_t had                   : 1;  /**< [ 24: 24](R/W) V8.1: Hierarchical Attribute Disable.
30994                                                                  HAD (bit[24]): Hierarchical Attribute Disable.
30995                                                                  0 = Hierarchical Attributes are enabled.
30996                                                                  1 = Hierarchical Attributes are disabled. */
30997         uint32_t reserved_25_30        : 6;
30998         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
30999 #endif /* Word 0 - End */
31000     } cn;
31001 };
31002 typedef union bdk_ap_tcr_el3 bdk_ap_tcr_el3_t;
31003 
31004 #define BDK_AP_TCR_EL3 BDK_AP_TCR_EL3_FUNC()
31005 static inline uint64_t BDK_AP_TCR_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TCR_EL3_FUNC(void)31006 static inline uint64_t BDK_AP_TCR_EL3_FUNC(void)
31007 {
31008     return 0x30602000200ll;
31009 }
31010 
31011 #define typedef_BDK_AP_TCR_EL3 bdk_ap_tcr_el3_t
31012 #define bustype_BDK_AP_TCR_EL3 BDK_CSR_TYPE_SYSREG
31013 #define basename_BDK_AP_TCR_EL3 "AP_TCR_EL3"
31014 #define busnum_BDK_AP_TCR_EL3 0
31015 #define arguments_BDK_AP_TCR_EL3 -1,-1,-1,-1
31016 
31017 /**
31018  * Register (SYSREG) ap_teecr32_el1
31019  *
31020  * AP T32EE Configuration Register
31021  * Allows access to the AArch32 register TEECR from AArch64 state
31022  *     only. Its value has no effect on execution in AArch64 state.
31023  */
31024 union bdk_ap_teecr32_el1
31025 {
31026     uint32_t u;
31027     struct bdk_ap_teecr32_el1_s
31028     {
31029 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31030         uint32_t reserved_1_31         : 31;
31031         uint32_t xed                   : 1;  /**< [  0:  0](R/W) Execution Environment Disable bit. Control unprivileged access
31032                                                                      to TEEHBR.
31033 
31034                                                                  The effects of a write to this register on T32EE configuration
31035                                                                      are only guaranteed to be visible to subsequent instructions
31036                                                                      after the execution of a context synchronization operation.
31037                                                                      However, a read of this register always returns the value most
31038                                                                      recently written to the register.
31039                                                                  0 = Unprivileged access permitted.
31040                                                                  1 = Unprivileged access disabled. */
31041 #else /* Word 0 - Little Endian */
31042         uint32_t xed                   : 1;  /**< [  0:  0](R/W) Execution Environment Disable bit. Control unprivileged access
31043                                                                      to TEEHBR.
31044 
31045                                                                  The effects of a write to this register on T32EE configuration
31046                                                                      are only guaranteed to be visible to subsequent instructions
31047                                                                      after the execution of a context synchronization operation.
31048                                                                      However, a read of this register always returns the value most
31049                                                                      recently written to the register.
31050                                                                  0 = Unprivileged access permitted.
31051                                                                  1 = Unprivileged access disabled. */
31052         uint32_t reserved_1_31         : 31;
31053 #endif /* Word 0 - End */
31054     } s;
31055     /* struct bdk_ap_teecr32_el1_s cn8; */
31056     struct bdk_ap_teecr32_el1_cn9
31057     {
31058 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31059         uint32_t reserved_1_31         : 31;
31060         uint32_t xed                   : 1;  /**< [  0:  0](RAZ) Execution Environment Disable bit. Control unprivileged access
31061                                                                      to TEEHBR.
31062 
31063                                                                  The effects of a write to this register on T32EE configuration
31064                                                                      are only guaranteed to be visible to subsequent instructions
31065                                                                      after the execution of a context synchronization operation.
31066                                                                      However, a read of this register always returns the value most
31067                                                                      recently written to the register.
31068                                                                  0 = Unprivileged access permitted.
31069                                                                  1 = Unprivileged access disabled. */
31070 #else /* Word 0 - Little Endian */
31071         uint32_t xed                   : 1;  /**< [  0:  0](RAZ) Execution Environment Disable bit. Control unprivileged access
31072                                                                      to TEEHBR.
31073 
31074                                                                  The effects of a write to this register on T32EE configuration
31075                                                                      are only guaranteed to be visible to subsequent instructions
31076                                                                      after the execution of a context synchronization operation.
31077                                                                      However, a read of this register always returns the value most
31078                                                                      recently written to the register.
31079                                                                  0 = Unprivileged access permitted.
31080                                                                  1 = Unprivileged access disabled. */
31081         uint32_t reserved_1_31         : 31;
31082 #endif /* Word 0 - End */
31083     } cn9;
31084 };
31085 typedef union bdk_ap_teecr32_el1 bdk_ap_teecr32_el1_t;
31086 
31087 #define BDK_AP_TEECR32_EL1 BDK_AP_TEECR32_EL1_FUNC()
31088 static inline uint64_t BDK_AP_TEECR32_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TEECR32_EL1_FUNC(void)31089 static inline uint64_t BDK_AP_TEECR32_EL1_FUNC(void)
31090 {
31091     return 0x20200000000ll;
31092 }
31093 
31094 #define typedef_BDK_AP_TEECR32_EL1 bdk_ap_teecr32_el1_t
31095 #define bustype_BDK_AP_TEECR32_EL1 BDK_CSR_TYPE_SYSREG
31096 #define basename_BDK_AP_TEECR32_EL1 "AP_TEECR32_EL1"
31097 #define busnum_BDK_AP_TEECR32_EL1 0
31098 #define arguments_BDK_AP_TEECR32_EL1 -1,-1,-1,-1
31099 
31100 /**
31101  * Register (SYSREG) ap_teehbr32_el1
31102  *
31103  * AP T32EE Handler Base Register
31104  * Allows access to the AArch32 register TEEHBR from AArch64
31105  *     state only. Its value has no effect on execution in AArch64
31106  *     state.
31107  */
31108 union bdk_ap_teehbr32_el1
31109 {
31110     uint32_t u;
31111     struct bdk_ap_teehbr32_el1_s
31112     {
31113 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31114         uint32_t handlerbase           : 30; /**< [ 31:  2](R/W) The address of the T32EE Handler_00 implementation. This is
31115                                                                      the address of the first of the T32EE handlers. */
31116         uint32_t reserved_0_1          : 2;
31117 #else /* Word 0 - Little Endian */
31118         uint32_t reserved_0_1          : 2;
31119         uint32_t handlerbase           : 30; /**< [ 31:  2](R/W) The address of the T32EE Handler_00 implementation. This is
31120                                                                      the address of the first of the T32EE handlers. */
31121 #endif /* Word 0 - End */
31122     } s;
31123     /* struct bdk_ap_teehbr32_el1_s cn8; */
31124     struct bdk_ap_teehbr32_el1_cn9
31125     {
31126 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31127         uint32_t handlerbase           : 30; /**< [ 31:  2](RAZ) The address of the T32EE Handler_00 implementation. This is
31128                                                                      the address of the first of the T32EE handlers. */
31129         uint32_t reserved_0_1          : 2;
31130 #else /* Word 0 - Little Endian */
31131         uint32_t reserved_0_1          : 2;
31132         uint32_t handlerbase           : 30; /**< [ 31:  2](RAZ) The address of the T32EE Handler_00 implementation. This is
31133                                                                      the address of the first of the T32EE handlers. */
31134 #endif /* Word 0 - End */
31135     } cn9;
31136 };
31137 typedef union bdk_ap_teehbr32_el1 bdk_ap_teehbr32_el1_t;
31138 
31139 #define BDK_AP_TEEHBR32_EL1 BDK_AP_TEEHBR32_EL1_FUNC()
31140 static inline uint64_t BDK_AP_TEEHBR32_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TEEHBR32_EL1_FUNC(void)31141 static inline uint64_t BDK_AP_TEEHBR32_EL1_FUNC(void)
31142 {
31143     return 0x20201000000ll;
31144 }
31145 
31146 #define typedef_BDK_AP_TEEHBR32_EL1 bdk_ap_teehbr32_el1_t
31147 #define bustype_BDK_AP_TEEHBR32_EL1 BDK_CSR_TYPE_SYSREG
31148 #define basename_BDK_AP_TEEHBR32_EL1 "AP_TEEHBR32_EL1"
31149 #define busnum_BDK_AP_TEEHBR32_EL1 0
31150 #define arguments_BDK_AP_TEEHBR32_EL1 -1,-1,-1,-1
31151 
31152 /**
31153  * Register (SYSREG) ap_tpidr_el#
31154  *
31155  * AP Thread Pointer / ID Register
31156  * Provides a location where software executing at EL3 can store
31157  *     thread identifying information, for OS management purposes.
31158  */
31159 union bdk_ap_tpidr_elx
31160 {
31161     uint64_t u;
31162     struct bdk_ap_tpidr_elx_s
31163     {
31164 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31165         uint64_t data                  : 64; /**< [ 63:  0](R/W) Thread ID. Thread identifying information stored by software
31166                                                                      running at this Exception level. */
31167 #else /* Word 0 - Little Endian */
31168         uint64_t data                  : 64; /**< [ 63:  0](R/W) Thread ID. Thread identifying information stored by software
31169                                                                      running at this Exception level. */
31170 #endif /* Word 0 - End */
31171     } s;
31172     /* struct bdk_ap_tpidr_elx_s cn; */
31173 };
31174 typedef union bdk_ap_tpidr_elx bdk_ap_tpidr_elx_t;
31175 
31176 static inline uint64_t BDK_AP_TPIDR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TPIDR_ELX(unsigned long a)31177 static inline uint64_t BDK_AP_TPIDR_ELX(unsigned long a)
31178 {
31179     if ((a>=2)&&(a<=3))
31180         return 0x3000d000200ll + 0x200000000ll * ((a) & 0x3);
31181     __bdk_csr_fatal("AP_TPIDR_ELX", 1, a, 0, 0, 0);
31182 }
31183 
31184 #define typedef_BDK_AP_TPIDR_ELX(a) bdk_ap_tpidr_elx_t
31185 #define bustype_BDK_AP_TPIDR_ELX(a) BDK_CSR_TYPE_SYSREG
31186 #define basename_BDK_AP_TPIDR_ELX(a) "AP_TPIDR_ELX"
31187 #define busnum_BDK_AP_TPIDR_ELX(a) (a)
31188 #define arguments_BDK_AP_TPIDR_ELX(a) (a),-1,-1,-1
31189 
31190 /**
31191  * Register (SYSREG) ap_tpidr_el0
31192  *
31193  * AP EL0 Read/Write Software Thread ID Register
31194  * Provides a location where software executing at EL0 can store
31195  *     thread identifying information, for OS management purposes.
31196  */
31197 union bdk_ap_tpidr_el0
31198 {
31199     uint64_t u;
31200     struct bdk_ap_tpidr_el0_s
31201     {
31202 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31203         uint64_t data                  : 64; /**< [ 63:  0](R/W) Thread ID. Thread identifying information stored by software
31204                                                                      running at this Exception level. */
31205 #else /* Word 0 - Little Endian */
31206         uint64_t data                  : 64; /**< [ 63:  0](R/W) Thread ID. Thread identifying information stored by software
31207                                                                      running at this Exception level. */
31208 #endif /* Word 0 - End */
31209     } s;
31210     /* struct bdk_ap_tpidr_el0_s cn; */
31211 };
31212 typedef union bdk_ap_tpidr_el0 bdk_ap_tpidr_el0_t;
31213 
31214 #define BDK_AP_TPIDR_EL0 BDK_AP_TPIDR_EL0_FUNC()
31215 static inline uint64_t BDK_AP_TPIDR_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TPIDR_EL0_FUNC(void)31216 static inline uint64_t BDK_AP_TPIDR_EL0_FUNC(void)
31217 {
31218     return 0x3030d000200ll;
31219 }
31220 
31221 #define typedef_BDK_AP_TPIDR_EL0 bdk_ap_tpidr_el0_t
31222 #define bustype_BDK_AP_TPIDR_EL0 BDK_CSR_TYPE_SYSREG
31223 #define basename_BDK_AP_TPIDR_EL0 "AP_TPIDR_EL0"
31224 #define busnum_BDK_AP_TPIDR_EL0 0
31225 #define arguments_BDK_AP_TPIDR_EL0 -1,-1,-1,-1
31226 
31227 /**
31228  * Register (SYSREG) ap_tpidr_el1
31229  *
31230  * AP EL1 Software Thread ID Register
31231  * Provides a location where software executing at EL1 can store
31232  *     thread identifying information, for OS management purposes.
31233  */
31234 union bdk_ap_tpidr_el1
31235 {
31236     uint64_t u;
31237     struct bdk_ap_tpidr_el1_s
31238     {
31239 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31240         uint64_t data                  : 64; /**< [ 63:  0](R/W) Thread ID. Thread identifying information stored by software
31241                                                                      running at this Exception level. */
31242 #else /* Word 0 - Little Endian */
31243         uint64_t data                  : 64; /**< [ 63:  0](R/W) Thread ID. Thread identifying information stored by software
31244                                                                      running at this Exception level. */
31245 #endif /* Word 0 - End */
31246     } s;
31247     /* struct bdk_ap_tpidr_el1_s cn; */
31248 };
31249 typedef union bdk_ap_tpidr_el1 bdk_ap_tpidr_el1_t;
31250 
31251 #define BDK_AP_TPIDR_EL1 BDK_AP_TPIDR_EL1_FUNC()
31252 static inline uint64_t BDK_AP_TPIDR_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TPIDR_EL1_FUNC(void)31253 static inline uint64_t BDK_AP_TPIDR_EL1_FUNC(void)
31254 {
31255     return 0x3000d000400ll;
31256 }
31257 
31258 #define typedef_BDK_AP_TPIDR_EL1 bdk_ap_tpidr_el1_t
31259 #define bustype_BDK_AP_TPIDR_EL1 BDK_CSR_TYPE_SYSREG
31260 #define basename_BDK_AP_TPIDR_EL1 "AP_TPIDR_EL1"
31261 #define busnum_BDK_AP_TPIDR_EL1 0
31262 #define arguments_BDK_AP_TPIDR_EL1 -1,-1,-1,-1
31263 
31264 /**
31265  * Register (SYSREG) ap_tpidrro_el0
31266  *
31267  * AP Thread Pointer / ID Read-Only EL0 Register
31268  * Provides a location where software executing at EL1 or higher
31269  *     can store thread identifying information that is visible to
31270  *     software executing at EL0, for OS management purposes.
31271  */
31272 union bdk_ap_tpidrro_el0
31273 {
31274     uint64_t u;
31275     struct bdk_ap_tpidrro_el0_s
31276     {
31277 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31278         uint64_t data                  : 64; /**< [ 63:  0](R/W) Thread ID. Thread identifying information stored by software
31279                                                                      running at this Exception level. */
31280 #else /* Word 0 - Little Endian */
31281         uint64_t data                  : 64; /**< [ 63:  0](R/W) Thread ID. Thread identifying information stored by software
31282                                                                      running at this Exception level. */
31283 #endif /* Word 0 - End */
31284     } s;
31285     /* struct bdk_ap_tpidrro_el0_s cn; */
31286 };
31287 typedef union bdk_ap_tpidrro_el0 bdk_ap_tpidrro_el0_t;
31288 
31289 #define BDK_AP_TPIDRRO_EL0 BDK_AP_TPIDRRO_EL0_FUNC()
31290 static inline uint64_t BDK_AP_TPIDRRO_EL0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TPIDRRO_EL0_FUNC(void)31291 static inline uint64_t BDK_AP_TPIDRRO_EL0_FUNC(void)
31292 {
31293     return 0x3030d000300ll;
31294 }
31295 
31296 #define typedef_BDK_AP_TPIDRRO_EL0 bdk_ap_tpidrro_el0_t
31297 #define bustype_BDK_AP_TPIDRRO_EL0 BDK_CSR_TYPE_SYSREG
31298 #define basename_BDK_AP_TPIDRRO_EL0 "AP_TPIDRRO_EL0"
31299 #define busnum_BDK_AP_TPIDRRO_EL0 0
31300 #define arguments_BDK_AP_TPIDRRO_EL0 -1,-1,-1,-1
31301 
31302 /**
31303  * Register (SYSREG) ap_trcacatr#
31304  *
31305  * AP Register
31306  */
31307 union bdk_ap_trcacatrx
31308 {
31309     uint64_t u;
31310     struct bdk_ap_trcacatrx_s
31311     {
31312 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31313         uint64_t reserved_0_63         : 64;
31314 #else /* Word 0 - Little Endian */
31315         uint64_t reserved_0_63         : 64;
31316 #endif /* Word 0 - End */
31317     } s;
31318     /* struct bdk_ap_trcacatrx_s cn; */
31319 };
31320 typedef union bdk_ap_trcacatrx bdk_ap_trcacatrx_t;
31321 
31322 static inline uint64_t BDK_AP_TRCACATRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCACATRX(unsigned long a)31323 static inline uint64_t BDK_AP_TRCACATRX(unsigned long a)
31324 {
31325     if (a<=15)
31326         return 0x20102000200ll + 0x20000ll * ((a) & 0xf);
31327     __bdk_csr_fatal("AP_TRCACATRX", 1, a, 0, 0, 0);
31328 }
31329 
31330 #define typedef_BDK_AP_TRCACATRX(a) bdk_ap_trcacatrx_t
31331 #define bustype_BDK_AP_TRCACATRX(a) BDK_CSR_TYPE_SYSREG
31332 #define basename_BDK_AP_TRCACATRX(a) "AP_TRCACATRX"
31333 #define busnum_BDK_AP_TRCACATRX(a) (a)
31334 #define arguments_BDK_AP_TRCACATRX(a) (a),-1,-1,-1
31335 
31336 /**
31337  * Register (SYSREG) ap_trcacvr#
31338  *
31339  * AP Register
31340  */
31341 union bdk_ap_trcacvrx
31342 {
31343     uint64_t u;
31344     struct bdk_ap_trcacvrx_s
31345     {
31346 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31347         uint64_t reserved_0_63         : 64;
31348 #else /* Word 0 - Little Endian */
31349         uint64_t reserved_0_63         : 64;
31350 #endif /* Word 0 - End */
31351     } s;
31352     /* struct bdk_ap_trcacvrx_s cn; */
31353 };
31354 typedef union bdk_ap_trcacvrx bdk_ap_trcacvrx_t;
31355 
31356 static inline uint64_t BDK_AP_TRCACVRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCACVRX(unsigned long a)31357 static inline uint64_t BDK_AP_TRCACVRX(unsigned long a)
31358 {
31359     if (a<=15)
31360         return 0x20102000000ll + 0x20000ll * ((a) & 0xf);
31361     __bdk_csr_fatal("AP_TRCACVRX", 1, a, 0, 0, 0);
31362 }
31363 
31364 #define typedef_BDK_AP_TRCACVRX(a) bdk_ap_trcacvrx_t
31365 #define bustype_BDK_AP_TRCACVRX(a) BDK_CSR_TYPE_SYSREG
31366 #define basename_BDK_AP_TRCACVRX(a) "AP_TRCACVRX"
31367 #define busnum_BDK_AP_TRCACVRX(a) (a)
31368 #define arguments_BDK_AP_TRCACVRX(a) (a),-1,-1,-1
31369 
31370 /**
31371  * Register (SYSREG) ap_trcauthstatus
31372  *
31373  * AP Register
31374  */
31375 union bdk_ap_trcauthstatus
31376 {
31377     uint64_t u;
31378     struct bdk_ap_trcauthstatus_s
31379     {
31380 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31381         uint64_t reserved_0_63         : 64;
31382 #else /* Word 0 - Little Endian */
31383         uint64_t reserved_0_63         : 64;
31384 #endif /* Word 0 - End */
31385     } s;
31386     /* struct bdk_ap_trcauthstatus_s cn; */
31387 };
31388 typedef union bdk_ap_trcauthstatus bdk_ap_trcauthstatus_t;
31389 
31390 #define BDK_AP_TRCAUTHSTATUS BDK_AP_TRCAUTHSTATUS_FUNC()
31391 static inline uint64_t BDK_AP_TRCAUTHSTATUS_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCAUTHSTATUS_FUNC(void)31392 static inline uint64_t BDK_AP_TRCAUTHSTATUS_FUNC(void)
31393 {
31394     return 0x201070e0600ll;
31395 }
31396 
31397 #define typedef_BDK_AP_TRCAUTHSTATUS bdk_ap_trcauthstatus_t
31398 #define bustype_BDK_AP_TRCAUTHSTATUS BDK_CSR_TYPE_SYSREG
31399 #define basename_BDK_AP_TRCAUTHSTATUS "AP_TRCAUTHSTATUS"
31400 #define busnum_BDK_AP_TRCAUTHSTATUS 0
31401 #define arguments_BDK_AP_TRCAUTHSTATUS -1,-1,-1,-1
31402 
31403 /**
31404  * Register (SYSREG) ap_trcauxctlr
31405  *
31406  * AP Register
31407  */
31408 union bdk_ap_trcauxctlr
31409 {
31410     uint64_t u;
31411     struct bdk_ap_trcauxctlr_s
31412     {
31413 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31414         uint64_t reserved_0_63         : 64;
31415 #else /* Word 0 - Little Endian */
31416         uint64_t reserved_0_63         : 64;
31417 #endif /* Word 0 - End */
31418     } s;
31419     /* struct bdk_ap_trcauxctlr_s cn; */
31420 };
31421 typedef union bdk_ap_trcauxctlr bdk_ap_trcauxctlr_t;
31422 
31423 #define BDK_AP_TRCAUXCTLR BDK_AP_TRCAUXCTLR_FUNC()
31424 static inline uint64_t BDK_AP_TRCAUXCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCAUXCTLR_FUNC(void)31425 static inline uint64_t BDK_AP_TRCAUXCTLR_FUNC(void)
31426 {
31427     return 0x20100060000ll;
31428 }
31429 
31430 #define typedef_BDK_AP_TRCAUXCTLR bdk_ap_trcauxctlr_t
31431 #define bustype_BDK_AP_TRCAUXCTLR BDK_CSR_TYPE_SYSREG
31432 #define basename_BDK_AP_TRCAUXCTLR "AP_TRCAUXCTLR"
31433 #define busnum_BDK_AP_TRCAUXCTLR 0
31434 #define arguments_BDK_AP_TRCAUXCTLR -1,-1,-1,-1
31435 
31436 /**
31437  * Register (SYSREG) ap_trcbbctlr
31438  *
31439  * AP Register
31440  */
31441 union bdk_ap_trcbbctlr
31442 {
31443     uint64_t u;
31444     struct bdk_ap_trcbbctlr_s
31445     {
31446 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31447         uint64_t reserved_0_63         : 64;
31448 #else /* Word 0 - Little Endian */
31449         uint64_t reserved_0_63         : 64;
31450 #endif /* Word 0 - End */
31451     } s;
31452     /* struct bdk_ap_trcbbctlr_s cn; */
31453 };
31454 typedef union bdk_ap_trcbbctlr bdk_ap_trcbbctlr_t;
31455 
31456 #define BDK_AP_TRCBBCTLR BDK_AP_TRCBBCTLR_FUNC()
31457 static inline uint64_t BDK_AP_TRCBBCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCBBCTLR_FUNC(void)31458 static inline uint64_t BDK_AP_TRCBBCTLR_FUNC(void)
31459 {
31460     return 0x201000f0000ll;
31461 }
31462 
31463 #define typedef_BDK_AP_TRCBBCTLR bdk_ap_trcbbctlr_t
31464 #define bustype_BDK_AP_TRCBBCTLR BDK_CSR_TYPE_SYSREG
31465 #define basename_BDK_AP_TRCBBCTLR "AP_TRCBBCTLR"
31466 #define busnum_BDK_AP_TRCBBCTLR 0
31467 #define arguments_BDK_AP_TRCBBCTLR -1,-1,-1,-1
31468 
31469 /**
31470  * Register (SYSREG) ap_trcccctlr
31471  *
31472  * AP Register
31473  */
31474 union bdk_ap_trcccctlr
31475 {
31476     uint64_t u;
31477     struct bdk_ap_trcccctlr_s
31478     {
31479 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31480         uint64_t reserved_0_63         : 64;
31481 #else /* Word 0 - Little Endian */
31482         uint64_t reserved_0_63         : 64;
31483 #endif /* Word 0 - End */
31484     } s;
31485     /* struct bdk_ap_trcccctlr_s cn; */
31486 };
31487 typedef union bdk_ap_trcccctlr bdk_ap_trcccctlr_t;
31488 
31489 #define BDK_AP_TRCCCCTLR BDK_AP_TRCCCCTLR_FUNC()
31490 static inline uint64_t BDK_AP_TRCCCCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCCCCTLR_FUNC(void)31491 static inline uint64_t BDK_AP_TRCCCCTLR_FUNC(void)
31492 {
31493     return 0x201000e0000ll;
31494 }
31495 
31496 #define typedef_BDK_AP_TRCCCCTLR bdk_ap_trcccctlr_t
31497 #define bustype_BDK_AP_TRCCCCTLR BDK_CSR_TYPE_SYSREG
31498 #define basename_BDK_AP_TRCCCCTLR "AP_TRCCCCTLR"
31499 #define busnum_BDK_AP_TRCCCCTLR 0
31500 #define arguments_BDK_AP_TRCCCCTLR -1,-1,-1,-1
31501 
31502 /**
31503  * Register (SYSREG) ap_trccidcctlr#
31504  *
31505  * AP Register
31506  */
31507 union bdk_ap_trccidcctlrx
31508 {
31509     uint64_t u;
31510     struct bdk_ap_trccidcctlrx_s
31511     {
31512 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31513         uint64_t reserved_0_63         : 64;
31514 #else /* Word 0 - Little Endian */
31515         uint64_t reserved_0_63         : 64;
31516 #endif /* Word 0 - End */
31517     } s;
31518     /* struct bdk_ap_trccidcctlrx_s cn; */
31519 };
31520 typedef union bdk_ap_trccidcctlrx bdk_ap_trccidcctlrx_t;
31521 
31522 static inline uint64_t BDK_AP_TRCCIDCCTLRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCCIDCCTLRX(unsigned long a)31523 static inline uint64_t BDK_AP_TRCCIDCCTLRX(unsigned long a)
31524 {
31525     if (a<=1)
31526         return 0x20103000200ll + 0x10000ll * ((a) & 0x1);
31527     __bdk_csr_fatal("AP_TRCCIDCCTLRX", 1, a, 0, 0, 0);
31528 }
31529 
31530 #define typedef_BDK_AP_TRCCIDCCTLRX(a) bdk_ap_trccidcctlrx_t
31531 #define bustype_BDK_AP_TRCCIDCCTLRX(a) BDK_CSR_TYPE_SYSREG
31532 #define basename_BDK_AP_TRCCIDCCTLRX(a) "AP_TRCCIDCCTLRX"
31533 #define busnum_BDK_AP_TRCCIDCCTLRX(a) (a)
31534 #define arguments_BDK_AP_TRCCIDCCTLRX(a) (a),-1,-1,-1
31535 
31536 /**
31537  * Register (SYSREG) ap_trccidcvr#
31538  *
31539  * AP Register
31540  */
31541 union bdk_ap_trccidcvrx
31542 {
31543     uint64_t u;
31544     struct bdk_ap_trccidcvrx_s
31545     {
31546 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31547         uint64_t reserved_0_63         : 64;
31548 #else /* Word 0 - Little Endian */
31549         uint64_t reserved_0_63         : 64;
31550 #endif /* Word 0 - End */
31551     } s;
31552     /* struct bdk_ap_trccidcvrx_s cn; */
31553 };
31554 typedef union bdk_ap_trccidcvrx bdk_ap_trccidcvrx_t;
31555 
31556 static inline uint64_t BDK_AP_TRCCIDCVRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCCIDCVRX(unsigned long a)31557 static inline uint64_t BDK_AP_TRCCIDCVRX(unsigned long a)
31558 {
31559     if (a<=7)
31560         return 0x20103000000ll + 0x20000ll * ((a) & 0x7);
31561     __bdk_csr_fatal("AP_TRCCIDCVRX", 1, a, 0, 0, 0);
31562 }
31563 
31564 #define typedef_BDK_AP_TRCCIDCVRX(a) bdk_ap_trccidcvrx_t
31565 #define bustype_BDK_AP_TRCCIDCVRX(a) BDK_CSR_TYPE_SYSREG
31566 #define basename_BDK_AP_TRCCIDCVRX(a) "AP_TRCCIDCVRX"
31567 #define busnum_BDK_AP_TRCCIDCVRX(a) (a)
31568 #define arguments_BDK_AP_TRCCIDCVRX(a) (a),-1,-1,-1
31569 
31570 /**
31571  * Register (SYSREG) ap_trccidr#
31572  *
31573  * AP Register
31574  */
31575 union bdk_ap_trccidrx
31576 {
31577     uint64_t u;
31578     struct bdk_ap_trccidrx_s
31579     {
31580 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31581         uint64_t reserved_0_63         : 64;
31582 #else /* Word 0 - Little Endian */
31583         uint64_t reserved_0_63         : 64;
31584 #endif /* Word 0 - End */
31585     } s;
31586     /* struct bdk_ap_trccidrx_s cn; */
31587 };
31588 typedef union bdk_ap_trccidrx bdk_ap_trccidrx_t;
31589 
31590 static inline uint64_t BDK_AP_TRCCIDRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCCIDRX(unsigned long a)31591 static inline uint64_t BDK_AP_TRCCIDRX(unsigned long a)
31592 {
31593     if (a<=3)
31594         return 0x201070c0700ll + 0x10000ll * ((a) & 0x3);
31595     __bdk_csr_fatal("AP_TRCCIDRX", 1, a, 0, 0, 0);
31596 }
31597 
31598 #define typedef_BDK_AP_TRCCIDRX(a) bdk_ap_trccidrx_t
31599 #define bustype_BDK_AP_TRCCIDRX(a) BDK_CSR_TYPE_SYSREG
31600 #define basename_BDK_AP_TRCCIDRX(a) "AP_TRCCIDRX"
31601 #define busnum_BDK_AP_TRCCIDRX(a) (a)
31602 #define arguments_BDK_AP_TRCCIDRX(a) (a),-1,-1,-1
31603 
31604 /**
31605  * Register (SYSREG) ap_trcclaimclr
31606  *
31607  * AP Register
31608  */
31609 union bdk_ap_trcclaimclr
31610 {
31611     uint64_t u;
31612     struct bdk_ap_trcclaimclr_s
31613     {
31614 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31615         uint64_t reserved_0_63         : 64;
31616 #else /* Word 0 - Little Endian */
31617         uint64_t reserved_0_63         : 64;
31618 #endif /* Word 0 - End */
31619     } s;
31620     /* struct bdk_ap_trcclaimclr_s cn; */
31621 };
31622 typedef union bdk_ap_trcclaimclr bdk_ap_trcclaimclr_t;
31623 
31624 #define BDK_AP_TRCCLAIMCLR BDK_AP_TRCCLAIMCLR_FUNC()
31625 static inline uint64_t BDK_AP_TRCCLAIMCLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCCLAIMCLR_FUNC(void)31626 static inline uint64_t BDK_AP_TRCCLAIMCLR_FUNC(void)
31627 {
31628     return 0x20107090600ll;
31629 }
31630 
31631 #define typedef_BDK_AP_TRCCLAIMCLR bdk_ap_trcclaimclr_t
31632 #define bustype_BDK_AP_TRCCLAIMCLR BDK_CSR_TYPE_SYSREG
31633 #define basename_BDK_AP_TRCCLAIMCLR "AP_TRCCLAIMCLR"
31634 #define busnum_BDK_AP_TRCCLAIMCLR 0
31635 #define arguments_BDK_AP_TRCCLAIMCLR -1,-1,-1,-1
31636 
31637 /**
31638  * Register (SYSREG) ap_trcclaimset
31639  *
31640  * AP Register
31641  */
31642 union bdk_ap_trcclaimset
31643 {
31644     uint64_t u;
31645     struct bdk_ap_trcclaimset_s
31646     {
31647 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31648         uint64_t reserved_0_63         : 64;
31649 #else /* Word 0 - Little Endian */
31650         uint64_t reserved_0_63         : 64;
31651 #endif /* Word 0 - End */
31652     } s;
31653     /* struct bdk_ap_trcclaimset_s cn; */
31654 };
31655 typedef union bdk_ap_trcclaimset bdk_ap_trcclaimset_t;
31656 
31657 #define BDK_AP_TRCCLAIMSET BDK_AP_TRCCLAIMSET_FUNC()
31658 static inline uint64_t BDK_AP_TRCCLAIMSET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCCLAIMSET_FUNC(void)31659 static inline uint64_t BDK_AP_TRCCLAIMSET_FUNC(void)
31660 {
31661     return 0x20107080600ll;
31662 }
31663 
31664 #define typedef_BDK_AP_TRCCLAIMSET bdk_ap_trcclaimset_t
31665 #define bustype_BDK_AP_TRCCLAIMSET BDK_CSR_TYPE_SYSREG
31666 #define basename_BDK_AP_TRCCLAIMSET "AP_TRCCLAIMSET"
31667 #define busnum_BDK_AP_TRCCLAIMSET 0
31668 #define arguments_BDK_AP_TRCCLAIMSET -1,-1,-1,-1
31669 
31670 /**
31671  * Register (SYSREG) ap_trccntctlr#
31672  *
31673  * AP Register
31674  */
31675 union bdk_ap_trccntctlrx
31676 {
31677     uint64_t u;
31678     struct bdk_ap_trccntctlrx_s
31679     {
31680 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31681         uint64_t reserved_0_63         : 64;
31682 #else /* Word 0 - Little Endian */
31683         uint64_t reserved_0_63         : 64;
31684 #endif /* Word 0 - End */
31685     } s;
31686     /* struct bdk_ap_trccntctlrx_s cn; */
31687 };
31688 typedef union bdk_ap_trccntctlrx bdk_ap_trccntctlrx_t;
31689 
31690 static inline uint64_t BDK_AP_TRCCNTCTLRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCCNTCTLRX(unsigned long a)31691 static inline uint64_t BDK_AP_TRCCNTCTLRX(unsigned long a)
31692 {
31693     if (a<=3)
31694         return 0x20100040500ll + 0x10000ll * ((a) & 0x3);
31695     __bdk_csr_fatal("AP_TRCCNTCTLRX", 1, a, 0, 0, 0);
31696 }
31697 
31698 #define typedef_BDK_AP_TRCCNTCTLRX(a) bdk_ap_trccntctlrx_t
31699 #define bustype_BDK_AP_TRCCNTCTLRX(a) BDK_CSR_TYPE_SYSREG
31700 #define basename_BDK_AP_TRCCNTCTLRX(a) "AP_TRCCNTCTLRX"
31701 #define busnum_BDK_AP_TRCCNTCTLRX(a) (a)
31702 #define arguments_BDK_AP_TRCCNTCTLRX(a) (a),-1,-1,-1
31703 
31704 /**
31705  * Register (SYSREG) ap_trccntrldvr#
31706  *
31707  * AP Register
31708  */
31709 union bdk_ap_trccntrldvrx
31710 {
31711     uint64_t u;
31712     struct bdk_ap_trccntrldvrx_s
31713     {
31714 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31715         uint64_t reserved_0_63         : 64;
31716 #else /* Word 0 - Little Endian */
31717         uint64_t reserved_0_63         : 64;
31718 #endif /* Word 0 - End */
31719     } s;
31720     /* struct bdk_ap_trccntrldvrx_s cn; */
31721 };
31722 typedef union bdk_ap_trccntrldvrx bdk_ap_trccntrldvrx_t;
31723 
31724 static inline uint64_t BDK_AP_TRCCNTRLDVRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCCNTRLDVRX(unsigned long a)31725 static inline uint64_t BDK_AP_TRCCNTRLDVRX(unsigned long a)
31726 {
31727     if (a<=3)
31728         return 0x20100000500ll + 0x10000ll * ((a) & 0x3);
31729     __bdk_csr_fatal("AP_TRCCNTRLDVRX", 1, a, 0, 0, 0);
31730 }
31731 
31732 #define typedef_BDK_AP_TRCCNTRLDVRX(a) bdk_ap_trccntrldvrx_t
31733 #define bustype_BDK_AP_TRCCNTRLDVRX(a) BDK_CSR_TYPE_SYSREG
31734 #define basename_BDK_AP_TRCCNTRLDVRX(a) "AP_TRCCNTRLDVRX"
31735 #define busnum_BDK_AP_TRCCNTRLDVRX(a) (a)
31736 #define arguments_BDK_AP_TRCCNTRLDVRX(a) (a),-1,-1,-1
31737 
31738 /**
31739  * Register (SYSREG) ap_trccntvr#
31740  *
31741  * AP Register
31742  */
31743 union bdk_ap_trccntvrx
31744 {
31745     uint64_t u;
31746     struct bdk_ap_trccntvrx_s
31747     {
31748 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31749         uint64_t reserved_0_63         : 64;
31750 #else /* Word 0 - Little Endian */
31751         uint64_t reserved_0_63         : 64;
31752 #endif /* Word 0 - End */
31753     } s;
31754     /* struct bdk_ap_trccntvrx_s cn; */
31755 };
31756 typedef union bdk_ap_trccntvrx bdk_ap_trccntvrx_t;
31757 
31758 static inline uint64_t BDK_AP_TRCCNTVRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCCNTVRX(unsigned long a)31759 static inline uint64_t BDK_AP_TRCCNTVRX(unsigned long a)
31760 {
31761     if (a<=3)
31762         return 0x20100080500ll + 0x10000ll * ((a) & 0x3);
31763     __bdk_csr_fatal("AP_TRCCNTVRX", 1, a, 0, 0, 0);
31764 }
31765 
31766 #define typedef_BDK_AP_TRCCNTVRX(a) bdk_ap_trccntvrx_t
31767 #define bustype_BDK_AP_TRCCNTVRX(a) BDK_CSR_TYPE_SYSREG
31768 #define basename_BDK_AP_TRCCNTVRX(a) "AP_TRCCNTVRX"
31769 #define busnum_BDK_AP_TRCCNTVRX(a) (a)
31770 #define arguments_BDK_AP_TRCCNTVRX(a) (a),-1,-1,-1
31771 
31772 /**
31773  * Register (SYSREG) ap_trcconfigr
31774  *
31775  * AP Register
31776  */
31777 union bdk_ap_trcconfigr
31778 {
31779     uint64_t u;
31780     struct bdk_ap_trcconfigr_s
31781     {
31782 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31783         uint64_t reserved_0_63         : 64;
31784 #else /* Word 0 - Little Endian */
31785         uint64_t reserved_0_63         : 64;
31786 #endif /* Word 0 - End */
31787     } s;
31788     /* struct bdk_ap_trcconfigr_s cn; */
31789 };
31790 typedef union bdk_ap_trcconfigr bdk_ap_trcconfigr_t;
31791 
31792 #define BDK_AP_TRCCONFIGR BDK_AP_TRCCONFIGR_FUNC()
31793 static inline uint64_t BDK_AP_TRCCONFIGR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCCONFIGR_FUNC(void)31794 static inline uint64_t BDK_AP_TRCCONFIGR_FUNC(void)
31795 {
31796     return 0x20100040000ll;
31797 }
31798 
31799 #define typedef_BDK_AP_TRCCONFIGR bdk_ap_trcconfigr_t
31800 #define bustype_BDK_AP_TRCCONFIGR BDK_CSR_TYPE_SYSREG
31801 #define basename_BDK_AP_TRCCONFIGR "AP_TRCCONFIGR"
31802 #define busnum_BDK_AP_TRCCONFIGR 0
31803 #define arguments_BDK_AP_TRCCONFIGR -1,-1,-1,-1
31804 
31805 /**
31806  * Register (SYSREG) ap_trcdevaff#
31807  *
31808  * AP Register
31809  */
31810 union bdk_ap_trcdevaffx
31811 {
31812     uint64_t u;
31813     struct bdk_ap_trcdevaffx_s
31814     {
31815 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31816         uint64_t reserved_0_63         : 64;
31817 #else /* Word 0 - Little Endian */
31818         uint64_t reserved_0_63         : 64;
31819 #endif /* Word 0 - End */
31820     } s;
31821     /* struct bdk_ap_trcdevaffx_s cn; */
31822 };
31823 typedef union bdk_ap_trcdevaffx bdk_ap_trcdevaffx_t;
31824 
31825 static inline uint64_t BDK_AP_TRCDEVAFFX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCDEVAFFX(unsigned long a)31826 static inline uint64_t BDK_AP_TRCDEVAFFX(unsigned long a)
31827 {
31828     if (a<=1)
31829         return 0x201070a0600ll + 0x10000ll * ((a) & 0x1);
31830     __bdk_csr_fatal("AP_TRCDEVAFFX", 1, a, 0, 0, 0);
31831 }
31832 
31833 #define typedef_BDK_AP_TRCDEVAFFX(a) bdk_ap_trcdevaffx_t
31834 #define bustype_BDK_AP_TRCDEVAFFX(a) BDK_CSR_TYPE_SYSREG
31835 #define basename_BDK_AP_TRCDEVAFFX(a) "AP_TRCDEVAFFX"
31836 #define busnum_BDK_AP_TRCDEVAFFX(a) (a)
31837 #define arguments_BDK_AP_TRCDEVAFFX(a) (a),-1,-1,-1
31838 
31839 /**
31840  * Register (SYSREG) ap_trcdevarch
31841  *
31842  * AP Register
31843  */
31844 union bdk_ap_trcdevarch
31845 {
31846     uint64_t u;
31847     struct bdk_ap_trcdevarch_s
31848     {
31849 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31850         uint64_t reserved_0_63         : 64;
31851 #else /* Word 0 - Little Endian */
31852         uint64_t reserved_0_63         : 64;
31853 #endif /* Word 0 - End */
31854     } s;
31855     /* struct bdk_ap_trcdevarch_s cn; */
31856 };
31857 typedef union bdk_ap_trcdevarch bdk_ap_trcdevarch_t;
31858 
31859 #define BDK_AP_TRCDEVARCH BDK_AP_TRCDEVARCH_FUNC()
31860 static inline uint64_t BDK_AP_TRCDEVARCH_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCDEVARCH_FUNC(void)31861 static inline uint64_t BDK_AP_TRCDEVARCH_FUNC(void)
31862 {
31863     return 0x201070f0600ll;
31864 }
31865 
31866 #define typedef_BDK_AP_TRCDEVARCH bdk_ap_trcdevarch_t
31867 #define bustype_BDK_AP_TRCDEVARCH BDK_CSR_TYPE_SYSREG
31868 #define basename_BDK_AP_TRCDEVARCH "AP_TRCDEVARCH"
31869 #define busnum_BDK_AP_TRCDEVARCH 0
31870 #define arguments_BDK_AP_TRCDEVARCH -1,-1,-1,-1
31871 
31872 /**
31873  * Register (SYSREG) ap_trcdevid
31874  *
31875  * AP Register
31876  */
31877 union bdk_ap_trcdevid
31878 {
31879     uint64_t u;
31880     struct bdk_ap_trcdevid_s
31881     {
31882 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31883         uint64_t reserved_0_63         : 64;
31884 #else /* Word 0 - Little Endian */
31885         uint64_t reserved_0_63         : 64;
31886 #endif /* Word 0 - End */
31887     } s;
31888     /* struct bdk_ap_trcdevid_s cn; */
31889 };
31890 typedef union bdk_ap_trcdevid bdk_ap_trcdevid_t;
31891 
31892 #define BDK_AP_TRCDEVID BDK_AP_TRCDEVID_FUNC()
31893 static inline uint64_t BDK_AP_TRCDEVID_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCDEVID_FUNC(void)31894 static inline uint64_t BDK_AP_TRCDEVID_FUNC(void)
31895 {
31896     return 0x20107020700ll;
31897 }
31898 
31899 #define typedef_BDK_AP_TRCDEVID bdk_ap_trcdevid_t
31900 #define bustype_BDK_AP_TRCDEVID BDK_CSR_TYPE_SYSREG
31901 #define basename_BDK_AP_TRCDEVID "AP_TRCDEVID"
31902 #define busnum_BDK_AP_TRCDEVID 0
31903 #define arguments_BDK_AP_TRCDEVID -1,-1,-1,-1
31904 
31905 /**
31906  * Register (SYSREG) ap_trcdevtype
31907  *
31908  * AP Register
31909  */
31910 union bdk_ap_trcdevtype
31911 {
31912     uint64_t u;
31913     struct bdk_ap_trcdevtype_s
31914     {
31915 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31916         uint64_t reserved_0_63         : 64;
31917 #else /* Word 0 - Little Endian */
31918         uint64_t reserved_0_63         : 64;
31919 #endif /* Word 0 - End */
31920     } s;
31921     /* struct bdk_ap_trcdevtype_s cn; */
31922 };
31923 typedef union bdk_ap_trcdevtype bdk_ap_trcdevtype_t;
31924 
31925 #define BDK_AP_TRCDEVTYPE BDK_AP_TRCDEVTYPE_FUNC()
31926 static inline uint64_t BDK_AP_TRCDEVTYPE_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCDEVTYPE_FUNC(void)31927 static inline uint64_t BDK_AP_TRCDEVTYPE_FUNC(void)
31928 {
31929     return 0x20107030700ll;
31930 }
31931 
31932 #define typedef_BDK_AP_TRCDEVTYPE bdk_ap_trcdevtype_t
31933 #define bustype_BDK_AP_TRCDEVTYPE BDK_CSR_TYPE_SYSREG
31934 #define basename_BDK_AP_TRCDEVTYPE "AP_TRCDEVTYPE"
31935 #define busnum_BDK_AP_TRCDEVTYPE 0
31936 #define arguments_BDK_AP_TRCDEVTYPE -1,-1,-1,-1
31937 
31938 /**
31939  * Register (SYSREG) ap_trcdvcmr#
31940  *
31941  * AP Register
31942  */
31943 union bdk_ap_trcdvcmrx
31944 {
31945     uint64_t u;
31946     struct bdk_ap_trcdvcmrx_s
31947     {
31948 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31949         uint64_t reserved_0_63         : 64;
31950 #else /* Word 0 - Little Endian */
31951         uint64_t reserved_0_63         : 64;
31952 #endif /* Word 0 - End */
31953     } s;
31954     /* struct bdk_ap_trcdvcmrx_s cn; */
31955 };
31956 typedef union bdk_ap_trcdvcmrx bdk_ap_trcdvcmrx_t;
31957 
31958 static inline uint64_t BDK_AP_TRCDVCMRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCDVCMRX(unsigned long a)31959 static inline uint64_t BDK_AP_TRCDVCMRX(unsigned long a)
31960 {
31961     if (a<=7)
31962         return 0x20102000600ll + 0x40000ll * ((a) & 0x7);
31963     __bdk_csr_fatal("AP_TRCDVCMRX", 1, a, 0, 0, 0);
31964 }
31965 
31966 #define typedef_BDK_AP_TRCDVCMRX(a) bdk_ap_trcdvcmrx_t
31967 #define bustype_BDK_AP_TRCDVCMRX(a) BDK_CSR_TYPE_SYSREG
31968 #define basename_BDK_AP_TRCDVCMRX(a) "AP_TRCDVCMRX"
31969 #define busnum_BDK_AP_TRCDVCMRX(a) (a)
31970 #define arguments_BDK_AP_TRCDVCMRX(a) (a),-1,-1,-1
31971 
31972 /**
31973  * Register (SYSREG) ap_trcdvcvr#
31974  *
31975  * AP Register
31976  */
31977 union bdk_ap_trcdvcvrx
31978 {
31979     uint64_t u;
31980     struct bdk_ap_trcdvcvrx_s
31981     {
31982 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
31983         uint64_t reserved_0_63         : 64;
31984 #else /* Word 0 - Little Endian */
31985         uint64_t reserved_0_63         : 64;
31986 #endif /* Word 0 - End */
31987     } s;
31988     /* struct bdk_ap_trcdvcvrx_s cn; */
31989 };
31990 typedef union bdk_ap_trcdvcvrx bdk_ap_trcdvcvrx_t;
31991 
31992 static inline uint64_t BDK_AP_TRCDVCVRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCDVCVRX(unsigned long a)31993 static inline uint64_t BDK_AP_TRCDVCVRX(unsigned long a)
31994 {
31995     if (a<=7)
31996         return 0x20102000400ll + 0x40000ll * ((a) & 0x7);
31997     __bdk_csr_fatal("AP_TRCDVCVRX", 1, a, 0, 0, 0);
31998 }
31999 
32000 #define typedef_BDK_AP_TRCDVCVRX(a) bdk_ap_trcdvcvrx_t
32001 #define bustype_BDK_AP_TRCDVCVRX(a) BDK_CSR_TYPE_SYSREG
32002 #define basename_BDK_AP_TRCDVCVRX(a) "AP_TRCDVCVRX"
32003 #define busnum_BDK_AP_TRCDVCVRX(a) (a)
32004 #define arguments_BDK_AP_TRCDVCVRX(a) (a),-1,-1,-1
32005 
32006 /**
32007  * Register (SYSREG) ap_trceventctl#r
32008  *
32009  * AP Register
32010  */
32011 union bdk_ap_trceventctlxr
32012 {
32013     uint64_t u;
32014     struct bdk_ap_trceventctlxr_s
32015     {
32016 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32017         uint64_t reserved_0_63         : 64;
32018 #else /* Word 0 - Little Endian */
32019         uint64_t reserved_0_63         : 64;
32020 #endif /* Word 0 - End */
32021     } s;
32022     /* struct bdk_ap_trceventctlxr_s cn; */
32023 };
32024 typedef union bdk_ap_trceventctlxr bdk_ap_trceventctlxr_t;
32025 
32026 static inline uint64_t BDK_AP_TRCEVENTCTLXR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCEVENTCTLXR(unsigned long a)32027 static inline uint64_t BDK_AP_TRCEVENTCTLXR(unsigned long a)
32028 {
32029     if (a<=1)
32030         return 0x20100080000ll + 0x10000ll * ((a) & 0x1);
32031     __bdk_csr_fatal("AP_TRCEVENTCTLXR", 1, a, 0, 0, 0);
32032 }
32033 
32034 #define typedef_BDK_AP_TRCEVENTCTLXR(a) bdk_ap_trceventctlxr_t
32035 #define bustype_BDK_AP_TRCEVENTCTLXR(a) BDK_CSR_TYPE_SYSREG
32036 #define basename_BDK_AP_TRCEVENTCTLXR(a) "AP_TRCEVENTCTLXR"
32037 #define busnum_BDK_AP_TRCEVENTCTLXR(a) (a)
32038 #define arguments_BDK_AP_TRCEVENTCTLXR(a) (a),-1,-1,-1
32039 
32040 /**
32041  * Register (SYSREG) ap_trcextinselr
32042  *
32043  * AP Register
32044  */
32045 union bdk_ap_trcextinselr
32046 {
32047     uint64_t u;
32048     struct bdk_ap_trcextinselr_s
32049     {
32050 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32051         uint64_t reserved_0_63         : 64;
32052 #else /* Word 0 - Little Endian */
32053         uint64_t reserved_0_63         : 64;
32054 #endif /* Word 0 - End */
32055     } s;
32056     /* struct bdk_ap_trcextinselr_s cn; */
32057 };
32058 typedef union bdk_ap_trcextinselr bdk_ap_trcextinselr_t;
32059 
32060 #define BDK_AP_TRCEXTINSELR BDK_AP_TRCEXTINSELR_FUNC()
32061 static inline uint64_t BDK_AP_TRCEXTINSELR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCEXTINSELR_FUNC(void)32062 static inline uint64_t BDK_AP_TRCEXTINSELR_FUNC(void)
32063 {
32064     return 0x20100080400ll;
32065 }
32066 
32067 #define typedef_BDK_AP_TRCEXTINSELR bdk_ap_trcextinselr_t
32068 #define bustype_BDK_AP_TRCEXTINSELR BDK_CSR_TYPE_SYSREG
32069 #define basename_BDK_AP_TRCEXTINSELR "AP_TRCEXTINSELR"
32070 #define busnum_BDK_AP_TRCEXTINSELR 0
32071 #define arguments_BDK_AP_TRCEXTINSELR -1,-1,-1,-1
32072 
32073 /**
32074  * Register (SYSREG) ap_trcidr#
32075  *
32076  * AP Register
32077  */
32078 union bdk_ap_trcidrx
32079 {
32080     uint64_t u;
32081     struct bdk_ap_trcidrx_s
32082     {
32083 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32084         uint64_t reserved_0_63         : 64;
32085 #else /* Word 0 - Little Endian */
32086         uint64_t reserved_0_63         : 64;
32087 #endif /* Word 0 - End */
32088     } s;
32089     /* struct bdk_ap_trcidrx_s cn; */
32090 };
32091 typedef union bdk_ap_trcidrx bdk_ap_trcidrx_t;
32092 
32093 static inline uint64_t BDK_AP_TRCIDRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCIDRX(unsigned long a)32094 static inline uint64_t BDK_AP_TRCIDRX(unsigned long a)
32095 {
32096     if (a<=13)
32097         return 0x20100080700ll + 0x10000ll * ((a) & 0xf);
32098     __bdk_csr_fatal("AP_TRCIDRX", 1, a, 0, 0, 0);
32099 }
32100 
32101 #define typedef_BDK_AP_TRCIDRX(a) bdk_ap_trcidrx_t
32102 #define bustype_BDK_AP_TRCIDRX(a) BDK_CSR_TYPE_SYSREG
32103 #define basename_BDK_AP_TRCIDRX(a) "AP_TRCIDRX"
32104 #define busnum_BDK_AP_TRCIDRX(a) (a)
32105 #define arguments_BDK_AP_TRCIDRX(a) (a),-1,-1,-1
32106 
32107 /**
32108  * Register (SYSREG) ap_trcimspec#
32109  *
32110  * AP Register
32111  */
32112 union bdk_ap_trcimspecx
32113 {
32114     uint64_t u;
32115     struct bdk_ap_trcimspecx_s
32116     {
32117 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32118         uint64_t reserved_0_63         : 64;
32119 #else /* Word 0 - Little Endian */
32120         uint64_t reserved_0_63         : 64;
32121 #endif /* Word 0 - End */
32122     } s;
32123     /* struct bdk_ap_trcimspecx_s cn; */
32124 };
32125 typedef union bdk_ap_trcimspecx bdk_ap_trcimspecx_t;
32126 
32127 static inline uint64_t BDK_AP_TRCIMSPECX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCIMSPECX(unsigned long a)32128 static inline uint64_t BDK_AP_TRCIMSPECX(unsigned long a)
32129 {
32130     if (a<=7)
32131         return 0x20100000700ll + 0x10000ll * ((a) & 0x7);
32132     __bdk_csr_fatal("AP_TRCIMSPECX", 1, a, 0, 0, 0);
32133 }
32134 
32135 #define typedef_BDK_AP_TRCIMSPECX(a) bdk_ap_trcimspecx_t
32136 #define bustype_BDK_AP_TRCIMSPECX(a) BDK_CSR_TYPE_SYSREG
32137 #define basename_BDK_AP_TRCIMSPECX(a) "AP_TRCIMSPECX"
32138 #define busnum_BDK_AP_TRCIMSPECX(a) (a)
32139 #define arguments_BDK_AP_TRCIMSPECX(a) (a),-1,-1,-1
32140 
32141 /**
32142  * Register (SYSREG) ap_trcitctrl
32143  *
32144  * AP Register
32145  */
32146 union bdk_ap_trcitctrl
32147 {
32148     uint64_t u;
32149     struct bdk_ap_trcitctrl_s
32150     {
32151 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32152         uint64_t reserved_0_63         : 64;
32153 #else /* Word 0 - Little Endian */
32154         uint64_t reserved_0_63         : 64;
32155 #endif /* Word 0 - End */
32156     } s;
32157     /* struct bdk_ap_trcitctrl_s cn; */
32158 };
32159 typedef union bdk_ap_trcitctrl bdk_ap_trcitctrl_t;
32160 
32161 #define BDK_AP_TRCITCTRL BDK_AP_TRCITCTRL_FUNC()
32162 static inline uint64_t BDK_AP_TRCITCTRL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCITCTRL_FUNC(void)32163 static inline uint64_t BDK_AP_TRCITCTRL_FUNC(void)
32164 {
32165     return 0x20107000400ll;
32166 }
32167 
32168 #define typedef_BDK_AP_TRCITCTRL bdk_ap_trcitctrl_t
32169 #define bustype_BDK_AP_TRCITCTRL BDK_CSR_TYPE_SYSREG
32170 #define basename_BDK_AP_TRCITCTRL "AP_TRCITCTRL"
32171 #define busnum_BDK_AP_TRCITCTRL 0
32172 #define arguments_BDK_AP_TRCITCTRL -1,-1,-1,-1
32173 
32174 /**
32175  * Register (SYSREG) ap_trclar
32176  *
32177  * AP Register
32178  */
32179 union bdk_ap_trclar
32180 {
32181     uint64_t u;
32182     struct bdk_ap_trclar_s
32183     {
32184 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32185         uint64_t reserved_0_63         : 64;
32186 #else /* Word 0 - Little Endian */
32187         uint64_t reserved_0_63         : 64;
32188 #endif /* Word 0 - End */
32189     } s;
32190     /* struct bdk_ap_trclar_s cn; */
32191 };
32192 typedef union bdk_ap_trclar bdk_ap_trclar_t;
32193 
32194 #define BDK_AP_TRCLAR BDK_AP_TRCLAR_FUNC()
32195 static inline uint64_t BDK_AP_TRCLAR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCLAR_FUNC(void)32196 static inline uint64_t BDK_AP_TRCLAR_FUNC(void)
32197 {
32198     return 0x201070c0600ll;
32199 }
32200 
32201 #define typedef_BDK_AP_TRCLAR bdk_ap_trclar_t
32202 #define bustype_BDK_AP_TRCLAR BDK_CSR_TYPE_SYSREG
32203 #define basename_BDK_AP_TRCLAR "AP_TRCLAR"
32204 #define busnum_BDK_AP_TRCLAR 0
32205 #define arguments_BDK_AP_TRCLAR -1,-1,-1,-1
32206 
32207 /**
32208  * Register (SYSREG) ap_trclsr
32209  *
32210  * AP Register
32211  */
32212 union bdk_ap_trclsr
32213 {
32214     uint64_t u;
32215     struct bdk_ap_trclsr_s
32216     {
32217 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32218         uint64_t reserved_0_63         : 64;
32219 #else /* Word 0 - Little Endian */
32220         uint64_t reserved_0_63         : 64;
32221 #endif /* Word 0 - End */
32222     } s;
32223     /* struct bdk_ap_trclsr_s cn; */
32224 };
32225 typedef union bdk_ap_trclsr bdk_ap_trclsr_t;
32226 
32227 #define BDK_AP_TRCLSR BDK_AP_TRCLSR_FUNC()
32228 static inline uint64_t BDK_AP_TRCLSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCLSR_FUNC(void)32229 static inline uint64_t BDK_AP_TRCLSR_FUNC(void)
32230 {
32231     return 0x201070d0600ll;
32232 }
32233 
32234 #define typedef_BDK_AP_TRCLSR bdk_ap_trclsr_t
32235 #define bustype_BDK_AP_TRCLSR BDK_CSR_TYPE_SYSREG
32236 #define basename_BDK_AP_TRCLSR "AP_TRCLSR"
32237 #define busnum_BDK_AP_TRCLSR 0
32238 #define arguments_BDK_AP_TRCLSR -1,-1,-1,-1
32239 
32240 /**
32241  * Register (SYSREG) ap_trcoslar
32242  *
32243  * AP Register
32244  */
32245 union bdk_ap_trcoslar
32246 {
32247     uint64_t u;
32248     struct bdk_ap_trcoslar_s
32249     {
32250 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32251         uint64_t reserved_0_63         : 64;
32252 #else /* Word 0 - Little Endian */
32253         uint64_t reserved_0_63         : 64;
32254 #endif /* Word 0 - End */
32255     } s;
32256     /* struct bdk_ap_trcoslar_s cn; */
32257 };
32258 typedef union bdk_ap_trcoslar bdk_ap_trcoslar_t;
32259 
32260 #define BDK_AP_TRCOSLAR BDK_AP_TRCOSLAR_FUNC()
32261 static inline uint64_t BDK_AP_TRCOSLAR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCOSLAR_FUNC(void)32262 static inline uint64_t BDK_AP_TRCOSLAR_FUNC(void)
32263 {
32264     return 0x20101000400ll;
32265 }
32266 
32267 #define typedef_BDK_AP_TRCOSLAR bdk_ap_trcoslar_t
32268 #define bustype_BDK_AP_TRCOSLAR BDK_CSR_TYPE_SYSREG
32269 #define basename_BDK_AP_TRCOSLAR "AP_TRCOSLAR"
32270 #define busnum_BDK_AP_TRCOSLAR 0
32271 #define arguments_BDK_AP_TRCOSLAR -1,-1,-1,-1
32272 
32273 /**
32274  * Register (SYSREG) ap_trcoslsr
32275  *
32276  * AP Register
32277  */
32278 union bdk_ap_trcoslsr
32279 {
32280     uint64_t u;
32281     struct bdk_ap_trcoslsr_s
32282     {
32283 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32284         uint64_t reserved_0_63         : 64;
32285 #else /* Word 0 - Little Endian */
32286         uint64_t reserved_0_63         : 64;
32287 #endif /* Word 0 - End */
32288     } s;
32289     /* struct bdk_ap_trcoslsr_s cn; */
32290 };
32291 typedef union bdk_ap_trcoslsr bdk_ap_trcoslsr_t;
32292 
32293 #define BDK_AP_TRCOSLSR BDK_AP_TRCOSLSR_FUNC()
32294 static inline uint64_t BDK_AP_TRCOSLSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCOSLSR_FUNC(void)32295 static inline uint64_t BDK_AP_TRCOSLSR_FUNC(void)
32296 {
32297     return 0x20101010400ll;
32298 }
32299 
32300 #define typedef_BDK_AP_TRCOSLSR bdk_ap_trcoslsr_t
32301 #define bustype_BDK_AP_TRCOSLSR BDK_CSR_TYPE_SYSREG
32302 #define basename_BDK_AP_TRCOSLSR "AP_TRCOSLSR"
32303 #define busnum_BDK_AP_TRCOSLSR 0
32304 #define arguments_BDK_AP_TRCOSLSR -1,-1,-1,-1
32305 
32306 /**
32307  * Register (SYSREG) ap_trcpdcr
32308  *
32309  * AP Register
32310  */
32311 union bdk_ap_trcpdcr
32312 {
32313     uint64_t u;
32314     struct bdk_ap_trcpdcr_s
32315     {
32316 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32317         uint64_t reserved_0_63         : 64;
32318 #else /* Word 0 - Little Endian */
32319         uint64_t reserved_0_63         : 64;
32320 #endif /* Word 0 - End */
32321     } s;
32322     /* struct bdk_ap_trcpdcr_s cn; */
32323 };
32324 typedef union bdk_ap_trcpdcr bdk_ap_trcpdcr_t;
32325 
32326 #define BDK_AP_TRCPDCR BDK_AP_TRCPDCR_FUNC()
32327 static inline uint64_t BDK_AP_TRCPDCR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCPDCR_FUNC(void)32328 static inline uint64_t BDK_AP_TRCPDCR_FUNC(void)
32329 {
32330     return 0x20101040400ll;
32331 }
32332 
32333 #define typedef_BDK_AP_TRCPDCR bdk_ap_trcpdcr_t
32334 #define bustype_BDK_AP_TRCPDCR BDK_CSR_TYPE_SYSREG
32335 #define basename_BDK_AP_TRCPDCR "AP_TRCPDCR"
32336 #define busnum_BDK_AP_TRCPDCR 0
32337 #define arguments_BDK_AP_TRCPDCR -1,-1,-1,-1
32338 
32339 /**
32340  * Register (SYSREG) ap_trcpdsr
32341  *
32342  * AP Register
32343  */
32344 union bdk_ap_trcpdsr
32345 {
32346     uint64_t u;
32347     struct bdk_ap_trcpdsr_s
32348     {
32349 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32350         uint64_t reserved_0_63         : 64;
32351 #else /* Word 0 - Little Endian */
32352         uint64_t reserved_0_63         : 64;
32353 #endif /* Word 0 - End */
32354     } s;
32355     /* struct bdk_ap_trcpdsr_s cn; */
32356 };
32357 typedef union bdk_ap_trcpdsr bdk_ap_trcpdsr_t;
32358 
32359 #define BDK_AP_TRCPDSR BDK_AP_TRCPDSR_FUNC()
32360 static inline uint64_t BDK_AP_TRCPDSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCPDSR_FUNC(void)32361 static inline uint64_t BDK_AP_TRCPDSR_FUNC(void)
32362 {
32363     return 0x20101050400ll;
32364 }
32365 
32366 #define typedef_BDK_AP_TRCPDSR bdk_ap_trcpdsr_t
32367 #define bustype_BDK_AP_TRCPDSR BDK_CSR_TYPE_SYSREG
32368 #define basename_BDK_AP_TRCPDSR "AP_TRCPDSR"
32369 #define busnum_BDK_AP_TRCPDSR 0
32370 #define arguments_BDK_AP_TRCPDSR -1,-1,-1,-1
32371 
32372 /**
32373  * Register (SYSREG) ap_trcpidr#
32374  *
32375  * AP Register
32376  */
32377 union bdk_ap_trcpidrx
32378 {
32379     uint64_t u;
32380     struct bdk_ap_trcpidrx_s
32381     {
32382 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32383         uint64_t reserved_0_63         : 64;
32384 #else /* Word 0 - Little Endian */
32385         uint64_t reserved_0_63         : 64;
32386 #endif /* Word 0 - End */
32387     } s;
32388     /* struct bdk_ap_trcpidrx_s cn; */
32389 };
32390 typedef union bdk_ap_trcpidrx bdk_ap_trcpidrx_t;
32391 
32392 static inline uint64_t BDK_AP_TRCPIDRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCPIDRX(unsigned long a)32393 static inline uint64_t BDK_AP_TRCPIDRX(unsigned long a)
32394 {
32395     if (a<=7)
32396         return 0x20107080700ll + 0x10000ll * ((a) & 0x7);
32397     __bdk_csr_fatal("AP_TRCPIDRX", 1, a, 0, 0, 0);
32398 }
32399 
32400 #define typedef_BDK_AP_TRCPIDRX(a) bdk_ap_trcpidrx_t
32401 #define bustype_BDK_AP_TRCPIDRX(a) BDK_CSR_TYPE_SYSREG
32402 #define basename_BDK_AP_TRCPIDRX(a) "AP_TRCPIDRX"
32403 #define busnum_BDK_AP_TRCPIDRX(a) (a)
32404 #define arguments_BDK_AP_TRCPIDRX(a) (a),-1,-1,-1
32405 
32406 /**
32407  * Register (SYSREG) ap_trcprgctlr
32408  *
32409  * AP Register
32410  */
32411 union bdk_ap_trcprgctlr
32412 {
32413     uint64_t u;
32414     struct bdk_ap_trcprgctlr_s
32415     {
32416 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32417         uint64_t reserved_0_63         : 64;
32418 #else /* Word 0 - Little Endian */
32419         uint64_t reserved_0_63         : 64;
32420 #endif /* Word 0 - End */
32421     } s;
32422     /* struct bdk_ap_trcprgctlr_s cn; */
32423 };
32424 typedef union bdk_ap_trcprgctlr bdk_ap_trcprgctlr_t;
32425 
32426 #define BDK_AP_TRCPRGCTLR BDK_AP_TRCPRGCTLR_FUNC()
32427 static inline uint64_t BDK_AP_TRCPRGCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCPRGCTLR_FUNC(void)32428 static inline uint64_t BDK_AP_TRCPRGCTLR_FUNC(void)
32429 {
32430     return 0x20100010000ll;
32431 }
32432 
32433 #define typedef_BDK_AP_TRCPRGCTLR bdk_ap_trcprgctlr_t
32434 #define bustype_BDK_AP_TRCPRGCTLR BDK_CSR_TYPE_SYSREG
32435 #define basename_BDK_AP_TRCPRGCTLR "AP_TRCPRGCTLR"
32436 #define busnum_BDK_AP_TRCPRGCTLR 0
32437 #define arguments_BDK_AP_TRCPRGCTLR -1,-1,-1,-1
32438 
32439 /**
32440  * Register (SYSREG) ap_trcprocselr
32441  *
32442  * AP Register
32443  */
32444 union bdk_ap_trcprocselr
32445 {
32446     uint64_t u;
32447     struct bdk_ap_trcprocselr_s
32448     {
32449 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32450         uint64_t reserved_0_63         : 64;
32451 #else /* Word 0 - Little Endian */
32452         uint64_t reserved_0_63         : 64;
32453 #endif /* Word 0 - End */
32454     } s;
32455     /* struct bdk_ap_trcprocselr_s cn; */
32456 };
32457 typedef union bdk_ap_trcprocselr bdk_ap_trcprocselr_t;
32458 
32459 #define BDK_AP_TRCPROCSELR BDK_AP_TRCPROCSELR_FUNC()
32460 static inline uint64_t BDK_AP_TRCPROCSELR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCPROCSELR_FUNC(void)32461 static inline uint64_t BDK_AP_TRCPROCSELR_FUNC(void)
32462 {
32463     return 0x20100020000ll;
32464 }
32465 
32466 #define typedef_BDK_AP_TRCPROCSELR bdk_ap_trcprocselr_t
32467 #define bustype_BDK_AP_TRCPROCSELR BDK_CSR_TYPE_SYSREG
32468 #define basename_BDK_AP_TRCPROCSELR "AP_TRCPROCSELR"
32469 #define busnum_BDK_AP_TRCPROCSELR 0
32470 #define arguments_BDK_AP_TRCPROCSELR -1,-1,-1,-1
32471 
32472 /**
32473  * Register (SYSREG) ap_trcqctlr
32474  *
32475  * AP Register
32476  */
32477 union bdk_ap_trcqctlr
32478 {
32479     uint64_t u;
32480     struct bdk_ap_trcqctlr_s
32481     {
32482 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32483         uint64_t reserved_0_63         : 64;
32484 #else /* Word 0 - Little Endian */
32485         uint64_t reserved_0_63         : 64;
32486 #endif /* Word 0 - End */
32487     } s;
32488     /* struct bdk_ap_trcqctlr_s cn; */
32489 };
32490 typedef union bdk_ap_trcqctlr bdk_ap_trcqctlr_t;
32491 
32492 #define BDK_AP_TRCQCTLR BDK_AP_TRCQCTLR_FUNC()
32493 static inline uint64_t BDK_AP_TRCQCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCQCTLR_FUNC(void)32494 static inline uint64_t BDK_AP_TRCQCTLR_FUNC(void)
32495 {
32496     return 0x20100010100ll;
32497 }
32498 
32499 #define typedef_BDK_AP_TRCQCTLR bdk_ap_trcqctlr_t
32500 #define bustype_BDK_AP_TRCQCTLR BDK_CSR_TYPE_SYSREG
32501 #define basename_BDK_AP_TRCQCTLR "AP_TRCQCTLR"
32502 #define busnum_BDK_AP_TRCQCTLR 0
32503 #define arguments_BDK_AP_TRCQCTLR -1,-1,-1,-1
32504 
32505 /**
32506  * Register (SYSREG) ap_trcrsctlr#
32507  *
32508  * AP Register
32509  */
32510 union bdk_ap_trcrsctlrx
32511 {
32512     uint64_t u;
32513     struct bdk_ap_trcrsctlrx_s
32514     {
32515 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32516         uint64_t reserved_0_63         : 64;
32517 #else /* Word 0 - Little Endian */
32518         uint64_t reserved_0_63         : 64;
32519 #endif /* Word 0 - End */
32520     } s;
32521     /* struct bdk_ap_trcrsctlrx_s cn; */
32522 };
32523 typedef union bdk_ap_trcrsctlrx bdk_ap_trcrsctlrx_t;
32524 
32525 static inline uint64_t BDK_AP_TRCRSCTLRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCRSCTLRX(unsigned long a)32526 static inline uint64_t BDK_AP_TRCRSCTLRX(unsigned long a)
32527 {
32528     if ((a>=2)&&(a<=31))
32529         return 0x20101000000ll + 0x10000ll * ((a) & 0x1f);
32530     __bdk_csr_fatal("AP_TRCRSCTLRX", 1, a, 0, 0, 0);
32531 }
32532 
32533 #define typedef_BDK_AP_TRCRSCTLRX(a) bdk_ap_trcrsctlrx_t
32534 #define bustype_BDK_AP_TRCRSCTLRX(a) BDK_CSR_TYPE_SYSREG
32535 #define basename_BDK_AP_TRCRSCTLRX(a) "AP_TRCRSCTLRX"
32536 #define busnum_BDK_AP_TRCRSCTLRX(a) (a)
32537 #define arguments_BDK_AP_TRCRSCTLRX(a) (a),-1,-1,-1
32538 
32539 /**
32540  * Register (SYSREG) ap_trcseqevr#
32541  *
32542  * AP Register
32543  */
32544 union bdk_ap_trcseqevrx
32545 {
32546     uint64_t u;
32547     struct bdk_ap_trcseqevrx_s
32548     {
32549 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32550         uint64_t reserved_0_63         : 64;
32551 #else /* Word 0 - Little Endian */
32552         uint64_t reserved_0_63         : 64;
32553 #endif /* Word 0 - End */
32554     } s;
32555     /* struct bdk_ap_trcseqevrx_s cn; */
32556 };
32557 typedef union bdk_ap_trcseqevrx bdk_ap_trcseqevrx_t;
32558 
32559 static inline uint64_t BDK_AP_TRCSEQEVRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCSEQEVRX(unsigned long a)32560 static inline uint64_t BDK_AP_TRCSEQEVRX(unsigned long a)
32561 {
32562     if (a<=2)
32563         return 0x20100000400ll + 0x10000ll * ((a) & 0x3);
32564     __bdk_csr_fatal("AP_TRCSEQEVRX", 1, a, 0, 0, 0);
32565 }
32566 
32567 #define typedef_BDK_AP_TRCSEQEVRX(a) bdk_ap_trcseqevrx_t
32568 #define bustype_BDK_AP_TRCSEQEVRX(a) BDK_CSR_TYPE_SYSREG
32569 #define basename_BDK_AP_TRCSEQEVRX(a) "AP_TRCSEQEVRX"
32570 #define busnum_BDK_AP_TRCSEQEVRX(a) (a)
32571 #define arguments_BDK_AP_TRCSEQEVRX(a) (a),-1,-1,-1
32572 
32573 /**
32574  * Register (SYSREG) ap_trcseqrstevr
32575  *
32576  * AP Register
32577  */
32578 union bdk_ap_trcseqrstevr
32579 {
32580     uint64_t u;
32581     struct bdk_ap_trcseqrstevr_s
32582     {
32583 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32584         uint64_t reserved_0_63         : 64;
32585 #else /* Word 0 - Little Endian */
32586         uint64_t reserved_0_63         : 64;
32587 #endif /* Word 0 - End */
32588     } s;
32589     /* struct bdk_ap_trcseqrstevr_s cn; */
32590 };
32591 typedef union bdk_ap_trcseqrstevr bdk_ap_trcseqrstevr_t;
32592 
32593 #define BDK_AP_TRCSEQRSTEVR BDK_AP_TRCSEQRSTEVR_FUNC()
32594 static inline uint64_t BDK_AP_TRCSEQRSTEVR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCSEQRSTEVR_FUNC(void)32595 static inline uint64_t BDK_AP_TRCSEQRSTEVR_FUNC(void)
32596 {
32597     return 0x20100060400ll;
32598 }
32599 
32600 #define typedef_BDK_AP_TRCSEQRSTEVR bdk_ap_trcseqrstevr_t
32601 #define bustype_BDK_AP_TRCSEQRSTEVR BDK_CSR_TYPE_SYSREG
32602 #define basename_BDK_AP_TRCSEQRSTEVR "AP_TRCSEQRSTEVR"
32603 #define busnum_BDK_AP_TRCSEQRSTEVR 0
32604 #define arguments_BDK_AP_TRCSEQRSTEVR -1,-1,-1,-1
32605 
32606 /**
32607  * Register (SYSREG) ap_trcseqstr
32608  *
32609  * AP Register
32610  */
32611 union bdk_ap_trcseqstr
32612 {
32613     uint64_t u;
32614     struct bdk_ap_trcseqstr_s
32615     {
32616 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32617         uint64_t reserved_0_63         : 64;
32618 #else /* Word 0 - Little Endian */
32619         uint64_t reserved_0_63         : 64;
32620 #endif /* Word 0 - End */
32621     } s;
32622     /* struct bdk_ap_trcseqstr_s cn; */
32623 };
32624 typedef union bdk_ap_trcseqstr bdk_ap_trcseqstr_t;
32625 
32626 #define BDK_AP_TRCSEQSTR BDK_AP_TRCSEQSTR_FUNC()
32627 static inline uint64_t BDK_AP_TRCSEQSTR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCSEQSTR_FUNC(void)32628 static inline uint64_t BDK_AP_TRCSEQSTR_FUNC(void)
32629 {
32630     return 0x20100070400ll;
32631 }
32632 
32633 #define typedef_BDK_AP_TRCSEQSTR bdk_ap_trcseqstr_t
32634 #define bustype_BDK_AP_TRCSEQSTR BDK_CSR_TYPE_SYSREG
32635 #define basename_BDK_AP_TRCSEQSTR "AP_TRCSEQSTR"
32636 #define busnum_BDK_AP_TRCSEQSTR 0
32637 #define arguments_BDK_AP_TRCSEQSTR -1,-1,-1,-1
32638 
32639 /**
32640  * Register (SYSREG) ap_trcssccr#
32641  *
32642  * AP Register
32643  */
32644 union bdk_ap_trcssccrx
32645 {
32646     uint64_t u;
32647     struct bdk_ap_trcssccrx_s
32648     {
32649 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32650         uint64_t reserved_0_63         : 64;
32651 #else /* Word 0 - Little Endian */
32652         uint64_t reserved_0_63         : 64;
32653 #endif /* Word 0 - End */
32654     } s;
32655     /* struct bdk_ap_trcssccrx_s cn; */
32656 };
32657 typedef union bdk_ap_trcssccrx bdk_ap_trcssccrx_t;
32658 
32659 static inline uint64_t BDK_AP_TRCSSCCRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCSSCCRX(unsigned long a)32660 static inline uint64_t BDK_AP_TRCSSCCRX(unsigned long a)
32661 {
32662     if (a<=7)
32663         return 0x20101000200ll + 0x10000ll * ((a) & 0x7);
32664     __bdk_csr_fatal("AP_TRCSSCCRX", 1, a, 0, 0, 0);
32665 }
32666 
32667 #define typedef_BDK_AP_TRCSSCCRX(a) bdk_ap_trcssccrx_t
32668 #define bustype_BDK_AP_TRCSSCCRX(a) BDK_CSR_TYPE_SYSREG
32669 #define basename_BDK_AP_TRCSSCCRX(a) "AP_TRCSSCCRX"
32670 #define busnum_BDK_AP_TRCSSCCRX(a) (a)
32671 #define arguments_BDK_AP_TRCSSCCRX(a) (a),-1,-1,-1
32672 
32673 /**
32674  * Register (SYSREG) ap_trcsscsr#
32675  *
32676  * AP Register
32677  */
32678 union bdk_ap_trcsscsrx
32679 {
32680     uint64_t u;
32681     struct bdk_ap_trcsscsrx_s
32682     {
32683 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32684         uint64_t reserved_0_63         : 64;
32685 #else /* Word 0 - Little Endian */
32686         uint64_t reserved_0_63         : 64;
32687 #endif /* Word 0 - End */
32688     } s;
32689     /* struct bdk_ap_trcsscsrx_s cn; */
32690 };
32691 typedef union bdk_ap_trcsscsrx bdk_ap_trcsscsrx_t;
32692 
32693 static inline uint64_t BDK_AP_TRCSSCSRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCSSCSRX(unsigned long a)32694 static inline uint64_t BDK_AP_TRCSSCSRX(unsigned long a)
32695 {
32696     if (a<=7)
32697         return 0x20101080200ll + 0x10000ll * ((a) & 0x7);
32698     __bdk_csr_fatal("AP_TRCSSCSRX", 1, a, 0, 0, 0);
32699 }
32700 
32701 #define typedef_BDK_AP_TRCSSCSRX(a) bdk_ap_trcsscsrx_t
32702 #define bustype_BDK_AP_TRCSSCSRX(a) BDK_CSR_TYPE_SYSREG
32703 #define basename_BDK_AP_TRCSSCSRX(a) "AP_TRCSSCSRX"
32704 #define busnum_BDK_AP_TRCSSCSRX(a) (a)
32705 #define arguments_BDK_AP_TRCSSCSRX(a) (a),-1,-1,-1
32706 
32707 /**
32708  * Register (SYSREG) ap_trcsspcicr#
32709  *
32710  * AP Register
32711  */
32712 union bdk_ap_trcsspcicrx
32713 {
32714     uint64_t u;
32715     struct bdk_ap_trcsspcicrx_s
32716     {
32717 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32718         uint64_t reserved_0_63         : 64;
32719 #else /* Word 0 - Little Endian */
32720         uint64_t reserved_0_63         : 64;
32721 #endif /* Word 0 - End */
32722     } s;
32723     /* struct bdk_ap_trcsspcicrx_s cn; */
32724 };
32725 typedef union bdk_ap_trcsspcicrx bdk_ap_trcsspcicrx_t;
32726 
32727 static inline uint64_t BDK_AP_TRCSSPCICRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCSSPCICRX(unsigned long a)32728 static inline uint64_t BDK_AP_TRCSSPCICRX(unsigned long a)
32729 {
32730     if (a<=7)
32731         return 0x20101000300ll + 0x10000ll * ((a) & 0x7);
32732     __bdk_csr_fatal("AP_TRCSSPCICRX", 1, a, 0, 0, 0);
32733 }
32734 
32735 #define typedef_BDK_AP_TRCSSPCICRX(a) bdk_ap_trcsspcicrx_t
32736 #define bustype_BDK_AP_TRCSSPCICRX(a) BDK_CSR_TYPE_SYSREG
32737 #define basename_BDK_AP_TRCSSPCICRX(a) "AP_TRCSSPCICRX"
32738 #define busnum_BDK_AP_TRCSSPCICRX(a) (a)
32739 #define arguments_BDK_AP_TRCSSPCICRX(a) (a),-1,-1,-1
32740 
32741 /**
32742  * Register (SYSREG) ap_trcstallctlr
32743  *
32744  * AP Register
32745  */
32746 union bdk_ap_trcstallctlr
32747 {
32748     uint64_t u;
32749     struct bdk_ap_trcstallctlr_s
32750     {
32751 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32752         uint64_t reserved_0_63         : 64;
32753 #else /* Word 0 - Little Endian */
32754         uint64_t reserved_0_63         : 64;
32755 #endif /* Word 0 - End */
32756     } s;
32757     /* struct bdk_ap_trcstallctlr_s cn; */
32758 };
32759 typedef union bdk_ap_trcstallctlr bdk_ap_trcstallctlr_t;
32760 
32761 #define BDK_AP_TRCSTALLCTLR BDK_AP_TRCSTALLCTLR_FUNC()
32762 static inline uint64_t BDK_AP_TRCSTALLCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCSTALLCTLR_FUNC(void)32763 static inline uint64_t BDK_AP_TRCSTALLCTLR_FUNC(void)
32764 {
32765     return 0x201000b0000ll;
32766 }
32767 
32768 #define typedef_BDK_AP_TRCSTALLCTLR bdk_ap_trcstallctlr_t
32769 #define bustype_BDK_AP_TRCSTALLCTLR BDK_CSR_TYPE_SYSREG
32770 #define basename_BDK_AP_TRCSTALLCTLR "AP_TRCSTALLCTLR"
32771 #define busnum_BDK_AP_TRCSTALLCTLR 0
32772 #define arguments_BDK_AP_TRCSTALLCTLR -1,-1,-1,-1
32773 
32774 /**
32775  * Register (SYSREG) ap_trcstatr
32776  *
32777  * AP Register
32778  */
32779 union bdk_ap_trcstatr
32780 {
32781     uint64_t u;
32782     struct bdk_ap_trcstatr_s
32783     {
32784 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32785         uint64_t reserved_0_63         : 64;
32786 #else /* Word 0 - Little Endian */
32787         uint64_t reserved_0_63         : 64;
32788 #endif /* Word 0 - End */
32789     } s;
32790     /* struct bdk_ap_trcstatr_s cn; */
32791 };
32792 typedef union bdk_ap_trcstatr bdk_ap_trcstatr_t;
32793 
32794 #define BDK_AP_TRCSTATR BDK_AP_TRCSTATR_FUNC()
32795 static inline uint64_t BDK_AP_TRCSTATR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCSTATR_FUNC(void)32796 static inline uint64_t BDK_AP_TRCSTATR_FUNC(void)
32797 {
32798     return 0x20100030000ll;
32799 }
32800 
32801 #define typedef_BDK_AP_TRCSTATR bdk_ap_trcstatr_t
32802 #define bustype_BDK_AP_TRCSTATR BDK_CSR_TYPE_SYSREG
32803 #define basename_BDK_AP_TRCSTATR "AP_TRCSTATR"
32804 #define busnum_BDK_AP_TRCSTATR 0
32805 #define arguments_BDK_AP_TRCSTATR -1,-1,-1,-1
32806 
32807 /**
32808  * Register (SYSREG) ap_trcsyncpr
32809  *
32810  * AP Register
32811  */
32812 union bdk_ap_trcsyncpr
32813 {
32814     uint64_t u;
32815     struct bdk_ap_trcsyncpr_s
32816     {
32817 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32818         uint64_t reserved_0_63         : 64;
32819 #else /* Word 0 - Little Endian */
32820         uint64_t reserved_0_63         : 64;
32821 #endif /* Word 0 - End */
32822     } s;
32823     /* struct bdk_ap_trcsyncpr_s cn; */
32824 };
32825 typedef union bdk_ap_trcsyncpr bdk_ap_trcsyncpr_t;
32826 
32827 #define BDK_AP_TRCSYNCPR BDK_AP_TRCSYNCPR_FUNC()
32828 static inline uint64_t BDK_AP_TRCSYNCPR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCSYNCPR_FUNC(void)32829 static inline uint64_t BDK_AP_TRCSYNCPR_FUNC(void)
32830 {
32831     return 0x201000d0000ll;
32832 }
32833 
32834 #define typedef_BDK_AP_TRCSYNCPR bdk_ap_trcsyncpr_t
32835 #define bustype_BDK_AP_TRCSYNCPR BDK_CSR_TYPE_SYSREG
32836 #define basename_BDK_AP_TRCSYNCPR "AP_TRCSYNCPR"
32837 #define busnum_BDK_AP_TRCSYNCPR 0
32838 #define arguments_BDK_AP_TRCSYNCPR -1,-1,-1,-1
32839 
32840 /**
32841  * Register (SYSREG) ap_trctraceidr
32842  *
32843  * AP Register
32844  */
32845 union bdk_ap_trctraceidr
32846 {
32847     uint64_t u;
32848     struct bdk_ap_trctraceidr_s
32849     {
32850 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32851         uint64_t reserved_0_63         : 64;
32852 #else /* Word 0 - Little Endian */
32853         uint64_t reserved_0_63         : 64;
32854 #endif /* Word 0 - End */
32855     } s;
32856     /* struct bdk_ap_trctraceidr_s cn; */
32857 };
32858 typedef union bdk_ap_trctraceidr bdk_ap_trctraceidr_t;
32859 
32860 #define BDK_AP_TRCTRACEIDR BDK_AP_TRCTRACEIDR_FUNC()
32861 static inline uint64_t BDK_AP_TRCTRACEIDR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCTRACEIDR_FUNC(void)32862 static inline uint64_t BDK_AP_TRCTRACEIDR_FUNC(void)
32863 {
32864     return 0x20100000100ll;
32865 }
32866 
32867 #define typedef_BDK_AP_TRCTRACEIDR bdk_ap_trctraceidr_t
32868 #define bustype_BDK_AP_TRCTRACEIDR BDK_CSR_TYPE_SYSREG
32869 #define basename_BDK_AP_TRCTRACEIDR "AP_TRCTRACEIDR"
32870 #define busnum_BDK_AP_TRCTRACEIDR 0
32871 #define arguments_BDK_AP_TRCTRACEIDR -1,-1,-1,-1
32872 
32873 /**
32874  * Register (SYSREG) ap_trctsctlr
32875  *
32876  * AP Register
32877  */
32878 union bdk_ap_trctsctlr
32879 {
32880     uint64_t u;
32881     struct bdk_ap_trctsctlr_s
32882     {
32883 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32884         uint64_t reserved_0_63         : 64;
32885 #else /* Word 0 - Little Endian */
32886         uint64_t reserved_0_63         : 64;
32887 #endif /* Word 0 - End */
32888     } s;
32889     /* struct bdk_ap_trctsctlr_s cn; */
32890 };
32891 typedef union bdk_ap_trctsctlr bdk_ap_trctsctlr_t;
32892 
32893 #define BDK_AP_TRCTSCTLR BDK_AP_TRCTSCTLR_FUNC()
32894 static inline uint64_t BDK_AP_TRCTSCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCTSCTLR_FUNC(void)32895 static inline uint64_t BDK_AP_TRCTSCTLR_FUNC(void)
32896 {
32897     return 0x201000c0000ll;
32898 }
32899 
32900 #define typedef_BDK_AP_TRCTSCTLR bdk_ap_trctsctlr_t
32901 #define bustype_BDK_AP_TRCTSCTLR BDK_CSR_TYPE_SYSREG
32902 #define basename_BDK_AP_TRCTSCTLR "AP_TRCTSCTLR"
32903 #define busnum_BDK_AP_TRCTSCTLR 0
32904 #define arguments_BDK_AP_TRCTSCTLR -1,-1,-1,-1
32905 
32906 /**
32907  * Register (SYSREG) ap_trcvdarcctlr
32908  *
32909  * AP Register
32910  */
32911 union bdk_ap_trcvdarcctlr
32912 {
32913     uint64_t u;
32914     struct bdk_ap_trcvdarcctlr_s
32915     {
32916 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32917         uint64_t reserved_0_63         : 64;
32918 #else /* Word 0 - Little Endian */
32919         uint64_t reserved_0_63         : 64;
32920 #endif /* Word 0 - End */
32921     } s;
32922     /* struct bdk_ap_trcvdarcctlr_s cn; */
32923 };
32924 typedef union bdk_ap_trcvdarcctlr bdk_ap_trcvdarcctlr_t;
32925 
32926 #define BDK_AP_TRCVDARCCTLR BDK_AP_TRCVDARCCTLR_FUNC()
32927 static inline uint64_t BDK_AP_TRCVDARCCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCVDARCCTLR_FUNC(void)32928 static inline uint64_t BDK_AP_TRCVDARCCTLR_FUNC(void)
32929 {
32930     return 0x201000a0200ll;
32931 }
32932 
32933 #define typedef_BDK_AP_TRCVDARCCTLR bdk_ap_trcvdarcctlr_t
32934 #define bustype_BDK_AP_TRCVDARCCTLR BDK_CSR_TYPE_SYSREG
32935 #define basename_BDK_AP_TRCVDARCCTLR "AP_TRCVDARCCTLR"
32936 #define busnum_BDK_AP_TRCVDARCCTLR 0
32937 #define arguments_BDK_AP_TRCVDARCCTLR -1,-1,-1,-1
32938 
32939 /**
32940  * Register (SYSREG) ap_trcvdctlr
32941  *
32942  * AP Register
32943  */
32944 union bdk_ap_trcvdctlr
32945 {
32946     uint64_t u;
32947     struct bdk_ap_trcvdctlr_s
32948     {
32949 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32950         uint64_t reserved_0_63         : 64;
32951 #else /* Word 0 - Little Endian */
32952         uint64_t reserved_0_63         : 64;
32953 #endif /* Word 0 - End */
32954     } s;
32955     /* struct bdk_ap_trcvdctlr_s cn; */
32956 };
32957 typedef union bdk_ap_trcvdctlr bdk_ap_trcvdctlr_t;
32958 
32959 #define BDK_AP_TRCVDCTLR BDK_AP_TRCVDCTLR_FUNC()
32960 static inline uint64_t BDK_AP_TRCVDCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCVDCTLR_FUNC(void)32961 static inline uint64_t BDK_AP_TRCVDCTLR_FUNC(void)
32962 {
32963     return 0x20100080200ll;
32964 }
32965 
32966 #define typedef_BDK_AP_TRCVDCTLR bdk_ap_trcvdctlr_t
32967 #define bustype_BDK_AP_TRCVDCTLR BDK_CSR_TYPE_SYSREG
32968 #define basename_BDK_AP_TRCVDCTLR "AP_TRCVDCTLR"
32969 #define busnum_BDK_AP_TRCVDCTLR 0
32970 #define arguments_BDK_AP_TRCVDCTLR -1,-1,-1,-1
32971 
32972 /**
32973  * Register (SYSREG) ap_trcvdsacctlr
32974  *
32975  * AP Register
32976  */
32977 union bdk_ap_trcvdsacctlr
32978 {
32979     uint64_t u;
32980     struct bdk_ap_trcvdsacctlr_s
32981     {
32982 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
32983         uint64_t reserved_0_63         : 64;
32984 #else /* Word 0 - Little Endian */
32985         uint64_t reserved_0_63         : 64;
32986 #endif /* Word 0 - End */
32987     } s;
32988     /* struct bdk_ap_trcvdsacctlr_s cn; */
32989 };
32990 typedef union bdk_ap_trcvdsacctlr bdk_ap_trcvdsacctlr_t;
32991 
32992 #define BDK_AP_TRCVDSACCTLR BDK_AP_TRCVDSACCTLR_FUNC()
32993 static inline uint64_t BDK_AP_TRCVDSACCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCVDSACCTLR_FUNC(void)32994 static inline uint64_t BDK_AP_TRCVDSACCTLR_FUNC(void)
32995 {
32996     return 0x20100090200ll;
32997 }
32998 
32999 #define typedef_BDK_AP_TRCVDSACCTLR bdk_ap_trcvdsacctlr_t
33000 #define bustype_BDK_AP_TRCVDSACCTLR BDK_CSR_TYPE_SYSREG
33001 #define basename_BDK_AP_TRCVDSACCTLR "AP_TRCVDSACCTLR"
33002 #define busnum_BDK_AP_TRCVDSACCTLR 0
33003 #define arguments_BDK_AP_TRCVDSACCTLR -1,-1,-1,-1
33004 
33005 /**
33006  * Register (SYSREG) ap_trcvictlr
33007  *
33008  * AP Register
33009  */
33010 union bdk_ap_trcvictlr
33011 {
33012     uint64_t u;
33013     struct bdk_ap_trcvictlr_s
33014     {
33015 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33016         uint64_t reserved_0_63         : 64;
33017 #else /* Word 0 - Little Endian */
33018         uint64_t reserved_0_63         : 64;
33019 #endif /* Word 0 - End */
33020     } s;
33021     /* struct bdk_ap_trcvictlr_s cn; */
33022 };
33023 typedef union bdk_ap_trcvictlr bdk_ap_trcvictlr_t;
33024 
33025 #define BDK_AP_TRCVICTLR BDK_AP_TRCVICTLR_FUNC()
33026 static inline uint64_t BDK_AP_TRCVICTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCVICTLR_FUNC(void)33027 static inline uint64_t BDK_AP_TRCVICTLR_FUNC(void)
33028 {
33029     return 0x20100000200ll;
33030 }
33031 
33032 #define typedef_BDK_AP_TRCVICTLR bdk_ap_trcvictlr_t
33033 #define bustype_BDK_AP_TRCVICTLR BDK_CSR_TYPE_SYSREG
33034 #define basename_BDK_AP_TRCVICTLR "AP_TRCVICTLR"
33035 #define busnum_BDK_AP_TRCVICTLR 0
33036 #define arguments_BDK_AP_TRCVICTLR -1,-1,-1,-1
33037 
33038 /**
33039  * Register (SYSREG) ap_trcviiectlr
33040  *
33041  * AP Register
33042  */
33043 union bdk_ap_trcviiectlr
33044 {
33045     uint64_t u;
33046     struct bdk_ap_trcviiectlr_s
33047     {
33048 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33049         uint64_t reserved_0_63         : 64;
33050 #else /* Word 0 - Little Endian */
33051         uint64_t reserved_0_63         : 64;
33052 #endif /* Word 0 - End */
33053     } s;
33054     /* struct bdk_ap_trcviiectlr_s cn; */
33055 };
33056 typedef union bdk_ap_trcviiectlr bdk_ap_trcviiectlr_t;
33057 
33058 #define BDK_AP_TRCVIIECTLR BDK_AP_TRCVIIECTLR_FUNC()
33059 static inline uint64_t BDK_AP_TRCVIIECTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCVIIECTLR_FUNC(void)33060 static inline uint64_t BDK_AP_TRCVIIECTLR_FUNC(void)
33061 {
33062     return 0x20100010200ll;
33063 }
33064 
33065 #define typedef_BDK_AP_TRCVIIECTLR bdk_ap_trcviiectlr_t
33066 #define bustype_BDK_AP_TRCVIIECTLR BDK_CSR_TYPE_SYSREG
33067 #define basename_BDK_AP_TRCVIIECTLR "AP_TRCVIIECTLR"
33068 #define busnum_BDK_AP_TRCVIIECTLR 0
33069 #define arguments_BDK_AP_TRCVIIECTLR -1,-1,-1,-1
33070 
33071 /**
33072  * Register (SYSREG) ap_trcvipcssctlr
33073  *
33074  * AP Register
33075  */
33076 union bdk_ap_trcvipcssctlr
33077 {
33078     uint64_t u;
33079     struct bdk_ap_trcvipcssctlr_s
33080     {
33081 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33082         uint64_t reserved_0_63         : 64;
33083 #else /* Word 0 - Little Endian */
33084         uint64_t reserved_0_63         : 64;
33085 #endif /* Word 0 - End */
33086     } s;
33087     /* struct bdk_ap_trcvipcssctlr_s cn; */
33088 };
33089 typedef union bdk_ap_trcvipcssctlr bdk_ap_trcvipcssctlr_t;
33090 
33091 #define BDK_AP_TRCVIPCSSCTLR BDK_AP_TRCVIPCSSCTLR_FUNC()
33092 static inline uint64_t BDK_AP_TRCVIPCSSCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCVIPCSSCTLR_FUNC(void)33093 static inline uint64_t BDK_AP_TRCVIPCSSCTLR_FUNC(void)
33094 {
33095     return 0x20100030200ll;
33096 }
33097 
33098 #define typedef_BDK_AP_TRCVIPCSSCTLR bdk_ap_trcvipcssctlr_t
33099 #define bustype_BDK_AP_TRCVIPCSSCTLR BDK_CSR_TYPE_SYSREG
33100 #define basename_BDK_AP_TRCVIPCSSCTLR "AP_TRCVIPCSSCTLR"
33101 #define busnum_BDK_AP_TRCVIPCSSCTLR 0
33102 #define arguments_BDK_AP_TRCVIPCSSCTLR -1,-1,-1,-1
33103 
33104 /**
33105  * Register (SYSREG) ap_trcvissctlr
33106  *
33107  * AP Register
33108  */
33109 union bdk_ap_trcvissctlr
33110 {
33111     uint64_t u;
33112     struct bdk_ap_trcvissctlr_s
33113     {
33114 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33115         uint64_t reserved_0_63         : 64;
33116 #else /* Word 0 - Little Endian */
33117         uint64_t reserved_0_63         : 64;
33118 #endif /* Word 0 - End */
33119     } s;
33120     /* struct bdk_ap_trcvissctlr_s cn; */
33121 };
33122 typedef union bdk_ap_trcvissctlr bdk_ap_trcvissctlr_t;
33123 
33124 #define BDK_AP_TRCVISSCTLR BDK_AP_TRCVISSCTLR_FUNC()
33125 static inline uint64_t BDK_AP_TRCVISSCTLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TRCVISSCTLR_FUNC(void)33126 static inline uint64_t BDK_AP_TRCVISSCTLR_FUNC(void)
33127 {
33128     return 0x20100020200ll;
33129 }
33130 
33131 #define typedef_BDK_AP_TRCVISSCTLR bdk_ap_trcvissctlr_t
33132 #define bustype_BDK_AP_TRCVISSCTLR BDK_CSR_TYPE_SYSREG
33133 #define basename_BDK_AP_TRCVISSCTLR "AP_TRCVISSCTLR"
33134 #define busnum_BDK_AP_TRCVISSCTLR 0
33135 #define arguments_BDK_AP_TRCVISSCTLR -1,-1,-1,-1
33136 
33137 /**
33138  * Register (SYSREG) ap_trcvmidcctlr#
33139  *
33140  * AP Register
33141  */
33142 union bdk_ap_trcvmidcctlrx
33143 {
33144     uint64_t u;
33145     struct bdk_ap_trcvmidcctlrx_s
33146     {
33147 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33148         uint64_t reserved_0_63         : 64;
33149 #else /* Word 0 - Little Endian */
33150         uint64_t reserved_0_63         : 64;
33151 #endif /* Word 0 - End */
33152     } s;
33153     /* struct bdk_ap_trcvmidcctlrx_s cn; */
33154 };
33155 typedef union bdk_ap_trcvmidcctlrx bdk_ap_trcvmidcctlrx_t;
33156 
33157 static inline uint64_t BDK_AP_TRCVMIDCCTLRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCVMIDCCTLRX(unsigned long a)33158 static inline uint64_t BDK_AP_TRCVMIDCCTLRX(unsigned long a)
33159 {
33160     if (a<=1)
33161         return 0x20103020200ll + 0x10000ll * ((a) & 0x1);
33162     __bdk_csr_fatal("AP_TRCVMIDCCTLRX", 1, a, 0, 0, 0);
33163 }
33164 
33165 #define typedef_BDK_AP_TRCVMIDCCTLRX(a) bdk_ap_trcvmidcctlrx_t
33166 #define bustype_BDK_AP_TRCVMIDCCTLRX(a) BDK_CSR_TYPE_SYSREG
33167 #define basename_BDK_AP_TRCVMIDCCTLRX(a) "AP_TRCVMIDCCTLRX"
33168 #define busnum_BDK_AP_TRCVMIDCCTLRX(a) (a)
33169 #define arguments_BDK_AP_TRCVMIDCCTLRX(a) (a),-1,-1,-1
33170 
33171 /**
33172  * Register (SYSREG) ap_trcvmidcvr#
33173  *
33174  * AP Register
33175  */
33176 union bdk_ap_trcvmidcvrx
33177 {
33178     uint64_t u;
33179     struct bdk_ap_trcvmidcvrx_s
33180     {
33181 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33182         uint64_t reserved_0_63         : 64;
33183 #else /* Word 0 - Little Endian */
33184         uint64_t reserved_0_63         : 64;
33185 #endif /* Word 0 - End */
33186     } s;
33187     /* struct bdk_ap_trcvmidcvrx_s cn; */
33188 };
33189 typedef union bdk_ap_trcvmidcvrx bdk_ap_trcvmidcvrx_t;
33190 
33191 static inline uint64_t BDK_AP_TRCVMIDCVRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_TRCVMIDCVRX(unsigned long a)33192 static inline uint64_t BDK_AP_TRCVMIDCVRX(unsigned long a)
33193 {
33194     if (a<=7)
33195         return 0x20103000100ll + 0x20000ll * ((a) & 0x7);
33196     __bdk_csr_fatal("AP_TRCVMIDCVRX", 1, a, 0, 0, 0);
33197 }
33198 
33199 #define typedef_BDK_AP_TRCVMIDCVRX(a) bdk_ap_trcvmidcvrx_t
33200 #define bustype_BDK_AP_TRCVMIDCVRX(a) BDK_CSR_TYPE_SYSREG
33201 #define basename_BDK_AP_TRCVMIDCVRX(a) "AP_TRCVMIDCVRX"
33202 #define busnum_BDK_AP_TRCVMIDCVRX(a) (a)
33203 #define arguments_BDK_AP_TRCVMIDCVRX(a) (a),-1,-1,-1
33204 
33205 /**
33206  * Register (SYSREG) ap_ttbr0_el1
33207  *
33208  * AP Translation Table Base EL1 Register 0
33209  * Holds the base address of translation table 0, and information
33210  *     about the memory it occupies. This is one of the translation
33211  *     tables for the stage 1 translation of memory accesses at EL0
33212  *     and EL1.
33213  */
33214 union bdk_ap_ttbr0_el1
33215 {
33216     uint64_t u;
33217     struct bdk_ap_ttbr0_el1_s
33218     {
33219 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33220         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33221                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33222                                                                  If the implementation has only 8 bits of ASID, then the upper
33223                                                                      8 bits of this field are RES0. */
33224         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33225                                                                      RES0.
33226 
33227                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33228                                                                      translation, and the memory translation granule size.
33229                                                                  The AArch64 Virtual Memory System Architecture chapter
33230                                                                      describes how x is calculated.
33231                                                                  The value of x determines the required alignment of the
33232                                                                      translation table, which must be aligned to 22^(x)
33233                                                                      bytes.
33234 
33235                                                                  If bits [x-1:0] are not all zero, this is a misaligned
33236                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33237                                                                      UNPREDICTABLE, and can be one of the following:
33238 
33239                                                                   Bits [x-1:0] are treated as if all the bits are zero. The
33240                                                                      value read back from those bits might be the value written or
33241                                                                      might be zero.
33242 
33243                                                                   The calculation of an address for a translation table walk
33244                                                                      using this register can be corrupted in those bits that are
33245                                                                      nonzero. */
33246         uint64_t reserved_1_3          : 3;
33247         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
33248 #else /* Word 0 - Little Endian */
33249         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
33250         uint64_t reserved_1_3          : 3;
33251         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33252                                                                      RES0.
33253 
33254                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33255                                                                      translation, and the memory translation granule size.
33256                                                                  The AArch64 Virtual Memory System Architecture chapter
33257                                                                      describes how x is calculated.
33258                                                                  The value of x determines the required alignment of the
33259                                                                      translation table, which must be aligned to 22^(x)
33260                                                                      bytes.
33261 
33262                                                                  If bits [x-1:0] are not all zero, this is a misaligned
33263                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33264                                                                      UNPREDICTABLE, and can be one of the following:
33265 
33266                                                                   Bits [x-1:0] are treated as if all the bits are zero. The
33267                                                                      value read back from those bits might be the value written or
33268                                                                      might be zero.
33269 
33270                                                                   The calculation of an address for a translation table walk
33271                                                                      using this register can be corrupted in those bits that are
33272                                                                      nonzero. */
33273         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33274                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33275                                                                  If the implementation has only 8 bits of ASID, then the upper
33276                                                                      8 bits of this field are RES0. */
33277 #endif /* Word 0 - End */
33278     } s;
33279     struct bdk_ap_ttbr0_el1_cn8
33280     {
33281 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33282         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33283                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33284                                                                  If the implementation has only 8 bits of ASID, then the upper
33285                                                                      8 bits of this field are RES0. */
33286         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33287                                                                      RES0.
33288 
33289                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33290                                                                      translation, and the memory translation granule size.
33291                                                                  The AArch64 Virtual Memory System Architecture chapter
33292                                                                      describes how x is calculated.
33293                                                                  The value of x determines the required alignment of the
33294                                                                      translation table, which must be aligned to 22^(x)
33295                                                                      bytes.
33296 
33297                                                                  If bits [x-1:0] are not all zero, this is a misaligned
33298                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33299                                                                      UNPREDICTABLE, and can be one of the following:
33300 
33301                                                                   Bits [x-1:0] are treated as if all the bits are zero. The
33302                                                                      value read back from those bits might be the value written or
33303                                                                      might be zero.
33304 
33305                                                                   The calculation of an address for a translation table walk
33306                                                                      using this register can be corrupted in those bits that are
33307                                                                      nonzero. */
33308         uint64_t reserved_0_3          : 4;
33309 #else /* Word 0 - Little Endian */
33310         uint64_t reserved_0_3          : 4;
33311         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33312                                                                      RES0.
33313 
33314                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33315                                                                      translation, and the memory translation granule size.
33316                                                                  The AArch64 Virtual Memory System Architecture chapter
33317                                                                      describes how x is calculated.
33318                                                                  The value of x determines the required alignment of the
33319                                                                      translation table, which must be aligned to 22^(x)
33320                                                                      bytes.
33321 
33322                                                                  If bits [x-1:0] are not all zero, this is a misaligned
33323                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33324                                                                      UNPREDICTABLE, and can be one of the following:
33325 
33326                                                                   Bits [x-1:0] are treated as if all the bits are zero. The
33327                                                                      value read back from those bits might be the value written or
33328                                                                      might be zero.
33329 
33330                                                                   The calculation of an address for a translation table walk
33331                                                                      using this register can be corrupted in those bits that are
33332                                                                      nonzero. */
33333         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33334                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33335                                                                  If the implementation has only 8 bits of ASID, then the upper
33336                                                                      8 bits of this field are RES0. */
33337 #endif /* Word 0 - End */
33338     } cn8;
33339     /* struct bdk_ap_ttbr0_el1_s cn9; */
33340 };
33341 typedef union bdk_ap_ttbr0_el1 bdk_ap_ttbr0_el1_t;
33342 
33343 #define BDK_AP_TTBR0_EL1 BDK_AP_TTBR0_EL1_FUNC()
33344 static inline uint64_t BDK_AP_TTBR0_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TTBR0_EL1_FUNC(void)33345 static inline uint64_t BDK_AP_TTBR0_EL1_FUNC(void)
33346 {
33347     return 0x30002000000ll;
33348 }
33349 
33350 #define typedef_BDK_AP_TTBR0_EL1 bdk_ap_ttbr0_el1_t
33351 #define bustype_BDK_AP_TTBR0_EL1 BDK_CSR_TYPE_SYSREG
33352 #define basename_BDK_AP_TTBR0_EL1 "AP_TTBR0_EL1"
33353 #define busnum_BDK_AP_TTBR0_EL1 0
33354 #define arguments_BDK_AP_TTBR0_EL1 -1,-1,-1,-1
33355 
33356 /**
33357  * Register (SYSREG) ap_ttbr0_el12
33358  *
33359  * AP Translation Table Base EL1/2 Register 0
33360  * Alias of AP_TTBR0_EL1 from EL2 when AP_HCR_EL2[E2H] is set.
33361  */
33362 union bdk_ap_ttbr0_el12
33363 {
33364     uint64_t u;
33365     struct bdk_ap_ttbr0_el12_s
33366     {
33367 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33368         uint64_t reserved_0_63         : 64;
33369 #else /* Word 0 - Little Endian */
33370         uint64_t reserved_0_63         : 64;
33371 #endif /* Word 0 - End */
33372     } s;
33373     /* struct bdk_ap_ttbr0_el12_s cn; */
33374 };
33375 typedef union bdk_ap_ttbr0_el12 bdk_ap_ttbr0_el12_t;
33376 
33377 #define BDK_AP_TTBR0_EL12 BDK_AP_TTBR0_EL12_FUNC()
33378 static inline uint64_t BDK_AP_TTBR0_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TTBR0_EL12_FUNC(void)33379 static inline uint64_t BDK_AP_TTBR0_EL12_FUNC(void)
33380 {
33381     return 0x30502000000ll;
33382 }
33383 
33384 #define typedef_BDK_AP_TTBR0_EL12 bdk_ap_ttbr0_el12_t
33385 #define bustype_BDK_AP_TTBR0_EL12 BDK_CSR_TYPE_SYSREG
33386 #define basename_BDK_AP_TTBR0_EL12 "AP_TTBR0_EL12"
33387 #define busnum_BDK_AP_TTBR0_EL12 0
33388 #define arguments_BDK_AP_TTBR0_EL12 -1,-1,-1,-1
33389 
33390 /**
33391  * Register (SYSREG) ap_ttbr0_el2
33392  *
33393  * AP Translation Table Base EL2 Register 0
33394  * Holds the base address of translation table 0, and information
33395  *     about the memory it occupies. This is one of the translation
33396  *     tables for the stage 1 translation of memory accesses at EL0
33397  *     and EL2 when Virtual Host Extensions are enabled.
33398  */
33399 union bdk_ap_ttbr0_el2
33400 {
33401     uint64_t u;
33402     struct bdk_ap_ttbr0_el2_s
33403     {
33404 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33405         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33406                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33407                                                                  If the implementation has only 8 bits of ASID, then the upper
33408                                                                      8 bits of this field are RES0. */
33409         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33410                                                                      RES0.
33411 
33412                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33413                                                                      translation, and the memory translation granule size.
33414                                                                  The AArch64 Virtual Memory System Architecture chapter
33415                                                                      describes how x is calculated.
33416                                                                  The value of x determines the required alignment of the
33417                                                                      translation table, which must be aligned to 22^(x)
33418                                                                      bytes.
33419 
33420                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33421                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33422                                                                      UNPREDICTABLE, and can be one of the following:
33423 
33424                                                                   Bits \<x-1:0\> are treated as if all the bits are zero. The
33425                                                                      value read back from those bits might be the value written or
33426                                                                      might be zero.
33427 
33428                                                                   The calculation of an address for a translation table walk
33429                                                                      using this register can be corrupted in those bits that are
33430                                                                      nonzero. */
33431         uint64_t reserved_1_3          : 3;
33432         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
33433 #else /* Word 0 - Little Endian */
33434         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
33435         uint64_t reserved_1_3          : 3;
33436         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33437                                                                      RES0.
33438 
33439                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33440                                                                      translation, and the memory translation granule size.
33441                                                                  The AArch64 Virtual Memory System Architecture chapter
33442                                                                      describes how x is calculated.
33443                                                                  The value of x determines the required alignment of the
33444                                                                      translation table, which must be aligned to 22^(x)
33445                                                                      bytes.
33446 
33447                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33448                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33449                                                                      UNPREDICTABLE, and can be one of the following:
33450 
33451                                                                   Bits \<x-1:0\> are treated as if all the bits are zero. The
33452                                                                      value read back from those bits might be the value written or
33453                                                                      might be zero.
33454 
33455                                                                   The calculation of an address for a translation table walk
33456                                                                      using this register can be corrupted in those bits that are
33457                                                                      nonzero. */
33458         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33459                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33460                                                                  If the implementation has only 8 bits of ASID, then the upper
33461                                                                      8 bits of this field are RES0. */
33462 #endif /* Word 0 - End */
33463     } s;
33464     struct bdk_ap_ttbr0_el2_cn8
33465     {
33466 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33467         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33468                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33469                                                                  If the implementation has only 8 bits of ASID, then the upper
33470                                                                      8 bits of this field are RES0. */
33471         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33472                                                                      RES0.
33473 
33474                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33475                                                                      translation, and the memory translation granule size.
33476                                                                  The AArch64 Virtual Memory System Architecture chapter
33477                                                                      describes how x is calculated.
33478                                                                  The value of x determines the required alignment of the
33479                                                                      translation table, which must be aligned to 22^(x)
33480                                                                      bytes.
33481 
33482                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33483                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33484                                                                      UNPREDICTABLE, and can be one of the following:
33485 
33486                                                                   Bits \<x-1:0\> are treated as if all the bits are zero. The
33487                                                                      value read back from those bits might be the value written or
33488                                                                      might be zero.
33489 
33490                                                                   The calculation of an address for a translation table walk
33491                                                                      using this register can be corrupted in those bits that are
33492                                                                      nonzero. */
33493         uint64_t reserved_0_3          : 4;
33494 #else /* Word 0 - Little Endian */
33495         uint64_t reserved_0_3          : 4;
33496         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33497                                                                      RES0.
33498 
33499                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33500                                                                      translation, and the memory translation granule size.
33501                                                                  The AArch64 Virtual Memory System Architecture chapter
33502                                                                      describes how x is calculated.
33503                                                                  The value of x determines the required alignment of the
33504                                                                      translation table, which must be aligned to 22^(x)
33505                                                                      bytes.
33506 
33507                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33508                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33509                                                                      UNPREDICTABLE, and can be one of the following:
33510 
33511                                                                   Bits \<x-1:0\> are treated as if all the bits are zero. The
33512                                                                      value read back from those bits might be the value written or
33513                                                                      might be zero.
33514 
33515                                                                   The calculation of an address for a translation table walk
33516                                                                      using this register can be corrupted in those bits that are
33517                                                                      nonzero. */
33518         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33519                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33520                                                                  If the implementation has only 8 bits of ASID, then the upper
33521                                                                      8 bits of this field are RES0. */
33522 #endif /* Word 0 - End */
33523     } cn8;
33524     /* struct bdk_ap_ttbr0_el2_s cn9; */
33525 };
33526 typedef union bdk_ap_ttbr0_el2 bdk_ap_ttbr0_el2_t;
33527 
33528 #define BDK_AP_TTBR0_EL2 BDK_AP_TTBR0_EL2_FUNC()
33529 static inline uint64_t BDK_AP_TTBR0_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TTBR0_EL2_FUNC(void)33530 static inline uint64_t BDK_AP_TTBR0_EL2_FUNC(void)
33531 {
33532     return 0x30402000000ll;
33533 }
33534 
33535 #define typedef_BDK_AP_TTBR0_EL2 bdk_ap_ttbr0_el2_t
33536 #define bustype_BDK_AP_TTBR0_EL2 BDK_CSR_TYPE_SYSREG
33537 #define basename_BDK_AP_TTBR0_EL2 "AP_TTBR0_EL2"
33538 #define busnum_BDK_AP_TTBR0_EL2 0
33539 #define arguments_BDK_AP_TTBR0_EL2 -1,-1,-1,-1
33540 
33541 /**
33542  * Register (SYSREG) ap_ttbr0_el3
33543  *
33544  * AP Translation Table Base EL2-EL3 Register 0
33545  * Holds the base address of the translation table for the stage
33546  *     1 translation of memory accesses from EL3.
33547  */
33548 union bdk_ap_ttbr0_el3
33549 {
33550     uint64_t u;
33551     struct bdk_ap_ttbr0_el3_s
33552     {
33553 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33554         uint64_t reserved_48_63        : 16;
33555         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits[47:x]. Bits [x-1:0] are
33556                                                                      RES0.
33557 
33558                                                                  x is based on the value of TCR_EL*[T0SZ], the stage of
33559                                                                      translation, and the memory translation granule size.
33560                                                                  The AArch64 Virtual Memory System Architecture chapter
33561                                                                      describes how x is calculated.
33562                                                                  The value of x determines the required alignment of the
33563                                                                      translation table, which must be aligned to 22^(x)
33564                                                                      bytes.
33565 
33566                                                                  If bits [x-1:0] are not all zero, this is a misaligned
33567                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33568                                                                      UNPREDICTABLE, and can be one of the following:
33569 
33570                                                                   Bits [x-1:0] are treated as if all the bits are zero. The
33571                                                                      value read back from those bits might be the value written or
33572                                                                      might be zero.
33573 
33574                                                                   The calculation of an address for a translation table walk
33575                                                                      using this register can be corrupted in those bits that are
33576                                                                      nonzero. */
33577         uint64_t reserved_1_3          : 3;
33578         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
33579 #else /* Word 0 - Little Endian */
33580         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
33581         uint64_t reserved_1_3          : 3;
33582         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits[47:x]. Bits [x-1:0] are
33583                                                                      RES0.
33584 
33585                                                                  x is based on the value of TCR_EL*[T0SZ], the stage of
33586                                                                      translation, and the memory translation granule size.
33587                                                                  The AArch64 Virtual Memory System Architecture chapter
33588                                                                      describes how x is calculated.
33589                                                                  The value of x determines the required alignment of the
33590                                                                      translation table, which must be aligned to 22^(x)
33591                                                                      bytes.
33592 
33593                                                                  If bits [x-1:0] are not all zero, this is a misaligned
33594                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33595                                                                      UNPREDICTABLE, and can be one of the following:
33596 
33597                                                                   Bits [x-1:0] are treated as if all the bits are zero. The
33598                                                                      value read back from those bits might be the value written or
33599                                                                      might be zero.
33600 
33601                                                                   The calculation of an address for a translation table walk
33602                                                                      using this register can be corrupted in those bits that are
33603                                                                      nonzero. */
33604         uint64_t reserved_48_63        : 16;
33605 #endif /* Word 0 - End */
33606     } s;
33607     struct bdk_ap_ttbr0_el3_cn8
33608     {
33609 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33610         uint64_t reserved_48_63        : 16;
33611         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits[47:x]. Bits [x-1:0] are
33612                                                                      RES0.
33613 
33614                                                                  x is based on the value of TCR_EL*[T0SZ], the stage of
33615                                                                      translation, and the memory translation granule size.
33616                                                                  The AArch64 Virtual Memory System Architecture chapter
33617                                                                      describes how x is calculated.
33618                                                                  The value of x determines the required alignment of the
33619                                                                      translation table, which must be aligned to 22^(x)
33620                                                                      bytes.
33621 
33622                                                                  If bits [x-1:0] are not all zero, this is a misaligned
33623                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33624                                                                      UNPREDICTABLE, and can be one of the following:
33625 
33626                                                                   Bits [x-1:0] are treated as if all the bits are zero. The
33627                                                                      value read back from those bits might be the value written or
33628                                                                      might be zero.
33629 
33630                                                                   The calculation of an address for a translation table walk
33631                                                                      using this register can be corrupted in those bits that are
33632                                                                      nonzero. */
33633         uint64_t reserved_0_3          : 4;
33634 #else /* Word 0 - Little Endian */
33635         uint64_t reserved_0_3          : 4;
33636         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits[47:x]. Bits [x-1:0] are
33637                                                                      RES0.
33638 
33639                                                                  x is based on the value of TCR_EL*[T0SZ], the stage of
33640                                                                      translation, and the memory translation granule size.
33641                                                                  The AArch64 Virtual Memory System Architecture chapter
33642                                                                      describes how x is calculated.
33643                                                                  The value of x determines the required alignment of the
33644                                                                      translation table, which must be aligned to 22^(x)
33645                                                                      bytes.
33646 
33647                                                                  If bits [x-1:0] are not all zero, this is a misaligned
33648                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33649                                                                      UNPREDICTABLE, and can be one of the following:
33650 
33651                                                                   Bits [x-1:0] are treated as if all the bits are zero. The
33652                                                                      value read back from those bits might be the value written or
33653                                                                      might be zero.
33654 
33655                                                                   The calculation of an address for a translation table walk
33656                                                                      using this register can be corrupted in those bits that are
33657                                                                      nonzero. */
33658         uint64_t reserved_48_63        : 16;
33659 #endif /* Word 0 - End */
33660     } cn8;
33661     /* struct bdk_ap_ttbr0_el3_s cn9; */
33662 };
33663 typedef union bdk_ap_ttbr0_el3 bdk_ap_ttbr0_el3_t;
33664 
33665 #define BDK_AP_TTBR0_EL3 BDK_AP_TTBR0_EL3_FUNC()
33666 static inline uint64_t BDK_AP_TTBR0_EL3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TTBR0_EL3_FUNC(void)33667 static inline uint64_t BDK_AP_TTBR0_EL3_FUNC(void)
33668 {
33669     return 0x30602000000ll;
33670 }
33671 
33672 #define typedef_BDK_AP_TTBR0_EL3 bdk_ap_ttbr0_el3_t
33673 #define bustype_BDK_AP_TTBR0_EL3 BDK_CSR_TYPE_SYSREG
33674 #define basename_BDK_AP_TTBR0_EL3 "AP_TTBR0_EL3"
33675 #define busnum_BDK_AP_TTBR0_EL3 0
33676 #define arguments_BDK_AP_TTBR0_EL3 -1,-1,-1,-1
33677 
33678 /**
33679  * Register (SYSREG) ap_ttbr1_el1
33680  *
33681  * AP Translation Table Base Register 1
33682  * Holds the base address of translation table 1, and information
33683  *     about the memory it occupies. This is one of the translation
33684  *     tables for the stage 1 translation of memory accesses at EL0
33685  *     and EL1.
33686  */
33687 union bdk_ap_ttbr1_el1
33688 {
33689     uint64_t u;
33690     struct bdk_ap_ttbr1_el1_s
33691     {
33692 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33693         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33694                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33695                                                                  If the implementation has only 8 bits of ASID, then the upper
33696                                                                      8 bits of this field are RES0. */
33697         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33698                                                                      RES0.
33699 
33700                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33701                                                                      translation, and the memory translation granule size.
33702                                                                  The AArch64 Virtual Memory System Architecture chapter
33703                                                                      describes how x is calculated.
33704                                                                  The value of x determines the required alignment of the
33705                                                                      translation table, which must be aligned to 22^(x)
33706                                                                      bytes.
33707 
33708                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33709                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33710                                                                      UNPREDICTABLE, and can be one of the following:
33711 
33712                                                                  Bits \<x-1:0\> are treated as if all the bits are zero. The
33713                                                                      value read back from those bits might be the value written or
33714                                                                      might be zero.
33715 
33716                                                                   The calculation of an address for a translation table walk
33717                                                                      using this register can be corrupted in those bits that are
33718                                                                      nonzero. */
33719         uint64_t reserved_1_3          : 3;
33720         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
33721 #else /* Word 0 - Little Endian */
33722         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
33723         uint64_t reserved_1_3          : 3;
33724         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33725                                                                      RES0.
33726 
33727                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33728                                                                      translation, and the memory translation granule size.
33729                                                                  The AArch64 Virtual Memory System Architecture chapter
33730                                                                      describes how x is calculated.
33731                                                                  The value of x determines the required alignment of the
33732                                                                      translation table, which must be aligned to 22^(x)
33733                                                                      bytes.
33734 
33735                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33736                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33737                                                                      UNPREDICTABLE, and can be one of the following:
33738 
33739                                                                  Bits \<x-1:0\> are treated as if all the bits are zero. The
33740                                                                      value read back from those bits might be the value written or
33741                                                                      might be zero.
33742 
33743                                                                   The calculation of an address for a translation table walk
33744                                                                      using this register can be corrupted in those bits that are
33745                                                                      nonzero. */
33746         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33747                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33748                                                                  If the implementation has only 8 bits of ASID, then the upper
33749                                                                      8 bits of this field are RES0. */
33750 #endif /* Word 0 - End */
33751     } s;
33752     struct bdk_ap_ttbr1_el1_cn8
33753     {
33754 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33755         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33756                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33757                                                                  If the implementation has only 8 bits of ASID, then the upper
33758                                                                      8 bits of this field are RES0. */
33759         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33760                                                                      RES0.
33761 
33762                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33763                                                                      translation, and the memory translation granule size.
33764                                                                  The AArch64 Virtual Memory System Architecture chapter
33765                                                                      describes how x is calculated.
33766                                                                  The value of x determines the required alignment of the
33767                                                                      translation table, which must be aligned to 22^(x)
33768                                                                      bytes.
33769 
33770                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33771                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33772                                                                      UNPREDICTABLE, and can be one of the following:
33773 
33774                                                                  Bits \<x-1:0\> are treated as if all the bits are zero. The
33775                                                                      value read back from those bits might be the value written or
33776                                                                      might be zero.
33777 
33778                                                                   The calculation of an address for a translation table walk
33779                                                                      using this register can be corrupted in those bits that are
33780                                                                      nonzero. */
33781         uint64_t reserved_0_3          : 4;
33782 #else /* Word 0 - Little Endian */
33783         uint64_t reserved_0_3          : 4;
33784         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33785                                                                      RES0.
33786 
33787                                                                  x is based on the value of AP_TCR_EL1[T0SZ], the stage of
33788                                                                      translation, and the memory translation granule size.
33789                                                                  The AArch64 Virtual Memory System Architecture chapter
33790                                                                      describes how x is calculated.
33791                                                                  The value of x determines the required alignment of the
33792                                                                      translation table, which must be aligned to 22^(x)
33793                                                                      bytes.
33794 
33795                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33796                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33797                                                                      UNPREDICTABLE, and can be one of the following:
33798 
33799                                                                  Bits \<x-1:0\> are treated as if all the bits are zero. The
33800                                                                      value read back from those bits might be the value written or
33801                                                                      might be zero.
33802 
33803                                                                   The calculation of an address for a translation table walk
33804                                                                      using this register can be corrupted in those bits that are
33805                                                                      nonzero. */
33806         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL1[A1]
33807                                                                      field selects either AP_TTBR0_EL1[ASID] or AP_TTBR1_EL1[ASID].
33808                                                                  If the implementation has only 8 bits of ASID, then the upper
33809                                                                      8 bits of this field are RES0. */
33810 #endif /* Word 0 - End */
33811     } cn8;
33812     /* struct bdk_ap_ttbr1_el1_s cn9; */
33813 };
33814 typedef union bdk_ap_ttbr1_el1 bdk_ap_ttbr1_el1_t;
33815 
33816 #define BDK_AP_TTBR1_EL1 BDK_AP_TTBR1_EL1_FUNC()
33817 static inline uint64_t BDK_AP_TTBR1_EL1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TTBR1_EL1_FUNC(void)33818 static inline uint64_t BDK_AP_TTBR1_EL1_FUNC(void)
33819 {
33820     return 0x30002000100ll;
33821 }
33822 
33823 #define typedef_BDK_AP_TTBR1_EL1 bdk_ap_ttbr1_el1_t
33824 #define bustype_BDK_AP_TTBR1_EL1 BDK_CSR_TYPE_SYSREG
33825 #define basename_BDK_AP_TTBR1_EL1 "AP_TTBR1_EL1"
33826 #define busnum_BDK_AP_TTBR1_EL1 0
33827 #define arguments_BDK_AP_TTBR1_EL1 -1,-1,-1,-1
33828 
33829 /**
33830  * Register (SYSREG) ap_ttbr1_el12
33831  *
33832  * AP Translation Table Base Register 1
33833  * Alias of AP_TTBR1_EL1 from EL2 when AP_HCR_EL2[E2H] is set.
33834  */
33835 union bdk_ap_ttbr1_el12
33836 {
33837     uint64_t u;
33838     struct bdk_ap_ttbr1_el12_s
33839     {
33840 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33841         uint64_t reserved_0_63         : 64;
33842 #else /* Word 0 - Little Endian */
33843         uint64_t reserved_0_63         : 64;
33844 #endif /* Word 0 - End */
33845     } s;
33846     /* struct bdk_ap_ttbr1_el12_s cn; */
33847 };
33848 typedef union bdk_ap_ttbr1_el12 bdk_ap_ttbr1_el12_t;
33849 
33850 #define BDK_AP_TTBR1_EL12 BDK_AP_TTBR1_EL12_FUNC()
33851 static inline uint64_t BDK_AP_TTBR1_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TTBR1_EL12_FUNC(void)33852 static inline uint64_t BDK_AP_TTBR1_EL12_FUNC(void)
33853 {
33854     return 0x30502000100ll;
33855 }
33856 
33857 #define typedef_BDK_AP_TTBR1_EL12 bdk_ap_ttbr1_el12_t
33858 #define bustype_BDK_AP_TTBR1_EL12 BDK_CSR_TYPE_SYSREG
33859 #define basename_BDK_AP_TTBR1_EL12 "AP_TTBR1_EL12"
33860 #define busnum_BDK_AP_TTBR1_EL12 0
33861 #define arguments_BDK_AP_TTBR1_EL12 -1,-1,-1,-1
33862 
33863 /**
33864  * Register (SYSREG) ap_ttbr1_el2
33865  *
33866  * AP EL2 Translation Table Base (v8.1) Register 1
33867  * Holds the base address of translation table 1, and information
33868  *     about the memory it occupies. This is one of the translation
33869  *     tables for the stage 1 translation of memory accesses at EL2.
33870  */
33871 union bdk_ap_ttbr1_el2
33872 {
33873     uint64_t u;
33874     struct bdk_ap_ttbr1_el2_s
33875     {
33876 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33877         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL2[A1]
33878                                                                      field selects either AP_TTBR0_EL2[ASID] or AP_TTBR1_EL2[ASID].
33879                                                                  If the implementation has only 8 bits of ASID, then the upper
33880                                                                      8 bits of this field are RES0. */
33881         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33882                                                                      RES0.
33883 
33884                                                                  x is based on the value of AP_TCR_EL2[T0SZ], the stage of
33885                                                                      translation, and the memory translation granule size.
33886                                                                  The AArch64 Virtual Memory System Architecture chapter
33887                                                                      describes how x is calculated.
33888                                                                  The value of x determines the required alignment of the
33889                                                                      translation table, which must be aligned to 22^(x)
33890                                                                      bytes.
33891 
33892                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33893                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33894                                                                      UNPREDICTABLE, and can be one of the following:
33895 
33896                                                                   Bits \<x-1:0\> are treated as if all the bits are zero. The
33897                                                                      value read back from those bits might be the value written or
33898                                                                      might be zero.
33899 
33900                                                                   The calculation of an address for a translation table walk
33901                                                                      using this register can be corrupted in those bits that are
33902                                                                      nonzero. */
33903         uint64_t reserved_1_3          : 3;
33904         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
33905 #else /* Word 0 - Little Endian */
33906         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
33907         uint64_t reserved_1_3          : 3;
33908         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33909                                                                      RES0.
33910 
33911                                                                  x is based on the value of AP_TCR_EL2[T0SZ], the stage of
33912                                                                      translation, and the memory translation granule size.
33913                                                                  The AArch64 Virtual Memory System Architecture chapter
33914                                                                      describes how x is calculated.
33915                                                                  The value of x determines the required alignment of the
33916                                                                      translation table, which must be aligned to 22^(x)
33917                                                                      bytes.
33918 
33919                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33920                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33921                                                                      UNPREDICTABLE, and can be one of the following:
33922 
33923                                                                   Bits \<x-1:0\> are treated as if all the bits are zero. The
33924                                                                      value read back from those bits might be the value written or
33925                                                                      might be zero.
33926 
33927                                                                   The calculation of an address for a translation table walk
33928                                                                      using this register can be corrupted in those bits that are
33929                                                                      nonzero. */
33930         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL2[A1]
33931                                                                      field selects either AP_TTBR0_EL2[ASID] or AP_TTBR1_EL2[ASID].
33932                                                                  If the implementation has only 8 bits of ASID, then the upper
33933                                                                      8 bits of this field are RES0. */
33934 #endif /* Word 0 - End */
33935     } s;
33936     struct bdk_ap_ttbr1_el2_cn8
33937     {
33938 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
33939         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL2[A1]
33940                                                                      field selects either AP_TTBR0_EL2[ASID] or AP_TTBR1_EL2[ASID].
33941                                                                  If the implementation has only 8 bits of ASID, then the upper
33942                                                                      8 bits of this field are RES0. */
33943         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33944                                                                      RES0.
33945 
33946                                                                  x is based on the value of AP_TCR_EL2[T0SZ], the stage of
33947                                                                      translation, and the memory translation granule size.
33948                                                                  The AArch64 Virtual Memory System Architecture chapter
33949                                                                      describes how x is calculated.
33950                                                                  The value of x determines the required alignment of the
33951                                                                      translation table, which must be aligned to 22^(x)
33952                                                                      bytes.
33953 
33954                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33955                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33956                                                                      UNPREDICTABLE, and can be one of the following:
33957 
33958                                                                   Bits \<x-1:0\> are treated as if all the bits are zero. The
33959                                                                      value read back from those bits might be the value written or
33960                                                                      might be zero.
33961 
33962                                                                   The calculation of an address for a translation table walk
33963                                                                      using this register can be corrupted in those bits that are
33964                                                                      nonzero. */
33965         uint64_t reserved_0_3          : 4;
33966 #else /* Word 0 - Little Endian */
33967         uint64_t reserved_0_3          : 4;
33968         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
33969                                                                      RES0.
33970 
33971                                                                  x is based on the value of AP_TCR_EL2[T0SZ], the stage of
33972                                                                      translation, and the memory translation granule size.
33973                                                                  The AArch64 Virtual Memory System Architecture chapter
33974                                                                      describes how x is calculated.
33975                                                                  The value of x determines the required alignment of the
33976                                                                      translation table, which must be aligned to 22^(x)
33977                                                                      bytes.
33978 
33979                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
33980                                                                      Translation Table Base Address. Its effects are CONSTRAINED
33981                                                                      UNPREDICTABLE, and can be one of the following:
33982 
33983                                                                   Bits \<x-1:0\> are treated as if all the bits are zero. The
33984                                                                      value read back from those bits might be the value written or
33985                                                                      might be zero.
33986 
33987                                                                   The calculation of an address for a translation table walk
33988                                                                      using this register can be corrupted in those bits that are
33989                                                                      nonzero. */
33990         uint64_t asid                  : 16; /**< [ 63: 48](R/W) An ASID for the translation table base address. The AP_TCR_EL2[A1]
33991                                                                      field selects either AP_TTBR0_EL2[ASID] or AP_TTBR1_EL2[ASID].
33992                                                                  If the implementation has only 8 bits of ASID, then the upper
33993                                                                      8 bits of this field are RES0. */
33994 #endif /* Word 0 - End */
33995     } cn8;
33996     /* struct bdk_ap_ttbr1_el2_s cn9; */
33997 };
33998 typedef union bdk_ap_ttbr1_el2 bdk_ap_ttbr1_el2_t;
33999 
34000 #define BDK_AP_TTBR1_EL2 BDK_AP_TTBR1_EL2_FUNC()
34001 static inline uint64_t BDK_AP_TTBR1_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_TTBR1_EL2_FUNC(void)34002 static inline uint64_t BDK_AP_TTBR1_EL2_FUNC(void)
34003 {
34004     return 0x30402000100ll;
34005 }
34006 
34007 #define typedef_BDK_AP_TTBR1_EL2 bdk_ap_ttbr1_el2_t
34008 #define bustype_BDK_AP_TTBR1_EL2 BDK_CSR_TYPE_SYSREG
34009 #define basename_BDK_AP_TTBR1_EL2 "AP_TTBR1_EL2"
34010 #define busnum_BDK_AP_TTBR1_EL2 0
34011 #define arguments_BDK_AP_TTBR1_EL2 -1,-1,-1,-1
34012 
34013 /**
34014  * Register (SYSREG) ap_uao
34015  *
34016  * AP User Access Override Register
34017  * v8.2: User Access Override bit.
34018  *
34019  * When 0, The behaviour of LDTR* /STTR* instructions is as defined in the base
34020  * ARMv8 architecture.
34021  * When 1, LDTR* /STTR* instructions when executed at EL1, or at EL2 with
34022  * HCR_EL2.E2H==1 && HCR_EL2.TGE==1, behave as the equivalent LDR* /STR*
34023  * instructions.
34024  *
34025  * UAO is held in SPSR_ELx[23] and DSPSR_EL0[23].
34026  * PSTATE.UAO is copied to SPSR_ELx.UAO and is then set to 0 on an exception taken from AArch64
34027  * to AArch64
34028  * PSTATE.UAO is set to 0 on an exception taken from AArch32 to AArch64.
34029  * SPSR_ELx.UAO is set to 0 on an exception taken from AArch32 to AArch64
34030  * SPSR_ELx.UAO is copied to PSTATE.UAO on an exception return to AArch64 from AArch64
34031  * PSTATE.UAO is set to zero by a DCPS instruction to AArch64 in Debug state.
34032  * SPSR_ELx.UAO is copied to PSTATE.UAO by DRPS to AArch64 from AArch64 in Debug state.
34033  * DSPSR_EL0.UAO is copied to PSTATE.UAO on exit from Debug state to AArch64.
34034  * PSTATE.UAO is copied to DSPSR_EL0.UAO on entry to Debug state from AArch64
34035  *
34036  * Note, PSTATE.UAO is unchanged on entry into Debug state
34037  */
34038 union bdk_ap_uao
34039 {
34040     uint64_t u;
34041     struct bdk_ap_uao_s
34042     {
34043 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34044         uint64_t reserved_24_63        : 40;
34045         uint64_t uao                   : 1;  /**< [ 23: 23](R/W) User access override bit. */
34046         uint64_t reserved_0_22         : 23;
34047 #else /* Word 0 - Little Endian */
34048         uint64_t reserved_0_22         : 23;
34049         uint64_t uao                   : 1;  /**< [ 23: 23](R/W) User access override bit. */
34050         uint64_t reserved_24_63        : 40;
34051 #endif /* Word 0 - End */
34052     } s;
34053     /* struct bdk_ap_uao_s cn; */
34054 };
34055 typedef union bdk_ap_uao bdk_ap_uao_t;
34056 
34057 #define BDK_AP_UAO BDK_AP_UAO_FUNC()
34058 static inline uint64_t BDK_AP_UAO_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_UAO_FUNC(void)34059 static inline uint64_t BDK_AP_UAO_FUNC(void)
34060 {
34061     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
34062         return 0x30004020400ll;
34063     __bdk_csr_fatal("AP_UAO", 0, 0, 0, 0, 0);
34064 }
34065 
34066 #define typedef_BDK_AP_UAO bdk_ap_uao_t
34067 #define bustype_BDK_AP_UAO BDK_CSR_TYPE_SYSREG
34068 #define basename_BDK_AP_UAO "AP_UAO"
34069 #define busnum_BDK_AP_UAO 0
34070 #define arguments_BDK_AP_UAO -1,-1,-1,-1
34071 
34072 /**
34073  * Register (SYSREG) ap_vbar_el#
34074  *
34075  * AP Vector Base Address EL* Register
34076  * Holds the exception base address for any exception that is
34077  *     taken to EL*.
34078  */
34079 union bdk_ap_vbar_elx
34080 {
34081     uint64_t u;
34082     struct bdk_ap_vbar_elx_s
34083     {
34084 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34085         uint64_t data                  : 53; /**< [ 63: 11](R/W) Vector base address. Base address of the exception vectors for
34086                                                                      exceptions taken in EL*.
34087                                                                  If tagged addresses are being used, bits \<55:48\> of VBAR_EL*
34088                                                                      must be 0 or else the use of the vector address will result in
34089                                                                      a recursive exception.
34090 
34091                                                                  If tagged addresses are not being used, bits \<63:48\> of
34092                                                                      VBAR_EL* must be 0 or else the use of the vector address will
34093                                                                      result in a recursive exception. */
34094         uint64_t reserved_0_10         : 11;
34095 #else /* Word 0 - Little Endian */
34096         uint64_t reserved_0_10         : 11;
34097         uint64_t data                  : 53; /**< [ 63: 11](R/W) Vector base address. Base address of the exception vectors for
34098                                                                      exceptions taken in EL*.
34099                                                                  If tagged addresses are being used, bits \<55:48\> of VBAR_EL*
34100                                                                      must be 0 or else the use of the vector address will result in
34101                                                                      a recursive exception.
34102 
34103                                                                  If tagged addresses are not being used, bits \<63:48\> of
34104                                                                      VBAR_EL* must be 0 or else the use of the vector address will
34105                                                                      result in a recursive exception. */
34106 #endif /* Word 0 - End */
34107     } s;
34108     /* struct bdk_ap_vbar_elx_s cn; */
34109 };
34110 typedef union bdk_ap_vbar_elx bdk_ap_vbar_elx_t;
34111 
34112 static inline uint64_t BDK_AP_VBAR_ELX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_AP_VBAR_ELX(unsigned long a)34113 static inline uint64_t BDK_AP_VBAR_ELX(unsigned long a)
34114 {
34115     if ((a>=1)&&(a<=3))
34116         return 0x3000c000000ll + 0ll * ((a) & 0x3);
34117     __bdk_csr_fatal("AP_VBAR_ELX", 1, a, 0, 0, 0);
34118 }
34119 
34120 #define typedef_BDK_AP_VBAR_ELX(a) bdk_ap_vbar_elx_t
34121 #define bustype_BDK_AP_VBAR_ELX(a) BDK_CSR_TYPE_SYSREG
34122 #define basename_BDK_AP_VBAR_ELX(a) "AP_VBAR_ELX"
34123 #define busnum_BDK_AP_VBAR_ELX(a) (a)
34124 #define arguments_BDK_AP_VBAR_ELX(a) (a),-1,-1,-1
34125 
34126 /**
34127  * Register (SYSREG) ap_vbar_el12
34128  *
34129  * AP Vector Base Address EL1/2 Register
34130  * Alias of VBAR_EL1 when accessed at EL2/3 and AP_HCR_EL2[E2H] is set.
34131  */
34132 union bdk_ap_vbar_el12
34133 {
34134     uint64_t u;
34135     struct bdk_ap_vbar_el12_s
34136     {
34137 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34138         uint64_t reserved_0_63         : 64;
34139 #else /* Word 0 - Little Endian */
34140         uint64_t reserved_0_63         : 64;
34141 #endif /* Word 0 - End */
34142     } s;
34143     /* struct bdk_ap_vbar_el12_s cn; */
34144 };
34145 typedef union bdk_ap_vbar_el12 bdk_ap_vbar_el12_t;
34146 
34147 #define BDK_AP_VBAR_EL12 BDK_AP_VBAR_EL12_FUNC()
34148 static inline uint64_t BDK_AP_VBAR_EL12_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_VBAR_EL12_FUNC(void)34149 static inline uint64_t BDK_AP_VBAR_EL12_FUNC(void)
34150 {
34151     return 0x3050c000000ll;
34152 }
34153 
34154 #define typedef_BDK_AP_VBAR_EL12 bdk_ap_vbar_el12_t
34155 #define bustype_BDK_AP_VBAR_EL12 BDK_CSR_TYPE_SYSREG
34156 #define basename_BDK_AP_VBAR_EL12 "AP_VBAR_EL12"
34157 #define busnum_BDK_AP_VBAR_EL12 0
34158 #define arguments_BDK_AP_VBAR_EL12 -1,-1,-1,-1
34159 
34160 /**
34161  * Register (SYSREG) ap_vdisr_el2
34162  *
34163  * AP Virtual Deferred Interrupt Status Register
34164  * Records that a virtual SError interrupt has been consumed by an ESB instruction executed at
34165  * Nonsecure EL1.
34166  *
34167  * Usage constraints:
34168  *   VDISR_EL2 is UNDEFINED at EL1 and EL0.
34169  *   If EL1 is using AArch64 and HCR_EL2.AMO is set to 1, then direct reads and writes of
34170  * DISR_EL1 at Non-secure EL1 access VDISR_EL2.
34171  *   If EL1 is using AArch32 and HCR_EL2.AMO is set to 1, then direct reads and writes of DISR at
34172  * Nonsecure EL1 access VDISR_EL2.
34173  *   An indirect write to VDISR_EL2 made by an ESB instruction does not require an explicit
34174  * synchronization operation for the value written to be observed by a direct read of DISR_EL1 or
34175  * DISR occurring in program order after the ESB.
34176  */
34177 union bdk_ap_vdisr_el2
34178 {
34179     uint64_t u;
34180     struct bdk_ap_vdisr_el2_s
34181     {
34182 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34183         uint64_t reserved_32_63        : 32;
34184         uint64_t aa                    : 1;  /**< [ 31: 31](R/W) Set to 1 when ESB defers a virtual SError interrupt. */
34185         uint64_t reserved_25_30        : 6;
34186         uint64_t ids                   : 1;  /**< [ 24: 24](R/W) Contains the value from AP_VSESR_EL2[IDS]. */
34187         uint64_t iss                   : 24; /**< [ 23:  0](R/W) Contains the value from VSESR_EL2[23:0]. */
34188 #else /* Word 0 - Little Endian */
34189         uint64_t iss                   : 24; /**< [ 23:  0](R/W) Contains the value from VSESR_EL2[23:0]. */
34190         uint64_t ids                   : 1;  /**< [ 24: 24](R/W) Contains the value from AP_VSESR_EL2[IDS]. */
34191         uint64_t reserved_25_30        : 6;
34192         uint64_t aa                    : 1;  /**< [ 31: 31](R/W) Set to 1 when ESB defers a virtual SError interrupt. */
34193         uint64_t reserved_32_63        : 32;
34194 #endif /* Word 0 - End */
34195     } s;
34196     /* struct bdk_ap_vdisr_el2_s cn; */
34197 };
34198 typedef union bdk_ap_vdisr_el2 bdk_ap_vdisr_el2_t;
34199 
34200 #define BDK_AP_VDISR_EL2 BDK_AP_VDISR_EL2_FUNC()
34201 static inline uint64_t BDK_AP_VDISR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_VDISR_EL2_FUNC(void)34202 static inline uint64_t BDK_AP_VDISR_EL2_FUNC(void)
34203 {
34204     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
34205         return 0x3040c010100ll;
34206     __bdk_csr_fatal("AP_VDISR_EL2", 0, 0, 0, 0, 0);
34207 }
34208 
34209 #define typedef_BDK_AP_VDISR_EL2 bdk_ap_vdisr_el2_t
34210 #define bustype_BDK_AP_VDISR_EL2 BDK_CSR_TYPE_SYSREG
34211 #define basename_BDK_AP_VDISR_EL2 "AP_VDISR_EL2"
34212 #define busnum_BDK_AP_VDISR_EL2 0
34213 #define arguments_BDK_AP_VDISR_EL2 -1,-1,-1,-1
34214 
34215 /**
34216  * Register (SYSREG) ap_vmpidr_el2
34217  *
34218  * AP Virtualization Multiprocessor ID Register
34219  * Holds the value of the Virtualization Multiprocessor ID. This
34220  *     is the value returned by nonsecure EL1 reads of AP_MPIDR_EL1.
34221  */
34222 union bdk_ap_vmpidr_el2
34223 {
34224     uint64_t u;
34225     struct bdk_ap_vmpidr_el2_s
34226     {
34227 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34228         uint64_t reserved_40_63        : 24;
34229         uint64_t aff3                  : 8;  /**< [ 39: 32](R/W) Affinity level 3. Highest level affinity field. */
34230         uint64_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
34231         uint64_t u                     : 1;  /**< [ 30: 30](R/W) Indicates a Uniprocessor system, as distinct from PE 0 in a
34232                                                                      multiprocessor system.
34233                                                                  0 = Processor is part of a multiprocessor system.
34234                                                                  1 = Processor is part of a uniprocessor system. */
34235         uint64_t reserved_25_29        : 5;
34236         uint64_t mt                    : 1;  /**< [ 24: 24](R/W) Indicates whether the lowest level of affinity consists of
34237                                                                      logical PEs that are implemented using a multi-threading type
34238                                                                      approach.
34239                                                                  0 = Performance of PEs at the lowest affinity level is largely
34240                                                                      independent.
34241                                                                  1 = Performance of PEs at the lowest affinity level is very
34242                                                                      interdependent. */
34243         uint64_t aff2                  : 8;  /**< [ 23: 16](R/W) Affinity level 2. Second highest level affinity field. */
34244         uint64_t aff1                  : 8;  /**< [ 15:  8](R/W) Affinity level 1. Third highest level affinity field. */
34245         uint64_t aff0                  : 8;  /**< [  7:  0](R/W) Affinity level 0. Lowest level affinity field. */
34246 #else /* Word 0 - Little Endian */
34247         uint64_t aff0                  : 8;  /**< [  7:  0](R/W) Affinity level 0. Lowest level affinity field. */
34248         uint64_t aff1                  : 8;  /**< [ 15:  8](R/W) Affinity level 1. Third highest level affinity field. */
34249         uint64_t aff2                  : 8;  /**< [ 23: 16](R/W) Affinity level 2. Second highest level affinity field. */
34250         uint64_t mt                    : 1;  /**< [ 24: 24](R/W) Indicates whether the lowest level of affinity consists of
34251                                                                      logical PEs that are implemented using a multi-threading type
34252                                                                      approach.
34253                                                                  0 = Performance of PEs at the lowest affinity level is largely
34254                                                                      independent.
34255                                                                  1 = Performance of PEs at the lowest affinity level is very
34256                                                                      interdependent. */
34257         uint64_t reserved_25_29        : 5;
34258         uint64_t u                     : 1;  /**< [ 30: 30](R/W) Indicates a Uniprocessor system, as distinct from PE 0 in a
34259                                                                      multiprocessor system.
34260                                                                  0 = Processor is part of a multiprocessor system.
34261                                                                  1 = Processor is part of a uniprocessor system. */
34262         uint64_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
34263         uint64_t aff3                  : 8;  /**< [ 39: 32](R/W) Affinity level 3. Highest level affinity field. */
34264         uint64_t reserved_40_63        : 24;
34265 #endif /* Word 0 - End */
34266     } s;
34267     /* struct bdk_ap_vmpidr_el2_s cn; */
34268 };
34269 typedef union bdk_ap_vmpidr_el2 bdk_ap_vmpidr_el2_t;
34270 
34271 #define BDK_AP_VMPIDR_EL2 BDK_AP_VMPIDR_EL2_FUNC()
34272 static inline uint64_t BDK_AP_VMPIDR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_VMPIDR_EL2_FUNC(void)34273 static inline uint64_t BDK_AP_VMPIDR_EL2_FUNC(void)
34274 {
34275     return 0x30400000500ll;
34276 }
34277 
34278 #define typedef_BDK_AP_VMPIDR_EL2 bdk_ap_vmpidr_el2_t
34279 #define bustype_BDK_AP_VMPIDR_EL2 BDK_CSR_TYPE_SYSREG
34280 #define basename_BDK_AP_VMPIDR_EL2 "AP_VMPIDR_EL2"
34281 #define busnum_BDK_AP_VMPIDR_EL2 0
34282 #define arguments_BDK_AP_VMPIDR_EL2 -1,-1,-1,-1
34283 
34284 /**
34285  * Register (SYSREG) ap_vpidr_el2
34286  *
34287  * AP Virtualization Processor ID Register
34288  * Holds the value of the Virtualization Processor ID. This is
34289  *     the value returned by nonsecure EL1 reads of AP_MIDR_EL1.
34290  */
34291 union bdk_ap_vpidr_el2
34292 {
34293     uint32_t u;
34294     struct bdk_ap_vpidr_el2_s
34295     {
34296 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34297         uint32_t implementer           : 8;  /**< [ 31: 24](R/W) The implementer code. This field must hold an implementer code
34298                                                                      that has been assigned by ARM.
34299                                                                  Hex representation  ASCII representation.
34300                                                                  0x41 = 'A' = ARM Limited.
34301                                                                  0x42 = 'B' = Broadcom Corporation.
34302                                                                  0x43 = 'C' = Cavium Inc.
34303                                                                  0x44 = 'D' = Digital Equipment Corporation.
34304                                                                  0x49 = 'I' = Infineon Technologies AG.
34305                                                                  0x4D = 'M' = Motorola or Freescale Semiconductor Inc.
34306                                                                  0x4E = 'N' = NVIDIA Corporation.
34307                                                                  0x50 = 'P' = Applied Micro Circuits Corporation.
34308                                                                  0x51 = 'Q' = Qualcomm Inc.
34309                                                                  0x56 = 'V' = Marvell International Ltd.
34310                                                                  0x69 = 'i' = Intel Corporation.
34311 
34312                                                                  ARM can assign codes that are not published in this manual.
34313                                                                      All values not assigned by ARM are reserved and must not be
34314                                                                      used. */
34315         uint32_t variant               : 4;  /**< [ 23: 20](R/W) An implementation defined variant number. Typically, this
34316                                                                      field is used to distinguish between different product
34317                                                                      variants, or major revisions of a product. */
34318         uint32_t architecture          : 4;  /**< [ 19: 16](R/W) Architecture:
34319                                                                  0x1 = ARMv4.
34320                                                                  0x2 = ARMv4T.
34321                                                                  0x3 = ARMv5 (obsolete).
34322                                                                  0x4 = ARMv5T.
34323                                                                  0x5 = ARMv5TE.
34324                                                                  0x6 = ARMv5TEJ.
34325                                                                  0x7 = ARMv6.
34326                                                                  0xF = Defined by CPUID scheme.
34327                                                                  _ All other values are reserved. */
34328         uint32_t partnum               : 12; /**< [ 15:  4](R/W) An implementation defined primary part number for the device.
34329                                                                  On processors implemented by ARM, if the top four bits of the
34330                                                                      primary part number are 0x00x7. */
34331         uint32_t revision              : 4;  /**< [  3:  0](R/W) An implementation defined revision number for the device. */
34332 #else /* Word 0 - Little Endian */
34333         uint32_t revision              : 4;  /**< [  3:  0](R/W) An implementation defined revision number for the device. */
34334         uint32_t partnum               : 12; /**< [ 15:  4](R/W) An implementation defined primary part number for the device.
34335                                                                  On processors implemented by ARM, if the top four bits of the
34336                                                                      primary part number are 0x00x7. */
34337         uint32_t architecture          : 4;  /**< [ 19: 16](R/W) Architecture:
34338                                                                  0x1 = ARMv4.
34339                                                                  0x2 = ARMv4T.
34340                                                                  0x3 = ARMv5 (obsolete).
34341                                                                  0x4 = ARMv5T.
34342                                                                  0x5 = ARMv5TE.
34343                                                                  0x6 = ARMv5TEJ.
34344                                                                  0x7 = ARMv6.
34345                                                                  0xF = Defined by CPUID scheme.
34346                                                                  _ All other values are reserved. */
34347         uint32_t variant               : 4;  /**< [ 23: 20](R/W) An implementation defined variant number. Typically, this
34348                                                                      field is used to distinguish between different product
34349                                                                      variants, or major revisions of a product. */
34350         uint32_t implementer           : 8;  /**< [ 31: 24](R/W) The implementer code. This field must hold an implementer code
34351                                                                      that has been assigned by ARM.
34352                                                                  Hex representation  ASCII representation.
34353                                                                  0x41 = 'A' = ARM Limited.
34354                                                                  0x42 = 'B' = Broadcom Corporation.
34355                                                                  0x43 = 'C' = Cavium Inc.
34356                                                                  0x44 = 'D' = Digital Equipment Corporation.
34357                                                                  0x49 = 'I' = Infineon Technologies AG.
34358                                                                  0x4D = 'M' = Motorola or Freescale Semiconductor Inc.
34359                                                                  0x4E = 'N' = NVIDIA Corporation.
34360                                                                  0x50 = 'P' = Applied Micro Circuits Corporation.
34361                                                                  0x51 = 'Q' = Qualcomm Inc.
34362                                                                  0x56 = 'V' = Marvell International Ltd.
34363                                                                  0x69 = 'i' = Intel Corporation.
34364 
34365                                                                  ARM can assign codes that are not published in this manual.
34366                                                                      All values not assigned by ARM are reserved and must not be
34367                                                                      used. */
34368 #endif /* Word 0 - End */
34369     } s;
34370     /* struct bdk_ap_vpidr_el2_s cn; */
34371 };
34372 typedef union bdk_ap_vpidr_el2 bdk_ap_vpidr_el2_t;
34373 
34374 #define BDK_AP_VPIDR_EL2 BDK_AP_VPIDR_EL2_FUNC()
34375 static inline uint64_t BDK_AP_VPIDR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_VPIDR_EL2_FUNC(void)34376 static inline uint64_t BDK_AP_VPIDR_EL2_FUNC(void)
34377 {
34378     return 0x30400000000ll;
34379 }
34380 
34381 #define typedef_BDK_AP_VPIDR_EL2 bdk_ap_vpidr_el2_t
34382 #define bustype_BDK_AP_VPIDR_EL2 BDK_CSR_TYPE_SYSREG
34383 #define basename_BDK_AP_VPIDR_EL2 "AP_VPIDR_EL2"
34384 #define busnum_BDK_AP_VPIDR_EL2 0
34385 #define arguments_BDK_AP_VPIDR_EL2 -1,-1,-1,-1
34386 
34387 /**
34388  * Register (SYSREG) ap_vsesr_el2
34389  *
34390  * AP Virtual SError Exception Syndrome Register
34391  * Provides the syndrome value reported to software on taking a virtual SError interrupt
34392  * exception:
34393  *   - If the virtual SError interrupt is taken to EL1 using AArch64, VSESR_EL2 provides the
34394  * syndrome value reported in ESR_EL1.
34395  *   - If the virtual SError interrupt is taken to EL1 using AArch32, VSESR_EL2 provides the
34396  * syndrome values reported in DFSR.{AET, ExT} and the remainder of the DFSR is set as defined by
34397  * VMSAv8-32.
34398  *
34399  * Usage constraints:
34400  *   VSESR_EL2 is UNDEFINED at EL1 and EL0.
34401  */
34402 union bdk_ap_vsesr_el2
34403 {
34404     uint64_t u;
34405     struct bdk_ap_vsesr_el2_s
34406     {
34407 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34408         uint64_t reserved_25_63        : 39;
34409         uint64_t ids                   : 1;  /**< [ 24: 24](R/W) On taking a virtual SError interrupt to EL1 using AArch64 due to AP_HCR_EL2[VSE] == 1,
34410                                                                  AP_ESR_EL1[24] is set to AP_VSESR_EL2[IDS]. */
34411         uint64_t iss                   : 24; /**< [ 23:  0](RAZ) On taking a virtual SError interrupt to EL1 using AArch64 due to AP_HCR_EL2[VSE] == 1,
34412                                                                  AP_ESR_EL1[23:0] is set to AP_VSESR_EL2[ISS]. */
34413 #else /* Word 0 - Little Endian */
34414         uint64_t iss                   : 24; /**< [ 23:  0](RAZ) On taking a virtual SError interrupt to EL1 using AArch64 due to AP_HCR_EL2[VSE] == 1,
34415                                                                  AP_ESR_EL1[23:0] is set to AP_VSESR_EL2[ISS]. */
34416         uint64_t ids                   : 1;  /**< [ 24: 24](R/W) On taking a virtual SError interrupt to EL1 using AArch64 due to AP_HCR_EL2[VSE] == 1,
34417                                                                  AP_ESR_EL1[24] is set to AP_VSESR_EL2[IDS]. */
34418         uint64_t reserved_25_63        : 39;
34419 #endif /* Word 0 - End */
34420     } s;
34421     /* struct bdk_ap_vsesr_el2_s cn; */
34422 };
34423 typedef union bdk_ap_vsesr_el2 bdk_ap_vsesr_el2_t;
34424 
34425 #define BDK_AP_VSESR_EL2 BDK_AP_VSESR_EL2_FUNC()
34426 static inline uint64_t BDK_AP_VSESR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_VSESR_EL2_FUNC(void)34427 static inline uint64_t BDK_AP_VSESR_EL2_FUNC(void)
34428 {
34429     if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
34430         return 0x30405020300ll;
34431     __bdk_csr_fatal("AP_VSESR_EL2", 0, 0, 0, 0, 0);
34432 }
34433 
34434 #define typedef_BDK_AP_VSESR_EL2 bdk_ap_vsesr_el2_t
34435 #define bustype_BDK_AP_VSESR_EL2 BDK_CSR_TYPE_SYSREG
34436 #define basename_BDK_AP_VSESR_EL2 "AP_VSESR_EL2"
34437 #define busnum_BDK_AP_VSESR_EL2 0
34438 #define arguments_BDK_AP_VSESR_EL2 -1,-1,-1,-1
34439 
34440 /**
34441  * Register (SYSREG) ap_vtcr_el2
34442  *
34443  * AP Virtualization Translation Control Register
34444  * Controls the translation table walks required for the stage 2
34445  *     translation of memory accesses from nonsecure EL0 and EL1,
34446  *     and holds cacheability and shareability information for the
34447  *     accesses.
34448  */
34449 union bdk_ap_vtcr_el2
34450 {
34451     uint32_t u;
34452     struct bdk_ap_vtcr_el2_s
34453     {
34454 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34455         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
34456         uint32_t reserved_20_30        : 11;
34457         uint32_t vs                    : 1;  /**< [ 19: 19](R/W) VMID size.
34458                                                                  0 = 8 bits.
34459                                                                  1 = 16 bits. */
34460         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
34461 
34462                                                                  0x0 = 32 bits, 4GB.
34463                                                                  0x1 = 36 bits, 64GB.
34464                                                                  0x2 = 40 bits, 1TB.
34465                                                                  0x3 = 42 bits, 4TB.
34466                                                                  0x4 = 44 bits, 16TB.
34467                                                                  0x5 = 48 bits, 256TB. */
34468         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
34469                                                                      address register.
34470 
34471                                                                  If the value is programmed to either a reserved value, or a
34472                                                                      size that has not been implemented, then the hardware will
34473                                                                      treat the field as if it has been programmed to an
34474                                                                      implementation defined choice of the sizes that has been
34475                                                                      implemented for all purposes other than the value read back
34476                                                                      from this register.
34477 
34478                                                                  It is implementation defined whether the value read back is
34479                                                                      the value programmed or the value that corresponds to the size
34480                                                                      chosen.
34481 
34482                                                                  0x0 = 4 KB.
34483                                                                  0x1 = 64 KB.
34484                                                                  0x2 = 16 KB. */
34485         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
34486                                                                      table walks using AP_VTTBR_EL2.
34487                                                                  0x0 = Non-shareable.
34488                                                                  0x2 = Outer shareable.
34489                                                                  0x3 = Inner shareable. */
34490         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
34491                                                                      translation table walks using AP_VTTBR_EL2.
34492                                                                  0x0 = Normal memory, outer non-cacheable.
34493                                                                  0x1 = Normal memory, outer write-back write-allocate cacheable.
34494                                                                  0x2 = Normal memory, outer write-through cacheable.
34495                                                                  0x3 = Normal memory, outer write-back no write-allocate cacheable. */
34496         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
34497                                                                      translation table walks using AP_VTTBR_EL2.
34498                                                                  0x0 = Normal memory, inner non-cacheable
34499                                                                  0x1 = Normal memory, inner write-back write-allocate cacheable
34500                                                                  0x2 = Normal memory, inner write-through cacheable
34501                                                                  0x3 = Normal memory, inner write-back no write-allocate cacheable */
34502         uint32_t sl0                   : 2;  /**< [  7:  6](R/W) Starting level of the AP_VTCR_EL2 addressed region. The meaning
34503                                                                      of this field depends on the value of AP_VTCR_EL2[TG0] (the
34504                                                                      granule size). */
34505         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_VTTBR_EL2.
34506                                                                      The region size is 22^(64-T0SZ) bytes.
34507                                                                  The maximum and minimum possible values for T0SZ depend on the
34508                                                                      level of translation table and the memory translation granule
34509                                                                      size, as described in the AArch64 Virtual Memory System
34510                                                                      Architecture chapter. */
34511 #else /* Word 0 - Little Endian */
34512         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_VTTBR_EL2.
34513                                                                      The region size is 22^(64-T0SZ) bytes.
34514                                                                  The maximum and minimum possible values for T0SZ depend on the
34515                                                                      level of translation table and the memory translation granule
34516                                                                      size, as described in the AArch64 Virtual Memory System
34517                                                                      Architecture chapter. */
34518         uint32_t sl0                   : 2;  /**< [  7:  6](R/W) Starting level of the AP_VTCR_EL2 addressed region. The meaning
34519                                                                      of this field depends on the value of AP_VTCR_EL2[TG0] (the
34520                                                                      granule size). */
34521         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
34522                                                                      translation table walks using AP_VTTBR_EL2.
34523                                                                  0x0 = Normal memory, inner non-cacheable
34524                                                                  0x1 = Normal memory, inner write-back write-allocate cacheable
34525                                                                  0x2 = Normal memory, inner write-through cacheable
34526                                                                  0x3 = Normal memory, inner write-back no write-allocate cacheable */
34527         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
34528                                                                      translation table walks using AP_VTTBR_EL2.
34529                                                                  0x0 = Normal memory, outer non-cacheable.
34530                                                                  0x1 = Normal memory, outer write-back write-allocate cacheable.
34531                                                                  0x2 = Normal memory, outer write-through cacheable.
34532                                                                  0x3 = Normal memory, outer write-back no write-allocate cacheable. */
34533         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
34534                                                                      table walks using AP_VTTBR_EL2.
34535                                                                  0x0 = Non-shareable.
34536                                                                  0x2 = Outer shareable.
34537                                                                  0x3 = Inner shareable. */
34538         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
34539                                                                      address register.
34540 
34541                                                                  If the value is programmed to either a reserved value, or a
34542                                                                      size that has not been implemented, then the hardware will
34543                                                                      treat the field as if it has been programmed to an
34544                                                                      implementation defined choice of the sizes that has been
34545                                                                      implemented for all purposes other than the value read back
34546                                                                      from this register.
34547 
34548                                                                  It is implementation defined whether the value read back is
34549                                                                      the value programmed or the value that corresponds to the size
34550                                                                      chosen.
34551 
34552                                                                  0x0 = 4 KB.
34553                                                                  0x1 = 64 KB.
34554                                                                  0x2 = 16 KB. */
34555         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
34556 
34557                                                                  0x0 = 32 bits, 4GB.
34558                                                                  0x1 = 36 bits, 64GB.
34559                                                                  0x2 = 40 bits, 1TB.
34560                                                                  0x3 = 42 bits, 4TB.
34561                                                                  0x4 = 44 bits, 16TB.
34562                                                                  0x5 = 48 bits, 256TB. */
34563         uint32_t vs                    : 1;  /**< [ 19: 19](R/W) VMID size.
34564                                                                  0 = 8 bits.
34565                                                                  1 = 16 bits. */
34566         uint32_t reserved_20_30        : 11;
34567         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
34568 #endif /* Word 0 - End */
34569     } s;
34570     struct bdk_ap_vtcr_el2_cn
34571     {
34572 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34573         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
34574         uint32_t reserved_23_30        : 8;
34575         uint32_t reserved_22           : 1;
34576         uint32_t reserved_21           : 1;
34577         uint32_t reserved_20           : 1;
34578         uint32_t vs                    : 1;  /**< [ 19: 19](R/W) VMID size.
34579                                                                  0 = 8 bits.
34580                                                                  1 = 16 bits. */
34581         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
34582 
34583                                                                  0x0 = 32 bits, 4GB.
34584                                                                  0x1 = 36 bits, 64GB.
34585                                                                  0x2 = 40 bits, 1TB.
34586                                                                  0x3 = 42 bits, 4TB.
34587                                                                  0x4 = 44 bits, 16TB.
34588                                                                  0x5 = 48 bits, 256TB. */
34589         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
34590                                                                      address register.
34591 
34592                                                                  If the value is programmed to either a reserved value, or a
34593                                                                      size that has not been implemented, then the hardware will
34594                                                                      treat the field as if it has been programmed to an
34595                                                                      implementation defined choice of the sizes that has been
34596                                                                      implemented for all purposes other than the value read back
34597                                                                      from this register.
34598 
34599                                                                  It is implementation defined whether the value read back is
34600                                                                      the value programmed or the value that corresponds to the size
34601                                                                      chosen.
34602 
34603                                                                  0x0 = 4 KB.
34604                                                                  0x1 = 64 KB.
34605                                                                  0x2 = 16 KB. */
34606         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
34607                                                                      table walks using AP_VTTBR_EL2.
34608                                                                  0x0 = Non-shareable.
34609                                                                  0x2 = Outer shareable.
34610                                                                  0x3 = Inner shareable. */
34611         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
34612                                                                      translation table walks using AP_VTTBR_EL2.
34613                                                                  0x0 = Normal memory, outer non-cacheable.
34614                                                                  0x1 = Normal memory, outer write-back write-allocate cacheable.
34615                                                                  0x2 = Normal memory, outer write-through cacheable.
34616                                                                  0x3 = Normal memory, outer write-back no write-allocate cacheable. */
34617         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
34618                                                                      translation table walks using AP_VTTBR_EL2.
34619                                                                  0x0 = Normal memory, inner non-cacheable
34620                                                                  0x1 = Normal memory, inner write-back write-allocate cacheable
34621                                                                  0x2 = Normal memory, inner write-through cacheable
34622                                                                  0x3 = Normal memory, inner write-back no write-allocate cacheable */
34623         uint32_t sl0                   : 2;  /**< [  7:  6](R/W) Starting level of the AP_VTCR_EL2 addressed region. The meaning
34624                                                                      of this field depends on the value of AP_VTCR_EL2[TG0] (the
34625                                                                      granule size). */
34626         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_VTTBR_EL2.
34627                                                                      The region size is 22^(64-T0SZ) bytes.
34628                                                                  The maximum and minimum possible values for T0SZ depend on the
34629                                                                      level of translation table and the memory translation granule
34630                                                                      size, as described in the AArch64 Virtual Memory System
34631                                                                      Architecture chapter. */
34632 #else /* Word 0 - Little Endian */
34633         uint32_t t0sz                  : 6;  /**< [  5:  0](R/W) The size offset of the memory region addressed by AP_VTTBR_EL2.
34634                                                                      The region size is 22^(64-T0SZ) bytes.
34635                                                                  The maximum and minimum possible values for T0SZ depend on the
34636                                                                      level of translation table and the memory translation granule
34637                                                                      size, as described in the AArch64 Virtual Memory System
34638                                                                      Architecture chapter. */
34639         uint32_t sl0                   : 2;  /**< [  7:  6](R/W) Starting level of the AP_VTCR_EL2 addressed region. The meaning
34640                                                                      of this field depends on the value of AP_VTCR_EL2[TG0] (the
34641                                                                      granule size). */
34642         uint32_t irgn0                 : 2;  /**< [  9:  8](R/W) Inner cacheability attribute for memory associated with
34643                                                                      translation table walks using AP_VTTBR_EL2.
34644                                                                  0x0 = Normal memory, inner non-cacheable
34645                                                                  0x1 = Normal memory, inner write-back write-allocate cacheable
34646                                                                  0x2 = Normal memory, inner write-through cacheable
34647                                                                  0x3 = Normal memory, inner write-back no write-allocate cacheable */
34648         uint32_t orgn0                 : 2;  /**< [ 11: 10](R/W) Outer cacheability attribute for memory associated with
34649                                                                      translation table walks using AP_VTTBR_EL2.
34650                                                                  0x0 = Normal memory, outer non-cacheable.
34651                                                                  0x1 = Normal memory, outer write-back write-allocate cacheable.
34652                                                                  0x2 = Normal memory, outer write-through cacheable.
34653                                                                  0x3 = Normal memory, outer write-back no write-allocate cacheable. */
34654         uint32_t sh0                   : 2;  /**< [ 13: 12](R/W) Shareability attribute for memory associated with translation
34655                                                                      table walks using AP_VTTBR_EL2.
34656                                                                  0x0 = Non-shareable.
34657                                                                  0x2 = Outer shareable.
34658                                                                  0x3 = Inner shareable. */
34659         uint32_t tg0                   : 2;  /**< [ 15: 14](R/W) Granule size for the corresponding translation table base
34660                                                                      address register.
34661 
34662                                                                  If the value is programmed to either a reserved value, or a
34663                                                                      size that has not been implemented, then the hardware will
34664                                                                      treat the field as if it has been programmed to an
34665                                                                      implementation defined choice of the sizes that has been
34666                                                                      implemented for all purposes other than the value read back
34667                                                                      from this register.
34668 
34669                                                                  It is implementation defined whether the value read back is
34670                                                                      the value programmed or the value that corresponds to the size
34671                                                                      chosen.
34672 
34673                                                                  0x0 = 4 KB.
34674                                                                  0x1 = 64 KB.
34675                                                                  0x2 = 16 KB. */
34676         uint32_t ps                    : 3;  /**< [ 18: 16](R/W) Physical Address Size.
34677 
34678                                                                  0x0 = 32 bits, 4GB.
34679                                                                  0x1 = 36 bits, 64GB.
34680                                                                  0x2 = 40 bits, 1TB.
34681                                                                  0x3 = 42 bits, 4TB.
34682                                                                  0x4 = 44 bits, 16TB.
34683                                                                  0x5 = 48 bits, 256TB. */
34684         uint32_t vs                    : 1;  /**< [ 19: 19](R/W) VMID size.
34685                                                                  0 = 8 bits.
34686                                                                  1 = 16 bits. */
34687         uint32_t reserved_20           : 1;
34688         uint32_t reserved_21           : 1;
34689         uint32_t reserved_22           : 1;
34690         uint32_t reserved_23_30        : 8;
34691         uint32_t rsvd_31               : 1;  /**< [ 31: 31](RO) Reserved 1. */
34692 #endif /* Word 0 - End */
34693     } cn;
34694 };
34695 typedef union bdk_ap_vtcr_el2 bdk_ap_vtcr_el2_t;
34696 
34697 #define BDK_AP_VTCR_EL2 BDK_AP_VTCR_EL2_FUNC()
34698 static inline uint64_t BDK_AP_VTCR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_VTCR_EL2_FUNC(void)34699 static inline uint64_t BDK_AP_VTCR_EL2_FUNC(void)
34700 {
34701     return 0x30402010200ll;
34702 }
34703 
34704 #define typedef_BDK_AP_VTCR_EL2 bdk_ap_vtcr_el2_t
34705 #define bustype_BDK_AP_VTCR_EL2 BDK_CSR_TYPE_SYSREG
34706 #define basename_BDK_AP_VTCR_EL2 "AP_VTCR_EL2"
34707 #define busnum_BDK_AP_VTCR_EL2 0
34708 #define arguments_BDK_AP_VTCR_EL2 -1,-1,-1,-1
34709 
34710 /**
34711  * Register (SYSREG) ap_vttbr_el2
34712  *
34713  * AP Virtualization Translation Table Base Register
34714  * Holds the base address of the translation table for the stage
34715  *     2 translation of memory accesses from nonsecure EL0 and EL1.
34716  */
34717 union bdk_ap_vttbr_el2
34718 {
34719     uint64_t u;
34720     struct bdk_ap_vttbr_el2_s
34721     {
34722 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34723         uint64_t vmid                  : 16; /**< [ 63: 48](R/W) The VMID for the translation table. Expanded to 16 bits
34724                                                                  by the ARM Large System Extensions. */
34725         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
34726                                                                      RES0.
34727 
34728                                                                  x is based on the value of AP_VTCR_EL2[T0SZ], the stage of
34729                                                                      translation, and the memory translation granule size.
34730                                                                  The AArch64 Virtual Memory System Architecture chapter
34731                                                                      describes how x is calculated.
34732                                                                  The value of x determines the required alignment of the
34733                                                                      translation table, which must be aligned to 22^(x)
34734                                                                      bytes.
34735 
34736                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
34737                                                                      Translation Table Base Address. Its effects are CONSTRAINED
34738                                                                      UNPREDICTABLE, and can be one of the following:
34739 
34740                                                                  Bits \<x-1:0\> are treated as if all the bits are zero. The
34741                                                                      value read back from those bits might be the value written or
34742                                                                      might be zero.
34743 
34744                                                                  The calculation of an address for a translation table walk
34745                                                                      using this register can be corrupted in those bits that are
34746                                                                      nonzero. */
34747         uint64_t reserved_1_3          : 3;
34748         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
34749 #else /* Word 0 - Little Endian */
34750         uint64_t cnp                   : 1;  /**< [  0:  0](R/W) Common not private. */
34751         uint64_t reserved_1_3          : 3;
34752         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
34753                                                                      RES0.
34754 
34755                                                                  x is based on the value of AP_VTCR_EL2[T0SZ], the stage of
34756                                                                      translation, and the memory translation granule size.
34757                                                                  The AArch64 Virtual Memory System Architecture chapter
34758                                                                      describes how x is calculated.
34759                                                                  The value of x determines the required alignment of the
34760                                                                      translation table, which must be aligned to 22^(x)
34761                                                                      bytes.
34762 
34763                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
34764                                                                      Translation Table Base Address. Its effects are CONSTRAINED
34765                                                                      UNPREDICTABLE, and can be one of the following:
34766 
34767                                                                  Bits \<x-1:0\> are treated as if all the bits are zero. The
34768                                                                      value read back from those bits might be the value written or
34769                                                                      might be zero.
34770 
34771                                                                  The calculation of an address for a translation table walk
34772                                                                      using this register can be corrupted in those bits that are
34773                                                                      nonzero. */
34774         uint64_t vmid                  : 16; /**< [ 63: 48](R/W) The VMID for the translation table. Expanded to 16 bits
34775                                                                  by the ARM Large System Extensions. */
34776 #endif /* Word 0 - End */
34777     } s;
34778     struct bdk_ap_vttbr_el2_cn8
34779     {
34780 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
34781         uint64_t vmid                  : 16; /**< [ 63: 48](R/W) The VMID for the translation table. Expanded to 16 bits
34782                                                                  by the ARM Large System Extensions. */
34783         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
34784                                                                      RES0.
34785 
34786                                                                  x is based on the value of AP_VTCR_EL2[T0SZ], the stage of
34787                                                                      translation, and the memory translation granule size.
34788                                                                  The AArch64 Virtual Memory System Architecture chapter
34789                                                                      describes how x is calculated.
34790                                                                  The value of x determines the required alignment of the
34791                                                                      translation table, which must be aligned to 22^(x)
34792                                                                      bytes.
34793 
34794                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
34795                                                                      Translation Table Base Address. Its effects are CONSTRAINED
34796                                                                      UNPREDICTABLE, and can be one of the following:
34797 
34798                                                                  Bits \<x-1:0\> are treated as if all the bits are zero. The
34799                                                                      value read back from those bits might be the value written or
34800                                                                      might be zero.
34801 
34802                                                                  The calculation of an address for a translation table walk
34803                                                                      using this register can be corrupted in those bits that are
34804                                                                      nonzero. */
34805         uint64_t reserved_0_3          : 4;
34806 #else /* Word 0 - Little Endian */
34807         uint64_t reserved_0_3          : 4;
34808         uint64_t baddr                 : 44; /**< [ 47:  4](R/W) Translation table base address, bits\<47:x\>. Bits \<x-1:0\> are
34809                                                                      RES0.
34810 
34811                                                                  x is based on the value of AP_VTCR_EL2[T0SZ], the stage of
34812                                                                      translation, and the memory translation granule size.
34813                                                                  The AArch64 Virtual Memory System Architecture chapter
34814                                                                      describes how x is calculated.
34815                                                                  The value of x determines the required alignment of the
34816                                                                      translation table, which must be aligned to 22^(x)
34817                                                                      bytes.
34818 
34819                                                                  If bits \<x-1:0\> are not all zero, this is a misaligned
34820                                                                      Translation Table Base Address. Its effects are CONSTRAINED
34821                                                                      UNPREDICTABLE, and can be one of the following:
34822 
34823                                                                  Bits \<x-1:0\> are treated as if all the bits are zero. The
34824                                                                      value read back from those bits might be the value written or
34825                                                                      might be zero.
34826 
34827                                                                  The calculation of an address for a translation table walk
34828                                                                      using this register can be corrupted in those bits that are
34829                                                                      nonzero. */
34830         uint64_t vmid                  : 16; /**< [ 63: 48](R/W) The VMID for the translation table. Expanded to 16 bits
34831                                                                  by the ARM Large System Extensions. */
34832 #endif /* Word 0 - End */
34833     } cn8;
34834     /* struct bdk_ap_vttbr_el2_s cn9; */
34835 };
34836 typedef union bdk_ap_vttbr_el2 bdk_ap_vttbr_el2_t;
34837 
34838 #define BDK_AP_VTTBR_EL2 BDK_AP_VTTBR_EL2_FUNC()
34839 static inline uint64_t BDK_AP_VTTBR_EL2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_AP_VTTBR_EL2_FUNC(void)34840 static inline uint64_t BDK_AP_VTTBR_EL2_FUNC(void)
34841 {
34842     return 0x30402010000ll;
34843 }
34844 
34845 #define typedef_BDK_AP_VTTBR_EL2 bdk_ap_vttbr_el2_t
34846 #define bustype_BDK_AP_VTTBR_EL2 BDK_CSR_TYPE_SYSREG
34847 #define basename_BDK_AP_VTTBR_EL2 "AP_VTTBR_EL2"
34848 #define busnum_BDK_AP_VTTBR_EL2 0
34849 #define arguments_BDK_AP_VTTBR_EL2 -1,-1,-1,-1
34850 
34851 #endif /* __BDK_CSRS_AP_H__ */
34852