1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include <linux/vmalloc.h>
6
7 #include "dml2_internal_types.h"
8 #include "dml_top.h"
9 #include "dml2_core_dcn4_calcs.h"
10 #include "dml2_internal_shared_types.h"
11 #include "dml21_utils.h"
12 #include "dml21_translation_helper.h"
13 #include "dml2_dc_resource_mgmt.h"
14
dml21_allocate_memory(struct dml2_context ** dml_ctx)15 static bool dml21_allocate_memory(struct dml2_context **dml_ctx)
16 {
17 *dml_ctx = vzalloc(sizeof(struct dml2_context));
18 if (!(*dml_ctx))
19 return false;
20
21 (*dml_ctx)->v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance));
22 if (!((*dml_ctx)->v21.dml_init.dml2_instance))
23 return false;
24
25 (*dml_ctx)->v21.mode_support.dml2_instance = (*dml_ctx)->v21.dml_init.dml2_instance;
26 (*dml_ctx)->v21.mode_programming.dml2_instance = (*dml_ctx)->v21.dml_init.dml2_instance;
27
28 (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config;
29 (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config;
30
31 (*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming));
32 if (!((*dml_ctx)->v21.mode_programming.programming))
33 return false;
34
35 return true;
36 }
37
dml21_apply_debug_options(const struct dc * in_dc,struct dml2_context * dml_ctx,const struct dml2_configuration_options * config)38 static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)
39 {
40 bool disable_fams2;
41 struct dml2_pmo_options *pmo_options = &dml_ctx->v21.dml_init.options.pmo_options;
42
43 /* ODM options */
44 pmo_options->disable_dyn_odm = !config->minimize_dispclk_using_odm;
45 pmo_options->disable_dyn_odm_for_multi_stream = true;
46 pmo_options->disable_dyn_odm_for_stream_with_svp = true;
47
48 /* UCLK P-State options */
49 if (in_dc->debug.dml21_force_pstate_method) {
50 dml_ctx->config.pmo.force_pstate_method_enable = true;
51 for (int i = 0; i < MAX_PIPES; i++)
52 dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i];
53 } else {
54 dml_ctx->config.pmo.force_pstate_method_enable = false;
55 }
56
57 pmo_options->disable_vblank = ((in_dc->debug.dml21_disable_pstate_method_mask >> 1) & 1);
58
59 /* NOTE: DRR and SubVP Require FAMS2 */
60 disable_fams2 = !in_dc->debug.fams2_config.bits.enable;
61 pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) ||
62 in_dc->debug.force_disable_subvp ||
63 disable_fams2;
64 pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) ||
65 disable_fams2;
66 pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) ||
67 disable_fams2;
68 pmo_options->disable_fams2 = disable_fams2;
69
70 pmo_options->disable_drr_var_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE ||
71 in_dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY;
72 pmo_options->disable_drr_clamped_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE;
73 }
74
dml21_init(const struct dc * in_dc,struct dml2_context ** dml_ctx,const struct dml2_configuration_options * config)75 static void dml21_init(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)
76 {
77 switch (in_dc->ctx->dce_version) {
78 case DCN_VERSION_4_01:
79 (*dml_ctx)->v21.dml_init.options.project_id = dml2_project_dcn4x_stage2_auto_drr_svp;
80 break;
81 default:
82 (*dml_ctx)->v21.dml_init.options.project_id = dml2_project_invalid;
83 }
84
85 (*dml_ctx)->architecture = dml2_architecture_21;
86
87 /* Store configuration options */
88 (*dml_ctx)->config = *config;
89
90 DC_FP_START();
91
92 /*Initialize SOCBB and DCNIP params */
93 dml21_initialize_soc_bb_params(&(*dml_ctx)->v21.dml_init, config, in_dc);
94 dml21_initialize_ip_params(&(*dml_ctx)->v21.dml_init, config, in_dc);
95 dml21_apply_soc_bb_overrides(&(*dml_ctx)->v21.dml_init, config, in_dc);
96
97 /* apply debug overrides */
98 dml21_apply_debug_options(in_dc, *dml_ctx, config);
99
100 /*Initialize DML21 instance */
101 dml2_initialize_instance(&(*dml_ctx)->v21.dml_init);
102
103 DC_FP_END();
104 }
105
dml21_create(const struct dc * in_dc,struct dml2_context ** dml_ctx,const struct dml2_configuration_options * config)106 bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)
107 {
108 /* Allocate memory for initializing DML21 instance */
109 if (!dml21_allocate_memory(dml_ctx))
110 return false;
111
112 dml21_init(in_dc, dml_ctx, config);
113
114 return true;
115 }
116
dml21_destroy(struct dml2_context * dml2)117 void dml21_destroy(struct dml2_context *dml2)
118 {
119 vfree(dml2->v21.dml_init.dml2_instance);
120 vfree(dml2->v21.mode_programming.programming);
121 }
122
dml21_calculate_rq_and_dlg_params(const struct dc * dc,struct dc_state * context,struct resource_context * out_new_hw_state,struct dml2_context * in_ctx,unsigned int pipe_cnt)123 static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state,
124 struct dml2_context *in_ctx, unsigned int pipe_cnt)
125 {
126 unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0;
127 struct dml2_per_plane_programming *pln_prog = NULL;
128 struct dml2_per_stream_programming *stream_prog = NULL;
129 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
130 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};
131 int num_pipes;
132
133 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
134
135 /* copy global DCHUBBUB arbiter registers */
136 memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs));
137
138 /* legacy only */
139 context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64;
140
141 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0;
142 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0;
143 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0;
144
145 for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) {
146 pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
147
148 if (!pln_prog->plane_descriptor)
149 continue;
150
151 stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descriptor->stream_index];
152 num_dpps_required = pln_prog->num_dpps_required;
153
154 if (num_dpps_required == 0) {
155 continue;
156 }
157 num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
158
159 if (num_pipes <= 0)
160 continue;
161
162 /* program each pipe */
163 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
164 dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog);
165
166 if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) {
167 dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog);
168 }
169 }
170 }
171
172 /* assign global clocks */
173 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
174 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
175 if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) {
176 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz =
177 in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000;
178 } else {
179 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000;
180 }
181
182 if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) {
183 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
184 in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000;
185 } else {
186 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000;
187 }
188
189 /* get global mall allocation */
190 if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {
191 context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);
192 } else {
193 context->bw_ctx.bw.dcn.clk.num_ways = 0;
194 }
195 }
196
dml21_mode_check_and_programming(const struct dc * in_dc,struct dc_state * context,struct dml2_context * dml_ctx)197 static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
198 {
199 bool result = false;
200 struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming;
201
202 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg));
203 memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));
204 memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out));
205
206 if (!context)
207 return true;
208
209 if (context->stream_count == 0) {
210 dml21_build_fams2_programming(in_dc, context, dml_ctx);
211 return true;
212 }
213
214 /* scrub phantom's from current dc_state */
215 dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);
216 dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);
217
218 /* Populate stream, plane mappings and other fields in display config. */
219 result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx);
220 if (!result)
221 return false;
222
223 result = dml2_build_mode_programming(mode_programming);
224 if (!result)
225 return false;
226
227 /* Check and map HW resources */
228 if (result && !dml_ctx->config.skip_hw_state_mapping) {
229 dml21_map_hw_resources(dml_ctx);
230 dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state);
231 /* if subvp phantoms are present, expand them into dc context */
232 dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx);
233 }
234
235 /* Copy DML CLK, WM and REG outputs to bandwidth context */
236 if (result && !dml_ctx->config.skip_hw_state_mapping) {
237 dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count);
238 dml21_copy_clocks_to_dc_state(dml_ctx, context);
239 dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx);
240 dml21_build_fams2_programming(in_dc, context, dml_ctx);
241 }
242
243 return true;
244 }
245
dml21_check_mode_support(const struct dc * in_dc,struct dc_state * context,struct dml2_context * dml_ctx)246 static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
247 {
248 bool is_supported = false;
249 struct dml2_initialize_instance_in_out *dml_init = &dml_ctx->v21.dml_init;
250 struct dml2_check_mode_supported_in_out *mode_support = &dml_ctx->v21.mode_support;
251
252 memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg));
253 memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));
254 memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out));
255
256 if (!context || context->stream_count == 0)
257 return true;
258
259 /* Scrub phantom's from current dc_state */
260 dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context);
261 dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context);
262
263 mode_support->dml2_instance = dml_init->dml2_instance;
264 dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx);
265 dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming;
266 is_supported = dml2_check_mode_supported(mode_support);
267 if (!is_supported)
268 return false;
269
270 return true;
271 }
272
dml21_validate(const struct dc * in_dc,struct dc_state * context,struct dml2_context * dml_ctx,bool fast_validate)273 bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, bool fast_validate)
274 {
275 bool out = false;
276
277 DC_FP_START();
278
279 /* Use dml_validate_only for fast_validate path */
280 if (fast_validate)
281 out = dml21_check_mode_support(in_dc, context, dml_ctx);
282 else
283 out = dml21_mode_check_and_programming(in_dc, context, dml_ctx);
284
285 DC_FP_END();
286
287 return out;
288 }
289
dml21_prepare_mcache_programming(struct dc * in_dc,struct dc_state * context,struct dml2_context * dml_ctx)290 void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx)
291 {
292 unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index;
293 int num_pipes;
294 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
295 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0};
296
297 struct dml2_per_plane_programming *pln_prog = NULL;
298 struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL;
299 struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals;
300
301 if (context->stream_count == 0) {
302 return;
303 }
304
305 memset(&l->build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out));
306 l->build_mcache_programming_params.dml2_instance = dml_ctx->v21.dml_init.dml2_instance;
307
308 /* phantom's start after main planes */
309 dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes;
310
311 /* Build mcache programming parameters per plane per pipe */
312 for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) {
313 pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
314
315 mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_prog_idx];
316 memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
317 mcache_config->plane_descriptor = pln_prog->plane_descriptor;
318 mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx];
319 mcache_config->num_pipes = pln_prog->num_dpps_required;
320 l->build_mcache_programming_params.num_configurations++;
321
322 if (pln_prog->num_dpps_required == 0) {
323 continue;
324 }
325
326 num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
327 if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL ||
328 dc_main_pipes[0]->plane_state == NULL)
329 continue;
330
331 /* get config for each pipe */
332 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
333 ASSERT(dc_main_pipes[dc_pipe_index]);
334 dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]);
335 }
336
337 /* get config for each phantom pipe */
338 if (pln_prog->phantom_plane.valid &&
339 dc_phantom_pipes[0] &&
340 dc_main_pipes[0]->stream &&
341 dc_phantom_pipes[0]->plane_state) {
342 mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx];
343 memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
344 mcache_config->plane_descriptor = pln_prog->plane_descriptor;
345 mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx];
346 mcache_config->num_pipes = pln_prog->num_dpps_required;
347 l->build_mcache_programming_params.num_configurations++;
348
349 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
350 ASSERT(dc_phantom_pipes[dc_pipe_index]);
351 dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]);
352 }
353
354 /* increment phantom index */
355 dml_phantom_prog_idx++;
356 }
357 }
358
359 /* Call to generate mcache programming per plane per pipe for the given display configuration */
360 dml2_build_mcache_programming(&l->build_mcache_programming_params);
361
362 /* get per plane per pipe mcache programming */
363 for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) {
364 pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx];
365
366 num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx);
367 if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL ||
368 dc_main_pipes[0]->plane_state == NULL)
369 continue;
370
371 /* get config for each pipe */
372 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
373 ASSERT(dc_main_pipes[dc_pipe_index]);
374 if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) {
375 memcpy(&dc_main_pipes[dc_pipe_index]->mcache_regs,
376 l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index],
377 sizeof(struct dml2_hubp_pipe_mcache_regs));
378 }
379 }
380
381 /* get config for each phantom pipe */
382 if (pln_prog->phantom_plane.valid &&
383 dc_phantom_pipes[0] &&
384 dc_main_pipes[0]->stream &&
385 dc_phantom_pipes[0]->plane_state) {
386 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
387 ASSERT(dc_phantom_pipes[dc_pipe_index]);
388 if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) {
389 memcpy(&dc_phantom_pipes[dc_pipe_index]->mcache_regs,
390 l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index],
391 sizeof(struct dml2_hubp_pipe_mcache_regs));
392 }
393 }
394 /* increment phantom index */
395 dml_phantom_prog_idx++;
396 }
397 }
398 }
399
dml21_copy(struct dml2_context * dst_dml_ctx,struct dml2_context * src_dml_ctx)400 void dml21_copy(struct dml2_context *dst_dml_ctx,
401 struct dml2_context *src_dml_ctx)
402 {
403 /* Preserve references to internals */
404 struct dml2_instance *dst_dml2_instance = dst_dml_ctx->v21.dml_init.dml2_instance;
405 struct dml2_display_cfg_programming *dst_dml2_programming = dst_dml_ctx->v21.mode_programming.programming;
406
407 /* Copy context */
408 memcpy(dst_dml_ctx, src_dml_ctx, sizeof(struct dml2_context));
409
410 /* Copy Internals */
411 memcpy(dst_dml2_instance, src_dml_ctx->v21.dml_init.dml2_instance, sizeof(struct dml2_instance));
412 memcpy(dst_dml2_programming, src_dml_ctx->v21.mode_programming.programming, sizeof(struct dml2_display_cfg_programming));
413
414 /* Restore references to internals */
415 dst_dml_ctx->v21.dml_init.dml2_instance = dst_dml2_instance;
416
417 dst_dml_ctx->v21.mode_support.dml2_instance = dst_dml2_instance;
418 dst_dml_ctx->v21.mode_programming.dml2_instance = dst_dml2_instance;
419
420 dst_dml_ctx->v21.mode_support.display_config = &dst_dml_ctx->v21.display_config;
421 dst_dml_ctx->v21.mode_programming.display_config = dst_dml_ctx->v21.mode_support.display_config;
422
423 dst_dml_ctx->v21.mode_programming.programming = dst_dml2_programming;
424
425 DC_FP_START();
426
427 /* need to initialize copied instance for internal references to be correct */
428 dml2_initialize_instance(&dst_dml_ctx->v21.dml_init);
429
430 DC_FP_END();
431 }
432
dml21_create_copy(struct dml2_context ** dst_dml_ctx,struct dml2_context * src_dml_ctx)433 bool dml21_create_copy(struct dml2_context **dst_dml_ctx,
434 struct dml2_context *src_dml_ctx)
435 {
436 /* Allocate memory for initializing DML21 instance */
437 if (!dml21_allocate_memory(dst_dml_ctx))
438 return false;
439
440 dml21_copy(*dst_dml_ctx, src_dml_ctx);
441
442 return true;
443 }
444
dml21_reinit(const struct dc * in_dc,struct dml2_context ** dml_ctx,const struct dml2_configuration_options * config)445 void dml21_reinit(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)
446 {
447 dml21_init(in_dc, dml_ctx, config);
448 }
449
450