1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <amdblocks/acpi.h>
5 #include <amdblocks/biosram.h>
6 #include <device/pci_ops.h>
7 #include <arch/hpet.h>
8 #include <arch/ioapic.h>
9 #include <arch/vga.h>
10 #include <acpi/acpi.h>
11 #include <acpi/acpigen.h>
12 #include <cbmem.h>
13 #include <console/console.h>
14 #include <cpu/amd/mtrr.h>
15 #include <cpu/x86/lapic_def.h>
16 #include <cpu/x86/msr.h>
17 #include <device/device.h>
18 #include <device/pci.h>
19 #include <device/pci_ids.h>
20 #include <amdblocks/agesawrapper.h>
21 #include <amdblocks/agesawrapper_call.h>
22 #include <amdblocks/ioapic.h>
23 #include <agesa_headers.h>
24 #include <soc/cpu.h>
25 #include <soc/northbridge.h>
26 #include <soc/pci_devs.h>
27 #include <soc/iomap.h>
28 #include <stdint.h>
29 #include <string.h>
30
31 #include "chip.h"
32
read_resources(struct device * dev)33 static void read_resources(struct device *dev)
34 {
35 unsigned int idx = 0;
36
37 /* The northbridge has no PCI BARs implemented, so there's no need to call
38 pci_dev_read_resources for it */
39
40 /*
41 * This MMCONF resource must be reserved in the PCI domain.
42 * It is not honored by the coreboot resource allocator if it is in
43 * the CPU_CLUSTER.
44 */
45 mmconf_resource(dev, idx++);
46 }
47
48 /**
49 * I tried to reuse the resource allocation code in set_resource()
50 * but it is too difficult to deal with the resource allocation magic.
51 */
52
create_vga_resource(struct device * dev)53 static void create_vga_resource(struct device *dev)
54 {
55 if (!dev->downstream)
56 return;
57 if (!(dev->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA))
58 return;
59
60 printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev));
61 /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */
62 pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
63 }
64
set_resources(struct device * dev)65 static void set_resources(struct device *dev)
66 {
67 /* do we need this? */
68 create_vga_resource(dev);
69
70 if (dev->downstream && dev->downstream->children)
71 assign_resources(dev->downstream);
72 }
73
northbridge_init(struct device * dev)74 static void northbridge_init(struct device *dev)
75 {
76 register_new_ioapic(IO_APIC2_ADDR);
77 }
78
79 /* Used by \_SB.PCI0._CRS */
acpi_fill_root_complex_tom(const struct device * device)80 static void acpi_fill_root_complex_tom(const struct device *device)
81 {
82 const char *scope;
83
84 assert(device);
85
86 scope = acpi_device_scope(device);
87 assert(scope);
88 acpigen_write_scope(scope);
89
90 acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb());
91
92 /*
93 * Since XP only implements parts of ACPI 2.0, we can't use a qword
94 * here.
95 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
96 * slide 22ff.
97 * Shift value right by 20 bit to make it fit into 32bit,
98 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
99 */
100 acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20);
101 acpigen_pop_len();
102 }
103
acpi_fill_hest(acpi_hest_t * hest)104 static unsigned long acpi_fill_hest(acpi_hest_t *hest)
105 {
106 void *addr, *current;
107
108 /* Skip the HEST header. */
109 current = (void *)(hest + 1);
110
111 addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
112 if (addr != NULL)
113 current += acpi_create_hest_error_source(hest, current, 0,
114 (void *)((u32)addr + 2), *(uint16_t *)addr - 2);
115
116 addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
117 if (addr != NULL)
118 current += acpi_create_hest_error_source(hest, current, 1,
119 (void *)((u32)addr + 2), *(uint16_t *)addr - 2);
120
121 return (unsigned long)current;
122 }
123
soc_acpi_write_tables(const struct device * device,unsigned long current,acpi_rsdp_t * rsdp)124 unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
125 acpi_rsdp_t *rsdp)
126 {
127 acpi_srat_t *srat;
128 acpi_slit_t *slit;
129 acpi_header_t *alib;
130 acpi_header_t *ivrs;
131 acpi_hest_t *hest;
132
133 /* HEST */
134 current = acpi_align_current(current);
135 hest = (acpi_hest_t *)current;
136 acpi_write_hest(hest, acpi_fill_hest);
137 acpi_add_table(rsdp, (void *)current);
138 current += hest->header.length;
139
140 current = acpi_align_current(current);
141 printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
142 ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
143 if (ivrs != NULL) {
144 memcpy((void *)current, ivrs, ivrs->length);
145 ivrs = (acpi_header_t *)current;
146 current += ivrs->length;
147 acpi_add_table(rsdp, ivrs);
148 } else {
149 printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
150 }
151
152 /* SRAT */
153 current = acpi_align_current(current);
154 printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
155 srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT);
156 if (srat != NULL) {
157 memcpy((void *)current, srat, srat->header.length);
158 srat = (acpi_srat_t *)current;
159 current += srat->header.length;
160 acpi_add_table(rsdp, srat);
161 } else {
162 printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
163 }
164
165 /* SLIT */
166 current = acpi_align_current(current);
167 printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
168 slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT);
169 if (slit != NULL) {
170 memcpy((void *)current, slit, slit->header.length);
171 slit = (acpi_slit_t *)current;
172 current += slit->header.length;
173 acpi_add_table(rsdp, slit);
174 } else {
175 printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
176 }
177
178 /* ALIB */
179 current = acpi_align_current(current);
180 printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
181 alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB);
182 if (alib != NULL) {
183 memcpy((void *)current, alib, alib->length);
184 alib = (acpi_header_t *)current;
185 current += alib->length;
186 acpi_add_table(rsdp, (void *)alib);
187 } else {
188 printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL."
189 " Skipping.\n");
190 }
191
192 printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
193 return current;
194 }
195
196 struct device_operations stoneyridge_northbridge_operations = {
197 .read_resources = read_resources,
198 .set_resources = set_resources,
199 .enable_resources = pci_dev_enable_resources,
200 .init = northbridge_init,
201 .acpi_fill_ssdt = acpi_fill_root_complex_tom,
202 .write_acpi_tables = soc_acpi_write_tables,
203 };
204
205 /*
206 * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,
207 * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining
208 * MMIO to posted. Route all I/O to the southbridge.
209 */
amd_initcpuio(void)210 void amd_initcpuio(void)
211 {
212 uintptr_t topmem = get_top_of_mem_below_4gb();
213 uintptr_t base, limit;
214
215 /* Enable legacy video routing: D18F1xF4 VGA Enable */
216 pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
217
218 /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
219 base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
220 limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP;
221 pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit);
222 pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base);
223
224 /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
225 base = (topmem >> 8) | MMIO_WE | MMIO_RE;
226 limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8;
227 pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit);
228 pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base);
229
230 /* Route all I/O downstream */
231 base = 0 | IO_WE | IO_RE;
232 limit = ALIGN_DOWN(0xffff, 4 * KiB);
233 pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit);
234 pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base);
235 }
236
fam15_finalize(void * chip_info)237 void fam15_finalize(void *chip_info)
238 {
239 u32 value;
240
241 /* TODO: move IOAPIC code to dsdt.asl */
242 pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0);
243 pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5);
244
245 /* disable No Snoop */
246 value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS);
247 value &= ~HDA_NO_SNOOP_EN;
248 pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value);
249 }
250
domain_enable_resources(struct device * dev)251 void domain_enable_resources(struct device *dev)
252 {
253 /* Must be called after PCI enumeration and resource allocation */
254 if (!acpi_is_wakeup_s3())
255 do_agesawrapper(AMD_INIT_MID, "amdinitmid");
256 }
257
domain_read_resources(struct device * dev)258 void domain_read_resources(struct device *dev)
259 {
260 uint64_t uma_base = get_uma_base();
261 uint32_t uma_size = get_uma_size();
262 uint32_t mem_useable = cbmem_top();
263 uint32_t tom = get_top_of_mem_below_4gb();
264 uint64_t high_tom = get_top_of_mem_above_4gb();
265 uint64_t high_mem_useable;
266 int idx = 0x10;
267
268 pci_domain_read_resources(dev);
269
270 fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
271
272 /* 0x0 -> 0x9ffff */
273 ram_range(dev, idx++, 0, 0xa0000);
274
275 /* 0xa0000 -> 0xbffff: legacy VGA */
276 mmio_range(dev, idx++, VGA_MMIO_BASE, VGA_MMIO_SIZE);
277
278 /* 0xc0000 -> 0xfffff: Option ROM */
279 reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
280
281 /*
282 * 0x100000 (1MiB) -> low top usable RAM
283 * cbmem_top() accounts for low UMA and TSEG if they are used.
284 */
285 ram_from_to(dev, idx++, 1 * MiB, mem_useable);
286
287 /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
288 reserved_ram_from_to(dev, idx++, mem_useable, tom);
289
290 /* NB IOAPIC2 resource. IOMMU_IOAPIC_IDX is used as index, so that the common AMD MADT
291 code can find this resource */
292 mmio_range(dev, IOMMU_IOAPIC_IDX, IO_APIC2_ADDR, 0x1000);
293
294 /* If there is memory above 4GiB */
295 if (high_tom >> 32) {
296 /* 4GiB -> high top usable */
297 if (uma_base >= (4ull * GiB))
298 high_mem_useable = uma_base;
299 else
300 high_mem_useable = high_tom;
301
302 ram_from_to(dev, idx++, 4ull * GiB, high_mem_useable);
303
304 /* High top usable RAM -> high top RAM */
305 if (uma_base >= (4ull * GiB)) {
306 reserved_ram_range(dev, idx++, uma_base, uma_size);
307 }
308 }
309 }
310
set_board_env_params(GNB_ENV_CONFIGURATION * params)311 __weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { }
312
SetNbEnvParams(GNB_ENV_CONFIGURATION * params)313 void SetNbEnvParams(GNB_ENV_CONFIGURATION *params)
314 {
315 params->IommuSupport = is_dev_enabled(DEV_PTR(iommu));
316 set_board_env_params(params);
317 }
318
SetNbMidParams(GNB_MID_CONFIGURATION * params)319 void SetNbMidParams(GNB_MID_CONFIGURATION *params)
320 {
321 /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */
322 params->iGpuVgaMode = 0;
323 params->GnbIoapicAddress = IO_APIC2_ADDR;
324 }
325