1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <types.h>
4 #include <console/console.h>
5 #include <device/pci_def.h>
6 #include <southbridge/intel/common/pmbase.h>
7 #include <southbridge/intel/common/gpio.h>
8
9 #include "pmutil.h"
10
alt_gpi_mask(u16 clr,u16 set)11 void alt_gpi_mask(u16 clr, u16 set)
12 {
13 u16 alt_gp = read_pmbase16(ALT_GP_SMI_EN);
14 alt_gp &= ~clr;
15 alt_gp |= set;
16 write_pmbase16(ALT_GP_SMI_EN, alt_gp);
17 }
18
gpe0_mask(u32 clr,u32 set)19 void gpe0_mask(u32 clr, u32 set)
20 {
21 u32 gpe0 = read_pmbase32(GPE0_EN);
22 gpe0 &= ~clr;
23 gpe0 |= set;
24 write_pmbase32(GPE0_EN, gpe0);
25 }
26
27 /**
28 * @brief read and clear PM1_STS
29 * @return PM1_STS register
30 */
reset_pm1_status(void)31 u16 reset_pm1_status(void)
32 {
33 u16 reg16 = read_pmbase16(PM1_STS);
34 /* set status bits are cleared by writing 1 to them */
35 write_pmbase16(PM1_STS, reg16);
36
37 return reg16;
38 }
39
dump_pm1_status(u16 pm1_sts)40 void dump_pm1_status(u16 pm1_sts)
41 {
42 printk(BIOS_SPEW, "PM1_STS: ");
43 if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
44 if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
45 if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
46 if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
47 if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
48 if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
49 if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
50 if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
51 printk(BIOS_SPEW, "\n");
52
53 int reg16 = read_pmbase16(PM1_EN);
54 printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
55 }
56
57 /**
58 * @brief read and clear SMI_STS
59 * @return SMI_STS register
60 */
reset_smi_status(void)61 u32 reset_smi_status(void)
62 {
63 u32 reg32;
64
65 reg32 = read_pmbase32(SMI_STS);
66 /* set status bits are cleared by writing 1 to them */
67 write_pmbase32(SMI_STS, reg32);
68
69 return reg32;
70 }
71
dump_smi_status(u32 smi_sts)72 void dump_smi_status(u32 smi_sts)
73 {
74 printk(BIOS_DEBUG, "SMI_STS: ");
75 if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
76 if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
77 if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
78 if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
79 if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
80 if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
81 if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
82 if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
83 if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
84 if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
85 if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
86 if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
87 if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
88 if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
89 if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
90 if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
91 if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
92 if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
93 if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
94 if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
95 printk(BIOS_DEBUG, "\n");
96 }
97
98 /**
99 * @brief read and clear GPE0_STS
100 * @return GPE0_STS register
101 */
reset_gpe0_status(void)102 u64 reset_gpe0_status(void)
103 {
104 u32 reg_h = 0, reg_l;
105
106 reg_l = read_pmbase32(GPE0_STS);
107 if (GPE0_HAS_64_EVENTS)
108 reg_h = read_pmbase32(GPE0_STS + 4);
109 /* set status bits are cleared by writing 1 to them */
110 write_pmbase32(GPE0_STS, reg_l);
111 if (GPE0_HAS_64_EVENTS)
112 write_pmbase32(GPE0_STS + 4, reg_h);
113
114 return (((u64)reg_h) << 32) | reg_l;
115 }
116
dump_gpe0_status(u64 gpe0_sts)117 void dump_gpe0_status(u64 gpe0_sts)
118 {
119 int i;
120 printk(BIOS_DEBUG, "GPE0_STS: ");
121 if (gpe0_sts & (1LL << 32)) printk(BIOS_DEBUG, "USB6 ");
122 for (i=31; i>= 16; i--) {
123 if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
124 }
125 if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
126 if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
127 if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
128 if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
129 if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
130 if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
131 if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
132 if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
133 if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
134 if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97/USB5 ");
135 if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
136 if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
137 if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");
138 if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOT_PLUG ");
139 if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
140 printk(BIOS_DEBUG, "\n");
141 }
142
143 /**
144 * @brief read and clear TCOx_STS
145 * @return TCOx_STS registers
146 */
reset_tco_status(void)147 u32 reset_tco_status(void)
148 {
149 u32 reg32;
150
151 reg32 = read_pmbase32(TCO1_STS);
152 /*
153 * set status bits are cleared by writing 1 to them, but don't
154 * clear BOOT_STS before SECOND_TO_STS.
155 */
156 write_pmbase32(TCO1_STS, reg32 & ~BOOT_STS);
157 if (reg32 & BOOT_STS)
158 write_pmbase32(TCO1_STS, BOOT_STS);
159
160 return reg32;
161 }
162
dump_tco_status(u32 tco_sts)163 void dump_tco_status(u32 tco_sts)
164 {
165 printk(BIOS_DEBUG, "TCO_STS: ");
166 if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
167 if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
168 if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
169 if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
170 if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
171 if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
172 if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
173 if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
174 if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
175 if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
176 if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
177 if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
178 if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
179 printk(BIOS_DEBUG, "\n");
180 }
181
dump_alt_gp_smi_status(u16 alt_gp_smi_sts)182 void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
183 {
184 int i;
185 printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
186 for (i=15; i>= 0; i--) {
187 if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);
188 }
189 printk(BIOS_DEBUG, "\n");
190 }
191
192 /**
193 * @brief read and clear ALT_GP_SMI_STS
194 * @return ALT_GP_SMI_STS register
195 */
reset_alt_gp_smi_status(void)196 u16 reset_alt_gp_smi_status(void)
197 {
198 u16 reg16;
199
200 reg16 = read_pmbase16(ALT_GP_SMI_STS);
201 /* set status bits are cleared by writing 1 to them */
202 write_pmbase16(ALT_GP_SMI_STS, reg16);
203
204 return reg16;
205 }
206
dump_all_status(void)207 void dump_all_status(void)
208 {
209 dump_smi_status(reset_smi_status());
210 dump_pm1_status(reset_pm1_status());
211 dump_gpe0_status(reset_gpe0_status());
212 dump_alt_gp_smi_status(reset_alt_gp_smi_status());
213 dump_tco_status(reset_tco_status());
214 }
215