1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codec_def_common_hevc.h 24 //! \brief Defines basic HEVC types and macros shared by CodecHal, MHW, and DDI layer 25 //! \details This is the base header for all codec_def HEVC files. All codec_def HEVC files should include this file which should not contain any DDI specific code. 26 //! 27 #ifndef __CODEC_DEF_COMMON_HEVC_H__ 28 #define __CODEC_DEF_COMMON_HEVC_H__ 29 30 #include "codec_def_common.h" 31 32 #define CODEC_MAX_NUM_REF_FRAME_HEVC 15 33 #define CODECHAL_MAX_CUR_NUM_REF_FRAME_HEVC 8 34 #define CODEC_HEVC_VDENC_LCU_WIDTH 64 35 #define CODEC_HEVC_VDENC_LCU_HEIGHT 64 36 37 /*! \brief Quantization matrix data, which is sent on a per-picture basis. 38 * 39 * The quantization matrix buffer is sent only when scaling_list_enabled_flag takes value 1. If 0, driver should assume "flat" scaling lists are present and all the entries takes value 16. 40 */ 41 typedef struct _CODECHAL_HEVC_IQ_MATRIX_PARAMS 42 { 43 /*! \brief Scaling lists for the 4x4 scaling process. 44 * 45 * Corresponding to ScalingList[ 0 ][ MatrixID ][ i ] in HEVC specification, where MatrixID is in the range of 0 to 5, inclusive, and i is in the range of 0 to 15, inclusive. 46 */ 47 uint8_t ucScalingLists0[6][16]; 48 49 /*! \brief Scaling lists for the 8x8 scaling process. 50 * 51 * Corresponding to ScalingList[ 1 ][ MatrixID ][ i ] in the HEVC specification, where MatrixID is in the range of 0 to 5, inclusive, and i is in the range of 0 to 63, inclusive. 52 */ 53 uint8_t ucScalingLists1[6][64]; 54 55 /*! \brief Scaling lists for the 8x8 scaling process. 56 * 57 * Corresponding to ScalingList[ 2 ][ MatrixID ][ i ] in HEVC specification, where MatrixID is in the range of 0 to 5, inclusive, and i is in the range of 0 to 63, inclusive. 58 */ 59 uint8_t ucScalingLists2[6][64]; 60 61 /*! \brief Scaling lists for the 8x8 scaling process. 62 * 63 * Corresponding to ScalingList[ 3 ][ MatrixID ][ i ] in HEVC specification, where MatrixID is in the range of 0 to 1, inclusive, and i is in the range of 0 to 63, inclusive. 64 */ 65 uint8_t ucScalingLists3[2][64]; 66 67 /*! \brief DC value of the scaling list for 16x16 size. 68 * 69 * With sizeID equal to 2 and corresponding to scaling_list_dc_coef_minus8[ sizeID − 2 ][ matrixID ] +8 with sizeID equal to 2 and matrixID in the range of 0 to 5, inclusive, in HEVC specification. 70 */ 71 uint8_t ucScalingListDCCoefSizeID2[6]; 72 73 /*! \brief DC value of the scaling list for 32x32 size. 74 * 75 * With sizeID equal to 3, and corresponding to scaling_list_dc_coef_minus8[ sizeID − 2 ][ matrixID ] +8 with sizeID equal to 3 and matrixID in the range of 0 to 1, inclusive, in HEVC specification. 76 */ 77 uint8_t ucScalingListDCCoefSizeID3[2]; 78 } CODECHAL_HEVC_IQ_MATRIX_PARAMS, *PCODECHAL_HEVC_IQ_MATRIX_PARAMS; 79 80 typedef struct _CODEC_HEVC_SCC_PIC_PARAMS 81 { 82 union 83 { 84 struct 85 { 86 uint32_t pps_curr_pic_ref_enabled_flag : 1; 87 uint32_t palette_mode_enabled_flag : 1; 88 uint32_t motion_vector_resolution_control_idc : 2; //[0..2] 89 uint32_t intra_boundary_filtering_disabled_flag : 1; 90 uint32_t residual_adaptive_colour_transform_enabled_flag : 1; 91 uint32_t pps_slice_act_qp_offsets_present_flag : 1; 92 uint32_t ReservedBits6 : 25; 93 } fields; 94 uint32_t dwScreenContentCodingPropertyFlags; 95 } PicSCCExtensionFlags; 96 97 uint8_t palette_max_size; // [0..64] 98 uint8_t delta_palette_max_predictor_size; // [0..128] 99 uint8_t PredictorPaletteSize; // [0..127] 100 uint16_t PredictorPaletteEntries[3][128]; 101 char pps_act_y_qp_offset_plus5; // [-7..17] 102 char pps_act_cb_qp_offset_plus5; // [-7..17] 103 char pps_act_cr_qp_offset_plus3; // [-9..15] 104 105 } CODEC_HEVC_SCC_PIC_PARAMS, *PCODEC_HEVC_SCC_PIC_PARAMS; 106 107 #endif // __CODEC_DEF_COMMON_HEVC_H__ 108