1 /*
2 *
3 * Copyright (C) 2010 coresystems GmbH
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 //#define USB_DEBUG
30
31 #include <inttypes.h>
32 #include <libpayload.h>
33 #include <arch/barrier.h>
34 #include <arch/cache.h>
35 #include "ehci.h"
36 #include "ehci_private.h"
37
dump_td(u32 addr)38 static void dump_td(u32 addr)
39 {
40 qtd_t *td = phys_to_virt(addr);
41 usb_debug("+---------------------------------------------------+\n");
42 if (((td->token & (3UL << 8)) >> 8) == 2)
43 usb_debug("|..[SETUP]..........................................|\n");
44 else if (((td->token & (3UL << 8)) >> 8) == 1)
45 usb_debug("|..[IN].............................................|\n");
46 else if (((td->token & (3UL << 8)) >> 8) == 0)
47 usb_debug("|..[OUT]............................................|\n");
48 else
49 usb_debug("|..[]...............................................|\n");
50 usb_debug("|:|============ EHCI TD at [0x%08"PRIx32"] ==========|:|\n", addr);
51 usb_debug("|:| ERRORS = [%"PRId32"] | TOKEN = [0x%08"PRIx32"] | |:|\n",
52 3 - ((td->token & QTD_CERR_MASK) >> QTD_CERR_SHIFT), td->token);
53 usb_debug("|:+-----------------------------------------------+:|\n");
54 usb_debug("|:| Next qTD [0x%08"PRIx32"] |:|\n", td->next_qtd);
55 usb_debug("|:+-----------------------------------------------+:|\n");
56 usb_debug("|:| Alt. Next qTD [0x%08"PRIx32"] |:|\n", td->alt_next_qtd);
57 usb_debug("|:+-----------------------------------------------+:|\n");
58 usb_debug("|:| | Bytes to Transfer |[%05"PRId32"] |:|\n", (td->token & QTD_TOTAL_LEN_MASK) >> 16);
59 usb_debug("|:| | PID CODE: | [%ld] |:|\n", (td->token & (3UL << 8)) >> 8);
60 usb_debug("|:| | Interrupt On Complete (IOC) | [%ld] |:|\n", (td->token & (1UL << 15)) >> 15);
61 usb_debug("|:| | Status Active | [%ld] |:|\n", (td->token & (1UL << 7)) >> 7);
62 usb_debug("|:| | Status Halted | [%ld] |:|\n", (td->token & (1UL << 6)) >> 6);
63 usb_debug("|:| TOKEN | Status Data Buffer Error | [%ld] |:|\n", (td->token & (1UL << 5)) >> 5);
64 usb_debug("|:| | Status Babble detected | [%ld] |:|\n", (td->token & (1UL << 4)) >> 4);
65 usb_debug("|:| | Status Transaction Error | [%ld] |:|\n", (td->token & (1UL << 3)) >> 3);
66 usb_debug("|:| | Status Missed Micro Frame | [%ld] |:|\n", (td->token & (1UL << 2)) >> 2);
67 usb_debug("|:| | Split Transaction State | [%ld] |:|\n", (td->token & (1UL << 1)) >> 1);
68 usb_debug("|:| | Ping State | [%ld] |:|\n", td->token & 1UL);
69 usb_debug("|:|-----------------------------------------------|:|\n");
70 usb_debug("|...................................................|\n");
71 usb_debug("+---------------------------------------------------+\n");
72 }
73
74 #if 0 && defined(USB_DEBUG)
75 static void dump_qh(ehci_qh_t *cur)
76 {
77 qtd_t *tmp_qtd = NULL;
78 usb_debug("+===================================================+\n");
79 usb_debug("| ############# EHCI QH at [0x%08lx] ########### |\n", virt_to_phys(cur));
80 usb_debug("+---------------------------------------------------+\n");
81 usb_debug("| Horizontal Link Pointer [0x%08lx] |\n", cur->horiz_link_ptr);
82 usb_debug("+------------------[ 0x%08lx ]-------------------+\n", cur->epchar);
83 usb_debug("| | Maximum Packet Length | [%04ld] |\n", ((cur->epchar & (0x7ffUL << 16)) >> 16));
84 usb_debug("| | Device Address | [%ld] |\n", cur->epchar & 0x7F);
85 usb_debug("| | Inactivate on Next Transaction | [%ld] |\n", ((cur->epchar & (1UL << 7)) >> 7));
86 usb_debug("| | Endpoint Number | [%ld] |\n", ((cur->epchar & (0xFUL << 8)) >> 8));
87 usb_debug("| EPCHAR | Endpoint Speed | [%ld] |\n", ((cur->epchar & (3UL << 12)) >> 12));
88 usb_debug("| | Data Toggle Control | [%ld] |\n", ((cur->epchar & (1UL << 14)) >> 14));
89 usb_debug("| | Head of Reclamation List Flag | [%ld] |\n", ((cur->epchar & (1UL << 15)) >> 15));
90 usb_debug("| | Control Endpoint Flag | [%ld] |\n", ((cur->epchar & (1UL << 27)) >> 27));
91 usb_debug("| | Nak Count Reload | [%ld] |\n", ((cur->epchar & (0xFUL << 28)) >> 28));
92 if (((cur->epchar & (1UL << QH_NON_HS_CTRL_EP_SHIFT)) >> QH_NON_HS_CTRL_EP_SHIFT) == 1) { /* Split transaction */
93 usb_debug("+--------+---------[ 0x%08lx ]----------+--------+\n", cur->epcaps);
94 usb_debug("| | Hub Port | [%ld] |\n", ((cur->epcaps & (0x7FUL << 23)) >> 23)); /* [29:23] */
95 usb_debug("| | Hub Address | [%ld] |\n", ((cur->epcaps & (0x7FUL << 16)) >> 16)); /* [22:16] */
96 }
97 usb_debug("+---------------------------------------------------+\n");
98 usb_debug("| Current QTD [0x%08lx] |\n", cur->current_td_ptr);
99
100 if (!((cur->horiz_link_ptr == 0) && (cur->epchar == 0))) {
101 /* Dump overlay QTD for this QH */
102 usb_debug("+---------------------------------------------------+\n");
103 usb_debug("|::::::::::::::::::: QTD OVERLAY :::::::::::::::::::|\n");
104 dump_td(virt_to_phys((void *)&(cur->td)));
105 /* Dump all TD tree for this QH */
106 tmp_qtd = (qtd_t *)phys_to_virt((cur->td.next_qtd & ~0x1FUL));
107 if (tmp_qtd != NULL)
108 usb_debug("|:::::::::::::::::: EHCI QTD CHAIN :::::::::::::::::|\n");
109 while (tmp_qtd != NULL)
110 {
111 dump_td(virt_to_phys(tmp_qtd));
112 tmp_qtd = (qtd_t *)phys_to_virt((tmp_qtd->next_qtd & ~0x1FUL));
113 }
114 usb_debug("|:::::::::::::::: EOF EHCI QTD CHAIN :::::::::::::::|\n");
115 usb_debug("+---------------------------------------------------+\n");
116 } else {
117 usb_debug("+---------------------------------------------------+\n");
118 }
119 }
120 #endif
121
ehci_start(hci_t * controller)122 static void ehci_start(hci_t *controller)
123 {
124 EHCI_INST(controller)->operation->usbcmd |= HC_OP_RS;
125 }
126
ehci_stop(hci_t * controller)127 static void ehci_stop(hci_t *controller)
128 {
129 EHCI_INST(controller)->operation->usbcmd &= ~HC_OP_RS;
130 }
131
ehci_reset(hci_t * controller)132 static void ehci_reset(hci_t *controller)
133 {
134 short count = 0;
135 ehci_stop(controller);
136 /* wait 10 ms just to be sure */
137 mdelay(10);
138 if (EHCI_INST(controller)->operation->usbsts & HC_OP_HC_HALTED) {
139 EHCI_INST(controller)->operation->usbcmd = HC_OP_HC_RESET;
140 /* wait 100 ms */
141 for (count = 0; count < 10; count++) {
142 mdelay(10);
143 if (!(EHCI_INST(controller)->operation->usbcmd & HC_OP_HC_RESET)) {
144 return;
145 }
146 }
147 }
148 usb_debug("ehci_reset(): reset failed!\n");
149 }
150
ehci_reinit(hci_t * controller)151 static void ehci_reinit(hci_t *controller)
152 {
153 }
154
ehci_set_periodic_schedule(ehci_t * ehcic,int enable)155 static int ehci_set_periodic_schedule(ehci_t *ehcic, int enable)
156 {
157 /* Set periodic schedule status. */
158 if (enable)
159 ehcic->operation->usbcmd |= HC_OP_PERIODIC_SCHED_EN;
160 else
161 ehcic->operation->usbcmd &= ~HC_OP_PERIODIC_SCHED_EN;
162 /* Wait for the controller to accept periodic schedule status.
163 * This shouldn't take too long, but we should timeout nevertheless.
164 */
165 enable = enable ? HC_OP_PERIODIC_SCHED_STAT : 0;
166 int timeout = 100000; /* time out after 100ms */
167 while (((ehcic->operation->usbsts & HC_OP_PERIODIC_SCHED_STAT) != enable)
168 && timeout--)
169 udelay(1);
170 if (timeout < 0) {
171 usb_debug("ehci periodic schedule status change timed out.\n");
172 return 1;
173 }
174 return 0;
175 }
176
ehci_shutdown(hci_t * controller)177 static void ehci_shutdown(hci_t *controller)
178 {
179 detach_controller(controller);
180
181 /* Make sure periodic schedule is disabled */
182 ehci_set_periodic_schedule(EHCI_INST(controller), 0);
183
184 /* Give all ports back to companion controller */
185 EHCI_INST(controller)->operation->configflag = 0;
186
187 /* Free all dynamic allocations */
188 free(EHCI_INST(controller)->dma_buffer);
189 free(phys_to_virt(EHCI_INST(controller)->operation->periodiclistbase));
190 free((void *)EHCI_INST(controller)->dummy_qh);
191 free(EHCI_INST(controller));
192 free(controller);
193 }
194
195 enum { EHCI_OUT = 0, EHCI_IN = 1, EHCI_SETUP = 2 };
196
197 /* returns handled bytes. assumes that the fields it writes are empty on entry */
fill_td(qtd_t * td,void * data,int datalen)198 static int fill_td(qtd_t *td, void* data, int datalen)
199 {
200 u32 total_len = 0;
201 u32 page_no = 0;
202
203 u32 start = virt_to_phys(data);
204 u32 page = start & ~4095;
205 u32 offset = start & 4095;
206 u32 page_len = 4096 - offset;
207
208 td->token |= 0 << QTD_CPAGE_SHIFT;
209 td->bufptrs[page_no++] = start;
210
211 if (datalen <= page_len) {
212 total_len = datalen;
213 } else {
214 datalen -= page_len;
215 total_len += page_len;
216
217 while (page_no < 5) {
218 /* we have a contiguous mapping between virtual and physical memory */
219 page += 4096;
220
221 td->bufptrs[page_no++] = page;
222 if (datalen <= 4096) {
223 total_len += datalen;
224 break;
225 }
226 datalen -= 4096;
227 total_len += 4096;
228
229 /* end TD at a packet boundary if transfer not complete */
230 if (page_no == 5)
231 total_len &= ~511;
232 }
233 }
234 td->token |= total_len << QTD_TOTAL_LEN_SHIFT;
235 return total_len;
236 }
237
238 /* free up data structures */
free_qh_and_tds(ehci_qh_t * qh,qtd_t * cur)239 static void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur)
240 {
241 qtd_t *next;
242 while (cur) {
243 next = (qtd_t*)phys_to_virt(cur->next_qtd & ~31);
244 free((void *)cur);
245 cur = next;
246 }
247 free((void *)qh);
248 }
249
250 #define EHCI_SLEEP_TIME_US 50
251
wait_for_tds(qtd_t * head)252 static int wait_for_tds(qtd_t *head)
253 {
254 /* returns the amount of bytes *not* transmitted, or -1 for error */
255 int result = 0;
256 qtd_t *cur = head;
257 while (1) {
258 if (0) dump_td(virt_to_phys(cur));
259
260 /* wait for results */
261 int timeout = USB_MAX_PROCESSING_TIME_US / EHCI_SLEEP_TIME_US;
262 while ((cur->token & QTD_ACTIVE) && !(cur->token & QTD_HALTED)
263 && timeout--)
264 udelay(EHCI_SLEEP_TIME_US);
265 if (timeout < 0) {
266 usb_debug("Error: ehci: queue transfer "
267 "processing timed out.\n");
268 return -1;
269 }
270 if (cur->token & QTD_HALTED) {
271 usb_debug("ERROR with packet\n");
272 dump_td(virt_to_phys(cur));
273 usb_debug("-----------------\n");
274 return -1;
275 }
276 result += (cur->token & QTD_TOTAL_LEN_MASK)
277 >> QTD_TOTAL_LEN_SHIFT;
278 if (cur->next_qtd & 1) {
279 break;
280 }
281 if (0)
282 dump_td(virt_to_phys(cur));
283 /* helps debugging the TD chain */
284 if (0)
285 usb_debug("\nmoving from %p to %p\n", cur, phys_to_virt(cur->next_qtd));
286 cur = phys_to_virt(cur->next_qtd);
287 }
288 return result;
289 }
290
ehci_set_async_schedule(ehci_t * ehcic,int enable)291 static int ehci_set_async_schedule(ehci_t *ehcic, int enable)
292 {
293
294 /* Memory barrier to ensure that all memory accesses before we set the
295 * async schedule are complete. It was observed especially in the case of
296 * arm64, that netboot and USB stuff resulted in lots of errors possibly
297 * due to CPU reordering. Hence, enforcing strict CPU ordering.
298 */
299 mb();
300
301 /* Set async schedule status. */
302 if (enable)
303 ehcic->operation->usbcmd |= HC_OP_ASYNC_SCHED_EN;
304 else
305 ehcic->operation->usbcmd &= ~HC_OP_ASYNC_SCHED_EN;
306 /* Wait for the controller to accept async schedule status.
307 * This shouldn't take too long, but we should timeout nevertheless.
308 */
309 enable = enable ? HC_OP_ASYNC_SCHED_STAT : 0;
310 int timeout = 100; /* time out after 100ms */
311 while (((ehcic->operation->usbsts & HC_OP_ASYNC_SCHED_STAT) != enable)
312 && timeout--)
313 mdelay(1);
314 if (timeout < 0) {
315 usb_debug("ehci async schedule status change timed out.\n");
316 return 1;
317 }
318 return 0;
319 }
320
ehci_process_async_schedule(ehci_t * ehcic,ehci_qh_t * qhead,qtd_t * head)321 static int ehci_process_async_schedule(
322 ehci_t *ehcic, ehci_qh_t *qhead, qtd_t *head)
323 {
324 int result;
325
326 /* make sure async schedule is disabled */
327 if (ehci_set_async_schedule(ehcic, 0)) return -1;
328
329 /* hook up QH */
330 ehcic->operation->asynclistaddr = virt_to_phys(qhead);
331
332 /* start async schedule */
333 if (ehci_set_async_schedule(ehcic, 1)) return -1;
334
335 /* wait for result */
336 result = wait_for_tds(head);
337
338 /* disable async schedule */
339 ehci_set_async_schedule(ehcic, 0);
340
341 return result;
342 }
343
ehci_bulk(endpoint_t * ep,int size,u8 * src,int finalize)344 static int ehci_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
345 {
346 int result = 0;
347 u8 *end = src + size;
348 int remaining = size;
349 int endp = ep->endpoint & 0xf;
350 int pid = (ep->direction == IN)?EHCI_IN:EHCI_OUT;
351
352 int hubaddr = 0, hubport = 0;
353 if (ep->dev->speed < 2) {
354 /* we need a split transaction */
355 if (closest_usb2_hub(ep->dev, &hubaddr, &hubport))
356 return -1;
357 }
358
359 if (!dma_coherent(src)) {
360 end = EHCI_INST(ep->dev->controller)->dma_buffer + size;
361 if (size > DMA_SIZE) {
362 usb_debug("EHCI bulk transfer too large for DMA buffer: %d\n", size);
363 return -1;
364 }
365 if (pid == EHCI_OUT)
366 memcpy(end - size, src, size);
367 }
368
369 ehci_qh_t *qh = dma_memalign(64, sizeof(ehci_qh_t));
370 qtd_t *head = dma_memalign(64, sizeof(qtd_t));
371 qtd_t *cur = head;
372 if (!qh || !head)
373 goto oom;
374 while (1) {
375 memset((void *)cur, 0, sizeof(qtd_t));
376 cur->token = QTD_ACTIVE |
377 (pid << QTD_PID_SHIFT) |
378 (0 << QTD_CERR_SHIFT);
379 remaining -= fill_td(cur, end - remaining, remaining);
380
381 cur->alt_next_qtd = QTD_TERMINATE;
382 if (remaining <= 0) {
383 cur->next_qtd = virt_to_phys(0) | QTD_TERMINATE;
384 break;
385 } else {
386 qtd_t *next = dma_memalign(64, sizeof(qtd_t));
387 if (!next)
388 goto oom;
389 cur->next_qtd = virt_to_phys(next);
390 cur = next;
391 }
392 }
393
394 /* create QH */
395 memset((void *)qh, 0, sizeof(ehci_qh_t));
396 qh->horiz_link_ptr = virt_to_phys(qh) | QH_QH;
397 qh->epchar = ep->dev->address |
398 (endp << QH_EP_SHIFT) |
399 (ep->dev->speed << QH_EPS_SHIFT) |
400 (0 << QH_DTC_SHIFT) |
401 (1 << QH_RECLAIM_HEAD_SHIFT) |
402 (ep->maxpacketsize << QH_MPS_SHIFT) |
403 (0 << QH_NAK_CNT_SHIFT);
404 qh->epcaps = (3 << QH_PIPE_MULTIPLIER_SHIFT) |
405 (hubport << QH_PORT_NUMBER_SHIFT) |
406 (hubaddr << QH_HUB_ADDRESS_SHIFT);
407
408 qh->td.next_qtd = virt_to_phys(head);
409 qh->td.token |= (ep->toggle?QTD_TOGGLE_DATA1:0);
410 head->token |= (ep->toggle?QTD_TOGGLE_DATA1:0);
411
412 result = ehci_process_async_schedule(
413 EHCI_INST(ep->dev->controller), qh, head);
414 if (result >= 0) {
415 result = size - result;
416 if (pid == EHCI_IN && end != src + size)
417 memcpy(src, end - size, result);
418 }
419
420 ep->toggle = (cur->token & QTD_TOGGLE_MASK) >> QTD_TOGGLE_SHIFT;
421
422 free_qh_and_tds(qh, head);
423
424 return result;
425
426 oom:
427 usb_debug("Not enough DMA memory for EHCI control structures!\n");
428 free_qh_and_tds(qh, head);
429 return -1;
430 }
431
432 /* FIXME: Handle control transfers as 3 QHs, so the 2nd stage can be >0x4000 bytes */
ehci_control(usbdev_t * dev,direction_t dir,int drlen,void * setup,int dalen,u8 * src)433 static int ehci_control(usbdev_t *dev, direction_t dir, int drlen, void *setup,
434 int dalen, u8 *src)
435 {
436 u8 *data = src;
437 u8 *devreq = setup;
438 int endp = 0; // this is control. always 0 (for now)
439 int toggle = 0;
440 int mlen = dev->endpoints[0].maxpacketsize;
441 int result = 0;
442
443 int hubaddr = 0, hubport = 0, non_hs_ctrl_ep = 0;
444 if (dev->speed < 2) {
445 /* we need a split transaction */
446 if (closest_usb2_hub(dev, &hubaddr, &hubport))
447 return -1;
448 non_hs_ctrl_ep = 1;
449 }
450
451 if (!dma_coherent(setup)) {
452 devreq = EHCI_INST(dev->controller)->dma_buffer;
453 memcpy(devreq, setup, drlen);
454 }
455 if (dalen > 0 && !dma_coherent(src)) {
456 data = EHCI_INST(dev->controller)->dma_buffer + drlen;
457 if (drlen + dalen > DMA_SIZE) {
458 usb_debug("EHCI control transfer too large for DMA buffer: %d\n", drlen + dalen);
459 return -1;
460 }
461 if (dir == OUT)
462 memcpy(data, src, dalen);
463 }
464
465 /* create qTDs */
466 qtd_t *head = dma_memalign(64, sizeof(qtd_t));
467 ehci_qh_t *qh = dma_memalign(64, sizeof(ehci_qh_t));
468 qtd_t *cur = head;
469 if (!qh || !head)
470 goto oom;
471 memset((void *)cur, 0, sizeof(qtd_t));
472 cur->token = QTD_ACTIVE |
473 (toggle?QTD_TOGGLE_DATA1:0) |
474 (EHCI_SETUP << QTD_PID_SHIFT) |
475 (3 << QTD_CERR_SHIFT);
476 if (fill_td(cur, devreq, drlen) != drlen) {
477 usb_debug("ERROR: couldn't send the entire device request\n");
478 }
479 qtd_t *next = dma_memalign(64, sizeof(qtd_t));
480 cur->next_qtd = virt_to_phys(next);
481 cur->alt_next_qtd = QTD_TERMINATE;
482 if (!next)
483 goto oom;
484
485 /* FIXME: We're limited to 16-20K (depending on alignment) for payload for now.
486 * Figure out, how toggle can be set sensibly in this scenario */
487 if (dalen > 0) {
488 toggle ^= 1;
489 cur = next;
490 memset((void *)cur, 0, sizeof(qtd_t));
491 cur->token = QTD_ACTIVE |
492 (toggle?QTD_TOGGLE_DATA1:0) |
493 (((dir == OUT)?EHCI_OUT:EHCI_IN) << QTD_PID_SHIFT) |
494 (3 << QTD_CERR_SHIFT);
495 if (fill_td(cur, data, dalen) != dalen) {
496 usb_debug("ERROR: couldn't send the entire control payload\n");
497 }
498 next = dma_memalign(64, sizeof(qtd_t));
499 if (!next)
500 goto oom;
501 cur->next_qtd = virt_to_phys(next);
502 cur->alt_next_qtd = QTD_TERMINATE;
503 }
504
505 toggle = 1;
506 cur = next;
507 memset((void *)cur, 0, sizeof(qtd_t));
508 cur->token = QTD_ACTIVE |
509 (toggle?QTD_TOGGLE_DATA1:QTD_TOGGLE_DATA0) |
510 ((dir == OUT)?EHCI_IN:EHCI_OUT) << QTD_PID_SHIFT |
511 (0 << QTD_CERR_SHIFT);
512 fill_td(cur, NULL, 0);
513 cur->next_qtd = virt_to_phys(0) | QTD_TERMINATE;
514 cur->alt_next_qtd = QTD_TERMINATE;
515
516 /* create QH */
517 memset((void *)qh, 0, sizeof(ehci_qh_t));
518 qh->horiz_link_ptr = virt_to_phys(qh) | QH_QH;
519 qh->epchar = dev->address |
520 (endp << QH_EP_SHIFT) |
521 (dev->speed << QH_EPS_SHIFT) |
522 (1 << QH_DTC_SHIFT) | /* ctrl transfers are special: take toggle bit from TD */
523 (1 << QH_RECLAIM_HEAD_SHIFT) |
524 (mlen << QH_MPS_SHIFT) |
525 (non_hs_ctrl_ep << QH_NON_HS_CTRL_EP_SHIFT) |
526 (0 << QH_NAK_CNT_SHIFT);
527 qh->epcaps = (3 << QH_PIPE_MULTIPLIER_SHIFT) |
528 (hubport << QH_PORT_NUMBER_SHIFT) |
529 (hubaddr << QH_HUB_ADDRESS_SHIFT);
530 qh->td.next_qtd = virt_to_phys(head);
531
532 result = ehci_process_async_schedule(
533 EHCI_INST(dev->controller), qh, head);
534 if (result >= 0) {
535 result = dalen - result;
536 if (dir == IN && data != src)
537 memcpy(src, data, result);
538 }
539
540 free_qh_and_tds(qh, head);
541 return result;
542
543 oom:
544 usb_debug("Not enough DMA memory for EHCI control structures!\n");
545 free_qh_and_tds(qh, head);
546 return -1;
547 }
548
549 typedef struct _intr_qtd_t intr_qtd_t;
550
551 struct _intr_qtd_t {
552 volatile qtd_t td;
553 u8 *data;
554 intr_qtd_t *next;
555 };
556
557 typedef struct {
558 volatile ehci_qh_t qh;
559 intr_qtd_t *head;
560 intr_qtd_t *tail;
561 intr_qtd_t *spare;
562 u8 *data;
563 endpoint_t *endp;
564 int reqsize;
565 } intr_queue_t;
566
fill_intr_queue_td(intr_queue_t * const intrq,intr_qtd_t * const intr_qtd,u8 * const data)567 static void fill_intr_queue_td(
568 intr_queue_t *const intrq,
569 intr_qtd_t *const intr_qtd,
570 u8 *const data)
571 {
572 const int pid = (intrq->endp->direction == IN) ? EHCI_IN
573 : (intrq->endp->direction == OUT) ? EHCI_OUT
574 : EHCI_SETUP;
575 const int cerr = (intrq->endp->dev->speed < 2) ? 1 : 0;
576
577 memset(intr_qtd, 0, sizeof(*intr_qtd));
578 intr_qtd->td.next_qtd = QTD_TERMINATE;
579 intr_qtd->td.alt_next_qtd = QTD_TERMINATE;
580 intr_qtd->td.token = QTD_ACTIVE |
581 (pid << QTD_PID_SHIFT) |
582 (cerr << QTD_CERR_SHIFT) |
583 ((intrq->endp->toggle & 1) << QTD_TOGGLE_SHIFT);
584 fill_td(&intr_qtd->td, data, intrq->reqsize);
585 intr_qtd->data = data;
586 intr_qtd->next = NULL;
587
588 intrq->endp->toggle ^= 1;
589 }
590
591 static void ehci_destroy_intr_queue(endpoint_t *const, void *const);
592
ehci_create_intr_queue(endpoint_t * const ep,const int reqsize,int reqcount,const int reqtiming)593 static void *ehci_create_intr_queue(
594 endpoint_t *const ep,
595 const int reqsize,
596 int reqcount,
597 const int reqtiming)
598 {
599 int i;
600
601 if ((reqsize > (4 * 4096 + 1)) || /* the maximum for arbitrary aligned
602 data in five 4096 byte pages */
603 (reqtiming > 1024))
604 return NULL;
605 if (reqcount < 2) /* we need at least 2:
606 one for processing, one for the hc to advance to */
607 reqcount = 2;
608
609 int hubaddr = 0, hubport = 0;
610 if (ep->dev->speed < 2) {
611 /* we need a split transaction */
612 if (closest_usb2_hub(ep->dev, &hubaddr, &hubport))
613 return NULL;
614 }
615
616 intr_queue_t *const intrq = (intr_queue_t *)dma_memalign(64,
617 sizeof(intr_queue_t));
618 /*
619 * reqcount data chunks
620 * plus one more spare, which we'll leave out of queue
621 */
622 u8 *data = (u8 *)dma_malloc(reqsize * (reqcount + 1));
623 if (!intrq || !data)
624 fatal("Not enough memory to create USB interrupt queue.\n");
625 intrq->data = data;
626 intrq->endp = ep;
627 intrq->reqsize = reqsize;
628
629 /* create #reqcount transfer descriptors (qTDs) */
630 intrq->head = (intr_qtd_t *)dma_memalign(64, sizeof(intr_qtd_t));
631 if (!intrq->head)
632 fatal("Not enough DMA memory to create #reqcount TD.\n");
633 intr_qtd_t *cur_td = intrq->head;
634 for (i = 0; i < reqcount; ++i) {
635 fill_intr_queue_td(intrq, cur_td, data);
636 data += reqsize;
637 if (i < reqcount - 1) {
638 /* create one more qTD */
639 intr_qtd_t *const next_td =
640 (intr_qtd_t *)dma_memalign(64, sizeof(intr_qtd_t));
641 if (!next_td)
642 fatal("Not enough DMA memory to create TD.\n");
643 cur_td->td.next_qtd = virt_to_phys(&next_td->td);
644 cur_td->next = next_td;
645 cur_td = next_td;
646 }
647 }
648 intrq->tail = cur_td;
649
650 /* create spare qTD */
651 intrq->spare = (intr_qtd_t *)dma_memalign(64, sizeof(intr_qtd_t));
652 if (!intrq->spare)
653 fatal("Not enough DMA memory to create spare qTD.\n");
654 intrq->spare->data = data;
655
656 /* initialize QH */
657 const int endp = ep->endpoint & 0xf;
658 memset((void *)&intrq->qh, 0, sizeof(intrq->qh));
659 intrq->qh.horiz_link_ptr = PS_TERMINATE;
660 intrq->qh.epchar = ep->dev->address |
661 (endp << QH_EP_SHIFT) |
662 (ep->dev->speed << QH_EPS_SHIFT) |
663 (1 << QH_DTC_SHIFT) |
664 (0 << QH_RECLAIM_HEAD_SHIFT) |
665 (ep->maxpacketsize << QH_MPS_SHIFT) |
666 (0 << QH_NAK_CNT_SHIFT);
667 intrq->qh.epcaps = (1 << QH_PIPE_MULTIPLIER_SHIFT) |
668 (hubport << QH_PORT_NUMBER_SHIFT) |
669 (hubaddr << QH_HUB_ADDRESS_SHIFT) |
670 (0xfe << QH_UFRAME_CMASK_SHIFT) |
671 1 /* uFrame S-mask */;
672 intrq->qh.td.next_qtd = virt_to_phys(&intrq->head->td);
673
674 /* insert QH into periodic schedule */
675 int nothing_placed = 1;
676 u32 *const ps = (u32 *)phys_to_virt(EHCI_INST(ep->dev->controller)
677 ->operation->periodiclistbase);
678 const u32 dummy_ptr = virt_to_phys(EHCI_INST(
679 ep->dev->controller)->dummy_qh) | PS_TYPE_QH;
680 for (i = 0; i < 1024; i += reqtiming) {
681 /* advance to the next free position */
682 while ((i < 1024) && (ps[i] != dummy_ptr)) ++i;
683 if (i < 1024) {
684 ps[i] = virt_to_phys(&intrq->qh) | PS_TYPE_QH;
685 nothing_placed = 0;
686 }
687 }
688 if (nothing_placed) {
689 usb_debug("Error: Failed to place ehci interrupt queue head "
690 "into periodic schedule: no space left\n");
691 ehci_destroy_intr_queue(ep, intrq);
692 return NULL;
693 }
694
695 return intrq;
696 }
697
ehci_destroy_intr_queue(endpoint_t * const ep,void * const queue)698 static void ehci_destroy_intr_queue(endpoint_t *const ep, void *const queue)
699 {
700 intr_queue_t *const intrq = (intr_queue_t *)queue;
701
702 /* remove QH from periodic schedule */
703 int i;
704 u32 *const ps = (u32 *)phys_to_virt(EHCI_INST(
705 ep->dev->controller)->operation->periodiclistbase);
706 const u32 dummy_ptr = virt_to_phys(EHCI_INST(
707 ep->dev->controller)->dummy_qh) | PS_TYPE_QH;
708 for (i = 0; i < 1024; ++i) {
709 if ((ps[i] & PS_PTR_MASK) == virt_to_phys(&intrq->qh))
710 ps[i] = dummy_ptr;
711 }
712
713 /* wait 1ms for frame to end */
714 mdelay(1);
715
716 while (intrq->head) {
717 /* disable qTD and destroy list */
718 intrq->head->td.next_qtd = QTD_TERMINATE;
719 intrq->head->td.token &= ~QTD_ACTIVE;
720
721 /* save and advance head ptr */
722 intr_qtd_t *const to_free = intrq->head;
723 intrq->head = intrq->head->next;
724
725 /* free current interrupt qTD */
726 free(to_free);
727 }
728 free(intrq->spare);
729 free(intrq->data);
730 free(intrq);
731 }
732
ehci_poll_intr_queue(void * const queue)733 static u8 *ehci_poll_intr_queue(void *const queue)
734 {
735 intr_queue_t *const intrq = (intr_queue_t *)queue;
736
737 u8 *ret = NULL;
738
739 /* process if head qTD is inactive AND QH has been moved forward */
740 if (!(intrq->head->td.token & QTD_ACTIVE)) {
741 if (!(intrq->head->td.token & QTD_STATUS_MASK))
742 ret = intrq->head->data;
743 else
744 usb_debug("ehci_poll_intr_queue: transfer failed, "
745 "status == 0x%02x\n",
746 intrq->head->td.token & QTD_STATUS_MASK);
747
748 /* insert spare qTD at the end and advance our tail ptr */
749 fill_intr_queue_td(intrq, intrq->spare, intrq->spare->data);
750 intrq->tail->td.next_qtd = virt_to_phys(&intrq->spare->td);
751 intrq->tail->next = intrq->spare;
752 intrq->tail = intrq->tail->next;
753
754 /* reuse executed qTD as spare one and advance our head ptr */
755 intrq->spare = intrq->head;
756 intrq->head = intrq->head->next;
757 }
758 /* reset queue if we fully processed it after underrun */
759 else if ((intrq->qh.td.next_qtd & QTD_TERMINATE) &&
760 /* to prevent race conditions:
761 not our head and not active */
762 (intrq->qh.current_td_ptr !=
763 virt_to_phys(&intrq->head->td)) &&
764 !(intrq->qh.td.token & QTD_ACTIVE)) {
765 usb_debug("resetting underrun ehci interrupt queue.\n");
766 intrq->qh.current_td_ptr = 0;
767 memset((void *)&intrq->qh.td, 0, sizeof(intrq->qh.td));
768 intrq->qh.td.next_qtd = virt_to_phys(&intrq->head->td);
769 }
770 return ret;
771 }
772
773 hci_t *
ehci_init(unsigned long physical_bar)774 ehci_init(unsigned long physical_bar)
775 {
776 int i;
777 hci_t *controller = new_controller();
778 controller->instance = xzalloc(sizeof(ehci_t));
779 controller->reg_base = (uintptr_t)physical_bar;
780 controller->type = EHCI;
781 controller->start = ehci_start;
782 controller->stop = ehci_stop;
783 controller->reset = ehci_reset;
784 controller->init = ehci_reinit;
785 controller->shutdown = ehci_shutdown;
786 controller->bulk = ehci_bulk;
787 controller->control = ehci_control;
788 controller->set_address = generic_set_address;
789 controller->finish_device_config = NULL;
790 controller->destroy_device = NULL;
791 controller->create_intr_queue = ehci_create_intr_queue;
792 controller->destroy_intr_queue = ehci_destroy_intr_queue;
793 controller->poll_intr_queue = ehci_poll_intr_queue;
794 init_device_entry(controller, 0);
795
796 EHCI_INST(controller)->capabilities = phys_to_virt(physical_bar);
797 EHCI_INST(controller)->operation = (hc_op_t *)(phys_to_virt(physical_bar) + EHCI_INST(controller)->capabilities->caplength);
798
799 /* Set the high address word (aka segment) if controller is 64-bit */
800 if (EHCI_INST(controller)->capabilities->hccparams & 1)
801 EHCI_INST(controller)->operation->ctrldssegment = 0;
802
803 /* Enable operation of controller */
804 controller->start(controller);
805
806 /* take over all ports. USB1 should be blind now */
807 EHCI_INST(controller)->operation->configflag = 1;
808
809 /* Initialize periodic frame list */
810 /* 1024 32-bit pointers, 4kb aligned */
811 u32 *const periodic_list = (u32 *)dma_memalign(4096, 1024 * sizeof(u32));
812 if (!periodic_list)
813 fatal("Not enough memory creating EHCI periodic frame list.\n");
814
815 if (dma_initialized()) {
816 EHCI_INST(controller)->dma_buffer = dma_memalign(4096, DMA_SIZE);
817 if (!EHCI_INST(controller)->dma_buffer)
818 fatal("Not enough DMA memory for EHCI bounce buffer.\n");
819 }
820
821 /*
822 * Insert dummy QH in periodic frame list
823 * This helps with broken host controllers
824 * and doesn't violate the standard.
825 */
826 EHCI_INST(controller)->dummy_qh = (ehci_qh_t *)dma_memalign(64, sizeof(ehci_qh_t));
827 if (!EHCI_INST(controller)->dummy_qh)
828 fatal("Not enough DMA memory for EHCI dummy TD.\n");
829 memset((void *)EHCI_INST(controller)->dummy_qh, 0,
830 sizeof(*EHCI_INST(controller)->dummy_qh));
831 EHCI_INST(controller)->dummy_qh->horiz_link_ptr = QH_TERMINATE;
832 EHCI_INST(controller)->dummy_qh->td.next_qtd = QH_TERMINATE;
833 EHCI_INST(controller)->dummy_qh->td.alt_next_qtd = QH_TERMINATE;
834 for (i = 0; i < 1024; ++i)
835 periodic_list[i] =
836 virt_to_phys(EHCI_INST(controller)->dummy_qh)
837 | PS_TYPE_QH;
838
839 /* Make sure periodic schedule is disabled */
840 ehci_set_periodic_schedule(EHCI_INST(controller), 0);
841 /* Set periodic frame list pointer */
842 EHCI_INST(controller)->operation->periodiclistbase =
843 virt_to_phys(periodic_list);
844 /* Enable use of periodic schedule */
845 ehci_set_periodic_schedule(EHCI_INST(controller), 1);
846
847 /* TODO lots of stuff missing */
848
849 controller->devices[0]->controller = controller;
850 controller->devices[0]->init = ehci_rh_init;
851 controller->devices[0]->init(controller->devices[0]);
852
853 return controller;
854 }
855
856 #if CONFIG(LP_USB_PCI)
857 hci_t *
ehci_pci_init(pcidev_t addr)858 ehci_pci_init(pcidev_t addr)
859 {
860 hci_t *controller;
861 u32 reg_base;
862
863 u16 pci_command = pci_read_config16(addr, PCI_COMMAND);
864 pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO;
865 pci_write_config16(addr, PCI_COMMAND, pci_command);
866
867 reg_base = pci_read_config32(addr, USBBASE);
868
869 /* default value for frame length adjust */
870 pci_write_config8(addr, FLADJ, FLADJ_framelength(60000));
871
872 controller = ehci_init((unsigned long)reg_base);
873
874 if (controller)
875 controller->pcidev = addr;
876
877 return controller;
878 }
879 #endif
880