1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 //=============================================================================
4 // Include Files
5 //=============================================================================
6 //#include <common.h>
7 //#include <ett_common.h>
8 //#include <test_case_controller.h>
9 //#include <api.h>
10 //#include "gpio.h"
11 //#include "ett_cust.h"
12 //#include "emi_setting.h"
13 //#include "pll.h"
14 //#include "dramc_pi_api.h"
15 #include <assert.h>
16 #include <print.h>
17 #include <string.h>
18 #include "dramc_common.h"
19 #include "dramc_int_global.h"
20
21 #include <emi_hw.h>
22 #include <emi.h>
23
24 #if !__FLASH_TOOL_DA__ && !__ETT__
25 #include "custom_emi.h" // fix build error: emi_settings
26 #endif
27
28 #if (FOR_DV_SIMULATION_USED==0)
29 #include <soc/mt6359p.h>
30 #include <soc/regulator.h>
31
32 /* now we can use definition MTK_PMIC_MT6359
33 * ==============================================================
34 * PMIC |Power |Dflt. Volt. |Step |Support FPWM |Cmt.
35 * --------------------------------------------------------------
36 * MT6359 |Vcore |0.8v |6.25mV |Yes |
37 * |Vm18 |1.8v |0.1V |No |
38 * --------------------------------------------------------------
39 * MT6360 |Vdram |1.125v |5mV |Yes |(DRAM Vdram)
40 * |Vmddr |0.75v |10mV |No |(AP Vdram)
41 * |Vddq |0.6v |10mV |No |
42 * ==============================================================
43 */
44 //#define MTK_PMIC_MT6359
45 #endif
46
47 #if !__ETT__
48 #define mt_reg_sync_write(x,y) mt_reg_sync_writel(y,x)
49 #endif
50 #define seclib_get_devinfo_with_index(x) 0
51
52 #ifdef MTK_PMIC_MT6359
53 #include <regulator/mtk_regulator.h>
54 #include <mt6359.h>
55 #endif
56
57 #include <soc/dramc_param.h>
58 #include <soc/emi.h>
59
60 //=============================================================================
61 // Definition
62 //=============================================================================
63
64 //=============================================================================
65 // Global Variables
66 //=============================================================================
67 int emi_setting_index = -1;
68
69 #ifdef MTK_PMIC_MT6359
70 static struct mtk_regulator reg_vio18, reg_vdram, reg_vcore, reg_vddq, reg_vmddr;
71 #endif
72
73 #ifdef LAST_DRAMC
74 static LAST_DRAMC_INFO_T* last_dramc_info_ptr;
75 #endif
76
77 #ifdef VOLTAGE_SEL
78 static VOLTAGE_SEL_INFO_T voltage_sel_info_ptr;
79 #endif
80
81 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
82 extern u64 get_part_addr(const char *name);
83 #endif
84
85 #if defined(SLT) && (!__ETT__)
86 #include <pl_version.h>
87 static u64 part_dram_data_addr_slt = 0;
88 int read_slt_data(DRAM_SLT_DATA_T *data);
89 int write_slt_data(DRAM_SLT_DATA_T *data);
90 int clean_slt_data(void);
91 #endif
92 //=============================================================================
93 // External references
94 //=============================================================================
95 extern char* opt_dle_value;
96
97 void print_DBG_info(DRAMC_CTX_T *p);
98
mdl_setting(DRAMC_CTX_T * p)99 void mdl_setting(DRAMC_CTX_T *p)
100 {
101 EMI_SETTINGS *emi_set;
102
103 if(emi_setting_index == -1)
104 emi_set = &default_emi_setting;
105 #if (FOR_DV_SIMULATION_USED==0)
106 else
107 emi_set = &emi_settings[emi_setting_index];
108 #endif
109
110 emi_init();
111
112 //The following is MDL settings
113 set_cen_emi_cona(emi_set->EMI_CONA_VAL);
114 set_cen_emi_conf(emi_set->EMI_CONF_VAL);
115 set_cen_emi_conh(emi_set->EMI_CONH_VAL);
116
117 // CHNA and CHNB uses the same CH0 setting
118 set_chn_emi_cona(emi_set->CHN0_EMI_CONA_VAL);
119 //set_chn_emi_conc(0x4);
120
121 p->vendor_id = emi_set->iLPDDR3_MODE_REG_5;
122 }
123
print_DBG_info(DRAMC_CTX_T * p)124 void print_DBG_info(DRAMC_CTX_T *p)
125 {
126 }
127
mt_get_dram_type(void)128 int mt_get_dram_type(void)
129 {
130 unsigned int dtype = mt_get_dram_type_from_hw_trap();
131
132 if (dtype == TYPE_LPDDR4X)
133 return DTYPE_LPDDR4X;
134 else
135 ASSERT(0);
136
137 return 0;
138 }
139
140 #ifdef DDR_RESERVE_MODE
141 extern u32 g_ddr_reserve_enable;
142 extern u32 g_ddr_reserve_success;
143 #define TIMEOUT 3
144 extern void before_Dramc_DDR_Reserved_Mode_setting(void);
145
146 #define CHAN_DRAMC_NAO_MISC_STATUSA(base) (base + 0x80)
147 #define SREF_STATE (1 << 16)
148
is_dramc_exit_slf(void)149 unsigned int is_dramc_exit_slf(void)
150 {
151 unsigned int ret;
152
153 ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_A_DRAMC_NAO_BASE_ADDRESS);
154 if ((ret & SREF_STATE) != 0) {
155 dramc_crit("DRAM CHAN-A is in self-refresh (MISC_STATUSA = 0x%x)\n", ret);
156 return 0;
157 }
158
159 ret = *(volatile unsigned *)CHAN_DRAMC_NAO_MISC_STATUSA(Channel_B_DRAMC_NAO_BASE_ADDRESS);
160 if ((ret & SREF_STATE) != 0) {
161 dramc_crit("DRAM CHAN-B is in self-refresh (MISC_STATUSA = 0x%x)\n", ret);
162 return 0;
163 }
164
165 dramc_crit("ALL DRAM CHAN is not in self-refresh\n");
166 return 1;
167 }
168
169 #endif
170
dramc_set_vcore_voltage(unsigned int vcore)171 unsigned int dramc_set_vcore_voltage(unsigned int vcore)
172 {
173 #ifdef MTK_PMIC_MT6359
174 return mtk_regulator_set_voltage(®_vcore, vcore, MAX_VCORE);
175 #endif
176 dramc_debug("%s set vcore to %d\n", __func__, vcore);
177 //mt6359p_buck_set_voltage(MT6359P_GPU11, vcore);
178
179 mainboard_set_regulator_voltage(MTK_REGULATOR_VCORE, vcore);
180
181 return 0;
182 }
183
dramc_get_vcore_voltage(void)184 unsigned int dramc_get_vcore_voltage(void)
185 {
186 #ifdef MTK_PMIC_MT6359
187 return mtk_regulator_get_voltage(®_vcore);
188 #else
189 return mainboard_get_regulator_voltage(MTK_REGULATOR_VCORE);
190 #endif
191 }
192
dramc_set_vdram_voltage(unsigned int ddr_type,unsigned int vdram)193 unsigned int dramc_set_vdram_voltage(unsigned int ddr_type, unsigned int vdram)
194 {
195 #ifdef MTK_PMIC_MT6359
196 mtk_regulator_set_voltage(®_vdram, vdram, MAX_VDRAM);
197 #endif
198 mainboard_set_regulator_voltage(MTK_REGULATOR_VDD2, vdram);
199 return 0;
200 }
201
dramc_get_vdram_voltage(unsigned int ddr_type)202 unsigned int dramc_get_vdram_voltage(unsigned int ddr_type)
203 {
204 #ifdef MTK_PMIC_MT6359
205 return mtk_regulator_get_voltage(®_vdram);
206 #else
207 return mainboard_get_regulator_voltage(MTK_REGULATOR_VDD2);
208 #endif
209 }
210
dramc_set_vddq_voltage(unsigned int ddr_type,unsigned int vddq)211 unsigned int dramc_set_vddq_voltage(unsigned int ddr_type, unsigned int vddq)
212 {
213 #ifdef MTK_PMIC_MT6359
214 mtk_regulator_set_voltage(®_vddq, vddq, MAX_VDDQ);
215 #endif
216 mainboard_set_regulator_voltage(MTK_REGULATOR_VDDQ, vddq);
217 return 0;
218 }
219
dramc_get_vddq_voltage(unsigned int ddr_type)220 unsigned int dramc_get_vddq_voltage(unsigned int ddr_type)
221 {
222 #ifdef MTK_PMIC_MT6359
223 return mtk_regulator_get_voltage(®_vddq);
224 #else
225 return mainboard_get_regulator_voltage(MTK_REGULATOR_VDDQ);
226 #endif
227 }
228
dramc_set_vmddr_voltage(unsigned int vmddr)229 unsigned int dramc_set_vmddr_voltage(unsigned int vmddr)
230 {
231 #ifdef MTK_PMIC_MT6359
232 return mtk_regulator_set_voltage(®_vmddr, vmddr, MAX_VMDDR);
233 #endif
234 mainboard_set_regulator_voltage(MTK_REGULATOR_VMDDR, vmddr);
235 return 0;
236 }
237
dramc_get_vmddr_voltage(void)238 unsigned int dramc_get_vmddr_voltage(void)
239 {
240 #ifdef MTK_PMIC_MT6359
241 return mtk_regulator_get_voltage(®_vmddr);
242 #else
243 return mainboard_get_regulator_voltage(MTK_REGULATOR_VMDDR);
244 #endif
245 }
246
dramc_set_vio18_voltage(unsigned int vio18)247 unsigned int dramc_set_vio18_voltage(unsigned int vio18)
248 {
249 #ifdef MTK_PMIC_MT6359
250 unsigned int twist = vio18 % UNIT_VIO18_STEP / UNIT_VIO18;
251 vio18 -= vio18 % UNIT_VIO18_STEP;
252 pmic_config_interface(PMIC_RG_VM18_VOCAL_ADDR, twist, PMIC_RG_VM18_VOCAL_MASK, PMIC_RG_VM18_VOCAL_SHIFT);
253 return mtk_regulator_set_voltage(®_vio18, vio18, MAX_VIO18);
254 #else
255 mainboard_set_regulator_voltage(MTK_REGULATOR_VDD1, vio18);
256 return 0;
257 #endif
258 }
259
260
dramc_get_vio18_voltage(void)261 unsigned int dramc_get_vio18_voltage(void)
262 {
263 #ifdef MTK_PMIC_MT6359
264 unsigned int twist = 0;
265 pmic_read_interface(PMIC_RG_VM18_VOCAL_ADDR, &twist, PMIC_RG_VM18_VOCAL_MASK, PMIC_RG_VM18_VOCAL_SHIFT);
266 return mtk_regulator_get_voltage(®_vio18) + twist * UNIT_VIO18;
267 #else
268 return mainboard_get_regulator_voltage(MTK_REGULATOR_VDD1);
269 #endif
270 }
271
272 #define GPIO_TRAPPING_REG (0x100056f0)
is_discrete_lpddr4(void)273 unsigned int is_discrete_lpddr4(void)
274 {
275 unsigned int type, ret;
276
277 type = get_ddr_type();
278
279 ret = (type == DDR_TYPE_DISCRETE) ? 1 : 0;
280 dramc_debug("%s: %d\n", __func__, ret);
281
282 return ret;
283 }
284
mt_get_dram_type_from_hw_trap(void)285 unsigned int mt_get_dram_type_from_hw_trap(void)
286 {
287 return TYPE_LPDDR4X;
288 }
289
setup_dramc_voltage_by_pmic(void)290 void setup_dramc_voltage_by_pmic(void)
291 {
292 #ifdef VOLTAGE_SEL
293 int vcore;
294 #endif
295 #ifdef MTK_PMIC_MT6359
296 int ret;
297
298 ret = mtk_regulator_get("vm18", ®_vio18);
299 if (ret)
300 dramc_debug("mtk_regulator_get vio18 fail\n");
301
302 ret = mtk_regulator_get("vcore", ®_vcore);
303 if (ret)
304 dramc_debug("mtk_regulator_get vcore fail\n");
305
306 ret = mtk_regulator_get("VDRAM1", ®_vdram);
307 if (ret)
308 printf("mtk_regulator_get vdram fail\n");
309
310 ret = mtk_regulator_get("VDRAM2", ®_vddq);
311 if (ret)
312 printf("mtk_regulator_get vddq fail\n");
313
314 ret = mtk_regulator_get("VMDDR", ®_vmddr);
315 if (ret)
316 printf("mtk_regulator_get vmddr fail\n");
317
318 mtk_regulator_set_mode(®_vcore, 0x1);
319 mtk_regulator_set_mode(®_vdram, 0x1);
320
321 #ifdef VOLTAGE_SEL
322 dramc_set_vio18_voltage(vio18_voltage_select());
323 #else
324 dramc_set_vio18_voltage(SEL_VIO18);
325 #endif
326 #if defined(VCORE_BIN)
327 #ifdef VOLTAGE_SEL
328 vcore = vcore_voltage_select(KSHU0);
329 if (vcore)
330 dramc_set_vcore_voltage(vcore);
331 else
332 #endif
333 dramc_set_vcore_voltage(get_vcore_uv_table(0));
334 #else
335 #ifdef VOLTAGE_SEL
336 dramc_set_vcore_voltage(vcore_voltage_select(KSHU0));
337 #else
338 dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP4, KSHU0));
339 #endif
340 #endif
341 #ifdef VOLTAGE_SEL
342 dramc_set_vdram_voltage(TYPE_LPDDR4, vdram_voltage_select());
343 #else
344 dramc_set_vdram_voltage(TYPE_LPDDR4, SEL_PREFIX_VDRAM(LP4));
345 #endif
346
347 #ifdef VOLTAGE_SEL
348 dramc_set_vddq_voltage(TYPE_LPDDR4, vddq_voltage_select());
349 #else
350 dramc_set_vddq_voltage(TYPE_LPDDR4, SEL_PREFIX_VDDQ);
351 #endif
352
353 #ifdef VOLTAGE_SEL
354 dramc_set_vmddr_voltage(vmddr_voltage_select());
355 #else
356 dramc_set_vmddr_voltage(SEL_PREFIX_VMDDR);
357 #endif
358
359 dramc_debug("Vio18 = %d\n", dramc_get_vio18_voltage());
360 dramc_debug("Vcore = %d\n", dramc_get_vcore_voltage());
361 dramc_debug("Vdram = %d\n", dramc_get_vdram_voltage(TYPE_LPDDR4));
362 dramc_debug("Vddq = %d\n", dramc_get_vddq_voltage(TYPE_LPDDR4));
363 dramc_debug("Vmddr = %d\n", dramc_get_vmddr_voltage());
364 #endif
365 }
366
restore_vcore_setting(void)367 static void restore_vcore_setting(void)
368 {
369 #ifdef VOLTAGE_SEL
370 int vcore;
371 #endif
372 #ifdef MTK_PMIC_MT6359
373 int ret;
374
375 ret = mtk_regulator_get("vcore", ®_vcore);
376 if (ret)
377 printf("mtk_regulator_get vcore fail\n");
378
379 #if defined(VCORE_BIN)
380 #ifdef VOLTAGE_SEL
381 vcore = vcore_voltage_select(KSHU0);
382 if ((doe_get_config("dram_fix_3094_0825")) || (doe_get_config("dram_all_3094_0825")) || (doe_get_config("dram_opp0_3733_others_3094_0825")))
383 dramc_set_vcore_voltage(825000);
384 else if (doe_get_config("dram_fix_3094_0725") || (doe_get_config("dram_fix_2400_0725")) || (doe_get_config("dram_fix_1534_0725")) || (doe_get_config("dram_fix_1200_0725")) || (doe_get_config("dram_all_3094_0725")) || (doe_get_config("dram_all_1534_0725")) || (doe_get_config("dram_opp0_3094_others_1534_0725")) || (doe_get_config("dram_opp0_2400_others_1534_0725")))
385 dramc_set_vcore_voltage(725000);
386 else if ((doe_get_config("dram_fix_1200_065")) || (doe_get_config("dram_fix_800_065")))
387 dramc_set_vcore_voltage(650000);
388 else if (vcore)
389 dramc_set_vcore_voltage(vcore);
390 else
391 #endif
392 dramc_set_vcore_voltage(get_vcore_uv_table(0));
393 #else
394 #ifdef VOLTAGE_SEL
395 dramc_set_vcore_voltage(vcore_voltage_select(KSHU0));
396 #else
397 dramc_set_vcore_voltage(SEL_PREFIX_VCORE(LP4, KSHU0));
398 #endif
399 #endif
400
401 dramc_debug("Vcore = %d\n", dramc_get_vcore_voltage());
402 #endif
403 }
404
switch_dramc_voltage_to_auto_mode(void)405 void switch_dramc_voltage_to_auto_mode(void)
406 {
407 #ifdef MTK_PMIC_MT6359
408 mtk_regulator_set_mode(®_vcore, 0x0);
409 mtk_regulator_set_mode(®_vdram, 0x0);
410 #endif
411 }
412
413 #ifdef COMBO_MCP
mt_get_mdl_number(void)414 static int mt_get_mdl_number(void)
415 {
416 static int mdl_number = -1;
417
418 mdl_number = get_ddr_geometry();
419
420 return mdl_number;
421 }
422 #endif
423
get_dram_channel_support_nr(void)424 int get_dram_channel_support_nr(void)
425 {
426 return DRAMC_MAX_CH;
427 }
428
get_dram_channel_nr(void)429 int get_dram_channel_nr(void)
430 {
431 return get_channel_nr_by_emi();
432 }
433
get_dram_rank_nr(void)434 int get_dram_rank_nr(void)
435 {
436 int index;
437 int cen_emi_cona;
438
439 #ifdef COMBO_MCP
440 #ifdef DDR_RESERVE_MODE
441 if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1) {
442 return get_rank_nr_by_emi();
443 } else
444 #endif
445 {
446 index = mt_get_mdl_number();
447 if (index < 0 || index >= num_of_emi_records)
448 return 0;
449
450 cen_emi_cona = emi_settings[index].EMI_CONA_VAL;
451 }
452 #else
453 cen_emi_cona = default_emi_setting.EMI_CONA_VAL;
454 #endif
455
456 if ((cen_emi_cona & (1 << 17)) != 0 || //for channel 0
457 (cen_emi_cona & (1 << 16)) != 0 ) //for channel 1
458 return 2;
459 else
460 return 1;
461 }
462
get_dram_mr_cnt(void)463 int get_dram_mr_cnt(void)
464 {
465 return DRAMC_MR_CNT;
466 }
467
get_dram_freq_cnt(void)468 int get_dram_freq_cnt(void)
469 {
470 return DRAMC_FREQ_CNT;
471 }
472
473 #if (FOR_DV_SIMULATION_USED==0)
474 #if !__FLASH_TOOL_DA__ && !__ETT__
475
get_dram_rank_size(u64 dram_rank_size[])476 void get_dram_rank_size(u64 dram_rank_size[])
477 {
478 #ifdef COMBO_MCP
479 int index, rank_nr, i;
480
481 #ifdef DDR_RESERVE_MODE
482 if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==1)
483 {
484 get_rank_size_by_emi(dram_rank_size);
485 }
486 else
487 #endif
488 {
489 index = mt_get_mdl_number();
490
491 if (index < 0 || index >= num_of_emi_records)
492 {
493 return;
494 }
495
496 rank_nr = get_dram_rank_nr();
497
498 for(i = 0; i < rank_nr; i++){
499 dram_rank_size[i] = emi_settings[index].DRAM_RANK_SIZE[i];
500 dramc_debug("%d:dram_rank_size:%llx\n",i,dram_rank_size[i]);
501 }
502 }
503 return;
504 #else
505 get_rank_size_by_emi(dram_rank_size);
506 return;
507 #endif
508 }
509
get_dram_freq_step(u32 dram_freq_step[])510 void get_dram_freq_step(u32 dram_freq_step[])
511 {
512 unsigned int i;
513 unsigned int defined_step[DRAMC_FREQ_CNT] = {
514 4266, 3200, 2400, 1866, 1600, 1200, 800};
515
516 if (is_discrete_lpddr4()) {
517 defined_step[0] = 3200;
518 }
519 for (i = 0; i < DRAMC_FREQ_CNT; i++) {
520 dram_freq_step[i] = defined_step[i];
521 }
522 }
523
set_dram_mr(unsigned int index,unsigned short value)524 void set_dram_mr(unsigned int index, unsigned short value)
525 {
526 #if 0
527 unsigned short value_2rk;
528
529 value_2rk = value & 0xFF;
530 value_2rk |= (value_2rk << 8);
531
532 switch (index) {
533 case 5:
534 mr5 = value_2rk;
535 break;
536 case 6:
537 mr6 = value_2rk;
538 break;
539 case 7:
540 mr7 = value_2rk;
541 break;
542 case 8:
543 mr8 = value;
544 default:
545 break;
546 }
547 #endif
548 }
549
get_dram_mr(unsigned int index)550 unsigned short get_dram_mr(unsigned int index)
551 {
552 unsigned int value = 0;
553 #if 0
554 switch (index) {
555 case 5:
556 value = last_dramc_info_ptr->mr5;
557 break;
558 case 6:
559 value = last_dramc_info_ptr->mr6;
560 break;
561 case 7:
562 value = last_dramc_info_ptr->mr7;
563 break;
564 case 8:
565 value = last_dramc_info_ptr->mr8;
566 default:
567 break;
568 }
569 return (unsigned short)(value & 0xFFFF);
570 #else
571 return (unsigned short)(value & 0xFFFF);
572 #endif
573 }
574
get_dram_mr_info(struct mr_info_t mr_info[])575 void get_dram_mr_info(struct mr_info_t mr_info[])
576 {
577 #if 0
578 unsigned int i;
579 unsigned int mr_list[DRAMC_MR_CNT] = {5, 6, 7, 8};
580
581 for (i = 0; i < DRAMC_MR_CNT; i++) {
582 mr_info[i].mr_index = mr_list[i];
583 mr_info[i].mr_value = get_dram_mr(mr_list[i]);
584 }
585 #endif
586 }
587
588 #endif //#if !__FLASH_TOOL_DA__ && !__ETT__
589 #endif
590
freq_table_are_all_3094(void)591 static void freq_table_are_all_3094(void)
592 {
593 gFreqTbl[0].freq_sel = LP4_DDR3200;
594 gFreqTbl[0].divmode = DIV8_MODE;
595 gFreqTbl[0].shuffleIdx = SRAM_SHU1;
596 gFreqTbl[0].duty_calibration_mode = DUTY_NEED_K;
597 gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON;
598 gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE;
599
600 gFreqTbl[1].freq_sel = LP4_DDR3200;
601 gFreqTbl[1].divmode = DIV8_MODE;
602 gFreqTbl[1].shuffleIdx = SRAM_SHU3;
603 gFreqTbl[1].duty_calibration_mode = DUTY_NEED_K;
604 gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON;
605 gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE;
606
607 gFreqTbl[2].freq_sel = LP4_DDR3200;
608 gFreqTbl[2].divmode = DIV8_MODE;
609 gFreqTbl[2].shuffleIdx = SRAM_SHU2;
610 gFreqTbl[2].duty_calibration_mode = DUTY_NEED_K;
611 gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON;
612 gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE;
613
614 gFreqTbl[3].freq_sel = LP4_DDR3200;
615 gFreqTbl[3].divmode = DIV8_MODE;
616 gFreqTbl[3].shuffleIdx = SRAM_SHU0;
617 gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K;
618 gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON;
619 gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE;
620
621 gFreqTbl[4].freq_sel = LP4_DDR3200;
622 gFreqTbl[4].divmode = DIV8_MODE;
623 gFreqTbl[4].shuffleIdx = SRAM_SHU5;
624 gFreqTbl[4].duty_calibration_mode = DUTY_NEED_K;
625 gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON;
626 gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE;
627
628 gFreqTbl[5].freq_sel = LP4_DDR3200;
629 gFreqTbl[5].divmode = DIV8_MODE;
630 gFreqTbl[5].shuffleIdx = SRAM_SHU4;
631 gFreqTbl[5].duty_calibration_mode = DUTY_NEED_K;
632 gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON;
633 gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE;
634
635 gFreqTbl[6].freq_sel = LP4_DDR3200;
636 gFreqTbl[6].divmode = DIV8_MODE;
637 gFreqTbl[6].shuffleIdx = SRAM_SHU6;
638 gFreqTbl[6].duty_calibration_mode = DUTY_NEED_K;
639 gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON;
640 gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE;
641
642 }
643
freq_table_are_all_1534(void)644 static void freq_table_are_all_1534(void)
645 {
646 gFreqTbl[0].freq_sel = LP4_DDR1600;
647 gFreqTbl[0].divmode = DIV8_MODE;
648 gFreqTbl[0].shuffleIdx = SRAM_SHU1;
649 gFreqTbl[0].duty_calibration_mode = DUTY_DEFAULT;
650 gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON;
651 gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE;
652
653 gFreqTbl[1].freq_sel = LP4_DDR1600;
654 gFreqTbl[1].divmode = DIV8_MODE;
655 gFreqTbl[1].shuffleIdx = SRAM_SHU3;
656 gFreqTbl[1].duty_calibration_mode = DUTY_DEFAULT;
657 gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON;
658 gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE;
659
660 gFreqTbl[2].freq_sel = LP4_DDR1600;
661 gFreqTbl[2].divmode = DIV8_MODE;
662 gFreqTbl[2].shuffleIdx = SRAM_SHU2;
663 gFreqTbl[2].duty_calibration_mode = DUTY_DEFAULT;
664 gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON;
665 gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE;
666
667 gFreqTbl[3].freq_sel = LP4_DDR1600;
668 gFreqTbl[3].divmode = DIV8_MODE;
669 gFreqTbl[3].shuffleIdx = SRAM_SHU0;
670 gFreqTbl[3].duty_calibration_mode = DUTY_DEFAULT;
671 gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON;
672 gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE;
673
674 gFreqTbl[4].freq_sel = LP4_DDR1600;
675 gFreqTbl[4].divmode = DIV8_MODE;
676 gFreqTbl[4].shuffleIdx = SRAM_SHU5;
677 gFreqTbl[4].duty_calibration_mode = DUTY_DEFAULT;
678 gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON;
679 gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE;
680
681 gFreqTbl[5].freq_sel = LP4_DDR1600;
682 gFreqTbl[5].divmode = DIV8_MODE;
683 gFreqTbl[5].shuffleIdx = SRAM_SHU4;
684 gFreqTbl[5].duty_calibration_mode = DUTY_DEFAULT;
685 gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON;
686 gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE;
687
688 gFreqTbl[6].freq_sel = LP4_DDR1600;
689 gFreqTbl[6].divmode = DIV8_MODE;
690 gFreqTbl[6].shuffleIdx = SRAM_SHU6;
691 gFreqTbl[6].duty_calibration_mode = DUTY_DEFAULT;
692 gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON;
693 gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE;
694
695 }
696
freq_table_opp0_3733_others_3094(void)697 static void freq_table_opp0_3733_others_3094(void)
698 {
699 gFreqTbl[0].freq_sel = LP4_DDR3200;
700 gFreqTbl[0].divmode = DIV8_MODE;
701 gFreqTbl[0].shuffleIdx = SRAM_SHU1;
702 gFreqTbl[0].duty_calibration_mode = DUTY_NEED_K;
703 gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON;
704 gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE;
705
706 gFreqTbl[1].freq_sel = LP4_DDR3200;
707 gFreqTbl[1].divmode = DIV8_MODE;
708 gFreqTbl[1].shuffleIdx = SRAM_SHU3;
709 gFreqTbl[1].duty_calibration_mode = DUTY_NEED_K;
710 gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON;
711 gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE;
712
713 gFreqTbl[2].freq_sel = LP4_DDR3200;
714 gFreqTbl[2].divmode = DIV8_MODE;
715 gFreqTbl[2].shuffleIdx = SRAM_SHU2;
716 gFreqTbl[2].duty_calibration_mode = DUTY_NEED_K;
717 gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON;
718 gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE;
719
720 gFreqTbl[3].freq_sel = LP4_DDR3733;
721 gFreqTbl[3].divmode = DIV8_MODE;
722 gFreqTbl[3].shuffleIdx = SRAM_SHU0;
723 gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K;
724 gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON;
725 gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE;
726
727 gFreqTbl[4].freq_sel = LP4_DDR3200;
728 gFreqTbl[4].divmode = DIV8_MODE;
729 gFreqTbl[4].shuffleIdx = SRAM_SHU5;
730 gFreqTbl[4].duty_calibration_mode = DUTY_NEED_K;
731 gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON;
732 gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE;
733
734 gFreqTbl[5].freq_sel = LP4_DDR3200;
735 gFreqTbl[5].divmode = DIV8_MODE;
736 gFreqTbl[5].shuffleIdx = SRAM_SHU4;
737 gFreqTbl[5].duty_calibration_mode = DUTY_NEED_K;
738 gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON;
739 gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE;
740
741 gFreqTbl[6].freq_sel = LP4_DDR3200;
742 gFreqTbl[6].divmode = DIV8_MODE;
743 gFreqTbl[6].shuffleIdx = SRAM_SHU6;
744 gFreqTbl[6].duty_calibration_mode = DUTY_NEED_K;
745 gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON;
746 gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE;
747 }
748
freq_table_opp0_3094_others_1534(void)749 static void freq_table_opp0_3094_others_1534(void)
750 {
751 gFreqTbl[0].freq_sel = LP4_DDR1600;
752 gFreqTbl[0].divmode = DIV8_MODE;
753 gFreqTbl[0].shuffleIdx = SRAM_SHU1;
754 gFreqTbl[0].duty_calibration_mode = DUTY_DEFAULT;
755 gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON;
756 gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE;
757
758 gFreqTbl[1].freq_sel = LP4_DDR1600;
759 gFreqTbl[1].divmode = DIV8_MODE;
760 gFreqTbl[1].shuffleIdx = SRAM_SHU3;
761 gFreqTbl[1].duty_calibration_mode = DUTY_DEFAULT;
762 gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON;
763 gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE;
764
765 gFreqTbl[2].freq_sel = LP4_DDR1600;
766 gFreqTbl[2].divmode = DIV8_MODE;
767 gFreqTbl[2].shuffleIdx = SRAM_SHU2;
768 gFreqTbl[2].duty_calibration_mode = DUTY_DEFAULT;
769 gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON;
770 gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE;
771
772 gFreqTbl[3].freq_sel = LP4_DDR3200;
773 gFreqTbl[3].divmode = DIV8_MODE;
774 gFreqTbl[3].shuffleIdx = SRAM_SHU0;
775 gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K;
776 gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON;
777 gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE;
778
779 gFreqTbl[4].freq_sel = LP4_DDR1600;
780 gFreqTbl[4].divmode = DIV8_MODE;
781 gFreqTbl[4].shuffleIdx = SRAM_SHU5;
782 gFreqTbl[4].duty_calibration_mode = DUTY_DEFAULT;
783 gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON;
784 gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE;
785
786 gFreqTbl[5].freq_sel = LP4_DDR1600;
787 gFreqTbl[5].divmode = DIV8_MODE;
788 gFreqTbl[5].shuffleIdx = SRAM_SHU4;
789 gFreqTbl[5].duty_calibration_mode = DUTY_DEFAULT;
790 gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON;
791 gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE;
792
793 gFreqTbl[6].freq_sel = LP4_DDR1600;
794 gFreqTbl[6].divmode = DIV8_MODE;
795 gFreqTbl[6].shuffleIdx = SRAM_SHU6;
796 gFreqTbl[6].duty_calibration_mode = DUTY_DEFAULT;
797 gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON;
798 gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE;
799 }
800
freq_table_opp0_2400_others_1534(void)801 static void freq_table_opp0_2400_others_1534(void)
802 {
803 gFreqTbl[0].freq_sel = LP4_DDR1600;
804 gFreqTbl[0].divmode = DIV8_MODE;
805 gFreqTbl[0].shuffleIdx = SRAM_SHU1;
806 gFreqTbl[0].duty_calibration_mode = DUTY_DEFAULT;
807 gFreqTbl[0].vref_calibartion_enable = VREF_CALI_ON;
808 gFreqTbl[0].ddr_loop_mode = CLOSE_LOOP_MODE;
809
810 gFreqTbl[1].freq_sel = LP4_DDR1600;
811 gFreqTbl[1].divmode = DIV8_MODE;
812 gFreqTbl[1].shuffleIdx = SRAM_SHU3;
813 gFreqTbl[1].duty_calibration_mode = DUTY_DEFAULT;
814 gFreqTbl[1].vref_calibartion_enable = VREF_CALI_ON;
815 gFreqTbl[1].ddr_loop_mode = CLOSE_LOOP_MODE;
816
817 gFreqTbl[2].freq_sel = LP4_DDR1600;
818 gFreqTbl[2].divmode = DIV8_MODE;
819 gFreqTbl[2].shuffleIdx = SRAM_SHU2;
820 gFreqTbl[2].duty_calibration_mode = DUTY_DEFAULT;
821 gFreqTbl[2].vref_calibartion_enable = VREF_CALI_ON;
822 gFreqTbl[2].ddr_loop_mode = CLOSE_LOOP_MODE;
823
824 gFreqTbl[3].freq_sel = LP4_DDR2400;
825 gFreqTbl[3].divmode = DIV8_MODE;
826 gFreqTbl[3].shuffleIdx = SRAM_SHU0;
827 gFreqTbl[3].duty_calibration_mode = DUTY_NEED_K;
828 gFreqTbl[3].vref_calibartion_enable = VREF_CALI_ON;
829 gFreqTbl[3].ddr_loop_mode = CLOSE_LOOP_MODE;
830
831 gFreqTbl[4].freq_sel = LP4_DDR1600;
832 gFreqTbl[4].divmode = DIV8_MODE;
833 gFreqTbl[4].shuffleIdx = SRAM_SHU5;
834 gFreqTbl[4].duty_calibration_mode = DUTY_DEFAULT;
835 gFreqTbl[4].vref_calibartion_enable = VREF_CALI_ON;
836 gFreqTbl[4].ddr_loop_mode = CLOSE_LOOP_MODE;
837
838 gFreqTbl[5].freq_sel = LP4_DDR1600;
839 gFreqTbl[5].divmode = DIV8_MODE;
840 gFreqTbl[5].shuffleIdx = SRAM_SHU4;
841 gFreqTbl[5].duty_calibration_mode = DUTY_DEFAULT;
842 gFreqTbl[5].vref_calibartion_enable = VREF_CALI_ON;
843 gFreqTbl[5].ddr_loop_mode = CLOSE_LOOP_MODE;
844
845 gFreqTbl[6].freq_sel = LP4_DDR1600;
846 gFreqTbl[6].divmode = DIV8_MODE;
847 gFreqTbl[6].shuffleIdx = SRAM_SHU6;
848 gFreqTbl[6].duty_calibration_mode = DUTY_DEFAULT;
849 gFreqTbl[6].vref_calibartion_enable = VREF_CALI_ON;
850 gFreqTbl[6].ddr_loop_mode = CLOSE_LOOP_MODE;
851 }
852 #if (CFG_DRAM_LOG_TO_STORAGE)
853
854 extern u64 get_part_addr(const char *name);
855 u64 part_dram_data_addr_uart = 0;
856 u32 log_start = 0;
857 static char logbuf[1024];
858 static int logcount;
859 #endif
860
861 #ifdef VOLTAGE_SEL
update_voltage_select_info(void)862 void update_voltage_select_info(void)
863 {
864 voltage_sel_info_ptr.vcore = doe_get_config("vcore");
865 voltage_sel_info_ptr.vdram = doe_get_config("vdram");
866 voltage_sel_info_ptr.vddq = doe_get_config("vddq");
867 voltage_sel_info_ptr.vmddr = doe_get_config("vmddr");
868 voltage_sel_info_ptr.vio18 = doe_get_config("vio18");
869
870 print("DOE setting: vcore %d, vdram %d, vddq %d, vmddr %d, vio18 %d \n",
871 voltage_sel_info_ptr.vcore, voltage_sel_info_ptr.vdram,
872 voltage_sel_info_ptr.vddq, voltage_sel_info_ptr.vmddr,
873 voltage_sel_info_ptr.vio18);
874 }
875
vio18_voltage_select()876 int vio18_voltage_select()
877 {
878 if (voltage_sel_info_ptr.vio18 == LEVEL_LV) {
879 return HQA_VIO18_LV;
880 } else if (voltage_sel_info_ptr.vio18 == LEVEL_HV) {
881 return HQA_VIO18_HV;
882 } else {
883 return HQA_VIO18_NV;
884 }
885 }
886
vmddr_voltage_select()887 int vmddr_voltage_select()
888 {
889 if (voltage_sel_info_ptr.vmddr == LEVEL_LV) {
890 return HQA_VMDDR_LV_LP4;
891 } else if (voltage_sel_info_ptr.vmddr == LEVEL_HV) {
892 return HQA_VMDDR_HV_LP4;
893 } else {
894 return HQA_VMDDR_NV_LP4;
895 }
896 }
897
vddq_voltage_select()898 int vddq_voltage_select()
899 {
900 if (voltage_sel_info_ptr.vddq == LEVEL_LV) {
901 return HQA_VDDQ_LV_LP4;
902 } else if (voltage_sel_info_ptr.vddq == LEVEL_HV) {
903 return HQA_VDDQ_HV_LP4;
904 } else {
905 return HQA_VDDQ_NV_LP4;
906 }
907 }
908
vdram_voltage_select(void)909 int vdram_voltage_select(void)
910 {
911 if (voltage_sel_info_ptr.vdram == LEVEL_LV) {
912 return HQA_VDRAM_LV_LP4;
913 } else if (voltage_sel_info_ptr.vdram == LEVEL_HV) {
914 return HQA_VDRAM_HV_LP4;
915 } else {
916 return HQA_VDRAM_NV_LP4;
917 }
918 }
919
vcore_voltage_select(DRAM_KSHU kshu)920 int vcore_voltage_select(DRAM_KSHU kshu)
921 {
922 int ret = 0;
923 if (voltage_sel_info_ptr.vcore == LEVEL_LV) {
924 switch(kshu) {
925 case KSHU0:
926 ret = HQA_VCORE_LV_LP4_KSHU0_PL;
927 break;
928 case KSHU1:
929 ret = HQA_VCORE_LV_LP4_KSHU1_PL;
930 break;
931 case KSHU2:
932 ret = HQA_VCORE_LV_LP4_KSHU2_PL;
933 break;
934 case KSHU3:
935 ret = HQA_VCORE_LV_LP4_KSHU3_PL;
936 break;
937 case KSHU4:
938 ret = HQA_VCORE_LV_LP4_KSHU4_PL;
939 break;
940 case KSHU5:
941 ret = HQA_VCORE_LV_LP4_KSHU5_PL;
942 break;
943 case KSHU6:
944 ret = HQA_VCORE_LV_LP4_KSHU6_PL;
945 break;
946 };
947 } else if (voltage_sel_info_ptr.vcore == LEVEL_HV) {
948 switch(kshu) {
949 case KSHU0:
950 ret = HQA_VCORE_HV_LP4_KSHU0_PL;
951 break;
952 case KSHU1:
953 ret = HQA_VCORE_HV_LP4_KSHU1_PL;
954 break;
955 case KSHU2:
956 ret = HQA_VCORE_HV_LP4_KSHU2_PL;
957 break;
958 case KSHU3:
959 ret = HQA_VCORE_HV_LP4_KSHU3_PL;
960 break;
961 case KSHU4:
962 ret = HQA_VCORE_HV_LP4_KSHU4_PL;
963 break;
964 case KSHU5:
965 ret = HQA_VCORE_HV_LP4_KSHU5_PL;
966 break;
967 case KSHU6:
968 ret = HQA_VCORE_HV_LP4_KSHU6_PL;
969 break;
970 };
971 } else {
972 #if defined(VCORE_BIN)
973 ret = 0;
974 #else
975 switch(kshu) {
976 case KSHU0:
977 ret = HQA_VCORE_NV_LP4_KSHU0_PL;
978 break;
979 case KSHU1:
980 ret = HQA_VCORE_NV_LP4_KSHU1_PL;
981 break;
982 case KSHU2:
983 ret = HQA_VCORE_NV_LP4_KSHU2_PL;
984 break;
985 case KSHU3:
986 ret = HQA_VCORE_NV_LP4_KSHU3_PL;
987 break;
988 case KSHU4:
989 ret = HQA_VCORE_NV_LP4_KSHU4_PL;
990 break;
991 case KSHU5:
992 ret = HQA_VCORE_NV_LP4_KSHU5_PL;
993 break;
994 case KSHU6:
995 ret = HQA_VCORE_NV_LP4_KSHU6_PL;
996 break;
997 };
998 #endif
999 }
1000
1001 return ret;
1002 }
1003
1004 #endif
1005
1006 #if (FOR_DV_SIMULATION_USED==0)
1007 #if !__ETT__
mt_set_emi(struct dramc_param * dparam)1008 void mt_set_emi(struct dramc_param *dparam)
1009 {
1010 int index;
1011 /*unsigned int SW_CTRL_VC, HW_CTRL_VC;*/
1012 EMI_SETTINGS *emi_set = &emi_settings[0];
1013
1014 int segment;
1015
1016 #ifdef VOLTAGE_SEL
1017 update_voltage_select_info();
1018 #endif
1019 #if ENABLE_PINMUX_FOR_RANK_SWAP
1020 EMI_rank_swap_handle();
1021 #endif
1022
1023 // set voltage and hw trapping before mdl
1024 setup_dramc_voltage_by_pmic();
1025
1026 if ((doe_get_config("dram_all_3094_0825")) || (doe_get_config("dram_all_3094_0725")))
1027 freq_table_are_all_3094();
1028 else if (doe_get_config("dram_all_1534_0725"))
1029 freq_table_are_all_1534();
1030 else if (doe_get_config("dram_opp0_3733_others_3094_0825"))
1031 freq_table_opp0_3733_others_3094();
1032 else if (doe_get_config("dram_opp0_3094_others_1534_0725"))
1033 freq_table_opp0_3094_others_1534();
1034 else if (doe_get_config("dram_opp0_2400_others_1534_0725"))
1035 freq_table_opp0_2400_others_1534();
1036
1037 #ifdef COMBO_MCP
1038
1039 index = mt_get_mdl_number();
1040 dramc_crit("[EMI] MDL number = %d\r\n", index);
1041 if (index < 0 || index >= num_of_emi_records)
1042 {
1043 die("[EMI] setting failed 0x%x\r\n", index);
1044 }
1045 else
1046 {
1047 emi_setting_index = index;
1048 emi_set = &emi_settings[emi_setting_index];
1049 }
1050 dramc_crit("[EMI] Get MDL freq = %d\r\n", emi_set->DRAMC_ACTIME_UNION[0]);
1051 #else
1052 dramc_crit("[EMI] ComboMCP not ready, using default setting\n");
1053 emi_setting_index = -1;
1054 emi_set = &default_emi_setting;
1055 #endif
1056 segment = (seclib_get_devinfo_with_index(7) & 0xFF);
1057 if ((segment == 0x80) || (segment == 0x01) || (segment == 0x40) || (segment == 0x02))
1058 {
1059 emi_set->DRAMC_ACTIME_UNION[0] = 3733;
1060 }
1061 #ifdef DDR_RESERVE_MODE
1062 if(g_ddr_reserve_enable==1 && g_ddr_reserve_success==0)
1063 Before_Init_DRAM_While_Reserve_Mode_fail(emi_set->type & 0xF);
1064 #endif
1065
1066 #if (CFG_DRAM_LOG_TO_STORAGE)
1067 log_start = 1;
1068 print("log_start=0x%x part_dram_data_addr_uart=0x%llx \n",log_start,part_dram_data_addr_uart);
1069 #endif
1070 #if defined(SLT)
1071 SLT_Init_DRAM((emi_set->type & 0xF), emi_set->dram_cbt_mode_extern, NULL, NORMAL_USED);
1072 #else
1073 Init_DRAM((emi_set->type & 0xF), emi_set->dram_cbt_mode_extern, NULL, NORMAL_USED);
1074 #endif
1075 switch_dramc_voltage_to_auto_mode();
1076 restore_vcore_setting();
1077
1078 #if (CFG_DRAM_LOG_TO_STORAGE)
1079 log_start = 0;
1080 print("log_start=0x%x part_dram_data_addr_uart=0x%llx \n",log_start,part_dram_data_addr_uart);
1081 #endif
1082 #if 0
1083 {
1084 DRAMC_CTX_T * p = psCurrDramCtx;
1085 DramcRegDump(p);
1086 }
1087 #endif
1088 }
1089 #endif
1090 #endif
1091
1092 #define DRAMC_ADDR_SHIFT_CHN(addr, channel) (addr + (channel * 0x10000))
1093
1094 #if (FOR_DV_SIMULATION_USED==0) // for DV sim build pass
doe_get_config(const char * feature)1095 int doe_get_config(const char* feature)
1096 {
1097 #if defined(ENABLE_DOE)
1098 char *doe_feature = dconfig_getenv(feature);
1099 int doe_result = atoi(doe_feature);
1100 dramc_crit("DOE force setting %s=%d\n", feature, doe_result);
1101 return doe_result;
1102 #else
1103 return 0;
1104 #endif
1105 }
1106 #endif
1107
1108 #if (CFG_DRAM_LOG_TO_STORAGE)
log_to_storage(const char c)1109 void log_to_storage(const char c)
1110 {
1111 int ret, clr_count;
1112 blkdev_t *bootdev = NULL;
1113 static u8 logen = 0;
1114
1115 bootdev = blkdev_get(CFG_BOOT_DEV);
1116
1117 if (log_start && (!logen)) {
1118 logen = 1;
1119 logcount = 0;
1120 part_dram_data_addr_uart = get_part_addr("boot_para") + 0x100000; // addr = 0x1f300000, the first 1MB for debug
1121 memset(&logbuf, 0, sizeof(logbuf));
1122 for (clr_count = 0; clr_count < 3072 ; clr_count++) //3M
1123 ret = blkdev_write(bootdev, (part_dram_data_addr_uart + (1024 * clr_count)), 1024, (u8*)&logbuf, storage_get_part_id(STORAGE_PHYS_PART_USER));
1124 }
1125
1126 if (log_start) {
1127 if (((((char) c >> 4) & 0x7) > 1) & ((((char) c >> 4) & 0x7) < 7))
1128 logbuf[logcount] = ((char) c & 0xF0) | (((char) c >> 2) & 0x03) | (((char) c << 2) & 0x0C);
1129 else
1130 logbuf[logcount] = (char) c;
1131 logcount = logcount + 1;
1132 //write to storage
1133 if (logcount==1024) {
1134 logcount = 0;
1135 ret = blkdev_write(bootdev, part_dram_data_addr_uart, 1024, (u8*)&logbuf, storage_get_part_id(STORAGE_PHYS_PART_USER));
1136 part_dram_data_addr_uart = part_dram_data_addr_uart + 1024;
1137 }
1138 }
1139 }
1140 #endif
1141 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
1142
1143 u32 g_dram_storage_api_err_code;
1144
1145 #if !__ETT__
read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle,SAVE_TIME_FOR_CALIBRATION_T * offLine_SaveData)1146 int read_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
1147 {
1148 struct sdram_params *params;
1149
1150 if (!dramc_params)
1151 return -1;
1152 params = &dramc_params->dramc_datas.freq_params[shuffle];
1153
1154 dramc_info("read calibration data from shuffle %d(For verify: WL B0:%u, B1: %u)\n",
1155 shuffle, params->wr_level[CHANNEL_A][RANK_0][0], params->wr_level[CHANNEL_B][RANK_0][0]);
1156 /* copy the data stored in storage to the data structure for calibration */
1157 memcpy(offLine_SaveData, params, sizeof(*offLine_SaveData));
1158
1159 return 0;
1160 }
1161
write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle,SAVE_TIME_FOR_CALIBRATION_T * offLine_SaveData)1162 int write_offline_dram_calibration_data(DRAM_DFS_SHUFFLE_TYPE_T shuffle, SAVE_TIME_FOR_CALIBRATION_T *offLine_SaveData)
1163 {
1164 return 0;
1165 }
1166
clean_dram_calibration_data(void)1167 int clean_dram_calibration_data(void)
1168 {
1169 return 0;
1170 }
1171 #endif
1172
1173 #endif
1174
1175
1176 #if __FLASH_TOOL_DA__
get_mr8_by_mrr(U8 channel,U8 rank)1177 unsigned int get_mr8_by_mrr(U8 channel, U8 rank)
1178 {
1179 DRAMC_CTX_T *p = psCurrDramCtx;
1180 unsigned int mr8_value;
1181
1182 p->channel = channel;
1183
1184 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), rank, SWCMD_CTRL0_MRRRK);
1185 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 8, SWCMD_CTRL0_MRSMA);
1186 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 1, SWCMD_EN_MRREN);
1187 while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRR_RESPONSE) ==0)
1188 mcDELAY_US(1);
1189 mr8_value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS), MRR_STATUS_MRR_REG);
1190 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_MRREN);
1191 vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), 0, SWCMD_CTRL0_MRRRK);
1192
1193 return (mr8_value & 0xff);
1194 }
1195 #endif
1196