1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 **************************************************************************/ 8 9 #ifndef _RADEON_VCN_ENC_H 10 #define _RADEON_VCN_ENC_H 11 12 #include "radeon_vcn.h" 13 #include "util/macros.h" 14 15 #include "ac_vcn_enc.h" 16 17 #define PIPE_ALIGN_IN_BLOCK_SIZE(value, alignment) DIV_ROUND_UP(value, alignment) 18 19 #define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value)) 20 #define RADEON_ENC_BEGIN(cmd) \ 21 { \ 22 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \ 23 RADEON_ENC_CS(cmd) 24 #define RADEON_ENC_READ(buf, domain, off) \ 25 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off)) 26 #define RADEON_ENC_WRITE(buf, domain, off) \ 27 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off)) 28 #define RADEON_ENC_READWRITE(buf, domain, off) \ 29 radeon_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off)) 30 #define RADEON_ENC_END() \ 31 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \ 32 enc->total_task_size += *begin; \ 33 } 34 #define RADEON_ENC_ADDR_SWAP() \ 35 do { \ 36 unsigned int *low = &enc->cs.current.buf[enc->cs.current.cdw - 2]; \ 37 unsigned int *high = &enc->cs.current.buf[enc->cs.current.cdw - 1]; \ 38 unsigned int temp = *low; \ 39 *low = *high; \ 40 *high = temp; \ 41 } while(0) 42 43 #define RADEON_ENC_DESTROY_VIDEO_BUFFER(buf) \ 44 do { \ 45 if (buf) { \ 46 si_vid_destroy_buffer(buf); \ 47 FREE(buf); \ 48 (buf) = NULL; \ 49 } \ 50 } while(0) 51 52 typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer_lean **handle, 53 struct radeon_surf **surface); 54 55 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context, 56 const struct pipe_video_codec *templat, 57 struct radeon_winsys *ws, 58 radeon_enc_get_buffer get_buffer); 59 60 struct radeon_enc_pic { 61 union { 62 enum pipe_h2645_enc_picture_type picture_type; 63 enum pipe_av1_enc_frame_type frame_type; 64 }; 65 66 union { 67 struct { 68 struct pipe_h264_enc_picture_desc *desc; 69 } h264; 70 struct { 71 struct pipe_h265_enc_picture_desc *desc; 72 } hevc; 73 }; 74 75 unsigned frame_num; 76 unsigned crop_left; 77 unsigned crop_right; 78 unsigned crop_top; 79 unsigned crop_bottom; 80 unsigned general_tier_flag; 81 unsigned general_profile_idc; 82 unsigned general_level_idc; 83 unsigned pic_width_in_luma_samples; 84 unsigned pic_height_in_luma_samples; 85 unsigned bit_depth_luma_minus8; 86 unsigned bit_depth_chroma_minus8; 87 unsigned nal_unit_type; 88 unsigned temporal_id; 89 unsigned num_temporal_layers; 90 unsigned temporal_layer_pattern_index; 91 rvcn_enc_quality_modes_t quality_modes; 92 93 bool not_referenced; 94 bool need_sequence_header; 95 bool use_rc_per_pic_ex; 96 bool av1_tile_splitting_legacy_flag; 97 98 struct { 99 struct { 100 struct { 101 uint32_t enable_tile_obu:1; 102 uint32_t enable_render_size:1; 103 uint32_t enable_error_resilient_mode:1; 104 uint32_t enable_order_hint:1; 105 uint32_t enable_color_description:1; 106 uint32_t timing_info_present:1; 107 uint32_t timing_info_equal_picture_interval:1; 108 uint32_t frame_id_numbers_present:1; 109 uint32_t force_integer_mv:1; 110 uint32_t disable_screen_content_tools:1; 111 uint32_t is_obu_frame:1; 112 uint32_t stream_obu_frame:1; /* all frames have the same number of tiles */ 113 uint32_t need_av1_seq:1; 114 uint32_t av1_mark_long_term_reference:1; 115 }; 116 uint32_t render_width; 117 uint32_t render_height; 118 uint32_t frame_to_show_map_index; 119 enum pipe_av1_enc_frame_type last_frame_type; 120 uint32_t display_frame_id; 121 uint32_t frame_id; 122 uint32_t temporal_seq_num; 123 uint32_t order_hint; 124 uint32_t order_hint_bits; 125 uint32_t refresh_frame_flags; 126 uint32_t reference_delta_frame_id; 127 uint32_t reference_frame_index; 128 uint32_t reference_order_hint[RENCDOE_AV1_NUM_REF_FRAMES]; 129 uint32_t *copy_start; 130 }; 131 rvcn_enc_av1_spec_misc_t av1_spec_misc; 132 rvcn_enc_av1_cdf_default_table_t av1_cdf_default_table; 133 rvcn_enc_av1_timing_info_t av1_timing_info; 134 rvcn_enc_av1_color_description_t av1_color_description; 135 uint32_t count_last_layer; 136 rvcn_enc_av1_ref_frame_t frames[RENCDOE_AV1_NUM_REF_FRAMES]; 137 rvcn_enc_av1_recon_slot_t recon_slots[RENCDOE_AV1_NUM_REF_FRAMES + 1]; 138 uint8_t av1_ref_frame_idx[RENCDOE_AV1_REFS_PER_FRAME]; 139 void *av1_ref_list[RENCDOE_AV1_NUM_REF_FRAMES]; 140 void *av1_recon_frame; 141 uint32_t av1_ref_frame_ctrl_l0; 142 uint32_t av1_ref_frame_ctrl_l1; 143 uint32_t av1_ltr_seq; 144 }; 145 146 rvcn_enc_session_info_t session_info; 147 rvcn_enc_task_info_t task_info; 148 rvcn_enc_session_init_t session_init; 149 rvcn_enc_layer_control_t layer_ctrl; 150 rvcn_enc_layer_select_t layer_sel; 151 rvcn_enc_h264_slice_control_t slice_ctrl; 152 rvcn_enc_hevc_slice_control_t hevc_slice_ctrl; 153 rvcn_enc_h264_spec_misc_t spec_misc; 154 rvcn_enc_hevc_spec_misc_t hevc_spec_misc; 155 rvcn_enc_rate_ctl_session_init_t rc_session_init; 156 rvcn_enc_rate_ctl_layer_init_t rc_layer_init[RENCODE_MAX_NUM_TEMPORAL_LAYERS]; 157 rvcn_enc_h264_encode_params_t h264_enc_params; 158 rvcn_enc_h264_deblocking_filter_t h264_deblock; 159 rvcn_enc_hevc_deblocking_filter_t hevc_deblock; 160 rvcn_enc_hevc_encode_params_t hevc_enc_params; 161 rvcn_enc_av1_encode_params_t av1_enc_params; 162 rvcn_enc_av1_tile_config_t av1_tile_config; 163 rvcn_enc_rate_ctl_per_picture_t rc_per_pic; 164 rvcn_enc_quality_params_t quality_params; 165 rvcn_enc_encode_context_buffer_t ctx_buf; 166 rvcn_enc_video_bitstream_buffer_t bit_buf; 167 rvcn_enc_feedback_buffer_t fb_buf; 168 rvcn_enc_intra_refresh_t intra_refresh; 169 rvcn_enc_encode_params_t enc_params; 170 rvcn_enc_stats_t enc_statistics; 171 rvcn_enc_input_format_t enc_input_format; 172 rvcn_enc_output_format_t enc_output_format; 173 rvcn_enc_qp_map_t enc_qp_map; 174 rvcn_enc_metadata_buffer_t metadata; 175 rvcn_enc_latency_t enc_latency; 176 rvcn_enc_seidata_t enc_sei; 177 }; 178 179 struct radeon_encoder { 180 struct pipe_video_codec base; 181 182 void (*begin)(struct radeon_encoder *enc); 183 void (*before_encode)(struct radeon_encoder *enc); 184 void (*encode)(struct radeon_encoder *enc); 185 void (*destroy)(struct radeon_encoder *enc); 186 void (*session_info)(struct radeon_encoder *enc); 187 void (*task_info)(struct radeon_encoder *enc, bool need_feedback); 188 void (*session_init)(struct radeon_encoder *enc); 189 void (*layer_control)(struct radeon_encoder *enc); 190 void (*layer_select)(struct radeon_encoder *enc); 191 void (*slice_control)(struct radeon_encoder *enc); 192 void (*spec_misc)(struct radeon_encoder *enc); 193 void (*rc_session_init)(struct radeon_encoder *enc); 194 void (*rc_layer_init)(struct radeon_encoder *enc); 195 void (*deblocking_filter)(struct radeon_encoder *enc); 196 void (*quality_params)(struct radeon_encoder *enc); 197 void (*slice_header)(struct radeon_encoder *enc); 198 void (*ctx)(struct radeon_encoder *enc); 199 void (*bitstream)(struct radeon_encoder *enc); 200 void (*feedback)(struct radeon_encoder *enc); 201 void (*intra_refresh)(struct radeon_encoder *enc); 202 void (*rc_per_pic)(struct radeon_encoder *enc); 203 void (*encode_params)(struct radeon_encoder *enc); 204 void (*encode_params_codec_spec)(struct radeon_encoder *enc); 205 void (*qp_map)(struct radeon_encoder *enc); 206 void (*op_init)(struct radeon_encoder *enc); 207 void (*op_close)(struct radeon_encoder *enc); 208 void (*op_enc)(struct radeon_encoder *enc); 209 void (*op_init_rc)(struct radeon_encoder *enc); 210 void (*op_init_rc_vbv)(struct radeon_encoder *enc); 211 void (*op_preset)(struct radeon_encoder *enc); 212 void (*encode_headers)(struct radeon_encoder *enc); 213 void (*input_format)(struct radeon_encoder *enc); 214 void (*output_format)(struct radeon_encoder *enc); 215 void (*encode_statistics)(struct radeon_encoder *enc); 216 void (*obu_instructions)(struct radeon_encoder *enc); 217 void (*cdf_default_table)(struct radeon_encoder *enc); 218 void (*ctx_override)(struct radeon_encoder *enc); 219 void (*metadata)(struct radeon_encoder *enc); 220 void (*tile_config)(struct radeon_encoder *enc); 221 void (*encode_latency)(struct radeon_encoder *enc); 222 /* mq is used for preversing multiple queue ibs */ 223 void (*mq_begin)(struct radeon_encoder *enc); 224 void (*mq_encode)(struct radeon_encoder *enc); 225 void (*mq_destroy)(struct radeon_encoder *enc); 226 227 unsigned stream_handle; 228 229 struct pipe_screen *screen; 230 struct radeon_winsys *ws; 231 struct radeon_cmdbuf cs; 232 233 radeon_enc_get_buffer get_buffer; 234 235 struct pb_buffer_lean *handle; 236 struct radeon_surf *luma; 237 struct radeon_surf *chroma; 238 239 struct pb_buffer_lean *bs_handle; 240 unsigned bs_size; 241 unsigned bs_offset; 242 243 struct rvid_buffer *si; 244 struct rvid_buffer *fb; 245 struct rvid_buffer *dpb; 246 struct rvid_buffer *cdf; 247 struct rvid_buffer *roi; 248 struct rvid_buffer *meta; 249 struct radeon_enc_pic enc_pic; 250 struct pb_buffer_lean *stats; 251 rvcn_enc_cmd_t cmd; 252 253 unsigned alignment; 254 unsigned shifter; 255 unsigned bits_in_shifter; 256 unsigned num_zeros; 257 unsigned byte_index; 258 unsigned bits_output; 259 unsigned bits_size; 260 uint8_t *bits_buf; 261 uint32_t bits_buf_pos; 262 uint32_t total_task_size; 263 uint32_t *p_task_size; 264 struct rvcn_sq_var sq; 265 266 bool emulation_prevention; 267 bool need_feedback; 268 bool need_rate_control; 269 bool need_rc_per_pic; 270 unsigned dpb_size; 271 unsigned dpb_slots; 272 unsigned roi_size; 273 unsigned metadata_size; 274 275 struct pipe_context *ectx; 276 }; 277 278 struct rvcn_enc_output_unit_segment { 279 bool is_slice; 280 unsigned size; 281 unsigned offset; 282 }; 283 284 struct rvcn_enc_feedback_data { 285 unsigned num_segments; 286 struct rvcn_enc_output_unit_segment segments[]; 287 }; 288 289 /* structure for determining av1 tile division scheme. 290 * In one direction, it is trying to split width/height into two parts, 291 * main and border, each of which has a length (number of sbs), 292 * Therefore, it has two possible tile sizes, even with multiple 293 * tiles, and in non-uniformed case, it is trying to make tile sizes 294 * as similar as possible. 295 */ 296 297 struct tile_1d_layout { 298 bool uniform_tile_flag; 299 uint32_t nb_main_sb; /* if non-uniform, it means the first part */ 300 uint32_t nb_border_sb; /* if non-uniform, it means the second part */ 301 uint32_t nb_main_tile; 302 uint32_t nb_border_tile; 303 }; 304 305 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer_lean *buf, 306 unsigned usage, enum radeon_bo_domain domain, signed offset); 307 308 void radeon_enc_dummy(struct radeon_encoder *enc); 309 310 void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set); 311 312 void radeon_enc_set_output_buffer(struct radeon_encoder *enc, uint8_t *buffer); 313 314 void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte); 315 316 void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte); 317 318 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value, 319 unsigned int num_bits); 320 321 void radeon_enc_reset(struct radeon_encoder *enc); 322 323 void radeon_enc_byte_align(struct radeon_encoder *enc); 324 325 void radeon_enc_flush_headers(struct radeon_encoder *enc); 326 327 void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value); 328 329 void radeon_enc_code_se(struct radeon_encoder *enc, int value); 330 331 void radeon_enc_code_uvlc(struct radeon_encoder *enc, unsigned int value); 332 333 void radeon_enc_code_leb128(unsigned char *buf, unsigned int value, 334 unsigned int num_bytes); 335 336 void radeon_enc_code_ns(struct radeon_encoder *enc, unsigned int value, 337 unsigned int max); 338 339 void radeon_enc_1_2_init(struct radeon_encoder *enc); 340 341 void radeon_enc_2_0_init(struct radeon_encoder *enc); 342 343 void radeon_enc_3_0_init(struct radeon_encoder *enc); 344 345 void radeon_enc_4_0_init(struct radeon_encoder *enc); 346 347 void radeon_enc_5_0_init(struct radeon_encoder *enc); 348 349 unsigned int radeon_enc_write_sps(struct radeon_encoder *enc, uint8_t *out); 350 351 unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t *out); 352 353 unsigned int radeon_enc_write_vps(struct radeon_encoder *enc, uint8_t *out); 354 355 unsigned int radeon_enc_write_sps_hevc(struct radeon_encoder *enc, uint8_t *out); 356 357 unsigned int radeon_enc_write_pps_hevc(struct radeon_encoder *enc, uint8_t *out); 358 359 void radeon_enc_hrd_parameters(struct radeon_encoder *enc, 360 struct pipe_h264_enc_hrd_params *hrd); 361 362 void radeon_enc_hevc_profile_tier_level(struct radeon_encoder *enc, 363 unsigned int max_num_sub_layers_minus1, 364 struct pipe_h265_profile_tier_level *ptl); 365 366 void radeon_enc_hevc_hrd_parameters(struct radeon_encoder *enc, 367 unsigned int common_inf_present_flag, 368 unsigned int max_sub_layers_minus1, 369 struct pipe_h265_enc_hrd_params *hrd); 370 371 unsigned int radeon_enc_hevc_st_ref_pic_set(struct radeon_encoder *enc, 372 unsigned int index, 373 unsigned int num_short_term_ref_pic_sets, 374 struct pipe_h265_st_ref_pic_set *st_rps); 375 376 void radeon_enc_av1_bs_instruction_type(struct radeon_encoder *enc, 377 unsigned int inst, unsigned int obu_type); 378 379 void radeon_enc_av1_obu_header(struct radeon_encoder *enc, uint32_t obu_type); 380 381 void radeon_enc_av1_temporal_delimiter(struct radeon_encoder *enc); 382 383 void radeon_enc_av1_sequence_header(struct radeon_encoder *enc, bool separate_delta_q); 384 385 void radeon_enc_av1_tile_group(struct radeon_encoder *enc); 386 387 void radeon_enc_av1_metadata_obu(struct radeon_encoder *enc); 388 389 unsigned char *radeon_enc_av1_header_size_offset(struct radeon_encoder *enc); 390 391 unsigned int radeon_enc_value_bits(unsigned int value); 392 393 unsigned int radeon_enc_av1_tile_log2(unsigned int blk_size, unsigned int max); 394 395 bool radeon_enc_is_av1_uniform_tile (uint32_t nb_sb, uint32_t nb_tiles, 396 uint32_t min_nb_sb, struct tile_1d_layout *p); 397 398 void radeon_enc_av1_tile_layout (uint32_t nb_sb, uint32_t nb_tiles, uint32_t min_nb_sb, 399 struct tile_1d_layout *p); 400 #endif // _RADEON_VCN_ENC_H 401