xref: /aosp_15_r20/external/coreboot/src/soc/qualcomm/sc7280/include/soc/cpucp.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _SOC_QUALCOMM_SC7280_CPUCP_H__
4 #define _SOC_QUALCOMM_SC7280_CPUCP_H__
5 
6 #include <soc/addressmap.h>
7 
8 struct epsstop_epss_top {
9 	uint32_t access_override;
10 	uint32_t global_enable;
11 	uint32_t trace_bus_ctrl;
12 	uint32_t debug_bus_ctrl;
13 	uint32_t muc_hang_det_ctrl;
14 	uint32_t muc_hang_irq_sts;
15 	uint32_t muc_hang_count_threshold;
16 	uint32_t muc_hang_count_sts;
17 	uint32_t muc_hang_det_sts;
18 	uint32_t l3_voting_en;
19 };
20 
21 struct epssfast_epss_fast {
22 	uint32_t epss_muc_clk_ctrl;
23 	uint32_t muc_rvbar;
24 	uint32_t muc_rvbar_ctrl;
25 	uint32_t muc_non_secure_dmem_start_addr;
26 	uint32_t muc_non_secure_dmem_end_addr;
27 	uint32_t reserved_1[2];
28 	uint32_t cpr_data_fifo[4];
29 	uint32_t reserved_2[4];
30 	uint32_t pll_data_fifo[4];
31 	uint32_t reserved_3[4];
32 	uint32_t gfmux_data_fifo_1[4];
33 	uint32_t cpu_pcu_spare_irq_status;
34 	uint32_t cpu_pcu_spare_irq_clr;
35 	uint32_t cpu_pcu_spare_wait_event;
36 	uint32_t seq_mem[256];
37 };
38 
39 static struct epsstop_epss_top *const epss_top = (void *)EPSSTOP_EPSS_TOP;
40 static struct epssfast_epss_fast *const epss_fast = (void *)EPSSFAST_BASE_ADDR;
41 
42 void cpucp_fw_load_reset(void);
43 void cpucp_prepare(void);
44 
45 #endif  // _SOC_QUALCOMM_SC7280_CPUCP_H__
46