1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <[email protected]>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
8 #define __ARM64_KVM_HYP_SWITCH_H__
9
10 #include <hyp/adjust_pc.h>
11 #include <hyp/fault.h>
12
13 #include <linux/arm-smccc.h>
14 #include <linux/kvm_host.h>
15 #include <linux/types.h>
16 #include <linux/jump_label.h>
17 #include <uapi/linux/psci.h>
18
19 #include <kvm/arm_psci.h>
20
21 #include <asm/barrier.h>
22 #include <asm/cpufeature.h>
23 #include <asm/extable.h>
24 #include <asm/kprobes.h>
25 #include <asm/kvm_asm.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_hyp.h>
28 #include <asm/kvm_mmu.h>
29 #include <asm/kvm_nested.h>
30 #include <asm/fpsimd.h>
31 #include <asm/debug-monitors.h>
32 #include <asm/processor.h>
33 #include <asm/traps.h>
34
35 struct kvm_exception_table_entry {
36 int insn, fixup;
37 };
38
39 extern struct kvm_exception_table_entry __start___kvm_ex_table;
40 extern struct kvm_exception_table_entry __stop___kvm_ex_table;
41
42 /* Save the 32-bit only FPSIMD system register state */
__fpsimd_save_fpexc32(struct kvm_vcpu * vcpu)43 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
44 {
45 if (!vcpu_el1_is_32bit(vcpu))
46 return;
47
48 __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2);
49 }
50
__activate_traps_fpsimd32(struct kvm_vcpu * vcpu)51 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
52 {
53 /*
54 * We are about to set CPTR_EL2.TFP to trap all floating point
55 * register accesses to EL2, however, the ARM ARM clearly states that
56 * traps are only taken to EL2 if the operation would not otherwise
57 * trap to EL1. Therefore, always make sure that for 32-bit guests,
58 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
59 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
60 * it will cause an exception.
61 */
62 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
63 write_sysreg(1 << 30, fpexc32_el2);
64 isb();
65 }
66 }
67
68 #define compute_clr_set(vcpu, reg, clr, set) \
69 do { \
70 u64 hfg; \
71 hfg = __vcpu_sys_reg(vcpu, reg) & ~__ ## reg ## _RES0; \
72 set |= hfg & __ ## reg ## _MASK; \
73 clr |= ~hfg & __ ## reg ## _nMASK; \
74 } while(0)
75
76 #define reg_to_fgt_group_id(reg) \
77 ({ \
78 enum fgt_group_id id; \
79 switch(reg) { \
80 case HFGRTR_EL2: \
81 case HFGWTR_EL2: \
82 id = HFGxTR_GROUP; \
83 break; \
84 case HFGITR_EL2: \
85 id = HFGITR_GROUP; \
86 break; \
87 case HDFGRTR_EL2: \
88 case HDFGWTR_EL2: \
89 id = HDFGRTR_GROUP; \
90 break; \
91 case HAFGRTR_EL2: \
92 id = HAFGRTR_GROUP; \
93 break; \
94 default: \
95 BUILD_BUG_ON(1); \
96 } \
97 \
98 id; \
99 })
100
101 #define compute_undef_clr_set(vcpu, kvm, reg, clr, set) \
102 do { \
103 u64 hfg = kvm->arch.fgu[reg_to_fgt_group_id(reg)]; \
104 set |= hfg & __ ## reg ## _MASK; \
105 clr |= hfg & __ ## reg ## _nMASK; \
106 } while(0)
107
108 #define update_fgt_traps_cs(hctxt, vcpu, kvm, reg, clr, set) \
109 do { \
110 u64 c = 0, s = 0; \
111 \
112 ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg); \
113 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) \
114 compute_clr_set(vcpu, reg, c, s); \
115 \
116 compute_undef_clr_set(vcpu, kvm, reg, c, s); \
117 \
118 s |= set; \
119 c |= clr; \
120 if (c || s) { \
121 u64 val = __ ## reg ## _nMASK; \
122 val |= s; \
123 val &= ~c; \
124 write_sysreg_s(val, SYS_ ## reg); \
125 } \
126 } while(0)
127
128 #define update_fgt_traps(hctxt, vcpu, kvm, reg) \
129 update_fgt_traps_cs(hctxt, vcpu, kvm, reg, 0, 0)
130
131 /*
132 * Validate the fine grain trap masks.
133 * Check that the masks do not overlap and that all bits are accounted for.
134 */
135 #define CHECK_FGT_MASKS(reg) \
136 do { \
137 BUILD_BUG_ON((__ ## reg ## _MASK) & (__ ## reg ## _nMASK)); \
138 BUILD_BUG_ON(~((__ ## reg ## _RES0) ^ (__ ## reg ## _MASK) ^ \
139 (__ ## reg ## _nMASK))); \
140 } while(0)
141
cpu_has_amu(void)142 static inline bool cpu_has_amu(void)
143 {
144 u64 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
145
146 return cpuid_feature_extract_unsigned_field(pfr0,
147 ID_AA64PFR0_EL1_AMU_SHIFT);
148 }
149
__activate_traps_hfgxtr(struct kvm_vcpu * vcpu)150 static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
151 {
152 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
153 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
154
155 CHECK_FGT_MASKS(HFGRTR_EL2);
156 CHECK_FGT_MASKS(HFGWTR_EL2);
157 CHECK_FGT_MASKS(HFGITR_EL2);
158 CHECK_FGT_MASKS(HDFGRTR_EL2);
159 CHECK_FGT_MASKS(HDFGWTR_EL2);
160 CHECK_FGT_MASKS(HAFGRTR_EL2);
161 CHECK_FGT_MASKS(HCRX_EL2);
162
163 if (!cpus_have_final_cap(ARM64_HAS_FGT))
164 return;
165
166 update_fgt_traps(hctxt, vcpu, kvm, HFGRTR_EL2);
167 update_fgt_traps_cs(hctxt, vcpu, kvm, HFGWTR_EL2, 0,
168 cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) ?
169 HFGxTR_EL2_TCR_EL1_MASK : 0);
170 update_fgt_traps(hctxt, vcpu, kvm, HFGITR_EL2);
171 update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR_EL2);
172 update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR_EL2);
173
174 if (cpu_has_amu())
175 update_fgt_traps(hctxt, vcpu, kvm, HAFGRTR_EL2);
176 }
177
178 #define __deactivate_fgt(htcxt, vcpu, kvm, reg) \
179 do { \
180 if ((vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) || \
181 kvm->arch.fgu[reg_to_fgt_group_id(reg)]) \
182 write_sysreg_s(ctxt_sys_reg(hctxt, reg), \
183 SYS_ ## reg); \
184 } while(0)
185
__deactivate_traps_hfgxtr(struct kvm_vcpu * vcpu)186 static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
187 {
188 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
189 struct kvm *kvm = kern_hyp_va(vcpu->kvm);
190
191 if (!cpus_have_final_cap(ARM64_HAS_FGT))
192 return;
193
194 __deactivate_fgt(hctxt, vcpu, kvm, HFGRTR_EL2);
195 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
196 write_sysreg_s(ctxt_sys_reg(hctxt, HFGWTR_EL2), SYS_HFGWTR_EL2);
197 else
198 __deactivate_fgt(hctxt, vcpu, kvm, HFGWTR_EL2);
199 __deactivate_fgt(hctxt, vcpu, kvm, HFGITR_EL2);
200 __deactivate_fgt(hctxt, vcpu, kvm, HDFGRTR_EL2);
201 __deactivate_fgt(hctxt, vcpu, kvm, HDFGWTR_EL2);
202
203 if (cpu_has_amu())
204 __deactivate_fgt(hctxt, vcpu, kvm, HAFGRTR_EL2);
205 }
206
__activate_traps_mpam(struct kvm_vcpu * vcpu)207 static inline void __activate_traps_mpam(struct kvm_vcpu *vcpu)
208 {
209 u64 r = MPAM2_EL2_TRAPMPAM0EL1 | MPAM2_EL2_TRAPMPAM1EL1;
210
211 if (!system_supports_mpam())
212 return;
213
214 /* trap guest access to MPAMIDR_EL1 */
215 if (system_supports_mpam_hcr()) {
216 write_sysreg_s(MPAMHCR_EL2_TRAP_MPAMIDR_EL1, SYS_MPAMHCR_EL2);
217 } else {
218 /* From v1.1 TIDR can trap MPAMIDR, set it unconditionally */
219 r |= MPAM2_EL2_TIDR;
220 }
221
222 write_sysreg_s(r, SYS_MPAM2_EL2);
223 }
224
__deactivate_traps_mpam(void)225 static inline void __deactivate_traps_mpam(void)
226 {
227 if (!system_supports_mpam())
228 return;
229
230 write_sysreg_s(0, SYS_MPAM2_EL2);
231
232 if (system_supports_mpam_hcr())
233 write_sysreg_s(MPAMHCR_HOST_FLAGS, SYS_MPAMHCR_EL2);
234 }
235
__activate_traps_common(struct kvm_vcpu * vcpu)236 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
237 {
238 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
239 write_sysreg(1 << 15, hstr_el2);
240
241 /*
242 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
243 * PMSELR_EL0 to make sure it never contains the cycle
244 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
245 * EL1 instead of being trapped to EL2.
246 */
247 if (kvm_arm_support_pmu_v3()) {
248 struct kvm_cpu_context *hctxt;
249
250 write_sysreg(0, pmselr_el0);
251
252 hctxt = host_data_ptr(host_ctxt);
253 ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0);
254 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
255 vcpu_set_flag(vcpu, PMUSERENR_ON_CPU);
256 }
257
258 *host_data_ptr(host_debug_state.mdcr_el2) = read_sysreg(mdcr_el2);
259 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
260
261 if (cpus_have_final_cap(ARM64_HAS_HCX)) {
262 u64 hcrx = vcpu->arch.hcrx_el2;
263 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) {
264 u64 clr = 0, set = 0;
265
266 compute_clr_set(vcpu, HCRX_EL2, clr, set);
267
268 hcrx |= set;
269 hcrx &= ~clr;
270 }
271
272 write_sysreg_s(hcrx, SYS_HCRX_EL2);
273 }
274
275 __activate_traps_hfgxtr(vcpu);
276 __activate_traps_mpam(vcpu);
277 }
278
__deactivate_traps_common(struct kvm_vcpu * vcpu)279 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
280 {
281 write_sysreg(*host_data_ptr(host_debug_state.mdcr_el2), mdcr_el2);
282
283 write_sysreg(0, hstr_el2);
284 if (kvm_arm_support_pmu_v3()) {
285 struct kvm_cpu_context *hctxt;
286
287 hctxt = host_data_ptr(host_ctxt);
288 write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0);
289 vcpu_clear_flag(vcpu, PMUSERENR_ON_CPU);
290 }
291
292 if (cpus_have_final_cap(ARM64_HAS_HCX))
293 write_sysreg_s(HCRX_HOST_FLAGS, SYS_HCRX_EL2);
294
295 __deactivate_traps_hfgxtr(vcpu);
296 __deactivate_traps_mpam();
297 }
298
___activate_traps(struct kvm_vcpu * vcpu,u64 hcr)299 static inline void ___activate_traps(struct kvm_vcpu *vcpu, u64 hcr)
300 {
301 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
302 hcr |= HCR_TVM;
303
304 write_sysreg(hcr, hcr_el2);
305
306 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
307 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
308 }
309
___deactivate_traps(struct kvm_vcpu * vcpu)310 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
311 {
312 /*
313 * If we pended a virtual abort, preserve it until it gets
314 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
315 * the crucial bit is "On taking a vSError interrupt,
316 * HCR_EL2.VSE is cleared to 0."
317 */
318 if (vcpu->arch.hcr_el2 & HCR_VSE) {
319 vcpu->arch.hcr_el2 &= ~HCR_VSE;
320 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
321 }
322 }
323
__populate_fault_info(struct kvm_vcpu * vcpu)324 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
325 {
326 return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
327 }
328
kvm_hyp_handle_mops(struct kvm_vcpu * vcpu,u64 * exit_code)329 static inline bool kvm_hyp_handle_mops(struct kvm_vcpu *vcpu, u64 *exit_code)
330 {
331 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
332 arm64_mops_reset_regs(vcpu_gp_regs(vcpu), vcpu->arch.fault.esr_el2);
333 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
334
335 /*
336 * Finish potential single step before executing the prologue
337 * instruction.
338 */
339 *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
340 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
341
342 return true;
343 }
344
__hyp_sve_restore_guest(struct kvm_vcpu * vcpu)345 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
346 {
347 /*
348 * The vCPU's saved SVE state layout always matches the max VL of the
349 * vCPU. Start off with the max VL so we can load the SVE state.
350 */
351 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
352 __sve_restore_state(vcpu_sve_pffr(vcpu),
353 &vcpu->arch.ctxt.fp_regs.fpsr,
354 true);
355
356 /*
357 * The effective VL for a VM could differ from the max VL when running a
358 * nested guest, as the guest hypervisor could select a smaller VL. Slap
359 * that into hardware before wrapping up.
360 */
361 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu))
362 sve_cond_update_zcr_vq(__vcpu_sys_reg(vcpu, ZCR_EL2), SYS_ZCR_EL2);
363
364 write_sysreg_el1(__vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)), SYS_ZCR);
365 }
366
__hyp_sve_save_host(void)367 static inline void __hyp_sve_save_host(void)
368 {
369 struct cpu_sve_state *sve_state = *host_data_ptr(sve_state);
370
371 sve_state->zcr_el1 = read_sysreg_el1(SYS_ZCR);
372 write_sysreg_s(sve_vq_from_vl(kvm_host_sve_max_vl) - 1, SYS_ZCR_EL2);
373 __sve_save_state(sve_state->sve_regs + sve_ffr_offset(kvm_host_sve_max_vl),
374 &sve_state->fpsr,
375 true);
376 }
377
fpsimd_lazy_switch_to_guest(struct kvm_vcpu * vcpu)378 static inline void fpsimd_lazy_switch_to_guest(struct kvm_vcpu *vcpu)
379 {
380 u64 zcr_el1, zcr_el2;
381
382 if (!guest_owns_fp_regs())
383 return;
384
385 if (vcpu_has_sve(vcpu)) {
386 /* A guest hypervisor may restrict the effective max VL. */
387 if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu))
388 zcr_el2 = __vcpu_sys_reg(vcpu, ZCR_EL2);
389 else
390 zcr_el2 = vcpu_sve_max_vq(vcpu) - 1;
391
392 write_sysreg_el2(zcr_el2, SYS_ZCR);
393
394 zcr_el1 = __vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu));
395 write_sysreg_el1(zcr_el1, SYS_ZCR);
396 }
397 }
398
fpsimd_lazy_switch_to_host(struct kvm_vcpu * vcpu)399 static inline void fpsimd_lazy_switch_to_host(struct kvm_vcpu *vcpu)
400 {
401 u64 zcr_el1, zcr_el2;
402
403 if (!guest_owns_fp_regs())
404 return;
405
406 /*
407 * When the guest owns the FP regs, we know that guest+hyp traps for
408 * any FPSIMD/SVE/SME features exposed to the guest have been disabled
409 * by either fpsimd_lazy_switch_to_guest() or kvm_hyp_handle_fpsimd()
410 * prior to __guest_entry(). As __guest_entry() guarantees a context
411 * synchronization event, we don't need an ISB here to avoid taking
412 * traps for anything that was exposed to the guest.
413 */
414 if (vcpu_has_sve(vcpu)) {
415 zcr_el1 = read_sysreg_el1(SYS_ZCR);
416 __vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)) = zcr_el1;
417
418 /*
419 * The guest's state is always saved using the guest's max VL.
420 * Ensure that the host has the guest's max VL active such that
421 * the host can save the guest's state lazily, but don't
422 * artificially restrict the host to the guest's max VL.
423 */
424 if (has_vhe()) {
425 zcr_el2 = vcpu_sve_max_vq(vcpu) - 1;
426 write_sysreg_el2(zcr_el2, SYS_ZCR);
427 } else {
428 zcr_el2 = sve_vq_from_vl(kvm_host_sve_max_vl) - 1;
429 write_sysreg_el2(zcr_el2, SYS_ZCR);
430
431 zcr_el1 = vcpu_sve_max_vq(vcpu) - 1;
432 write_sysreg_el1(zcr_el1, SYS_ZCR);
433 }
434 }
435 }
436
kvm_hyp_save_fpsimd_host(struct kvm_vcpu * vcpu)437 static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu)
438 {
439 /*
440 * Non-protected kvm relies on the host restoring its sve state.
441 * Protected kvm restores the host's sve state as not to reveal that
442 * fpsimd was used by a guest nor leak upper sve bits.
443 */
444 if (system_supports_sve()) {
445 __hyp_sve_save_host();
446
447 /* Re-enable SVE traps if not supported for the guest vcpu. */
448 if (!vcpu_has_sve(vcpu))
449 cpacr_clear_set(CPACR_EL1_ZEN, 0);
450
451 } else {
452 __fpsimd_save_state(host_data_ptr(host_ctxt.fp_regs));
453 }
454
455 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
456 *host_data_ptr(fpmr) = read_sysreg_s(SYS_FPMR);
457 }
458
459
460 /*
461 * We trap the first access to the FP/SIMD to save the host context and
462 * restore the guest context lazily.
463 * If FP/SIMD is not implemented, handle the trap and inject an undefined
464 * instruction exception to the guest. Similarly for trapped SVE accesses.
465 */
kvm_hyp_handle_fpsimd(struct kvm_vcpu * vcpu,u64 * exit_code)466 static inline bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
467 {
468 bool sve_guest;
469 u8 esr_ec;
470
471 if (!system_supports_fpsimd())
472 return false;
473
474 sve_guest = vcpu_has_sve(vcpu);
475 esr_ec = kvm_vcpu_trap_get_class(vcpu);
476
477 /* Only handle traps the vCPU can support here: */
478 switch (esr_ec) {
479 case ESR_ELx_EC_FP_ASIMD:
480 /* Forward traps to the guest hypervisor as required */
481 if (guest_hyp_fpsimd_traps_enabled(vcpu))
482 return false;
483 break;
484 case ESR_ELx_EC_SYS64:
485 if (WARN_ON_ONCE(!is_hyp_ctxt(vcpu)))
486 return false;
487 fallthrough;
488 case ESR_ELx_EC_SVE:
489 if (!sve_guest)
490 return false;
491 if (guest_hyp_sve_traps_enabled(vcpu))
492 return false;
493 break;
494 default:
495 return false;
496 }
497
498 /* Valid trap. Switch the context: */
499
500 /* First disable enough traps to allow us to update the registers */
501 if (sve_guest || (is_protected_kvm_enabled() && system_supports_sve()))
502 cpacr_clear_set(0, CPACR_EL1_FPEN | CPACR_EL1_ZEN);
503 else
504 cpacr_clear_set(0, CPACR_EL1_FPEN);
505 isb();
506
507 /* Write out the host state if it's in the registers */
508 if (is_protected_kvm_enabled() && host_owns_fp_regs())
509 kvm_hyp_save_fpsimd_host(vcpu);
510
511 /* Restore the guest state */
512 if (sve_guest)
513 __hyp_sve_restore_guest(vcpu);
514 else
515 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
516
517 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
518 write_sysreg_s(__vcpu_sys_reg(vcpu, FPMR), SYS_FPMR);
519
520 /* Skip restoring fpexc32 for AArch64 guests */
521 if (!(read_sysreg(hcr_el2) & HCR_RW))
522 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
523
524 *host_data_ptr(fp_owner) = FP_STATE_GUEST_OWNED;
525
526 return true;
527 }
528
handle_tx2_tvm(struct kvm_vcpu * vcpu)529 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
530 {
531 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
532 int rt = kvm_vcpu_sys_get_rt(vcpu);
533 u64 val = vcpu_get_reg(vcpu, rt);
534
535 /*
536 * The normal sysreg handling code expects to see the traps,
537 * let's not do anything here.
538 */
539 if (vcpu->arch.hcr_el2 & HCR_TVM)
540 return false;
541
542 switch (sysreg) {
543 case SYS_SCTLR_EL1:
544 write_sysreg_el1(val, SYS_SCTLR);
545 break;
546 case SYS_TTBR0_EL1:
547 write_sysreg_el1(val, SYS_TTBR0);
548 break;
549 case SYS_TTBR1_EL1:
550 write_sysreg_el1(val, SYS_TTBR1);
551 break;
552 case SYS_TCR_EL1:
553 write_sysreg_el1(val, SYS_TCR);
554 break;
555 case SYS_ESR_EL1:
556 write_sysreg_el1(val, SYS_ESR);
557 break;
558 case SYS_FAR_EL1:
559 write_sysreg_el1(val, SYS_FAR);
560 break;
561 case SYS_AFSR0_EL1:
562 write_sysreg_el1(val, SYS_AFSR0);
563 break;
564 case SYS_AFSR1_EL1:
565 write_sysreg_el1(val, SYS_AFSR1);
566 break;
567 case SYS_MAIR_EL1:
568 write_sysreg_el1(val, SYS_MAIR);
569 break;
570 case SYS_AMAIR_EL1:
571 write_sysreg_el1(val, SYS_AMAIR);
572 break;
573 case SYS_CONTEXTIDR_EL1:
574 write_sysreg_el1(val, SYS_CONTEXTIDR);
575 break;
576 default:
577 return false;
578 }
579
580 __kvm_skip_instr(vcpu);
581 return true;
582 }
583
584 /* Open-coded version of timer_get_offset() to allow for kern_hyp_va() */
hyp_timer_get_offset(struct arch_timer_context * ctxt)585 static inline u64 hyp_timer_get_offset(struct arch_timer_context *ctxt)
586 {
587 u64 offset = 0;
588
589 if (ctxt->offset.vm_offset)
590 offset += *kern_hyp_va(ctxt->offset.vm_offset);
591 if (ctxt->offset.vcpu_offset)
592 offset += *kern_hyp_va(ctxt->offset.vcpu_offset);
593
594 return offset;
595 }
596
compute_counter_value(struct arch_timer_context * ctxt)597 static inline u64 compute_counter_value(struct arch_timer_context *ctxt)
598 {
599 return arch_timer_read_cntpct_el0() - hyp_timer_get_offset(ctxt);
600 }
601
kvm_handle_cntxct(struct kvm_vcpu * vcpu)602 static bool kvm_handle_cntxct(struct kvm_vcpu *vcpu)
603 {
604 struct arch_timer_context *ctxt;
605 u32 sysreg;
606 u64 val;
607
608 /*
609 * We only get here for 64bit guests, 32bit guests will hit
610 * the long and winding road all the way to the standard
611 * handling. Yes, it sucks to be irrelevant.
612 *
613 * Also, we only deal with non-hypervisor context here (either
614 * an EL1 guest, or a non-HYP context of an EL2 guest).
615 */
616 if (is_hyp_ctxt(vcpu))
617 return false;
618
619 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
620
621 switch (sysreg) {
622 case SYS_CNTPCT_EL0:
623 case SYS_CNTPCTSS_EL0:
624 if (vcpu_has_nv(vcpu)) {
625 /* Check for guest hypervisor trapping */
626 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
627 if (!vcpu_el2_e2h_is_set(vcpu))
628 val = (val & CNTHCTL_EL1PCTEN) << 10;
629
630 if (!(val & (CNTHCTL_EL1PCTEN << 10)))
631 return false;
632 }
633
634 ctxt = vcpu_ptimer(vcpu);
635 break;
636 case SYS_CNTVCT_EL0:
637 case SYS_CNTVCTSS_EL0:
638 if (vcpu_has_nv(vcpu)) {
639 /* Check for guest hypervisor trapping */
640 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
641
642 if (val & CNTHCTL_EL1TVCT)
643 return false;
644 }
645
646 ctxt = vcpu_vtimer(vcpu);
647 break;
648 default:
649 return false;
650 }
651
652 val = compute_counter_value(ctxt);
653
654 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
655 __kvm_skip_instr(vcpu);
656 return true;
657 }
658
handle_ampere1_tcr(struct kvm_vcpu * vcpu)659 static bool handle_ampere1_tcr(struct kvm_vcpu *vcpu)
660 {
661 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
662 int rt = kvm_vcpu_sys_get_rt(vcpu);
663 u64 val = vcpu_get_reg(vcpu, rt);
664
665 if (sysreg != SYS_TCR_EL1)
666 return false;
667
668 /*
669 * Affected parts do not advertise support for hardware Access Flag /
670 * Dirty state management in ID_AA64MMFR1_EL1.HAFDBS, but the underlying
671 * control bits are still functional. The architecture requires these be
672 * RES0 on systems that do not implement FEAT_HAFDBS.
673 *
674 * Uphold the requirements of the architecture by masking guest writes
675 * to TCR_EL1.{HA,HD} here.
676 */
677 val &= ~(TCR_HD | TCR_HA);
678 write_sysreg_el1(val, SYS_TCR);
679 __kvm_skip_instr(vcpu);
680 return true;
681 }
682
kvm_hyp_handle_sysreg(struct kvm_vcpu * vcpu,u64 * exit_code)683 static inline bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
684 {
685 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
686 handle_tx2_tvm(vcpu))
687 return true;
688
689 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) &&
690 handle_ampere1_tcr(vcpu))
691 return true;
692
693 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
694 __vgic_v3_perform_cpuif_access(vcpu) == 1)
695 return true;
696
697 if (kvm_handle_cntxct(vcpu))
698 return true;
699
700 return false;
701 }
702
kvm_hyp_handle_cp15_32(struct kvm_vcpu * vcpu,u64 * exit_code)703 static inline bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
704 {
705 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
706 __vgic_v3_perform_cpuif_access(vcpu) == 1)
707 return true;
708
709 return false;
710 }
711
kvm_hyp_handle_memory_fault(struct kvm_vcpu * vcpu,u64 * exit_code)712 static inline bool kvm_hyp_handle_memory_fault(struct kvm_vcpu *vcpu,
713 u64 *exit_code)
714 {
715 if (!__populate_fault_info(vcpu))
716 return true;
717
718 return false;
719 }
720 #define kvm_hyp_handle_iabt_low kvm_hyp_handle_memory_fault
721 #define kvm_hyp_handle_watchpt_low kvm_hyp_handle_memory_fault
722
kvm_hyp_handle_dabt_low(struct kvm_vcpu * vcpu,u64 * exit_code)723 static inline bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
724 {
725 if (kvm_hyp_handle_memory_fault(vcpu, exit_code))
726 return true;
727
728 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
729 bool valid;
730
731 valid = kvm_vcpu_trap_is_translation_fault(vcpu) &&
732 kvm_vcpu_dabt_isvalid(vcpu) &&
733 !kvm_vcpu_abt_issea(vcpu) &&
734 !kvm_vcpu_abt_iss1tw(vcpu);
735
736 if (valid) {
737 int ret = __vgic_v2_perform_cpuif_access(vcpu);
738
739 if (ret == 1)
740 return true;
741
742 /* Promote an illegal access to an SError.*/
743 if (ret == -1)
744 *exit_code = ARM_EXCEPTION_EL1_SERROR;
745 }
746 }
747
748 return false;
749 }
750
751 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
752
753 /*
754 * Allow the hypervisor to handle the exit with an exit handler if it has one.
755 *
756 * Returns true if the hypervisor handled the exit, and control should go back
757 * to the guest, or false if it hasn't.
758 */
kvm_hyp_handle_exit(struct kvm_vcpu * vcpu,u64 * exit_code,const exit_handler_fn * handlers)759 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code,
760 const exit_handler_fn *handlers)
761 {
762 exit_handler_fn fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
763 if (fn)
764 return fn(vcpu, exit_code);
765
766 return false;
767 }
768
synchronize_vcpu_pstate(struct kvm_vcpu * vcpu,u64 * exit_code)769 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code)
770 {
771 /*
772 * Check for the conditions of Cortex-A510's #2077057. When these occur
773 * SPSR_EL2 can't be trusted, but isn't needed either as it is
774 * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
775 * Are we single-stepping the guest, and took a PAC exception from the
776 * active-not-pending state?
777 */
778 if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) &&
779 vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
780 *vcpu_cpsr(vcpu) & DBG_SPSR_SS &&
781 ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
782 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
783
784 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
785 }
786
787 /*
788 * Return true when we were able to fixup the guest exit and should return to
789 * the guest, false when we should restore the host state and return to the
790 * main run loop.
791 */
__fixup_guest_exit(struct kvm_vcpu * vcpu,u64 * exit_code,const exit_handler_fn * handlers)792 static inline bool __fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code,
793 const exit_handler_fn *handlers)
794 {
795 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
796 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
797
798 if (ARM_SERROR_PENDING(*exit_code) &&
799 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
800 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
801
802 /*
803 * HVC already have an adjusted PC, which we need to
804 * correct in order to return to after having injected
805 * the SError.
806 *
807 * SMC, on the other hand, is *trapped*, meaning its
808 * preferred return address is the SMC itself.
809 */
810 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
811 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
812 }
813
814 /*
815 * We're using the raw exception code in order to only process
816 * the trap if no SError is pending. We will come back to the
817 * same PC once the SError has been injected, and replay the
818 * trapping instruction.
819 */
820 if (*exit_code != ARM_EXCEPTION_TRAP)
821 goto exit;
822
823 /* Check if there's an exit handler and allow it to handle the exit. */
824 if (kvm_hyp_handle_exit(vcpu, exit_code, handlers))
825 goto guest;
826 exit:
827 /* Return to the host kernel and handle the exit */
828 return false;
829
830 guest:
831 /* Re-enter the guest */
832 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
833 return true;
834 }
835
__kvm_unexpected_el2_exception(void)836 static inline void __kvm_unexpected_el2_exception(void)
837 {
838 extern char __guest_exit_restore_elr_and_panic[];
839 unsigned long addr, fixup;
840 struct kvm_exception_table_entry *entry, *end;
841 unsigned long elr_el2 = read_sysreg(elr_el2);
842
843 entry = &__start___kvm_ex_table;
844 end = &__stop___kvm_ex_table;
845
846 while (entry < end) {
847 addr = (unsigned long)&entry->insn + entry->insn;
848 fixup = (unsigned long)&entry->fixup + entry->fixup;
849
850 if (addr != elr_el2) {
851 entry++;
852 continue;
853 }
854
855 write_sysreg(fixup, elr_el2);
856 return;
857 }
858
859 /* Trigger a panic after restoring the hyp context. */
860 this_cpu_ptr(&kvm_hyp_ctxt)->sys_regs[ELR_EL2] = elr_el2;
861 write_sysreg(__guest_exit_restore_elr_and_panic, elr_el2);
862 }
863
864 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */
865