1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2024 Intel Corporation. */ 3 4 #ifndef _IXGBE_TYPE_E610_H_ 5 #define _IXGBE_TYPE_E610_H_ 6 7 #define BYTES_PER_DWORD 4 8 9 /* General E610 defines */ 10 #define IXGBE_MAX_VSI 768 11 12 /* Checksum and Shadow RAM pointers */ 13 #define E610_SR_SW_CHECKSUM_WORD 0x3F 14 15 /* Shadow RAM related */ 16 #define IXGBE_SR_WORDS_IN_1KB 512 17 18 /* Firmware Status Register (GL_FWSTS) */ 19 #define GL_FWSTS 0x00083048 /* Reset Source: POR */ 20 #define GL_FWSTS_EP_PF0 BIT(24) 21 #define GL_FWSTS_EP_PF1 BIT(25) 22 23 /* Global NVM General Status Register */ 24 #define GLNVM_GENS 0x000B6100 /* Reset Source: POR */ 25 #define GLNVM_GENS_SR_SIZE_M GENMASK(7, 5) 26 27 /* Flash Access Register */ 28 #define IXGBE_GLNVM_FLA 0x000B6108 /* Reset Source: POR */ 29 #define IXGBE_GLNVM_FLA_LOCKED_S 6 30 #define IXGBE_GLNVM_FLA_LOCKED_M BIT(6) 31 32 /* Admin Command Interface (ACI) registers */ 33 #define IXGBE_PF_HIDA(_i) (0x00085000 + ((_i) * 4)) 34 #define IXGBE_PF_HIDA_2(_i) (0x00085020 + ((_i) * 4)) 35 #define IXGBE_PF_HIBA(_i) (0x00084000 + ((_i) * 4)) 36 #define IXGBE_PF_HICR 0x00082048 37 38 #define IXGBE_PF_HICR_EN BIT(0) 39 #define IXGBE_PF_HICR_C BIT(1) 40 #define IXGBE_PF_HICR_SV BIT(2) 41 #define IXGBE_PF_HICR_EV BIT(3) 42 43 #define IXGBE_ACI_DESC_SIZE 32 44 #define IXGBE_ACI_DESC_SIZE_IN_DWORDS (IXGBE_ACI_DESC_SIZE / BYTES_PER_DWORD) 45 46 #define IXGBE_ACI_MAX_BUFFER_SIZE 4096 /* Size in bytes */ 47 #define IXGBE_ACI_SEND_DELAY_TIME_MS 10 48 #define IXGBE_ACI_SEND_MAX_EXECUTE 3 49 #define IXGBE_ACI_SEND_TIMEOUT_MS \ 50 (IXGBE_ACI_SEND_MAX_EXECUTE * IXGBE_ACI_SEND_DELAY_TIME_MS) 51 /* [ms] timeout of waiting for sync response */ 52 #define IXGBE_ACI_SYNC_RESPONSE_TIMEOUT 100000 53 /* [ms] timeout of waiting for async response */ 54 #define IXGBE_ACI_ASYNC_RESPONSE_TIMEOUT 150000 55 /* [ms] timeout of waiting for resource release */ 56 #define IXGBE_ACI_RELEASE_RES_TIMEOUT 10000 57 58 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 59 #define IXGBE_ACI_LG_BUF 512 60 61 /* Flags sub-structure 62 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 63 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 64 */ 65 66 #define IXGBE_ACI_FLAG_DD BIT(0) /* 0x1 */ 67 #define IXGBE_ACI_FLAG_CMP BIT(1) /* 0x2 */ 68 #define IXGBE_ACI_FLAG_ERR BIT(2) /* 0x4 */ 69 #define IXGBE_ACI_FLAG_VFE BIT(3) /* 0x8 */ 70 #define IXGBE_ACI_FLAG_LB BIT(9) /* 0x200 */ 71 #define IXGBE_ACI_FLAG_RD BIT(10) /* 0x400 */ 72 #define IXGBE_ACI_FLAG_VFC BIT(11) /* 0x800 */ 73 #define IXGBE_ACI_FLAG_BUF BIT(12) /* 0x1000 */ 74 #define IXGBE_ACI_FLAG_SI BIT(13) /* 0x2000 */ 75 #define IXGBE_ACI_FLAG_EI BIT(14) /* 0x4000 */ 76 #define IXGBE_ACI_FLAG_FE BIT(15) /* 0x8000 */ 77 78 /* Admin Command Interface (ACI) error codes */ 79 enum ixgbe_aci_err { 80 IXGBE_ACI_RC_OK = 0, /* Success */ 81 IXGBE_ACI_RC_EPERM = 1, /* Operation not permitted */ 82 IXGBE_ACI_RC_ENOENT = 2, /* No such element */ 83 IXGBE_ACI_RC_ESRCH = 3, /* Bad opcode */ 84 IXGBE_ACI_RC_EINTR = 4, /* Operation interrupted */ 85 IXGBE_ACI_RC_EIO = 5, /* I/O error */ 86 IXGBE_ACI_RC_ENXIO = 6, /* No such resource */ 87 IXGBE_ACI_RC_E2BIG = 7, /* Arg too long */ 88 IXGBE_ACI_RC_EAGAIN = 8, /* Try again */ 89 IXGBE_ACI_RC_ENOMEM = 9, /* Out of memory */ 90 IXGBE_ACI_RC_EACCES = 10, /* Permission denied */ 91 IXGBE_ACI_RC_EFAULT = 11, /* Bad address */ 92 IXGBE_ACI_RC_EBUSY = 12, /* Device or resource busy */ 93 IXGBE_ACI_RC_EEXIST = 13, /* Object already exists */ 94 IXGBE_ACI_RC_EINVAL = 14, /* Invalid argument */ 95 IXGBE_ACI_RC_ENOTTY = 15, /* Not a typewriter */ 96 IXGBE_ACI_RC_ENOSPC = 16, /* No space left or alloc failure */ 97 IXGBE_ACI_RC_ENOSYS = 17, /* Function not implemented */ 98 IXGBE_ACI_RC_ERANGE = 18, /* Parameter out of range */ 99 IXGBE_ACI_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 100 IXGBE_ACI_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 101 IXGBE_ACI_RC_EMODE = 21, /* Op not allowed in current dev mode */ 102 IXGBE_ACI_RC_EFBIG = 22, /* File too big */ 103 IXGBE_ACI_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 104 IXGBE_ACI_RC_ENOSEC = 24, /* Missing security manifest */ 105 IXGBE_ACI_RC_EBADSIG = 25, /* Bad RSA signature */ 106 IXGBE_ACI_RC_ESVN = 26, /* SVN number prohibits this package */ 107 IXGBE_ACI_RC_EBADMAN = 27, /* Manifest hash mismatch */ 108 IXGBE_ACI_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 109 IXGBE_ACI_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 110 }; 111 112 /* Admin Command Interface (ACI) opcodes */ 113 enum ixgbe_aci_opc { 114 ixgbe_aci_opc_get_ver = 0x0001, 115 ixgbe_aci_opc_driver_ver = 0x0002, 116 ixgbe_aci_opc_get_exp_err = 0x0005, 117 118 /* resource ownership */ 119 ixgbe_aci_opc_req_res = 0x0008, 120 ixgbe_aci_opc_release_res = 0x0009, 121 122 /* device/function capabilities */ 123 ixgbe_aci_opc_list_func_caps = 0x000A, 124 ixgbe_aci_opc_list_dev_caps = 0x000B, 125 126 /* safe disable of RXEN */ 127 ixgbe_aci_opc_disable_rxen = 0x000C, 128 129 /* FW events */ 130 ixgbe_aci_opc_get_fw_event = 0x0014, 131 132 /* PHY commands */ 133 ixgbe_aci_opc_get_phy_caps = 0x0600, 134 ixgbe_aci_opc_set_phy_cfg = 0x0601, 135 ixgbe_aci_opc_restart_an = 0x0605, 136 ixgbe_aci_opc_get_link_status = 0x0607, 137 ixgbe_aci_opc_set_event_mask = 0x0613, 138 ixgbe_aci_opc_get_link_topo = 0x06E0, 139 ixgbe_aci_opc_get_link_topo_pin = 0x06E1, 140 ixgbe_aci_opc_read_i2c = 0x06E2, 141 ixgbe_aci_opc_write_i2c = 0x06E3, 142 ixgbe_aci_opc_read_mdio = 0x06E4, 143 ixgbe_aci_opc_write_mdio = 0x06E5, 144 ixgbe_aci_opc_set_gpio_by_func = 0x06E6, 145 ixgbe_aci_opc_get_gpio_by_func = 0x06E7, 146 ixgbe_aci_opc_set_gpio = 0x06EC, 147 ixgbe_aci_opc_get_gpio = 0x06ED, 148 ixgbe_aci_opc_sff_eeprom = 0x06EE, 149 ixgbe_aci_opc_prog_topo_dev_nvm = 0x06F2, 150 ixgbe_aci_opc_read_topo_dev_nvm = 0x06F3, 151 152 /* NVM commands */ 153 ixgbe_aci_opc_nvm_read = 0x0701, 154 ixgbe_aci_opc_nvm_erase = 0x0702, 155 ixgbe_aci_opc_nvm_write = 0x0703, 156 ixgbe_aci_opc_nvm_cfg_read = 0x0704, 157 ixgbe_aci_opc_nvm_cfg_write = 0x0705, 158 ixgbe_aci_opc_nvm_checksum = 0x0706, 159 ixgbe_aci_opc_nvm_write_activate = 0x0707, 160 ixgbe_aci_opc_nvm_sr_dump = 0x0707, 161 ixgbe_aci_opc_nvm_save_factory_settings = 0x0708, 162 ixgbe_aci_opc_nvm_update_empr = 0x0709, 163 ixgbe_aci_opc_nvm_pkg_data = 0x070A, 164 ixgbe_aci_opc_nvm_pass_component_tbl = 0x070B, 165 166 /* Alternate Structure Commands */ 167 ixgbe_aci_opc_write_alt_direct = 0x0900, 168 ixgbe_aci_opc_write_alt_indirect = 0x0901, 169 ixgbe_aci_opc_read_alt_direct = 0x0902, 170 ixgbe_aci_opc_read_alt_indirect = 0x0903, 171 ixgbe_aci_opc_done_alt_write = 0x0904, 172 ixgbe_aci_opc_clear_port_alt_write = 0x0906, 173 174 /* debug commands */ 175 ixgbe_aci_opc_debug_dump_internals = 0xFF08, 176 177 /* SystemDiagnostic commands */ 178 ixgbe_aci_opc_set_health_status_config = 0xFF20, 179 ixgbe_aci_opc_get_supported_health_status_codes = 0xFF21, 180 ixgbe_aci_opc_get_health_status = 0xFF22, 181 ixgbe_aci_opc_clear_health_status = 0xFF23, 182 }; 183 184 /* Get version (direct 0x0001) */ 185 struct ixgbe_aci_cmd_get_ver { 186 __le32 rom_ver; 187 __le32 fw_build; 188 u8 fw_branch; 189 u8 fw_major; 190 u8 fw_minor; 191 u8 fw_patch; 192 u8 api_branch; 193 u8 api_major; 194 u8 api_minor; 195 u8 api_patch; 196 }; 197 198 #define IXGBE_DRV_VER_STR_LEN_E610 32 199 200 /* Send driver version (indirect 0x0002) */ 201 struct ixgbe_aci_cmd_driver_ver { 202 u8 major_ver; 203 u8 minor_ver; 204 u8 build_ver; 205 u8 subbuild_ver; 206 u8 reserved[4]; 207 __le32 addr_high; 208 __le32 addr_low; 209 }; 210 211 /* Get Expanded Error Code (0x0005, direct) */ 212 struct ixgbe_aci_cmd_get_exp_err { 213 __le32 reason; 214 #define IXGBE_ACI_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 215 __le32 identifier; 216 u8 rsvd[8]; 217 }; 218 219 /* FW update timeout definitions are in milliseconds */ 220 #define IXGBE_NVM_TIMEOUT 180000 221 222 enum ixgbe_aci_res_access_type { 223 IXGBE_RES_READ = 1, 224 IXGBE_RES_WRITE 225 }; 226 227 enum ixgbe_aci_res_ids { 228 IXGBE_NVM_RES_ID = 1, 229 IXGBE_SPD_RES_ID, 230 IXGBE_CHANGE_LOCK_RES_ID, 231 IXGBE_GLOBAL_CFG_LOCK_RES_ID 232 }; 233 234 /* Request resource ownership (direct 0x0008) 235 * Release resource ownership (direct 0x0009) 236 */ 237 struct ixgbe_aci_cmd_req_res { 238 __le16 res_id; 239 __le16 access_type; 240 241 /* Upon successful completion, FW writes this value and driver is 242 * expected to release resource before timeout. This value is provided 243 * in milliseconds. 244 */ 245 __le32 timeout; 246 #define IXGBE_ACI_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 247 #define IXGBE_ACI_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 248 #define IXGBE_ACI_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 249 #define IXGBE_ACI_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 250 /* For SDP: pin ID of the SDP */ 251 __le32 res_number; 252 __le16 status; 253 #define IXGBE_ACI_RES_GLBL_SUCCESS 0 254 #define IXGBE_ACI_RES_GLBL_IN_PROG 1 255 #define IXGBE_ACI_RES_GLBL_DONE 2 256 u8 reserved[2]; 257 }; 258 259 /* Get function capabilities (indirect 0x000A) 260 * Get device capabilities (indirect 0x000B) 261 */ 262 struct ixgbe_aci_cmd_list_caps { 263 u8 cmd_flags; 264 u8 pf_index; 265 u8 reserved[2]; 266 __le32 count; 267 __le32 addr_high; 268 __le32 addr_low; 269 }; 270 271 /* Device/Function buffer entry, repeated per reported capability */ 272 struct ixgbe_aci_cmd_list_caps_elem { 273 __le16 cap; 274 #define IXGBE_ACI_CAPS_VALID_FUNCTIONS 0x0005 275 #define IXGBE_ACI_MAX_VALID_FUNCTIONS 0x8 276 #define IXGBE_ACI_CAPS_SRIOV 0x0012 277 #define IXGBE_ACI_CAPS_VF 0x0013 278 #define IXGBE_ACI_CAPS_VMDQ 0x0014 279 #define IXGBE_ACI_CAPS_VSI 0x0017 280 #define IXGBE_ACI_CAPS_DCB 0x0018 281 #define IXGBE_ACI_CAPS_RSS 0x0040 282 #define IXGBE_ACI_CAPS_RXQS 0x0041 283 #define IXGBE_ACI_CAPS_TXQS 0x0042 284 #define IXGBE_ACI_CAPS_MSIX 0x0043 285 #define IXGBE_ACI_CAPS_FD 0x0045 286 #define IXGBE_ACI_CAPS_1588 0x0046 287 #define IXGBE_ACI_CAPS_MAX_MTU 0x0047 288 #define IXGBE_ACI_CAPS_NVM_VER 0x0048 289 #define IXGBE_ACI_CAPS_PENDING_NVM_VER 0x0049 290 #define IXGBE_ACI_CAPS_OROM_VER 0x004A 291 #define IXGBE_ACI_CAPS_PENDING_OROM_VER 0x004B 292 #define IXGBE_ACI_CAPS_PENDING_NET_VER 0x004D 293 #define IXGBE_ACI_CAPS_INLINE_IPSEC 0x0070 294 #define IXGBE_ACI_CAPS_NUM_ENABLED_PORTS 0x0072 295 #define IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE 0x0076 296 #define IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 297 #define IXGBE_ACI_CAPS_NVM_MGMT 0x0080 298 #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0 0x0081 299 #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1 0x0082 300 #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2 0x0083 301 #define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3 0x0084 302 u8 major_ver; 303 u8 minor_ver; 304 /* Number of resources described by this capability */ 305 __le32 number; 306 /* Only meaningful for some types of resources */ 307 __le32 logical_id; 308 /* Only meaningful for some types of resources */ 309 __le32 phys_id; 310 __le64 rsvd1; 311 __le64 rsvd2; 312 }; 313 314 /* Disable RXEN (direct 0x000C) */ 315 struct ixgbe_aci_cmd_disable_rxen { 316 u8 lport_num; 317 u8 reserved[15]; 318 }; 319 320 /* Get PHY capabilities (indirect 0x0600) */ 321 struct ixgbe_aci_cmd_get_phy_caps { 322 u8 lport_num; 323 u8 reserved; 324 __le16 param0; 325 /* 18.0 - Report qualified modules */ 326 #define IXGBE_ACI_GET_PHY_RQM BIT(0) 327 /* 18.1 - 18.3 : Report mode 328 * 000b - Report topology capabilities, without media 329 * 001b - Report topology capabilities, with media 330 * 010b - Report Active configuration 331 * 011b - Report PHY Type and FEC mode capabilities 332 * 100b - Report Default capabilities 333 */ 334 #define IXGBE_ACI_REPORT_MODE_M GENMASK(3, 1) 335 #define IXGBE_ACI_REPORT_TOPO_CAP_NO_MEDIA 0 336 #define IXGBE_ACI_REPORT_TOPO_CAP_MEDIA BIT(1) 337 #define IXGBE_ACI_REPORT_ACTIVE_CFG BIT(2) 338 #define IXGBE_ACI_REPORT_DFLT_CFG BIT(3) 339 __le32 reserved1; 340 __le32 addr_high; 341 __le32 addr_low; 342 }; 343 344 /* This is #define of PHY type (Extended): 345 * The first set of defines is for phy_type_low. 346 */ 347 #define IXGBE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 348 #define IXGBE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 349 #define IXGBE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 350 #define IXGBE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 351 #define IXGBE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 352 #define IXGBE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 353 #define IXGBE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 354 #define IXGBE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 355 #define IXGBE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 356 #define IXGBE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 357 #define IXGBE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 358 #define IXGBE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 359 #define IXGBE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 360 #define IXGBE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 361 #define IXGBE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 362 #define IXGBE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 363 #define IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 364 #define IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 365 #define IXGBE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 366 #define IXGBE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 367 #define IXGBE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 368 #define IXGBE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 369 #define IXGBE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 370 #define IXGBE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 371 #define IXGBE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 372 #define IXGBE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 373 #define IXGBE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 374 #define IXGBE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 375 #define IXGBE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 376 #define IXGBE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 377 #define IXGBE_PHY_TYPE_LOW_MAX_INDEX 29 378 /* The second set of defines is for phy_type_high. */ 379 #define IXGBE_PHY_TYPE_HIGH_10BASE_T BIT_ULL(1) 380 #define IXGBE_PHY_TYPE_HIGH_10M_SGMII BIT_ULL(2) 381 #define IXGBE_PHY_TYPE_HIGH_2500M_SGMII BIT_ULL(56) 382 #define IXGBE_PHY_TYPE_HIGH_100M_USXGMII BIT_ULL(57) 383 #define IXGBE_PHY_TYPE_HIGH_1G_USXGMII BIT_ULL(58) 384 #define IXGBE_PHY_TYPE_HIGH_2500M_USXGMII BIT_ULL(59) 385 #define IXGBE_PHY_TYPE_HIGH_5G_USXGMII BIT_ULL(60) 386 #define IXGBE_PHY_TYPE_HIGH_10G_USXGMII BIT_ULL(61) 387 #define IXGBE_PHY_TYPE_HIGH_MAX_INDEX 61 388 389 struct ixgbe_aci_cmd_get_phy_caps_data { 390 __le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */ 391 __le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */ 392 u8 caps; 393 #define IXGBE_ACI_PHY_EN_TX_LINK_PAUSE BIT(0) 394 #define IXGBE_ACI_PHY_EN_RX_LINK_PAUSE BIT(1) 395 #define IXGBE_ACI_PHY_LOW_POWER_MODE BIT(2) 396 #define IXGBE_ACI_PHY_EN_LINK BIT(3) 397 #define IXGBE_ACI_PHY_AN_MODE BIT(4) 398 #define IXGBE_ACI_PHY_EN_MOD_QUAL BIT(5) 399 #define IXGBE_ACI_PHY_EN_LESM BIT(6) 400 #define IXGBE_ACI_PHY_EN_AUTO_FEC BIT(7) 401 #define IXGBE_ACI_PHY_CAPS_MASK GENMASK(7, 0) 402 u8 low_power_ctrl_an; 403 #define IXGBE_ACI_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 404 #define IXGBE_ACI_PHY_AN_EN_CLAUSE28 BIT(1) 405 #define IXGBE_ACI_PHY_AN_EN_CLAUSE73 BIT(2) 406 #define IXGBE_ACI_PHY_AN_EN_CLAUSE37 BIT(3) 407 __le16 eee_cap; 408 #define IXGBE_ACI_PHY_EEE_EN_100BASE_TX BIT(0) 409 #define IXGBE_ACI_PHY_EEE_EN_1000BASE_T BIT(1) 410 #define IXGBE_ACI_PHY_EEE_EN_10GBASE_T BIT(2) 411 #define IXGBE_ACI_PHY_EEE_EN_1000BASE_KX BIT(3) 412 #define IXGBE_ACI_PHY_EEE_EN_10GBASE_KR BIT(4) 413 #define IXGBE_ACI_PHY_EEE_EN_25GBASE_KR BIT(5) 414 #define IXGBE_ACI_PHY_EEE_EN_10BASE_T BIT(11) 415 __le16 eeer_value; 416 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 417 u8 phy_fw_ver[8]; 418 u8 link_fec_options; 419 #define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 420 #define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 421 #define IXGBE_ACI_PHY_FEC_25G_RS_528_REQ BIT(2) 422 #define IXGBE_ACI_PHY_FEC_25G_KR_REQ BIT(3) 423 #define IXGBE_ACI_PHY_FEC_25G_RS_544_REQ BIT(4) 424 #define IXGBE_ACI_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 425 #define IXGBE_ACI_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 426 #define IXGBE_ACI_PHY_FEC_MASK 0xdf 427 u8 module_compliance_enforcement; 428 #define IXGBE_ACI_MOD_ENFORCE_STRICT_MODE BIT(0) 429 u8 extended_compliance_code; 430 #define IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE 3 431 u8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE]; 432 #define IXGBE_ACI_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 433 #define IXGBE_ACI_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 434 #define IXGBE_ACI_MOD_TYPE_IDENT 1 435 #define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 436 #define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 437 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 438 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 439 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 440 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 441 #define IXGBE_ACI_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 442 #define IXGBE_ACI_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 443 u8 qualified_module_count; 444 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 445 #define IXGBE_ACI_QUAL_MOD_COUNT_MAX 16 446 struct { 447 u8 v_oui[3]; 448 u8 rsvd3; 449 u8 v_part[16]; 450 __le32 v_rev; 451 __le64 rsvd4; 452 } qual_modules[IXGBE_ACI_QUAL_MOD_COUNT_MAX]; 453 }; 454 455 /* Set PHY capabilities (direct 0x0601) 456 * NOTE: This command must be followed by setup link and restart auto-neg 457 */ 458 struct ixgbe_aci_cmd_set_phy_cfg { 459 u8 lport_num; 460 u8 reserved[7]; 461 __le32 addr_high; 462 __le32 addr_low; 463 }; 464 465 /* Set PHY config command data structure */ 466 struct ixgbe_aci_cmd_set_phy_cfg_data { 467 __le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */ 468 __le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */ 469 u8 caps; 470 #define IXGBE_ACI_PHY_ENA_VALID_MASK 0xef 471 #define IXGBE_ACI_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 472 #define IXGBE_ACI_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 473 #define IXGBE_ACI_PHY_ENA_LOW_POWER BIT(2) 474 #define IXGBE_ACI_PHY_ENA_LINK BIT(3) 475 #define IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT BIT(5) 476 #define IXGBE_ACI_PHY_ENA_LESM BIT(6) 477 #define IXGBE_ACI_PHY_ENA_AUTO_FEC BIT(7) 478 u8 low_power_ctrl_an; 479 __le16 eee_cap; /* Value from ixgbe_aci_get_phy_caps */ 480 __le16 eeer_value; /* Use defines from ixgbe_aci_get_phy_caps */ 481 u8 link_fec_opt; /* Use defines from ixgbe_aci_get_phy_caps */ 482 u8 module_compliance_enforcement; 483 }; 484 485 /* Restart AN command data structure (direct 0x0605) 486 * Also used for response, with only the lport_num field present. 487 */ 488 struct ixgbe_aci_cmd_restart_an { 489 u8 lport_num; 490 u8 reserved; 491 u8 cmd_flags; 492 #define IXGBE_ACI_RESTART_AN_LINK_RESTART BIT(1) 493 #define IXGBE_ACI_RESTART_AN_LINK_ENABLE BIT(2) 494 u8 reserved2[13]; 495 }; 496 497 /* Get link status (indirect 0x0607), also used for Link Status Event */ 498 struct ixgbe_aci_cmd_get_link_status { 499 u8 lport_num; 500 u8 reserved; 501 __le16 cmd_flags; 502 #define IXGBE_ACI_LSE_M GENMASK(1, 0) 503 #define IXGBE_ACI_LSE_NOP 0x0 504 #define IXGBE_ACI_LSE_DIS 0x2 505 #define IXGBE_ACI_LSE_ENA 0x3 506 /* only response uses this flag */ 507 #define IXGBE_ACI_LSE_IS_ENABLED 0x1 508 __le32 reserved2; 509 __le32 addr_high; 510 __le32 addr_low; 511 }; 512 513 /* Get link status response data structure, also used for Link Status Event */ 514 struct ixgbe_aci_cmd_get_link_status_data { 515 u8 topo_media_conflict; 516 #define IXGBE_ACI_LINK_TOPO_CONFLICT BIT(0) 517 #define IXGBE_ACI_LINK_MEDIA_CONFLICT BIT(1) 518 #define IXGBE_ACI_LINK_TOPO_CORRUPT BIT(2) 519 #define IXGBE_ACI_LINK_TOPO_UNREACH_PRT BIT(4) 520 #define IXGBE_ACI_LINK_TOPO_UNDRUTIL_PRT BIT(5) 521 #define IXGBE_ACI_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 522 #define IXGBE_ACI_LINK_TOPO_UNSUPP_MEDIA BIT(7) 523 u8 link_cfg_err; 524 #define IXGBE_ACI_LINK_CFG_ERR BIT(0) 525 #define IXGBE_ACI_LINK_CFG_COMPLETED BIT(1) 526 #define IXGBE_ACI_LINK_ACT_PORT_OPT_INVAL BIT(2) 527 #define IXGBE_ACI_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 528 #define IXGBE_ACI_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 529 #define IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 530 #define IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 531 #define IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 532 u8 link_info; 533 #define IXGBE_ACI_LINK_UP BIT(0) /* Link Status */ 534 #define IXGBE_ACI_LINK_FAULT BIT(1) 535 #define IXGBE_ACI_LINK_FAULT_TX BIT(2) 536 #define IXGBE_ACI_LINK_FAULT_RX BIT(3) 537 #define IXGBE_ACI_LINK_FAULT_REMOTE BIT(4) 538 #define IXGBE_ACI_LINK_UP_PORT BIT(5) /* External Port Link Status */ 539 #define IXGBE_ACI_MEDIA_AVAILABLE BIT(6) 540 #define IXGBE_ACI_SIGNAL_DETECT BIT(7) 541 u8 an_info; 542 #define IXGBE_ACI_AN_COMPLETED BIT(0) 543 #define IXGBE_ACI_LP_AN_ABILITY BIT(1) 544 #define IXGBE_ACI_PD_FAULT BIT(2) /* Parallel Detection Fault */ 545 #define IXGBE_ACI_FEC_EN BIT(3) 546 #define IXGBE_ACI_PHY_LOW_POWER BIT(4) /* Low Power State */ 547 #define IXGBE_ACI_LINK_PAUSE_TX BIT(5) 548 #define IXGBE_ACI_LINK_PAUSE_RX BIT(6) 549 #define IXGBE_ACI_QUALIFIED_MODULE BIT(7) 550 u8 ext_info; 551 #define IXGBE_ACI_LINK_PHY_TEMP_ALARM BIT(0) 552 #define IXGBE_ACI_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 553 /* Port Tx Suspended */ 554 #define IXGBE_ACI_LINK_TX_ACTIVE 0 555 #define IXGBE_ACI_LINK_TX_DRAINED 1 556 #define IXGBE_ACI_LINK_TX_FLUSHED 3 557 u8 lb_status; 558 #define IXGBE_ACI_LINK_LB_PHY_LCL BIT(0) 559 #define IXGBE_ACI_LINK_LB_PHY_RMT BIT(1) 560 #define IXGBE_ACI_LINK_LB_MAC_LCL BIT(2) 561 __le16 max_frame_size; 562 u8 cfg; 563 #define IXGBE_ACI_LINK_25G_KR_FEC_EN BIT(0) 564 #define IXGBE_ACI_LINK_25G_RS_528_FEC_EN BIT(1) 565 #define IXGBE_ACI_LINK_25G_RS_544_FEC_EN BIT(2) 566 #define IXGBE_ACI_FEC_MASK GENMASK(2, 0) 567 /* Pacing Config */ 568 #define IXGBE_ACI_CFG_PACING_M GENMASK(6, 3) 569 #define IXGBE_ACI_CFG_PACING_TYPE_M BIT(7) 570 #define IXGBE_ACI_CFG_PACING_TYPE_AVG 0 571 #define IXGBE_ACI_CFG_PACING_TYPE_FIXED IXGBE_ACI_CFG_PACING_TYPE_M 572 /* External Device Power Ability */ 573 u8 power_desc; 574 #define IXGBE_ACI_PWR_CLASS_M GENMASK(5, 0) 575 #define IXGBE_ACI_LINK_PWR_BASET_LOW_HIGH 0 576 #define IXGBE_ACI_LINK_PWR_BASET_HIGH 1 577 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_1 0 578 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_2 1 579 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_3 2 580 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_4 3 581 __le16 link_speed; 582 #define IXGBE_ACI_LINK_SPEED_M GENMASK(10, 0) 583 #define IXGBE_ACI_LINK_SPEED_10MB BIT(0) 584 #define IXGBE_ACI_LINK_SPEED_100MB BIT(1) 585 #define IXGBE_ACI_LINK_SPEED_1000MB BIT(2) 586 #define IXGBE_ACI_LINK_SPEED_2500MB BIT(3) 587 #define IXGBE_ACI_LINK_SPEED_5GB BIT(4) 588 #define IXGBE_ACI_LINK_SPEED_10GB BIT(5) 589 #define IXGBE_ACI_LINK_SPEED_20GB BIT(6) 590 #define IXGBE_ACI_LINK_SPEED_25GB BIT(7) 591 #define IXGBE_ACI_LINK_SPEED_40GB BIT(8) 592 #define IXGBE_ACI_LINK_SPEED_50GB BIT(9) 593 #define IXGBE_ACI_LINK_SPEED_100GB BIT(10) 594 #define IXGBE_ACI_LINK_SPEED_200GB BIT(11) 595 #define IXGBE_ACI_LINK_SPEED_UNKNOWN BIT(15) 596 __le16 reserved3; 597 u8 ext_fec_status; 598 #define IXGBE_ACI_LINK_RS_272_FEC_EN BIT(0) /* RS 272 FEC enabled */ 599 u8 reserved4; 600 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 601 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 602 /* Get link status version 2 link partner data */ 603 __le64 lp_phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 604 __le64 lp_phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 605 u8 lp_fec_adv; 606 #define IXGBE_ACI_LINK_LP_10G_KR_FEC_CAP BIT(0) 607 #define IXGBE_ACI_LINK_LP_25G_KR_FEC_CAP BIT(1) 608 #define IXGBE_ACI_LINK_LP_RS_528_FEC_CAP BIT(2) 609 #define IXGBE_ACI_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 610 #define IXGBE_ACI_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 611 #define IXGBE_ACI_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 612 u8 lp_fec_req; 613 #define IXGBE_ACI_LINK_LP_10G_KR_FEC_REQ BIT(0) 614 #define IXGBE_ACI_LINK_LP_25G_KR_FEC_REQ BIT(1) 615 #define IXGBE_ACI_LINK_LP_RS_528_FEC_REQ BIT(2) 616 #define IXGBE_ACI_LINK_LP_KR_272_FEC_REQ BIT(3) 617 u8 lp_flowcontrol; 618 #define IXGBE_ACI_LINK_LP_PAUSE_ADV BIT(0) 619 #define IXGBE_ACI_LINK_LP_ASM_DIR_ADV BIT(1) 620 u8 reserved5[5]; 621 } __packed; 622 623 /* Set event mask command (direct 0x0613) */ 624 struct ixgbe_aci_cmd_set_event_mask { 625 u8 lport_num; 626 u8 reserved[7]; 627 __le16 event_mask; 628 #define IXGBE_ACI_LINK_EVENT_UPDOWN BIT(1) 629 #define IXGBE_ACI_LINK_EVENT_MEDIA_NA BIT(2) 630 #define IXGBE_ACI_LINK_EVENT_LINK_FAULT BIT(3) 631 #define IXGBE_ACI_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 632 #define IXGBE_ACI_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 633 #define IXGBE_ACI_LINK_EVENT_SIGNAL_DETECT BIT(6) 634 #define IXGBE_ACI_LINK_EVENT_AN_COMPLETED BIT(7) 635 #define IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 636 #define IXGBE_ACI_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 637 #define IXGBE_ACI_LINK_EVENT_TOPO_CONFLICT BIT(10) 638 #define IXGBE_ACI_LINK_EVENT_MEDIA_CONFLICT BIT(11) 639 #define IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 640 u8 reserved1[6]; 641 }; 642 643 struct ixgbe_aci_cmd_link_topo_params { 644 u8 lport_num; 645 u8 lport_num_valid; 646 #define IXGBE_ACI_LINK_TOPO_PORT_NUM_VALID BIT(0) 647 u8 node_type_ctx; 648 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_M GENMASK(3, 0) 649 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_PHY 0 650 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 651 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 652 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_LED_CTRL 3 653 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_LED 4 654 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_THERMAL 5 655 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_CAGE 6 656 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_MEZZ 7 657 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 658 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_CLK_CTRL 9 659 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_CLK_MUX 10 660 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_GPS 11 661 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_S 4 662 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_M GENMASK(7, 4) 663 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_GLOBAL 0 664 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_BOARD 1 665 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_PORT 2 666 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE 3 667 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE_HANDLE 4 668 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_DIRECT_BUS_ACCESS 5 669 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE_HANDLE_BUS_ADDRESS 6 670 u8 index; 671 }; 672 673 struct ixgbe_aci_cmd_link_topo_addr { 674 struct ixgbe_aci_cmd_link_topo_params topo_params; 675 __le16 handle; 676 /* Used to decode the handle field */ 677 #define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 678 #define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 679 #define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 680 }; 681 682 /* Get Link Topology Handle (direct, 0x06E0) */ 683 struct ixgbe_aci_cmd_get_link_topo { 684 struct ixgbe_aci_cmd_link_topo_addr addr; 685 u8 node_part_num; 686 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 687 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 688 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_SI5384 0x25 689 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_C827 0x31 690 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 691 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 692 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_E610_PTC 0x49 693 u8 rsvd[9]; 694 }; 695 696 /* Get Link Topology Pin (direct, 0x06E1) */ 697 struct ixgbe_aci_cmd_get_link_topo_pin { 698 struct ixgbe_aci_cmd_link_topo_addr addr; 699 u8 input_io_params; 700 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_GPIO 0 701 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_RESET_N 1 702 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_INT_N 2 703 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_PRESENT_N 3 704 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_TX_DIS 4 705 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_MODSEL_N 5 706 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_LPMODE 6 707 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_TX_FAULT 7 708 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_RX_LOSS 8 709 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_RS0 9 710 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_RS1 10 711 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_EEPROM_WP 11 712 /* 12 repeats intentionally due to two different uses depending on context */ 713 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_LED 12 714 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_RED_LED 12 715 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_GREEN_LED 13 716 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_BLUE_LED 14 717 #define IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_GPIO 3 718 /* Use IXGBE_ACI_LINK_TOPO_NODE_TYPE_* for the type values */ 719 u8 output_io_params; 720 /* Use IXGBE_ACI_LINK_TOPO_NODE_TYPE_* for the type values */ 721 u8 output_io_flags; 722 #define IXGBE_ACI_LINK_TOPO_OUTPUT_POLARITY BIT(5) 723 #define IXGBE_ACI_LINK_TOPO_OUTPUT_VALUE BIT(6) 724 #define IXGBE_ACI_LINK_TOPO_OUTPUT_DRIVEN BIT(7) 725 u8 rsvd[7]; 726 }; 727 728 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 729 struct ixgbe_aci_cmd_sff_eeprom { 730 u8 lport_num; 731 u8 lport_num_valid; 732 #define IXGBE_ACI_SFF_PORT_NUM_VALID BIT(0) 733 __le16 i2c_bus_addr; 734 #define IXGBE_ACI_SFF_I2CBUS_7BIT_M GENMASK(6, 0) 735 #define IXGBE_ACI_SFF_I2CBUS_10BIT_M GENMASK(9, 0) 736 #define IXGBE_ACI_SFF_I2CBUS_TYPE_M BIT(10) 737 #define IXGBE_ACI_SFF_I2CBUS_TYPE_7BIT 0 738 #define IXGBE_ACI_SFF_I2CBUS_TYPE_10BIT IXGBE_ACI_SFF_I2CBUS_TYPE_M 739 #define IXGBE_ACI_SFF_NO_PAGE_BANK_UPDATE 0 740 #define IXGBE_ACI_SFF_UPDATE_PAGE 1 741 #define IXGBE_ACI_SFF_UPDATE_BANK 2 742 #define IXGBE_ACI_SFF_UPDATE_PAGE_BANK 3 743 #define IXGBE_ACI_SFF_IS_WRITE BIT(15) 744 __le16 i2c_offset; 745 u8 module_bank; 746 u8 module_page; 747 __le32 addr_high; 748 __le32 addr_low; 749 }; 750 751 /* NVM Read command (indirect 0x0701) 752 * NVM Erase commands (direct 0x0702) 753 * NVM Write commands (indirect 0x0703) 754 * NVM Write Activate commands (direct 0x0707) 755 * NVM Shadow RAM Dump commands (direct 0x0707) 756 */ 757 struct ixgbe_aci_cmd_nvm { 758 #define IXGBE_ACI_NVM_MAX_OFFSET 0xFFFFFF 759 __le16 offset_low; 760 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 761 u8 cmd_flags; 762 #define IXGBE_ACI_NVM_LAST_CMD BIT(0) 763 #define IXGBE_ACI_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 764 #define IXGBE_ACI_NVM_PRESERVE_ALL BIT(1) 765 #define IXGBE_ACI_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 766 #define IXGBE_ACI_NVM_ACTIV_SEL_OROM BIT(4) 767 #define IXGBE_ACI_NVM_ACTIV_SEL_NETLIST BIT(5) 768 #define IXGBE_ACI_NVM_SPECIAL_UPDATE BIT(6) 769 #define IXGBE_ACI_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 770 #define IXGBE_ACI_NVM_FLASH_ONLY BIT(7) 771 #define IXGBE_ACI_NVM_RESET_LVL_M GENMASK(1, 0) /* Write reply only */ 772 #define IXGBE_ACI_NVM_POR_FLAG 0 773 #define IXGBE_ACI_NVM_PERST_FLAG 1 774 #define IXGBE_ACI_NVM_EMPR_FLAG 2 775 #define IXGBE_ACI_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 776 /* For Write Activate, several flags are sent as part of a separate 777 * flags2 field using a separate byte. For simplicity of the software 778 * interface, we pass the flags as a 16 bit value so these flags are 779 * all offset by 8 bits 780 */ 781 #define IXGBE_ACI_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 782 __le16 module_typeid; 783 __le16 length; 784 #define IXGBE_ACI_NVM_ERASE_LEN 0xFFFF 785 __le32 addr_high; 786 __le32 addr_low; 787 }; 788 789 /* NVM Module_Type ID, needed offset and read_len for 790 * struct ixgbe_aci_cmd_nvm. 791 */ 792 #define IXGBE_ACI_NVM_START_POINT 0 793 794 /* NVM Checksum Command (direct, 0x0706) */ 795 struct ixgbe_aci_cmd_nvm_checksum { 796 u8 flags; 797 #define IXGBE_ACI_NVM_CHECKSUM_VERIFY BIT(0) 798 #define IXGBE_ACI_NVM_CHECKSUM_RECALC BIT(1) 799 u8 rsvd; 800 __le16 checksum; /* Used only by response */ 801 #define IXGBE_ACI_NVM_CHECKSUM_CORRECT 0xBABA 802 u8 rsvd2[12]; 803 }; 804 805 /** 806 * struct ixgbe_aci_desc - Admin Command (AC) descriptor 807 * @flags: IXGBE_ACI_FLAG_* flags 808 * @opcode: Admin command opcode 809 * @datalen: length in bytes of indirect/external data buffer 810 * @retval: return value from firmware 811 * @cookie_high: opaque data high-half 812 * @cookie_low: opaque data low-half 813 * @params: command-specific parameters 814 * 815 * Descriptor format for commands the driver posts via the 816 * Admin Command Interface (ACI). 817 * The firmware writes back onto the command descriptor and returns 818 * the result of the command. Asynchronous events that are not an immediate 819 * result of the command are written to the Admin Command Interface (ACI) using 820 * the same descriptor format. Descriptors are in little-endian notation with 821 * 32-bit words. 822 */ 823 struct ixgbe_aci_desc { 824 __le16 flags; 825 __le16 opcode; 826 __le16 datalen; 827 __le16 retval; 828 __le32 cookie_high; 829 __le32 cookie_low; 830 union { 831 u8 raw[16]; 832 struct ixgbe_aci_cmd_get_ver get_ver; 833 struct ixgbe_aci_cmd_driver_ver driver_ver; 834 struct ixgbe_aci_cmd_get_exp_err exp_err; 835 struct ixgbe_aci_cmd_req_res res_owner; 836 struct ixgbe_aci_cmd_list_caps get_cap; 837 struct ixgbe_aci_cmd_disable_rxen disable_rxen; 838 struct ixgbe_aci_cmd_get_phy_caps get_phy; 839 struct ixgbe_aci_cmd_set_phy_cfg set_phy; 840 struct ixgbe_aci_cmd_restart_an restart_an; 841 struct ixgbe_aci_cmd_get_link_status get_link_status; 842 struct ixgbe_aci_cmd_set_event_mask set_event_mask; 843 struct ixgbe_aci_cmd_get_link_topo get_link_topo; 844 struct ixgbe_aci_cmd_get_link_topo_pin get_link_topo_pin; 845 struct ixgbe_aci_cmd_sff_eeprom read_write_sff_param; 846 struct ixgbe_aci_cmd_nvm nvm; 847 struct ixgbe_aci_cmd_nvm_checksum nvm_checksum; 848 } params; 849 }; 850 851 /* E610-specific adapter context structures */ 852 853 struct ixgbe_link_status { 854 /* Refer to ixgbe_aci_phy_type for bits definition */ 855 u64 phy_type_low; 856 u64 phy_type_high; 857 u16 max_frame_size; 858 u16 link_speed; 859 u16 req_speeds; 860 u8 topo_media_conflict; 861 u8 link_cfg_err; 862 u8 lse_ena; /* Link Status Event notification */ 863 u8 link_info; 864 u8 an_info; 865 u8 ext_info; 866 u8 fec_info; 867 u8 pacing; 868 /* Refer to #define from module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE] 869 * of ixgbe_aci_get_phy_caps structure 870 */ 871 u8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE]; 872 }; 873 874 /* Common HW capabilities for SW use */ 875 struct ixgbe_hw_caps { 876 /* Write CSR protection */ 877 u64 wr_csr_prot; 878 u32 switching_mode; 879 /* switching mode supported - EVB switching (including cloud) */ 880 #define IXGBE_NVM_IMAGE_TYPE_EVB 0x0 881 882 /* Manageability mode & supported protocols over MCTP */ 883 u32 mgmt_mode; 884 #define IXGBE_MGMT_MODE_PASS_THRU_MODE_M GENMASK(3, 0) 885 #define IXGBE_MGMT_MODE_CTL_INTERFACE_M GENMASK(7, 4) 886 #define IXGBE_MGMT_MODE_REDIR_SB_INTERFACE_M GENMASK(11, 8) 887 888 u32 mgmt_protocols_mctp; 889 #define IXGBE_MGMT_MODE_PROTO_RSVD BIT(0) 890 #define IXGBE_MGMT_MODE_PROTO_PLDM BIT(1) 891 #define IXGBE_MGMT_MODE_PROTO_OEM BIT(2) 892 #define IXGBE_MGMT_MODE_PROTO_NC_SI BIT(3) 893 894 u32 os2bmc; 895 u32 valid_functions; 896 /* DCB capabilities */ 897 u32 active_tc_bitmap; 898 u32 maxtc; 899 900 /* RSS related capabilities */ 901 u32 rss_table_size; /* 512 for PFs and 64 for VFs */ 902 u32 rss_table_entry_width; /* RSS Entry width in bits */ 903 904 /* Tx/Rx queues */ 905 u32 num_rxq; /* Number/Total Rx queues */ 906 u32 rxq_first_id; /* First queue ID for Rx queues */ 907 u32 num_txq; /* Number/Total Tx queues */ 908 u32 txq_first_id; /* First queue ID for Tx queues */ 909 910 /* MSI-X vectors */ 911 u32 num_msix_vectors; 912 u32 msix_vector_first_id; 913 914 /* Max MTU for function or device */ 915 u32 max_mtu; 916 917 /* WOL related */ 918 u32 num_wol_proxy_fltr; 919 u32 wol_proxy_vsi_seid; 920 921 /* LED/SDP pin count */ 922 u32 led_pin_num; 923 u32 sdp_pin_num; 924 925 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */ 926 #define IXGBE_MAX_SUPPORTED_GPIO_LED 12 927 #define IXGBE_MAX_SUPPORTED_GPIO_SDP 8 928 u8 led[IXGBE_MAX_SUPPORTED_GPIO_LED]; 929 u8 sdp[IXGBE_MAX_SUPPORTED_GPIO_SDP]; 930 /* SR-IOV virtualization */ 931 u8 sr_iov_1_1; /* SR-IOV enabled */ 932 /* VMDQ */ 933 u8 vmdq; /* VMDQ supported */ 934 935 /* EVB capabilities */ 936 u8 evb_802_1_qbg; /* Edge Virtual Bridging */ 937 u8 evb_802_1_qbh; /* Bridge Port Extension */ 938 939 u8 dcb; 940 u8 iscsi; 941 u8 ieee_1588; 942 u8 mgmt_cem; 943 944 /* WoL and APM support */ 945 #define IXGBE_WOL_SUPPORT_M BIT(0) 946 #define IXGBE_ACPI_PROG_MTHD_M BIT(1) 947 #define IXGBE_PROXY_SUPPORT_M BIT(2) 948 u8 apm_wol_support; 949 u8 acpi_prog_mthd; 950 u8 proxy_support; 951 bool nvm_update_pending_nvm; 952 bool nvm_update_pending_orom; 953 bool nvm_update_pending_netlist; 954 #define IXGBE_NVM_PENDING_NVM_IMAGE BIT(0) 955 #define IXGBE_NVM_PENDING_OROM BIT(1) 956 #define IXGBE_NVM_PENDING_NETLIST BIT(2) 957 bool sec_rev_disabled; 958 bool update_disabled; 959 bool nvm_unified_update; 960 bool netlist_auth; 961 #define IXGBE_NVM_MGMT_SEC_REV_DISABLED BIT(0) 962 #define IXGBE_NVM_MGMT_UPDATE_DISABLED BIT(1) 963 #define IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 964 #define IXGBE_NVM_MGMT_NETLIST_AUTH_SUPPORT BIT(5) 965 bool no_drop_policy_support; 966 /* PCIe reset avoidance */ 967 bool pcie_reset_avoidance; /* false: not supported, true: supported */ 968 /* Post update reset restriction */ 969 bool reset_restrict_support; /* false: not supported, true: supported */ 970 971 /* External topology device images within the NVM */ 972 #define IXGBE_EXT_TOPO_DEV_IMG_COUNT 4 973 u32 ext_topo_dev_img_ver_high[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 974 u32 ext_topo_dev_img_ver_low[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 975 u8 ext_topo_dev_img_part_num[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 976 #define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_S 8 977 #define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M GENMASK(15, 8) 978 bool ext_topo_dev_img_load_en[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 979 #define IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0) 980 bool ext_topo_dev_img_prog_en[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 981 #define IXGBE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1) 982 } __packed; 983 984 /* Function specific capabilities */ 985 struct ixgbe_hw_func_caps { 986 u32 num_allocd_vfs; /* Number of allocated VFs */ 987 u32 vf_base_id; /* Logical ID of the first VF */ 988 u32 guar_num_vsi; 989 struct ixgbe_hw_caps common_cap; 990 bool no_drop_policy_ena; 991 }; 992 993 /* Device wide capabilities */ 994 struct ixgbe_hw_dev_caps { 995 struct ixgbe_hw_caps common_cap; 996 u32 num_vfs_exposed; /* Total number of VFs exposed */ 997 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 998 u32 num_flow_director_fltr; /* Number of FD filters available */ 999 u32 num_funcs; 1000 }; 1001 1002 /* ACI event information */ 1003 struct ixgbe_aci_event { 1004 struct ixgbe_aci_desc desc; 1005 u8 *msg_buf; 1006 u16 msg_len; 1007 u16 buf_len; 1008 }; 1009 1010 struct ixgbe_aci_info { 1011 struct mutex lock; /* admin command interface lock */ 1012 enum ixgbe_aci_err last_status; /* last status of sent admin command */ 1013 }; 1014 1015 /* Option ROM version information */ 1016 struct ixgbe_orom_info { 1017 u8 major; /* Major version of OROM */ 1018 u8 patch; /* Patch version of OROM */ 1019 u16 build; /* Build version of OROM */ 1020 u32 srev; /* Security revision */ 1021 }; 1022 1023 /* NVM version information */ 1024 struct ixgbe_nvm_info { 1025 u32 eetrack; 1026 u32 srev; 1027 u8 major; 1028 u8 minor; 1029 } __packed; 1030 1031 /* netlist version information */ 1032 struct ixgbe_netlist_info { 1033 u32 major; /* major high/low */ 1034 u32 minor; /* minor high/low */ 1035 u32 type; /* type high/low */ 1036 u32 rev; /* revision high/low */ 1037 u32 hash; /* SHA-1 hash word */ 1038 u16 cust_ver; /* customer version */ 1039 } __packed; 1040 1041 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 1042 * of the flash image. 1043 */ 1044 enum ixgbe_flash_bank { 1045 IXGBE_INVALID_FLASH_BANK, 1046 IXGBE_1ST_FLASH_BANK, 1047 IXGBE_2ND_FLASH_BANK, 1048 }; 1049 1050 /* information for accessing NVM, OROM, and Netlist flash banks */ 1051 struct ixgbe_bank_info { 1052 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 1053 u32 nvm_size; /* Size of NVM bank */ 1054 u32 orom_ptr; /* Pointer to 1st OROM bank */ 1055 u32 orom_size; /* Size of OROM bank */ 1056 u32 netlist_ptr; /* Ptr to 1st Netlist bank */ 1057 u32 netlist_size; /* Size of Netlist bank */ 1058 enum ixgbe_flash_bank nvm_bank; /* Active NVM bank */ 1059 enum ixgbe_flash_bank orom_bank; /* Active OROM bank */ 1060 enum ixgbe_flash_bank netlist_bank; /* Active Netlist bank */ 1061 }; 1062 1063 /* Flash Chip Information */ 1064 struct ixgbe_flash_info { 1065 struct ixgbe_orom_info orom; /* Option ROM version info */ 1066 u32 flash_size; /* Available flash size in bytes */ 1067 struct ixgbe_nvm_info nvm; /* NVM version information */ 1068 struct ixgbe_netlist_info netlist; /* Netlist version info */ 1069 struct ixgbe_bank_info banks; /* Flash Bank information */ 1070 u16 sr_words; /* Shadow RAM size in words */ 1071 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 1072 }; 1073 1074 #endif /* _IXGBE_TYPE_E610_H_ */ 1075