1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * Author: Jacek Anaszewski <[email protected]>
6 *
7 * Register interface file for JPEG driver on Exynos4x12.
8 */
9 #include <linux/io.h>
10 #include <linux/delay.h>
11
12 #include "jpeg-core.h"
13 #include "jpeg-hw-exynos4.h"
14 #include "jpeg-regs.h"
15
exynos4_jpeg_sw_reset(void __iomem * base)16 void exynos4_jpeg_sw_reset(void __iomem *base)
17 {
18 unsigned int reg;
19
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG);
21 writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE),
22 base + EXYNOS4_JPEG_CNTL_REG);
23
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG);
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG);
26
27 udelay(100);
28
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG);
30 }
31
exynos4_jpeg_set_enc_dec_mode(void __iomem * base,unsigned int mode)32 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode)
33 {
34 unsigned int reg;
35
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG);
37 /* set exynos4_jpeg mod register */
38 if (mode == S5P_JPEG_DECODE) {
39 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) |
40 EXYNOS4_DEC_MODE,
41 base + EXYNOS4_JPEG_CNTL_REG);
42 } else if (mode == S5P_JPEG_ENCODE) {/* encode */
43 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) |
44 EXYNOS4_ENC_MODE,
45 base + EXYNOS4_JPEG_CNTL_REG);
46 } else { /* disable both */
47 writel(reg & EXYNOS4_ENC_DEC_MODE_MASK,
48 base + EXYNOS4_JPEG_CNTL_REG);
49 }
50 }
51
__exynos4_jpeg_set_img_fmt(void __iomem * base,unsigned int img_fmt,unsigned int version)52 void __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt,
53 unsigned int version)
54 {
55 unsigned int reg;
56 unsigned int exynos4_swap_chroma_cbcr;
57 unsigned int exynos4_swap_chroma_crcb;
58
59 if (version == SJPEG_EXYNOS4) {
60 exynos4_swap_chroma_cbcr = EXYNOS4_SWAP_CHROMA_CBCR;
61 exynos4_swap_chroma_crcb = EXYNOS4_SWAP_CHROMA_CRCB;
62 } else {
63 exynos4_swap_chroma_cbcr = EXYNOS5433_SWAP_CHROMA_CBCR;
64 exynos4_swap_chroma_crcb = EXYNOS5433_SWAP_CHROMA_CRCB;
65 }
66
67 reg = readl(base + EXYNOS4_IMG_FMT_REG) &
68 EXYNOS4_ENC_IN_FMT_MASK; /* clear except enc format */
69
70 switch (img_fmt) {
71 case V4L2_PIX_FMT_GREY:
72 reg = reg | EXYNOS4_ENC_GRAY_IMG | EXYNOS4_GRAY_IMG_IP;
73 break;
74 case V4L2_PIX_FMT_RGB32:
75 reg = reg | EXYNOS4_ENC_RGB_IMG |
76 EXYNOS4_RGB_IP_RGB_32BIT_IMG;
77 break;
78 case V4L2_PIX_FMT_RGB565:
79 reg = reg | EXYNOS4_ENC_RGB_IMG |
80 EXYNOS4_RGB_IP_RGB_16BIT_IMG;
81 break;
82 case V4L2_PIX_FMT_NV24:
83 reg = reg | EXYNOS4_ENC_YUV_444_IMG |
84 EXYNOS4_YUV_444_IP_YUV_444_2P_IMG |
85 exynos4_swap_chroma_cbcr;
86 break;
87 case V4L2_PIX_FMT_NV42:
88 reg = reg | EXYNOS4_ENC_YUV_444_IMG |
89 EXYNOS4_YUV_444_IP_YUV_444_2P_IMG |
90 exynos4_swap_chroma_crcb;
91 break;
92 case V4L2_PIX_FMT_YUYV:
93 reg = reg | EXYNOS4_DEC_YUV_422_IMG |
94 EXYNOS4_YUV_422_IP_YUV_422_1P_IMG |
95 exynos4_swap_chroma_cbcr;
96 break;
97
98 case V4L2_PIX_FMT_YVYU:
99 reg = reg | EXYNOS4_DEC_YUV_422_IMG |
100 EXYNOS4_YUV_422_IP_YUV_422_1P_IMG |
101 exynos4_swap_chroma_crcb;
102 break;
103 case V4L2_PIX_FMT_NV16:
104 reg = reg | EXYNOS4_DEC_YUV_422_IMG |
105 EXYNOS4_YUV_422_IP_YUV_422_2P_IMG |
106 exynos4_swap_chroma_cbcr;
107 break;
108 case V4L2_PIX_FMT_NV61:
109 reg = reg | EXYNOS4_DEC_YUV_422_IMG |
110 EXYNOS4_YUV_422_IP_YUV_422_2P_IMG |
111 exynos4_swap_chroma_crcb;
112 break;
113 case V4L2_PIX_FMT_NV12:
114 reg = reg | EXYNOS4_DEC_YUV_420_IMG |
115 EXYNOS4_YUV_420_IP_YUV_420_2P_IMG |
116 exynos4_swap_chroma_cbcr;
117 break;
118 case V4L2_PIX_FMT_NV21:
119 reg = reg | EXYNOS4_DEC_YUV_420_IMG |
120 EXYNOS4_YUV_420_IP_YUV_420_2P_IMG |
121 exynos4_swap_chroma_crcb;
122 break;
123 case V4L2_PIX_FMT_YUV420:
124 reg = reg | EXYNOS4_DEC_YUV_420_IMG |
125 EXYNOS4_YUV_420_IP_YUV_420_3P_IMG |
126 exynos4_swap_chroma_cbcr;
127 break;
128 default:
129 break;
130
131 }
132
133 writel(reg, base + EXYNOS4_IMG_FMT_REG);
134 }
135
__exynos4_jpeg_set_enc_out_fmt(void __iomem * base,unsigned int out_fmt,unsigned int version)136 void __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt,
137 unsigned int version)
138 {
139 unsigned int reg;
140
141 reg = readl(base + EXYNOS4_IMG_FMT_REG) &
142 ~(version == SJPEG_EXYNOS4 ? EXYNOS4_ENC_FMT_MASK :
143 EXYNOS5433_ENC_FMT_MASK); /* clear enc format */
144
145 switch (out_fmt) {
146 case V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY:
147 reg = reg | EXYNOS4_ENC_FMT_GRAY;
148 break;
149
150 case V4L2_JPEG_CHROMA_SUBSAMPLING_444:
151 reg = reg | EXYNOS4_ENC_FMT_YUV_444;
152 break;
153
154 case V4L2_JPEG_CHROMA_SUBSAMPLING_422:
155 reg = reg | EXYNOS4_ENC_FMT_YUV_422;
156 break;
157
158 case V4L2_JPEG_CHROMA_SUBSAMPLING_420:
159 reg = reg | EXYNOS4_ENC_FMT_YUV_420;
160 break;
161
162 default:
163 break;
164 }
165
166 writel(reg, base + EXYNOS4_IMG_FMT_REG);
167 }
168
exynos4_jpeg_set_interrupt(void __iomem * base,unsigned int version)169 void exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version)
170 {
171 unsigned int reg;
172
173 if (version == SJPEG_EXYNOS4) {
174 reg = readl(base + EXYNOS4_INT_EN_REG) & ~EXYNOS4_INT_EN_MASK;
175 writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG);
176 } else {
177 reg = readl(base + EXYNOS4_INT_EN_REG) &
178 ~EXYNOS5433_INT_EN_MASK;
179 writel(reg | EXYNOS5433_INT_EN_ALL, base + EXYNOS4_INT_EN_REG);
180 }
181 }
182
exynos4_jpeg_get_int_status(void __iomem * base)183 unsigned int exynos4_jpeg_get_int_status(void __iomem *base)
184 {
185 return readl(base + EXYNOS4_INT_STATUS_REG);
186 }
187
exynos4_jpeg_set_huf_table_enable(void __iomem * base,int value)188 void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value)
189 {
190 unsigned int reg;
191
192 reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~EXYNOS4_HUF_TBL_EN;
193
194 if (value == 1)
195 writel(reg | EXYNOS4_HUF_TBL_EN,
196 base + EXYNOS4_JPEG_CNTL_REG);
197 else
198 writel(reg & ~EXYNOS4_HUF_TBL_EN,
199 base + EXYNOS4_JPEG_CNTL_REG);
200 }
201
exynos4_jpeg_set_sys_int_enable(void __iomem * base,int value)202 void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value)
203 {
204 unsigned int reg;
205
206 reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~(EXYNOS4_SYS_INT_EN);
207
208 if (value == 1)
209 writel(reg | EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG);
210 else
211 writel(reg & ~EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG);
212 }
213
exynos4_jpeg_set_stream_buf_address(void __iomem * base,unsigned int address)214 void exynos4_jpeg_set_stream_buf_address(void __iomem *base,
215 unsigned int address)
216 {
217 writel(address, base + EXYNOS4_OUT_MEM_BASE_REG);
218 }
219
exynos4_jpeg_set_stream_size(void __iomem * base,unsigned int x_value,unsigned int y_value)220 void exynos4_jpeg_set_stream_size(void __iomem *base,
221 unsigned int x_value, unsigned int y_value)
222 {
223 writel(0x0, base + EXYNOS4_JPEG_IMG_SIZE_REG); /* clear */
224 writel(EXYNOS4_X_SIZE(x_value) | EXYNOS4_Y_SIZE(y_value),
225 base + EXYNOS4_JPEG_IMG_SIZE_REG);
226 }
227
exynos4_jpeg_set_frame_buf_address(void __iomem * base,struct s5p_jpeg_addr * exynos4_jpeg_addr)228 void exynos4_jpeg_set_frame_buf_address(void __iomem *base,
229 struct s5p_jpeg_addr *exynos4_jpeg_addr)
230 {
231 writel(exynos4_jpeg_addr->y, base + EXYNOS4_IMG_BA_PLANE_1_REG);
232 writel(exynos4_jpeg_addr->cb, base + EXYNOS4_IMG_BA_PLANE_2_REG);
233 writel(exynos4_jpeg_addr->cr, base + EXYNOS4_IMG_BA_PLANE_3_REG);
234 }
235
exynos4_jpeg_set_encode_tbl_select(void __iomem * base,enum exynos4_jpeg_img_quality_level level)236 void exynos4_jpeg_set_encode_tbl_select(void __iomem *base,
237 enum exynos4_jpeg_img_quality_level level)
238 {
239 unsigned int reg;
240
241 reg = EXYNOS4_Q_TBL_COMP1_0 | EXYNOS4_Q_TBL_COMP2_1 |
242 EXYNOS4_Q_TBL_COMP3_1 |
243 EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_1 |
244 EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_0 |
245 EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_1;
246
247 writel(reg, base + EXYNOS4_TBL_SEL_REG);
248 }
249
exynos4_jpeg_set_dec_components(void __iomem * base,int n)250 void exynos4_jpeg_set_dec_components(void __iomem *base, int n)
251 {
252 unsigned int reg;
253
254 reg = readl(base + EXYNOS4_TBL_SEL_REG);
255
256 reg |= EXYNOS4_NF(n);
257 writel(reg, base + EXYNOS4_TBL_SEL_REG);
258 }
259
exynos4_jpeg_select_dec_q_tbl(void __iomem * base,char c,char x)260 void exynos4_jpeg_select_dec_q_tbl(void __iomem *base, char c, char x)
261 {
262 unsigned int reg;
263
264 reg = readl(base + EXYNOS4_TBL_SEL_REG);
265
266 reg |= EXYNOS4_Q_TBL_COMP(c, x);
267 writel(reg, base + EXYNOS4_TBL_SEL_REG);
268 }
269
exynos4_jpeg_select_dec_h_tbl(void __iomem * base,char c,char x)270 void exynos4_jpeg_select_dec_h_tbl(void __iomem *base, char c, char x)
271 {
272 unsigned int reg;
273
274 reg = readl(base + EXYNOS4_TBL_SEL_REG);
275
276 reg |= EXYNOS4_HUFF_TBL_COMP(c, x);
277 writel(reg, base + EXYNOS4_TBL_SEL_REG);
278 }
279
exynos4_jpeg_set_encode_hoff_cnt(void __iomem * base,unsigned int fmt)280 void exynos4_jpeg_set_encode_hoff_cnt(void __iomem *base, unsigned int fmt)
281 {
282 if (fmt == V4L2_PIX_FMT_GREY)
283 writel(0xd2, base + EXYNOS4_HUFF_CNT_REG);
284 else
285 writel(0x1a2, base + EXYNOS4_HUFF_CNT_REG);
286 }
287
exynos4_jpeg_get_stream_size(void __iomem * base)288 unsigned int exynos4_jpeg_get_stream_size(void __iomem *base)
289 {
290 return readl(base + EXYNOS4_BITSTREAM_SIZE_REG);
291 }
292
exynos4_jpeg_set_dec_bitstream_size(void __iomem * base,unsigned int size)293 void exynos4_jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size)
294 {
295 writel(size, base + EXYNOS4_BITSTREAM_SIZE_REG);
296 }
297
exynos4_jpeg_get_frame_fmt(void __iomem * base)298 unsigned int exynos4_jpeg_get_frame_fmt(void __iomem *base)
299 {
300 return readl(base + EXYNOS4_DECODE_IMG_FMT_REG) &
301 EXYNOS4_JPEG_DECODED_IMG_FMT_MASK;
302 }
303