1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <console/console.h>
4 #include <delay.h>
5 #include <soc/dp.h>
6 #include <soc/fimd.h>
7 #include <soc/i2c.h>
8 #include <soc/power.h>
9 #include <soc/sysreg.h>
10 #include <string.h>
11
12 /*
13 * Here is the rough outline of how we bring up the display:
14 * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
15 * 2. Source determines video mode by reading DPCD receiver capability field
16 * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
17 * 0000Dh).
18 * 3. Sink replies DPCD receiver capability field.
19 * 4. Source starts EDID read thru I2C-over-AUX.
20 * 5. Sink replies EDID thru I2C-over-AUX.
21 * 6. Source determines link configuration, such as MAX_LINK_RATE and
22 * MAX_LANE_COUNT. Source also determines which type of eDP Authentication
23 * method to use and writes DPCD link configuration field (DPCD 00100h to
24 * 0010Ah) including eDP configuration set (DPCD 0010Ah).
25 * 7. Source starts link training. Sink does clock recovery and equalization.
26 * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
27 * 9. Sink replies DPCD link status field. If main link is not stable, Source
28 * repeats Step 7.
29 * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
30 * parameters and recovers stream clock.
31 * 11. Source sends video data.
32 */
33
exynos_dp_init_dp(void)34 static int exynos_dp_init_dp(void)
35 {
36 int ret;
37 exynos_dp_reset();
38
39 /* SW defined function Normal operation */
40 exynos_dp_enable_sw_func(DP_ENABLE);
41
42 ret = exynos_dp_init_analog_func();
43 if (ret != EXYNOS_DP_SUCCESS)
44 return ret;
45
46 exynos_dp_init_hpd();
47 exynos_dp_init_aux();
48
49 return ret;
50 }
51
exynos_dp_calc_edid_check_sum(unsigned char * edid_data)52 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
53 {
54 int i;
55 unsigned char sum = 0;
56
57 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
58 sum = sum + edid_data[i];
59
60 return sum;
61 }
62
exynos_dp_read_edid(void)63 static unsigned int exynos_dp_read_edid(void)
64 {
65 unsigned char edid[EDID_BLOCK_LENGTH * 2];
66 unsigned int extend_block = 0;
67 unsigned char sum;
68 unsigned char test_vector;
69 int retval = 0;
70
71 /*
72 * EDID device address is 0x50.
73 * However, if necessary, you must have set upper address
74 * into E-EDID in I2C device, 0x30.
75 */
76
77 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
78 if (exynos_dp_read_byte_from_i2c
79 (I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG, &extend_block))
80 return -1;
81
82 if (extend_block > 0) {
83 /* Read EDID data */
84 retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
85 EDID_HEADER_PATTERN,
86 EDID_BLOCK_LENGTH,
87 &edid[EDID_HEADER_PATTERN]);
88
89 if (retval != 0) {
90 printk(BIOS_ERR, "DP EDID Read failed!\n");
91 return -1;
92 }
93 sum = exynos_dp_calc_edid_check_sum(edid);
94 if (sum != 0) {
95 printk(BIOS_ERR, "DP EDID bad checksum!\n");
96 return -1;
97 }
98 /* Read additional EDID data */
99 retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
100 EDID_BLOCK_LENGTH,
101 EDID_BLOCK_LENGTH,
102 &edid[EDID_BLOCK_LENGTH]);
103 if (retval != 0) {
104 printk(BIOS_ERR, "DP EDID Read failed!\n");
105 return -1;
106 }
107 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
108 if (sum != 0) {
109 printk(BIOS_ERR, "DP EDID bad checksum!\n");
110 return -1;
111 }
112 exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
113 &test_vector);
114 if (test_vector & DPCD_TEST_EDID_READ) {
115 exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
116 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
117 exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
118 DPCD_TEST_EDID_CHECKSUM_WRITE);
119 }
120 } else {
121 /* Read EDID data */
122 retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
123 EDID_HEADER_PATTERN,
124 EDID_BLOCK_LENGTH,
125 &edid[EDID_HEADER_PATTERN]);
126
127 if (retval != 0) {
128 printk(BIOS_ERR, "DP EDID Read failed!\n");
129 return -1;
130 }
131 sum = exynos_dp_calc_edid_check_sum(edid);
132 if (sum != 0) {
133 printk(BIOS_ERR, "DP EDID bad checksum!\n");
134 return -1;
135 }
136
137 exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
138 &test_vector);
139 if (test_vector & DPCD_TEST_EDID_READ) {
140 exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
141 edid[EDID_CHECKSUM]);
142 exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
143 DPCD_TEST_EDID_CHECKSUM_WRITE);
144 }
145 }
146
147 return 0;
148 }
149
exynos_dp_handle_edid(struct edp_device_info * edp_info)150 static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
151 {
152 unsigned char buf[12];
153 unsigned int ret;
154 unsigned char temp;
155 unsigned char retry_cnt;
156 unsigned char dpcd_rev[16];
157 unsigned char lane_bw[16];
158 unsigned char lane_cnt[16];
159
160 memset(dpcd_rev, 0, sizeof(dpcd_rev));
161 memset(lane_bw, 0, sizeof(lane_bw));
162 memset(lane_cnt, 0, sizeof(lane_cnt));
163 memset(buf, 0, sizeof(buf));
164
165 retry_cnt = 5;
166 while (retry_cnt) {
167 /* Read DPCD 0x0000-0x000b */
168 ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12,
169 buf);
170 if (ret != EXYNOS_DP_SUCCESS) {
171 if (retry_cnt == 0) {
172 printk(BIOS_ERR, "DP read_byte_from_dpcd() failed\n");
173 return ret;
174 }
175 retry_cnt--;
176 } else
177 break;
178 }
179 /* */
180 temp = buf[DPCD_DPCD_REV];
181 if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
182 edp_info->dpcd_rev = temp;
183 else {
184 printk(BIOS_ERR, "DP Wrong DPCD Rev : %x\n", temp);
185 return -1;
186 }
187 temp = buf[DPCD_MAX_LINK_RATE];
188 if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
189 edp_info->lane_bw = temp;
190 else {
191 printk(BIOS_ERR, "DP Wrong MAX LINK RATE : %x\n", temp);
192 return -1;
193 }
194 /*Refer VESA Display Port Standard Ver1.1a Page 120 */
195 if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
196 temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
197 if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
198 edp_info->dpcd_efc = 1;
199 else
200 edp_info->dpcd_efc = 0;
201 } else {
202 temp = buf[DPCD_MAX_LANE_COUNT];
203 edp_info->dpcd_efc = 0;
204 }
205
206 if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
207 temp == DP_LANE_CNT_4) {
208 edp_info->lane_cnt = temp;
209 } else {
210 printk(BIOS_ERR, "DP Wrong MAX LANE COUNT : %x\n", temp);
211 return -1;
212 }
213
214 if (edp_info->raw_edid){
215 ret = EXYNOS_DP_SUCCESS;
216 printk(BIOS_SPEW, "EDID compiled in, skipping read\n");
217 } else {
218 ret = exynos_dp_read_edid();
219 if (ret != EXYNOS_DP_SUCCESS) {
220 printk(BIOS_ERR, "DP exynos_dp_read_edid() failed\n");
221 return -1;
222 }
223 }
224
225 return ret;
226 }
227
exynos_dp_init_training(void)228 static void exynos_dp_init_training(void)
229 {
230 /*
231 * MACRO_RST must be applied after the PLL_LOCK to avoid
232 * the DP inter pair skew issue for at least 10 us
233 */
234 exynos_dp_reset_macro();
235
236 /* All DP analog module power up */
237 exynos_dp_set_analog_power_down(POWER_ALL, 0);
238 }
239
exynos_dp_link_start(struct edp_device_info * edp_info)240 static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
241 {
242 unsigned char buf[5];
243 unsigned int ret;
244
245 edp_info->lt_info.lt_status = DP_LT_CR;
246 edp_info->lt_info.ep_loop = 0;
247 edp_info->lt_info.cr_loop[0] = 0;
248 edp_info->lt_info.cr_loop[1] = 0;
249 edp_info->lt_info.cr_loop[2] = 0;
250 edp_info->lt_info.cr_loop[3] = 0;
251
252 /* Set sink to D0 (Sink Not Ready) mode. */
253 ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE,
254 DPCD_SET_POWER_STATE_D0);
255 if (ret != EXYNOS_DP_SUCCESS) {
256 printk(BIOS_ERR, "DP write_dpcd_byte failed\n");
257 return ret;
258 }
259
260 /* Set link rate and count as you want to establish*/
261 exynos_dp_set_link_bandwidth(edp_info->lane_bw);
262 exynos_dp_set_lane_count(edp_info->lane_cnt);
263
264 /* Setup RX configuration */
265 buf[0] = edp_info->lane_bw;
266 buf[1] = edp_info->lane_cnt;
267
268 ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2,
269 buf);
270 if (ret != EXYNOS_DP_SUCCESS) {
271 printk(BIOS_ERR, "DP write_dpcd_byte failed\n");
272 return ret;
273 }
274
275 exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0,
276 edp_info->lane_cnt);
277
278 /* Set training pattern 1 */
279 exynos_dp_set_training_pattern(TRAINING_PTN1);
280
281 /* Set RX training pattern */
282 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
283
284 buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
285 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
286 buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
287 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
288 buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
289 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
290 buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
291 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
292
293 ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET,
294 5, buf);
295 if (ret != EXYNOS_DP_SUCCESS) {
296 printk(BIOS_ERR, "DP write_dpcd_byte failed\n");
297 return ret;
298 }
299 return ret;
300 }
301
exynos_dp_training_pattern_dis(void)302 static unsigned int exynos_dp_training_pattern_dis(void)
303 {
304 unsigned int ret;
305
306 exynos_dp_set_training_pattern(DP_NONE);
307
308 ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
309 DPCD_TRAINING_PATTERN_DISABLED);
310 if (ret != EXYNOS_DP_SUCCESS) {
311 printk(BIOS_ERR, "DP requst_link_traninig_req failed\n");
312 return -1;
313 }
314
315 return ret;
316 }
317
exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)318 static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
319 {
320 unsigned char data;
321 unsigned int ret;
322
323 ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET,
324 &data);
325 if (ret != EXYNOS_DP_SUCCESS) {
326 printk(BIOS_ERR, "DP read_from_dpcd failed\n");
327 return -1;
328 }
329
330 if (enable)
331 data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
332 else
333 data = DPCD_LN_COUNT_SET(data);
334
335 ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
336 data);
337 if (ret != EXYNOS_DP_SUCCESS) {
338 printk(BIOS_ERR, "DP write_to_dpcd failed\n");
339 return -1;
340 }
341
342 return ret;
343 }
344
exynos_dp_set_enhanced_mode(unsigned char enhance_mode)345 static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode)
346 {
347 unsigned int ret;
348
349 ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode);
350 if (ret != EXYNOS_DP_SUCCESS) {
351 printk(BIOS_ERR, "DP rx_enhance_mode failed\n");
352 return -1;
353 }
354
355 exynos_dp_enable_enhanced_mode(enhance_mode);
356
357 return ret;
358 }
359
exynos_dp_read_dpcd_lane_stat(struct edp_device_info * edp_info,unsigned char * status)360 static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
361 unsigned char *status)
362 {
363 unsigned int ret, i;
364 unsigned char buf[2];
365 unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
366 const unsigned char shift_val[] = {0, 4, 0, 4};
367
368 ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf);
369 if (ret != EXYNOS_DP_SUCCESS) {
370 printk(BIOS_ERR, "DP read lane status failed\n");
371 return ret;
372 }
373
374 for (i = 0; i < edp_info->lane_cnt; i++) {
375 lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
376 if (lane_stat[0] != lane_stat[i]) {
377 printk(BIOS_ERR, "Wrong lane status\n");
378 return -1;
379 }
380 }
381
382 *status = lane_stat[0];
383
384 return ret;
385 }
386
exynos_dp_read_dpcd_adj_req(unsigned char lane_num,unsigned char * sw,unsigned char * em)387 static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
388 unsigned char *sw, unsigned char *em)
389 {
390 const unsigned char shift_val[] = {0, 4, 0, 4};
391 unsigned int ret;
392 unsigned char buf;
393 unsigned int dpcd_addr;
394
395 /*lane_num value is used as array index, so this range 0 ~ 3 */
396 dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
397
398 ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
399 if (ret != EXYNOS_DP_SUCCESS) {
400 printk(BIOS_ERR, "DP read adjust request failed\n");
401 return -1;
402 }
403
404 *sw = ((buf >> shift_val[lane_num]) & 0x03);
405 *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
406
407 return ret;
408 }
409
exynos_dp_equalizer_err_link(struct edp_device_info * edp_info)410 static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
411 {
412 int ret;
413
414 ret = exynos_dp_training_pattern_dis();
415 if (ret != EXYNOS_DP_SUCCESS) {
416 printk(BIOS_ERR, "DP training_patter_disable() failed\n");
417 edp_info->lt_info.lt_status = DP_LT_FAIL;
418 }
419
420 ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
421 if (ret != EXYNOS_DP_SUCCESS) {
422 printk(BIOS_ERR, "DP set_enhanced_mode() failed\n");
423 edp_info->lt_info.lt_status = DP_LT_FAIL;
424 }
425
426 return ret;
427 }
428
exynos_dp_reduce_link_rate(struct edp_device_info * edp_info)429 static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
430 {
431 int ret;
432
433 if (edp_info->lane_bw == DP_LANE_BW_2_70) {
434 edp_info->lane_bw = DP_LANE_BW_1_62;
435 printk(BIOS_ERR, "DP Change lane bw to 1.62Gbps\n");
436 edp_info->lt_info.lt_status = DP_LT_START;
437 ret = EXYNOS_DP_SUCCESS;
438 } else {
439 ret = exynos_dp_training_pattern_dis();
440 if (ret != EXYNOS_DP_SUCCESS)
441 printk(BIOS_ERR, "DP training_patter_disable() failed\n");
442
443 ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
444 if (ret != EXYNOS_DP_SUCCESS)
445 printk(BIOS_ERR, "DP set_enhanced_mode() failed\n");
446
447 edp_info->lt_info.lt_status = DP_LT_FAIL;
448 }
449
450 return ret;
451 }
452
exynos_dp_process_clock_recovery(struct edp_device_info * edp_info)453 static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
454 *edp_info)
455 {
456 unsigned int ret;
457 unsigned char lane_stat;
458 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
459 unsigned int i;
460 unsigned char adj_req_sw;
461 unsigned char adj_req_em;
462 unsigned char buf[5];
463
464 mdelay(1);
465
466 ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
467 if (ret != EXYNOS_DP_SUCCESS) {
468 printk(BIOS_ERR, "DP read lane status failed\n");
469 edp_info->lt_info.lt_status = DP_LT_FAIL;
470 return ret;
471 }
472
473 if (lane_stat & DP_LANE_STAT_CR_DONE) {
474 printk(BIOS_DEBUG,"DP clock Recovery training succeed\n");
475 exynos_dp_set_training_pattern(TRAINING_PTN2);
476
477 for (i = 0; i < edp_info->lane_cnt; i++) {
478 ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw,
479 &adj_req_em);
480 if (ret != EXYNOS_DP_SUCCESS) {
481 edp_info->lt_info.lt_status = DP_LT_FAIL;
482 return ret;
483 }
484
485 lt_ctl_val[i] = 0;
486 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
487
488 if ((adj_req_sw == VOLTAGE_LEVEL_3)
489 || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
490 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
491 MAX_PRE_EMPHASIS_REACH_3;
492 }
493 exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
494 }
495
496 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
497 buf[1] = lt_ctl_val[0];
498 buf[2] = lt_ctl_val[1];
499 buf[3] = lt_ctl_val[2];
500 buf[4] = lt_ctl_val[3];
501
502 ret = exynos_dp_write_bytes_to_dpcd(
503 DPCD_TRAINING_PATTERN_SET, 5, buf);
504 if (ret != EXYNOS_DP_SUCCESS) {
505 printk(BIOS_ERR, "DP write training pattern1 failed\n");
506 edp_info->lt_info.lt_status = DP_LT_FAIL;
507 return ret;
508 } else
509 edp_info->lt_info.lt_status = DP_LT_ET;
510 } else {
511 for (i = 0; i < edp_info->lane_cnt; i++) {
512 lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i);
513 ret = exynos_dp_read_dpcd_adj_req(i,
514 &adj_req_sw, &adj_req_em);
515 if (ret != EXYNOS_DP_SUCCESS) {
516 printk(BIOS_ERR, "DP read adj req failed\n");
517 edp_info->lt_info.lt_status = DP_LT_FAIL;
518 return ret;
519 }
520
521 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
522 (adj_req_em == PRE_EMPHASIS_LEVEL_3))
523 ret = exynos_dp_reduce_link_rate(edp_info);
524
525 if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
526 adj_req_sw) &&
527 (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
528 adj_req_em)) {
529 edp_info->lt_info.cr_loop[i]++;
530 if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
531 ret = exynos_dp_reduce_link_rate(
532 edp_info);
533 }
534
535 lt_ctl_val[i] = 0;
536 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
537
538 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
539 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
540 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
541 MAX_PRE_EMPHASIS_REACH_3;
542 }
543 exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
544 }
545
546 ret = exynos_dp_write_bytes_to_dpcd(
547 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
548 if (ret != EXYNOS_DP_SUCCESS) {
549 printk(BIOS_ERR, "DP write training pattern2 failed\n");
550 edp_info->lt_info.lt_status = DP_LT_FAIL;
551 return ret;
552 }
553 }
554
555 return ret;
556 }
557
exynos_dp_process_equalizer_training(struct edp_device_info * edp_info)558 static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
559 *edp_info)
560 {
561 unsigned int ret;
562 unsigned char lane_stat, adj_req_sw, adj_req_em, i;
563 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
564 unsigned char interlane_aligned = 0;
565 unsigned char f_bw;
566 unsigned char f_lane_cnt;
567 unsigned char sink_stat;
568
569 mdelay(1);
570
571 ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
572 if (ret != EXYNOS_DP_SUCCESS) {
573 printk(BIOS_ERR, "DP read lane status failed\n");
574 edp_info->lt_info.lt_status = DP_LT_FAIL;
575 return ret;
576 }
577
578 printk(BIOS_DEBUG,"DP lane stat : %x\n", lane_stat);
579
580 if (lane_stat & DP_LANE_STAT_CR_DONE) {
581 printk(BIOS_DEBUG, "DP_LANE_STAT_CR_DONE ok\n");
582 ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED,
583 &sink_stat);
584 if (ret != EXYNOS_DP_SUCCESS) {
585 edp_info->lt_info.lt_status = DP_LT_FAIL;
586 printk(BIOS_ERR, "DP read DPCD_LN_ALIGN_UPDATED failed\n");
587 return ret;
588 }
589
590 interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
591 printk(BIOS_DEBUG, "interlane_aligned: %d\n", interlane_aligned);
592 printk(BIOS_DEBUG, "Check %d lanes\n", edp_info->lane_cnt);
593
594 for (i = 0; i < edp_info->lane_cnt; i++) {
595 ret = exynos_dp_read_dpcd_adj_req(i,
596 &adj_req_sw, &adj_req_em);
597 if (ret != EXYNOS_DP_SUCCESS) {
598 printk(BIOS_ERR, "DP read adj req 1 failed\n");
599 edp_info->lt_info.lt_status = DP_LT_FAIL;
600
601 return ret;
602 }
603
604 lt_ctl_val[i] = 0;
605 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
606
607 if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
608 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
609 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
610 lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
611 }
612 }
613
614 if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
615 (lane_stat&DP_LANE_STAT_SYM_LOCK))
616 && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
617 printk(BIOS_DEBUG,"DP Equalizer training succeed\n");
618
619 f_bw = exynos_dp_get_link_bandwidth();
620 f_lane_cnt = exynos_dp_get_lane_count();
621
622 printk(BIOS_DEBUG,"DP final BandWidth : %x\n", f_bw);
623 printk(BIOS_DEBUG,"DP final Lane Count : %x\n", f_lane_cnt);
624
625 edp_info->lt_info.lt_status = DP_LT_FINISHED;
626
627 exynos_dp_equalizer_err_link(edp_info);
628
629 } else {
630 edp_info->lt_info.ep_loop++;
631
632 if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
633 if (edp_info->lane_bw == DP_LANE_BW_2_70) {
634 ret = exynos_dp_reduce_link_rate(
635 edp_info);
636 } else {
637 edp_info->lt_info.lt_status =
638 DP_LT_FAIL;
639 exynos_dp_equalizer_err_link(edp_info);
640 }
641 } else {
642 for (i = 0; i < edp_info->lane_cnt; i++)
643 exynos_dp_set_lanex_pre_emphasis(
644 lt_ctl_val[i], i);
645
646 ret = exynos_dp_write_bytes_to_dpcd(
647 DPCD_TRAINING_LANE0_SET,
648 4, lt_ctl_val);
649 if (ret != EXYNOS_DP_SUCCESS) {
650 printk(BIOS_ERR, "DP set lt pattern failed\n");
651 edp_info->lt_info.lt_status =
652 DP_LT_FAIL;
653 exynos_dp_equalizer_err_link(edp_info);
654 }
655 }
656 }
657 } else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
658 ret = exynos_dp_reduce_link_rate(edp_info);
659 } else {
660 edp_info->lt_info.lt_status = DP_LT_FAIL;
661 exynos_dp_equalizer_err_link(edp_info);
662 }
663
664 return ret;
665 }
666
exynos_dp_sw_link_training(struct edp_device_info * edp_info)667 static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
668 {
669 /* the C compiler is almost smart enough to know this gets set.
670 * But not quite.
671 */
672 unsigned int ret = 0;
673 int training_finished;
674
675 /* Turn off unnecessary lane */
676 if (edp_info->lane_cnt == 1)
677 exynos_dp_set_analog_power_down(CH1_BLOCK, 1);
678
679 training_finished = 0;
680
681 edp_info->lt_info.lt_status = DP_LT_START;
682
683 /* Process here */
684 while (!training_finished) {
685 switch (edp_info->lt_info.lt_status) {
686 case DP_LT_START:
687 ret = exynos_dp_link_start(edp_info);
688 if (ret != EXYNOS_DP_SUCCESS) {
689 printk(BIOS_ERR, "DP LT:link start failed\n");
690 training_finished = 1;
691 }
692 break;
693 case DP_LT_CR:
694 ret = exynos_dp_process_clock_recovery(edp_info);
695 if (ret != EXYNOS_DP_SUCCESS) {
696 printk(BIOS_ERR, "DP LT:clock recovery failed\n");
697 training_finished = 1;
698 }
699 break;
700 case DP_LT_ET:
701 ret = exynos_dp_process_equalizer_training(edp_info);
702 if (ret != EXYNOS_DP_SUCCESS) {
703 printk(BIOS_ERR, "DP LT:equalizer training failed\n");
704 training_finished = 1;
705 }
706 break;
707 case DP_LT_FINISHED:
708 training_finished = 1;
709 break;
710 case DP_LT_FAIL:
711 printk(BIOS_ERR,"DP: %s: DP_LT_FAIL: failed\n", __func__);
712 training_finished = 1;
713 ret = -1;
714 }
715 }
716
717 return ret;
718 }
719
exynos_dp_set_link_train(struct edp_device_info * edp_info)720 static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
721 {
722 unsigned int ret;
723
724 exynos_dp_init_training();
725
726 ret = exynos_dp_sw_link_training(edp_info);
727 if (ret != EXYNOS_DP_SUCCESS)
728 printk(BIOS_ERR, "DP dp_sw_link_traning() failed\n");
729
730 return ret;
731 }
732
exynos_dp_enable_scramble(unsigned int enable)733 static void exynos_dp_enable_scramble(unsigned int enable)
734 {
735 unsigned char data;
736
737 if (enable) {
738 exynos_dp_enable_scrambling(DP_ENABLE);
739
740 exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
741 &data);
742 exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
743 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
744 } else {
745 exynos_dp_enable_scrambling(DP_DISABLE);
746 exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
747 &data);
748 exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
749 (u8)(data | DPCD_SCRAMBLING_DISABLED));
750 }
751 }
752
exynos_dp_config_video(struct edp_device_info * edp_info)753 static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
754 {
755 unsigned int ret = 0;
756 unsigned int retry_cnt;
757
758 mdelay(1);
759
760 if (edp_info->video_info.master_mode) {
761 printk(BIOS_ERR,
762 "DP does not support master mode: bailing out\n");
763 return -1;
764 } else {
765 /* debug slave */
766 exynos_dp_config_video_slave_mode(&edp_info->video_info);
767 }
768
769 exynos_dp_set_video_color_format(&edp_info->video_info);
770
771 ret = exynos_dp_get_pll_lock_status();
772 if (ret != PLL_LOCKED) {
773 printk(BIOS_ERR, "DP PLL is not locked yet\n");
774 return -1;
775 }
776
777 if (edp_info->video_info.master_mode == 0) {
778 retry_cnt = 10;
779 while (retry_cnt) {
780 ret = exynos_dp_is_slave_video_stream_clock_on();
781 if (ret != EXYNOS_DP_SUCCESS) {
782 if (retry_cnt == 0) {
783 printk(BIOS_ERR, "DP stream_clock_on failed\n");
784 return ret;
785 }
786 retry_cnt--;
787 mdelay(1);
788 } else {
789 printk(BIOS_DEBUG, "DP stream_clock succeeds\n");
790 break;
791 }
792 }
793 }
794
795 /* Set to use the register calculated M/N video */
796 exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0);
797
798 /* For video bist, Video timing must be generated by register
799 * not clear if we still need this. We could take it out and it
800 * might appear to work, then fail strangely.
801 */
802 exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE);
803
804 /* we need to be sure this is off. */
805 exynos_dp_disable_video_bist();
806
807 /* Disable video mute */
808 exynos_dp_enable_video_mute(DP_DISABLE);
809
810 /* Configure video Master or Slave mode */
811 exynos_dp_enable_video_master(edp_info->video_info.master_mode);
812
813 /* Enable video */
814 exynos_dp_start_video();
815
816 if (edp_info->video_info.master_mode == 0) {
817 retry_cnt = 500;
818 while (retry_cnt) {
819 ret = exynos_dp_is_video_stream_on();
820 if (ret != EXYNOS_DP_SUCCESS) {
821 retry_cnt--;
822 if (retry_cnt == 0) {
823 printk(BIOS_ERR, "DP Timeout of video stream\n");
824 }
825 } else {
826 printk(BIOS_DEBUG, "DP video stream is on\n");
827 break;
828 }
829 /* this is a cheap operation, involving some register
830 * reads, and no AUX channel IO. A ms. delay is fine.
831 */
832 mdelay(1);
833 }
834 }
835
836 return ret;
837 }
838
exynos_init_dp(struct edp_device_info * edp_info)839 int exynos_init_dp(struct edp_device_info *edp_info)
840 {
841 unsigned int ret;
842
843 dp_phy_control(1);
844
845 ret = exynos_dp_init_dp();
846 if (ret != EXYNOS_DP_SUCCESS) {
847 printk(BIOS_ERR, "DP exynos_dp_init_dp() failed\n");
848 return ret;
849 }
850
851 ret = exynos_dp_handle_edid(edp_info);
852 if (ret != EXYNOS_DP_SUCCESS) {
853 printk(BIOS_ERR, "EDP handle_edid fail\n");
854 return ret;
855 }
856
857 ret = exynos_dp_set_link_train(edp_info);
858 if (ret != EXYNOS_DP_SUCCESS) {
859 printk(BIOS_ERR, "DP link training fail\n");
860 return ret;
861 }
862 printk(BIOS_DEBUG, "EDP link training ok\n");
863
864 exynos_dp_enable_scramble(DP_ENABLE);
865 exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE);
866 exynos_dp_enable_enhanced_mode(DP_ENABLE);
867
868 exynos_dp_set_link_bandwidth(edp_info->lane_bw);
869 exynos_dp_set_lane_count(edp_info->lane_cnt);
870
871 exynos_dp_init_video();
872 ret = exynos_dp_config_video(edp_info);
873
874 if (ret != EXYNOS_DP_SUCCESS) {
875 printk(BIOS_ERR, "Exynos DP init failed\n");
876 return ret;
877 }
878 printk(BIOS_DEBUG, "Exynos DP init done\n");
879
880 return ret;
881 }
882