1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #define __SIMPLE_DEVICE__
4
5 #include <acpi/acpi.h>
6 #include <acpi/acpigen.h>
7 #include <arch/romstage.h>
8 #include <device/mmio.h>
9 #include <assert.h>
10 #include <device/pci.h>
11 #include <device/pci_ids.h>
12 #include <device/pci_ops.h>
13 #include <console/console.h>
14 #include <commonlib/helpers.h>
15 #include <cpu/x86/mtrr.h>
16 #include <fast_spi_def.h>
17 #include <intelblocks/fast_spi.h>
18 #include <intelblocks/gpmr.h>
19 #include <lib.h>
20 #include <soc/pci_devs.h>
21 #include <spi_flash.h>
22 #include <spi-generic.h>
23
24 #define FLASH_MMIO_SIZE (16 * MiB)
25 #define FLASH_BASE_ADDR ((0xffffffff - FLASH_MMIO_SIZE) + 1)
26
27 /*
28 * Get the FAST_SPIBAR.
29 */
fast_spi_get_bar(void)30 void *fast_spi_get_bar(void)
31 {
32 const pci_devfn_t dev = PCH_DEV_SPI;
33 uintptr_t bar;
34
35 bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
36 assert(bar != 0);
37 /*
38 * Bits 31-12 are the base address as per EDS for SPI,
39 * Don't care about 0-11 bit
40 */
41 return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
42 }
43
44 /*
45 * Disable the BIOS write protect and Enable Prefetching and Caching.
46 */
fast_spi_init(void)47 void fast_spi_init(void)
48 {
49 const pci_devfn_t dev = PCH_DEV_SPI;
50 uint8_t bios_cntl;
51
52 bios_cntl = pci_read_config8(dev, SPI_BIOS_CONTROL);
53
54 /* Disable the BIOS write protect so write commands are allowed. */
55 bios_cntl &= ~SPI_BIOS_CONTROL_EISS;
56 bios_cntl |= SPI_BIOS_CONTROL_WPD;
57 /* Enable Prefetching and caching. */
58 bios_cntl |= SPI_BIOS_CONTROL_PREFETCH_ENABLE;
59 bios_cntl &= ~SPI_BIOS_CONTROL_CACHE_DISABLE;
60
61 pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl);
62 }
63
64 /*
65 * Set FAST_SPIBAR BIOS Control register based on input bit field.
66 */
fast_spi_set_bios_control_reg(uint32_t bios_cntl_bit)67 static void fast_spi_set_bios_control_reg(uint32_t bios_cntl_bit)
68 {
69 const pci_devfn_t dev = PCH_DEV_SPI;
70 uint32_t bc_cntl;
71
72 assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0);
73 bc_cntl = pci_read_config32(dev, SPI_BIOS_CONTROL);
74 bc_cntl |= bios_cntl_bit;
75 pci_write_config32(dev, SPI_BIOS_CONTROL, bc_cntl);
76 }
77
78 /*
79 * Ensure an additional read back after performing lock down
80 */
fast_spi_read_post_write(uint8_t reg)81 static void fast_spi_read_post_write(uint8_t reg)
82 {
83 pci_read_config8(PCH_DEV_SPI, reg);
84 }
85
86 /*
87 * Set FAST_SPIBAR BIOS Control BILD bit.
88 */
fast_spi_set_bios_interface_lock_down(void)89 void fast_spi_set_bios_interface_lock_down(void)
90 {
91 fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_BILD);
92
93 fast_spi_read_post_write(SPI_BIOS_CONTROL);
94 }
95
96 /*
97 * Set FAST_SPIBAR BIOS Control LE bit.
98 */
fast_spi_set_lock_enable(void)99 void fast_spi_set_lock_enable(void)
100 {
101 fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_LOCK_ENABLE);
102
103 fast_spi_read_post_write(SPI_BIOS_CONTROL);
104 }
105
106 /*
107 * Set FAST_SPIBAR BIOS Control EXT BIOS LE bit.
108 */
fast_spi_set_ext_bios_lock_enable(void)109 void fast_spi_set_ext_bios_lock_enable(void)
110 {
111 if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW))
112 return;
113
114 fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE);
115
116 fast_spi_read_post_write(SPI_BIOS_CONTROL);
117 }
118
119 /*
120 * Set FAST_SPIBAR BIOS Control EISS bit.
121 */
fast_spi_set_eiss(void)122 void fast_spi_set_eiss(void)
123 {
124 fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_EISS);
125
126 fast_spi_read_post_write(SPI_BIOS_CONTROL);
127 }
128
129 /*
130 * Set FAST_SPI opcode menu.
131 */
fast_spi_set_opcode_menu(void)132 void fast_spi_set_opcode_menu(void)
133 {
134 void *spibar = fast_spi_get_bar();
135
136 write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX);
137 write16(spibar + SPIBAR_OPTYPE, SPI_OPTYPE);
138 write32(spibar + SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER);
139 write32(spibar + SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER);
140 }
141
142 /*
143 * Lock FAST_SPIBAR.
144 * Use 16bit write to avoid touching two upper bytes what may cause the write
145 * cycle to fail in case a prior transaction has not completed.
146 * While WRSDIS is lockable with FLOCKDN, writing both in the same
147 * cycle is guaranteed to work by design.
148 *
149 * Avoid read->modify->write not to clear RW1C bits unintentionally.
150 */
fast_spi_lock_bar(void)151 void fast_spi_lock_bar(void)
152 {
153 void *spibar = fast_spi_get_bar();
154 uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN | SPIBAR_HSFSTS_PRR34_LOCKDN;
155
156 if (CONFIG(FAST_SPI_DISABLE_WRITE_STATUS))
157 hsfs |= SPIBAR_HSFSTS_WRSDIS;
158
159 write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);
160 }
161
162 /*
163 * Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the
164 * FAST_SPI Protected Range (PR) registers.
165 */
fast_spi_pr_dlock(void)166 void fast_spi_pr_dlock(void)
167 {
168 void *spibar = fast_spi_get_bar();
169 uint32_t dlock;
170
171 dlock = read32(spibar + SPIBAR_DLOCK);
172 dlock |= (SPIBAR_DLOCK_PR0LOCKDN | SPIBAR_DLOCK_PR1LOCKDN
173 | SPIBAR_DLOCK_PR2LOCKDN | SPIBAR_DLOCK_PR3LOCKDN
174 | SPIBAR_DLOCK_PR4LOCKDN);
175
176 write32(spibar + SPIBAR_DLOCK, dlock);
177 }
178
179 /*
180 * Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30).
181 */
fast_spi_vscc0_lock(void)182 void fast_spi_vscc0_lock(void)
183 {
184 void *spibar = fast_spi_get_bar();
185
186 /*
187 * SPI Flash Programming Guide Section 5.5.2 describes Vendor Component Lock (VCL).
188 * It is recommended to set the VCL bit. VCL applies to both VSCC0 and VSCC1.
189 * Without this bit being set, it is possible to modify Host/GbE VSCC register(s),
190 * which might results in undesired host and integrated GbE Serial Flash
191 * functionality.
192 */
193 setbits32(spibar + SPIBAR_SFDP0_VSCC0, SPIBAR_VSCC0_VCL);
194 }
195
196 /*
197 * Set FAST_SPIBAR Soft Reset Data Register value.
198 */
fast_spi_set_strap_msg_data(uint32_t soft_reset_data)199 void fast_spi_set_strap_msg_data(uint32_t soft_reset_data)
200 {
201 void *spibar = fast_spi_get_bar();
202 uint32_t ssl, ssms;
203
204 /* Set Strap Lock Disable */
205 ssl = read32(spibar + SPIBAR_RESET_LOCK);
206 ssl &= ~SPIBAR_RESET_LOCK_ENABLE;
207 write32(spibar + SPIBAR_RESET_LOCK, ssl);
208
209 /* Write Soft Reset Data register at SPIBAR0 offset 0xF8[0:15] */
210 write32(spibar + SPIBAR_RESET_DATA, soft_reset_data);
211
212 /* Set Strap Mux Select set to '1' */
213 ssms = read32(spibar + SPIBAR_RESET_CTRL);
214 ssms |= SPIBAR_RESET_CTRL_SSMC;
215 write32(spibar + SPIBAR_RESET_CTRL, ssms);
216
217 /* Set Strap Lock Enable */
218 ssl = read32(spibar + SPIBAR_RESET_LOCK);
219 ssl |= SPIBAR_RESET_LOCK_ENABLE;
220 write32(spibar + SPIBAR_RESET_LOCK, ssl);
221 }
222
fast_spi_enable_cache_range(unsigned int base,unsigned int size)223 static void fast_spi_enable_cache_range(unsigned int base, unsigned int size)
224 {
225 if (ENV_RAMSTAGE) {
226 mtrr_use_temp_range(base, size, MTRR_TYPE_WRPROT);
227 return;
228 }
229
230 const int type = MTRR_TYPE_WRPROT;
231 int mtrr = get_free_var_mtrr();
232 if (mtrr == -1) {
233 printk(BIOS_WARNING, "ROM caching failed due to no free MTRR available!\n");
234 return;
235 }
236
237 set_var_mtrr(mtrr, base, size, type);
238 }
239
240 /*
241 * Returns bios_start and fills in size of the BIOS region.
242 */
fast_spi_get_bios_region(size_t * bios_size)243 size_t fast_spi_get_bios_region(size_t *bios_size)
244 {
245 size_t bios_start, bios_end;
246 /*
247 * BIOS_BFPREG provides info about BIOS Flash Primary Region
248 * Base and Limit.
249 * Base and Limit fields are in units of 4KiB.
250 */
251 uint32_t val = read32(fast_spi_get_bar() + SPIBAR_BFPREG);
252
253 bios_start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB;
254 bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
255 SPIBAR_BFPREG_PRL_SHIFT) + 1) * 4 * KiB;
256 *bios_size = bios_end - bios_start;
257 return bios_start;
258 }
259
fast_spi_ext_bios_cache_range(uintptr_t * base,size_t * size)260 static bool fast_spi_ext_bios_cache_range(uintptr_t *base, size_t *size)
261 {
262 uint32_t alignment;
263 if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW))
264 return false;
265
266 fast_spi_get_ext_bios_window(base, size);
267
268 /* Enable extended bios only if Size of Bios region is greater than 16MiB */
269 if (*size == 0 || *base == 0)
270 return false;
271
272 /* Round to power of two */
273 alignment = 1UL << (log2_ceil(*size));
274 *size = ALIGN_UP(*size, alignment);
275 *base = ALIGN_DOWN(*base, *size);
276
277 return true;
278 }
279
fast_spi_cache_ext_bios_window(void)280 static void fast_spi_cache_ext_bios_window(void)
281 {
282 size_t ext_bios_size;
283 uintptr_t ext_bios_base;
284
285 if (!fast_spi_ext_bios_cache_range(&ext_bios_base, &ext_bios_size))
286 return;
287
288 fast_spi_enable_cache_range(ext_bios_base, ext_bios_size);
289 }
290
fast_spi_cache_ext_bios_postcar(struct postcar_frame * pcf)291 void fast_spi_cache_ext_bios_postcar(struct postcar_frame *pcf)
292 {
293 size_t ext_bios_size;
294 uintptr_t ext_bios_base;
295 const int type = MTRR_TYPE_WRPROT;
296
297 if (!fast_spi_ext_bios_cache_range(&ext_bios_base, &ext_bios_size))
298 return;
299
300 postcar_frame_add_mtrr(pcf, ext_bios_base, ext_bios_size, type);
301 }
302
fast_spi_cache_bios_region(void)303 void fast_spi_cache_bios_region(void)
304 {
305 size_t bios_size;
306 uint32_t alignment;
307 uintptr_t base;
308
309 /* Only the IFD BIOS region is memory mapped (at top of 4G) */
310 fast_spi_get_bios_region(&bios_size);
311
312 /* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will
313 * cause memory type conflict when setting memory type to write
314 * protection, so limit the cached BIOS region to be no more than 16MB.
315 * */
316 bios_size = MIN(bios_size, 16 * MiB);
317 if (bios_size <= 0)
318 return;
319
320 /* Round to power of two */
321 alignment = 1UL << (log2_ceil(bios_size));
322 bios_size = ALIGN_UP(bios_size, alignment);
323 base = 4ULL*GiB - bios_size;
324
325 fast_spi_enable_cache_range(base, bios_size);
326
327 /* Check if caching is needed for extended bios region if supported */
328 fast_spi_cache_ext_bios_window();
329 }
330
331 /*
332 * Enable extended BIOS support
333 * Checks BIOS region in the flashmap, if its more than 16Mib, enables extended BIOS
334 * region support.
335 */
fast_spi_enable_ext_bios(void)336 static void fast_spi_enable_ext_bios(void)
337 {
338 const pci_devfn_t dev = PCH_DEV_SPI;
339 if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW))
340 return;
341
342 #if CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)
343 /*
344 * Ensure that the base for the extended window in host space is a multiple of 32 MiB
345 * and size is fixed at 32 MiB. Controller assumes that the extended window has a fixed
346 * size of 32 MiB even if the actual BIOS region is smaller. The mapping of the BIOS
347 * region happens at the top of the extended window in this case.
348 */
349 _Static_assert(ALIGN_UP(CONFIG_EXT_BIOS_WIN_BASE, 32 * MiB) == CONFIG_EXT_BIOS_WIN_BASE,
350 "Extended BIOS window base must be a multiple of 32 * MiB!");
351 _Static_assert(CONFIG_EXT_BIOS_WIN_SIZE == (32 * MiB),
352 "Only 32MiB windows are supported for extended BIOS!");
353 #endif
354
355 /* Configure Source decode for Extended BIOS Region */
356 if (enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE,
357 soc_get_spi_psf_destination_id()) == CB_ERR)
358 return;
359
360 /* Program EXT_BIOS_BAR1 with obtained ext_bios_base */
361 pci_write_config32(dev, SPI_CFG_BAR1,
362 CONFIG_EXT_BIOS_WIN_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY);
363
364 /*
365 * Since the top 16MiB of the BIOS region is always decoded by the standard window
366 * below the 4G boundary, we need to map the rest of the BIOS region that lies
367 * below the top 16MiB in the extended window. Thus, EXT_BIOS_LIMIT will be set to
368 * 16MiB. This determines the maximum address in the SPI flash space that is mapped
369 * to the top of the extended window in the host address space. EXT_BIOS_LIMIT is
370 * basically the offset from the end of the BIOS region that will be mapped to the top
371 * of the extended window.
372 * This enables the decoding as follows:
373 -Standard decode window: (bios_region_top - 16MiB) to bios_region_top
374 -Extended decode window:
375 (bios_region_top - 16MiB - MIN(extended_window_size, bios_size - 16MiB))
376 to (bios_region_top - 16MiB).
377 */
378 pci_or_config32(dev, SPI_BIOS_CONTROL, SPI_BIOS_CONTROL_EXT_BIOS_LIMIT(16 * MiB));
379
380 /* Program EXT_BIOS EN */
381 pci_or_config32(dev, SPI_BIOS_CONTROL, SPI_BIOS_CONTROL_EXT_BIOS_ENABLE);
382 }
383
384 /*
385 * Program temporary BAR for SPI in case any of the stages before ramstage need
386 * to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI
387 * enumeration.
388 */
fast_spi_early_init(uintptr_t spi_base_address)389 void fast_spi_early_init(uintptr_t spi_base_address)
390 {
391 const pci_devfn_t dev = PCH_DEV_SPI;
392 uint16_t pcireg;
393
394 /* Assign Resources to SPI Controller */
395 /* Clear BIT 1-2 SPI Command Register */
396 pcireg = pci_read_config16(dev, PCI_COMMAND);
397 pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
398 pci_write_config16(dev, PCI_COMMAND, pcireg);
399
400 /* Program Temporary BAR for SPI */
401 pci_write_config32(dev, PCI_BASE_ADDRESS_0,
402 spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY);
403
404 /*
405 * Enable extended bios support. Since it configures memory BAR, this is done before
406 * enabling MMIO space.
407 */
408 fast_spi_enable_ext_bios();
409
410 /* Enable Bus Master and MMIO Space */
411 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
412
413 /* Initialize SPI to allow BIOS to write/erase on flash. */
414 fast_spi_init();
415 }
416
417 /* Clear SPI Synchronous SMI status bit and return its value. */
fast_spi_clear_sync_smi_status(void)418 bool fast_spi_clear_sync_smi_status(void)
419 {
420 const uint32_t bios_cntl = pci_read_config32(PCH_DEV_SPI, SPI_BIOS_CONTROL);
421 const bool smi_asserted = bios_cntl & SPI_BIOS_CONTROL_SYNC_SS;
422 /*
423 * Do not unconditionally write 1 to clear SYNC_SS. Hardware could set
424 * SYNC_SS here (after we read but before we write SPI_BIOS_CONTROL),
425 * and the event would be lost when unconditionally clearing SYNC_SS.
426 */
427 pci_write_config32(PCH_DEV_SPI, SPI_BIOS_CONTROL, bios_cntl);
428 return smi_asserted;
429 }
430
431 /* Read SPI Write Protect disable status. */
fast_spi_wpd_status(void)432 bool fast_spi_wpd_status(void)
433 {
434 return pci_read_config16(PCH_DEV_SPI, SPI_BIOS_CONTROL) &
435 SPI_BIOS_CONTROL_WPD;
436 }
437
438 /* Enable SPI Write Protect. */
fast_spi_enable_wp(void)439 void fast_spi_enable_wp(void)
440 {
441 const pci_devfn_t dev = PCH_DEV_SPI;
442 uint8_t bios_cntl;
443
444 bios_cntl = pci_read_config8(dev, SPI_BIOS_CONTROL);
445 bios_cntl &= ~SPI_BIOS_CONTROL_WPD;
446 pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl);
447 }
448
449 /* Disable SPI Write Protect. */
fast_spi_disable_wp(void)450 void fast_spi_disable_wp(void)
451 {
452 const pci_devfn_t dev = PCH_DEV_SPI;
453 uint8_t bios_cntl;
454
455 bios_cntl = pci_read_config8(dev, SPI_BIOS_CONTROL);
456 bios_cntl |= SPI_BIOS_CONTROL_WPD;
457 pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl);
458 }
459
fast_spi_set_bde(void)460 void fast_spi_set_bde(void)
461 {
462 const pci_devfn_t dev = PCH_DEV_SPI;
463
464 pci_or_config32(dev, SPI_BIOS_DECODE_EN, SPI_BIOS_DECODE_LOCK);
465 }
466
467 /* Set FAST_SPIBAR + SPIBAR_SFDP0_VSCC0 (0xc4) Vendor Control Lock */
fast_spi_set_vcl(void)468 void fast_spi_set_vcl(void)
469 {
470 void *spibar = fast_spi_get_bar();
471 uint32_t vcss;
472
473 vcss = read32(spibar + SPIBAR_SFDP0_VSCC0);
474 vcss |= SPIBAR_SFDP0_VSCC0_VCL;
475 write32(spibar + SPIBAR_SFDP0_VSCC0, vcss);
476 }
477
fast_spi_clear_outstanding_status(void)478 void fast_spi_clear_outstanding_status(void)
479 {
480 void *spibar = fast_spi_get_bar();
481
482 /* Make sure all W1C status bits get cleared. */
483 write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS);
484 }
485
486
487 /* As there is no official ACPI ID for this controller use the generic PNP ID for now. */
fast_spi_acpi_hid(const struct device * dev)488 static const char *fast_spi_acpi_hid(const struct device *dev)
489 {
490 return "PNP0C02";
491 }
492
fast_spi_acpi_name(const struct device * dev)493 static const char *fast_spi_acpi_name(const struct device *dev)
494 {
495 return "FSPI";
496 }
497
498 /*
499 * Generate an ACPI entry for the SPI controller. This way the allocated resources
500 * for the SPI controller can be communicated to the OS even if the device is
501 * not visible on PCI (because it is hidden) and therefore can not be probed by the OS.
502 */
fast_spi_fill_ssdt(const struct device * dev)503 static void fast_spi_fill_ssdt(const struct device *dev)
504 {
505 /* Do not add SSDT if the fast SPI device is hidden. */
506 if (!CONFIG(FAST_SPI_GENERATE_SSDT) || dev->hidden)
507 return;
508
509 const char *scope = acpi_device_scope(dev);
510 const char *hid = fast_spi_acpi_hid(dev);
511
512 if (!scope || !hid)
513 return;
514
515 struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
516 if (!res)
517 return;
518
519 /* Scope */
520 acpigen_write_scope(scope);
521
522 /* Device */
523 acpigen_write_device(acpi_device_name(dev));
524 acpigen_write_name_string("_HID", hid);
525 acpi_device_write_uid(dev);
526 acpigen_write_name_string("_DDN", "ACPI Fast SPI");
527 acpigen_write_STA(acpi_device_status(dev));
528
529 /* Resources */
530 acpigen_write_name("_CRS");
531 acpigen_write_resourcetemplate_header();
532
533 /* Add BAR0 resource. */
534 acpigen_write_mem32fixed(1, res->base, res->size);
535
536 acpigen_write_resourcetemplate_footer();
537
538 acpigen_pop_len(); /* Device */
539 acpigen_pop_len(); /* Scope */
540 }
541
fast_spi_read_resources(struct device * dev)542 static void fast_spi_read_resources(struct device *dev)
543 {
544 /* Read standard PCI resources. */
545 pci_dev_read_resources(dev);
546
547 /* Add SPI flash MMIO window as a reserved resource. */
548 mmio_range(dev, 0, FLASH_BASE_ADDR, FLASH_MMIO_SIZE);
549 /* Add extended SPI flash MMIO window as reserved resource if enabled. */
550 if (CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)) {
551 mmio_range(dev, 1, CONFIG_EXT_BIOS_WIN_BASE,
552 CONFIG_EXT_BIOS_WIN_SIZE);
553 }
554 }
555
556 static struct device_operations fast_spi_dev_ops = {
557 .read_resources = fast_spi_read_resources,
558 .set_resources = pci_dev_set_resources,
559 .enable_resources = pci_dev_enable_resources,
560 .acpi_fill_ssdt = fast_spi_fill_ssdt,
561 .acpi_name = fast_spi_acpi_name,
562 .ops_pci = &pci_dev_ops_pci,
563 };
564
565 static const unsigned short pci_device_ids[] = {
566 PCI_DID_INTEL_LNL_HWSEQ_SPI,
567 PCI_DID_INTEL_ADP_M_N_HWSEQ_SPI,
568 PCI_DID_INTEL_ADP_P_HWSEQ_SPI,
569 PCI_DID_INTEL_ADP_S_HWSEQ_SPI,
570 PCI_DID_INTEL_APL_HWSEQ_SPI,
571 PCI_DID_INTEL_GLK_HWSEQ_SPI,
572 PCI_DID_INTEL_CMP_HWSEQ_SPI,
573 PCI_DID_INTEL_CMP_H_HWSEQ_SPI,
574 PCI_DID_INTEL_CNL_HWSEQ_SPI,
575 PCI_DID_INTEL_CNP_H_HWSEQ_SPI,
576 PCI_DID_INTEL_ICP_HWSEQ_SPI,
577 PCI_DID_INTEL_JSP_HWSEQ_SPI,
578 PCI_DID_INTEL_LWB_SPI,
579 PCI_DID_INTEL_LWB_SPI_SUPER,
580 PCI_DID_INTEL_MCC_SPI0,
581 PCI_DID_INTEL_MTL_HWSEQ_SPI,
582 PCI_DID_INTEL_RPP_S_HWSEQ_SPI,
583 PCI_DID_INTEL_SPR_HWSEQ_SPI,
584 PCI_DID_INTEL_TGP_SPI0,
585 0
586 };
587
588 static const struct pci_driver fast_spi __pci_driver = {
589 .ops = &fast_spi_dev_ops,
590 .vendor = PCI_VID_INTEL,
591 .devices = pci_device_ids,
592 };
593