1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/mmio.h>
4 #include <boot/tables.h>
5 #include <console/console.h>
6 #include <delay.h>
7 #include <device/device.h>
8 #include <soc/addressmap.h>
9 #include <soc/clock.h>
10 #include <soc/display.h>
11 #include <soc/sdram.h>
12 #include <soc/nvidia/tegra/dc.h>
13 #include <soc/nvidia/tegra/pwm.h>
14 #include <stdint.h>
15 #include <string.h>
16 #include <framebuffer_info.h>
17
18 #include "chip.h"
19
20 struct tegra_dc dc_data;
21
22 int dump = 0;
READL(void * p)23 unsigned long READL(void *p)
24 {
25 unsigned long value;
26
27 /*
28 * In case of hard hung on readl(p), we can set dump > 1 to print out
29 * the address accessed.
30 */
31 if (dump > 1)
32 printk(BIOS_SPEW, "readl %p\n", p);
33
34 value = read32(p);
35 if (dump)
36 printk(BIOS_SPEW, "readl %p %08lx\n", p, value);
37 return value;
38 }
39
WRITEL(unsigned long value,void * p)40 void WRITEL(unsigned long value, void *p)
41 {
42 if (dump)
43 printk(BIOS_SPEW, "writel %p %08lx\n", p, value);
44 write32(p, value);
45 }
46
47 /* return in 1000ths of a Hertz */
tegra_dc_calc_refresh(const struct soc_nvidia_tegra124_config * config)48 static int tegra_dc_calc_refresh(const struct soc_nvidia_tegra124_config *config)
49 {
50 int h_total, v_total, refresh;
51 int pclk = config->pixel_clock;
52
53 h_total = config->xres + config->hfront_porch + config->hback_porch +
54 config->hsync_width;
55 v_total = config->yres + config->vfront_porch + config->vback_porch +
56 config->vsync_width;
57 if (!pclk || !h_total || !v_total)
58 return 0;
59 refresh = pclk / h_total;
60 refresh *= 1000;
61 refresh /= v_total;
62 return refresh;
63 }
64
print_mode(const struct soc_nvidia_tegra124_config * config)65 static void print_mode(const struct soc_nvidia_tegra124_config *config)
66 {
67 if (config) {
68 int refresh = tegra_dc_calc_refresh(config);
69 printk(BIOS_ERR,
70 "MODE:%dx%d@%d.%03uHz pclk=%d\n",
71 config->xres, config->yres,
72 refresh / 1000, refresh % 1000,
73 config->pixel_clock);
74 }
75 }
76
update_display_mode(struct display_controller * disp_ctrl,struct soc_nvidia_tegra124_config * config)77 static int update_display_mode(struct display_controller *disp_ctrl,
78 struct soc_nvidia_tegra124_config *config)
79 {
80 print_mode(config);
81
82 WRITEL(0x1, &disp_ctrl->disp.disp_timing_opt);
83
84 WRITEL(config->vref_to_sync << 16 | config->href_to_sync,
85 &disp_ctrl->disp.ref_to_sync);
86
87 WRITEL(config->vsync_width << 16 | config->hsync_width,
88 &disp_ctrl->disp.sync_width);
89
90 WRITEL(((config->vback_porch - config->vref_to_sync) << 16) | config->hback_porch,
91 &disp_ctrl->disp.back_porch);
92
93 WRITEL(((config->vfront_porch + config->vref_to_sync) << 16) | config->hfront_porch,
94 &disp_ctrl->disp.front_porch);
95
96 WRITEL(config->xres | (config->yres << 16),
97 &disp_ctrl->disp.disp_active);
98
99 /**
100 * We want to use PLLD_out0, which is PLLD / 2:
101 * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv.
102 *
103 * Currently most panels work inside clock range 50MHz~100MHz, and PLLD
104 * has some requirements to have VCO in range 500MHz~1000MHz (see
105 * clock.c for more detail). To simplify calculation, we set
106 * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
107 * may be calculated by clock_display, to allow wider frequency range.
108 *
109 * Note ShiftClockDiv is a 7.1 format value.
110 */
111 const u32 shift_clock_div = 1;
112 WRITEL((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
113 ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT,
114 &disp_ctrl->disp.disp_clk_ctrl);
115 printk(BIOS_DEBUG, "%s: PixelClock=%u, ShiftClockDiv=%u\n",
116 __func__, config->pixel_clock, shift_clock_div);
117 return 0;
118 }
119
update_window(struct display_controller * disp_ctrl,struct soc_nvidia_tegra124_config * config)120 static void update_window(struct display_controller *disp_ctrl,
121 struct soc_nvidia_tegra124_config *config)
122 {
123 u32 val;
124
125 WRITEL(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
126
127 WRITEL(((config->yres << 16) | config->xres), &disp_ctrl->win.size);
128 WRITEL(((config->yres << 16) |
129 (config->xres * config->framebuffer_bits_per_pixel / 8)),
130 &disp_ctrl->win.prescaled_size);
131 WRITEL(((config->xres * config->framebuffer_bits_per_pixel / 8 + 31) /
132 32 * 32), &disp_ctrl->win.line_stride);
133
134 WRITEL(config->color_depth, &disp_ctrl->win.color_depth);
135
136 WRITEL(config->framebuffer_base, &disp_ctrl->winbuf.start_addr);
137 WRITEL((V_DDA_INC(0x1000) | H_DDA_INC(0x1000)), &disp_ctrl->win.dda_increment);
138
139 WRITEL(COLOR_WHITE, &disp_ctrl->disp.blend_background_color);
140 WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
141
142 WRITEL(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
143
144 val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
145 val |= GENERAL_UPDATE | WIN_A_UPDATE;
146 WRITEL(val, &disp_ctrl->cmd.state_ctrl);
147
148 // Enable win_a
149 val = READL(&disp_ctrl->win.win_opt);
150 WRITEL(val | WIN_ENABLE, &disp_ctrl->win.win_opt);
151 }
152
tegra_dc_init(struct display_controller * disp_ctrl)153 static int tegra_dc_init(struct display_controller *disp_ctrl)
154 {
155 /* do not accept interrupts during initialization */
156 WRITEL(0x00000000, &disp_ctrl->cmd.int_mask);
157 WRITEL(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
158 &disp_ctrl->cmd.state_access);
159 WRITEL(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
160 WRITEL(0x00000000, &disp_ctrl->win.win_opt);
161 WRITEL(0x00000000, &disp_ctrl->win.byte_swap);
162 WRITEL(0x00000000, &disp_ctrl->win.buffer_ctrl);
163
164 WRITEL(0x00000000, &disp_ctrl->win.pos);
165 WRITEL(0x00000000, &disp_ctrl->win.h_initial_dda);
166 WRITEL(0x00000000, &disp_ctrl->win.v_initial_dda);
167 WRITEL(0x00000000, &disp_ctrl->win.dda_increment);
168 WRITEL(0x00000000, &disp_ctrl->win.dv_ctrl);
169
170 WRITEL(0x01000000, &disp_ctrl->win.blend_layer_ctrl);
171 WRITEL(0x00000000, &disp_ctrl->win.blend_match_select);
172 WRITEL(0x00000000, &disp_ctrl->win.blend_nomatch_select);
173 WRITEL(0x00000000, &disp_ctrl->win.blend_alpha_1bit);
174
175 WRITEL(0x00000000, &disp_ctrl->winbuf.start_addr_hi);
176 WRITEL(0x00000000, &disp_ctrl->winbuf.addr_h_offset);
177 WRITEL(0x00000000, &disp_ctrl->winbuf.addr_v_offset);
178
179 WRITEL(0x00000000, &disp_ctrl->com.crc_checksum);
180 WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[0]);
181 WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[1]);
182 WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[2]);
183 WRITEL(0x00000000, &disp_ctrl->com.pin_output_enb[3]);
184 WRITEL(0x00000000, &disp_ctrl->disp.disp_signal_opt0);
185
186 return 0;
187 }
188
fb_base_mb(void)189 uint32_t fb_base_mb(void)
190 {
191 return sdram_max_addressable_mb() - FB_SIZE_MB;
192 }
193
194 /* this is really aimed at the lcd panel. That said, there are two display
195 * devices on this part and we may someday want to extend it for other boards.
196 */
display_startup(struct device * dev)197 void display_startup(struct device *dev)
198 {
199 struct soc_nvidia_tegra124_config *config = dev->chip_info;
200 struct display_controller *disp_ctrl = (void *)config->display_controller;
201 struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE;
202 struct tegra_dc *dc = &dc_data;
203 u32 plld_rate;
204
205 /* init dc */
206 dc->base = (void *)TEGRA_ARM_DISPLAYA;
207 dc->config = config;
208 config->dc_data = dc;
209
210 /* Note dp_init may read EDID and change some config values. */
211 dp_init(config);
212
213 /* should probably just make it all MiB ... in future */
214 u32 framebuffer_size_mb = config->framebuffer_size / MiB;
215 u32 framebuffer_base_mb= config->framebuffer_base / MiB;
216
217 /* light it all up */
218 /* This one may have been done in romstage but that's ok for now. */
219 if (config->panel_vdd_gpio){
220 gpio_output(config->panel_vdd_gpio, 1);
221 printk(BIOS_SPEW,"%s: panel_vdd setting gpio %08x to %d\n",
222 __func__, config->panel_vdd_gpio, 1);
223 }
224 udelay(config->vdd_delay_ms * 1000);
225 if (config->backlight_vdd_gpio){
226 gpio_output(config->backlight_vdd_gpio, 1);
227 printk(BIOS_SPEW,"%s: backlight vdd setting gpio %08x to %d\n",
228 __func__, config->backlight_vdd_gpio, 1);
229 }
230 if (config->lvds_shutdown_gpio){
231 gpio_output(config->lvds_shutdown_gpio, 0);
232 printk(BIOS_SPEW,"%s: lvds shutdown setting gpio %08x to %d\n",
233 __func__, config->lvds_shutdown_gpio, 0);
234 }
235
236 if (framebuffer_size_mb == 0){
237 framebuffer_size_mb = ALIGN_UP(config->xres * config->yres *
238 (config->framebuffer_bits_per_pixel / 8), MiB)/MiB;
239 }
240
241 if (! framebuffer_base_mb)
242 framebuffer_base_mb = fb_base_mb();
243
244 config->framebuffer_size = framebuffer_size_mb * MiB;
245 config->framebuffer_base = framebuffer_base_mb * MiB;
246
247 mmu_config_range(framebuffer_base_mb, framebuffer_size_mb,
248 DCACHE_WRITETHROUGH);
249
250 printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb,
251 framebuffer_base_mb + framebuffer_size_mb);
252
253 /* GPIO magic here if needed to start powering up things. You
254 * really only want to enable vdd, wait a bit, and then enable
255 * the panel. However ... the timings in the tegra20 dts make
256 * no sense to me. I'm pretty sure they're wrong.
257 * The panel_vdd is done in the romstage, so we need only
258 * light things up here once we're sure it's all working.
259 */
260
261 /* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
262 * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
263 * update_display_mode() for detail.
264 */
265 plld_rate = clock_display(config->pixel_clock * 2);
266 if (plld_rate == 0) {
267 printk(BIOS_ERR, "dc: clock init failed\n");
268 return;
269 } else if (plld_rate != config->pixel_clock * 2) {
270 printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate);
271 config->pixel_clock = plld_rate / 2;
272 }
273
274 /* Init dc */
275 if (tegra_dc_init(disp_ctrl)) {
276 printk(BIOS_ERR, "dc: init failed\n");
277 return;
278 }
279
280 /* Configure dc mode */
281 if (update_display_mode(disp_ctrl, config)) {
282 printk(BIOS_ERR, "dc: failed to configure display mode.\n");
283 return;
284 }
285
286 /* Enable dp */
287 dp_enable(dc->out);
288
289 /* Init frame buffer */
290 memset((void *)(framebuffer_base_mb*MiB), 0x00,
291 framebuffer_size_mb*MiB);
292
293 update_window(disp_ctrl, config);
294
295 /* Set up Tegra PWM n (where n is specified in config->pwm) to drive the
296 * panel backlight.
297 */
298 printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__);
299 WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) |
300 (220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */
301 0x02e), /* frequency divider */
302 &pwm->pwm[config->pwm].csr);
303
304 udelay(config->pwm_to_bl_delay_ms * 1000);
305 if (config->backlight_en_gpio){
306 gpio_output(config->backlight_en_gpio, 1);
307 printk(BIOS_SPEW,"%s: backlight enable setting gpio %08x to %d\n",
308 __func__, config->backlight_en_gpio, 1);
309 }
310
311 printk(BIOS_INFO, "%s: display init done.\n", __func__);
312
313 /* tell depthcharge ...
314 */
315 const uint32_t bytes_per_line = ALIGN_UP(config->xres *
316 DIV_ROUND_UP(config->framebuffer_bits_per_pixel, 8), 32);
317
318 fb_add_framebuffer_info(framebuffer_base_mb*MiB, config->xres, config->yres,
319 bytes_per_line, config->framebuffer_bits_per_pixel);
320 }
321