1 /*
2 * Copyright © 2019 Google, Inc.
3 * SPDX-License-Identifier: MIT
4 */
5
6 #ifndef FREEDRENO_LAYOUT_H_
7 #define FREEDRENO_LAYOUT_H_
8
9 #include <stdbool.h>
10 #include <stdint.h>
11
12 #include "util/format/u_format.h"
13 #include "util/u_debug.h"
14 #include "util/u_math.h"
15
16 #include "common/freedreno_common.h"
17
18 BEGINC;
19
20 /* Shared freedreno mipmap layout helper
21 *
22 * It does *not* attempt to track surface transitions, in particular
23 * about UBWC state. Possibly it should, but
24 * (a) I'm not sure if in all cases we can transparently do in-
25 * place transitions (ie. a5xx textures with interleaved
26 * meta and pixel data
27 * (b) Even if we can, we probably can't assume that we have
28 * figured out yet how to do in-place transition for every
29 * generation.
30 */
31
32 /* Texture Layout on a3xx:
33 * -----------------------
34 *
35 * Each mipmap-level contains all of it's layers (ie. all cubmap
36 * faces, all 1d/2d array elements, etc). The texture sampler is
37 * programmed with the start address of each mipmap level, and hw
38 * derives the layer offset within the level.
39 *
40 *
41 * Texture Layout on a4xx+:
42 * -----------------------
43 *
44 * For cubemap and 2d array, each layer contains all of it's mipmap
45 * levels (layer_first layout).
46 *
47 * 3d textures are laid out as on a3xx.
48 *
49 * In either case, the slice represents the per-miplevel information,
50 * but in layer_first layout it only includes the first layer, and
51 * an additional offset of (rsc->layer_size * layer) must be added.
52 *
53 *
54 * UBWC Color Compressions (a5xx+):
55 * -------------------------------
56 *
57 * Color compression is only supported for tiled layouts. In general
58 * the meta "flag" buffer (ie. what holds the compression state for
59 * each block) can be separate from the color data, except for textures
60 * on a5xx where it needs to be interleaved with layers/levels of a
61 * texture.
62 */
63
64 #define FDL_MAX_MIP_LEVELS 15
65
66 struct fdl_slice {
67 uint32_t offset; /* offset of first layer in slice */
68 uint32_t size0; /* size of first layer in slice */
69 };
70
71 /* parameters for explicit (imported) layout */
72 struct fdl_explicit_layout {
73 uint32_t offset;
74 uint32_t pitch;
75 };
76
77 /**
78 * Metadata shared between vk and gallium driver for interop.
79 *
80 * NOTE: EXT_external_objects requires app to check device and driver
81 * UUIDs to ensure that the vk and gl driver are compatible. So for
82 * now we don't need any additional versioning of the metadata.
83 */
84 struct fdl_metadata {
85 uint64_t modifier;
86 };
87
88 /**
89 * Encapsulates the layout of a resource, including position of given 2d
90 * surface (layer, level) within. Or rather all the information needed
91 * to derive this.
92 */
93 struct fdl_layout {
94 struct fdl_slice slices[FDL_MAX_MIP_LEVELS];
95 struct fdl_slice ubwc_slices[FDL_MAX_MIP_LEVELS];
96 uint32_t pitch0;
97 uint32_t ubwc_width0;
98 uint64_t layer_size;
99 uint64_t ubwc_layer_size; /* in bytes */
100 bool ubwc : 1;
101 bool layer_first : 1; /* see above description */
102 bool tile_all : 1;
103
104 /* Note that for tiled textures, beyond a certain mipmap level (ie.
105 * when width is less than block size) things switch to linear. In
106 * general you should not directly look at fdl_layout::tile_mode,
107 * but instead use fdl_surface::tile_mode which will correctly take
108 * this into account.
109 */
110 uint32_t tile_mode : 2;
111 /* Bytes per pixel (where a "pixel" is a single row of a block in the case
112 * of compression), including each sample in the case of multisample
113 * layouts.
114 */
115 uint8_t cpp;
116
117 /**
118 * Left shift necessary to multiply by cpp. Invalid for NPOT cpp, please
119 * use fdl_cpp_shift() to sanity check you aren't hitting that case.
120 */
121 uint8_t cpp_shift;
122
123 uint32_t width0, height0, depth0;
124 uint32_t mip_levels;
125 uint32_t nr_samples;
126 enum pipe_format format;
127
128 uint64_t size; /* Size of the whole image, in bytes. */
129 uint32_t base_align; /* Alignment of the base address, in bytes. */
130 uint8_t pitchalign; /* log2(pitchalign) */
131 };
132
133 static inline uint32_t
fdl_cpp_shift(const struct fdl_layout * layout)134 fdl_cpp_shift(const struct fdl_layout *layout)
135 {
136 assert(util_is_power_of_two_or_zero(layout->cpp));
137 return layout->cpp_shift;
138 }
139
140 static inline uint32_t
fdl_pitch(const struct fdl_layout * layout,unsigned level)141 fdl_pitch(const struct fdl_layout *layout, unsigned level)
142 {
143 return align(u_minify(layout->pitch0, level), 1 << layout->pitchalign);
144 }
145
146 #define RGB_TILE_WIDTH_ALIGNMENT 64
147 #define RGB_TILE_HEIGHT_ALIGNMENT 16
148 #define UBWC_PLANE_SIZE_ALIGNMENT 4096
149
150 static inline uint32_t
fdl_ubwc_pitch(const struct fdl_layout * layout,unsigned level)151 fdl_ubwc_pitch(const struct fdl_layout *layout, unsigned level)
152 {
153 if (!layout->ubwc)
154 return 0;
155 return align(u_minify(layout->ubwc_width0, level), RGB_TILE_WIDTH_ALIGNMENT);
156 }
157
158 static inline uint32_t
fdl_layer_stride(const struct fdl_layout * layout,unsigned level)159 fdl_layer_stride(const struct fdl_layout *layout, unsigned level)
160 {
161 if (layout->layer_first)
162 return layout->layer_size;
163 else
164 return layout->slices[level].size0;
165 }
166
167 /* a2xx is special and needs PoT alignment for mipmaps: */
168 static inline uint32_t
fdl2_pitch(const struct fdl_layout * layout,unsigned level)169 fdl2_pitch(const struct fdl_layout *layout, unsigned level)
170 {
171 uint32_t pitch = fdl_pitch(layout, level);
172 if (level)
173 pitch = util_next_power_of_two(pitch);
174 return pitch;
175 }
176
177 static inline uint32_t
fdl2_pitch_pixels(const struct fdl_layout * layout,unsigned level)178 fdl2_pitch_pixels(const struct fdl_layout *layout, unsigned level)
179 {
180 return fdl2_pitch(layout, level) >> fdl_cpp_shift(layout);
181 }
182
183 static inline uint32_t
fdl_surface_offset(const struct fdl_layout * layout,unsigned level,unsigned layer)184 fdl_surface_offset(const struct fdl_layout *layout, unsigned level,
185 unsigned layer)
186 {
187 const struct fdl_slice *slice = &layout->slices[level];
188 return slice->offset + fdl_layer_stride(layout, level) * layer;
189 }
190
191 static inline uint32_t
fdl_ubwc_offset(const struct fdl_layout * layout,unsigned level,unsigned layer)192 fdl_ubwc_offset(const struct fdl_layout *layout, unsigned level, unsigned layer)
193 {
194 const struct fdl_slice *slice = &layout->ubwc_slices[level];
195 return slice->offset + layer * layout->ubwc_layer_size;
196 }
197
198 /* Minimum layout width to enable UBWC. */
199 #define FDL_MIN_UBWC_WIDTH 16
200
201 static inline bool
fdl_level_linear(const struct fdl_layout * layout,int level)202 fdl_level_linear(const struct fdl_layout *layout, int level)
203 {
204 if (layout->tile_all)
205 return false;
206
207 unsigned w = u_minify(layout->width0, level);
208 if (w < FDL_MIN_UBWC_WIDTH)
209 return true;
210
211 return false;
212 }
213
214 static inline uint32_t
fdl_tile_mode(const struct fdl_layout * layout,int level)215 fdl_tile_mode(const struct fdl_layout *layout, int level)
216 {
217 if (layout->tile_mode && fdl_level_linear(layout, level))
218 return 0; /* linear */
219 else
220 return layout->tile_mode;
221 }
222
223 static inline bool
fdl_ubwc_enabled(const struct fdl_layout * layout,int level)224 fdl_ubwc_enabled(const struct fdl_layout *layout, int level)
225 {
226 return layout->ubwc;
227 }
228
229 const char *fdl_tile_mode_desc(const struct fdl_layout *layout, int level);
230
231 void fdl_layout_buffer(struct fdl_layout *layout, uint32_t size);
232
233 void fdl5_layout(struct fdl_layout *layout, enum pipe_format format,
234 uint32_t nr_samples, uint32_t width0, uint32_t height0,
235 uint32_t depth0, uint32_t mip_levels, uint32_t array_size,
236 bool is_3d);
237
238 bool fdl6_layout(struct fdl_layout *layout, enum pipe_format format,
239 uint32_t nr_samples, uint32_t width0, uint32_t height0,
240 uint32_t depth0, uint32_t mip_levels, uint32_t array_size,
241 bool is_3d, struct fdl_explicit_layout *plane_layout);
242
243 static inline void
fdl_set_pitchalign(struct fdl_layout * layout,unsigned pitchalign)244 fdl_set_pitchalign(struct fdl_layout *layout, unsigned pitchalign)
245 {
246 uint32_t nblocksx = util_format_get_nblocksx(layout->format, layout->width0);
247 layout->pitchalign = pitchalign;
248 layout->pitch0 = align(nblocksx * layout->cpp, 1 << pitchalign);
249 }
250
251 void fdl_dump_layout(struct fdl_layout *layout);
252
253 void fdl6_get_ubwc_blockwidth(const struct fdl_layout *layout,
254 uint32_t *blockwidth, uint32_t *blockheight);
255
256 enum fdl_view_type {
257 FDL_VIEW_TYPE_1D = 0,
258 FDL_VIEW_TYPE_2D = 1,
259 FDL_VIEW_TYPE_CUBE = 2,
260 FDL_VIEW_TYPE_3D = 3,
261 FDL_VIEW_TYPE_BUFFER = 4,
262 };
263
264 enum fdl_chroma_location {
265 FDL_CHROMA_LOCATION_COSITED_EVEN = 0,
266 FDL_CHROMA_LOCATION_MIDPOINT = 1,
267 };
268
269 struct fdl_view_args {
270 uint32_t chip;
271 uint64_t iova;
272 uint32_t base_miplevel;
273 uint32_t level_count;
274 uint32_t base_array_layer;
275 uint32_t layer_count;
276 float min_lod_clamp;
277 unsigned char swiz[4];
278 enum pipe_format format;
279 enum fdl_view_type type;
280 enum fdl_chroma_location chroma_offsets[2];
281 bool ubwc_fc_mutable;
282 };
283
284 #define FDL6_TEX_CONST_DWORDS 16
285
286 struct fdl6_view {
287 uint64_t base_addr;
288 uint64_t ubwc_addr;
289 uint32_t layer_size;
290 uint32_t ubwc_layer_size;
291
292 uint32_t offset;
293
294 uint32_t width, height;
295 bool need_y2_align;
296
297 bool ubwc_enabled;
298
299 enum pipe_format format;
300
301 uint32_t descriptor[FDL6_TEX_CONST_DWORDS];
302
303 /* Descriptor for use as a storage image as opposed to a sampled image.
304 * This has a few differences for cube maps (e.g. type).
305 */
306 uint32_t storage_descriptor[FDL6_TEX_CONST_DWORDS];
307
308 uint32_t pitch;
309
310 /* pre-filled register values */
311 uint32_t FLAG_BUFFER_PITCH;
312
313 uint32_t RB_MRT_BUF_INFO;
314 uint32_t SP_FS_MRT_REG;
315
316 uint32_t SP_PS_2D_SRC_INFO;
317 uint32_t SP_PS_2D_SRC_SIZE;
318
319 uint32_t RB_2D_DST_INFO;
320
321 uint32_t RB_BLIT_DST_INFO;
322
323 uint32_t GRAS_LRZ_DEPTH_VIEW;
324 };
325
326 void
327 fdl6_view_init(struct fdl6_view *view, const struct fdl_layout **layouts,
328 const struct fdl_view_args *args, bool has_z24uint_s8uint);
329 void
330 fdl6_buffer_view_init(uint32_t *descriptor, enum pipe_format format,
331 const uint8_t *swiz, uint64_t iova, uint32_t size);
332
333 void
334 fdl6_format_swiz(enum pipe_format format, bool has_z24uint_s8uint,
335 unsigned char *format_swiz);
336
337 ENDC;
338
339 #endif /* FREEDRENO_LAYOUT_H_ */
340