1 //===----------------------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPUArgumentUsageInfo.h"
10 #include "AMDGPU.h"
11 #include "AMDGPUTargetMachine.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "SIRegisterInfo.h"
14 #include "llvm/CodeGen/TargetRegisterInfo.h"
15 #include "llvm/IR/Function.h"
16 #include "llvm/Support/NativeFormatting.h"
17 #include "llvm/Support/raw_ostream.h"
18 
19 using namespace llvm;
20 
21 #define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
22 
23 INITIALIZE_PASS(AMDGPUArgumentUsageInfo, DEBUG_TYPE,
24                 "Argument Register Usage Information Storage", false, true)
25 
print(raw_ostream & OS,const TargetRegisterInfo * TRI) const26 void ArgDescriptor::print(raw_ostream &OS,
27                           const TargetRegisterInfo *TRI) const {
28   if (!isSet()) {
29     OS << "<not set>\n";
30     return;
31   }
32 
33   if (isRegister())
34     OS << "Reg " << printReg(getRegister(), TRI);
35   else
36     OS << "Stack offset " << getStackOffset();
37 
38   if (isMasked()) {
39     OS << " & ";
40     llvm::write_hex(OS, Mask, llvm::HexPrintStyle::PrefixLower);
41   }
42 
43   OS << '\n';
44 }
45 
46 char AMDGPUArgumentUsageInfo::ID = 0;
47 
48 const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::ExternFunctionInfo{};
49 
50 // Hardcoded registers from fixed function ABI
51 const AMDGPUFunctionArgInfo AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
52   = AMDGPUFunctionArgInfo::fixedABILayout();
53 
doInitialization(Module & M)54 bool AMDGPUArgumentUsageInfo::doInitialization(Module &M) {
55   return false;
56 }
57 
doFinalization(Module & M)58 bool AMDGPUArgumentUsageInfo::doFinalization(Module &M) {
59   ArgInfoMap.clear();
60   return false;
61 }
62 
print(raw_ostream & OS,const Module * M) const63 void AMDGPUArgumentUsageInfo::print(raw_ostream &OS, const Module *M) const {
64   for (const auto &FI : ArgInfoMap) {
65     OS << "Arguments for " << FI.first->getName() << '\n'
66        << "  PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
67        << "  DispatchPtr: " << FI.second.DispatchPtr
68        << "  QueuePtr: " << FI.second.QueuePtr
69        << "  KernargSegmentPtr: " << FI.second.KernargSegmentPtr
70        << "  DispatchID: " << FI.second.DispatchID
71        << "  FlatScratchInit: " << FI.second.FlatScratchInit
72        << "  PrivateSegmentSize: " << FI.second.PrivateSegmentSize
73        << "  WorkGroupIDX: " << FI.second.WorkGroupIDX
74        << "  WorkGroupIDY: " << FI.second.WorkGroupIDY
75        << "  WorkGroupIDZ: " << FI.second.WorkGroupIDZ
76        << "  WorkGroupInfo: " << FI.second.WorkGroupInfo
77        << "  LDSKernelId: " << FI.second.LDSKernelId
78        << "  PrivateSegmentWaveByteOffset: "
79           << FI.second.PrivateSegmentWaveByteOffset
80        << "  ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
81        << "  ImplicitArgPtr: " << FI.second.ImplicitArgPtr
82        << "  WorkItemIDX " << FI.second.WorkItemIDX
83        << "  WorkItemIDY " << FI.second.WorkItemIDY
84        << "  WorkItemIDZ " << FI.second.WorkItemIDZ
85        << '\n';
86   }
87 }
88 
89 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const90 AMDGPUFunctionArgInfo::getPreloadedValue(
91     AMDGPUFunctionArgInfo::PreloadedValue Value) const {
92   switch (Value) {
93   case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: {
94     return std::tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
95                       &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32));
96   }
97   case AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR:
98     return std::tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
99                       &AMDGPU::SGPR_64RegClass,
100                       LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
101   case AMDGPUFunctionArgInfo::WORKGROUP_ID_X:
102     return std::tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
103                       &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
104   case AMDGPUFunctionArgInfo::WORKGROUP_ID_Y:
105     return std::tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
106                       &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
107   case AMDGPUFunctionArgInfo::WORKGROUP_ID_Z:
108     return std::tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
109                       &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
110   case AMDGPUFunctionArgInfo::LDS_KERNEL_ID:
111     return std::tuple(LDSKernelId ? &LDSKernelId : nullptr,
112                       &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
113   case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET:
114     return std::tuple(
115         PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
116         &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
117   case AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR:
118     return std::tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
119                       &AMDGPU::SGPR_64RegClass,
120                       LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
121   case AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR:
122     return std::tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
123                       &AMDGPU::SGPR_64RegClass,
124                       LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
125   case AMDGPUFunctionArgInfo::DISPATCH_ID:
126     return std::tuple(DispatchID ? &DispatchID : nullptr,
127                       &AMDGPU::SGPR_64RegClass, LLT::scalar(64));
128   case AMDGPUFunctionArgInfo::FLAT_SCRATCH_INIT:
129     return std::tuple(FlatScratchInit ? &FlatScratchInit : nullptr,
130                       &AMDGPU::SGPR_64RegClass, LLT::scalar(64));
131   case AMDGPUFunctionArgInfo::DISPATCH_PTR:
132     return std::tuple(DispatchPtr ? &DispatchPtr : nullptr,
133                       &AMDGPU::SGPR_64RegClass,
134                       LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
135   case AMDGPUFunctionArgInfo::QUEUE_PTR:
136     return std::tuple(QueuePtr ? &QueuePtr : nullptr, &AMDGPU::SGPR_64RegClass,
137                       LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
138   case AMDGPUFunctionArgInfo::WORKITEM_ID_X:
139     return std::tuple(WorkItemIDX ? &WorkItemIDX : nullptr,
140                       &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
141   case AMDGPUFunctionArgInfo::WORKITEM_ID_Y:
142     return std::tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
143                       &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
144   case AMDGPUFunctionArgInfo::WORKITEM_ID_Z:
145     return std::tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
146                       &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
147   }
148   llvm_unreachable("unexpected preloaded value type");
149 }
150 
fixedABILayout()151 constexpr AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::fixedABILayout() {
152   AMDGPUFunctionArgInfo AI;
153   AI.PrivateSegmentBuffer
154     = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
155   AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5);
156   AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7);
157 
158   // Do not pass kernarg segment pointer, only pass increment version in its
159   // place.
160   AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9);
161   AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11);
162 
163   // Skip FlatScratchInit/PrivateSegmentSize
164   AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12);
165   AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13);
166   AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14);
167   AI.LDSKernelId = ArgDescriptor::createRegister(AMDGPU::SGPR15);
168 
169   const unsigned Mask = 0x3ff;
170   AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask);
171   AI.WorkItemIDY = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 10);
172   AI.WorkItemIDZ = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 20);
173   return AI;
174 }
175 
176 const AMDGPUFunctionArgInfo &
lookupFuncArgInfo(const Function & F) const177 AMDGPUArgumentUsageInfo::lookupFuncArgInfo(const Function &F) const {
178   auto I = ArgInfoMap.find(&F);
179   if (I == ArgInfoMap.end())
180     return FixedABIFunctionInfo;
181   return I->second;
182 }
183