1 /*
2 * Copyright (c) 2021-2024, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_vdbox_aqm_cmdpar.h
24 //! \brief MHW command parameters
25 //! \details
26 //!
27
28 #ifndef __MHW_VDBOX_AQM_CMDPAR_H__
29 #define __MHW_VDBOX_AQM_CMDPAR_H__
30
31 #include "codec_def_common_encode.h"
32 #include "mhw_vdbox_cmdpar.h"
33
34 #if IGFX_AQM_INTERFACE_EXT_SUPPORT
35 #include "mhw_vdbox_aqm_cmdpar_ext.h"
36 #define __MHW_VDBOX_AQM_WRAPPER(STUFF)
37 #define __MHW_VDBOX_AQM_WRAPPER_EXT(STUFF) STUFF
38 #else
39 #define __MHW_VDBOX_AQM_WRAPPER(STUFF) STUFF
40 #define __MHW_VDBOX_AQM_WRAPPER_EXT(STUFF)
41 #endif // _MEDIA_RESERVED
42
43 namespace mhw
44 {
45 namespace vdbox
46 {
47 namespace aqm
48 {
49 enum class AQM_SURFACE_FORMAT
50 {
51 SURFACE_FORMAT_P010VARIANT = 3,
52 SURFACE_FORMAT_PLANAR4208 = 4,
53 SURFACE_FORMAT_P010 = 13,
54 };
55
_MHW_PAR_T(AQM_FRAME_START)56 struct _MHW_PAR_T(AQM_FRAME_START)
57 {
58 uint32_t aqmFrameStart = 0;
59 };
60
_MHW_PAR_T(AQM_PIC_STATE)61 struct _MHW_PAR_T(AQM_PIC_STATE)
62 {
63 uint16_t frameWidthInPixelMinus1 = 0;
64 uint16_t FrameHeightInPixelMinus1 = 0;
65 bool vdaqmEnable = false;
66 bool tileBasedEngine = false;
67 uint8_t lcuSize = 0;
68 uint8_t pixelbitdepth = 0;
69 uint8_t chromasubsampling = 0;
70 uint8_t aqmMode = 0;
71 uint8_t codectype = 0;
72 bool sseEnable = false;
73
74 __MHW_VDBOX_AQM_WRAPPER(
75 std::vector<std::function<MOS_STATUS(uint32_t *)>> extSettings);
76 __MHW_VDBOX_AQM_WRAPPER_EXT(AQM_PIC_STATE_CMDPAR_EXT);
77 };
78
_MHW_PAR_T(AQM_SURFACE_STATE)79 struct _MHW_PAR_T(AQM_SURFACE_STATE)
80 {
81 uint32_t pitch = 0;
82 uint32_t uOffset = 0;
83 uint32_t vOffset = 0;
84 uint8_t surfaceStateId = 0;
85 MOS_MEMCOMP_STATE mmcStateRawSurf = MOS_MEMCOMP_DISABLED ;
86 MOS_MEMCOMP_STATE mmcStateReconSurf = MOS_MEMCOMP_DISABLED;
87 uint32_t compressionFormat = 0;
88 AQM_SURFACE_FORMAT surfaceFormat = AQM_SURFACE_FORMAT::SURFACE_FORMAT_PLANAR4208;
89 };
90
_MHW_PAR_T(AQM_PIPE_BUF_ADDR_STATE)91 struct _MHW_PAR_T(AQM_PIPE_BUF_ADDR_STATE)
92 {
93 MOS_MEMCOMP_STATE mmcStateRawSurf = MOS_MEMCOMP_DISABLED;
94 MOS_MEMCOMP_STATE mmcStateReconSurf = MOS_MEMCOMP_DISABLED;
95 uint32_t compressionFormat = 0;
96 PMOS_RESOURCE surfaceRawBuffer = nullptr;
97 PMOS_RESOURCE surfaceReconBuffer = nullptr;
98 PMOS_RESOURCE AqmPipeBufAddrStatePar0[5] = {};
99 uint32_t AqmPipeBufAddrStatePar1[5] = {};
100 PMOS_RESOURCE AqmPipeBufAddrStatePar2 = nullptr;
101 MOS_MEMCOMP_STATE AqmPipeBufAddrStatePar3 = {};
102 PMOS_RESOURCE AqmPipeBufAddrStatePar4[5] = {};
103 MOS_MEMCOMP_STATE AqmPipeBufAddrStatePar5[5] = {};
104 };
105
_MHW_PAR_T(AQM_TILE_CODING)106 struct _MHW_PAR_T(AQM_TILE_CODING)
107 {
108 uint16_t tileId = 0;
109 uint16_t tileGroupId = 0;
110
111 uint16_t tileColPositionInSb = 0;
112 uint16_t tileRowPositionInSb = 0;
113
114 uint16_t tileWidthInSbMinus1 = 0; //!< Tile width minus 1 in SB unit
115 uint16_t tileHeightInSbMinus1 = 0; //!< Tile height minus 1 in SB unit
116
117 uint16_t tileNum = 0; //!< Tile ID in its Tile group
118 };
119
_MHW_PAR_T(AQM_VD_CONTROL_STATE)120 struct _MHW_PAR_T(AQM_VD_CONTROL_STATE)
121 {
122 };
123
_MHW_PAR_T(AQM_SLICE_STATE)124 struct _MHW_PAR_T(AQM_SLICE_STATE)
125 {
126 bool firstSuperSlice = true;
127 uint32_t tileSliceStartLcuMbX = 0;
128 uint32_t tileSliceStartLcuMbY = 0;
129 uint32_t nextTileSliceStartLcuMbX = 0;
130 uint32_t nextTileSliceStartLcuMbY = 0;
131 };
132
133 __MHW_VDBOX_AQM_WRAPPER_EXT(AQM_CMD_CMDPAR_EXT);
134
135 } // namespace aqm
136 } // namespace vdbox
137 } // namespace mhw
138
139 #endif // __MHW_VDBOX_AQM_CMDPAR_H__
140