1 /*
2 * Copyright (c) 2021-2023, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file renderhal_xe_hpg_base.cpp
24 //! \brief implementation of Gen12 hardware functions
25 //! \details Render functions
26 //!
27
28 #include "renderhal_xe_hpg_base.h"
29 #include "vp_utils.h"
30
31 //!
32 //! \brief GSH settings for Xe_hpg_base
33 //!
34 #define RENDERHAL_SAMPLERS_AVS_HPG_BASE 0
35 #define ENLARGE_KERNEL_COUNT_HPG_BASE RENDERHAL_KERNEL_COUNT * 3
36 #define ENLARGE_KERNEL_HEAP_HPG_BASE RENDERHAL_KERNEL_HEAP * 3
37 #define ENLARGE_CURBE_SIZE_HPG_BASE RENDERHAL_CURBE_SIZE * 16
38
39 extern const RENDERHAL_STATE_HEAP_SETTINGS g_cRenderHal_State_Heap_Settings_hpg_base =
40 {
41 // Global GSH Allocation parameters
42 RENDERHAL_SYNC_SIZE, //!< iSyncSize
43
44 // Media State Allocation parameters
45 RENDERHAL_MEDIA_STATES, //!< iMediaStateHeaps - Set by Initialize
46 RENDERHAL_MEDIA_IDS, //!< iMediaIDs
47 RENDERHAL_CURBE_SIZE, //!< iCurbeSize
48 RENDERHAL_SAMPLERS, //!< iSamplers
49 RENDERHAL_SAMPLERS_AVS_HPG_BASE, //!< iSamplersAVS
50 RENDERHAL_SAMPLERS_VA, //!< iSamplersVA
51 RENDERHAL_KERNEL_COUNT, //!< iKernelCount
52 RENDERHAL_KERNEL_HEAP, //!< iKernelHeapSize
53 RENDERHAL_KERNEL_BLOCK_SIZE, //!< iKernelBlockSize
54
55 // Media VFE/ID configuration, limits
56 0, //!< iPerThreadScratchSize
57 RENDERHAL_MAX_SIP_SIZE, //!< iSipSize
58
59 // Surface State Heap Settings
60 RENDERHAL_SSH_INSTANCES, //!< iSurfaceStateHeaps
61 RENDERHAL_SSH_BINDING_TABLES, //!< iBindingTables
62 RENDERHAL_SSH_SURFACE_STATES, //!< iSurfaceStates
63 RENDERHAL_SSH_SURFACES_PER_BT, //!< iSurfacesPerBT
64 RENDERHAL_SSH_BINDING_TABLE_ALIGN, //!< iBTAlignment
65 MOS_CODEC_RESOURCE_USAGE_BEGIN_CODEC //!< heapUsageType
66 };
67
68 extern const RENDERHAL_ENLARGE_PARAMS g_cRenderHal_Enlarge_State_Heap_Settings_Adv_hpg_base =
69 {
70 RENDERHAL_SSH_BINDING_TABLES_MAX, //!< iBindingTables
71 RENDERHAL_SSH_SURFACE_STATES_MAX, //!< iSurfaceStates
72 RENDERHAL_SSH_SURFACES_PER_BT, //!< iSurfacesPerBT
73 ENLARGE_KERNEL_COUNT_HPG_BASE, //!< iKernelCount
74 ENLARGE_KERNEL_HEAP_HPG_BASE, //!< iKernelHeapSize
75 ENLARGE_CURBE_SIZE_HPG_BASE //!< iCurbeSize
76 };
77
78 const uint32_t g_cLookup_RotationMode_hpg_base[8] =
79 {
80 ROTATION_IDENTITY, // 0 - MHW_ROTATION_IDENTITY
81 ROTATION_90, // 1 - MHW_ROTATION_90
82 ROTATION_180, // 2 - MHW_ROTATION_180
83 ROTATION_270, // 3 - MHW_ROTATION_270
84 ROTATION_IDENTITY, // 4 - MHW_MIRROR_HORIZONTAL
85 ROTATION_180, // 5 - MHW_MIRROR_VERTICAL
86 ROTATION_270, // 6 - MHW_ROTATE_90_MIRROR_VERTICAL
87 ROTATION_90 // 7 - MHW_ROTATE_90_MIRROR_HORIZONTAL
88 };
89
90 #define RENDERHAL_NS_PER_TICK_RENDER_HPG_BASE (83.333) // Assume it same as SKL, 83.333 nano seconds per tick in render engine
91
XRenderHal_Interface_Xe_Hpg_Base()92 XRenderHal_Interface_Xe_Hpg_Base::XRenderHal_Interface_Xe_Hpg_Base()
93 {
94 }
95
96 //!
97 //! \brief Setup Surface State
98 //! \details Setup Surface State for Gen11
99 //! \param PRENDERHAL_INTERFACE pRenderHal
100 //! [in] Pointer to Hardware Interface Structure
101 //! \param PRENDERHAL_SURFACE pRenderHalSurface
102 //! [in] Pointer to Render Hal Surface
103 //! \param PRENDERHAL_SURFACE_STATE_PARAMS pParams
104 //! [in] Pointer to Surface State Params
105 //! \param int32_t *piNumEntries
106 //! [out] Pointer to Number of Surface State Entries (Num Planes)
107 //! \param PRENDERHAL_SURFACE_STATE_ENTRY * ppSurfaceEntries
108 //! [out] Array of Surface State Entries
109 //! \param PRENDERHAL_OFFSET_OVERRIDE pOffsetOverride
110 //! [in] Ignored (not used in Gen11)
111 //! \return MOS_STATUS
112 //!
SetupSurfaceState(PRENDERHAL_INTERFACE pRenderHal,PRENDERHAL_SURFACE pRenderHalSurface,PRENDERHAL_SURFACE_STATE_PARAMS pParams,int32_t * piNumEntries,PRENDERHAL_SURFACE_STATE_ENTRY * ppSurfaceEntries,PRENDERHAL_OFFSET_OVERRIDE pOffsetOverride)113 MOS_STATUS XRenderHal_Interface_Xe_Hpg_Base::SetupSurfaceState(
114 PRENDERHAL_INTERFACE pRenderHal,
115 PRENDERHAL_SURFACE pRenderHalSurface,
116 PRENDERHAL_SURFACE_STATE_PARAMS pParams,
117 int32_t *piNumEntries,
118 PRENDERHAL_SURFACE_STATE_ENTRY *ppSurfaceEntries,
119 PRENDERHAL_OFFSET_OVERRIDE pOffsetOverride)
120 {
121 VP_FUNC_CALL();
122
123 PRENDERHAL_SURFACE_STATE_ENTRY pSurfaceEntry;
124 PMOS_PLANE_OFFSET pPlaneOffset;
125 MHW_SURFACE_STATE_PARAMS SurfStateParams;
126 PMOS_SURFACE pSurface;
127 int32_t i;
128 uint32_t dwPixelsPerSampleUV;
129 uint32_t dwSurfaceSize;
130 MOS_STATUS eStatus = MOS_STATUS_UNKNOWN;
131
132 //-----------------------------------------
133 MHW_RENDERHAL_UNUSED(pOffsetOverride);
134 MHW_RENDERHAL_CHK_NULL_RETURN(pRenderHal);
135 MHW_RENDERHAL_CHK_NULL_RETURN(pRenderHalSurface);
136 MHW_RENDERHAL_CHK_NULL_RETURN(pParams);
137 MHW_RENDERHAL_CHK_NULL_RETURN(ppSurfaceEntries);
138 MHW_RENDERHAL_CHK_NULL_RETURN(pRenderHal->pStateHeap);
139 MHW_RENDERHAL_CHK_NULL_RETURN(pRenderHal->pHwSizes);
140 MHW_RENDERHAL_CHK_NULL_RETURN(pRenderHal->pMhwStateHeap);
141
142 int32_t index = pRenderHalSurface->Rotation;
143 if (!(index >= 0 && index < 8))
144 {
145 MHW_RENDERHAL_ASSERTMESSAGE("Invalid Rotation");
146 }
147
148 dwSurfaceSize = pRenderHal->pHwSizes->dwSizeSurfaceState;
149
150 MOS_ZeroMemory(&SurfStateParams, sizeof(SurfStateParams));
151
152 // Get the Surface State Entries
153 MHW_RENDERHAL_CHK_STATUS_RETURN(pRenderHal->pfnGetSurfaceStateEntries(
154 pRenderHal,
155 pRenderHalSurface,
156 pParams,
157 piNumEntries,
158 ppSurfaceEntries));
159
160 for (i = 0; i < *piNumEntries; i++)
161 {
162 // Pointer to surface state entry for current plane
163 pSurfaceEntry = ppSurfaceEntries[i];
164
165 pSurface = pSurfaceEntry->pSurface;
166 MHW_RENDERHAL_CHK_NULL_RETURN(pSurface);
167
168 // Set the Surface State Offset from base of SSH
169 pSurfaceEntry->dwSurfStateOffset = pRenderHal->pStateHeap->iSurfaceStateOffset + // Offset to Base Of Current Surface State Area
170 pSurfaceEntry->iSurfStateID * dwSurfaceSize; // Offset to Surface State within the area
171
172 // Obtain the Pointer to the Surface state from SSH Buffer
173 if (pSurfaceEntry->dwFormat == MHW_GFX3DSTATE_SURFACEFORMAT_L8_UNORM && !IsL8FormatSupported())
174 {
175 pSurfaceEntry->dwFormat = MHW_GFX3DSTATE_SURFACEFORMAT_R8_UNORM;
176 }
177 SurfStateParams.pSurfaceState = pSurfaceEntry->pSurfaceState;
178 SurfStateParams.bUseAdvState = pSurfaceEntry->bAVS;
179 SurfStateParams.dwWidth = pSurfaceEntry->dwWidth;
180 SurfStateParams.dwHeight = pSurfaceEntry->dwHeight;
181 SurfStateParams.dwFormat = pSurfaceEntry->dwFormat;
182 SurfStateParams.dwPitch = pSurfaceEntry->dwPitch;
183 SurfStateParams.dwQPitch = pSurfaceEntry->dwQPitch;
184 SurfStateParams.bTiledSurface = pSurfaceEntry->bTiledSurface;
185 SurfStateParams.bTileWalk = pSurfaceEntry->bTileWalk;
186 SurfStateParams.dwCacheabilityControl = pRenderHal->pfnGetSurfaceMemoryObjectControl(pRenderHal, pParams);
187 SurfStateParams.RotationMode = g_cLookup_RotationMode_hpg_base[pRenderHalSurface->Rotation];
188 SurfStateParams.TileModeGMM = pSurface->TileModeGMM;
189 SurfStateParams.bGMMTileEnabled = pSurface->bGMMTileEnabled;
190
191 if (pSurface->MmcState == MOS_MEMCOMP_RC)
192 {
193 m_renderHalMMCEnabled = MEDIA_IS_SKU(pRenderHal->pSkuTable, FtrE2ECompression);
194 pRenderHal->isMMCEnabled = m_renderHalMMCEnabled;
195 }
196
197 if (IsFormatMMCSupported(pSurface->Format) &&
198 m_renderHalMMCEnabled)
199 {
200 if (pSurface->MmcState == MOS_MEMCOMP_MC ||
201 pSurface->MmcState == MOS_MEMCOMP_RC)
202 {
203 SurfStateParams.MmcState = pSurface->MmcState;
204
205 if (pSurfaceEntry->YUVPlane == MHW_U_PLANE &&
206 (pSurface->Format == Format_NV12 ||
207 pSurface->Format == Format_P010 ||
208 pSurface->Format == Format_P016))
209 {
210 SurfStateParams.dwCompressionFormat = (uint32_t)(0x00000010) | (pSurface->CompressionFormat & 0x0f);
211 }
212 else if ((pSurface->Format == Format_R8G8UN) &&
213 (pSurface->MmcState == MOS_MEMCOMP_MC))
214 {
215 /* it will be an issue if the R8G8UN surface with MC enable
216 is not chroma plane from NV12 surface, so far there is no
217 such case
218 */
219 SurfStateParams.dwCompressionFormat = (uint32_t)(0x00000010) | (pSurface->CompressionFormat & 0x0f);
220 }
221 else
222 {
223 SurfStateParams.dwCompressionFormat = pSurface->CompressionFormat & 0x1f;
224 }
225 }
226 else
227 {
228 MHW_RENDERHAL_NORMALMESSAGE("Unsupported Compression Mode for Render Engine.");
229 SurfStateParams.MmcState = MOS_MEMCOMP_DISABLED;
230 SurfStateParams.dwCompressionFormat = 0;
231 }
232
233 if (pParams->isOutput &&
234 pSurface->MmcState == MOS_MEMCOMP_RC &&
235 pSurface->OsResource.bUncompressedWriteNeeded)
236 {
237 MHW_RENDERHAL_NORMALMESSAGE("force uncompressed write if requested from resources");
238 SurfStateParams.MmcState = MOS_MEMCOMP_MC;
239 SurfStateParams.dwCompressionFormat = 0;
240 }
241
242 if (!pParams->isOutput &&
243 pSurface->MmcState != MOS_MEMCOMP_DISABLED &&
244 pSurfaceEntry->bVertStride)
245 {
246 // If input surface is interlaced, then surface should be uncompressed
247 // Remove compression setting for such surface
248 MHW_RENDERHAL_NORMALMESSAGE("interlaced input for Render Engine.");
249 SurfStateParams.MmcState = MOS_MEMCOMP_DISABLED;
250 SurfStateParams.dwCompressionFormat = 0;
251 }
252 }
253
254 // 2D/3D Surface (non-AVS)
255 SurfStateParams.SurfaceType3D = (pSurface->dwDepth > 1) ? GFX3DSTATE_SURFACETYPE_3D : GFX3DSTATE_SURFACETYPE_2D;
256 SurfStateParams.dwDepth = MOS_MAX(1, pSurface->dwDepth);
257 SurfStateParams.bVerticalLineStrideOffset = pSurfaceEntry->bVertStrideOffs;
258 SurfStateParams.bVerticalLineStride = pSurfaceEntry->bVertStride;
259 SurfStateParams.bHalfPitchChroma = pSurfaceEntry->bHalfPitchChroma;
260 SurfStateParams.bBoardColorOGL = pParams->bWidthInDword_UV ? false : true; //sampler surface
261
262 // Setup surface state
263 if (pSurfaceEntry->YUVPlane == MHW_U_PLANE ||
264 pSurfaceEntry->YUVPlane == MHW_V_PLANE)
265 {
266 pPlaneOffset = (pSurfaceEntry->YUVPlane == MHW_U_PLANE) ? &pSurface->UPlaneOffset : &pSurface->VPlaneOffset;
267
268 // Get Pixels Per Sample if we use dataport read
269 if (pParams->bWidthInDword_UV)
270 {
271 RenderHal_GetPixelsPerSample(pSurface->Format, &dwPixelsPerSampleUV);
272 }
273 else
274 {
275 // If the kernel uses sampler - do not change width (it affects coordinates)
276 dwPixelsPerSampleUV = 1;
277 }
278
279 if (dwPixelsPerSampleUV == 1)
280 {
281 SurfStateParams.iXOffset = pPlaneOffset->iXOffset;
282 }
283 else
284 {
285 SurfStateParams.iXOffset = pPlaneOffset->iXOffset / sizeof(uint32_t);
286 }
287
288 SurfStateParams.iYOffset = pPlaneOffset->iYOffset;
289 }
290 else // Y plane
291 {
292 pPlaneOffset = &pSurface->YPlaneOffset;
293 SurfStateParams.iXOffset = pPlaneOffset->iXOffset / sizeof(uint32_t);
294 SurfStateParams.iYOffset = pPlaneOffset->iYOffset;
295
296 if ((pSurfaceEntry->YUVPlane == MHW_Y_PLANE) &&
297 (pSurfaceEntry->dwFormat == MHW_GFX3DSTATE_SURFACEFORMAT_PLANAR_420_8))
298 {
299 if (pSurface->Format == Format_YV12)
300 {
301 SurfStateParams.bSeperateUVPlane = true;
302 SurfStateParams.dwXOffsetForU = 0;
303 SurfStateParams.dwYOffsetForU = pSurface->dwHeight * 2 + pSurface->dwHeight / 2;
304 SurfStateParams.dwXOffsetForV = 0;
305 SurfStateParams.dwYOffsetForV = pSurface->dwHeight * 2;
306 }
307 else
308 {
309 SurfStateParams.bSeperateUVPlane = false;
310 SurfStateParams.dwXOffsetForU = 0;
311 SurfStateParams.dwYOffsetForU = (uint32_t)((pSurface->UPlaneOffset.iSurfaceOffset - pSurface->YPlaneOffset.iSurfaceOffset) / pSurface->dwPitch) + pSurface->UPlaneOffset.iYOffset;
312 SurfStateParams.dwXOffsetForV = 0;
313 SurfStateParams.dwYOffsetForV = 0;
314 }
315 }
316
317 if ((pSurfaceEntry->YUVPlane == MHW_Y_PLANE) &&
318 (pSurfaceEntry->dwFormat == MHW_GFX3DSTATE_SURFACEFORMAT_PLANAR_420_16))
319 {
320 SurfStateParams.bSeperateUVPlane = false;
321 SurfStateParams.dwXOffsetForU = 0;
322 SurfStateParams.dwYOffsetForU = (uint32_t)((pSurface->UPlaneOffset.iSurfaceOffset - pSurface->YPlaneOffset.iSurfaceOffset) / pSurface->dwPitch) + pSurface->UPlaneOffset.iYOffset;
323 SurfStateParams.dwXOffsetForV = 0;
324 SurfStateParams.dwYOffsetForV = 0;
325 }
326 }
327
328 // Call MHW to setup the Surface State Heap entry
329 MHW_RENDERHAL_CHK_STATUS_RETURN(pRenderHal->pMhwStateHeap->SetSurfaceStateEntry(&SurfStateParams));
330
331 // Setup OS specific states
332 MHW_RENDERHAL_CHK_STATUS_RETURN(pRenderHal->pfnSetupSurfaceStatesOs(pRenderHal, pParams, pSurfaceEntry));
333 }
334
335 eStatus = MOS_STATUS_SUCCESS;
336
337 return eStatus;
338 }
339
340 //!
341 //! \brief Convert To Nano Seconds
342 //! \details Convert to Nano Seconds
343 //! \param PRENDERHAL_INTERFACE pRenderHal
344 //! [in] Pointer to Hardware Interface Structure
345 //! \param uint64_t iTicks
346 //! [in] Ticks
347 //! \param uint64_t *piNs
348 //! [in] Nano Seconds
349 //! \return void
350 //!
ConvertToNanoSeconds(PRENDERHAL_INTERFACE pRenderHal,uint64_t iTicks,uint64_t * piNs)351 void XRenderHal_Interface_Xe_Hpg_Base::ConvertToNanoSeconds(
352 PRENDERHAL_INTERFACE pRenderHal,
353 uint64_t iTicks,
354 uint64_t *piNs)
355 {
356 //-----------------------------
357 MHW_RENDERHAL_UNUSED(pRenderHal);
358 MHW_RENDERHAL_CHK_NULL_NO_STATUS_RETURN(pRenderHal);
359 MHW_RENDERHAL_CHK_NULL_NO_STATUS_RETURN(piNs);
360 //-----------------------------
361 *piNs = (uint64_t)(iTicks * RENDERHAL_NS_PER_TICK_RENDER_HPG_BASE);
362 }
363
364 //!
365 //! \brief Initialize the State Heap Settings per platform
366 //! \param PRENDERHAL_STATE_HEAP_SETTINGS pSettings
367 //! [out] Pointer to PRENDERHAL_STATE_HEAP_SETTINGSStructure
368 //! \return void
369 //!
InitStateHeapSettings(PRENDERHAL_INTERFACE pRenderHal)370 void XRenderHal_Interface_Xe_Hpg_Base::InitStateHeapSettings(
371 PRENDERHAL_INTERFACE pRenderHal)
372 {
373 MHW_RENDERHAL_CHK_NULL_NO_STATUS_RETURN(pRenderHal);
374 // Set State Heap settings for hpg_base
375 pRenderHal->StateHeapSettings = g_cRenderHal_State_Heap_Settings_hpg_base;
376 pRenderHal->enlargeStateHeapSettingsForAdv = g_cRenderHal_Enlarge_State_Heap_Settings_Adv_hpg_base;
377 }
378
379 //!
380 //! \brief Enables L3 cacheing flag and sets related registers/values
381 //! \param PRENDERHAL_INTERFACE pRenderHal
382 //! [in] Pointer to Hardware Interface
383 //! \param pCacheSettings
384 //! [in] L3 Cache Configurations
385 //! \return MOS_STATUS
386 //! MOS_STATUS_SUCCESS if success, else fail reason
387 //!
EnableL3Caching(PRENDERHAL_INTERFACE pRenderHal,PRENDERHAL_L3_CACHE_SETTINGS pCacheSettings)388 MOS_STATUS XRenderHal_Interface_Xe_Hpg_Base::EnableL3Caching(
389 PRENDERHAL_INTERFACE pRenderHal,
390 PRENDERHAL_L3_CACHE_SETTINGS pCacheSettings)
391 {
392 VP_FUNC_CALL();
393
394 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
395 mhw::render::MHW_RENDER_ENGINE_L3_CACHE_SETTINGS cacheConfig = {};
396
397 MHW_RENDERHAL_CHK_NULL_RETURN(pRenderHal);
398 MHW_RENDERHAL_CHK_NULL_RETURN(m_renderItf);
399
400 if (nullptr == pCacheSettings)
401 {
402 MHW_RENDERHAL_CHK_STATUS_RETURN(m_renderItf->EnableL3Caching(nullptr));
403 return eStatus;
404 }
405 cacheConfig.dwCntlReg = RENDERHAL_L3_CACHE_CONFIG_CNTLREG_VALUE_XE_HPG_BASE_RENDERHAL;
406 // Override L3 cache configuration
407 if (pCacheSettings->bOverride)
408 {
409 if (pCacheSettings->bCntlRegOverride)
410 {
411 cacheConfig.dwCntlReg = pCacheSettings->dwCntlReg;
412 }
413 }
414 MHW_RENDERHAL_CHK_STATUS_RETURN(m_renderItf->EnableL3Caching(&cacheConfig));
415
416 return eStatus;
417 }
418
SetFusedEUDispatch(bool enable)419 void XRenderHal_Interface_Xe_Hpg_Base::SetFusedEUDispatch(bool enable)
420 {
421 m_vfeStateParams.bFusedEuDispatch = enable? true : false;
422 }
423
SetNumOfWalkers(uint32_t numOfWalkers)424 MOS_STATUS XRenderHal_Interface_Xe_Hpg_Base::SetNumOfWalkers(uint32_t numOfWalkers)
425 {
426 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
427 // value: [0,1] - One or two active walkers per context.
428 if (numOfWalkers > 2)
429 {
430 m_vfeStateParams.numOfWalkers = 1;
431 }
432 else if (numOfWalkers > 0)
433 {
434 m_vfeStateParams.numOfWalkers = numOfWalkers - 1;
435 }
436 return eStatus;
437 }
438
439 //! \brief Set L3 cache override config parameters
440 //! \param [in] pRenderHal
441 //! Pointer to RenderHal Interface Structure
442 //! \param [in,out] pCacheSettings
443 //! Pointer to pCacheSettings
444 //! \param [in] bEnableSLM
445 //! Flag to enable SLM
446 //! \return MOS_STATUS
447 //! MOS_STATUS_SUCCESS if success. Error code otherwise
448 //!
SetCacheOverrideParams(PRENDERHAL_INTERFACE pRenderHal,PRENDERHAL_L3_CACHE_SETTINGS pCacheSettings,bool bEnableSLM)449 MOS_STATUS XRenderHal_Interface_Xe_Hpg_Base::SetCacheOverrideParams(
450 PRENDERHAL_INTERFACE pRenderHal,
451 PRENDERHAL_L3_CACHE_SETTINGS pCacheSettings,
452 bool bEnableSLM)
453 {
454 VP_FUNC_CALL();
455
456 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
457
458 MHW_RENDERHAL_CHK_NULL_RETURN(pCacheSettings);
459 MHW_RENDERHAL_CHK_NULL_RETURN(pRenderHal);
460
461 pCacheSettings->dwCntlReg = RENDERHAL_L3_CACHE_CONFIG_CNTLREG_VALUE_XE_HPG_BASE_RENDERHAL;
462
463 pCacheSettings->bCntlRegOverride = true;
464
465 return eStatus;
466 }
467
468 //! \brief Get the size of Render Surface State Command
469 //! \return size_t
470 //! the size of render surface state command
GetSurfaceStateCmdSize()471 size_t XRenderHal_Interface_Xe_Hpg_Base::GetSurfaceStateCmdSize()
472 {
473 return MOS_ALIGN_CEIL( MOS_MAX(mhw_state_heap_xe_hpg::RENDER_SURFACE_STATE_CMD::byteSize,
474 mhw_state_heap_xe_hpg::MEDIA_SURFACE_STATE_CMD::byteSize), MHW_SURFACE_STATE_ALIGN);
475 }
476
477 static const uint32_t FIXED_SCRATCH_SPACE_BUFFER_INDEX = 6;
478
SetScratchSpaceBufferState(RENDERHAL_INTERFACE * renderHal,uint32_t indexOfBindingTable)479 MOS_STATUS XRenderHal_Interface_Xe_Hpg_Base::SetScratchSpaceBufferState(
480 RENDERHAL_INTERFACE *renderHal,
481 uint32_t indexOfBindingTable)
482 {
483 if (m_scratchSpaceResource.iSize <= 0)
484 {
485 return MOS_STATUS_SUCCESS; // Scratch space is not allocated. No need to set states.
486 }
487
488 RENDERHAL_SURFACE renderhal_surface;
489 MOS_ZeroMemory(&renderhal_surface, sizeof(renderhal_surface));
490 renderhal_surface.OsSurface.OsResource = m_scratchSpaceResource;
491 renderhal_surface.OsSurface.dwWidth = m_scratchSpaceResource.iSize;
492 renderhal_surface.OsSurface.dwHeight = 1;
493 renderhal_surface.OsSurface.Format = Format_RAW;
494 renderhal_surface.OsSurface.Type = MOS_GFXRES_SCRATCH;
495 renderhal_surface.rcSrc.right = m_scratchSpaceResource.iSize;;
496 renderhal_surface.rcSrc.bottom = 1;
497 renderhal_surface.rcDst = renderhal_surface.rcSrc;
498
499 MOS_STATUS result = renderHal->pOsInterface->pfnRegisterResource(
500 renderHal->pOsInterface, &(renderhal_surface.OsSurface.OsResource),
501 true, true);
502 if (MOS_STATUS_SUCCESS != result)
503 {
504 return result;
505 }
506
507 RENDERHAL_SURFACE_STATE_PARAMS renderhal_surface_state_param;
508 MOS_ZeroMemory(&renderhal_surface_state_param,
509 sizeof(renderhal_surface_state_param));
510 renderhal_surface_state_param.isOutput = 1;
511 renderhal_surface_state_param.MemObjCtl = 2;
512
513 RENDERHAL_SURFACE_STATE_ENTRY *renderhal_surface_state_entry = nullptr;
514 renderHal->pfnSetupBufferSurfaceState(renderHal, &renderhal_surface,
515 &renderhal_surface_state_param,
516 &renderhal_surface_state_entry);
517 m_vfeStateParams.scratchStateOffset
518 = renderhal_surface_state_entry->dwSurfStateOffset;
519
520 renderHal->pfnBindSurfaceState(renderHal,
521 indexOfBindingTable,
522 FIXED_SCRATCH_SPACE_BUFFER_INDEX,
523 renderhal_surface_state_entry);
524 return MOS_STATUS_SUCCESS;
525 }
526
MHW_SETPAR_DECL_SRC(CFE_STATE,XRenderHal_Interface_Xe_Hpg_Base)527 MHW_SETPAR_DECL_SRC(CFE_STATE, XRenderHal_Interface_Xe_Hpg_Base)
528 {
529 MHW_VFE_PARAMS* pVfeStateParams = nullptr;
530 MHW_VFE_PARAMS_XE_HPG* paramsNext = nullptr;
531 pVfeStateParams = nullptr;
532
533 MHW_RENDERHAL_CHK_NULL_RETURN(m_renderHal);
534 MHW_RENDERHAL_CHK_NULL_RETURN(m_renderHal->pHwCaps);
535 MHW_RENDERHAL_CHK_NULL_RETURN(m_renderHal->pRenderHalPltInterface);
536 MHW_RENDERHAL_CHK_NULL_RETURN(m_renderHal->pRenderHalPltInterface->GetVfeStateParameters());
537
538 pVfeStateParams = m_renderHal->pRenderHalPltInterface->GetVfeStateParameters();
539 params.pKernelState = pVfeStateParams->pKernelState;
540
541 if (pVfeStateParams->pKernelState)
542 {
543 params.dwMaximumNumberofThreads = (pVfeStateParams->dwMaximumNumberofThreads) ? pVfeStateParams->dwMaximumNumberofThreads - 1 : pVfeStateParams->pKernelState->KernelParams.iThreadCount - 1;
544 }
545 else
546 {
547 params.dwMaximumNumberofThreads = (pVfeStateParams->dwMaximumNumberofThreads) ? pVfeStateParams->dwMaximumNumberofThreads - 1 : m_renderHal->pHwCaps->dwMaxThreads - 1;
548 }
549
550 paramsNext = dynamic_cast<MHW_VFE_PARAMS_XE_HPG*>(pVfeStateParams);
551 if (paramsNext != nullptr)
552 {
553 params.ScratchSpaceBuffer = paramsNext->scratchStateOffset >> 6;
554 params.FusedEuDispatch = paramsNext->bFusedEuDispatch ? false : true; // disabled if DW3.FusedEuDispath = 1
555 params.NumberOfWalkers = paramsNext->numOfWalkers;
556 params.SingleSliceDispatchCcsMode = paramsNext->enableSingleSliceDispatchCcsMode;
557 }
558
559 return MOS_STATUS_SUCCESS;
560 }