1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/blend.h"
35 #include "util/macros.h"
36 #include "common/v3d_debug.h"
37 #include "common/v3d_device_info.h"
38 #include "common/v3d_limits.h"
39 #include "compiler/nir/nir.h"
40 #include "util/list.h"
41 #include "util/u_math.h"
42
43 #include "qpu/qpu_instr.h"
44
45 /**
46 * Maximum number of outstanding TMU operations we can queue for execution.
47 *
48 * This is mostly limited by the size of the TMU fifos. The Input and Config
49 * fifos can stall, but we prefer that than injecting TMU flushes manually
50 * in the driver, so we can ignore these, but we can't overflow the Output fifo,
51 * which has 16 / threads per-thread entries, meaning that the maximum number
52 * of outstanding LDTMUs we can ever have is 8, for a 2-way threaded shader.
53 * This means that at most we can have 8 outstanding TMU loads, if each load
54 * is just one component.
55 *
56 * NOTE: we could actually have a larger value here because TMU stores don't
57 * consume any entries in the Output fifo (so we could have any number of
58 * outstanding stores) and the driver keeps track of used Output fifo entries
59 * and will flush if we ever needs more than 8, but since loads are much more
60 * common than stores, it is probably not worth it.
61 */
62 #define MAX_TMU_QUEUE_SIZE 8
63
64 /**
65 * Maximum offset distance in bytes between two consecutive constant UBO loads
66 * for the same UBO where we would favor updating the unifa address by emitting
67 * dummy ldunifa instructions to avoid writing the unifa register.
68 */
69 #define MAX_UNIFA_SKIP_DISTANCE 16
70
71 struct nir_builder;
72
73 struct v3d_fs_inputs {
74 /**
75 * Array of the meanings of the VPM inputs this shader needs.
76 *
77 * It doesn't include those that aren't part of the VPM, like
78 * point/line coordinates.
79 */
80 struct v3d_varying_slot *input_slots;
81 uint32_t num_inputs;
82 };
83
84 enum qfile {
85 /** An unused source or destination register. */
86 QFILE_NULL,
87
88 /** A physical register, such as the W coordinate payload. */
89 QFILE_REG,
90 /** One of the registers for fixed function interactions. */
91 QFILE_MAGIC,
92
93 /**
94 * A virtual register, that will be allocated to actual accumulator
95 * or physical registers later.
96 */
97 QFILE_TEMP,
98
99 /**
100 * Stores an immediate value in the index field that will be used
101 * directly by qpu_load_imm().
102 */
103 QFILE_LOAD_IMM,
104
105 /**
106 * Stores an immediate value in the index field that can be turned
107 * into a small immediate field by qpu_encode_small_immediate().
108 */
109 QFILE_SMALL_IMM,
110 };
111
112 /**
113 * A reference to a QPU register or a virtual temp register.
114 */
115 struct qreg {
116 enum qfile file;
117 uint32_t index;
118 };
119
vir_reg(enum qfile file,uint32_t index)120 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
121 {
122 return (struct qreg){file, index};
123 }
124
vir_magic_reg(uint32_t index)125 static inline struct qreg vir_magic_reg(uint32_t index)
126 {
127 return (struct qreg){QFILE_MAGIC, index};
128 }
129
vir_nop_reg(void)130 static inline struct qreg vir_nop_reg(void)
131 {
132 return (struct qreg){QFILE_NULL, 0};
133 }
134
135 /**
136 * A reference to an actual register at the QPU level, for register
137 * allocation.
138 */
139 struct qpu_reg {
140 bool magic;
141 bool smimm;
142 int index;
143 };
144
145 struct qinst {
146 /** Entry in qblock->instructions */
147 struct list_head link;
148
149 /**
150 * The instruction being wrapped. Its condition codes, pack flags,
151 * signals, etc. will all be used, with just the register references
152 * being replaced by the contents of qinst->dst and qinst->src[].
153 */
154 struct v3d_qpu_instr qpu;
155
156 /* Pre-register-allocation references to src/dst registers */
157 struct qreg dst;
158 struct qreg src[3];
159 bool is_last_thrsw;
160
161 /* If the instruction reads a uniform (other than through src[i].file
162 * == QFILE_UNIF), that uniform's index in c->uniform_contents. ~0
163 * otherwise.
164 */
165 int uniform;
166
167 /* If this is a a TLB Z write */
168 bool is_tlb_z_write;
169
170 /* If this is a retiring TMU instruction (the last in a lookup sequence),
171 * how many ldtmu instructions are required to read the results.
172 */
173 uint32_t ldtmu_count;
174
175 /* Position of this instruction in the program. Filled in during
176 * register allocation.
177 */
178 int32_t ip;
179 };
180
181 enum quniform_contents {
182 /**
183 * Indicates that a constant 32-bit value is copied from the program's
184 * uniform contents.
185 */
186 QUNIFORM_CONSTANT,
187 /**
188 * Indicates that the program's uniform contents are used as an index
189 * into the GL uniform storage.
190 */
191 QUNIFORM_UNIFORM,
192
193 /** @{
194 * Scaling factors from clip coordinates to relative to the viewport
195 * center.
196 *
197 * This is used by the coordinate and vertex shaders to produce the
198 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
199 * point offsets from the viewport ccenter.
200 */
201 QUNIFORM_VIEWPORT_X_SCALE,
202 QUNIFORM_VIEWPORT_Y_SCALE,
203 /** @} */
204
205 QUNIFORM_VIEWPORT_Z_OFFSET,
206 QUNIFORM_VIEWPORT_Z_SCALE,
207
208 QUNIFORM_USER_CLIP_PLANE,
209
210 /**
211 * A reference to a V3D 3.x texture config parameter 0 uniform.
212 *
213 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
214 * defines texture type, miplevels, and such. It will be found as a
215 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
216 */
217 QUNIFORM_TEXTURE_CONFIG_P0_0,
218 QUNIFORM_TEXTURE_CONFIG_P0_1,
219 QUNIFORM_TEXTURE_CONFIG_P0_2,
220 QUNIFORM_TEXTURE_CONFIG_P0_3,
221 QUNIFORM_TEXTURE_CONFIG_P0_4,
222 QUNIFORM_TEXTURE_CONFIG_P0_5,
223 QUNIFORM_TEXTURE_CONFIG_P0_6,
224 QUNIFORM_TEXTURE_CONFIG_P0_7,
225 QUNIFORM_TEXTURE_CONFIG_P0_8,
226 QUNIFORM_TEXTURE_CONFIG_P0_9,
227 QUNIFORM_TEXTURE_CONFIG_P0_10,
228 QUNIFORM_TEXTURE_CONFIG_P0_11,
229 QUNIFORM_TEXTURE_CONFIG_P0_12,
230 QUNIFORM_TEXTURE_CONFIG_P0_13,
231 QUNIFORM_TEXTURE_CONFIG_P0_14,
232 QUNIFORM_TEXTURE_CONFIG_P0_15,
233 QUNIFORM_TEXTURE_CONFIG_P0_16,
234 QUNIFORM_TEXTURE_CONFIG_P0_17,
235 QUNIFORM_TEXTURE_CONFIG_P0_18,
236 QUNIFORM_TEXTURE_CONFIG_P0_19,
237 QUNIFORM_TEXTURE_CONFIG_P0_20,
238 QUNIFORM_TEXTURE_CONFIG_P0_21,
239 QUNIFORM_TEXTURE_CONFIG_P0_22,
240 QUNIFORM_TEXTURE_CONFIG_P0_23,
241 QUNIFORM_TEXTURE_CONFIG_P0_24,
242 QUNIFORM_TEXTURE_CONFIG_P0_25,
243 QUNIFORM_TEXTURE_CONFIG_P0_26,
244 QUNIFORM_TEXTURE_CONFIG_P0_27,
245 QUNIFORM_TEXTURE_CONFIG_P0_28,
246 QUNIFORM_TEXTURE_CONFIG_P0_29,
247 QUNIFORM_TEXTURE_CONFIG_P0_30,
248 QUNIFORM_TEXTURE_CONFIG_P0_31,
249 QUNIFORM_TEXTURE_CONFIG_P0_32,
250
251 /**
252 * A reference to a V3D 3.x texture config parameter 1 uniform.
253 *
254 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
255 * has the pointer to the indirect texture state. Our data[] field
256 * will have a packed p1 value, but the address field will be just
257 * which texture unit's texture should be referenced.
258 */
259 QUNIFORM_TEXTURE_CONFIG_P1,
260
261 /* A V3D 4.x texture config parameter. The high 8 bits will be
262 * which texture or sampler is being sampled, and the driver must
263 * replace the address field with the appropriate address.
264 */
265 QUNIFORM_TMU_CONFIG_P0,
266 QUNIFORM_TMU_CONFIG_P1,
267
268 QUNIFORM_IMAGE_TMU_CONFIG_P0,
269
270 QUNIFORM_TEXTURE_FIRST_LEVEL,
271
272 QUNIFORM_TEXTURE_WIDTH,
273 QUNIFORM_TEXTURE_HEIGHT,
274 QUNIFORM_TEXTURE_DEPTH,
275 QUNIFORM_TEXTURE_ARRAY_SIZE,
276 QUNIFORM_TEXTURE_LEVELS,
277 QUNIFORM_TEXTURE_SAMPLES,
278
279 QUNIFORM_UBO_ADDR,
280
281 QUNIFORM_TEXRECT_SCALE_X,
282 QUNIFORM_TEXRECT_SCALE_Y,
283
284 /* Returns the base offset of the SSBO given by the data value. */
285 QUNIFORM_SSBO_OFFSET,
286
287 /* Returns the size of the SSBO or UBO given by the data value. */
288 QUNIFORM_GET_SSBO_SIZE,
289 QUNIFORM_GET_UBO_SIZE,
290
291 /* Sizes (in pixels) of a shader image given by the data value. */
292 QUNIFORM_IMAGE_WIDTH,
293 QUNIFORM_IMAGE_HEIGHT,
294 QUNIFORM_IMAGE_DEPTH,
295 QUNIFORM_IMAGE_ARRAY_SIZE,
296
297 QUNIFORM_LINE_WIDTH,
298
299 /* The line width sent to hardware. This includes the expanded width
300 * when anti-aliasing is enabled.
301 */
302 QUNIFORM_AA_LINE_WIDTH,
303
304 /* Number of workgroups passed to glDispatchCompute in the dimension
305 * selected by the data value.
306 */
307 QUNIFORM_NUM_WORK_GROUPS,
308
309 /* Base workgroup offset passed to vkCmdDispatchBase in the dimension
310 * selected by the data value.
311 */
312 QUNIFORM_WORK_GROUP_BASE,
313
314 /* Workgroup size for variable workgroup support */
315 QUNIFORM_WORK_GROUP_SIZE,
316
317 /**
318 * Returns the the offset of the scratch buffer for register spilling.
319 */
320 QUNIFORM_SPILL_OFFSET,
321 QUNIFORM_SPILL_SIZE_PER_THREAD,
322
323 /**
324 * Returns the offset of the shared memory for compute shaders.
325 *
326 * This will be accessed using TMU general memory operations, so the
327 * L2T cache will effectively be the shared memory area.
328 */
329 QUNIFORM_SHARED_OFFSET,
330
331 /**
332 * OpenCL variable shared memory
333 *
334 * This will only be used when the shader declares variable_shared_memory.
335 */
336 QUNIFORM_SHARED_SIZE,
337
338 /**
339 * Returns the number of layers in the framebuffer.
340 *
341 * This is used to cap gl_Layer in geometry shaders to avoid
342 * out-of-bounds accesses into the tile state during binning.
343 */
344 QUNIFORM_FB_LAYERS,
345
346 /**
347 * Current value of gl_ViewIndex for Multiview rendering.
348 */
349 QUNIFORM_VIEW_INDEX,
350
351 /**
352 * Inline uniform buffers
353 */
354 QUNIFORM_INLINE_UBO_0,
355 QUNIFORM_INLINE_UBO_1,
356 QUNIFORM_INLINE_UBO_2,
357 QUNIFORM_INLINE_UBO_3,
358
359 /**
360 * Current value of DrawIndex for Multidraw
361 */
362 QUNIFORM_DRAW_ID,
363 };
364
v3d_unit_data_create(uint32_t unit,uint32_t value)365 static inline uint32_t v3d_unit_data_create(uint32_t unit, uint32_t value)
366 {
367 assert(value < (1 << 24));
368 return unit << 24 | value;
369 }
370
v3d_unit_data_get_unit(uint32_t data)371 static inline uint32_t v3d_unit_data_get_unit(uint32_t data)
372 {
373 return data >> 24;
374 }
375
v3d_unit_data_get_offset(uint32_t data)376 static inline uint32_t v3d_unit_data_get_offset(uint32_t data)
377 {
378 return data & 0xffffff;
379 }
380
381 struct v3d_varying_slot {
382 uint8_t slot_and_component;
383 };
384
385 static inline struct v3d_varying_slot
v3d_slot_from_slot_and_component(uint8_t slot,uint8_t component)386 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
387 {
388 assert(slot < 255 / 4);
389 return (struct v3d_varying_slot){ (slot << 2) + component };
390 }
391
v3d_slot_get_slot(struct v3d_varying_slot slot)392 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
393 {
394 return slot.slot_and_component >> 2;
395 }
396
v3d_slot_get_component(struct v3d_varying_slot slot)397 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
398 {
399 return slot.slot_and_component & 3;
400 }
401
402 struct v3d_key {
403 struct {
404 uint8_t swizzle[4];
405 } tex[V3D_MAX_TEXTURE_SAMPLERS];
406 struct {
407 uint8_t return_size;
408 uint8_t return_channels;
409 } sampler[V3D_MAX_TEXTURE_SAMPLERS];
410
411 uint8_t num_tex_used;
412 uint8_t num_samplers_used;
413 uint8_t ucp_enables;
414 bool is_last_geometry_stage;
415 bool robust_uniform_access;
416 bool robust_storage_access;
417 bool robust_image_access;
418 };
419
420 struct v3d_fs_key {
421 struct v3d_key base;
422 bool is_points;
423 bool is_lines;
424 bool line_smoothing;
425 bool point_coord_upper_left;
426 bool msaa;
427 bool sample_alpha_to_coverage;
428 bool sample_alpha_to_one;
429 /* Mask of which color render targets are present. */
430 uint8_t cbufs;
431 uint8_t swap_color_rb;
432 /* Mask of which render targets need to be written as 32-bit floats */
433 uint8_t f32_color_rb;
434 /* Masks of which render targets need to be written as ints/uints.
435 * Used by gallium to work around lost information in TGSI.
436 */
437 uint8_t int_color_rb;
438 uint8_t uint_color_rb;
439
440 /* Color format information per render target. Only set when logic
441 * operations are enabled.
442 */
443 struct {
444 enum pipe_format format;
445 uint8_t swizzle[4];
446 } color_fmt[V3D_MAX_DRAW_BUFFERS];
447
448 enum pipe_logicop logicop_func;
449 uint32_t point_sprite_mask;
450
451 /* If the fragment shader reads gl_PrimitiveID then we have 2 scenarios:
452 *
453 * - If there is a geometry shader, then gl_PrimitiveID must be written
454 * by it and the fragment shader loads it as a regular explicit input
455 * varying. This is the only valid use case in GLES 3.1.
456 *
457 * - If there is not a geometry shader (allowed since GLES 3.2 and
458 * Vulkan 1.0), then gl_PrimitiveID must be implicitly written by
459 * hardware and is considered an implicit input varying in the
460 * fragment shader.
461 */
462 bool has_gs;
463 };
464
465 struct v3d_gs_key {
466 struct v3d_key base;
467
468 struct v3d_varying_slot used_outputs[V3D_MAX_FS_INPUTS];
469 uint8_t num_used_outputs;
470
471 bool is_coord;
472 bool per_vertex_point_size;
473 };
474
475 struct v3d_vs_key {
476 struct v3d_key base;
477
478 struct v3d_varying_slot used_outputs[V3D_MAX_ANY_STAGE_INPUTS];
479 uint8_t num_used_outputs;
480
481 /* A bit-mask indicating if we need to swap the R/B channels for
482 * vertex attributes. Since the hardware doesn't provide any
483 * means to swizzle vertex attributes we need to do it in the shader.
484 */
485 uint32_t va_swap_rb_mask;
486
487 bool is_coord;
488 bool per_vertex_point_size;
489 bool clamp_color;
490 };
491
492 /** A basic block of VIR instructions. */
493 struct qblock {
494 struct list_head link;
495
496 struct list_head instructions;
497
498 struct set *predecessors;
499 struct qblock *successors[2];
500
501 int index;
502
503 /* Instruction IPs for the first and last instruction of the block.
504 * Set by qpu_schedule.c.
505 */
506 uint32_t start_qpu_ip;
507 uint32_t end_qpu_ip;
508
509 /* Instruction IP for the branch instruction of the block. Set by
510 * qpu_schedule.c.
511 */
512 uint32_t branch_qpu_ip;
513
514 /** Offset within the uniform stream at the start of the block. */
515 uint32_t start_uniform;
516 /** Offset within the uniform stream of the branch instruction */
517 uint32_t branch_uniform;
518
519 /**
520 * Has the terminating branch of this block already been emitted
521 * by a break or continue?
522 */
523 bool branch_emitted;
524
525 /** @{ used by v3d_vir_live_variables.c */
526 BITSET_WORD *def;
527 BITSET_WORD *defin;
528 BITSET_WORD *defout;
529 BITSET_WORD *use;
530 BITSET_WORD *live_in;
531 BITSET_WORD *live_out;
532 int start_ip, end_ip;
533 /** @} */
534 };
535
536 /** Which util/list.h add mode we should use when inserting an instruction. */
537 enum vir_cursor_mode {
538 vir_cursor_add,
539 vir_cursor_addtail,
540 };
541
542 /**
543 * Tracking structure for where new instructions should be inserted. Create
544 * with one of the vir_after_inst()-style helper functions.
545 *
546 * This does not protect against removal of the block or instruction, so we
547 * have an assert in instruction removal to try to catch it.
548 */
549 struct vir_cursor {
550 enum vir_cursor_mode mode;
551 struct list_head *link;
552 };
553
554 static inline struct vir_cursor
vir_before_inst(struct qinst * inst)555 vir_before_inst(struct qinst *inst)
556 {
557 return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
558 }
559
560 static inline struct vir_cursor
vir_after_inst(struct qinst * inst)561 vir_after_inst(struct qinst *inst)
562 {
563 return (struct vir_cursor){ vir_cursor_add, &inst->link };
564 }
565
566 static inline struct vir_cursor
vir_before_block(struct qblock * block)567 vir_before_block(struct qblock *block)
568 {
569 return (struct vir_cursor){ vir_cursor_add, &block->instructions };
570 }
571
572 static inline struct vir_cursor
vir_after_block(struct qblock * block)573 vir_after_block(struct qblock *block)
574 {
575 return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
576 }
577
578 enum v3d_compilation_result {
579 V3D_COMPILATION_SUCCEEDED,
580 V3D_COMPILATION_FAILED_REGISTER_ALLOCATION,
581 V3D_COMPILATION_FAILED,
582 };
583
584 /**
585 * Compiler state saved across compiler invocations, for any expensive global
586 * setup.
587 */
588 struct v3d_compiler {
589 const struct v3d_device_info *devinfo;
590 uint32_t max_inline_uniform_buffers;
591 struct ra_regs *regs;
592 struct ra_class *reg_class_any[3];
593 struct ra_class *reg_class_r5[3];
594 struct ra_class *reg_class_phys[3];
595 struct ra_class *reg_class_phys_or_acc[3];
596 };
597
598 /**
599 * This holds partially interpolated inputs as provided by hardware
600 * (The Vp = A*(x - x0) + B*(y - y0) term), as well as the C coefficient
601 * required to compute the final interpolated value.
602 */
603 struct v3d_interp_input {
604 struct qreg vp;
605 struct qreg C;
606 unsigned mode; /* interpolation mode */
607 };
608
609 struct v3d_ra_node_info {
610 struct {
611 uint32_t priority;
612 uint8_t class_bits;
613 bool is_program_end;
614 bool unused;
615
616 /* If this node may have an allocation conflict with a
617 * payload register.
618 */
619 bool payload_conflict;
620
621 /* V3D 7.x */
622 bool is_ldunif_dst;
623 } *info;
624 uint32_t alloc_count;
625 };
626
627 struct v3d_compile {
628 const struct v3d_device_info *devinfo;
629 nir_shader *s;
630 nir_function_impl *impl;
631 struct exec_list *cf_node_list;
632 const struct v3d_compiler *compiler;
633
634 void (*debug_output)(const char *msg,
635 void *debug_output_data);
636 void *debug_output_data;
637
638 /**
639 * Mapping from nir_register * or nir_def * to array of struct
640 * qreg for the values.
641 */
642 struct hash_table *def_ht;
643
644 /* For each temp, the instruction generating its value. */
645 struct qinst **defs;
646 uint32_t defs_array_size;
647
648 /* TMU pipelining tracking */
649 struct {
650 /* NIR registers that have been updated with a TMU operation
651 * that has not been flushed yet.
652 */
653 struct set *outstanding_regs;
654
655 uint32_t output_fifo_size;
656
657 struct {
658 nir_def *def;
659 uint8_t num_components;
660 uint8_t component_mask;
661 } flush[MAX_TMU_QUEUE_SIZE];
662 uint32_t flush_count;
663 uint32_t total_count;
664 } tmu;
665
666 /**
667 * Inputs to the shader, arranged by TGSI declaration order.
668 *
669 * Not all fragment shader QFILE_VARY reads are present in this array.
670 */
671 struct qreg *inputs;
672 /**
673 * Partially interpolated inputs to the shader.
674 */
675 struct v3d_interp_input *interp;
676 struct qreg *outputs;
677 bool msaa_per_sample_output;
678 struct qreg color_reads[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
679 struct qreg sample_colors[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
680 uint32_t inputs_array_size;
681 uint32_t outputs_array_size;
682 uint32_t uniforms_array_size;
683
684 /* Booleans for whether the corresponding QFILE_VARY[i] is
685 * flat-shaded. This includes gl_FragColor flat-shading, which is
686 * customized based on the shademodel_flat shader key.
687 */
688 uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
689
690 uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
691
692 uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
693
694 bool uses_center_w;
695 bool writes_z;
696 bool writes_z_from_fep;
697 bool reads_z;
698 bool uses_implicit_point_line_varyings;
699
700 /* True if a fragment shader reads gl_PrimitiveID */
701 bool fs_uses_primitive_id;
702
703 /* Whether we are using the fallback scheduler. This will be set after
704 * register allocation has failed once.
705 */
706 bool fallback_scheduler;
707
708 /* Disable TMU pipelining. This may increase the chances of being able
709 * to compile shaders with high register pressure that require to emit
710 * TMU spills.
711 */
712 bool disable_tmu_pipelining;
713 bool pipelined_any_tmu;
714
715 /* Disable sorting of UBO loads with constant offset. This may
716 * increase the chances of being able to compile shaders with high
717 * register pressure.
718 */
719 bool disable_constant_ubo_load_sorting;
720 bool sorted_any_ubo_loads;
721
722 /* Moves UBO/SSBO loads right before their first user (nir_opt_move).
723 * This can reduce register pressure.
724 */
725 bool move_buffer_loads;
726
727 /* Emits ldunif for each new uniform, even if the uniform was already
728 * emitted in the same block. Useful to compile shaders with high
729 * register pressure or to disable the optimization during uniform
730 * spills.
731 */
732 bool disable_ldunif_opt;
733
734 /* Disables loop unrolling to reduce register pressure. */
735 bool disable_loop_unrolling;
736 bool unrolled_any_loops;
737
738 /* Disables nir_opt_gcm to reduce register pressure. */
739 bool disable_gcm;
740
741 /* If calling nir_opt_gcm made any progress. Used to skip new rebuilds
742 * if possible
743 */
744 bool gcm_progress;
745
746 /* Disables scheduling of general TMU loads (and unfiltered image load).
747 */
748 bool disable_general_tmu_sched;
749 bool has_general_tmu_load;
750
751 /* Minimum number of threads we are willing to use to register allocate
752 * a shader with the current compilation strategy. This only prevents
753 * us from lowering the thread count to register allocate successfully,
754 * which can be useful when we prefer doing other changes to the
755 * compilation strategy before dropping thread count.
756 */
757 uint32_t min_threads_for_reg_alloc;
758
759 /* Whether TMU spills are allowed. If this is disabled it may cause
760 * register allocation to fail. We set this to favor other compilation
761 * strategies that can reduce register pressure and hopefully reduce or
762 * eliminate TMU spills in the shader.
763 */
764 uint32_t max_tmu_spills;
765
766 uint32_t compile_strategy_idx;
767
768 /* The UBO index and block used with the last unifa load, as well as the
769 * current unifa offset *after* emitting that load. This is used to skip
770 * unifa writes (and their 3 delay slot) when the next UBO load reads
771 * right after the previous one in the same block.
772 */
773 struct qblock *current_unifa_block;
774 int32_t current_unifa_index;
775 uint32_t current_unifa_offset;
776 bool current_unifa_is_ubo;
777
778 /* State for whether we're executing on each channel currently. 0 if
779 * yes, otherwise a block number + 1 that the channel jumped to.
780 */
781 struct qreg execute;
782 bool in_control_flow;
783
784 struct qreg line_x, point_x, point_y, primitive_id;
785
786 /**
787 * Instance ID, which comes in before the vertex attribute payload if
788 * the shader record requests it.
789 */
790 struct qreg iid;
791
792 /**
793 * Base Instance ID, which comes in before the vertex attribute payload
794 * (after Instance ID) if the shader record requests it.
795 */
796 struct qreg biid;
797
798 /**
799 * Vertex ID, which comes in before the vertex attribute payload
800 * (after Base Instance) if the shader record requests it.
801 */
802 struct qreg vid;
803
804 /* Fragment shader payload regs. */
805 struct qreg payload_w, payload_w_centroid, payload_z;
806
807 struct qreg cs_payload[2];
808 struct qreg cs_shared_offset;
809 int local_invocation_index_bits;
810
811 /* Starting value of the sample mask in a fragment shader. We use
812 * this to identify lanes that have been terminated/discarded.
813 */
814 struct qreg start_msf;
815
816 /* If the shader uses subgroup functionality */
817 bool has_subgroups;
818
819 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
820 uint32_t vpm_output_size;
821
822 /* Size in bytes of registers that have been spilled. This is how much
823 * space needs to be available in the spill BO per thread per QPU.
824 */
825 uint32_t spill_size;
826 /* Shader-db stats */
827 uint32_t spills, fills, loops;
828
829 /* Whether we are in the process of spilling registers for
830 * register allocation
831 */
832 bool spilling;
833
834 /**
835 * Register spilling's per-thread base address, shared between each
836 * spill/fill's addressing calculations (also used for scratch
837 * access).
838 */
839 struct qreg spill_base;
840
841 /* Bit vector of which temps may be spilled */
842 BITSET_WORD *spillable;
843
844 /* Used during register allocation */
845 int thread_index;
846 struct v3d_ra_node_info nodes;
847 struct ra_graph *g;
848
849 /**
850 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
851 *
852 * This includes those that aren't part of the VPM varyings, like
853 * point/line coordinates.
854 */
855 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
856
857 /**
858 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
859 * of the output is. Used to emit from the VS in the order that the
860 * FS needs.
861 */
862 struct v3d_varying_slot *output_slots;
863
864 struct pipe_shader_state *shader_state;
865 struct v3d_key *key;
866 struct v3d_fs_key *fs_key;
867 struct v3d_gs_key *gs_key;
868 struct v3d_vs_key *vs_key;
869
870 /* Live ranges of temps. */
871 int *temp_start, *temp_end;
872 bool live_intervals_valid;
873
874 uint32_t *uniform_data;
875 enum quniform_contents *uniform_contents;
876 uint32_t uniform_array_size;
877 uint32_t num_uniforms;
878 uint32_t output_position_index;
879 nir_variable *output_color_var[V3D_MAX_DRAW_BUFFERS];
880 uint32_t output_sample_mask_index;
881
882 struct qreg undef;
883 uint32_t num_temps;
884 /* Number of temps in the program right before we spill a new temp. We
885 * use this to know which temps existed before a spill and which were
886 * added with the spill itself.
887 */
888 uint32_t spill_start_num_temps;
889
890 struct vir_cursor cursor;
891 struct list_head blocks;
892 int next_block_index;
893 struct qblock *cur_block;
894 struct qblock *loop_cont_block;
895 struct qblock *loop_break_block;
896 /**
897 * Which temp, if any, do we currently have in the flags?
898 * This is set when processing a comparison instruction, and
899 * reset to -1 by anything else that touches the flags.
900 */
901 int32_t flags_temp;
902 enum v3d_qpu_cond flags_cond;
903
904 uint64_t *qpu_insts;
905 uint32_t qpu_inst_count;
906 uint32_t qpu_inst_size;
907 uint32_t qpu_inst_stalled_count;
908 uint32_t nop_count;
909
910 /* For the FS, the number of varying inputs not counting the
911 * point/line varyings payload
912 */
913 uint32_t num_inputs;
914
915 uint32_t program_id;
916 uint32_t variant_id;
917
918 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
919 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
920 * limiting ourselves to the part of the physical reg space.
921 *
922 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
923 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
924 * physical reg space in half.
925 */
926 uint8_t threads;
927 struct qinst *last_thrsw;
928 bool last_thrsw_at_top_level;
929
930 bool emitted_tlb_load;
931 bool lock_scoreboard_on_first_thrsw;
932
933 enum v3d_compilation_result compilation_result;
934
935 bool tmu_dirty_rcl;
936 bool has_global_address;
937
938 /* If we have processed a discard/terminate instruction. This may
939 * cause some lanes to be inactive even during uniform control
940 * flow.
941 */
942 bool emitted_discard;
943 };
944
945 struct v3d_uniform_list {
946 enum quniform_contents *contents;
947 uint32_t *data;
948 uint32_t count;
949 };
950
951 struct v3d_prog_data {
952 struct v3d_uniform_list uniforms;
953
954 uint32_t spill_size;
955 uint32_t tmu_spills;
956 uint32_t tmu_fills;
957 uint32_t tmu_count;
958
959 uint32_t qpu_read_stalls;
960
961 uint8_t compile_strategy_idx;
962
963 uint8_t threads;
964
965 /* For threads > 1, whether the program should be dispatched in the
966 * after-final-THRSW state.
967 */
968 bool single_seg;
969
970 bool tmu_dirty_rcl;
971
972 bool has_control_barrier;
973
974 bool has_global_address;
975 };
976
977 struct v3d_vs_prog_data {
978 struct v3d_prog_data base;
979
980 bool uses_iid, uses_biid, uses_vid;
981
982 /* Number of components read from each vertex attribute. */
983 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
984
985 /* Total number of components read, for the shader state record. */
986 uint32_t vpm_input_size;
987
988 /* Total number of components written, for the shader state record. */
989 uint32_t vpm_output_size;
990
991 /* Set if there should be separate VPM segments for input and output.
992 * If unset, vpm_input_size will be 0.
993 */
994 bool separate_segments;
995
996 /* Value to be programmed in VCM_CACHE_SIZE. */
997 uint8_t vcm_cache_size;
998
999 bool writes_psiz;
1000
1001 /* Maps the nir->data.location to its
1002 * nir->data.driver_location. In general we are using the
1003 * driver location as index (like vattr_sizes above), so this
1004 * map is useful when what we have is the location
1005 *
1006 * Returns -1 if the location is not used
1007 */
1008 int32_t driver_location_map[V3D_MAX_VS_INPUTS];
1009 };
1010
1011 struct v3d_gs_prog_data {
1012 struct v3d_prog_data base;
1013
1014 /* Whether the program reads gl_PrimitiveIDIn */
1015 bool uses_pid;
1016
1017 /* Number of components read from each input varying. */
1018 uint8_t input_sizes[V3D_MAX_GS_INPUTS / 4];
1019
1020 /* Number of inputs */
1021 uint8_t num_inputs;
1022 struct v3d_varying_slot input_slots[V3D_MAX_GS_INPUTS];
1023
1024 /* Total number of components written, for the shader state record. */
1025 uint32_t vpm_output_size;
1026
1027 /* Maximum SIMD dispatch width to not exceed VPM output size limits
1028 * in the geometry shader. Notice that the final dispatch width has to
1029 * be decided at draw time and could be lower based on the VPM pressure
1030 * added by other shader stages.
1031 */
1032 uint8_t simd_width;
1033
1034 /* Output primitive type */
1035 uint8_t out_prim_type;
1036
1037 /* Number of GS invocations */
1038 uint8_t num_invocations;
1039
1040 bool writes_psiz;
1041 };
1042
1043 struct v3d_fs_prog_data {
1044 struct v3d_prog_data base;
1045
1046 /* Whether the program reads gl_PrimitiveID */
1047 bool uses_pid;
1048
1049 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
1050
1051 /* Array of flat shade flags.
1052 *
1053 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
1054 * packet layout.
1055 */
1056 uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
1057
1058 uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
1059
1060 uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
1061
1062 uint8_t num_inputs;
1063 bool writes_z;
1064 bool writes_z_from_fep;
1065 bool disable_ez;
1066 bool uses_center_w;
1067 bool uses_implicit_point_line_varyings;
1068 bool lock_scoreboard_on_first_thrsw;
1069
1070 /* If the fragment shader does anything that requires to force
1071 * per-sample MSAA, such as reading gl_SampleID.
1072 */
1073 bool force_per_sample_msaa;
1074 };
1075
1076 struct v3d_compute_prog_data {
1077 struct v3d_prog_data base;
1078 /* Size in bytes of the workgroup's shared space. */
1079 uint32_t shared_size;
1080 uint16_t local_size[3];
1081 /* If the shader uses subgroup functionality */
1082 bool has_subgroups;
1083 };
1084
1085 struct vpm_config {
1086 uint32_t As;
1087 uint32_t Vc;
1088 uint32_t Gs;
1089 uint32_t Gd;
1090 uint32_t Gv;
1091 uint32_t Ve;
1092 uint32_t gs_width;
1093 };
1094
1095 bool
1096 v3d_compute_vpm_config(struct v3d_device_info *devinfo,
1097 struct v3d_vs_prog_data *vs_bin,
1098 struct v3d_vs_prog_data *vs,
1099 struct v3d_gs_prog_data *gs_bin,
1100 struct v3d_gs_prog_data *gs,
1101 struct vpm_config *vpm_cfg_bin,
1102 struct vpm_config *vpm_cfg);
1103 void
1104 v3d_pack_unnormalized_coordinates(struct v3d_device_info *devinfo,
1105 uint32_t *p1_packed,
1106 bool unnormalized_coordinates);
1107
1108 static inline bool
vir_has_uniform(struct qinst * inst)1109 vir_has_uniform(struct qinst *inst)
1110 {
1111 return inst->uniform != ~0;
1112 }
1113
1114 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo,
1115 uint32_t max_inline_uniform_buffers);
1116 void v3d_compiler_free(const struct v3d_compiler *compiler);
1117 void v3d_optimize_nir(struct v3d_compile *c, struct nir_shader *s);
1118
1119 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
1120 struct v3d_key *key,
1121 struct v3d_prog_data **prog_data,
1122 nir_shader *s,
1123 void (*debug_output)(const char *msg,
1124 void *debug_output_data),
1125 void *debug_output_data,
1126 int program_id, int variant_id,
1127 uint32_t *final_assembly_size);
1128
1129 uint32_t v3d_prog_data_size(gl_shader_stage stage);
1130 void v3d_nir_to_vir(struct v3d_compile *c);
1131
1132 void vir_compile_destroy(struct v3d_compile *c);
1133 const char *vir_get_stage_name(struct v3d_compile *c);
1134 struct qblock *vir_new_block(struct v3d_compile *c);
1135 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
1136 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
1137 struct qblock *vir_entry_block(struct v3d_compile *c);
1138 struct qblock *vir_exit_block(struct v3d_compile *c);
1139 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
1140 struct qreg src0, struct qreg src1);
1141 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
1142 struct qreg src0, struct qreg src1);
1143 struct qinst *vir_branch_inst(struct v3d_compile *c,
1144 enum v3d_qpu_branch_cond cond);
1145 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
1146 uint32_t vir_get_uniform_index(struct v3d_compile *c,
1147 enum quniform_contents contents,
1148 uint32_t data);
1149 struct qreg vir_uniform(struct v3d_compile *c,
1150 enum quniform_contents contents,
1151 uint32_t data);
1152 void vir_schedule_instructions(struct v3d_compile *c);
1153 void v3d_setup_spill_base(struct v3d_compile *c);
1154 struct v3d_qpu_instr v3d_qpu_nop(void);
1155
1156 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
1157 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
1158 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
1159 enum v3d_qpu_cond vir_get_cond(struct qinst *inst);
1160 void vir_set_pf(struct v3d_compile *c, struct qinst *inst, enum v3d_qpu_pf pf);
1161 void vir_set_uf(struct v3d_compile *c, struct qinst *inst, enum v3d_qpu_uf uf);
1162 void vir_set_unpack(struct qinst *inst, int src,
1163 enum v3d_qpu_input_unpack unpack);
1164 void vir_set_pack(struct qinst *inst, enum v3d_qpu_output_pack pack);
1165
1166 struct qreg vir_get_temp(struct v3d_compile *c);
1167 void vir_calculate_live_intervals(struct v3d_compile *c);
1168 int vir_get_nsrc(struct qinst *inst);
1169 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
1170 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
1171 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
1172 bool vir_is_raw_mov(struct qinst *inst);
1173 bool vir_is_tex(const struct v3d_device_info *devinfo, struct qinst *inst);
1174 bool vir_is_add(struct qinst *inst);
1175 bool vir_is_mul(struct qinst *inst);
1176 bool vir_writes_r4_implicitly(const struct v3d_device_info *devinfo, struct qinst *inst);
1177 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
1178 uint8_t vir_channels_written(struct qinst *inst);
1179 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
1180 void ntq_store_def(struct v3d_compile *c, nir_def *def, int chan,
1181 struct qreg result);
1182 bool ntq_tmu_fifo_overflow(struct v3d_compile *c, uint32_t components);
1183 void ntq_add_pending_tmu_flush(struct v3d_compile *c, nir_def *def,
1184 uint32_t component_mask);
1185 void ntq_flush_tmu(struct v3d_compile *c);
1186 void vir_emit_thrsw(struct v3d_compile *c);
1187
1188 void vir_dump(struct v3d_compile *c);
1189 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
1190 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
1191
1192 void vir_validate(struct v3d_compile *c);
1193
1194 void vir_optimize(struct v3d_compile *c);
1195 bool vir_opt_algebraic(struct v3d_compile *c);
1196 bool vir_opt_constant_folding(struct v3d_compile *c);
1197 bool vir_opt_copy_propagate(struct v3d_compile *c);
1198 bool vir_opt_dead_code(struct v3d_compile *c);
1199 bool vir_opt_peephole_sf(struct v3d_compile *c);
1200 bool vir_opt_redundant_flags(struct v3d_compile *c);
1201 bool vir_opt_small_immediates(struct v3d_compile *c);
1202 bool vir_opt_vpm(struct v3d_compile *c);
1203 bool vir_opt_constant_alu(struct v3d_compile *c);
1204 bool v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
1205 bool v3d_nir_lower_line_smooth(nir_shader *shader);
1206 bool v3d_nir_lower_logic_ops(nir_shader *s, struct v3d_compile *c);
1207 bool v3d_nir_lower_scratch(nir_shader *s);
1208 bool v3d_nir_lower_txf_ms(nir_shader *s);
1209 bool v3d_nir_lower_image_load_store(nir_shader *s, struct v3d_compile *c);
1210 bool v3d_nir_lower_global_2x32(nir_shader *s);
1211 bool v3d_nir_lower_load_store_bitsize(nir_shader *s);
1212 bool v3d_nir_lower_algebraic(struct nir_shader *shader);
1213
1214 void v3d_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
1215 void v3d_vir_emit_image_load_store(struct v3d_compile *c,
1216 nir_intrinsic_instr *instr);
1217
1218 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
1219 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
1220 void qpu_validate(struct v3d_compile *c);
1221 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c);
1222 bool vir_init_reg_sets(struct v3d_compiler *compiler);
1223
1224 int v3d_shaderdb_dump(struct v3d_compile *c, char **shaderdb_str);
1225
1226 bool v3d_gl_format_is_return_32(enum pipe_format format);
1227
1228 uint32_t
1229 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src);
1230
1231 static inline bool
quniform_contents_is_texture_p0(enum quniform_contents contents)1232 quniform_contents_is_texture_p0(enum quniform_contents contents)
1233 {
1234 return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
1235 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
1236 V3D_MAX_TEXTURE_SAMPLERS));
1237 }
1238
1239 static inline bool
vir_in_nonuniform_control_flow(struct v3d_compile * c)1240 vir_in_nonuniform_control_flow(struct v3d_compile *c)
1241 {
1242 return c->execute.file != QFILE_NULL;
1243 }
1244
1245 static inline struct qreg
vir_uniform_ui(struct v3d_compile * c,uint32_t ui)1246 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
1247 {
1248 return vir_uniform(c, QUNIFORM_CONSTANT, ui);
1249 }
1250
1251 static inline struct qreg
vir_uniform_f(struct v3d_compile * c,float f)1252 vir_uniform_f(struct v3d_compile *c, float f)
1253 {
1254 return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
1255 }
1256
1257 #define VIR_ALU0(name, vir_inst, op) \
1258 static inline struct qreg \
1259 vir_##name(struct v3d_compile *c) \
1260 { \
1261 return vir_emit_def(c, vir_inst(op, c->undef, \
1262 c->undef, c->undef)); \
1263 } \
1264 static inline struct qinst * \
1265 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
1266 { \
1267 return vir_emit_nondef(c, vir_inst(op, dest, \
1268 c->undef, c->undef)); \
1269 }
1270
1271 #define VIR_ALU1(name, vir_inst, op) \
1272 static inline struct qreg \
1273 vir_##name(struct v3d_compile *c, struct qreg a) \
1274 { \
1275 return vir_emit_def(c, vir_inst(op, c->undef, \
1276 a, c->undef)); \
1277 } \
1278 static inline struct qinst * \
1279 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1280 struct qreg a) \
1281 { \
1282 return vir_emit_nondef(c, vir_inst(op, dest, a, \
1283 c->undef)); \
1284 }
1285
1286 #define VIR_ALU2(name, vir_inst, op) \
1287 static inline struct qreg \
1288 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1289 { \
1290 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
1291 } \
1292 static inline struct qinst * \
1293 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1294 struct qreg a, struct qreg b) \
1295 { \
1296 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
1297 }
1298
1299 #define VIR_NODST_0(name, vir_inst, op) \
1300 static inline struct qinst * \
1301 vir_##name(struct v3d_compile *c) \
1302 { \
1303 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1304 c->undef, c->undef)); \
1305 }
1306
1307 #define VIR_NODST_1(name, vir_inst, op) \
1308 static inline struct qinst * \
1309 vir_##name(struct v3d_compile *c, struct qreg a) \
1310 { \
1311 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1312 a, c->undef)); \
1313 }
1314
1315 #define VIR_NODST_2(name, vir_inst, op) \
1316 static inline struct qinst * \
1317 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1318 { \
1319 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1320 a, b)); \
1321 }
1322
1323 #define VIR_SFU(name) \
1324 static inline struct qreg \
1325 vir_##name(struct v3d_compile *c, struct qreg a) \
1326 { \
1327 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
1328 c->undef, \
1329 a, c->undef)); \
1330 } \
1331 static inline struct qinst * \
1332 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1333 struct qreg a) \
1334 { \
1335 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
1336 dest, \
1337 a, c->undef)); \
1338 }
1339
1340 #define VIR_SFU2(name) \
1341 static inline struct qreg \
1342 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1343 { \
1344 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
1345 c->undef, \
1346 a, b)); \
1347 } \
1348 static inline struct qinst * \
1349 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1350 struct qreg a, struct qreg b) \
1351 { \
1352 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
1353 dest, \
1354 a, b)); \
1355 }
1356
1357 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
1358 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
1359 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
1360 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
1361 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
1362 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
1363 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
1364 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
1365 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
1366 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
1367 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
1368
1369 VIR_A_ALU2(FADD)
VIR_A_ALU2(VFPACK)1370 VIR_A_ALU2(VFPACK)
1371 VIR_A_ALU2(FSUB)
1372 VIR_A_ALU2(FMIN)
1373 VIR_A_ALU2(FMAX)
1374
1375 VIR_A_ALU2(ADD)
1376 VIR_A_ALU2(SUB)
1377 VIR_A_ALU2(SHL)
1378 VIR_A_ALU2(SHR)
1379 VIR_A_ALU2(ASR)
1380 VIR_A_ALU2(ROR)
1381 VIR_A_ALU2(MIN)
1382 VIR_A_ALU2(MAX)
1383 VIR_A_ALU2(UMIN)
1384 VIR_A_ALU2(UMAX)
1385 VIR_A_ALU2(AND)
1386 VIR_A_ALU2(OR)
1387 VIR_A_ALU2(XOR)
1388 VIR_A_ALU2(VADD)
1389 VIR_A_ALU2(VSUB)
1390 VIR_A_NODST_2(STVPMV)
1391 VIR_A_NODST_2(STVPMD)
1392 VIR_A_ALU1(NOT)
1393 VIR_A_ALU1(NEG)
1394 VIR_A_ALU1(FLAPUSH)
1395 VIR_A_ALU1(FLBPUSH)
1396 VIR_A_ALU1(FLPOP)
1397 VIR_A_ALU0(FLAFIRST)
1398 VIR_A_ALU0(FLNAFIRST)
1399 VIR_A_ALU1(SETMSF)
1400 VIR_A_ALU1(SETREVF)
1401 VIR_A_ALU0(TIDX)
1402 VIR_A_ALU0(EIDX)
1403 VIR_A_ALU1(LDVPMV_IN)
1404 VIR_A_ALU1(LDVPMV_OUT)
1405 VIR_A_ALU1(LDVPMD_IN)
1406 VIR_A_ALU1(LDVPMD_OUT)
1407 VIR_A_ALU2(LDVPMG_IN)
1408 VIR_A_ALU2(LDVPMG_OUT)
1409 VIR_A_ALU0(TMUWT)
1410
1411 VIR_A_ALU0(IID)
1412 VIR_A_ALU0(FXCD)
1413 VIR_A_ALU0(XCD)
1414 VIR_A_ALU0(FYCD)
1415 VIR_A_ALU0(YCD)
1416 VIR_A_ALU0(MSF)
1417 VIR_A_ALU0(REVF)
1418 VIR_A_ALU0(BARRIERID)
1419 VIR_A_ALU0(SAMPID)
1420 VIR_A_NODST_1(VPMSETUP)
1421 VIR_A_NODST_0(VPMWT)
1422 VIR_A_ALU2(FCMP)
1423 VIR_A_ALU2(VFMAX)
1424
1425 VIR_A_ALU1(FROUND)
1426 VIR_A_ALU1(FTOIN)
1427 VIR_A_ALU1(FTRUNC)
1428 VIR_A_ALU1(FTOIZ)
1429 VIR_A_ALU1(FFLOOR)
1430 VIR_A_ALU1(FTOUZ)
1431 VIR_A_ALU1(FCEIL)
1432 VIR_A_ALU1(FTOC)
1433
1434 VIR_A_ALU1(FDX)
1435 VIR_A_ALU1(FDY)
1436
1437 VIR_A_ALU1(ITOF)
1438 VIR_A_ALU1(CLZ)
1439 VIR_A_ALU1(UTOF)
1440
1441 VIR_M_ALU2(UMUL24)
1442 VIR_M_ALU2(FMUL)
1443 VIR_M_ALU2(SMUL24)
1444 VIR_M_NODST_2(MULTOP)
1445
1446 VIR_M_ALU1(MOV)
1447 VIR_M_ALU1(FMOV)
1448
1449 VIR_SFU(RECIP)
1450 VIR_SFU(RSQRT)
1451 VIR_SFU(EXP)
1452 VIR_SFU(LOG)
1453 VIR_SFU(SIN)
1454 VIR_SFU(RSQRT2)
1455
1456 VIR_SFU(BALLOT)
1457 VIR_SFU(BCASTF)
1458 VIR_SFU(ALLEQ)
1459 VIR_SFU(ALLFEQ)
1460 VIR_SFU2(ROTQ)
1461 VIR_SFU2(ROT)
1462 VIR_SFU2(SHUFFLE)
1463
1464 VIR_A_ALU2(VPACK)
1465 VIR_A_ALU2(V8PACK)
1466 VIR_A_ALU2(V10PACK)
1467 VIR_A_ALU2(V11FPACK)
1468
1469 VIR_M_ALU1(FTOUNORM16)
1470 VIR_M_ALU1(FTOSNORM16)
1471
1472 VIR_M_ALU1(VFTOUNORM8)
1473 VIR_M_ALU1(VFTOSNORM8)
1474
1475 VIR_M_ALU1(VFTOUNORM10LO)
1476 VIR_M_ALU1(VFTOUNORM10HI)
1477
1478 static inline struct qinst *
1479 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1480 struct qreg dest, struct qreg src)
1481 {
1482 struct qinst *mov = vir_MOV_dest(c, dest, src);
1483 vir_set_cond(mov, cond);
1484 return mov;
1485 }
1486
1487 static inline struct qreg
vir_SEL(struct v3d_compile * c,enum v3d_qpu_cond cond,struct qreg src0,struct qreg src1)1488 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1489 struct qreg src0, struct qreg src1)
1490 {
1491 struct qreg t = vir_get_temp(c);
1492 vir_MOV_dest(c, t, src1);
1493 vir_MOV_cond(c, cond, t, src0);
1494 return t;
1495 }
1496
1497 static inline struct qinst *
vir_NOP(struct v3d_compile * c)1498 vir_NOP(struct v3d_compile *c)
1499 {
1500 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1501 c->undef, c->undef, c->undef));
1502 }
1503
1504 static inline struct qreg
vir_LDTMU(struct v3d_compile * c)1505 vir_LDTMU(struct v3d_compile *c)
1506 {
1507 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1508 c->undef, c->undef);
1509 ldtmu->qpu.sig.ldtmu = true;
1510
1511 return vir_emit_def(c, ldtmu);
1512 }
1513
1514 static inline struct qreg
vir_UMUL(struct v3d_compile * c,struct qreg src0,struct qreg src1)1515 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1516 {
1517 vir_MULTOP(c, src0, src1);
1518 return vir_UMUL24(c, src0, src1);
1519 }
1520
1521 static inline struct qreg
vir_TLBU_COLOR_READ(struct v3d_compile * c,uint32_t config)1522 vir_TLBU_COLOR_READ(struct v3d_compile *c, uint32_t config)
1523 {
1524 assert((config & 0xffffff00) == 0xffffff00);
1525
1526 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1527 c->undef, c->undef);
1528 ldtlb->qpu.sig.ldtlbu = true;
1529 ldtlb->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, config);
1530 return vir_emit_def(c, ldtlb);
1531 }
1532
1533 static inline struct qreg
vir_TLB_COLOR_READ(struct v3d_compile * c)1534 vir_TLB_COLOR_READ(struct v3d_compile *c)
1535 {
1536 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1537 c->undef, c->undef);
1538 ldtlb->qpu.sig.ldtlb = true;
1539 return vir_emit_def(c, ldtlb);
1540 }
1541
1542 static inline struct qinst *
vir_BRANCH(struct v3d_compile * c,enum v3d_qpu_branch_cond cond)1543 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1544 {
1545 /* The actual uniform_data value will be set at scheduling time */
1546 return vir_emit_nondef(c, vir_branch_inst(c, cond));
1547 }
1548
1549 #define vir_for_each_block(block, c) \
1550 list_for_each_entry(struct qblock, block, &c->blocks, link)
1551
1552 #define vir_for_each_block_rev(block, c) \
1553 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1554
1555 /* Loop over the non-NULL members of the successors array. */
1556 #define vir_for_each_successor(succ, block) \
1557 for (struct qblock *succ = block->successors[0]; \
1558 succ != NULL; \
1559 succ = (succ == block->successors[1] ? NULL : \
1560 block->successors[1]))
1561
1562 #define vir_for_each_inst(inst, block) \
1563 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1564
1565 #define vir_for_each_inst_rev(inst, block) \
1566 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1567
1568 #define vir_for_each_inst_safe(inst, block) \
1569 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1570
1571 #define vir_for_each_inst_inorder(inst, c) \
1572 vir_for_each_block(_block, c) \
1573 vir_for_each_inst(inst, _block)
1574
1575 #define vir_for_each_inst_inorder_safe(inst, c) \
1576 vir_for_each_block(_block, c) \
1577 vir_for_each_inst_safe(inst, _block)
1578
1579 #endif /* V3D_COMPILER_H */
1580