1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <acpi/acpi.h>
4 #include <acpi/acpigen.h>
5 #include <assert.h>
6 #include <commonlib/bsd/helpers.h>
7 #include <console/console.h>
8 #include <device/pci_def.h>
9 #include <intelblocks/acpi.h>
10 #include <intelblocks/pmc_ipc.h>
11 #include <stdlib.h>
12 #include <string.h>
13 #include <types.h>
14
15 #define LPI_S0_HELPER_UUID "c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"
16 #define PEP_S0IX_UUID "57a6512e-3979-4e9d-9708-ff13b2508972"
17 #define SYSTEM_POWER_MANAGEMENT_HID "INT33A1"
18 #define SYSTEM_POWER_MANAGEMENT_CID "PNP0D80"
19 #define EC_S0IX_HOOK "\\_SB.PCI0.LPCB.EC0.S0IX"
20 #define EC_DISPLAY_HOOK "\\_SB.PCI0.LPCB.EC0.EDSX"
21 #define MAINBOARD_HOOK "\\_SB.MS0X"
22 #define MAINBOARD_DISPLAY_HOOK "\\_SB.MDSX"
23 #define ENABLE_PM_BITS_HOOK "\\_SB.PCI0.EGPM"
24 #define RESTORE_PM_BITS_HOOK "\\_SB.PCI0.RGPM"
25 #define THUNDERBOLT_DEVICE "\\_SB.PCI0.TXHC"
26 #define THUNDERBOLT_IOM_DPOF "\\_SB.PCI0.DPOF"
27 #define PEPD_SCOPE "\\_SB.PCI0"
28
29 #define MIN_DEVICE_STATE ACPI_DEVICE_SLEEP_D0
30 #define LPI_STATES_ALL 0xff
31
32 enum {
33 LPI_REVISION_0 = 0,
34 };
35
36 enum {
37 LPI_DISABLED = 0,
38 LPI_ENABLED = 1,
39 };
40
41 struct reg_info {
42 uint8_t *addr;
43 size_t buffer_size;
44 };
45
read_pmc_lpm_requirements(const struct soc_pmc_lpm * lpm,struct reg_info * info)46 static void read_pmc_lpm_requirements(const struct soc_pmc_lpm *lpm,
47 struct reg_info *info)
48 {
49 assert(info);
50
51 if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ) || !lpm) {
52 memset(info, 0, sizeof(*info));
53 return;
54 }
55
56 const size_t register_count = lpm->num_substates * lpm->num_req_regs;
57 uint32_t *reg = calloc(register_count, sizeof(uint32_t));
58
59 /* Read the various LPM state requirement registers from the PMC */
60 for (size_t i = 0; i < lpm->num_substates; i++) {
61 if (!(lpm->lpm_enable_mask & BIT(i)))
62 continue;
63
64 for (size_t j = 0; j < lpm->num_req_regs; j++) {
65 const uint32_t offset = lpm->lpm_ipc_offset +
66 i * lpm->req_reg_stride +
67 j * sizeof(uint32_t);
68 const uint32_t cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_RD_PMC_REG,
69 PMC_IPC_CMD_SUBCMD_RD_PMC_REG, 0);
70 struct pmc_ipc_buffer req = {.buf[0] = offset};
71 struct pmc_ipc_buffer res = {};
72
73 enum cb_err result = pmc_send_ipc_cmd(cmd_reg, &req, &res);
74 if (result != CB_SUCCESS) {
75 printk(BIOS_ERR, "Failed to retrieve LPM substate registers"
76 "from LPM, substate %zu, reg %zu\n", i, j);
77 }
78
79 uint32_t *ptr = reg + i * lpm->num_req_regs + j;
80 *ptr = res.buf[0];
81 }
82 }
83
84 info->addr = (uint8_t *)reg;
85 info->buffer_size = register_count * sizeof(uint32_t);
86 }
87
88 /*
89 * Windows expects a non-empty package for this subfunction, otherwise it
90 * results in a bluescreen (`INTERNAL_POWER_ERROR`); returning an empty package
91 * does not work. To workaround this, return a package describing a single
92 * device, one that is known to exist, i.e. ACPI_CPU_STRING. expects at least
93 * one device and crashes without it with a bluescreen.
94 */
acpi_gen_default_lpi_constraints(void)95 static void acpi_gen_default_lpi_constraints(void)
96 {
97 printk(BIOS_INFO, "Returning default LPI constraint package\n");
98
99 /*
100 * Return (Package() {
101 * Package() { "\_SB.CP00", 0,
102 * Package() { 0,
103 * Package() { 0xff, 0 }}}})
104 */
105 acpigen_emit_byte(RETURN_OP);
106 acpigen_write_package(1);
107 {
108 acpigen_write_package(3);
109 {
110 acpigen_write_processor_namestring(0);
111 acpigen_write_integer(0); /* device disabled */
112 acpigen_write_package(2);
113 {
114 acpigen_write_integer(0); /* revision */
115 acpigen_write_package(2);
116 {
117 acpigen_write_integer(LPI_STATES_ALL);
118 acpigen_write_integer(MIN_DEVICE_STATE);
119 }
120 acpigen_write_package_end();
121 }
122 acpigen_write_package_end();
123 }
124 acpigen_write_package_end();
125 }
126 acpigen_write_package_end();
127 }
128
soc_get_min_sleep_state_array(size_t * size)129 __weak struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size)
130 {
131 printk(BIOS_DEBUG, "Empty min sleep state array returned\n");
132 *size = 0;
133 return NULL;
134 }
135
get_min_sleep_state(const struct device * dev,struct min_sleep_state * states_arr,size_t size)136 static enum acpi_device_sleep_states get_min_sleep_state(
137 const struct device *dev, struct min_sleep_state *states_arr, size_t size)
138 {
139 if (!is_dev_enabled(dev))
140 return ACPI_DEVICE_SLEEP_NONE;
141 switch (dev->path.type) {
142 case DEVICE_PATH_APIC:
143 return MIN_DEVICE_STATE;
144
145 case DEVICE_PATH_PCI:
146 /* skip external buses*/
147 if ((dev->upstream->secondary != 0) || (!states_arr))
148 return ACPI_DEVICE_SLEEP_NONE;
149 for (size_t i = 0; i < size; i++)
150 if (states_arr[i].pci_dev == dev->path.pci.devfn)
151 return states_arr[i].min_sleep_state;
152 printk(BIOS_WARNING, "Unknown min d_state for PCI: 00:%02x.%01x\n",
153 PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
154 return ACPI_DEVICE_SLEEP_NONE;
155
156 default:
157 return ACPI_DEVICE_SLEEP_NONE;
158 }
159 }
160
161 /* Generate the LPI constraint table */
acpi_lpi_get_constraints(void * unused)162 static void acpi_lpi_get_constraints(void *unused)
163 {
164 unsigned int num_entries = 0;
165 const struct device *dev;
166 enum acpi_device_sleep_states min_sleep_state;
167 size_t size;
168 struct min_sleep_state *states_arr = soc_get_min_sleep_state_array(&size);
169
170 if (size && states_arr) {
171 for (dev = all_devices; dev; dev = dev->next) {
172 if (!dev->enabled || dev->hidden)
173 continue;
174 if (get_min_sleep_state(dev, states_arr, size)
175 != ACPI_DEVICE_SLEEP_NONE)
176 num_entries++;
177 }
178 }
179 if (!num_entries) {
180 acpi_gen_default_lpi_constraints();
181 } else {
182 acpigen_emit_byte(RETURN_OP);
183 acpigen_write_package(num_entries);
184
185 size_t cpu_index = 0;
186 for (dev = all_devices; dev; dev = dev->next) {
187 if (!dev->enabled || dev->hidden)
188 continue;
189 min_sleep_state = get_min_sleep_state(dev, states_arr, size);
190 if (min_sleep_state == ACPI_DEVICE_SLEEP_NONE)
191 continue;
192
193 acpigen_write_package(3);
194 {
195 /* Emit the device path */
196 switch (dev->path.type) {
197 case DEVICE_PATH_PCI:
198 acpigen_emit_namestring(acpi_device_path(dev));
199 break;
200
201 case DEVICE_PATH_APIC:
202 acpigen_write_processor_namestring(cpu_index++);
203 break;
204
205 default:
206 /* Unhandled */
207 printk(BIOS_WARNING,
208 "Unhandled device path type %d\n",
209 dev->path.type);
210 acpigen_emit_namestring(NULL);
211 break;
212 }
213
214 acpigen_write_integer(LPI_ENABLED);
215 acpigen_write_package(2);
216 {
217 acpigen_write_integer(LPI_REVISION_0);
218 acpigen_write_package(2); /* no optional device info */
219 {
220 /* Assume constraints apply to all entries */
221 acpigen_write_integer(LPI_STATES_ALL);
222 /* min D-state */
223 acpigen_write_integer(min_sleep_state);
224 }
225 acpigen_write_package_end();
226 }
227 acpigen_write_package_end();
228 }
229 acpigen_write_package_end();
230 }
231 acpigen_write_package_end();
232 }
233 }
234
lpi_s0ix_entry(void * unused)235 static void lpi_s0ix_entry(void *unused)
236 {
237 /* Inform the EC */
238 acpigen_write_if_cond_ref_of(EC_S0IX_HOOK);
239 acpigen_emit_namestring(EC_S0IX_HOOK);
240 acpigen_write_integer(1);
241 acpigen_write_if_end();
242
243 /* Provide a board level S0ix hook */
244 acpigen_write_if_cond_ref_of(MAINBOARD_HOOK);
245 acpigen_emit_namestring(MAINBOARD_HOOK);
246 acpigen_write_integer(1);
247 acpigen_write_if_end();
248
249 /* Save the current PM bits then enable GPIO PM with
250 MISCCFG_GPIO_PM_CONFIG_BITS */
251 acpigen_write_if_cond_ref_of(ENABLE_PM_BITS_HOOK);
252 acpigen_emit_namestring(ENABLE_PM_BITS_HOOK);
253 acpigen_write_if_end();
254
255 /* Handle Thunderbolt displays */
256 if (CONFIG(FIRMWARE_CONNECTION_MANAGER)) {
257 acpigen_write_if_cond_ref_of(THUNDERBOLT_DEVICE);
258 acpigen_write_store_int_to_namestr(1, THUNDERBOLT_IOM_DPOF);
259 acpigen_write_if_end();
260 }
261 }
262
lpi_s0ix_exit(void * unused)263 static void lpi_s0ix_exit(void *unused)
264 {
265 /* Inform the EC */
266 acpigen_write_if_cond_ref_of(EC_S0IX_HOOK);
267 acpigen_emit_namestring(EC_S0IX_HOOK);
268 acpigen_write_integer(0);
269 acpigen_write_if_end();
270
271 /* Provide a board level S0ix hook */
272 acpigen_write_if_cond_ref_of(MAINBOARD_HOOK);
273 acpigen_emit_namestring(MAINBOARD_HOOK);
274 acpigen_write_integer(0);
275 acpigen_write_if_end();
276
277 /* Restore GPIO all Community PM */
278 acpigen_write_if_cond_ref_of(RESTORE_PM_BITS_HOOK);
279 acpigen_emit_namestring(RESTORE_PM_BITS_HOOK);
280 acpigen_write_if_end();
281
282 /* Handle Thunderbolt displays */
283 if (CONFIG(FIRMWARE_CONNECTION_MANAGER)) {
284 acpigen_write_if_cond_ref_of(THUNDERBOLT_DEVICE);
285 acpigen_write_store_int_to_namestr(0, THUNDERBOLT_IOM_DPOF);
286 acpigen_write_if_end();
287 }
288 }
289
lpi_display_on(void * unused)290 static void lpi_display_on(void *unused)
291 {
292 /* Inform the EC */
293 acpigen_write_if_cond_ref_of(EC_DISPLAY_HOOK);
294 acpigen_emit_namestring(EC_DISPLAY_HOOK);
295 acpigen_write_integer(1);
296 acpigen_write_if_end();
297
298 /* Provide a board level S0ix hook */
299 acpigen_write_if_cond_ref_of(MAINBOARD_DISPLAY_HOOK);
300 acpigen_emit_namestring(MAINBOARD_DISPLAY_HOOK);
301 acpigen_write_integer(1);
302 acpigen_write_if_end();
303 }
304
lpi_display_off(void * unused)305 static void lpi_display_off(void *unused)
306 {
307 /* Inform the EC */
308 acpigen_write_if_cond_ref_of(EC_DISPLAY_HOOK);
309 acpigen_emit_namestring(EC_DISPLAY_HOOK);
310 acpigen_write_integer(0);
311 acpigen_write_if_end();
312
313 /* Provide a board level S0ix hook */
314 acpigen_write_if_cond_ref_of(MAINBOARD_DISPLAY_HOOK);
315 acpigen_emit_namestring(MAINBOARD_DISPLAY_HOOK);
316 acpigen_write_integer(0);
317 acpigen_write_if_end();
318 }
319
320 static void (*lpi_s0_helpers[])(void *) = {
321 NULL, /* enumerate functions (autogenerated) */
322 acpi_lpi_get_constraints,/* get device constraints */
323 NULL, /* get crash dump device */
324 lpi_display_off, /* display off notify */
325 lpi_display_on, /* display on notify */
326 lpi_s0ix_entry, /* s0ix entry */
327 lpi_s0ix_exit, /* s0ix exit */
328 };
329
pep_s0ix_return_lpm_requirements(void * arg)330 static void pep_s0ix_return_lpm_requirements(void *arg)
331 {
332 if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ)) {
333 acpigen_write_return_singleton_buffer(0x0);
334 return;
335 }
336
337 struct reg_info *info = (struct reg_info *)arg;
338 acpigen_write_return_byte_buffer(info->addr, info->buffer_size);
339 }
340
341 static void (*pep_s0ix[])(void *) = {
342 NULL, /* enumerate functions (autogenerated) */
343 pep_s0ix_return_lpm_requirements, /* Return LPM requirements */
344 };
345
generate_acpi_power_engine_with_lpm(const struct soc_pmc_lpm * lpm)346 void generate_acpi_power_engine_with_lpm(const struct soc_pmc_lpm *lpm)
347 {
348 struct reg_info info;
349 size_t uuid_count = 1;
350 struct dsm_uuid ids[] = {
351 DSM_UUID(LPI_S0_HELPER_UUID, lpi_s0_helpers, ARRAY_SIZE(lpi_s0_helpers), NULL),
352 DSM_UUID(PEP_S0IX_UUID, pep_s0ix, ARRAY_SIZE(pep_s0ix), &info),
353 };
354
355 acpigen_write_scope(PEPD_SCOPE);
356 acpigen_write_device("PEPD");
357
358 acpigen_write_name_string("_HID", SYSTEM_POWER_MANAGEMENT_HID);
359 acpigen_write_name("_CID");
360 acpigen_emit_eisaid(SYSTEM_POWER_MANAGEMENT_CID);
361
362 read_pmc_lpm_requirements(lpm, &info);
363 if (info.buffer_size)
364 uuid_count++;
365
366 acpigen_write_dsm_uuid_arr(ids, uuid_count);
367 acpigen_write_device_end();
368 acpigen_write_scope_end();
369
370 free(info.addr);
371 printk(BIOS_INFO, PEPD_SCOPE ".PEPD: Intel Power Engine Plug-in\n");
372 }
373
generate_acpi_power_engine(void)374 void generate_acpi_power_engine(void)
375 {
376 generate_acpi_power_engine_with_lpm(NULL);
377 }
378