1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <variant/variant.h>
4 #include <gpio.h>
5 #include <variant/gpio.h>
6 #include <baseboard/variants.h>
7 #include <string.h>
8
9 /* Use spd_index array to save mem_id */
10 static const int spd_index[32] = {
11 10, 0, 0, 0, 11, 0, 0, 0,
12 0, 0, 0, 0, 9, 0, 0, 0,
13 0, 4, 3, 6, 1, 0, 0, 0,
14 0, 5, 8, 7, 2, 0, 0, 0
15 };
16
get_variant_memory_cfg(struct cnl_mb_cfg * mem_cfg)17 const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg)
18 {
19 int mem_sku;
20 struct cnl_mb_cfg baseboard_memcfg = {
21 /*
22 * The dqs_map arrays map the ddr4 pins to the SoC pins
23 * for both channels.
24 *
25 * the index = pin number on ddr4 part
26 * the value = pin number on SoC
27 */
28 .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 },
29 .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 },
30
31 /* Baseboard uses 120, 81 and 100 rcomp resistors */
32 .rcomp_resistor = { 120, 81, 100 },
33
34 /* Baseboard Rcomp target values */
35 .rcomp_targets = { 100, 40, 20, 20, 26 },
36
37 /* Set CaVref config to 2 */
38 .vref_ca_config = 2,
39
40 /* Enable Early Command Training */
41 .ect = 1,
42 };
43
44 mem_sku = variant_memory_sku();
45
46 memcpy(mem_cfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
47
48 /* In Drallion dual channel is enabled by default.
49 * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, Ch1D1 respectively.
50 * Dual-DIMM memory is not used in drallion family, so we only
51 * fill in spd info for CH0D0 and CH1D0 here.
52 */
53 for (int i = 0; i < 3; i = i+2) {
54 mem_cfg->spd[i].read_type = READ_SPD_CBFS;
55 mem_cfg->spd[i].spd_spec.spd_index = mem_sku;
56 }
57
58 return mem_cfg;
59 }
60
variant_memory_sku(void)61 int variant_memory_sku(void)
62 {
63 gpio_t spd_gpios[] = {
64 GPIO_MEM_CONFIG_0,
65 GPIO_MEM_CONFIG_1,
66 GPIO_MEM_CONFIG_2,
67 GPIO_MEM_CONFIG_3,
68 GPIO_MEM_CONFIG_4,
69 };
70
71 return spd_index[gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))];
72 }
73