1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/pci_ops.h>
8 #include <option.h>
9 #include <pc80/isa-dma.h>
10 #include <pc80/i8259.h>
11 #include <arch/io.h>
12 #include <arch/ioapic.h>
13 #include <acpi/acpi.h>
14 #include <cpu/x86/smm.h>
15 #include "chip.h"
16 #include "iobp.h"
17 #include "pch.h"
18 #include <acpi/acpigen.h>
19 #include <southbridge/intel/common/acpi_pirq_gen.h>
20 #include <southbridge/intel/common/rcba_pirq.h>
21 #include <southbridge/intel/common/rtc.h>
22 #include <southbridge/intel/common/spi.h>
23 #include <types.h>
24
25 #define NMI_OFF 0
26
27 /**
28 * Set miscellaneous static southbridge features.
29 *
30 * @param dev PCI device with I/O APIC control registers
31 */
pch_enable_ioapic(struct device * dev)32 static void pch_enable_ioapic(struct device *dev)
33 {
34 /* Assign unique bus/dev/fn for I/O APIC */
35 pci_write_config16(dev, LPC_IBDF,
36 PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
37
38 /* affirm full set of redirection table entries ("write once") */
39 /* PCH-LP has 40 redirection entries */
40 if (pch_is_lp())
41 ioapic_set_max_vectors(IO_APIC_ADDR, 40);
42 else
43 ioapic_lock_max_vectors(IO_APIC_ADDR);
44
45 register_new_ioapic_gsi0(IO_APIC_ADDR);
46 }
47
pch_enable_serial_irqs(struct device * dev)48 static void pch_enable_serial_irqs(struct device *dev)
49 {
50 /* Set packet length and toggle silent mode bit for one frame. */
51 pci_write_config8(dev, SERIRQ_CNTL,
52 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
53 #if !CONFIG(SERIRQ_CONTINUOUS_MODE)
54 pci_write_config8(dev, SERIRQ_CNTL,
55 (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
56 #endif
57 }
58
enable_hpet(struct device * const dev)59 static void enable_hpet(struct device *const dev)
60 {
61 u32 reg32;
62 size_t i;
63
64 /* Assign unique bus/dev/fn for each HPET */
65 for (i = 0; i < 8; ++i)
66 pci_write_config16(dev, LPC_HnBDF(i),
67 PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
68
69 /* Move HPET to default address 0xfed00000 and enable it */
70 reg32 = RCBA32(HPTC);
71 reg32 |= (1 << 7); // HPET Address Enable
72 reg32 &= ~(3 << 0);
73 RCBA32(HPTC) = reg32;
74 /* Read it back to stick. It's affected by posted write syndrome. */
75 RCBA32(HPTC);
76 }
77
78 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
79 * 0x00 - 0000 = Reserved
80 * 0x01 - 0001 = Reserved
81 * 0x02 - 0010 = Reserved
82 * 0x03 - 0011 = IRQ3
83 * 0x04 - 0100 = IRQ4
84 * 0x05 - 0101 = IRQ5
85 * 0x06 - 0110 = IRQ6
86 * 0x07 - 0111 = IRQ7
87 * 0x08 - 1000 = Reserved
88 * 0x09 - 1001 = IRQ9
89 * 0x0A - 1010 = IRQ10
90 * 0x0B - 1011 = IRQ11
91 * 0x0C - 1100 = IRQ12
92 * 0x0D - 1101 = Reserved
93 * 0x0E - 1110 = IRQ14
94 * 0x0F - 1111 = IRQ15
95 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
96 * 0x80 - The PIRQ is not routed.
97 */
98
pch_pirq_init(struct device * dev)99 static void pch_pirq_init(struct device *dev)
100 {
101 struct device *irq_dev;
102
103 const uint8_t pirq = 0x80;
104
105 pci_write_config8(dev, PIRQA_ROUT, pirq);
106 pci_write_config8(dev, PIRQB_ROUT, pirq);
107 pci_write_config8(dev, PIRQC_ROUT, pirq);
108 pci_write_config8(dev, PIRQD_ROUT, pirq);
109
110 pci_write_config8(dev, PIRQE_ROUT, pirq);
111 pci_write_config8(dev, PIRQF_ROUT, pirq);
112 pci_write_config8(dev, PIRQG_ROUT, pirq);
113 pci_write_config8(dev, PIRQH_ROUT, pirq);
114
115 /* Eric Biederman once said we should let the OS do this.
116 * I am not so sure anymore he was right.
117 */
118
119 for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
120 u8 int_pin = 0, int_line = 0;
121
122 if (!is_enabled_pci(irq_dev))
123 continue;
124
125 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
126
127 switch (int_pin) {
128 case 1: /* INTA# */
129 case 2: /* INTB# */
130 case 3: /* INTC# */
131 case 4: /* INTD# */
132 int_line = pirq;
133 break;
134 }
135
136 if (!int_line)
137 continue;
138
139 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
140 }
141 }
142
pch_gpi_routing(struct device * dev,struct southbridge_intel_lynxpoint_config * config)143 static void pch_gpi_routing(struct device *dev,
144 struct southbridge_intel_lynxpoint_config *config)
145 {
146 u32 reg32 = 0;
147
148 /* An array would be much nicer here, or some
149 * other method of doing this.
150 */
151 reg32 |= (config->gpi0_routing & 0x03) << 0;
152 reg32 |= (config->gpi1_routing & 0x03) << 2;
153 reg32 |= (config->gpi2_routing & 0x03) << 4;
154 reg32 |= (config->gpi3_routing & 0x03) << 6;
155 reg32 |= (config->gpi4_routing & 0x03) << 8;
156 reg32 |= (config->gpi5_routing & 0x03) << 10;
157 reg32 |= (config->gpi6_routing & 0x03) << 12;
158 reg32 |= (config->gpi7_routing & 0x03) << 14;
159 reg32 |= (config->gpi8_routing & 0x03) << 16;
160 reg32 |= (config->gpi9_routing & 0x03) << 18;
161 reg32 |= (config->gpi10_routing & 0x03) << 20;
162 reg32 |= (config->gpi11_routing & 0x03) << 22;
163 reg32 |= (config->gpi12_routing & 0x03) << 24;
164 reg32 |= (config->gpi13_routing & 0x03) << 26;
165 reg32 |= (config->gpi14_routing & 0x03) << 28;
166 reg32 |= (config->gpi15_routing & 0x03) << 30;
167
168 pci_write_config32(dev, GPIO_ROUT, reg32);
169 }
170
pch_power_options(struct device * dev)171 static void pch_power_options(struct device *dev)
172 {
173 u8 reg8;
174 u16 reg16;
175 u32 reg32;
176 const char *state;
177 u16 pmbase = get_pmbase();
178
179 /* Which state do we want to goto after g3 (power restored)?
180 * 0 == S0 Full On
181 * 1 == S5 Soft Off
182 *
183 * If the option is not existent (Laptops), use Kconfig setting.
184 */
185 const unsigned int pwr_on = get_uint_option("power_on_after_fail",
186 CONFIG_MAINBOARD_POWER_FAILURE_STATE);
187
188 reg16 = pci_read_config16(dev, GEN_PMCON_3);
189 reg16 &= 0xfffe;
190 switch (pwr_on) {
191 case MAINBOARD_POWER_OFF:
192 reg16 |= 1;
193 state = "off";
194 break;
195 case MAINBOARD_POWER_ON:
196 reg16 &= ~1;
197 state = "on";
198 break;
199 case MAINBOARD_POWER_KEEP:
200 reg16 &= ~1;
201 state = "state keep";
202 break;
203 default:
204 state = "undefined";
205 }
206
207 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
208 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
209
210 reg16 &= ~(1 << 10);
211 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
212
213 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
214
215 pci_write_config16(dev, GEN_PMCON_3, reg16);
216 printk(BIOS_INFO, "Set power %s after power failure.\n", state);
217
218 /* Set up NMI on errors. */
219 reg8 = inb(0x61);
220 reg8 &= 0x0f; /* Higher Nibble must be 0 */
221 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
222 // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
223 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
224 outb(reg8, 0x61);
225
226 reg8 = inb(0x70);
227 const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
228 if (nmi_option) {
229 printk(BIOS_INFO, "NMI sources enabled.\n");
230 reg8 &= ~(1 << 7); /* Set NMI. */
231 } else {
232 printk(BIOS_INFO, "NMI sources disabled.\n");
233 reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
234 }
235 outb(reg8, 0x70);
236
237 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
238 reg16 = pci_read_config16(dev, GEN_PMCON_1);
239 reg16 &= ~(3 << 0); // SMI# rate 1 minute
240 reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME
241 pci_write_config16(dev, GEN_PMCON_1, reg16);
242
243 if (dev->chip_info) {
244 struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
245
246 /*
247 * Set the board's GPI routing on LynxPoint-H.
248 * This is done as part of GPIO configuration on LynxPoint-LP.
249 */
250 if (!pch_is_lp())
251 pch_gpi_routing(dev, config);
252
253 /* GPE setup based on device tree configuration */
254 enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
255 config->gpe0_en_3, config->gpe0_en_4);
256
257 /* SMI setup based on device tree configuration */
258 enable_alt_smi(config->alt_gp_smi_en);
259 }
260
261 /* Set up power management block and determine sleep mode */
262 reg32 = inl(pmbase + 0x04); // PM1_CNT
263 reg32 &= ~(7 << 10); // SLP_TYP
264 reg32 |= (1 << 0); // SCI_EN
265 outl(reg32, pmbase + 0x04);
266
267 /* Clear magic status bits to prevent unexpected wake */
268 reg32 = RCBA32(0x3310);
269 reg32 |= (1 << 4) | (1 << 5) | (1 << 0);
270 RCBA32(0x3310) = reg32;
271
272 reg16 = RCBA16(0x3f02);
273 reg16 &= ~0xf;
274 RCBA16(0x3f02) = reg16;
275 }
276
configure_dmi_pm(struct device * dev)277 static void configure_dmi_pm(struct device *dev)
278 {
279 struct device *const pcie_dev = pcidev_on_root(0x1c, 0);
280
281 /* Additional PCH DMI programming steps */
282
283 /* EL0 */
284 u32 reg32 = 3 << 12;
285
286 /* EL1 */
287 if (pcie_dev && !(pci_read_config8(pcie_dev, 0xf5) & 1 << 0))
288 reg32 |= 2 << 15;
289 else
290 reg32 |= 4 << 15;
291
292 RCBA32_AND_OR(0x21a4, ~(7 << 15 | 7 << 12), reg32);
293
294 RCBA32_AND_OR(0x2348, ~0xf, 0);
295
296 /* Clear prior to enabling DMI ASPM */
297 RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
298
299 RCBA32_OR(0x21a4, 3 << 10);
300
301 RCBA16(0x21a8) |= 3 << 0;
302
303 /* Set again after enabling DMI ASPM */
304 RCBA32_OR(0x2304, 1 << 10);
305 }
306
307 /* LynxPoint PCH Power Management init */
lpt_pm_init(struct device * dev)308 static void lpt_pm_init(struct device *dev)
309 {
310 struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
311
312 struct device *const pcie_dev = pcidev_on_root(0x1c, 0);
313
314 printk(BIOS_DEBUG, "LynxPoint H PM init\n");
315
316 /* Configure additional PM */
317 pci_write_config8(dev, 0xa9, 0x46);
318
319 pci_or_config32(dev, PMIR, PMIR_CF9LOCK);
320
321 /* Step 3 is skipped */
322
323 /* Program DMI Hardware Width Control (thermal throttling) */
324 u32 reg32 = 0;
325 reg32 |= 1 << 0; /* DMI Thermal Sensor Autonomous Width Enable */
326 reg32 |= 0 << 4; /* Thermal Sensor 0 Target Width */
327 reg32 |= 1 << 6; /* Thermal Sensor 1 Target Width */
328 reg32 |= 1 << 8; /* Thermal Sensor 2 Target Width */
329 reg32 |= 2 << 10; /* Thermal Sensor 3 Target Width */
330 RCBA32(0x2238) = reg32;
331
332 RCBA32_OR(0x232c, 1 << 0);
333 RCBA32_OR(0x1100, 3 << 13); /* Assume trunk clock gating is to be enabled */
334
335 RCBA32(0x2304) = 0xc07b8400; /* DMI misc control */
336
337 RCBA32_OR(0x2314, 1 << 23 | 1 << 5);
338
339 if (pcie_dev)
340 pci_update_config8(pcie_dev, 0xf5, ~0xf, 0x5);
341
342 RCBA32_OR(0x2320, 1 << 1);
343
344 RCBA32(0x3314) = 0x000007bf;
345
346 /* NOTE: Preserve bit 5 */
347 RCBA32_OR(0x3318, 0x0dcf0000);
348
349 RCBA32(0x3324) = 0x04000000;
350 RCBA32(0x3340) = 0x020ddbff;
351
352 RCBA32_OR(0x3344, 1 << 0);
353
354 RCBA32(0x3368) = 0x00041000;
355 RCBA32(0x3378) = 0x3f8ddbff;
356 RCBA32(0x337c) = 0x000001e1;
357 RCBA32(0x3388) = 0x00001000;
358 RCBA32(0x33a0) = 0x00000800;
359 RCBA32(0x33ac) = 0x00001000;
360 RCBA32(0x33b0) = 0x00001000;
361 RCBA32(0x33c0) = 0x00011900;
362 RCBA32(0x33d0) = 0x06000802;
363 RCBA32(0x3a28) = 0x01010000;
364 RCBA32(0x3a2c) = 0x01010404;
365
366 RCBA32_OR(0x33a4, 1 << 0);
367
368 /* DMI power optimizer */
369 RCBA32_OR(0x33d4, 1 << 27);
370 RCBA32_OR(0x33c8, 1 << 27);
371 RCBA32(0x2b14) = 0x1e0a0317;
372 RCBA32(0x2b24) = 0x4000000b;
373 RCBA32(0x2b28) = 0x00000002;
374 RCBA32(0x2b2c) = 0x00008813;
375
376 RCBA32(0x3a80) = 0x01040000;
377 reg32 = 0x01041001;
378 /* Port 1 and 0 disabled */
379 if (config && (config->sata_port_map & ((1 << 1) | (1 << 0))) == 0)
380 reg32 |= (1 << 20) | (1 << 18);
381 /* Port 3 and 2 disabled */
382 if (config && (config->sata_port_map & ((1 << 3) | (1 << 2))) == 0)
383 reg32 |= (1 << 24) | (1 << 26);
384 RCBA32(0x3a84) = reg32;
385 RCBA32(0x3a88) = 0x00000001;
386 RCBA32(0x33d4) = 0xc80bc000;
387
388 configure_dmi_pm(dev);
389 }
390
391 /* LynxPoint LP PCH Power Management init */
lpt_lp_pm_init(struct device * dev)392 static void lpt_lp_pm_init(struct device *dev)
393 {
394 struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
395 u32 data;
396
397 printk(BIOS_DEBUG, "LynxPoint LP PM init\n");
398
399 pci_write_config8(dev, 0xa9, 0x46);
400
401 RCBA32_AND_OR(0x232c, ~1, 0);
402
403 RCBA32_AND_OR(0x1100, ~0xc000, 0xc000);
404 RCBA32_OR(0x1100, 0x00000100);
405 RCBA32_OR(0x1100, 0x0000003f);
406
407 RCBA32_AND_OR(0x2320, ~0x60, 0x10);
408
409 RCBA32(0x3314) = 0x00012fff;
410 RCBA32(0x3318) = 0x0dcf0400;
411 RCBA32(0x3324) = 0x04000000;
412 RCBA32(0x3368) = 0x00041400;
413 RCBA32(0x3388) = 0x3f8ddbff;
414 RCBA32(0x33ac) = 0x00007001;
415 RCBA32(0x33b0) = 0x00181900;
416 RCBA32(0x33c0) = 0x00060A00;
417 RCBA32(0x33d0) = 0x06200840;
418 RCBA32(0x3a28) = 0x01010101;
419 RCBA32(0x3a2c) = 0x04040404;
420 RCBA32(0x2b1c) = 0x03808033;
421 RCBA32(0x2b34) = 0x80000009;
422 RCBA32(0x3348) = 0x022ddfff;
423 RCBA32(0x334c) = 0x00000001;
424 RCBA32(0x3358) = 0x0001c000;
425 RCBA32(0x3380) = 0x3f8ddbff;
426 RCBA32(0x3384) = 0x0001c7e1;
427 RCBA32(0x338c) = 0x0001c7e1;
428 RCBA32(0x3398) = 0x0001c000;
429 RCBA32(0x33a8) = 0x00181900;
430 RCBA32(0x33dc) = 0x00080000;
431 RCBA32(0x33e0) = 0x00000001;
432 RCBA32(0x3a20) = 0x00000404;
433 RCBA32(0x3a24) = 0x01010101;
434 RCBA32(0x3a30) = 0x01010101;
435
436 RCBA32_OR(0x0410, 0x00000003);
437 RCBA32_OR(0x2618, 0x08000000);
438 RCBA32_OR(0x2300, 0x00000002);
439 RCBA32_OR(0x2600, 0x00000008);
440
441 RCBA32(0x33b4) = 0x00007001;
442 RCBA32(0x3350) = 0x022ddfff;
443 RCBA32(0x3354) = 0x00000001;
444
445 /* Power Optimizer */
446 RCBA32_OR(0x33d4, 0x08000000);
447 RCBA32_OR(0x33c8, 0x00000080);
448
449 RCBA32(0x2b10) = 0x0000883c;
450 RCBA32(0x2b14) = 0x1e0a4616;
451 RCBA32(0x2b24) = 0x40000005;
452 RCBA32(0x2b20) = 0x0005db01;
453 RCBA32(0x3a80) = 0x05145005;
454
455 pci_or_config32(dev, 0xac, 1 << 21);
456
457 pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700);
458 pch_iobp_update(0xED000118, ~0, 0x00c00000);
459 pch_iobp_update(0xED000120, ~0, 0x00240000);
460 pch_iobp_update(0xCA000000, ~0, 0x00000009);
461
462 /* Set RCBA CIR28 0x3A84 based on SATA port enables */
463 data = 0x00001005;
464 /* Port 3 and 2 disabled */
465 if (config && (config->sata_port_map & ((1 << 3) | (1 << 2))) == 0)
466 data |= (1 << 24) | (1 << 26);
467 /* Port 1 and 0 disabled */
468 if (config && (config->sata_port_map & ((1 << 1) | (1 << 0))) == 0)
469 data |= (1 << 20) | (1 << 18);
470 RCBA32(0x3a84) = data;
471
472 /* Set RCBA 0x2b1c[29]=1 if DSP disabled */
473 if (RCBA32(FD) & PCH_DISABLE_ADSPD)
474 RCBA32_OR(0x2b1c, (1 << 29));
475
476 /* Set RCBA 0x33D4 after other setup */
477 RCBA32_OR(0x33d4, 0x2fff2fb1);
478
479 /* Set RCBA 0x33C8[15]=1 as last step */
480 RCBA32_OR(0x33c8, (1 << 15));
481 }
482
enable_clock_gating(struct device * dev)483 static void enable_clock_gating(struct device *dev)
484 {
485 /* LynxPoint Mobile */
486 u32 reg32;
487 u16 reg16;
488
489 /* DMI */
490 RCBA32_AND_OR(0x2234, ~0, 0xf);
491 reg16 = pci_read_config16(dev, GEN_PMCON_1);
492 reg16 |= (1 << 11) | (1 << 12) | (1 << 14);
493 reg16 |= (1 << 2); // PCI CLKRUN# Enable
494 pci_write_config16(dev, GEN_PMCON_1, reg16);
495 RCBA32_OR(0x900, (1 << 14));
496
497 reg32 = RCBA32(CG);
498 reg32 |= (1 << 22); // HDA Dynamic
499 reg32 |= (1 << 31); // LPC Dynamic
500 reg32 |= (1 << 16); // PCIe Dynamic
501 reg32 |= (1 << 27); // HPET Dynamic
502 reg32 |= (1 << 28); // GPIO Dynamic
503 RCBA32(CG) = reg32;
504
505 RCBA32_OR(0x38c0, 0x7); // SPI Dynamic
506 }
507
enable_lp_clock_gating(struct device * dev)508 static void enable_lp_clock_gating(struct device *dev)
509 {
510 /* LynxPoint LP */
511 u32 reg32;
512 u16 reg16;
513
514 /* DMI */
515 RCBA32_AND_OR(0x2234, ~0, 0xf);
516 reg16 = pci_read_config16(dev, GEN_PMCON_1);
517 reg16 &= ~((1 << 11) | (1 << 14));
518 reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13);
519 reg16 |= (1 << 2); // PCI CLKRUN# Enable
520 pci_write_config16(dev, GEN_PMCON_1, reg16);
521
522 pci_or_config32(dev, 0x64, 1 << 6);
523
524 /*
525 * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1
526 * RCBA + 0x2614[23:16] = 0x20
527 * RCBA + 0x2614[30:28] = 0x0
528 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b)
529 */
530 RCBA32_AND_OR(0x2614, ~0x74000000, 0x0a206500);
531
532 /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */
533 struct device *const gma = pcidev_on_root(2, 0);
534 if (gma && pci_read_config8(gma, 0x8) >= 0x0b)
535 RCBA32_OR(0x2614, (1 << 26));
536
537 RCBA32_OR(0x900, 0x0000031f);
538
539 reg32 = RCBA32(CG);
540 if (RCBA32(0x3454) & (1 << 4))
541 reg32 &= ~(1 << 29); // LPC Dynamic
542 else
543 reg32 |= (1 << 29); // LPC Dynamic
544 reg32 |= (1 << 31); // LP LPC
545 reg32 |= (1 << 30); // LP BLA
546 reg32 |= (1 << 28); // GPIO Dynamic
547 reg32 |= (1 << 27); // HPET Dynamic
548 reg32 |= (1 << 26); // Generic Platform Event Clock
549 if (RCBA32(BUC) & PCH_DISABLE_GBE)
550 reg32 |= (1 << 23); // GbE Static
551 reg32 |= (1 << 22); // HDA Dynamic
552 reg32 |= (1 << 16); // PCI Dynamic
553 RCBA32(CG) = reg32;
554
555 RCBA32_OR(0x3434, 0x7); // LP LPC
556
557 RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic
558
559 pch_iobp_update(0xCF000000, ~0, 0x00007001);
560 pch_iobp_update(0xCE00C000, ~1, 0x00000000); // bit0=0 in BWG 1.4.0
561 }
562
pch_set_acpi_mode(void)563 static void pch_set_acpi_mode(void)
564 {
565 if (!acpi_is_wakeup_s3())
566 apm_control(APM_CNT_ACPI_DISABLE);
567 }
568
lpc_init(struct device * dev)569 static void lpc_init(struct device *dev)
570 {
571 printk(BIOS_DEBUG, "pch: %s\n", __func__);
572
573 /* IO APIC initialization. */
574 pch_enable_ioapic(dev);
575
576 pch_enable_serial_irqs(dev);
577
578 /* Setup the PIRQ. */
579 pch_pirq_init(dev);
580
581 /* Setup power options. */
582 pch_power_options(dev);
583
584 /* Initialize power management */
585 if (pch_is_lp()) {
586 lpt_lp_pm_init(dev);
587 enable_lp_clock_gating(dev);
588 } else {
589 lpt_pm_init(dev);
590 enable_clock_gating(dev);
591 }
592
593 /* Initialize the real time clock. */
594 sb_rtc_init();
595
596 /* Initialize ISA DMA. */
597 isa_dma_init();
598
599 /* Initialize the High Precision Event Timers, if present. */
600 enable_hpet(dev);
601
602 setup_i8259();
603
604 /* Interrupt 9 should be level triggered (SCI) */
605 i8259_configure_irq_trigger(9, 1);
606
607 pch_set_acpi_mode();
608
609 /* Indicate DRAM init done for MRC S3 to know it can resume */
610 pci_or_config8(dev, GEN_PMCON_2, 1 << 7);
611 }
612
pch_lpc_add_mmio_resources(struct device * dev)613 static void pch_lpc_add_mmio_resources(struct device *dev)
614 {
615 u32 reg;
616 struct resource *res;
617 const u32 default_decode_base = IO_APIC_ADDR;
618
619 /*
620 * Just report all resources from IO-APIC base to 4GiB. Don't mark
621 * them reserved as that may upset the OS if this range is marked
622 * as reserved in the e820.
623 */
624 res = new_resource(dev, OIC);
625 res->base = default_decode_base;
626 res->size = 4ull * GiB - default_decode_base;
627 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
628
629 /* RCBA */
630 if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) {
631 res = new_resource(dev, RCBA);
632 res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE;
633 res->size = CONFIG_RCBA_LENGTH;
634 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
635 IORESOURCE_FIXED | IORESOURCE_RESERVE;
636 }
637
638 /* Check LPC Memory Decode register. */
639 reg = pci_read_config32(dev, LGMR);
640 if (reg & 1) {
641 reg &= ~0xffff;
642 if (reg < default_decode_base) {
643 res = new_resource(dev, LGMR);
644 res->base = reg;
645 res->size = 16 * 1024;
646 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
647 IORESOURCE_FIXED | IORESOURCE_RESERVE;
648 }
649 }
650 }
651
652 /* Default IO range claimed by the LPC device. The upper bound is exclusive. */
653 #define LPC_DEFAULT_IO_RANGE_LOWER 0
654 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
655
pch_io_range_in_default(int base,int size)656 static inline int pch_io_range_in_default(int base, int size)
657 {
658 /* Does it start above the range? */
659 if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
660 return 0;
661
662 /* Is it entirely contained? */
663 if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
664 (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
665 return 1;
666
667 /* This will return not in range for partial overlaps. */
668 return 0;
669 }
670
671 /*
672 * Note: this function assumes there is no overlap with the default LPC device's
673 * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
674 */
pch_lpc_add_io_resource(struct device * dev,u16 base,u16 size,int index)675 static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size,
676 int index)
677 {
678 struct resource *res;
679
680 if (pch_io_range_in_default(base, size))
681 return;
682
683 res = new_resource(dev, index);
684 res->base = base;
685 res->size = size;
686 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
687 }
688
pch_lpc_add_gen_io_resources(struct device * dev,int reg_value,int index)689 static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
690 int index)
691 {
692 /*
693 * Check if the register is enabled. If so, and the base exceeds the
694 * device's default claim range, add the resource.
695 */
696 if (reg_value & 1) {
697 u16 base = reg_value & 0xfffc;
698 u16 size = (0x3 | ((reg_value >> 16) & 0xfc)) + 1;
699 pch_lpc_add_io_resource(dev, base, size, index);
700 }
701 }
702
pch_lpc_add_io_resources(struct device * dev)703 static void pch_lpc_add_io_resources(struct device *dev)
704 {
705 struct resource *res;
706
707 /* Add the default claimed IO range for the LPC device. */
708 res = new_resource(dev, 0);
709 res->base = LPC_DEFAULT_IO_RANGE_LOWER;
710 res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
711 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
712
713 /* GPIOBASE */
714 pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE);
715
716 /* PMBASE */
717 pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE);
718
719 /* LPC Generic IO Decode range. */
720 if (dev->chip_info) {
721 struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
722 pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
723 pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
724 pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);
725 pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
726 }
727 }
728
pch_lpc_read_resources(struct device * dev)729 static void pch_lpc_read_resources(struct device *dev)
730 {
731 /* Get the normal PCI resources of this device. */
732 pci_dev_read_resources(dev);
733
734 /* Add non-standard MMIO resources. */
735 pch_lpc_add_mmio_resources(dev);
736
737 /* Add IO resources. */
738 pch_lpc_add_io_resources(dev);
739 }
740
pch_lpc_enable(struct device * dev)741 static void pch_lpc_enable(struct device *dev)
742 {
743 /* Enable PCH Display Port */
744 RCBA16(DISPBDF) = 0x0010;
745 RCBA32_OR(FD2, PCH_ENABLE_DBDF);
746
747 pch_enable(dev);
748 }
749
lpc_acpi_name(const struct device * dev)750 static const char *lpc_acpi_name(const struct device *dev)
751 {
752 return "LPCB";
753 }
754
southbridge_fill_ssdt(const struct device * dev)755 static void southbridge_fill_ssdt(const struct device *dev)
756 {
757 intel_acpi_gen_def_acpi_pirq(dev);
758 }
759
southbridge_write_acpi_tables(const struct device * device,unsigned long start,struct acpi_rsdp * rsdp)760 static unsigned long southbridge_write_acpi_tables(const struct device *device,
761 unsigned long start,
762 struct acpi_rsdp *rsdp)
763 {
764 unsigned long current;
765
766 current = start;
767
768 /* Align ACPI tables to 16byte */
769 current = acpi_align_current(current);
770
771 /*
772 * We explicitly add these tables later on:
773 */
774 current = acpi_write_hpet(device, current, rsdp);
775
776 current = acpi_align_current(current);
777
778 if (pch_is_lp()) {
779 printk(BIOS_DEBUG, "ACPI: * SSDT2\n");
780 acpi_header_t *ssdt = (acpi_header_t *)current;
781 acpi_create_serialio_ssdt(ssdt);
782 current += ssdt->length;
783 acpi_add_table(rsdp, ssdt);
784 current = acpi_align_current(current);
785 }
786
787 printk(BIOS_DEBUG, "current = %lx\n", current);
788 return current;
789 }
790
lpc_final(struct device * dev)791 static void lpc_final(struct device *dev)
792 {
793 spi_finalize_ops();
794
795 /* Lock */
796 RCBA32_OR(0x3a6c, 0x00000001);
797
798 if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN))
799 apm_control(APM_CNT_FINALIZE);
800 }
801
802 static struct device_operations device_ops = {
803 .read_resources = pch_lpc_read_resources,
804 .set_resources = pci_dev_set_resources,
805 .enable_resources = pci_dev_enable_resources,
806 .acpi_fill_ssdt = southbridge_fill_ssdt,
807 .acpi_name = lpc_acpi_name,
808 .write_acpi_tables = southbridge_write_acpi_tables,
809 .init = lpc_init,
810 .final = lpc_final,
811 .enable = pch_lpc_enable,
812 .scan_bus = scan_static_bus,
813 .ops_pci = &pci_dev_ops_pci,
814 };
815
816 /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */
817 static const unsigned short pci_device_ids[] = {
818 PCI_DID_INTEL_LPT_MOBILE_SAMPLE,
819 PCI_DID_INTEL_LPT_DESKTOP_SAMPLE,
820 PCI_DID_INTEL_LPT_Z87,
821 PCI_DID_INTEL_LPT_Z85,
822 PCI_DID_INTEL_LPT_HM86,
823 PCI_DID_INTEL_LPT_H87,
824 PCI_DID_INTEL_LPT_HM87,
825 PCI_DID_INTEL_LPT_Q85,
826 PCI_DID_INTEL_LPT_Q87,
827 PCI_DID_INTEL_LPT_QM87,
828 PCI_DID_INTEL_LPT_B85,
829 PCI_DID_INTEL_LPT_C222,
830 PCI_DID_INTEL_LPT_C224,
831 PCI_DID_INTEL_LPT_C226,
832 PCI_DID_INTEL_LPT_H81,
833 PCI_DID_INTEL_LPT_LP_SAMPLE,
834 PCI_DID_INTEL_LPT_LP_PREMIUM,
835 PCI_DID_INTEL_LPT_LP_MAINSTREAM,
836 PCI_DID_INTEL_LPT_LP_VALUE,
837 PCI_DID_INTEL_LPT_MOBILE_SAMPLE_9,
838 PCI_DID_INTEL_LPT_DESKTOP_SAMPLE_9,
839 PCI_DID_INTEL_LPT_HM97,
840 PCI_DID_INTEL_LPT_Z97,
841 PCI_DID_INTEL_LPT_H97,
842 0
843 };
844
845 static const struct pci_driver pch_lpc __pci_driver = {
846 .ops = &device_ops,
847 .vendor = PCI_VID_INTEL,
848 .devices = pci_device_ids,
849 };
850