1 /*
2 * Copyright (c) 2020-2023, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_vdbox_vdenc_cmdpar.h
24 //! \brief MHW command parameters
25 //! \details
26 //!
27
28 #ifndef __MHW_VDBOX_VDENC_CMDPAR_H__
29 #define __MHW_VDBOX_VDENC_CMDPAR_H__
30
31 #include <functional>
32 #include "mhw_vdbox_cmdpar.h"
33 #include "codec_def_common.h"
34 #include "codec_def_common_encode.h"
35
36 #if _MEDIA_RESERVED
37 #include "mhw_vdbox_vdenc_cmdpar_ext.h"
38 #define __MHW_VDBOX_VDENC_WRAPPER(STUFF)
39 #define __MHW_VDBOX_VDENC_WRAPPER_EXT(STUFF) STUFF
40 #else
41 #define __MHW_VDBOX_VDENC_WRAPPER(STUFF) STUFF
42 #define __MHW_VDBOX_VDENC_WRAPPER_EXT(STUFF)
43 #endif // _MEDIA_RESERVED
44
45 namespace mhw
46 {
47 namespace vdbox
48 {
49 namespace vdenc
50 {
51 static constexpr uint32_t MAX_REF_LIST_NUM = 2;
52 static constexpr uint32_t MAX_REF_NUM_L0 = 4;
53 static constexpr uint32_t MAX_REF_NUM_L1 = 4; // low delay B may have 3 L1 refs
54 static constexpr uint32_t MAX_REF_NUM = MAX_REF_NUM_L0 > MAX_REF_NUM_L1 ? MAX_REF_NUM_L0 : MAX_REF_NUM_L1;
55 static constexpr uint32_t MAX_REF_NUM_L0L1 = MAX_REF_NUM_L0 + MAX_REF_NUM_L1;
56
57 enum class SurfaceFormat
58 {
59 yuv422 = 0x0,
60 rgba4444 = 0x1,
61 yuv444 = 0x2,
62 p010Variant = 0x3,
63 planar4208 = 0x4,
64 yCrCbSwapY422 = 0x5,
65 yCrCbSwapUv422 = 0x6,
66 yCrCbSwapUvy422 = 0x7,
67 y216 = 0x8,
68 y210 = 0x8,
69 r10g10b10a2 = 0x9,
70 y410 = 0xa,
71 nv21 = 0xb,
72 y416 = 0xc,
73 p010 = 0xd,
74 planarP016 = 0xe,
75 y8Unorm = 0xf,
76 y16 = 0x10,
77 y216Variant = 0x11,
78 y416Variant = 0x12,
79 yuyvVariant = 0x13,
80 ayuvVariant = 0x14,
81 };
82
83 struct RowStorePar
84 {
85 enum Codec
86 {
87 AVC,
88 HEVC,
89 VP9,
90 AV1
91 };
92
93 enum ChromaFormat
94 {
95 MONOCHROME,
96 YUV420,
97 YUV422,
98 YUV444
99 };
100
101 enum BitDepth
102 {
103 DEPTH_8,
104 DEPTH_10,
105 DEPTH_12
106 };
107
108 enum LcuSize
109 {
110 SIZE_32,
111 SIZE_64,
112 SIZE_OTHER,
113 };
114
115 Codec mode = AVC;
116 ChromaFormat format = MONOCHROME;
117 BitDepth bitDepth = DEPTH_8;
118 LcuSize lcuSize = SIZE_32;
119 bool isField = false;
120 uint32_t frameWidth = 0;
121 };
122
_MHW_PAR_T(VDENC_STREAMIN_STATE)123 struct _MHW_PAR_T(VDENC_STREAMIN_STATE)
124 {
125 uint8_t maxTuSize;
126 uint8_t maxCuSize;
127 uint8_t numImePredictors;
128 uint8_t numMergeCandidateCu64x64;
129 uint8_t numMergeCandidateCu32x32;
130 uint8_t numMergeCandidateCu16x16;
131 uint8_t numMergeCandidateCu8x8;
132 bool setQpRoiCtrl;
133 int8_t forceQp[4];
134 uint8_t roiCtrl;
135 uint8_t puTypeCtrl;
136 };
137
_MHW_PAR_T(VDENC_CONTROL_STATE)138 struct _MHW_PAR_T(VDENC_CONTROL_STATE)
139 {
140 bool vdencInitialization = true;
141 };
142
_MHW_PAR_T(VDENC_PIPE_MODE_SELECT)143 struct _MHW_PAR_T(VDENC_PIPE_MODE_SELECT)
144 {
145 uint8_t standardSelect = 0;
146 bool scalabilityMode = false;
147 bool frameStatisticsStreamOut = false;
148 bool pakObjCmdStreamOut = false;
149 bool tlbPrefetch = false;
150 bool dynamicSlice = false;
151 bool streamIn = false;
152 uint8_t bitDepthMinus8 = 0;
153 uint8_t chromaType = 0;
154 uint8_t outputRangeControlCsc = 1;
155 bool tileBasedReplayMode = false;
156 bool randomAccess = false;
157 bool rgbEncodingMode = false;
158 bool hmeRegionPrefetch = true;
159 uint8_t topPrefetchEnableMode = 0;
160 uint8_t leftPrefetchAtWrapAround = 1;
161 uint8_t verticalShift32Minus1 = 2;
162 uint8_t hzShift32Minus1 = 3;
163 uint8_t numVerticalReqMinus1 = 6;
164 uint8_t numHzReqMinus1 = 2;
165 uint8_t prefetchOffset = 0;
166 uint8_t captureMode = 0;
167 uint8_t wirelessSessionId = 0;
168 uint8_t tailPointerReadFrequency = 0;
169 uint8_t streamingBufferConfig = 0;
170 bool bt2020RGB2YUV = 0;
171 uint8_t rgbInputStudioRange = 0;
172 uint8_t convertedYUVStudioRange = 0;
173 uint8_t VdencPipeModeSelectPar0 = 0;
174 uint8_t VdencPipeModeSelectPar1 = 0;
175 uint8_t VdencPipeModeSelectPar2 = 0;
176 uint8_t VdencPipeModeSelectPar3 = 0;
177 uint8_t VdencPipeModeSelectPar4 = 0;
178 uint8_t VdencPipeModeSelectPar5 = 0;
179 uint8_t VdencPipeModeSelectPar6 = 0;
180 uint8_t VdencPipeModeSelectPar7 = 0;
181 uint8_t VdencPipeModeSelectPar8 = 0;
182 bool fastPassEn = false;
183 uint8_t fastPassScale = 0;
184 uint8_t DownScaleType = 0;
185 uint8_t VdencPipeModeSelectPar12 = 0;
186 uint8_t VdencPipeModeSelectPar13 = 0;
187 };
188
_MHW_PAR_T(VDENC_SRC_SURFACE_STATE)189 struct _MHW_PAR_T(VDENC_SRC_SURFACE_STATE)
190 {
191 uint32_t width = 0;
192 uint32_t height = 0;
193 uint32_t pitch = 0;
194 uint32_t uOffset = 0;
195 uint32_t vOffset = 0;
196 MOS_TILE_TYPE tileType = MOS_TILE_X;
197 MOS_TILE_MODE_GMM tileModeGmm = MOS_TILE_LINEAR_GMM;
198 MOS_FORMAT format = Format_Any;
199 bool gmmTileEn = false;
200 bool colorSpaceSelection = false;
201 bool displayFormatSwizzle = false;
202 uint32_t chromaDownsampleFilterControl = 0;
203 uint8_t vDirection = 0;
204 };
205
_MHW_PAR_T(VDENC_REF_SURFACE_STATE)206 struct _MHW_PAR_T(VDENC_REF_SURFACE_STATE)
207 {
208 uint32_t width = 0;
209 uint32_t height = 0;
210 uint32_t pitch = 0;
211 uint32_t uOffset = 0;
212 uint32_t vOffset = 0;
213 MOS_TILE_TYPE tileType = MOS_TILE_X;
214 MOS_TILE_MODE_GMM tileModeGmm = MOS_TILE_LINEAR_GMM;
215 MOS_FORMAT format = Format_Any;
216 bool gmmTileEn = false;
217 uint8_t vDirection = 0;
218 };
219
_MHW_PAR_T(VDENC_DS_REF_SURFACE_STATE)220 struct _MHW_PAR_T(VDENC_DS_REF_SURFACE_STATE)
221 {
222 uint8_t vDirectionStage1 = 0;
223 uint8_t vDirectionStage2 = 0;
224 uint32_t widthStage1 = 0;
225 uint32_t widthStage2 = 0;
226 uint32_t heightStage1 = 0;
227 uint32_t heightStage2 = 0;
228 uint32_t pitchStage1 = 0;
229 uint32_t pitchStage2 = 0;
230 uint32_t uOffsetStage1 = 0;
231 uint32_t uOffsetStage2 = 0;
232 uint32_t vOffsetStage1 = 0;
233 uint32_t vOffsetStage2 = 0;
234 MOS_TILE_TYPE tileTypeStage1 = MOS_TILE_X;
235 MOS_TILE_TYPE tileTypeStage2 = MOS_TILE_X;
236 MOS_TILE_MODE_GMM tileModeGmmStage1 = MOS_TILE_LINEAR_GMM;
237 MOS_TILE_MODE_GMM tileModeGmmStage2 = MOS_TILE_LINEAR_GMM;
238 bool gmmTileEnStage1 = false;
239 bool gmmTileEnStage2 = false;
240 };
241
_MHW_PAR_T(VDENC_PIPE_BUF_ADDR_STATE)242 struct _MHW_PAR_T(VDENC_PIPE_BUF_ADDR_STATE)
243 {
244 PMOS_SURFACE surfaceRaw = nullptr;
245 MOS_MEMCOMP_STATE mmcStateRaw = MOS_MEMCOMP_DISABLED;
246 uint32_t compressionFormatRaw = 0;
247 uint32_t compressionFormatRecon = 0;
248 PMOS_RESOURCE intraRowStoreScratchBuffer = nullptr;
249 PMOS_RESOURCE streamOutBuffer = nullptr;
250 uint32_t streamOutOffset = 0;
251 PMOS_RESOURCE streamInBuffer = nullptr;
252 uint32_t numActiveRefL0 = 0;
253 uint32_t numActiveRefL1 = 0;
254 PMOS_RESOURCE refs[MAX_REF_NUM_L0L1] = {};
255 PMOS_RESOURCE refsDsStage1[MAX_REF_NUM_L0L1] = {};
256 PMOS_RESOURCE refsDsStage2[MAX_REF_NUM_L0L1] = {};
257 MOS_MEMCOMP_STATE mmcStatePreDeblock = MOS_MEMCOMP_DISABLED;
258 MOS_MEMCOMP_STATE mmcStatePostDeblock = MOS_MEMCOMP_DISABLED;
259 PMOS_SURFACE surfaceDsStage1 = nullptr;
260 MOS_MEMCOMP_STATE mmcStateDsStage1 = MOS_MEMCOMP_DISABLED;
261 PMOS_SURFACE surfaceDsStage2 = nullptr;
262 MOS_MEMCOMP_STATE mmcStateDsStage2 = MOS_MEMCOMP_DISABLED;
263 uint8_t mmcSkipMask = 0;
264 bool mmcEnabled = false;
265 bool lowDelayB = false;
266 bool isPFrame = false; //only HEVC should touch this flag
267 PMOS_RESOURCE colocatedMvReadBuffer = nullptr;
268 PMOS_RESOURCE colMvTempBuffer[MAX_REF_NUM_L0L1] = {};
269 PMOS_RESOURCE pakObjCmdStreamOutBuffer = nullptr;
270 PMOS_RESOURCE segmentMapStreamInBuffer = nullptr;
271 PMOS_RESOURCE segmentMapStreamOutBuffer = nullptr;
272 PMOS_RESOURCE tileRowStoreBuffer = nullptr;
273 PMOS_RESOURCE mfdIntraRowStoreScratchBuffer = nullptr;
274 PMOS_RESOURCE cumulativeCuCountStreamOutBuffer = nullptr;
275 PMOS_RESOURCE colocatedMvWriteBuffer = nullptr;
276 PMOS_RESOURCE vdencPipeBufAddrStatePar0 = nullptr;
277 PMOS_RESOURCE vdencPipeBufAddrStatePar1 = nullptr;
278 PMOS_RESOURCE vdencPipeBufAddrStatePar2 = nullptr;
279 };
280
_MHW_PAR_T(VDENC_WEIGHTSOFFSETS_STATE)281 struct _MHW_PAR_T(VDENC_WEIGHTSOFFSETS_STATE)
282 {
283 int8_t weightsLuma[MAX_REF_LIST_NUM][MAX_REF_NUM] = {};
284 int16_t offsetsLuma[MAX_REF_LIST_NUM][MAX_REF_NUM] = {};
285 uint32_t denomLuma = 0;
286 int8_t weightsChroma[MAX_REF_LIST_NUM][MAX_REF_NUM][2] = {};
287 int16_t offsetsChroma[MAX_REF_LIST_NUM][MAX_REF_NUM][2] = {};
288 uint32_t denomChroma = 0;
289 };
290
_MHW_PAR_T(VDENC_HEVC_VP9_TILE_SLICE_STATE)291 struct _MHW_PAR_T(VDENC_HEVC_VP9_TILE_SLICE_STATE)
292 {
293 bool tileEnable = false;
294 bool tileRowStoreSelect = false;
295 uint32_t tileWidth = 0;
296 uint32_t tileHeight = 0;
297 uint32_t numPipe = 0;
298 uint32_t tileId = 0;
299 uint32_t tileStartLCUX = 0;
300 uint32_t tileStartLCUY = 0;
301 uint32_t ctbSize = 0;
302 uint32_t tileStreamInOffset = 0;
303 uint32_t tileLCUStreamOutOffset = 0;
304 uint32_t log2WeightDenomLuma = 0;
305 uint32_t log2WeightDenomChroma = 0;
306 uint32_t hevcVp9Log2WeightDenomLuma = 0;
307 uint32_t paletteModeEnable = 0;
308 uint32_t ibcControl = 0;
309 uint32_t VdencHEVCVP9TileSlicePar0 = 0;
310 uint32_t VdencHEVCVP9TileSlicePar1 = 0;
311 uint32_t VdencHEVCVP9TileSlicePar2 = 0;
312 uint32_t VdencHEVCVP9TileSlicePar3 = 0;
313 uint32_t VdencHEVCVP9TileSlicePar4 = 0;
314 uint32_t VdencHEVCVP9TileSlicePar5 = 0;
315 uint32_t VdencHEVCVP9TileSlicePar6 = 0;
316 uint32_t VdencHEVCVP9TileSlicePar7 = 0;
317 uint32_t VdencHEVCVP9TileSlicePar8 = 0;
318 uint32_t VdencHEVCVP9TileSlicePar9 = 0;
319 uint32_t VdencHEVCVP9TileSlicePar10 = 0;
320 uint32_t VdencHEVCVP9TileSlicePar11 = 0;
321 uint32_t VdencHEVCVP9TileSlicePar12 = 0;
322 uint32_t VdencHEVCVP9TileSlicePar13 = 0;
323 uint32_t VdencHEVCVP9TileSlicePar14 = 0;
324 uint32_t VdencHEVCVP9TileSlicePar15 = 0;
325 uint8_t VdencHEVCVP9TileSlicePar16[3] = {};
326 uint32_t VdencHEVCVP9TileSlicePar17[3] = {};
327 bool VdencHEVCVP9TileSlicePar18 = false;
328 uint32_t VdencHEVCVP9TileSlicePar19 = 0;
329 uint32_t VdencHEVCVP9TileSlicePar22 = 0;
330 uint32_t VdencHEVCVP9TileSlicePar23 = 0;
331 uint32_t VdencHEVCVP9TileSlicePar24 = 0;
332 uint32_t tileRowstoreOffset = 0;
333 };
334
_MHW_PAR_T(VDENC_WALKER_STATE)335 struct _MHW_PAR_T(VDENC_WALKER_STATE)
336 {
337 bool firstSuperSlice = true;
338 uint32_t tileSliceStartLcuMbX = 0;
339 uint32_t tileSliceStartLcuMbY = 0;
340 uint32_t nextTileSliceStartLcuMbX = 0;
341 uint32_t nextTileSliceStartLcuMbY = 0;
342 };
343
_MHW_PAR_T(VD_PIPELINE_FLUSH)344 struct _MHW_PAR_T(VD_PIPELINE_FLUSH)
345 {
346 bool waitDoneHEVC = false;
347 bool waitDoneVDENC = false;
348 bool waitDoneMFL = false;
349 bool waitDoneMFX = false;
350 bool waitDoneVDCmdMsgParser = false;
351 bool flushHEVC = false;
352 bool flushVDENC = false;
353 bool flushMFL = false;
354 bool flushMFX = false;
355 bool waitDoneAV1 = false;
356 bool flushAV1 = false;
357 bool waitDoneVDAQM = false;
358 bool flushVDAQM = false;
359 bool vvcpPipelineDone = false;
360 bool vvcpPipelineCommandFlush = false;
361
362 __MHW_VDBOX_VDENC_WRAPPER_EXT(VD_PIPELINE_FLUSH_CMDPAR_EXT);
363 };
364
_MHW_PAR_T(VDENC_AVC_SLICE_STATE)365 struct _MHW_PAR_T(VDENC_AVC_SLICE_STATE)
366 {
367 uint8_t roundIntra = 0;
368 uint8_t roundIntraEnable = 1;
369 uint8_t roundInter = 0;
370 uint8_t roundInterEnable = 0;
371 uint8_t log2WeightDenomLuma = 0;
372 };
373
_MHW_PAR_T(VDENC_AVC_IMG_STATE)374 struct _MHW_PAR_T(VDENC_AVC_IMG_STATE)
375 {
376 uint8_t pictureType = 0;
377 uint8_t transform8X8Flag = 0;
378 bool colMVWriteEnable = false;
379 uint8_t subpelMode = 3;
380 bool colMVReadEnable = false;
381 uint8_t bidirectionalWeight = 0;
382 uint16_t pictureHeightMinusOne = 0;
383 uint16_t pictureWidth = 0;
384 uint8_t fwdRefIdx0ReferencePicture = 0;
385 uint8_t bwdRefIdx0ReferencePicture = 0;
386 uint8_t fwdRefIdx1ReferencePicture = 0;
387 uint8_t fwdRefIdx2ReferencePicture = 0;
388 uint8_t numberOfL0ReferencesMinusOne = 0;
389 uint8_t numberOfL1ReferencesMinusOne = 0;
390 uint8_t intraRefreshMbPos = 0;
391 uint8_t intraRefreshMbSizeMinusOne = 0;
392 uint8_t intraRefreshEnableRollingIEnable = 0;
393 uint8_t intraRefreshMode = 0;
394 uint8_t qpAdjustmentForRollingI = 0;
395 uint8_t roiQpAdjustmentForZone0 = 0;
396 uint8_t roiQpAdjustmentForZone1 = 0;
397 uint8_t roiQpAdjustmentForZone2 = 0;
398 uint8_t roiQpAdjustmentForZone3 = 0;
399 uint8_t minQp = 0xa;
400 uint8_t maxQp = 0x33;
401 bool roiEnable = false;
402 bool mbLevelQpEnable = false;
403 bool mbLevelDeltaQpEnable = false;
404 bool longtermReferenceFrameBwdRef0Indicator = false;
405 uint8_t qpPrimeY = 0;
406 uint8_t trellisQuantEn = 0;
407 uint8_t pocNumberForCurrentPicture = 0;
408 uint8_t pocNumberForFwdRef0 = 0;
409 uint8_t pocNumberForFwdRef1 = 0;
410 uint8_t pocNumberForFwdRef2 = 0;
411 uint8_t pocNumberForBwdRef0 = 0;
412
413 __MHW_VDBOX_VDENC_WRAPPER(
414 std::vector<std::function<MOS_STATUS(uint32_t *)>> extSettings);
415 __MHW_VDBOX_VDENC_WRAPPER_EXT(
416 VDENC_AVC_IMG_STATE_CMDPAR_EXT);
417 };
418
_MHW_PAR_T(VDENC_CMD1)419 struct _MHW_PAR_T(VDENC_CMD1)
420 {
421 uint16_t vdencCmd1Par0 = 0;
422 uint16_t vdencCmd1Par1 = 0;
423 uint8_t vdencCmd1Par2[8] = {};
424 uint8_t vdencCmd1Par3[12] = {};
425 uint8_t vdencCmd1Par4[12] = {};
426 uint8_t vdencCmd1Par5 = 0;
427 uint8_t vdencCmd1Par6 = 0;
428 uint8_t vdencCmd1Par7 = 0;
429 uint8_t vdencCmd1Par8[4] = {};
430 uint8_t vdencCmd1Par9[4] = {};
431 uint8_t vdencCmd1Par10[4] = {};
432 uint8_t vdencCmd1Par11[4] = {};
433 uint8_t vdencCmd1Par12[4] = {};
434 uint8_t vdencCmd1Par13[4] = {};
435 uint8_t vdencCmd1Par14[4] = {};
436 uint8_t vdencCmd1Par15[4] = {};
437 uint8_t vdencCmd1Par16 = 0;
438 uint8_t vdencCmd1Par17 = 0;
439 uint8_t vdencCmd1Par18 = 0;
440 uint8_t vdencCmd1Par19 = 0;
441 uint8_t vdencCmd1Par20 = 0;
442 uint8_t vdencCmd1Par21 = 0;
443 uint8_t vdencCmd1Par22 = 0;
444 uint8_t vdencCmd1Par23 = 0;
445 uint8_t vdencCmd1Par24 = 0;
446 uint8_t vdencCmd1Par25 = 0;
447 uint8_t vdencCmd1Par26 = 0;
448 uint8_t vdencCmd1Par27 = 0;
449 uint8_t vdencCmd1Par28 = 0;
450 uint8_t vdencCmd1Par29 = 0;
451 uint8_t vdencCmd1Par30 = 0;
452 uint8_t vdencCmd1Par31 = 0;
453 uint8_t vdencCmd1Par32 = 0;
454 uint8_t vdencCmd1Par33 = 0;
455 uint8_t vdencCmd1Par34 = 0;
456 uint8_t vdencCmd1Par35 = 0;
457 uint8_t vdencCmd1Par36 = 0;
458 uint8_t vdencCmd1Par37 = 0;
459 uint8_t vdencCmd1Par38 = 0;
460 uint8_t vdencCmd1Par39 = 0;
461 uint8_t vdencCmd1Par40 = 0;
462 uint8_t vdencCmd1Par41 = 0;
463 uint8_t vdencCmd1Par42 = 0;
464 uint8_t vdencCmd1Par43 = 0;
465 uint8_t vdencCmd1Par44 = 0;
466 uint8_t vdencCmd1Par45 = 0;
467 uint8_t vdencCmd1Par46 = 0;
468 uint8_t vdencCmd1Par47 = 0;
469 uint8_t vdencCmd1Par48 = 0;
470 uint8_t vdencCmd1Par49 = 0;
471 uint8_t vdencCmd1Par50 = 0;
472 uint8_t vdencCmd1Par51 = 0;
473 uint8_t vdencCmd1Par52 = 0;
474 uint8_t vdencCmd1Par53 = 0;
475 uint8_t vdencCmd1Par54 = 0;
476 uint8_t vdencCmd1Par55 = 0;
477 uint8_t vdencCmd1Par56 = 0;
478 uint8_t vdencCmd1Par57 = 0;
479 uint8_t vdencCmd1Par58 = 0;
480 uint8_t vdencCmd1Par59 = 0;
481 uint8_t vdencCmd1Par60 = 0;
482 uint8_t vdencCmd1Par61 = 0;
483 uint8_t vdencCmd1Par62 = 0;
484 uint8_t vdencCmd1Par63 = 0;
485 uint8_t vdencCmd1Par64 = 0;
486 uint8_t vdencCmd1Par65 = 0;
487 uint8_t vdencCmd1Par66 = 0;
488 uint8_t vdencCmd1Par67 = 0;
489 uint8_t vdencCmd1Par68 = 0;
490 uint8_t vdencCmd1Par69 = 0;
491 uint8_t vdencCmd1Par70 = 0;
492 uint8_t vdencCmd1Par71 = 0;
493 uint8_t vdencCmd1Par72 = 0;
494 uint8_t vdencCmd1Par73 = 0;
495 uint8_t vdencCmd1Par74 = 0;
496 uint8_t vdencCmd1Par75 = 0;
497 uint8_t vdencCmd1Par76 = 0;
498 uint8_t vdencCmd1Par77 = 0;
499 uint8_t vdencCmd1Par78 = 0;
500 uint8_t vdencCmd1Par79 = 0;
501 uint8_t vdencCmd1Par80 = 0;
502 uint8_t vdencCmd1Par81 = 0;
503 uint8_t vdencCmd1Par82 = 0;
504 uint8_t vdencCmd1Par83 = 0;
505 uint8_t vdencCmd1Par84 = 0;
506 uint8_t vdencCmd1Par85 = 0;
507 uint8_t vdencCmd1Par86 = 0;
508 uint8_t vdencCmd1Par87 = 0;
509 uint8_t vdencCmd1Par88 = 0;
510 uint8_t vdencCmd1Par89 = 0;
511 uint8_t vdencCmd1Par90 = 0;
512 uint8_t vdencCmd1Par91 = 0;
513 uint8_t vdencCmd1Par92 = 0;
514 uint8_t vdencCmd1Par93 = 0;
515 uint8_t vdencCmd1Par94 = 0;
516 uint8_t vdencCmd1Par95 = 0;
517 uint8_t vdnecCmd1Par96[4] = {};
518 uint8_t vdnecCmd1Par97[4] = {};
519 uint8_t vdnecCmd1Par98[4] = {};
520 uint8_t vdnecCmd1Par99[4] = {};
521 uint8_t vdnecCmd1Par100[2] = {};
522 uint8_t vdnecCmd1Par101[2] = {};
523 uint8_t vdnecCmd1Par102[2] = {};
524 uint8_t vdnecCmd1Par103[2] = {};
525 uint8_t vdencCmd1Par104[4] = {};
526 uint8_t vdencCmd1Par105[4] = {};
527 uint8_t vdencCmd1Par106[4] = {};
528 uint8_t vdencCmd1Par107 = 0;
529 };
530
_MHW_PAR_T(VDENC_CMD2)531 struct _MHW_PAR_T(VDENC_CMD2)
532 {
533 uint32_t width = 0;
534 uint32_t height = 0;
535 bool constrainedIntraPred = false;
536 uint8_t pictureType = 0;
537 bool temporalMvp = false;
538 bool collocatedFromL0 = false;
539 uint8_t longTermReferenceFlagsL0 = 0;
540 uint8_t longTermReferenceFlagsL1 = 0;
541 bool transformSkip = false;
542 int8_t pocL0Ref0 = 1;
543 int8_t pocL1Ref0 = -1;
544 int8_t pocL0Ref1 = 2;
545 int8_t pocL1Ref1 = -2;
546 int8_t pocL0Ref2 = 3;
547 int8_t pocL1Ref2 = -3;
548 int8_t pocL0Ref3 = 4;
549 int8_t pocL1Ref3 = -4;
550 bool roiStreamIn = false;
551 uint8_t numRefL0 = 0;
552 uint8_t numRefL1 = 0;
553 bool segmentation = false;
554 bool segmentationTemporal = false;
555 bool tiling = false;
556 bool vdencStreamIn = false;
557 bool pakOnlyMultiPass = false;
558 uint8_t frameIdxL0Ref0 = 0;
559 uint8_t frameIdxL0Ref1 = 0;
560 uint8_t frameIdxL0Ref2 = 0;
561 uint8_t frameIdxL1Ref0 = 0;
562 uint8_t minQp = 0;
563 uint8_t maxQp = 255;
564 bool temporalMvEnableForIntegerSearch = false;
565 uint16_t intraRefreshPos = 0;
566 uint8_t intraRefreshMbSizeMinus1 = 1;
567 uint8_t intraRefreshMode = 0;
568 bool intraRefresh = false;
569 uint8_t qpAdjustmentForRollingI = 0;
570 uint8_t qpForSegs[8] = {};
571 bool vp9DynamicSlice = false;
572 uint8_t qpPrimeYDc = 0;
573 uint8_t qpPrimeYAc = 0;
574 uint32_t intraRefreshBoundary[3] = {};
575 uint8_t av1RefId[2][4] = {{1, 1, 1, 1}, {1, 1, 1, 1}};
576 uint8_t subPelMode = 3;
577
578 __MHW_VDBOX_VDENC_WRAPPER(
579 std::vector<std::function<MOS_STATUS(uint32_t *)>> extSettings);
580 __MHW_VDBOX_VDENC_WRAPPER_EXT(VDENC_CMD2_CMDPAR_EXT);
581 };
582
_MHW_PAR_T(VDENC_CMD3)583 struct _MHW_PAR_T(VDENC_CMD3)
584 {
585 uint8_t vdencCmd3Par0[8] = {};
586 uint8_t vdencCmd3Par1[12] = {};
587 uint8_t vdencCmd3Par2[12] = {};
588 uint8_t vdencCmd3Par3 = 0;
589 uint8_t vdencCmd3Par4 = 0;
590 uint8_t vdencCmd3Par5 = 0;
591 uint8_t vdencCmd3Par6 = 0;
592 uint8_t vdencCmd3Par7 = 0;
593 uint8_t vdencCmd3Par8 = 0;
594 uint8_t vdencCmd3Par9 = 0;
595 uint8_t vdencCmd3Par10 = 0;
596 uint8_t vdencCmd3Par11 = 0;
597 uint8_t vdencCmd3Par12 = 0;
598 uint8_t vdencCmd3Par13 = 0;
599 uint8_t vdencCmd3Par14 = 0;
600 uint8_t vdencCmd3Par15 = 0;
601 uint8_t vdencCmd3Par16 = 0;
602 uint8_t vdencCmd3Par17 = 0;
603 uint8_t vdencCmd3Par18 = 0;
604 uint8_t vdencCmd3Par19 = 0;
605 uint8_t vdencCmd3Par20 = 0;
606 uint8_t vdencCmd3Par21 = 0;
607 uint8_t vdencCmd3Par22 = 0;
608 uint8_t vdencCmd3Par23 = 0;
609 uint8_t vdencCmd3Par24 = 0;
610 uint8_t vdencCmd3Par25 = 0;
611 uint8_t vdencCmd3Par26 = 0;
612 uint8_t vdencCmd3Par27 = 0;
613 uint8_t vdencCmd3Par28 = 0;
614 uint8_t vdencCmd3Par29 = 0;
615 uint8_t vdencCmd3Par30 = 0;
616 uint16_t vdencCmd3Par31 = 0;
617 uint16_t vdencCmd3Par32 = 0;
618 };
619 } // namespace vdenc
620 } // namespace vdbox
621 } // namespace mhw
622
623 #endif // __MHW_VDBOX_VDENC_CMDPAR_H__
624