1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * SPDX-License-Identifier: MIT
9 */
10
11 #ifndef RADV_PIPELINE_GRAPHICS_H
12 #define RADV_PIPELINE_GRAPHICS_H
13
14 #include "sid.h"
15
16 #include "radv_descriptor_set.h"
17 #include "radv_pipeline.h"
18 #include "radv_shader.h"
19
20 #include "vk_graphics_state.h"
21
22 struct radv_sample_locations_state {
23 VkSampleCountFlagBits per_pixel;
24 VkExtent2D grid_size;
25 uint32_t count;
26 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
27 };
28
29 struct radv_dynamic_state {
30 struct vk_dynamic_graphics_state vk;
31
32 /**
33 * Bitmask of (1ull << VK_DYNAMIC_STATE_*).
34 * Defines the set of saved dynamic state.
35 */
36 uint64_t mask;
37
38 struct {
39 struct {
40 float scale[3];
41 float translate[3];
42 } xform[MAX_VIEWPORTS];
43 } hw_vp;
44
45 struct radv_sample_locations_state sample_location;
46
47 VkImageAspectFlags feedback_loop_aspects;
48 };
49
50 struct radv_multisample_state {
51 bool sample_shading_enable;
52 float min_sample_shading;
53 };
54
55 struct radv_ia_multi_vgt_param_helpers {
56 uint32_t base;
57 bool partial_es_wave;
58 bool ia_switch_on_eoi;
59 bool partial_vs_wave;
60 };
61
62 struct radv_sqtt_shaders_reloc {
63 struct radeon_winsys_bo *bo;
64 union radv_shader_arena_block *alloc;
65 uint64_t va[MESA_VULKAN_SHADER_STAGES];
66 };
67
68 struct radv_graphics_pipeline {
69 struct radv_pipeline base;
70
71 bool uses_drawid;
72 bool uses_baseinstance;
73
74 /* Whether the pipeline forces per-vertex VRS (GFX10.3+). */
75 bool force_vrs_per_vertex;
76
77 /* Whether the pipeline uses NGG (GFX10+). */
78 bool is_ngg;
79 bool has_ngg_culling;
80
81 uint8_t vtx_emit_num;
82
83 uint32_t vtx_base_sgpr;
84 uint64_t dynamic_states;
85 uint64_t needed_dynamic_state;
86
87 VkShaderStageFlags active_stages;
88
89 uint32_t spi_shader_col_format;
90 uint32_t cb_shader_mask;
91
92 struct radv_dynamic_state dynamic_state;
93
94 struct radv_vertex_input_state vertex_input;
95
96 struct radv_multisample_state ms;
97 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
98 uint32_t binding_stride[MAX_VBS];
99 uint32_t db_render_control;
100
101 /* Last pre-PS API stage */
102 gl_shader_stage last_vgt_api_stage;
103
104 unsigned rast_prim;
105
106
107 /* Custom blend mode for internal operations. */
108 unsigned custom_blend_mode;
109
110 /* Whether the pipeline uses out-of-order rasterization. */
111 bool uses_out_of_order_rast;
112
113 /* Whether the pipeline uses VRS. */
114 bool uses_vrs;
115
116 /* Whether the pipeline uses a VRS attachment. */
117 bool uses_vrs_attachment;
118
119 /* Whether the pipeline uses VRS coarse shading internally. */
120 bool uses_vrs_coarse_shading;
121
122 /* For relocation of shaders with RGP. */
123 struct radv_sqtt_shaders_reloc *sqtt_shaders_reloc;
124
125 /* Whether the pipeline imported binaries. */
126 bool has_pipeline_binaries;
127 };
128
129 RADV_DECL_PIPELINE_DOWNCAST(graphics, RADV_PIPELINE_GRAPHICS)
130
131 struct radv_retained_shaders {
132 struct {
133 void *serialized_nir;
134 size_t serialized_nir_size;
135 unsigned char shader_sha1[SHA1_DIGEST_LENGTH];
136 struct radv_shader_stage_key key;
137 } stages[MESA_VULKAN_SHADER_STAGES];
138 };
139
140 struct radv_graphics_lib_pipeline {
141 struct radv_graphics_pipeline base;
142
143 struct vk_graphics_pipeline_state graphics_state;
144
145 /* For vk_graphics_pipeline_state */
146 void *state_data;
147
148 struct radv_pipeline_layout layout;
149
150 VkGraphicsPipelineLibraryFlagsEXT lib_flags;
151
152 struct radv_retained_shaders retained_shaders;
153
154 void *mem_ctx;
155
156 unsigned stage_count;
157 VkPipelineShaderStageCreateInfo *stages;
158 struct radv_shader_stage_key stage_keys[MESA_VULKAN_SHADER_STAGES];
159 };
160
RADV_DECL_PIPELINE_DOWNCAST(graphics_lib,RADV_PIPELINE_GRAPHICS_LIB)161 RADV_DECL_PIPELINE_DOWNCAST(graphics_lib, RADV_PIPELINE_GRAPHICS_LIB)
162
163 static inline bool
164 radv_pipeline_has_stage(const struct radv_graphics_pipeline *pipeline, gl_shader_stage stage)
165 {
166 return pipeline->base.shaders[stage];
167 }
168
169 static inline uint32_t
radv_conv_prim_to_gs_out(uint32_t topology,bool is_ngg)170 radv_conv_prim_to_gs_out(uint32_t topology, bool is_ngg)
171 {
172 switch (topology) {
173 case V_008958_DI_PT_POINTLIST:
174 case V_008958_DI_PT_PATCH:
175 return V_028A6C_POINTLIST;
176 case V_008958_DI_PT_LINELIST:
177 case V_008958_DI_PT_LINESTRIP:
178 case V_008958_DI_PT_LINELIST_ADJ:
179 case V_008958_DI_PT_LINESTRIP_ADJ:
180 return V_028A6C_LINESTRIP;
181 case V_008958_DI_PT_TRILIST:
182 case V_008958_DI_PT_TRISTRIP:
183 case V_008958_DI_PT_TRIFAN:
184 case V_008958_DI_PT_TRILIST_ADJ:
185 case V_008958_DI_PT_TRISTRIP_ADJ:
186 return V_028A6C_TRISTRIP;
187 case V_008958_DI_PT_RECTLIST:
188 return is_ngg ? V_028A6C_RECTLIST : V_028A6C_TRISTRIP;
189 default:
190 assert(0);
191 return 0;
192 }
193 }
194
195 static inline uint32_t
radv_conv_gl_prim_to_gs_out(unsigned gl_prim)196 radv_conv_gl_prim_to_gs_out(unsigned gl_prim)
197 {
198 switch (gl_prim) {
199 case MESA_PRIM_POINTS:
200 return V_028A6C_POINTLIST;
201 case MESA_PRIM_LINES:
202 case MESA_PRIM_LINE_STRIP:
203 case MESA_PRIM_LINES_ADJACENCY:
204 return V_028A6C_LINESTRIP;
205
206 case MESA_PRIM_TRIANGLES:
207 case MESA_PRIM_TRIANGLE_STRIP_ADJACENCY:
208 case MESA_PRIM_TRIANGLE_STRIP:
209 case MESA_PRIM_QUADS:
210 return V_028A6C_TRISTRIP;
211 default:
212 assert(0);
213 return 0;
214 }
215 }
216
217 static inline uint32_t
radv_translate_prim(unsigned topology)218 radv_translate_prim(unsigned topology)
219 {
220 switch (topology) {
221 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
222 return V_008958_DI_PT_POINTLIST;
223 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
224 return V_008958_DI_PT_LINELIST;
225 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
226 return V_008958_DI_PT_LINESTRIP;
227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
228 return V_008958_DI_PT_TRILIST;
229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
230 return V_008958_DI_PT_TRISTRIP;
231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
232 return V_008958_DI_PT_TRIFAN;
233 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
234 return V_008958_DI_PT_LINELIST_ADJ;
235 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
236 return V_008958_DI_PT_LINESTRIP_ADJ;
237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
238 return V_008958_DI_PT_TRILIST_ADJ;
239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
240 return V_008958_DI_PT_TRISTRIP_ADJ;
241 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
242 return V_008958_DI_PT_PATCH;
243 default:
244 unreachable("unhandled primitive type");
245 }
246 }
247
248 static inline bool
radv_prim_is_points_or_lines(unsigned topology)249 radv_prim_is_points_or_lines(unsigned topology)
250 {
251 switch (topology) {
252 case V_008958_DI_PT_POINTLIST:
253 case V_008958_DI_PT_LINELIST:
254 case V_008958_DI_PT_LINESTRIP:
255 case V_008958_DI_PT_LINELIST_ADJ:
256 case V_008958_DI_PT_LINESTRIP_ADJ:
257 return true;
258 default:
259 return false;
260 }
261 }
262
263 static inline bool
radv_rast_prim_is_point(unsigned rast_prim)264 radv_rast_prim_is_point(unsigned rast_prim)
265 {
266 return rast_prim == V_028A6C_POINTLIST;
267 }
268
269 static inline bool
radv_rast_prim_is_line(unsigned rast_prim)270 radv_rast_prim_is_line(unsigned rast_prim)
271 {
272 return rast_prim == V_028A6C_LINESTRIP;
273 }
274
275 static inline bool
radv_rast_prim_is_points_or_lines(unsigned rast_prim)276 radv_rast_prim_is_points_or_lines(unsigned rast_prim)
277 {
278 return radv_rast_prim_is_point(rast_prim) || radv_rast_prim_is_line(rast_prim);
279 }
280
281 static inline bool
radv_polygon_mode_is_point(unsigned polygon_mode)282 radv_polygon_mode_is_point(unsigned polygon_mode)
283 {
284 return polygon_mode == V_028814_X_DRAW_POINTS;
285 }
286
287 static inline bool
radv_polygon_mode_is_line(unsigned polygon_mode)288 radv_polygon_mode_is_line(unsigned polygon_mode)
289 {
290 return polygon_mode == V_028814_X_DRAW_LINES;
291 }
292
293 static inline bool
radv_polygon_mode_is_points_or_lines(unsigned polygon_mode)294 radv_polygon_mode_is_points_or_lines(unsigned polygon_mode)
295 {
296 return radv_polygon_mode_is_point(polygon_mode) || radv_polygon_mode_is_line(polygon_mode);
297 }
298
299 static inline bool
radv_primitive_topology_is_line_list(unsigned primitive_topology)300 radv_primitive_topology_is_line_list(unsigned primitive_topology)
301 {
302 return primitive_topology == V_008958_DI_PT_LINELIST || primitive_topology == V_008958_DI_PT_LINELIST_ADJ;
303 }
304
305 static inline unsigned
radv_get_num_vertices_per_prim(const struct radv_graphics_state_key * gfx_state)306 radv_get_num_vertices_per_prim(const struct radv_graphics_state_key *gfx_state)
307 {
308 if (gfx_state->ia.topology == V_008958_DI_PT_NONE) {
309 /* When the topology is unknown (with graphics pipeline library), return the maximum number of
310 * vertices per primitives for VS. This is used to lower NGG (the HW will ignore the extra
311 * bits for points/lines) and also to enable NGG culling unconditionally (it will be disabled
312 * dynamically for points/lines).
313 */
314 return 3;
315 } else {
316 /* Need to add 1, because: V_028A6C_POINTLIST=0, V_028A6C_LINESTRIP=1, V_028A6C_TRISTRIP=2, etc. */
317 return radv_conv_prim_to_gs_out(gfx_state->ia.topology, false) + 1;
318 }
319 }
320
321 static inline uint32_t
radv_translate_fill(VkPolygonMode func)322 radv_translate_fill(VkPolygonMode func)
323 {
324 switch (func) {
325 case VK_POLYGON_MODE_FILL:
326 return V_028814_X_DRAW_TRIANGLES;
327 case VK_POLYGON_MODE_LINE:
328 return V_028814_X_DRAW_LINES;
329 case VK_POLYGON_MODE_POINT:
330 return V_028814_X_DRAW_POINTS;
331 default:
332 assert(0);
333 return V_028814_X_DRAW_POINTS;
334 }
335 }
336
337 static inline uint32_t
radv_translate_stencil_op(enum VkStencilOp op)338 radv_translate_stencil_op(enum VkStencilOp op)
339 {
340 switch (op) {
341 case VK_STENCIL_OP_KEEP:
342 return V_02842C_STENCIL_KEEP;
343 case VK_STENCIL_OP_ZERO:
344 return V_02842C_STENCIL_ZERO;
345 case VK_STENCIL_OP_REPLACE:
346 return V_02842C_STENCIL_REPLACE_TEST;
347 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
348 return V_02842C_STENCIL_ADD_CLAMP;
349 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
350 return V_02842C_STENCIL_SUB_CLAMP;
351 case VK_STENCIL_OP_INVERT:
352 return V_02842C_STENCIL_INVERT;
353 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
354 return V_02842C_STENCIL_ADD_WRAP;
355 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
356 return V_02842C_STENCIL_SUB_WRAP;
357 default:
358 return 0;
359 }
360 }
361
362 static inline uint32_t
radv_translate_blend_logic_op(VkLogicOp op)363 radv_translate_blend_logic_op(VkLogicOp op)
364 {
365 switch (op) {
366 case VK_LOGIC_OP_CLEAR:
367 return V_028808_ROP3_CLEAR;
368 case VK_LOGIC_OP_AND:
369 return V_028808_ROP3_AND;
370 case VK_LOGIC_OP_AND_REVERSE:
371 return V_028808_ROP3_AND_REVERSE;
372 case VK_LOGIC_OP_COPY:
373 return V_028808_ROP3_COPY;
374 case VK_LOGIC_OP_AND_INVERTED:
375 return V_028808_ROP3_AND_INVERTED;
376 case VK_LOGIC_OP_NO_OP:
377 return V_028808_ROP3_NO_OP;
378 case VK_LOGIC_OP_XOR:
379 return V_028808_ROP3_XOR;
380 case VK_LOGIC_OP_OR:
381 return V_028808_ROP3_OR;
382 case VK_LOGIC_OP_NOR:
383 return V_028808_ROP3_NOR;
384 case VK_LOGIC_OP_EQUIVALENT:
385 return V_028808_ROP3_EQUIVALENT;
386 case VK_LOGIC_OP_INVERT:
387 return V_028808_ROP3_INVERT;
388 case VK_LOGIC_OP_OR_REVERSE:
389 return V_028808_ROP3_OR_REVERSE;
390 case VK_LOGIC_OP_COPY_INVERTED:
391 return V_028808_ROP3_COPY_INVERTED;
392 case VK_LOGIC_OP_OR_INVERTED:
393 return V_028808_ROP3_OR_INVERTED;
394 case VK_LOGIC_OP_NAND:
395 return V_028808_ROP3_NAND;
396 case VK_LOGIC_OP_SET:
397 return V_028808_ROP3_SET;
398 default:
399 unreachable("Unhandled logic op");
400 }
401 }
402
403 static inline uint32_t
radv_translate_blend_function(VkBlendOp op)404 radv_translate_blend_function(VkBlendOp op)
405 {
406 switch (op) {
407 case VK_BLEND_OP_ADD:
408 return V_028780_COMB_DST_PLUS_SRC;
409 case VK_BLEND_OP_SUBTRACT:
410 return V_028780_COMB_SRC_MINUS_DST;
411 case VK_BLEND_OP_REVERSE_SUBTRACT:
412 return V_028780_COMB_DST_MINUS_SRC;
413 case VK_BLEND_OP_MIN:
414 return V_028780_COMB_MIN_DST_SRC;
415 case VK_BLEND_OP_MAX:
416 return V_028780_COMB_MAX_DST_SRC;
417 default:
418 return 0;
419 }
420 }
421
422 static inline uint32_t
radv_translate_blend_factor(enum amd_gfx_level gfx_level,VkBlendFactor factor)423 radv_translate_blend_factor(enum amd_gfx_level gfx_level, VkBlendFactor factor)
424 {
425 switch (factor) {
426 case VK_BLEND_FACTOR_ZERO:
427 return V_028780_BLEND_ZERO;
428 case VK_BLEND_FACTOR_ONE:
429 return V_028780_BLEND_ONE;
430 case VK_BLEND_FACTOR_SRC_COLOR:
431 return V_028780_BLEND_SRC_COLOR;
432 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
433 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
434 case VK_BLEND_FACTOR_DST_COLOR:
435 return V_028780_BLEND_DST_COLOR;
436 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
437 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
438 case VK_BLEND_FACTOR_SRC_ALPHA:
439 return V_028780_BLEND_SRC_ALPHA;
440 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
441 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
442 case VK_BLEND_FACTOR_DST_ALPHA:
443 return V_028780_BLEND_DST_ALPHA;
444 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
445 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
446 case VK_BLEND_FACTOR_CONSTANT_COLOR:
447 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_COLOR_GFX11 : V_028780_BLEND_CONSTANT_COLOR_GFX6;
448 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
449 return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX11
450 : V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX6;
451 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
452 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_ALPHA_GFX11 : V_028780_BLEND_CONSTANT_ALPHA_GFX6;
453 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
454 return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX11
455 : V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX6;
456 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
457 return V_028780_BLEND_SRC_ALPHA_SATURATE;
458 case VK_BLEND_FACTOR_SRC1_COLOR:
459 return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_COLOR_GFX11 : V_028780_BLEND_SRC1_COLOR_GFX6;
460 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
461 return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_COLOR_GFX11 : V_028780_BLEND_INV_SRC1_COLOR_GFX6;
462 case VK_BLEND_FACTOR_SRC1_ALPHA:
463 return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_ALPHA_GFX11 : V_028780_BLEND_SRC1_ALPHA_GFX6;
464 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
465 return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_ALPHA_GFX11 : V_028780_BLEND_INV_SRC1_ALPHA_GFX6;
466 default:
467 return 0;
468 }
469 }
470
471 static inline uint32_t
radv_translate_blend_opt_factor(VkBlendFactor factor,bool is_alpha)472 radv_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
473 {
474 switch (factor) {
475 case VK_BLEND_FACTOR_ZERO:
476 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
477 case VK_BLEND_FACTOR_ONE:
478 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
479 case VK_BLEND_FACTOR_SRC_COLOR:
480 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
481 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
482 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
483 case VK_BLEND_FACTOR_SRC_ALPHA:
484 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
485 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
486 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
487 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
488 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
489 default:
490 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
491 }
492 }
493
494 static inline uint32_t
radv_translate_blend_opt_function(VkBlendOp op)495 radv_translate_blend_opt_function(VkBlendOp op)
496 {
497 switch (op) {
498 case VK_BLEND_OP_ADD:
499 return V_028760_OPT_COMB_ADD;
500 case VK_BLEND_OP_SUBTRACT:
501 return V_028760_OPT_COMB_SUBTRACT;
502 case VK_BLEND_OP_REVERSE_SUBTRACT:
503 return V_028760_OPT_COMB_REVSUBTRACT;
504 case VK_BLEND_OP_MIN:
505 return V_028760_OPT_COMB_MIN;
506 case VK_BLEND_OP_MAX:
507 return V_028760_OPT_COMB_MAX;
508 default:
509 return V_028760_OPT_COMB_BLEND_DISABLED;
510 }
511 }
512
513 static inline bool
radv_blend_factor_uses_dst(VkBlendFactor factor)514 radv_blend_factor_uses_dst(VkBlendFactor factor)
515 {
516 return factor == VK_BLEND_FACTOR_DST_COLOR || factor == VK_BLEND_FACTOR_DST_ALPHA ||
517 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
518 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
519 }
520
521 static inline bool
radv_is_dual_src(VkBlendFactor factor)522 radv_is_dual_src(VkBlendFactor factor)
523 {
524 switch (factor) {
525 case VK_BLEND_FACTOR_SRC1_COLOR:
526 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
527 case VK_BLEND_FACTOR_SRC1_ALPHA:
528 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
529 return true;
530 default:
531 return false;
532 }
533 }
534
535 static ALWAYS_INLINE bool
radv_can_enable_dual_src(const struct vk_color_blend_attachment_state * att)536 radv_can_enable_dual_src(const struct vk_color_blend_attachment_state *att)
537 {
538 VkBlendOp eqRGB = att->color_blend_op;
539 VkBlendFactor srcRGB = att->src_color_blend_factor;
540 VkBlendFactor dstRGB = att->dst_color_blend_factor;
541 VkBlendOp eqA = att->alpha_blend_op;
542 VkBlendFactor srcA = att->src_alpha_blend_factor;
543 VkBlendFactor dstA = att->dst_alpha_blend_factor;
544 bool eqRGB_minmax = eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX;
545 bool eqA_minmax = eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX;
546
547 if (!eqRGB_minmax && (radv_is_dual_src(srcRGB) || radv_is_dual_src(dstRGB)))
548 return true;
549 if (!eqA_minmax && (radv_is_dual_src(srcA) || radv_is_dual_src(dstA)))
550 return true;
551 return false;
552 }
553
554 static inline void
radv_normalize_blend_factor(VkBlendOp op,VkBlendFactor * src_factor,VkBlendFactor * dst_factor)555 radv_normalize_blend_factor(VkBlendOp op, VkBlendFactor *src_factor, VkBlendFactor *dst_factor)
556 {
557 if (op == VK_BLEND_OP_MIN || op == VK_BLEND_OP_MAX) {
558 *src_factor = VK_BLEND_FACTOR_ONE;
559 *dst_factor = VK_BLEND_FACTOR_ONE;
560 }
561 }
562
563 void radv_blend_remove_dst(VkBlendOp *func, VkBlendFactor *src_factor, VkBlendFactor *dst_factor,
564 VkBlendFactor expected_dst, VkBlendFactor replacement_src);
565
566 unsigned radv_compact_spi_shader_col_format(uint32_t spi_shader_col_format);
567
568 unsigned radv_format_meta_fs_key(struct radv_device *device, VkFormat format);
569
570 struct radv_ia_multi_vgt_param_helpers radv_compute_ia_multi_vgt_param(const struct radv_device *device,
571 struct radv_shader *const *shaders);
572
573 void radv_get_viewport_xform(const VkViewport *viewport, float scale[3], float translate[3]);
574
575 struct radv_shader *radv_get_shader(struct radv_shader *const *shaders, gl_shader_stage stage);
576
577 struct radv_ps_epilog_state {
578 uint8_t color_attachment_count;
579 VkFormat color_attachment_formats[MAX_RTS];
580 uint8_t color_attachment_mappings[MAX_RTS];
581
582 uint32_t color_write_mask;
583 uint32_t color_blend_enable;
584
585 uint32_t colors_written;
586 bool mrt0_is_dual_src;
587 bool export_depth;
588 bool export_stencil;
589 bool export_sample_mask;
590 bool alpha_to_coverage_via_mrtz;
591 bool alpha_to_one;
592 uint8_t need_src_alpha;
593 };
594
595 struct radv_ps_epilog_key radv_generate_ps_epilog_key(const struct radv_device *device,
596 const struct radv_ps_epilog_state *state);
597
598 void radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cache *cache,
599 struct radv_shader_stage *stages, const struct radv_graphics_state_key *gfx_state,
600 bool keep_executable_info, bool keep_statistic_info, bool is_internal,
601 struct radv_retained_shaders *retained_shaders, bool noop_fs,
602 struct radv_shader **shaders, struct radv_shader_binary **binaries,
603 struct radv_shader **gs_copy_shader, struct radv_shader_binary **gs_copy_binary);
604
605 struct radv_vgt_shader_key {
606 uint8_t tess : 1;
607 uint8_t gs : 1;
608 uint8_t mesh_scratch_ring : 1;
609 uint8_t mesh : 1;
610 uint8_t ngg_passthrough : 1;
611 uint8_t ngg : 1; /* gfx10+ */
612 uint8_t ngg_streamout : 1;
613 uint8_t hs_wave32 : 1;
614 uint8_t gs_wave32 : 1;
615 uint8_t vs_wave32 : 1;
616 };
617
618 struct radv_vgt_shader_key radv_get_vgt_shader_key(const struct radv_device *device, struct radv_shader **shaders,
619 const struct radv_shader *gs_copy_shader);
620
621 uint32_t radv_get_vgt_gs_out(struct radv_shader **shaders, uint32_t primitive_topology);
622
623 bool radv_needs_null_export_workaround(const struct radv_device *device, const struct radv_shader *ps,
624 unsigned custom_blend_mode);
625
626 struct radv_graphics_pipeline_create_info {
627 bool use_rectlist;
628 bool db_depth_clear;
629 bool db_stencil_clear;
630 bool depth_compress_disable;
631 bool stencil_compress_disable;
632 uint32_t custom_blend_mode;
633 };
634
635 VkResult radv_graphics_pipeline_create(VkDevice device, VkPipelineCache cache,
636 const VkGraphicsPipelineCreateInfo *pCreateInfo,
637 const struct radv_graphics_pipeline_create_info *extra,
638 const VkAllocationCallbacks *alloc, VkPipeline *pPipeline);
639
640 void radv_destroy_graphics_pipeline(struct radv_device *device, struct radv_graphics_pipeline *pipeline);
641
642 void radv_destroy_graphics_lib_pipeline(struct radv_device *device, struct radv_graphics_lib_pipeline *pipeline);
643
644 struct radv_graphics_pipeline_state {
645 struct vk_graphics_pipeline_state vk;
646 void *vk_data;
647
648 bool compilation_required;
649
650 struct radv_shader_stage *stages;
651
652 struct radv_graphics_pipeline_key key;
653
654 struct radv_pipeline_layout layout;
655 };
656
657 void radv_graphics_pipeline_hash(const struct radv_device *device, const struct radv_graphics_pipeline_state *gfx_state,
658 unsigned char *hash);
659
660 VkResult radv_generate_graphics_pipeline_state(struct radv_device *device,
661 const VkGraphicsPipelineCreateInfo *pCreateInfo,
662 struct radv_graphics_pipeline_state *gfx_state);
663
664 void radv_graphics_pipeline_state_finish(struct radv_device *device, struct radv_graphics_pipeline_state *gfx_state);
665
666 #endif /* RADV_PIPELINE_GRAPHICS_H */
667