1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_GPIO_H_ 4 #define _SOC_GPIO_H_ 5 6 #include <stdint.h> 7 #include <soc/gpio_defs.h> 8 #include <soc/iomap.h> 9 10 #define CROS_GPIO_DEVICE_NAME "Braswell" 11 12 #define COMMUNITY_SIZE 0x20000 13 14 #define COMMUNITY_GPSOUTHWEST_BASE \ 15 (IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHWEST) 16 17 #define COMMUNITY_GPNORTH_BASE \ 18 (IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH) 19 20 #define COMMUNITY_GPEAST_BASE \ 21 (IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPEAST) 22 23 #define COMMUNITY_GPSOUTHEAST_BASE \ 24 (IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHEAST) 25 26 #define GPIO_COMMUNITY_COUNT 4 27 #define GPIO_FAMILIES_MAX_PER_COMM 7 28 #define GP_SOUTHWEST 0 29 #define GP_NORTH 1 30 #define GP_EAST 2 31 #define GP_SOUTHEAST 3 32 33 #define COMMUNITY_BASE(community) \ 34 (IO_BASE_ADDRESS + community * 0x8000) 35 36 #define GP_READ_ACCESS_POLICY_BASE(community) \ 37 (COMMUNITY_BASE(community) + 0x000) 38 39 #define GP_WRITE_ACCESS_POLICY_BASE(community) \ 40 (COMMUNITY_BASE(community) + 0x100) 41 42 #define GP_WAKE_STATUS_REG_BASE(community) \ 43 (COMMUNITY_BASE(community) + 0x200) 44 45 #define GP_WAKE_MASK_REG_BASE(community) \ 46 (COMMUNITY_BASE(community) + 0x280) 47 48 #define GP_INT_STATUS_REG_BASE(community) \ 49 (COMMUNITY_BASE(community) + 0x300) 50 51 #define GP_INT_MASK_REG_BASE(community) \ 52 (COMMUNITY_BASE(community) + 0x380) 53 54 #define GP_FAMILY_RCOMP_CTRL(community, family) \ 55 (COMMUNITY_BASE(community) + 0x1080 + 0x80 * family) 56 57 #define GP_FAMILY_RCOMP_OFFSET(community, family) \ 58 (COMMUNITY_BASE(community) + 0x1084 + 0x80 * family) 59 60 #define GP_FAMILY_RCOMP_OVERRIDE(community, family) \ 61 (COMMUNITY_BASE(community) + 0x1088 + 0x80 * family) 62 63 #define GP_FAMILY_RCOMP_VALUE(community, family) \ 64 (COMMUNITY_BASE(community) + 0x108C + 0x80 * family) 65 66 #define GP_FAMILY_CONF_COMP(community, family) \ 67 (COMMUNITY_BASE(community) + 0x1090 + 0x80 * family) 68 69 #define GP_FAMILY_CONF_REG(community, family) \ 70 (COMMUNITY_BASE(community) + 0x1094 + 0x80 * family) 71 72 /* Value written into pad control reg 0 */ 73 #define PAD_CONTROL_REG0_TRISTATE (PAD_CONFIG0_DEFAULT|PAD_GPIOFG_HI_Z) 74 75 /* Calculate the MMIO Address for specific GPIO pin 76 * control register pointed by index. 77 */ 78 #define FAMILY_NUMBER(gpio_pad) (gpio_pad / MAX_FAMILY_PAD_GPIO_NO) 79 #define INTERNAL_PAD_NUM(gpio_pad) (gpio_pad % MAX_FAMILY_PAD_GPIO_NO) 80 #define GPIO_OFFSET(gpio_pad) (FAMILY_PAD_REGS_OFF \ 81 + (FAMILY_PAD_REGS_SIZE * FAMILY_NUMBER(gpio_pad) \ 82 + (GPIO_REGS_SIZE * INTERNAL_PAD_NUM(gpio_pad)))) 83 84 /* Gpio to Pad mapping */ 85 #define SDMMC1_CMD_MMIO_OFFSET GPIO_OFFSET(23) 86 #define SDMMC1_D0_MMIO_OFFSET GPIO_OFFSET(17) 87 #define SDMMC1_D1_MMIO_OFFSET GPIO_OFFSET(24) 88 #define SDMMC1_D2_MMIO_OFFSET GPIO_OFFSET(20) 89 #define SDMMC1_D3_MMIO_OFFSET GPIO_OFFSET(26) 90 #define MMC1_D4_SD_WE_MMIO_OFFSET GPIO_OFFSET(67) 91 #define MMC1_D5_MMIO_OFFSET GPIO_OFFSET(65) 92 #define MMC1_D6_MMIO_OFFSET GPIO_OFFSET(63) 93 #define MMC1_D7_MMIO_OFFSET GPIO_OFFSET(68) 94 #define MMC1_RCLK_OFFSET GPIO_OFFSET(69) 95 #define HV_DDI2_DDC_SDA_MMIO_OFFSET GPIO_OFFSET(62) 96 #define HV_DDI2_DDC_SCL_MMIO_OFFSET GPIO_OFFSET(67) 97 #define CFIO_139_MMIO_OFFSET GPIO_OFFSET(64) 98 #define CFIO_140_MMIO_OFFSET GPIO_OFFSET(67) 99 100 /* GPIO Security registers offset */ 101 #define GPIO_READ_ACCESS_POLICY_REG 0x0000 102 #define GPIO_WRITE_ACCESS_POLICY_REG 0x0100 103 #define GPIO_WAKE_STATUS_REG 0x0200 104 #define GPIO_WAKE_MASK_REG0 0x0280 105 #define GPIO_WAKE_MASK_REG1 0x0284 106 #define GPIO_INTERRUPT_STATUS 0x0300 107 #define GPIO_INTERRUPT_MASK 0x0380 108 #define GPE0A_STS_REG 0x20 109 #define GPE0A_EN_REG 0x28 110 #define ALT_GPIO_SMI_REG 0x38 111 #define GPIO_ROUT_REG 0x58 112 113 /* Pad register offset */ 114 #define PAD_CONF0_REG 0x0 115 #define PAD_CONF1_REG 0x4 116 117 /* Number of GPIOs in each bank */ 118 #define GP_SOUTHWEST_COUNT 56 119 #define GP_NORTH_COUNT 59 120 #define GP_EAST_COUNT 24 121 #define GP_SOUTHEAST_COUNT 55 122 123 #define MAX_GPIO_CNT (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT + GP_SOUTHEAST_COUNT) 124 125 /* General */ 126 #define GPIO_REGS_SIZE 8 127 #define NA 0 128 #define MASK_WAKE 0 129 #define UNMASK_WAKE 1 130 #define GPE_CAPABLE 1 131 #define GPE_CAPABLE_NONE 0 132 133 #define MAX_FAMILY_PAD_GPIO_NO 15 134 #define FAMILY_PAD_REGS_OFF 0x4400 135 #define FAMILY_PAD_REGS_SIZE 0x400 136 137 /* config0[31:28] - Interrupt Selection Interrupt Select */ 138 #define PAD_INT_SEL(int_s) (int_s << 28) 139 140 /* config0[27:26] - Glitch Filter Config */ 141 #define PAD_GFCFG(glitch_cfg) (glitch_cfg << 26) 142 #define PAD_GFCFG_DISABLE (0 << 26) 143 #define PAD_ENABLE_EDGE_DETECTION (1 << 26) /* EDGE DETECTION ONLY */ 144 #define PAD_ENABLE_RX_DETECTION (2 << 26) /* RX DETECTION ONLY */ 145 #define PAD_ENABLE_EDGE_RX_DETECTION (3 << 26) /* RX & EDGE DETECTION */ 146 147 /* config0[25:24] - RX/TX Enable Config */ 148 #define PAD_FUNC_CTRL(tx_rx_enable) (tx_rx_enable << 24) 149 #define PAD_FUNC_CTRL_RX_TX_ENABLE (0 << 24) 150 #define PAD_FUNC_CTRL_TX_ENABLE_RX_DISABLE (1 << 24) 151 #define PAD_FUNC_CTRL_TX_ENABLE_RX_ENABLE (2 << 24) 152 #define PAD_TX_RX_ENABLE (3 << 24) 153 154 /* config0[23:20] - Termination */ 155 #define PAD_PULL(TERM) (TERM << 20) 156 #define PAD_PULL_DISABLE (0 << 20) 157 #define PAD_PULL_DOWN_20K (1 << 20) 158 #define PAD_PULL_DOWN_5K (2 << 20) 159 #define PAD_PULL_DOWN_1K (4 << 20) 160 #define PAD_PULL_UP_20K (9 << 20) 161 #define PAD_PULL_UP_5K (10 << 20) 162 #define PAD_PULL_UP_1K (12 << 20) 163 164 /* config0[19:16] - PAD Mode */ 165 #define PAD_MODE_SELECTION(MODE_SEL) (MODE_SEL<<16) 166 167 #define SET_PAD_MODE_SELECTION(pad_config, mode) \ 168 ((pad_config & 0xfff0ffff) | PAD_MODE_SELECTION(mode)) 169 170 /* config0[15] - GPIO Enable */ 171 #define PAD_GPIO_DISABLE (0 << 15) 172 #define PAD_GPIO_ENABLE (1 << 15) 173 174 /* config0[14:11] - Reserver2 */ 175 176 /* config0[10:8] - GPIO Config */ 177 #define PAD_GPIO_CFG(gpio_cfg) (gpio_cfg << 8) 178 #define PAD_GPIOFG_GPIO (0 << 8) 179 #define PAD_GPIOFG_GPO (1 << 8) 180 #define PAD_GPIOFG_GPI (2 << 8) 181 #define PAD_GPIOFG_HI_Z (3 << 8) 182 183 /* config0[7] - Gpio Light Mode Bar */ 184 /* config0[6:2] - Reserved1 */ 185 /* config0[1] - GPIO TX State */ 186 #define PAD_DEFAULT_TX(STATE) (STATE<<1) 187 /* config0[0] - GPIO RX State */ 188 #define PAD_RX_BIT 1 189 190 /* Pad Control Register 1 configuration */ 191 #define PAD_DISABLE_INT (0 << 0) 192 #define PAD_TRIG_EDGE_LOW (1 << 0) 193 #define PAD_TRIG_EDGE_HIGH (2 << 0) 194 #define PAD_TRIG_EDGE_BOTH (3 << 0) 195 #define PAD_TRIG_EDGE_LEVEL (4 << 0) 196 197 /* Pad config0 power-on values */ 198 #define PAD_CONFIG0_DEFAULT 0x00010300 199 #define PAD_CONFIG0_DEFAULT0 0x00910300 200 #define PAD_CONFIG0_DEFAULT1 0x00110300 201 #define PAD_CONFIG0_GPI_DEFAULT 0x00010200 202 203 /* Pad config1 reg power-on values */ 204 #define PAD_CONFIG1_DEFAULT0 0x05C00000 205 #define PAD_CONFIG1_CSEN 0x0DC00000 206 #define PAD_CONFIG1_DEFAULT1 0x05C00020 207 208 #define GPIO_INPUT_PULL(pull) \ 209 { .pad_conf0 = pull | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT, \ 210 .pad_conf1 = PAD_CONFIG1_DEFAULT0 } 211 212 #define GPIO_INPUT_NO_PULL GPIO_INPUT_PULL(PAD_PULL_DISABLE) 213 #define GPIO_INPUT_PU_20K GPIO_INPUT_PULL(PAD_PULL_UP_20K) 214 #define GPIO_INPUT_PU_5K GPIO_INPUT_PULL(PAD_PULL_UP_5K) 215 #define GPIO_INPUT_PU_1K GPIO_INPUT_PULL(PAD_PULL_UP_1K) 216 #define GPIO_INPUT_PD_20K GPIO_INPUT_PULL(PAD_PULL_DOWN_20K) 217 #define GPIO_INPUT_PD_5K GPIO_INPUT_PULL(PAD_PULL_DOWN_5K) 218 #define GPIO_INPUT_PD_1K GPIO_INPUT_PULL(PAD_PULL_DOWN_1K) 219 220 #define GPI(int_type, int_sel, term, int_msk, glitch_cfg, wake_msk, gpe_val) { \ 221 .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GFCFG(glitch_cfg) \ 222 | PAD_PULL(term) | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI, \ 223 .pad_conf1 = int_type << 0 | PAD_CONFIG1_DEFAULT0, \ 224 .wake_mask = wake_msk, \ 225 .int_mask = int_msk, \ 226 .gpe = gpe_val } 227 228 #define GPO_FUNC(term, tx_state) {\ 229 .pad_conf0 = PAD_GPIO_ENABLE | PAD_GPIOFG_GPO | PAD_PULL(term) \ 230 | tx_state << 1, \ 231 .pad_conf1 = PAD_CONFIG1_DEFAULT0 } 232 233 #define NATIVE_FUNC(mode, term, inv_rx_tx) {\ 234 .pad_conf0 = PAD_GPIO_DISABLE | PAD_GPIOFG_HI_Z \ 235 | PAD_MODE_SELECTION(mode) | PAD_PULL(term),\ 236 .pad_conf1 = PAD_CONFIG1_DEFAULT0 | inv_rx_tx << 4 } 237 238 #define NATIVE_FUNC_TX_RX(tx_rx_enable, mode, term, inv_rx_tx) {\ 239 .pad_conf0 = PAD_FUNC_CTRL(tx_rx_enable) | PAD_GPIO_DISABLE \ 240 | PAD_GPIOFG_GPIO | PAD_MODE_SELECTION(mode) \ 241 | PAD_PULL(term),\ 242 .pad_conf1 = PAD_CONFIG1_DEFAULT0 | inv_rx_tx << 4 } 243 244 #define NATIVE_FUNC_CSEN(mode, term, inv_rx_tx) {\ 245 .pad_conf0 = PAD_GPIO_DISABLE | PAD_GPIOFG_HI_Z \ 246 | PAD_MODE_SELECTION(mode) | PAD_PULL(term),\ 247 .pad_conf1 = PAD_CONFIG1_CSEN | inv_rx_tx << 4 } 248 249 #define NATIVE_INT(mode, int_sel) {\ 250 .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \ 251 | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\ 252 .pad_conf1 = PAD_CONFIG1_DEFAULT0 } 253 254 #define NATIVE_INT_PU20K(mode, int_sel) {\ 255 .pad_conf0 = PAD_PULL_UP_20K | PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \ 256 | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\ 257 .pad_conf1 = PAD_CONFIG1_DEFAULT0 } 258 259 #define SPEAKER \ 260 { .pad_conf0 = PAD_CONFIG0_DEFAULT0, \ 261 .pad_conf1 = PAD_CONFIG1_DEFAULT0 } 262 263 #define SPARE_PIN\ 264 { .pad_conf0 = 0x00110300,\ 265 .pad_conf1 = PAD_CONFIG1_DEFAULT0 } 266 267 /* SCI , SMI, Wake */ 268 #define GPIO_SCI(int_sel) \ 269 { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\ 270 | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \ 271 | PAD_INT_SEL(int_sel), \ 272 .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \ 273 .gpe = SCI, \ 274 .int_mask = 1 } 275 276 #define GPIO_WAKE(int_sel) \ 277 { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\ 278 | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \ 279 | PAD_INT_SEL(int_sel), \ 280 .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \ 281 .int_mask = 1,\ 282 .wake_mask = 1 } 283 284 #define GPIO_SMI(int_sel) \ 285 { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\ 286 | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \ 287 | PAD_INT_SEL(int_sel), \ 288 .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \ 289 .int_mask = 1,\ 290 .gpe = SMI } 291 292 #define GPIO_SKIP { .skip_config = 1 } 293 294 /* Common GPIO settings */ 295 #define NATIVE_DEFAULT(mode) NATIVE_FUNC(mode, 0, 0) /* no pull */ 296 #define NATIVE_PU20K(mode) NATIVE_FUNC(mode, 9, 0) /* PH 20k */ 297 #define NATIVE_PU5K(mode) NATIVE_FUNC(mode, 10, 0) /* PH 5k */ 298 #define NATIVE_PU5K_INVTX(mode) NATIVE_FUNC(mode, 10, inv_tx_enable) /* PH 5k */ 299 #define NATIVE_PU1K(mode) NATIVE_FUNC(mode, 12, 0) /* PH 1k */ 300 #define NATIVE_PU1K_CSEN_INVTX(mode) \ 301 NATIVE_FUNC_CSEN(mode, 12, inv_tx_enable) /* PH 1k */ 302 #define NATIVE_PU1K_INVTX(mode) NATIVE_FUNC(mode, 12, inv_tx_enable) /* PH 1k */ 303 #define NATIVE_PD20K(mode) NATIVE_FUNC(mode, 1, 0) /* PD 20k */ 304 #define NATIVE_PD5K(mode) NATIVE_FUNC(mode, 2, 0) /* PD 5k */ 305 #define NATIVE_PD1K(mode) NATIVE_FUNC(mode, 4, 0) /* PD 1k */ 306 #define NATIVE_PD1K_CSEN_INVTX(mode) NATIVE_FUNC_CSEN(mode, 4, inv_tx_enable) 307 /* no pull */ 308 #define NATIVE_TX_RX_EN NATIVE_FUNC_TX_RX(3, 1, 0, inv_tx_enable) 309 #define NATIVE_TX_RX_M1 NATIVE_FUNC_TX_RX(0, 1, 0, 0) /* no pull */ 310 #define NATIVE_TX_RX_M3 NATIVE_FUNC_TX_RX(0, 3, 0, 0) /* no pull */ 311 #define NATIVE_PU1K_M1 NATIVE_PU1K(1) /* PU1k M1 */ 312 313 /* Default native functions */ 314 #define Native_M0 NATIVE_DEFAULT(0) 315 #define Native_M1 NATIVE_DEFAULT(1) 316 #define Native_M2 NATIVE_DEFAULT(2) 317 #define Native_M3 NATIVE_DEFAULT(3) 318 #define Native_M4 NATIVE_DEFAULT(4) 319 #define Native_M5 NATIVE_DEFAULT(5) 320 #define Native_M6 NATIVE_DEFAULT(6) 321 #define Native_M7 NATIVE_DEFAULT(7) 322 #define Native_M8 NATIVE_DEFAULT(8) 323 324 #define GPIO_OUT_LOW GPO_FUNC(0, 0) /* gpo low */ 325 #define GPIO_OUT_HIGH GPO_FUNC(0, 1) /* gpo high */ 326 #define GPIO_NC GPIO_INPUT_PU_20K /* not connect */ 327 328 /* End marker */ 329 #define GPIO_LIST_END 0xffffffff 330 331 #define GPIO_END \ 332 { .pad_conf0 = GPIO_LIST_END } 333 334 /* Functions / defines for changing GPIOs in romstage */ 335 #define UART_RXD_PAD 82 336 #define UART_TXD_PAD 83 337 #define PCU_SMB_CLK_PAD 88 338 #define PCU_SMB_DATA_PAD 90 339 #define SOC_DDI1_VDDEN_PAD 16 340 #define UART1_RXD_PAD 9 341 #define UART1_TXD_PAD 13 342 #define DDI2_DDC_SCL 48 343 #define DDI2_DDC_SDA 53 344 345 struct soc_gpio_map { 346 u32 pad_conf0; 347 u32 pad_conf1; 348 u32 gpe; 349 u32 int_mask:1; 350 u32 wake_mask:1; 351 u32 is_gpio:1; 352 u32 skip_config:1; 353 } __packed; 354 355 struct soc_gpio_config { 356 const struct soc_gpio_map *north; 357 const struct soc_gpio_map *southeast; 358 const struct soc_gpio_map *southwest; 359 const struct soc_gpio_map *east; 360 }; 361 362 /* Description of a GPIO 'community' */ 363 struct gpio_bank { 364 const int gpio_count; 365 const u8 *gpio_to_pad; 366 const unsigned long pad_base; 367 const u8 has_gpe_en:1; 368 const u8 has_wake_en:1; 369 }; 370 371 typedef enum { 372 P_NONE = 0, /* Pull None */ 373 P_20K_L = 1, /* Pull Down 20K */ 374 P_5K_L = 2, /* Pull Down 5K */ 375 P_1K_L = 4, /* Pull Down 1K */ 376 P_20K_H = 9, /* Pull Up 20K */ 377 P_5K_H = 10, /* Pull Up 5K */ 378 P_1K_H = 12 /* Pull Up 1K */ 379 } pull_type_t; 380 381 typedef enum { 382 M0 = 0, 383 M1, 384 M2, 385 M3, 386 M4, 387 M5, 388 M6, 389 M7, 390 M8, 391 M9, 392 M10, 393 M11, 394 M12, 395 M13, 396 } mode_list_t; 397 398 typedef enum { 399 L0 = 0, 400 L1 = 1, 401 L2 = 2, 402 L3 = 3, 403 L4 = 4, 404 L5 = 5, 405 L6 = 6, 406 L7 = 7, 407 L8 = 8, 408 L9 = 9, 409 L10 = 10, 410 L11 = 11, 411 L12 = 12, 412 L13 = 13, 413 L14 = 14, 414 L15 = 15, 415 } int_select_t; 416 417 typedef enum { 418 INT_DIS = 0, 419 trig_edge_low = PAD_TRIG_EDGE_LOW, 420 trig_edge_high = PAD_TRIG_EDGE_HIGH, 421 trig_edge_both = PAD_TRIG_EDGE_BOTH, 422 trig_level_high = PAD_TRIG_EDGE_LEVEL | (0 << 4), 423 trig_level_low = PAD_TRIG_EDGE_LEVEL | (4 << 4), 424 } int_type_t; 425 426 typedef enum { 427 glitch_disable = 0, 428 en_edge_detect, 429 en_rx_data, 430 en_edge_rx_data, 431 } glitch_cfg; 432 433 typedef enum { 434 maskable = 0, 435 non_maskable, 436 } mask_t; 437 438 typedef enum { 439 GPE = 0, 440 SMI, 441 SCI, 442 } gpe_config_t; 443 444 /* 445 * InvertRxTx 7:4 446 * 0 - No Inversion 447 * 1 - Inversion 448 * [0] RX Enable 449 * [1] TX Enable 450 * [2] RX Data 451 * [3] TX Data 452 */ 453 typedef enum { 454 no_inversion = 0, 455 inv_rx_enable = 0x1, 456 inv_tx_enable = 0x2, 457 inv_rx_tx_enable = 0x3, 458 inv_rx_data = 0x4, 459 inv_tx_data = 0x8, 460 } invert_rx_tx_t; 461 462 #define PAD_VAL_HIGH (1 << 0) 463 464 void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap); 465 struct soc_gpio_config *mainboard_get_gpios(void); 466 467 typedef int gpio_t; 468 469 uint16_t gpio_family_number(uint8_t community, uint8_t pad); 470 uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad); 471 472 void lpc_init(void); 473 void lpc_set_low_power(void); 474 475 #endif /* _SOC_GPIO_H_ */ 476